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ALSA: hda - Fix mutex deadlock in HDMI codec driver
[linux-2.6-block.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
079d88cc
WF		 2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
079d88cc
WF		 17 */
18
84eb01be
TI		 19#include <linux/init.h>
20#include <linux/delay.h>
ade49db3 21#include <linux/pci.h>
84eb01be 22#include <linux/slab.h>
65a77217 23#include <linux/module.h>
aaa23f86 24#include <linux/pm_runtime.h>
84eb01be 25#include <sound/core.h>
07acecc1 26#include <sound/jack.h>
433968da 27#include <sound/asoundef.h>
d45e6889 28#include <sound/tlv.h>
25adc137
DH		 29#include <sound/hdaudio.h>
30#include <sound/hda_i915.h>
67b90cb8 31#include <sound/hda_chmap.h>
be57bfff 32#include <sound/hda_codec.h>
84eb01be 33#include "hda_local.h"
1835a0f9 34#include "hda_jack.h"
84eb01be 35
0ebaa24c
TI		 36static bool static_hdmi_pcm;
37module_param(static_hdmi_pcm, bool, 0644);
38MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
39
7639a06c
TI		 40#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
41#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
42#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 43#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
91815d8a 44#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
b9091b1c
SP		 45#define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
46 ((codec)->core.vendor_id == 0x80862800))
2b4584d0 47#define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
b0d8bc50 48#define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f)
432ac1a2 49#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
91815d8a 50 || is_skylake(codec) || is_broxton(codec) \
b0d8bc50
JK		 51 || is_kabylake(codec) || is_geminilake(codec) \
52 || is_cannonlake(codec) || is_icelake(codec))
7639a06c
TI		 53#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
54#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 55#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 56
384a48d7
SW		 57struct hdmi_spec_per_cvt {
58 hda_nid_t cvt_nid;
59 int assigned;
60 unsigned int channels_min;
61 unsigned int channels_max;
62 u32 rates;
63 u64 formats;
64 unsigned int maxbps;
65};
079d88cc 66
4eea3091
TI		 67/* max. connections to a widget */
68#define HDA_MAX_CONNECTIONS 32
69
384a48d7
SW		 70struct hdmi_spec_per_pin {
71 hda_nid_t pin_nid;
9152085d 72 int dev_id;
a76056f2
LY		 73 /* pin idx, different device entries on the same pin use the same idx */
74 int pin_nid_idx;
384a48d7
SW		 75 int num_mux_nids;
76 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 77 int mux_idx;
1df5a06a 78 hda_nid_t cvt_nid;
744626da
WF		 79
80 struct hda_codec *codec;
384a48d7 81 struct hdmi_eld sink_eld;
a4e9a38b 82 struct mutex lock;
744626da 83 struct delayed_work work;
2bea241a 84 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
a76056f2 85 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
c6e8453e 86 int repoll_count;
b054087d
TI		 87 bool setup; /* the stream has been set up by prepare callback */
88 int channels; /* current number of channels */
1a6003b5 89 bool non_pcm;
d45e6889
TI		 90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 92#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 93 struct snd_info_entry *proc_entry;
94#endif
384a48d7 95};
079d88cc 96
307229d2
AH		 97/* operations used by generic code that can be overridden by patches */
98struct hdmi_ops {
99 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
100 unsigned char *buf, int *eld_size);
101
307229d2
AH		 102 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
103 int ca, int active_channels, int conn_type);
104
105 /* enable/disable HBR (HD passthrough) */
106 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
107
108 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
109 hda_nid_t pin_nid, u32 stream_tag, int format);
110
4846a67e
TI		 111 void (*pin_cvt_fixup)(struct hda_codec *codec,
112 struct hdmi_spec_per_pin *per_pin,
113 hda_nid_t cvt_nid);
307229d2
AH		 114};
115
2bea241a
LY		 116struct hdmi_pcm {
117 struct hda_pcm *pcm;
118 struct snd_jack *jack;
fb087eaa 119 struct snd_kcontrol *eld_ctl;
2bea241a
LY		 120};
121
384a48d7 122struct hdmi_spec {
ade49db3 123 struct hda_codec *codec;
384a48d7 124 int num_cvts;
bce0d2a8
TI		 125 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
126 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 127
9152085d
LY		 128 /*
129 * num_pins is the number of virtual pins
130 * for example, there are 3 pins, and each pin
131 * has 4 device entries, then the num_pins is 12
132 */
384a48d7 133 int num_pins;
9152085d
LY		 134 /*
135 * num_nids is the number of real pins
136 * In the above example, num_nids is 3
137 */
138 int num_nids;
139 /*
140 * dev_num is the number of device entries
141 * on each pin.
142 * In the above example, dev_num is 4
143 */
144 int dev_num;
bce0d2a8 145 struct snd_array pins; /* struct hdmi_spec_per_pin */
2bea241a 146 struct hdmi_pcm pcm_rec[16];
42b29870 147 struct mutex pcm_lock;
302d5a80 148 struct mutex bind_lock; /* for audio component binding */
a76056f2
LY		 149 /* pcm_bitmap means which pcms have been assigned to pins*/
150 unsigned long pcm_bitmap;
2bf3c85a 151 int pcm_used; /* counter of pcm_rec[] */
ac98379a
LY		 152 /* bitmap shows whether the pcm is opened in user space
153 * bit 0 means the first playback PCM (PCM3);
154 * bit 1 means the second playback PCM, and so on.
155 */
156 unsigned long pcm_in_use;
079d88cc 157
4bd038f9 158 struct hdmi_eld temp_eld;
307229d2 159 struct hdmi_ops ops;
75fae117
SW		 160
161 bool dyn_pin_out;
6590faab 162 bool dyn_pcm_assign;
079d88cc 163 /*
5a613584 164 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 165 */
166 struct hda_multi_out multiout;
d0b1252d 167 struct hda_pcm_stream pcm_playback;
25adc137 168
ade49db3
TI		 169 bool use_jack_detect; /* jack detection enabled */
170 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
171 bool acomp_registered; /* audio component registered in this driver */
ae891abe 172 struct drm_audio_component_audio_ops drm_audio_ops;
ade49db3 173 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
67b90cb8
SP		 174
175 struct hdac_chmap chmap;
a87a4d23 176 hda_nid_t vendor_nid;
b0d8bc50
JK		 177 const int *port_map;
178 int port_num;
079d88cc
WF		 179};
180
a57942bf 181#ifdef CONFIG_SND_HDA_COMPONENT
691be973
TI		 182static inline bool codec_has_acomp(struct hda_codec *codec)
183{
184 struct hdmi_spec *spec = codec->spec;
185 return spec->use_acomp_notifier;
186}
f4e3040b
TI		 187#else
188#define codec_has_acomp(codec) false
189#endif
079d88cc
WF		 190
191struct hdmi_audio_infoframe {
192 u8 type; /* 0x84 */
193 u8 ver; /* 0x01 */
194 u8 len; /* 0x0a */
195
53d7d69d
WF		 196 u8 checksum;
197
079d88cc
WF		 198 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
199 u8 SS01_SF24;
200 u8 CXT04;
201 u8 CA;
202 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 203};
204
205struct dp_audio_infoframe {
206 u8 type; /* 0x84 */
207 u8 len; /* 0x1b */
208 u8 ver; /* 0x11 << 2 */
209
210 u8 CC02_CT47; /* match with HDMI infoframe from this on */
211 u8 SS01_SF24;
212 u8 CXT04;
213 u8 CA;
214 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 215};
216
2b203dbb
TI		 217union audio_infoframe {
218 struct hdmi_audio_infoframe hdmi;
219 struct dp_audio_infoframe dp;
220 u8 bytes[0];
221};
222
079d88cc
WF		 223/*
224 * HDMI routines
225 */
226
bce0d2a8
TI		 227#define get_pin(spec, idx) \
228 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
229#define get_cvt(spec, idx) \
230 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
2bea241a
LY		 231/* obtain hdmi_pcm object assigned to idx */
232#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
233/* obtain hda_pcm object assigned to idx */
234#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
bce0d2a8 235
9152085d
LY		 236static int pin_id_to_pin_index(struct hda_codec *codec,
237 hda_nid_t pin_nid, int dev_id)
079d88cc 238{
4e76a883 239 struct hdmi_spec *spec = codec->spec;
384a48d7 240 int pin_idx;
9152085d 241 struct hdmi_spec_per_pin *per_pin;
079d88cc 242
9152085d
LY		 243 /*
244 * (dev_id == -1) means it is NON-MST pin
245 * return the first virtual pin on this port
246 */
247 if (dev_id == -1)
248 dev_id = 0;
249
250 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
251 per_pin = get_pin(spec, pin_idx);
252 if ((per_pin->pin_nid == pin_nid) &&
253 (per_pin->dev_id == dev_id))
384a48d7 254 return pin_idx;
9152085d 255 }
079d88cc 256
4e76a883 257 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 258 return -EINVAL;
259}
260
2bf3c85a
LY		 261static int hinfo_to_pcm_index(struct hda_codec *codec,
262 struct hda_pcm_stream *hinfo)
263{
264 struct hdmi_spec *spec = codec->spec;
265 int pcm_idx;
266
267 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
268 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
269 return pcm_idx;
270
271 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
272 return -EINVAL;
273}
274
4e76a883 275static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 276 struct hda_pcm_stream *hinfo)
277{
4e76a883 278 struct hdmi_spec *spec = codec->spec;
6590faab 279 struct hdmi_spec_per_pin *per_pin;
384a48d7
SW		 280 int pin_idx;
281
6590faab
LY		 282 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
283 per_pin = get_pin(spec, pin_idx);
2bea241a
LY		 284 if (per_pin->pcm &&
285 per_pin->pcm->pcm->stream == hinfo)
384a48d7 286 return pin_idx;
6590faab 287 }
384a48d7 288
6590faab 289 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 290 return -EINVAL;
291}
292
022f344b
LY		 293static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
294 int pcm_idx)
295{
296 int i;
297 struct hdmi_spec_per_pin *per_pin;
298
299 for (i = 0; i < spec->num_pins; i++) {
300 per_pin = get_pin(spec, i);
301 if (per_pin->pcm_idx == pcm_idx)
302 return per_pin;
303 }
304 return NULL;
305}
306
4e76a883 307static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 308{
4e76a883 309 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 310 int cvt_idx;
311
312 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 313 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 314 return cvt_idx;
315
4e76a883 316 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 317 return -EINVAL;
318}
319
14bc52b8
PLB		 320static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
321 struct snd_ctl_elem_info *uinfo)
322{
323 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 324 struct hdmi_spec *spec = codec->spec;
a4e9a38b 325 struct hdmi_spec_per_pin *per_pin;
68e03de9 326 struct hdmi_eld *eld;
fb087eaa 327 int pcm_idx;
14bc52b8 328
14bc52b8
PLB		 329 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
330
fb087eaa
LY		 331 pcm_idx = kcontrol->private_value;
332 mutex_lock(&spec->pcm_lock);
333 per_pin = pcm_idx_to_pin(spec, pcm_idx);
334 if (!per_pin) {
335 /* no pin is bound to the pcm */
336 uinfo->count = 0;
f69548ff 337 goto unlock;
fb087eaa 338 }
a4e9a38b 339 eld = &per_pin->sink_eld;
68e03de9 340 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
14bc52b8 341
f69548ff
TI		 342 unlock:
343 mutex_unlock(&spec->pcm_lock);
14bc52b8
PLB		 344 return 0;
345}
346
347static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
348 struct snd_ctl_elem_value *ucontrol)
349{
350 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 351 struct hdmi_spec *spec = codec->spec;
a4e9a38b 352 struct hdmi_spec_per_pin *per_pin;
68e03de9 353 struct hdmi_eld *eld;
fb087eaa 354 int pcm_idx;
f69548ff 355 int err = 0;
14bc52b8 356
fb087eaa
LY		 357 pcm_idx = kcontrol->private_value;
358 mutex_lock(&spec->pcm_lock);
359 per_pin = pcm_idx_to_pin(spec, pcm_idx);
360 if (!per_pin) {
361 /* no pin is bound to the pcm */
362 memset(ucontrol->value.bytes.data, 0,
363 ARRAY_SIZE(ucontrol->value.bytes.data));
f69548ff 364 goto unlock;
fb087eaa 365 }
68e03de9 366
f69548ff 367 eld = &per_pin->sink_eld;
360a8245
DH		 368 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
369 eld->eld_size > ELD_MAX_SIZE) {
68e03de9 370 snd_BUG();
f69548ff
TI		 371 err = -EINVAL;
372 goto unlock;
68e03de9
DH		 373 }
374
375 memset(ucontrol->value.bytes.data, 0,
376 ARRAY_SIZE(ucontrol->value.bytes.data));
377 if (eld->eld_valid)
378 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
379 eld->eld_size);
14bc52b8 380
f69548ff
TI		 381 unlock:
382 mutex_unlock(&spec->pcm_lock);
383 return err;
14bc52b8
PLB		 384}
385
f3b827e0 386static const struct snd_kcontrol_new eld_bytes_ctl = {
14bc52b8
PLB		 387 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
388 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
389 .name = "ELD",
390 .info = hdmi_eld_ctl_info,
391 .get = hdmi_eld_ctl_get,
392};
393
fb087eaa 394static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
14bc52b8
PLB		 395 int device)
396{
397 struct snd_kcontrol *kctl;
398 struct hdmi_spec *spec = codec->spec;
399 int err;
400
401 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
402 if (!kctl)
403 return -ENOMEM;
fb087eaa 404 kctl->private_value = pcm_idx;
14bc52b8
PLB		 405 kctl->id.device = device;
406
fb087eaa
LY		 407 /* no pin nid is associated with the kctl now
408 * tbd: associate pin nid to eld ctl later
409 */
410 err = snd_hda_ctl_add(codec, 0, kctl);
14bc52b8
PLB		 411 if (err < 0)
412 return err;
413
fb087eaa 414 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
14bc52b8
PLB		 415 return 0;
416}
417
079d88cc
WF		 418#ifdef BE_PARANOID
419static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
420 int *packet_index, int *byte_index)
421{
422 int val;
423
424 val = snd_hda_codec_read(codec, pin_nid, 0,
425 AC_VERB_GET_HDMI_DIP_INDEX, 0);
426
427 *packet_index = val >> 5;
428 *byte_index = val & 0x1f;
429}
430#endif
431
432static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
433 int packet_index, int byte_index)
434{
435 int val;
436
437 val = (packet_index << 5) | (byte_index & 0x1f);
438
439 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
440}
441
442static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
443 unsigned char val)
444{
445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
446}
447
384a48d7 448static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 449{
75fae117
SW		 450 struct hdmi_spec *spec = codec->spec;
451 int pin_out;
452
079d88cc
WF		 453 /* Unmute */
454 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
455 snd_hda_codec_write(codec, pin_nid, 0,
456 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 457
458 if (spec->dyn_pin_out)
459 /* Disable pin out until stream is active */
460 pin_out = 0;
461 else
462 /* Enable pin out: some machines with GM965 gets broken output
463 * when the pin is disabled or changed while using with HDMI
464 */
465 pin_out = PIN_OUT;
466
079d88cc 467 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 468 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 469}
470
a4e9a38b
TI		 471/*
472 * ELD proc files
473 */
474
cd6a6503 475#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 476static void print_eld_info(struct snd_info_entry *entry,
477 struct snd_info_buffer *buffer)
478{
479 struct hdmi_spec_per_pin *per_pin = entry->private_data;
480
481 mutex_lock(&per_pin->lock);
482 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
483 mutex_unlock(&per_pin->lock);
484}
485
486static void write_eld_info(struct snd_info_entry *entry,
487 struct snd_info_buffer *buffer)
488{
489 struct hdmi_spec_per_pin *per_pin = entry->private_data;
490
491 mutex_lock(&per_pin->lock);
492 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
493 mutex_unlock(&per_pin->lock);
494}
495
496static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
497{
498 char name[32];
499 struct hda_codec *codec = per_pin->codec;
500 struct snd_info_entry *entry;
501 int err;
502
503 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 504 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 505 if (err < 0)
506 return err;
507
508 snd_info_set_text_ops(entry, per_pin, print_eld_info);
509 entry->c.text.write = write_eld_info;
6a73cf46 510 entry->mode |= 0200;
a4e9a38b
TI		 511 per_pin->proc_entry = entry;
512
513 return 0;
514}
515
516static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
517{
1947a114 518 if (!per_pin->codec->bus->shutdown) {
c560a679 519 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 520 per_pin->proc_entry = NULL;
521 }
522}
523#else
b55447a7
TI		 524static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
525 int index)
a4e9a38b
TI		 526{
527 return 0;
528}
b55447a7 529static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 530{
531}
532#endif
079d88cc 533
079d88cc
WF		 534/*
535 * Audio InfoFrame routines
536 */
537
538/*
539 * Enable Audio InfoFrame Transmission
540 */
541static void hdmi_start_infoframe_trans(struct hda_codec *codec,
542 hda_nid_t pin_nid)
543{
544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
546 AC_DIPXMIT_BEST);
547}
548
549/*
550 * Disable Audio InfoFrame Transmission
551 */
552static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
553 hda_nid_t pin_nid)
554{
555 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
556 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
557 AC_DIPXMIT_DISABLE);
558}
559
560static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
561{
562#ifdef CONFIG_SND_DEBUG_VERBOSE
563 int i;
564 int size;
565
566 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 567 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 568
569 for (i = 0; i < 8; i++) {
570 size = snd_hda_codec_read(codec, pin_nid, 0,
571 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 572 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 573 }
574#endif
575}
576
577static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
578{
579#ifdef BE_PARANOID
580 int i, j;
581 int size;
582 int pi, bi;
583 for (i = 0; i < 8; i++) {
584 size = snd_hda_codec_read(codec, pin_nid, 0,
585 AC_VERB_GET_HDMI_DIP_SIZE, i);
586 if (size == 0)
587 continue;
588
589 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
590 for (j = 1; j < 1000; j++) {
591 hdmi_write_dip_byte(codec, pin_nid, 0x0);
592 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
593 if (pi != i)
4e76a883 594 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 595 bi, pi, i);
596 if (bi == 0) /* byte index wrapped around */
597 break;
598 }
4e76a883 599 codec_dbg(codec,
079d88cc
WF		 600 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
601 i, size, j);
602 }
603#endif
604}
605
53d7d69d 606static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 607{
53d7d69d 608 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 609 u8 sum = 0;
610 int i;
611
53d7d69d 612 hdmi_ai->checksum = 0;
079d88cc 613
53d7d69d 614 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 615 sum += bytes[i];
616
53d7d69d 617 hdmi_ai->checksum = -sum;
079d88cc
WF		 618}
619
620static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
621 hda_nid_t pin_nid,
53d7d69d 622 u8 *dip, int size)
079d88cc 623{
079d88cc
WF		 624 int i;
625
626 hdmi_debug_dip_size(codec, pin_nid);
627 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
628
079d88cc 629 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 630 for (i = 0; i < size; i++)
631 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 632}
633
634static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 635 u8 *dip, int size)
079d88cc 636{
079d88cc
WF		 637 u8 val;
638 int i;
639
640 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
641 != AC_DIPXMIT_BEST)
642 return false;
643
644 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 645 for (i = 0; i < size; i++) {
079d88cc
WF		 646 val = snd_hda_codec_read(codec, pin_nid, 0,
647 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 648 if (val != dip[i])
079d88cc
WF		 649 return false;
650 }
651
652 return true;
653}
654
307229d2
AH		 655static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
656 hda_nid_t pin_nid,
657 int ca, int active_channels,
658 int conn_type)
659{
660 union audio_infoframe ai;
661
caaf5ef9 662 memset(&ai, 0, sizeof(ai));
307229d2
AH		 663 if (conn_type == 0) { /* HDMI */
664 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
665
666 hdmi_ai->type = 0x84;
667 hdmi_ai->ver = 0x01;
668 hdmi_ai->len = 0x0a;
669 hdmi_ai->CC02_CT47 = active_channels - 1;
670 hdmi_ai->CA = ca;
671 hdmi_checksum_audio_infoframe(hdmi_ai);
672 } else if (conn_type == 1) { /* DisplayPort */
673 struct dp_audio_infoframe *dp_ai = &ai.dp;
674
675 dp_ai->type = 0x84;
676 dp_ai->len = 0x1b;
677 dp_ai->ver = 0x11 << 2;
678 dp_ai->CC02_CT47 = active_channels - 1;
679 dp_ai->CA = ca;
680 } else {
4e76a883 681 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 682 pin_nid);
683 return;
684 }
685
686 /*
687 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
688 * sizeof(*dp_ai) to avoid partial match/update problems when
689 * the user switches between HDMI/DP monitors.
690 */
691 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
692 sizeof(ai))) {
4e76a883
TI		 693 codec_dbg(codec,
694 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 695 pin_nid,
696 active_channels, ca);
697 hdmi_stop_infoframe_trans(codec, pin_nid);
698 hdmi_fill_audio_infoframe(codec, pin_nid,
699 ai.bytes, sizeof(ai));
700 hdmi_start_infoframe_trans(codec, pin_nid);
701 }
702}
703
b054087d
TI		 704static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
705 struct hdmi_spec_per_pin *per_pin,
706 bool non_pcm)
079d88cc 707{
307229d2 708 struct hdmi_spec *spec = codec->spec;
739ffee9 709 struct hdac_chmap *chmap = &spec->chmap;
384a48d7 710 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 711 int channels = per_pin->channels;
1df5a06a 712 int active_channels;
384a48d7 713 struct hdmi_eld *eld;
828cb4ed 714 int ca;
079d88cc 715
b054087d
TI		 716 if (!channels)
717 return;
718
44bb6d0c
TI		 719 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
720 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
58f7d28d
ML		 721 snd_hda_codec_write(codec, pin_nid, 0,
722 AC_VERB_SET_AMP_GAIN_MUTE,
723 AMP_OUT_UNMUTE);
724
bce0d2a8 725 eld = &per_pin->sink_eld;
079d88cc 726
bb63f726 727 ca = snd_hdac_channel_allocation(&codec->core,
828cb4ed
SP		 728 eld->info.spk_alloc, channels,
729 per_pin->chmap_set, non_pcm, per_pin->chmap);
384a48d7 730
bb63f726 731 active_channels = snd_hdac_get_active_channels(ca);
1df5a06a 732
739ffee9
SP		 733 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
734 active_channels);
1df5a06a 735
39edac70
AH		 736 /*
737 * always configure channel mapping, it may have been changed by the
738 * user in the meantime
739 */
bb63f726 740 snd_hdac_setup_channel_mapping(&spec->chmap,
828cb4ed
SP		 741 pin_nid, non_pcm, ca, channels,
742 per_pin->chmap, per_pin->chmap_set);
39edac70 743
307229d2
AH		 744 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
745 eld->info.conn_type);
433968da 746
1a6003b5 747 per_pin->non_pcm = non_pcm;
079d88cc
WF		 748}
749
079d88cc
WF		 750/*
751 * Unsolicited events
752 */
753
efe47108 754static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 755
9152085d
LY		 756static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
757 int dev_id)
079d88cc
WF		 758{
759 struct hdmi_spec *spec = codec->spec;
9152085d 760 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
1a4f69d5 761
20ce9029
DH		 762 if (pin_idx < 0)
763 return;
aaa23f86 764 mutex_lock(&spec->pcm_lock);
20ce9029
DH		 765 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
766 snd_hda_jack_report_sync(codec);
aaa23f86 767 mutex_unlock(&spec->pcm_lock);
20ce9029
DH		 768}
769
1a4f69d5
TI		 770static void jack_callback(struct hda_codec *codec,
771 struct hda_jack_callback *jack)
772{
ade49db3
TI		 773 /* stop polling when notification is enabled */
774 if (codec_has_acomp(codec))
775 return;
776
9152085d
LY		 777 /* hda_jack don't support DP MST */
778 check_presence_and_report(codec, jack->nid, 0);
1a4f69d5
TI		 779}
780
20ce9029
DH		 781static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
782{
3a93897e 783 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 784 struct hda_jack_tbl *jack;
2e59e5ab 785 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e 786
9152085d
LY		 787 /*
788 * assume DP MST uses dyn_pcm_assign and acomp and
789 * never comes here
790 * if DP MST supports unsol event, below code need
791 * consider dev_entry
792 */
3a93897e
TI		 793 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
794 if (!jack)
795 return;
3a93897e 796 jack->jack_dirty = 1;
079d88cc 797
4e76a883 798 codec_dbg(codec,
2e59e5ab 799 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 800 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 801 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 802
9152085d
LY		 803 /* hda_jack don't support DP MST */
804 check_presence_and_report(codec, jack->nid, 0);
079d88cc
WF		 805}
806
807static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
808{
809 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
810 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
811 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
812 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
813
4e76a883 814 codec_info(codec,
e9ea8e8f 815 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 816 codec->addr,
079d88cc
WF		 817 tag,
818 subtag,
819 cp_state,
820 cp_ready);
821
822 /* TODO */
823 if (cp_state)
824 ;
825 if (cp_ready)
826 ;
827}
828
829
830static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
831{
079d88cc
WF		 832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
834
ade49db3
TI		 835 if (codec_has_acomp(codec))
836 return;
837
3a93897e 838 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 839 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 840 return;
841 }
842
843 if (subtag == 0)
844 hdmi_intrinsic_event(codec, res);
845 else
846 hdmi_non_intrinsic_event(codec, res);
847}
848
58f7d28d 849static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 850 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 851{
58f7d28d 852 int pwr;
83f26ad2 853
53b434f0
WX		 854 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
855 * thus pins could only choose converter 0 for use. Make sure the
856 * converters are in correct power state */
fd678cac 857 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 858 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
859
fd678cac 860 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 861 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
862 AC_PWRST_D0);
863 msleep(40);
864 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
865 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 866 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 867 }
83f26ad2
DH		 868}
869
079d88cc
WF		 870/*
871 * Callbacks
872 */
873
92f10b3f
TI		 874/* HBR should be Non-PCM, 8 channels */
875#define is_hbr_format(format) \
876 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
877
307229d2
AH		 878static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
879 bool hbr)
079d88cc 880{
307229d2 881 int pinctl, new_pinctl;
83f26ad2 882
384a48d7
SW		 883 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
884 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 885 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
886
13122e6e
AH		 887 if (pinctl < 0)
888 return hbr ? -EINVAL : 0;
889
ea87d1c4 890 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 891 if (hbr)
ea87d1c4
AH		 892 new_pinctl |= AC_PINCTL_EPT_HBR;
893 else
894 new_pinctl |= AC_PINCTL_EPT_NATIVE;
895
4e76a883
TI		 896 codec_dbg(codec,
897 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 898 pin_nid,
ea87d1c4
AH		 899 pinctl == new_pinctl ? "" : "new-",
900 new_pinctl);
901
902 if (pinctl != new_pinctl)
384a48d7 903 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 904 AC_VERB_SET_PIN_WIDGET_CONTROL,
905 new_pinctl);
307229d2
AH		 906 } else if (hbr)
907 return -EINVAL;
ea87d1c4 908
307229d2
AH		 909 return 0;
910}
911
912static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
913 hda_nid_t pin_nid, u32 stream_tag, int format)
914{
915 struct hdmi_spec *spec = codec->spec;
5a5d718f 916 unsigned int param;
307229d2
AH		 917 int err;
918
307229d2
AH		 919 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
920
921 if (err) {
4e76a883 922 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 923 return err;
ea87d1c4 924 }
079d88cc 925
5a5d718f
SP		 926 if (is_haswell_plus(codec)) {
927
928 /*
929 * on recent platforms IEC Coding Type is required for HBR
930 * support, read current Digital Converter settings and set
931 * ICT bitfield if needed.
932 */
933 param = snd_hda_codec_read(codec, cvt_nid, 0,
934 AC_VERB_GET_DIGI_CONVERT_1, 0);
935
936 param = (param >> 16) & ~(AC_DIG3_ICT);
937
938 /* on recent platforms ICT mode is required for HBR support */
939 if (is_hbr_format(format))
940 param |= 0x1;
941
942 snd_hda_codec_write(codec, cvt_nid, 0,
943 AC_VERB_SET_DIGI_CONVERT_3, param);
944 }
945
384a48d7 946 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 947 return 0;
079d88cc
WF		 948}
949
42b29870
LY		 950/* Try to find an available converter
951 * If pin_idx is less then zero, just try to find an available converter.
952 * Otherwise, try to find an available converter and get the cvt mux index
953 * of the pin.
954 */
7ef166b8 955static int hdmi_choose_cvt(struct hda_codec *codec,
4846a67e 956 int pin_idx, int *cvt_id)
bbbe3390
TI		 957{
958 struct hdmi_spec *spec = codec->spec;
384a48d7 959 struct hdmi_spec_per_pin *per_pin;
384a48d7 960 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 961 int cvt_idx, mux_idx = 0;
bbbe3390 962
42b29870
LY		 963 /* pin_idx < 0 means no pin will be bound to the converter */
964 if (pin_idx < 0)
965 per_pin = NULL;
966 else
967 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 968
969 /* Dynamically assign converter to stream */
970 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 971 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 972
384a48d7
SW		 973 /* Must not already be assigned */
974 if (per_cvt->assigned)
975 continue;
42b29870
LY		 976 if (per_pin == NULL)
977 break;
384a48d7
SW		 978 /* Must be in pin's mux's list of converters */
979 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
980 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
981 break;
982 /* Not in mux list */
983 if (mux_idx == per_pin->num_mux_nids)
984 continue;
985 break;
986 }
7ef166b8 987
384a48d7
SW		 988 /* No free converters */
989 if (cvt_idx == spec->num_cvts)
42b29870 990 return -EBUSY;
384a48d7 991
42b29870
LY		 992 if (per_pin != NULL)
993 per_pin->mux_idx = mux_idx;
2df6742f 994
7ef166b8
WX		 995 if (cvt_id)
996 *cvt_id = cvt_idx;
7ef166b8
WX		 997
998 return 0;
999}
1000
2df6742f
ML		 1001/* Assure the pin select the right convetor */
1002static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1003 struct hdmi_spec_per_pin *per_pin)
1004{
1005 hda_nid_t pin_nid = per_pin->pin_nid;
1006 int mux_idx, curr;
1007
1008 mux_idx = per_pin->mux_idx;
1009 curr = snd_hda_codec_read(codec, pin_nid, 0,
1010 AC_VERB_GET_CONNECT_SEL, 0);
1011 if (curr != mux_idx)
1012 snd_hda_codec_write_cache(codec, pin_nid, 0,
1013 AC_VERB_SET_CONNECT_SEL,
1014 mux_idx);
1015}
1016
42b29870
LY		 1017/* get the mux index for the converter of the pins
1018 * converter's mux index is the same for all pins on Intel platform
1019 */
1020static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1021 hda_nid_t cvt_nid)
1022{
1023 int i;
1024
1025 for (i = 0; i < spec->num_cvts; i++)
1026 if (spec->cvt_nids[i] == cvt_nid)
1027 return i;
1028 return -EINVAL;
1029}
1030
300016b9
ML		 1031/* Intel HDMI workaround to fix audio routing issue:
1032 * For some Intel display codecs, pins share the same connection list.
1033 * So a conveter can be selected by multiple pins and playback on any of these
1034 * pins will generate sound on the external display, because audio flows from
1035 * the same converter to the display pipeline. Also muting one pin may make
1036 * other pins have no sound output.
1037 * So this function assures that an assigned converter for a pin is not selected
1038 * by any other pins.
1039 */
1040static void intel_not_share_assigned_cvt(struct hda_codec *codec,
9152085d
LY		 1041 hda_nid_t pin_nid,
1042 int dev_id, int mux_idx)
7ef166b8
WX		 1043{
1044 struct hdmi_spec *spec = codec->spec;
7639a06c 1045 hda_nid_t nid;
f82d7d16
ML		 1046 int cvt_idx, curr;
1047 struct hdmi_spec_per_cvt *per_cvt;
9152085d
LY		 1048 struct hdmi_spec_per_pin *per_pin;
1049 int pin_idx;
1050
1051 /* configure the pins connections */
1052 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1053 int dev_id_saved;
1054 int dev_num;
7ef166b8 1055
9152085d
LY		 1056 per_pin = get_pin(spec, pin_idx);
1057 /*
1058 * pin not connected to monitor
1059 * no need to operate on it
1060 */
1061 if (!per_pin->pcm)
1062 continue;
f82d7d16 1063
9152085d
LY		 1064 if ((per_pin->pin_nid == pin_nid) &&
1065 (per_pin->dev_id == dev_id))
f82d7d16 1066 continue;
7ef166b8 1067
9152085d
LY		 1068 /*
1069 * if per_pin->dev_id >= dev_num,
1070 * snd_hda_get_dev_select() will fail,
1071 * and the following operation is unpredictable.
1072 * So skip this situation.
1073 */
1074 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1075 if (per_pin->dev_id >= dev_num)
7ef166b8
WX		 1076 continue;
1077
9152085d
LY		 1078 nid = per_pin->pin_nid;
1079
1080 /*
1081 * Calling this function should not impact
1082 * on the device entry selection
1083 * So let's save the dev id for each pin,
1084 * and restore it when return
1085 */
1086 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1087 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
f82d7d16 1088 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1089 AC_VERB_GET_CONNECT_SEL, 0);
9152085d
LY		 1090 if (curr != mux_idx) {
1091 snd_hda_set_dev_select(codec, nid, dev_id_saved);
f82d7d16 1092 continue;
9152085d
LY		 1093 }
1094
7ef166b8 1095
f82d7d16
ML		 1096 /* choose an unassigned converter. The conveters in the
1097 * connection list are in the same order as in the codec.
1098 */
1099 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1100 per_cvt = get_cvt(spec, cvt_idx);
1101 if (!per_cvt->assigned) {
4e76a883
TI		 1102 codec_dbg(codec,
1103 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1104 cvt_idx, nid);
1105 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1106 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1107 cvt_idx);
1108 break;
1109 }
7ef166b8 1110 }
9152085d 1111 snd_hda_set_dev_select(codec, nid, dev_id_saved);
7ef166b8
WX		 1112 }
1113}
1114
42b29870
LY		 1115/* A wrapper of intel_not_share_asigned_cvt() */
1116static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
9152085d 1117 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
42b29870
LY		 1118{
1119 int mux_idx;
1120 struct hdmi_spec *spec = codec->spec;
1121
42b29870
LY		 1122 /* On Intel platform, the mapping of converter nid to
1123 * mux index of the pins are always the same.
1124 * The pin nid may be 0, this means all pins will not
1125 * share the converter.
1126 */
1127 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1128 if (mux_idx >= 0)
9152085d 1129 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
42b29870
LY		 1130}
1131
4846a67e
TI		 1132/* skeleton caller of pin_cvt_fixup ops */
1133static void pin_cvt_fixup(struct hda_codec *codec,
1134 struct hdmi_spec_per_pin *per_pin,
1135 hda_nid_t cvt_nid)
1136{
1137 struct hdmi_spec *spec = codec->spec;
1138
1139 if (spec->ops.pin_cvt_fixup)
1140 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1141}
1142
42b29870
LY		 1143/* called in hdmi_pcm_open when no pin is assigned to the PCM
1144 * in dyn_pcm_assign mode.
1145 */
1146static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1147 struct hda_codec *codec,
1148 struct snd_pcm_substream *substream)
1149{
1150 struct hdmi_spec *spec = codec->spec;
1151 struct snd_pcm_runtime *runtime = substream->runtime;
ac98379a 1152 int cvt_idx, pcm_idx;
42b29870
LY		 1153 struct hdmi_spec_per_cvt *per_cvt = NULL;
1154 int err;
1155
ac98379a
LY		 1156 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1157 if (pcm_idx < 0)
1158 return -EINVAL;
1159
4846a67e 1160 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
42b29870
LY		 1161 if (err)
1162 return err;
1163
1164 per_cvt = get_cvt(spec, cvt_idx);
1165 per_cvt->assigned = 1;
1166 hinfo->nid = per_cvt->cvt_nid;
1167
4846a67e 1168 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
42b29870 1169
ac98379a 1170 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870
LY		 1171 /* todo: setup spdif ctls assign */
1172
1173 /* Initially set the converter's capabilities */
1174 hinfo->channels_min = per_cvt->channels_min;
1175 hinfo->channels_max = per_cvt->channels_max;
1176 hinfo->rates = per_cvt->rates;
1177 hinfo->formats = per_cvt->formats;
1178 hinfo->maxbps = per_cvt->maxbps;
1179
1180 /* Store the updated parameters */
1181 runtime->hw.channels_min = hinfo->channels_min;
1182 runtime->hw.channels_max = hinfo->channels_max;
1183 runtime->hw.formats = hinfo->formats;
1184 runtime->hw.rates = hinfo->rates;
1185
1186 snd_pcm_hw_constraint_step(substream->runtime, 0,
1187 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1188 return 0;
1189}
1190
7ef166b8
WX		 1191/*
1192 * HDA PCM callbacks
1193 */
1194static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1195 struct hda_codec *codec,
1196 struct snd_pcm_substream *substream)
1197{
1198 struct hdmi_spec *spec = codec->spec;
1199 struct snd_pcm_runtime *runtime = substream->runtime;
4846a67e 1200 int pin_idx, cvt_idx, pcm_idx;
7ef166b8
WX		 1201 struct hdmi_spec_per_pin *per_pin;
1202 struct hdmi_eld *eld;
1203 struct hdmi_spec_per_cvt *per_cvt = NULL;
1204 int err;
1205
1206 /* Validate hinfo */
2bf3c85a
LY		 1207 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1208 if (pcm_idx < 0)
7ef166b8 1209 return -EINVAL;
2bf3c85a 1210
42b29870 1211 mutex_lock(&spec->pcm_lock);
4e76a883 1212 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1213 if (!spec->dyn_pcm_assign) {
1214 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1215 err = -EINVAL;
1216 goto unlock;
42b29870
LY		 1217 }
1218 } else {
1219 /* no pin is assigned to the PCM
1220 * PA need pcm open successfully when probe
1221 */
1222 if (pin_idx < 0) {
1223 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
f69548ff 1224 goto unlock;
42b29870
LY		 1225 }
1226 }
7ef166b8 1227
4846a67e 1228 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
f69548ff
TI		 1229 if (err < 0)
1230 goto unlock;
7ef166b8
WX		 1231
1232 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1233 /* Claim converter */
1234 per_cvt->assigned = 1;
42b29870 1235
ac98379a 1236 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870 1237 per_pin = get_pin(spec, pin_idx);
1df5a06a 1238 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1239 hinfo->nid = per_cvt->cvt_nid;
1240
9152085d 1241 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
bddee96b 1242 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7 1243 AC_VERB_SET_CONNECT_SEL,
4846a67e 1244 per_pin->mux_idx);
7ef166b8
WX		 1245
1246 /* configure unused pins to choose other converters */
4846a67e 1247 pin_cvt_fixup(codec, per_pin, 0);
7ef166b8 1248
2bf3c85a 1249 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
bbbe3390 1250
2def8172 1251 /* Initially set the converter's capabilities */
384a48d7
SW		 1252 hinfo->channels_min = per_cvt->channels_min;
1253 hinfo->channels_max = per_cvt->channels_max;
1254 hinfo->rates = per_cvt->rates;
1255 hinfo->formats = per_cvt->formats;
1256 hinfo->maxbps = per_cvt->maxbps;
2def8172 1257
42b29870 1258 eld = &per_pin->sink_eld;
384a48d7 1259 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1260 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1261 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1262 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1263 !hinfo->rates || !hinfo->formats) {
1264 per_cvt->assigned = 0;
1265 hinfo->nid = 0;
2bf3c85a 1266 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
f69548ff
TI		 1267 err = -ENODEV;
1268 goto unlock;
2ad779b7 1269 }
bbbe3390 1270 }
2def8172
SW		 1271
1272 /* Store the updated parameters */
639cef0e
TI		 1273 runtime->hw.channels_min = hinfo->channels_min;
1274 runtime->hw.channels_max = hinfo->channels_max;
1275 runtime->hw.formats = hinfo->formats;
1276 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1277
1278 snd_pcm_hw_constraint_step(substream->runtime, 0,
1279 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
f69548ff
TI		 1280 unlock:
1281 mutex_unlock(&spec->pcm_lock);
1282 return err;
bbbe3390
TI		 1283}
1284
079d88cc
WF		 1285/*
1286 * HDA/HDMI auto parsing
1287 */
384a48d7 1288static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1289{
1290 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1291 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1292 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1293
1294 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1295 codec_warn(codec,
1296 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1297 pin_nid, get_wcaps(codec, pin_nid));
1298 return -EINVAL;
1299 }
1300
9152085d 1301 /* all the device entries on the same pin have the same conn list */
384a48d7
SW		 1302 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1303 per_pin->mux_nids,
1304 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1305
1306 return 0;
1307}
1308
a76056f2
LY		 1309static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1310 struct hdmi_spec_per_pin *per_pin)
1311{
1312 int i;
1313
1314 /* try the prefer PCM */
1315 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1316 return per_pin->pin_nid_idx;
1317
1318 /* have a second try; check the "reserved area" over num_pins */
9152085d 1319 for (i = spec->num_nids; i < spec->pcm_used; i++) {
a76056f2
LY		 1320 if (!test_bit(i, &spec->pcm_bitmap))
1321 return i;
1322 }
1323
1324 /* the last try; check the empty slots in pins */
9152085d 1325 for (i = 0; i < spec->num_nids; i++) {
a76056f2
LY		 1326 if (!test_bit(i, &spec->pcm_bitmap))
1327 return i;
1328 }
1329 return -EBUSY;
1330}
1331
1332static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1333 struct hdmi_spec_per_pin *per_pin)
1334{
1335 int idx;
1336
1337 /* pcm already be attached to the pin */
1338 if (per_pin->pcm)
1339 return;
1340 idx = hdmi_find_pcm_slot(spec, per_pin);
d10a80de 1341 if (idx == -EBUSY)
a76056f2
LY		 1342 return;
1343 per_pin->pcm_idx = idx;
2bea241a 1344 per_pin->pcm = get_hdmi_pcm(spec, idx);
a76056f2
LY		 1345 set_bit(idx, &spec->pcm_bitmap);
1346}
1347
1348static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1349 struct hdmi_spec_per_pin *per_pin)
1350{
1351 int idx;
1352
1353 /* pcm already be detached from the pin */
1354 if (!per_pin->pcm)
1355 return;
1356 idx = per_pin->pcm_idx;
1357 per_pin->pcm_idx = -1;
1358 per_pin->pcm = NULL;
1359 if (idx >= 0 && idx < spec->pcm_used)
1360 clear_bit(idx, &spec->pcm_bitmap);
1361}
1362
ac98379a
LY		 1363static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1364 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1365{
1366 int mux_idx;
1367
1368 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1369 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1370 break;
1371 return mux_idx;
1372}
1373
1374static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1375
1376static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1377 struct hdmi_spec_per_pin *per_pin)
1378{
1379 struct hda_codec *codec = per_pin->codec;
1380 struct hda_pcm *pcm;
1381 struct hda_pcm_stream *hinfo;
1382 struct snd_pcm_substream *substream;
1383 int mux_idx;
1384 bool non_pcm;
1385
1386 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
2bea241a 1387 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
ac98379a
LY		 1388 else
1389 return;
8a7d6003
TI		 1390 if (!pcm->pcm)
1391 return;
ac98379a
LY		 1392 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1393 return;
1394
1395 /* hdmi audio only uses playback and one substream */
1396 hinfo = pcm->stream;
1397 substream = pcm->pcm->streams[0].substream;
1398
1399 per_pin->cvt_nid = hinfo->nid;
1400
1401 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
9152085d
LY		 1402 if (mux_idx < per_pin->num_mux_nids) {
1403 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1404 per_pin->dev_id);
ac98379a
LY		 1405 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1406 AC_VERB_SET_CONNECT_SEL,
1407 mux_idx);
9152085d 1408 }
ac98379a
LY		 1409 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1410
1411 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1412 if (substream->runtime)
1413 per_pin->channels = substream->runtime->channels;
1414 per_pin->setup = true;
1415 per_pin->mux_idx = mux_idx;
1416
1417 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1418}
1419
1420static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1421 struct hdmi_spec_per_pin *per_pin)
1422{
1423 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1424 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1425
1426 per_pin->chmap_set = false;
1427 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1428
1429 per_pin->setup = false;
1430 per_pin->channels = 0;
1431}
1432
e90247f9
TI		 1433/* update per_pin ELD from the given new ELD;
1434 * setup info frame and notification accordingly
1435 */
551626ec 1436static bool update_eld(struct hda_codec *codec,
e90247f9
TI		 1437 struct hdmi_spec_per_pin *per_pin,
1438 struct hdmi_eld *eld)
1439{
1440 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
a76056f2 1441 struct hdmi_spec *spec = codec->spec;
e90247f9
TI		 1442 bool old_eld_valid = pin_eld->eld_valid;
1443 bool eld_changed;
f953e72c 1444 int pcm_idx;
e90247f9 1445
fb087eaa
LY		 1446 /* for monitor disconnection, save pcm_idx firstly */
1447 pcm_idx = per_pin->pcm_idx;
a76056f2 1448 if (spec->dyn_pcm_assign) {
ac98379a 1449 if (eld->eld_valid) {
a76056f2 1450 hdmi_attach_hda_pcm(spec, per_pin);
ac98379a
LY		 1451 hdmi_pcm_setup_pin(spec, per_pin);
1452 } else {
1453 hdmi_pcm_reset_pin(spec, per_pin);
a76056f2 1454 hdmi_detach_hda_pcm(spec, per_pin);
ac98379a 1455 }
a76056f2 1456 }
fb087eaa
LY		 1457 /* if pcm_idx == -1, it means this is in monitor connection event
1458 * we can get the correct pcm_idx now.
1459 */
1460 if (pcm_idx == -1)
1461 pcm_idx = per_pin->pcm_idx;
a76056f2 1462
e90247f9
TI		 1463 if (eld->eld_valid)
1464 snd_hdmi_show_eld(codec, &eld->info);
1465
1466 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
551626ec
TI		 1467 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1468 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
e90247f9
TI		 1469 if (pin_eld->eld_size != eld->eld_size ||
1470 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1471 eld->eld_size) != 0)
1472 eld_changed = true;
1473
551626ec
TI		 1474 if (eld_changed) {
1475 pin_eld->monitor_present = eld->monitor_present;
1476 pin_eld->eld_valid = eld->eld_valid;
1477 pin_eld->eld_size = eld->eld_size;
1478 if (eld->eld_valid)
1479 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1480 eld->eld_size);
1481 pin_eld->info = eld->info;
1482 }
e90247f9
TI		 1483
1484 /*
1485 * Re-setup pin and infoframe. This is needed e.g. when
1486 * - sink is first plugged-in
1487 * - transcoder can change during stream playback on Haswell
1488 * and this can make HW reset converter selection on a pin.
1489 */
1490 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
4846a67e 1491 pin_cvt_fixup(codec, per_pin, 0);
e90247f9
TI		 1492 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1493 }
1494
fb087eaa 1495 if (eld_changed && pcm_idx >= 0)
e90247f9
TI		 1496 snd_ctl_notify(codec->card,
1497 SNDRV_CTL_EVENT_MASK_VALUE |
1498 SNDRV_CTL_EVENT_MASK_INFO,
fb087eaa 1499 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
551626ec 1500 return eld_changed;
e90247f9
TI		 1501}
1502
788d441a
TI		 1503/* update ELD and jack state via HD-audio verbs */
1504static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1505 int repoll)
079d88cc 1506{
464837a7 1507 struct hda_jack_tbl *jack;
744626da 1508 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1509 struct hdmi_spec *spec = codec->spec;
1510 struct hdmi_eld *eld = &spec->temp_eld;
744626da 1511 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1512 /*
1513 * Always execute a GetPinSense verb here, even when called from
1514 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1515 * response's PD bit is not the real PD value, but indicates that
1516 * the real PD value changed. An older version of the HD-audio
1517 * specification worked this way. Hence, we just ignore the data in
1518 * the unsolicited response to avoid custom WARs.
1519 */
da4a7a39 1520 int present;
efe47108 1521 bool ret;
9a5e5234 1522 bool do_repoll = false;
079d88cc 1523
da4a7a39
DH		 1524 present = snd_hda_pin_sense(codec, pin_nid);
1525
a4e9a38b 1526 mutex_lock(&per_pin->lock);
c44da62b
TI		 1527 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1528 if (eld->monitor_present)
4bd038f9
DH		 1529 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1530 else
1531 eld->eld_valid = false;
079d88cc 1532
4e76a883 1533 codec_dbg(codec,
384a48d7 1534 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
c44da62b 1535 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
5d44f927 1536
4bd038f9 1537 if (eld->eld_valid) {
307229d2 1538 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1539 &eld->eld_size) < 0)
4bd038f9 1540 eld->eld_valid = false;
1613d6b4 1541 else {
79514d47 1542 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1543 eld->eld_size) < 0)
4bd038f9 1544 eld->eld_valid = false;
1613d6b4 1545 }
9a5e5234
TI		 1546 if (!eld->eld_valid && repoll)
1547 do_repoll = true;
744626da 1548 }
4bd038f9 1549
9a5e5234 1550 if (do_repoll)
e90247f9
TI		 1551 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1552 else
1553 update_eld(codec, per_pin, eld);
92c69e79 1554
c44da62b 1555 ret = !repoll || !eld->monitor_present || eld->eld_valid;
464837a7
DH		 1556
1557 jack = snd_hda_jack_tbl_get(codec, pin_nid);
7f641e26 1558 if (jack) {
464837a7 1559 jack->block_report = !ret;
7f641e26
HW		 1560 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ?
1561 AC_PINSENSE_PRESENCE : 0;
1562 }
a4e9a38b 1563 mutex_unlock(&per_pin->lock);
efe47108 1564 return ret;
079d88cc
WF		 1565}
1566
3184270e
LY		 1567static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1568 struct hdmi_spec_per_pin *per_pin)
1569{
1570 struct hdmi_spec *spec = codec->spec;
1571 struct snd_jack *jack = NULL;
1572 struct hda_jack_tbl *jack_tbl;
1573
1574 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1575 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1576 * NULL even after snd_hda_jack_tbl_clear() is called to
1577 * free snd_jack. This may cause access invalid memory
1578 * when calling snd_jack_report
1579 */
1580 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1581 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1582 else if (!spec->dyn_pcm_assign) {
9152085d
LY		 1583 /*
1584 * jack tbl doesn't support DP MST
1585 * DP MST will use dyn_pcm_assign,
1586 * so DP MST will never come here
1587 */
3184270e
LY		 1588 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1589 if (jack_tbl)
1590 jack = jack_tbl->jack;
1591 }
1592 return jack;
1593}
1594
788d441a
TI		 1595/* update ELD and jack state via audio component */
1596static void sync_eld_via_acomp(struct hda_codec *codec,
1597 struct hdmi_spec_per_pin *per_pin)
1598{
788d441a
TI		 1599 struct hdmi_spec *spec = codec->spec;
1600 struct hdmi_eld *eld = &spec->temp_eld;
25e4abb3 1601 struct snd_jack *jack = NULL;
551626ec 1602 bool changed;
788d441a
TI		 1603 int size;
1604
e2dc7d7d 1605 mutex_lock(&per_pin->lock);
c64c1437 1606 eld->monitor_present = false;
9152085d
LY		 1607 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1608 per_pin->dev_id, &eld->monitor_present,
1609 eld->eld_buffer, ELD_MAX_SIZE);
e2dc7d7d
TI		 1610 if (size > 0) {
1611 size = min(size, ELD_MAX_SIZE);
1612 if (snd_hdmi_parse_eld(codec, &eld->info,
1613 eld->eld_buffer, size) < 0)
1614 size = -EINVAL;
1615 }
788d441a 1616
e2dc7d7d
TI		 1617 if (size > 0) {
1618 eld->eld_valid = true;
1619 eld->eld_size = size;
1620 } else {
1621 eld->eld_valid = false;
1622 eld->eld_size = 0;
788d441a 1623 }
e2dc7d7d 1624
25e4abb3
LY		 1625 /* pcm_idx >=0 before update_eld() means it is in monitor
1626 * disconnected event. Jack must be fetched before update_eld()
1627 */
3184270e 1628 jack = pin_idx_to_jack(codec, per_pin);
551626ec 1629 changed = update_eld(codec, per_pin, eld);
3184270e
LY		 1630 if (jack == NULL)
1631 jack = pin_idx_to_jack(codec, per_pin);
551626ec
TI		 1632 if (changed && jack)
1633 snd_jack_report(jack,
1634 (eld->monitor_present && eld->eld_valid) ?
855b5e01 1635 SND_JACK_AVOUT : 0);
e2dc7d7d 1636 mutex_unlock(&per_pin->lock);
788d441a
TI		 1637}
1638
1639static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1640{
1641 struct hda_codec *codec = per_pin->codec;
a76056f2 1642 int ret;
788d441a 1643
222bde03 1644 /* no temporary power up/down needed for component notifier */
aaa23f86
CW		 1645 if (!codec_has_acomp(codec)) {
1646 ret = snd_hda_power_up_pm(codec);
1647 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1648 snd_hda_power_down_pm(codec);
1649 return false;
1650 }
ade49db3
TI		 1651 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1652 snd_hda_power_down_pm(codec);
1653 } else {
788d441a 1654 sync_eld_via_acomp(codec, per_pin);
a76056f2 1655 ret = false; /* don't call snd_hda_jack_report_sync() */
788d441a 1656 }
a76056f2
LY		 1657
1658 return ret;
788d441a
TI		 1659}
1660
744626da
WF		 1661static void hdmi_repoll_eld(struct work_struct *work)
1662{
1663 struct hdmi_spec_per_pin *per_pin =
1664 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
aaa23f86
CW		 1665 struct hda_codec *codec = per_pin->codec;
1666 struct hdmi_spec *spec = codec->spec;
8c2e6728
HW		 1667 struct hda_jack_tbl *jack;
1668
1669 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1670 if (jack)
1671 jack->jack_dirty = 1;
744626da 1672
c6e8453e
WF		 1673 if (per_pin->repoll_count++ > 6)
1674 per_pin->repoll_count = 0;
1675
aaa23f86 1676 mutex_lock(&spec->pcm_lock);
efe47108
TI		 1677 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1678 snd_hda_jack_report_sync(per_pin->codec);
aaa23f86 1679 mutex_unlock(&spec->pcm_lock);
744626da
WF		 1680}
1681
c88d4e84
TI		 1682static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1683 hda_nid_t nid);
1684
079d88cc
WF		 1685static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1686{
1687 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1688 unsigned int caps, config;
1689 int pin_idx;
1690 struct hdmi_spec_per_pin *per_pin;
07acecc1 1691 int err;
9152085d 1692 int dev_num, i;
079d88cc 1693
efc2f8de 1694 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1695 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1696 return 0;
1697
9152085d
LY		 1698 /*
1699 * For DP MST audio, Configuration Default is the same for
1700 * all device entries on the same pin
1701 */
efc2f8de 1702 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1703 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1704 return 0;
1705
9152085d
LY		 1706 /*
1707 * To simplify the implementation, malloc all
1708 * the virtual pins in the initialization statically
1709 */
1710 if (is_haswell_plus(codec)) {
1711 /*
1712 * On Intel platforms, device entries number is
1713 * changed dynamically. If there is a DP MST
1714 * hub connected, the device entries number is 3.
1715 * Otherwise, it is 1.
1716 * Here we manually set dev_num to 3, so that
1717 * we can initialize all the device entries when
1718 * bootup statically.
1719 */
1720 dev_num = 3;
1721 spec->dev_num = 3;
1722 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1723 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1724 /*
1725 * spec->dev_num is the maxinum number of device entries
1726 * among all the pins
1727 */
1728 spec->dev_num = (spec->dev_num > dev_num) ?
1729 spec->dev_num : dev_num;
1730 } else {
1731 /*
1732 * If the platform doesn't support DP MST,
1733 * manually set dev_num to 1. This means
1734 * the pin has only one device entry.
1735 */
1736 dev_num = 1;
1737 spec->dev_num = 1;
2bea241a 1738 }
079d88cc 1739
9152085d
LY		 1740 for (i = 0; i < dev_num; i++) {
1741 pin_idx = spec->num_pins;
1742 per_pin = snd_array_new(&spec->pins);
079d88cc 1743
9152085d
LY		 1744 if (!per_pin)
1745 return -ENOMEM;
1746
1747 if (spec->dyn_pcm_assign) {
1748 per_pin->pcm = NULL;
1749 per_pin->pcm_idx = -1;
1750 } else {
1751 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1752 per_pin->pcm_idx = pin_idx;
1753 }
1754 per_pin->pin_nid = pin_nid;
1755 per_pin->pin_nid_idx = spec->num_nids;
1756 per_pin->dev_id = i;
1757 per_pin->non_pcm = false;
1758 snd_hda_set_dev_select(codec, pin_nid, i);
1759 if (is_haswell_plus(codec))
1760 intel_haswell_fixup_connect_list(codec, pin_nid);
1761 err = hdmi_read_pin_conn(codec, pin_idx);
1762 if (err < 0)
1763 return err;
1764 spec->num_pins++;
1765 }
1766 spec->num_nids++;
079d88cc 1767
384a48d7 1768 return 0;
079d88cc
WF		 1769}
1770
384a48d7 1771static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1772{
1773 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1774 struct hdmi_spec_per_cvt *per_cvt;
1775 unsigned int chans;
1776 int err;
079d88cc 1777
384a48d7
SW		 1778 chans = get_wcaps(codec, cvt_nid);
1779 chans = get_wcaps_channels(chans);
1780
bce0d2a8
TI		 1781 per_cvt = snd_array_new(&spec->cvts);
1782 if (!per_cvt)
1783 return -ENOMEM;
384a48d7
SW		 1784
1785 per_cvt->cvt_nid = cvt_nid;
1786 per_cvt->channels_min = 2;
d45e6889 1787 if (chans <= 16) {
384a48d7 1788 per_cvt->channels_max = chans;
67b90cb8
SP		 1789 if (chans > spec->chmap.channels_max)
1790 spec->chmap.channels_max = chans;
d45e6889 1791 }
384a48d7
SW		 1792
1793 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1794 &per_cvt->rates,
1795 &per_cvt->formats,
1796 &per_cvt->maxbps);
1797 if (err < 0)
1798 return err;
1799
bce0d2a8
TI		 1800 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1801 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1802 spec->num_cvts++;
079d88cc
WF		 1803
1804 return 0;
1805}
1806
1807static int hdmi_parse_codec(struct hda_codec *codec)
1808{
1809 hda_nid_t nid;
1810 int i, nodes;
1811
7639a06c 1812 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 1813 if (!nid || nodes < 0) {
4e76a883 1814 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1815 return -EINVAL;
1816 }
1817
1818 for (i = 0; i < nodes; i++, nid++) {
1819 unsigned int caps;
1820 unsigned int type;
1821
efc2f8de 1822 caps = get_wcaps(codec, nid);
079d88cc
WF		 1823 type = get_wcaps_type(caps);
1824
1825 if (!(caps & AC_WCAP_DIGITAL))
1826 continue;
1827
1828 switch (type) {
1829 case AC_WID_AUD_OUT:
384a48d7 1830 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1831 break;
1832 case AC_WID_PIN:
3eaead57 1833 hdmi_add_pin(codec, nid);
079d88cc
WF		 1834 break;
1835 }
1836 }
1837
079d88cc
WF		 1838 return 0;
1839}
1840
84eb01be
TI		 1841/*
1842 */
1a6003b5
TI		 1843static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1844{
1845 struct hda_spdif_out *spdif;
1846 bool non_pcm;
1847
1848 mutex_lock(&codec->spdif_mutex);
1849 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
960a581e
LY		 1850 /* Add sanity check to pass klockwork check.
1851 * This should never happen.
1852 */
1853 if (WARN_ON(spdif == NULL))
1854 return true;
1a6003b5
TI		 1855 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1856 mutex_unlock(&codec->spdif_mutex);
1857 return non_pcm;
1858}
1859
84eb01be
TI		 1860/*
1861 * HDMI callbacks
1862 */
1863
1864static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1865 struct hda_codec *codec,
1866 unsigned int stream_tag,
1867 unsigned int format,
1868 struct snd_pcm_substream *substream)
1869{
384a48d7
SW		 1870 hda_nid_t cvt_nid = hinfo->nid;
1871 struct hdmi_spec *spec = codec->spec;
42b29870
LY		 1872 int pin_idx;
1873 struct hdmi_spec_per_pin *per_pin;
1874 hda_nid_t pin_nid;
ddd621fb 1875 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 1876 bool non_pcm;
053b0559 1877 int pinctl, stripe;
f69548ff 1878 int err = 0;
1a6003b5 1879
42b29870
LY		 1880 mutex_lock(&spec->pcm_lock);
1881 pin_idx = hinfo_to_pin_index(codec, hinfo);
1882 if (spec->dyn_pcm_assign && pin_idx < 0) {
1883 /* when dyn_pcm_assign and pcm is not bound to a pin
1884 * skip pin setup and return 0 to make audio playback
1885 * be ongoing
1886 */
4846a67e 1887 pin_cvt_fixup(codec, NULL, cvt_nid);
42b29870
LY		 1888 snd_hda_codec_setup_stream(codec, cvt_nid,
1889 stream_tag, 0, format);
f69548ff 1890 goto unlock;
42b29870 1891 }
1a6003b5 1892
42b29870 1893 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1894 err = -EINVAL;
1895 goto unlock;
42b29870
LY		 1896 }
1897 per_pin = get_pin(spec, pin_idx);
1898 pin_nid = per_pin->pin_nid;
4846a67e
TI		 1899
1900 /* Verify pin:cvt selections to avoid silent audio after S3.
1901 * After S3, the audio driver restores pin:cvt selections
1902 * but this can happen before gfx is ready and such selection
1903 * is overlooked by HW. Thus multiple pins can share a same
1904 * default convertor and mute control will affect each other,
1905 * which can cause a resumed audio playback become silent
1906 * after S3.
1907 */
1908 pin_cvt_fixup(codec, per_pin, 0);
2df6742f 1909
ddd621fb
LY		 1910 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1911 /* Todo: add DP1.2 MST audio support later */
93a9ff15 1912 if (codec_has_acomp(codec))
9152085d 1913 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
f9318941 1914 runtime->rate);
ddd621fb 1915
1a6003b5 1916 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1917 mutex_lock(&per_pin->lock);
b054087d
TI		 1918 per_pin->channels = substream->runtime->channels;
1919 per_pin->setup = true;
384a48d7 1920
053b0559
SP		 1921 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
1922 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
1923 substream);
1924 snd_hda_codec_write(codec, cvt_nid, 0,
1925 AC_VERB_SET_STRIPE_CONTROL,
1926 stripe);
1927 }
1928
b054087d 1929 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1930 mutex_unlock(&per_pin->lock);
75fae117
SW		 1931 if (spec->dyn_pin_out) {
1932 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1933 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1934 snd_hda_codec_write(codec, pin_nid, 0,
1935 AC_VERB_SET_PIN_WIDGET_CONTROL,
1936 pinctl | PIN_OUT);
1937 }
1938
9152085d 1939 /* snd_hda_set_dev_select() has been called before */
42b29870
LY		 1940 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1941 stream_tag, format);
f69548ff 1942 unlock:
42b29870
LY		 1943 mutex_unlock(&spec->pcm_lock);
1944 return err;
84eb01be
TI		 1945}
1946
8dfaa573
TI		 1947static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1948 struct hda_codec *codec,
1949 struct snd_pcm_substream *substream)
1950{
1951 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1952 return 0;
1953}
1954
f2ad24fa
TI		 1955static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1956 struct hda_codec *codec,
1957 struct snd_pcm_substream *substream)
384a48d7
SW		 1958{
1959 struct hdmi_spec *spec = codec->spec;
2bf3c85a 1960 int cvt_idx, pin_idx, pcm_idx;
384a48d7
SW		 1961 struct hdmi_spec_per_cvt *per_cvt;
1962 struct hdmi_spec_per_pin *per_pin;
75fae117 1963 int pinctl;
f69548ff 1964 int err = 0;
384a48d7 1965
384a48d7 1966 if (hinfo->nid) {
2bf3c85a
LY		 1967 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1968 if (snd_BUG_ON(pcm_idx < 0))
1969 return -EINVAL;
4e76a883 1970 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1971 if (snd_BUG_ON(cvt_idx < 0))
1972 return -EINVAL;
bce0d2a8 1973 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1974
1975 snd_BUG_ON(!per_cvt->assigned);
1976 per_cvt->assigned = 0;
1977 hinfo->nid = 0;
1978
42b29870 1979 mutex_lock(&spec->pcm_lock);
b09887f8 1980 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
ac98379a 1981 clear_bit(pcm_idx, &spec->pcm_in_use);
4e76a883 1982 pin_idx = hinfo_to_pin_index(codec, hinfo);
f69548ff
TI		 1983 if (spec->dyn_pcm_assign && pin_idx < 0)
1984 goto unlock;
42b29870
LY		 1985
1986 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1987 err = -EINVAL;
1988 goto unlock;
42b29870 1989 }
bce0d2a8 1990 per_pin = get_pin(spec, pin_idx);
384a48d7 1991
75fae117
SW		 1992 if (spec->dyn_pin_out) {
1993 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1994 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1995 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1996 AC_VERB_SET_PIN_WIDGET_CONTROL,
1997 pinctl & ~PIN_OUT);
1998 }
1999
a4e9a38b 2000 mutex_lock(&per_pin->lock);
d45e6889
TI		 2001 per_pin->chmap_set = false;
2002 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 2003
2004 per_pin->setup = false;
2005 per_pin->channels = 0;
a4e9a38b 2006 mutex_unlock(&per_pin->lock);
f69548ff 2007 unlock:
42b29870 2008 mutex_unlock(&spec->pcm_lock);
384a48d7 2009 }
d45e6889 2010
f69548ff 2011 return err;
384a48d7
SW		 2012}
2013
2014static const struct hda_pcm_ops generic_ops = {
2015 .open = hdmi_pcm_open,
f2ad24fa 2016 .close = hdmi_pcm_close,
384a48d7 2017 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 2018 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 2019};
2020
44fde3b8
SP		 2021static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2022{
2023 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2024 struct hdmi_spec *spec = codec->spec;
2025 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2026
2027 if (!per_pin)
2028 return 0;
2029
2030 return per_pin->sink_eld.info.spk_alloc;
2031}
2032
9b3dc8aa
SP		 2033static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2034 unsigned char *chmap)
2035{
2036 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2037 struct hdmi_spec *spec = codec->spec;
2038 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2039
2040 /* chmap is already set to 0 in caller */
2041 if (!per_pin)
2042 return;
2043
2044 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2045}
2046
2047static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2048 unsigned char *chmap, int prepared)
2049{
2050 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2051 struct hdmi_spec *spec = codec->spec;
2052 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2053
ed0739b5
LY		 2054 if (!per_pin)
2055 return;
9b3dc8aa
SP		 2056 mutex_lock(&per_pin->lock);
2057 per_pin->chmap_set = true;
2058 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2059 if (prepared)
2060 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2061 mutex_unlock(&per_pin->lock);
2062}
2063
2064static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2065{
2066 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2067 struct hdmi_spec *spec = codec->spec;
2068 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2069
2070 return per_pin ? true:false;
2071}
2072
84eb01be
TI		 2073static int generic_hdmi_build_pcms(struct hda_codec *codec)
2074{
2075 struct hdmi_spec *spec = codec->spec;
9152085d 2076 int idx;
84eb01be 2077
9152085d
LY		 2078 /*
2079 * for non-mst mode, pcm number is the same as before
2080 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2081 * dev_num is the device entry number in a pin
2082 *
2083 */
2084 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
384a48d7 2085 struct hda_pcm *info;
84eb01be 2086 struct hda_pcm_stream *pstr;
bce0d2a8 2087
9152085d 2088 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
bce0d2a8
TI		 2089 if (!info)
2090 return -ENOMEM;
2bea241a 2091
9152085d 2092 spec->pcm_rec[idx].pcm = info;
2bf3c85a 2093 spec->pcm_used++;
84eb01be 2094 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2095 info->own_chmap = true;
384a48d7 2096
84eb01be 2097 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2098 pstr->substreams = 1;
2099 pstr->ops = generic_ops;
9152085d
LY		 2100 /* pcm number is less than 16 */
2101 if (spec->pcm_used >= 16)
2102 break;
384a48d7 2103 /* other pstr fields are set in open */
84eb01be
TI		 2104 }
2105
2106 return 0;
2107}
2108
25e4abb3 2109static void free_hdmi_jack_priv(struct snd_jack *jack)
788d441a 2110{
25e4abb3 2111 struct hdmi_pcm *pcm = jack->private_data;
788d441a 2112
25e4abb3 2113 pcm->jack = NULL;
788d441a
TI		 2114}
2115
25e4abb3
LY		 2116static int add_hdmi_jack_kctl(struct hda_codec *codec,
2117 struct hdmi_spec *spec,
2118 int pcm_idx,
788d441a
TI		 2119 const char *name)
2120{
2121 struct snd_jack *jack;
2122 int err;
2123
2124 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2125 true, false);
2126 if (err < 0)
2127 return err;
25e4abb3
LY		 2128
2129 spec->pcm_rec[pcm_idx].jack = jack;
2130 jack->private_data = &spec->pcm_rec[pcm_idx];
2131 jack->private_free = free_hdmi_jack_priv;
788d441a
TI		 2132 return 0;
2133}
2134
25e4abb3 2135static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
0b6c49b5 2136{
31ef2257 2137 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2138 struct hdmi_spec *spec = codec->spec;
25e4abb3
LY		 2139 struct hdmi_spec_per_pin *per_pin;
2140 struct hda_jack_tbl *jack;
2141 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
909cadc6 2142 bool phantom_jack;
25e4abb3 2143 int ret;
0b6c49b5 2144
31ef2257
TI		 2145 if (pcmdev > 0)
2146 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
25e4abb3
LY		 2147
2148 if (spec->dyn_pcm_assign)
2149 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2150
2151 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2152 /* if !dyn_pcm_assign, it must be non-MST mode.
2153 * This means pcms and pins are statically mapped.
2154 * And pcm_idx is pin_idx.
2155 */
2156 per_pin = get_pin(spec, pcm_idx);
909cadc6
TI		 2157 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2158 if (phantom_jack)
30efd8de
DH		 2159 strncat(hdmi_str, " Phantom",
2160 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
25e4abb3 2161 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
911761c2 2162 phantom_jack, 0, NULL);
25e4abb3
LY		 2163 if (ret < 0)
2164 return ret;
2165 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2166 if (jack == NULL)
2167 return 0;
2168 /* assign jack->jack to pcm_rec[].jack to
2169 * align with dyn_pcm_assign mode
2170 */
2171 spec->pcm_rec[pcm_idx].jack = jack->jack;
2172 return 0;
0b6c49b5
DH		 2173}
2174
84eb01be
TI		 2175static int generic_hdmi_build_controls(struct hda_codec *codec)
2176{
2177 struct hdmi_spec *spec = codec->spec;
1f7f51a6 2178 int dev, err;
25e4abb3 2179 int pin_idx, pcm_idx;
84eb01be 2180
25e4abb3 2181 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
8a7d6003
TI		 2182 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2183 /* no PCM: mark this for skipping permanently */
2184 set_bit(pcm_idx, &spec->pcm_bitmap);
2185 continue;
2186 }
2187
25e4abb3 2188 err = generic_hdmi_build_jack(codec, pcm_idx);
0b6c49b5
DH		 2189 if (err < 0)
2190 return err;
2191
b09887f8
LY		 2192 /* create the spdif for each pcm
2193 * pin will be bound when monitor is connected
2194 */
2195 if (spec->dyn_pcm_assign)
2196 err = snd_hda_create_dig_out_ctls(codec,
2197 0, spec->cvt_nids[0],
2198 HDA_PCM_TYPE_HDMI);
2199 else {
2200 struct hdmi_spec_per_pin *per_pin =
2201 get_pin(spec, pcm_idx);
2202 err = snd_hda_create_dig_out_ctls(codec,
dcda5806
TI		 2203 per_pin->pin_nid,
2204 per_pin->mux_nids[0],
2205 HDA_PCM_TYPE_HDMI);
b09887f8 2206 }
84eb01be
TI		 2207 if (err < 0)
2208 return err;
b09887f8 2209 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
14bc52b8 2210
1f7f51a6
WY		 2211 dev = get_pcm_rec(spec, pcm_idx)->device;
2212 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2213 /* add control for ELD Bytes */
2214 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2215 if (err < 0)
2216 return err;
2217 }
fb087eaa
LY		 2218 }
2219
2220 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2221 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
31ef2257 2222
82b1d73f 2223 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2224 }
2225
d45e6889 2226 /* add channel maps */
022f344b 2227 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
bbbc7e85 2228 struct hda_pcm *pcm;
2ca320e2 2229
022f344b 2230 pcm = get_pcm_rec(spec, pcm_idx);
bbbc7e85 2231 if (!pcm || !pcm->pcm)
2ca320e2 2232 break;
2f6e8a85 2233 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
d45e6889
TI		 2234 if (err < 0)
2235 return err;
d45e6889
TI		 2236 }
2237
84eb01be
TI		 2238 return 0;
2239}
2240
8b8d654b 2241static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2242{
2243 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2244 int pin_idx;
2245
2246 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2247 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2248
744626da 2249 per_pin->codec = codec;
a4e9a38b 2250 mutex_init(&per_pin->lock);
744626da 2251 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2252 eld_proc_new(per_pin, pin_idx);
84eb01be 2253 }
8b8d654b
TI		 2254 return 0;
2255}
2256
2257static int generic_hdmi_init(struct hda_codec *codec)
2258{
2259 struct hdmi_spec *spec = codec->spec;
2260 int pin_idx;
2261
302d5a80 2262 mutex_lock(&spec->bind_lock);
ade49db3 2263 spec->use_jack_detect = !codec->jackpoll_interval;
8b8d654b 2264 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2265 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b 2266 hda_nid_t pin_nid = per_pin->pin_nid;
9152085d 2267 int dev_id = per_pin->dev_id;
8b8d654b 2268
9152085d 2269 snd_hda_set_dev_select(codec, pin_nid, dev_id);
8b8d654b 2270 hdmi_init_pin(codec, pin_nid);
ade49db3
TI		 2271 if (codec_has_acomp(codec))
2272 continue;
2273 if (spec->use_jack_detect)
2274 snd_hda_jack_detect_enable(codec, pin_nid);
2275 else
788d441a 2276 snd_hda_jack_detect_enable_callback(codec, pin_nid,
ade49db3 2277 jack_callback);
8b8d654b 2278 }
302d5a80 2279 mutex_unlock(&spec->bind_lock);
84eb01be
TI		 2280 return 0;
2281}
2282
bce0d2a8
TI		 2283static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2284{
2285 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2286 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2287}
2288
2289static void hdmi_array_free(struct hdmi_spec *spec)
2290{
2291 snd_array_free(&spec->pins);
2292 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2293}
2294
a686632f
TI		 2295static void generic_spec_free(struct hda_codec *codec)
2296{
2297 struct hdmi_spec *spec = codec->spec;
2298
2299 if (spec) {
2300 hdmi_array_free(spec);
2301 kfree(spec);
2302 codec->spec = NULL;
2303 }
2304 codec->dp_mst = false;
2305}
2306
84eb01be
TI		 2307static void generic_hdmi_free(struct hda_codec *codec)
2308{
2309 struct hdmi_spec *spec = codec->spec;
25e4abb3 2310 int pin_idx, pcm_idx;
384a48d7 2311
ade49db3
TI		 2312 if (spec->acomp_registered) {
2313 snd_hdac_acomp_exit(&codec->bus->core);
2314 } else if (codec_has_acomp(codec)) {
a57942bf 2315 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
4914da2f
TI		 2316 codec->relaxed_resume = 0;
2317 }
25adc137 2318
384a48d7 2319 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2320 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2f35c630 2321 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2322 eld_proc_free(per_pin);
25e4abb3
LY		 2323 }
2324
2325 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2326 if (spec->pcm_rec[pcm_idx].jack == NULL)
2327 continue;
2328 if (spec->dyn_pcm_assign)
2329 snd_device_free(codec->card,
2330 spec->pcm_rec[pcm_idx].jack);
2331 else
2332 spec->pcm_rec[pcm_idx].jack = NULL;
384a48d7 2333 }
84eb01be 2334
a686632f 2335 generic_spec_free(codec);
84eb01be
TI		 2336}
2337
28cb72e5
WX		 2338#ifdef CONFIG_PM
2339static int generic_hdmi_resume(struct hda_codec *codec)
2340{
2341 struct hdmi_spec *spec = codec->spec;
2342 int pin_idx;
2343
a2833683 2344 codec->patch_ops.init(codec);
eeecd9d1 2345 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2346
2347 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2348 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2349 hdmi_present_sense(per_pin, 1);
2350 }
2351 return 0;
2352}
2353#endif
2354
fb79e1e0 2355static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2356 .init = generic_hdmi_init,
2357 .free = generic_hdmi_free,
2358 .build_pcms = generic_hdmi_build_pcms,
2359 .build_controls = generic_hdmi_build_controls,
2360 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2361#ifdef CONFIG_PM
2362 .resume = generic_hdmi_resume,
2363#endif
84eb01be
TI		 2364};
2365
307229d2
AH		 2366static const struct hdmi_ops generic_standard_hdmi_ops = {
2367 .pin_get_eld = snd_hdmi_get_eld,
307229d2
AH		 2368 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2369 .pin_hbr_setup = hdmi_pin_hbr_setup,
2370 .setup_stream = hdmi_setup_stream,
67b90cb8
SP		 2371};
2372
a686632f
TI		 2373/* allocate codec->spec and assign/initialize generic parser ops */
2374static int alloc_generic_hdmi(struct hda_codec *codec)
2375{
2376 struct hdmi_spec *spec;
2377
2378 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2379 if (!spec)
2380 return -ENOMEM;
2381
ade49db3 2382 spec->codec = codec;
a686632f 2383 spec->ops = generic_standard_hdmi_ops;
9152085d 2384 spec->dev_num = 1; /* initialize to 1 */
a686632f 2385 mutex_init(&spec->pcm_lock);
302d5a80 2386 mutex_init(&spec->bind_lock);
a686632f
TI		 2387 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2388
2389 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2390 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2391 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
44fde3b8 2392 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
a686632f
TI		 2393
2394 codec->spec = spec;
2395 hdmi_array_init(spec, 4);
2396
2397 codec->patch_ops = generic_hdmi_patch_ops;
2398
2399 return 0;
2400}
2401
2402/* generic HDMI parser */
2403static int patch_generic_hdmi(struct hda_codec *codec)
2404{
2405 int err;
2406
2407 err = alloc_generic_hdmi(codec);
2408 if (err < 0)
2409 return err;
2410
2411 err = hdmi_parse_codec(codec);
2412 if (err < 0) {
2413 generic_spec_free(codec);
2414 return err;
2415 }
2416
2417 generic_hdmi_init_per_pins(codec);
2418 return 0;
2419}
2420
ade49db3
TI		 2421/*
2422 * generic audio component binding
2423 */
2424
2425/* turn on / off the unsol event jack detection dynamically */
2426static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2427 bool use_acomp)
2428{
2429 struct hda_jack_tbl *tbl;
2430
2431 tbl = snd_hda_jack_tbl_get(codec, nid);
2432 if (tbl) {
2433 /* clear unsol even if component notifier is used, or re-enable
2434 * if notifier is cleared
2435 */
2436 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2437 snd_hda_codec_write_cache(codec, nid, 0,
2438 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2439 } else {
2440 /* if no jack entry was defined beforehand, create a new one
2441 * at need (i.e. only when notifier is cleared)
2442 */
2443 if (!use_acomp)
2444 snd_hda_jack_detect_enable(codec, nid);
2445 }
2446}
2447
2448/* set up / clear component notifier dynamically */
2449static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2450 bool use_acomp)
2451{
2452 struct hdmi_spec *spec;
2453 int i;
2454
2455 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
302d5a80 2456 mutex_lock(&spec->bind_lock);
ade49db3
TI		 2457 spec->use_acomp_notifier = use_acomp;
2458 spec->codec->relaxed_resume = use_acomp;
2459 /* reprogram each jack detection logic depending on the notifier */
2460 if (spec->use_jack_detect) {
2461 for (i = 0; i < spec->num_pins; i++)
2462 reprogram_jack_detect(spec->codec,
2463 get_pin(spec, i)->pin_nid,
2464 use_acomp);
2465 }
302d5a80 2466 mutex_unlock(&spec->bind_lock);
ade49db3
TI		 2467}
2468
2469/* enable / disable the notifier via master bind / unbind */
2470static int generic_acomp_master_bind(struct device *dev,
2471 struct drm_audio_component *acomp)
2472{
2473 generic_acomp_notifier_set(acomp, true);
2474 return 0;
2475}
2476
2477static void generic_acomp_master_unbind(struct device *dev,
2478 struct drm_audio_component *acomp)
2479{
2480 generic_acomp_notifier_set(acomp, false);
2481}
2482
2483/* check whether both HD-audio and DRM PCI devices belong to the same bus */
2484static int match_bound_vga(struct device *dev, int subtype, void *data)
2485{
2486 struct hdac_bus *bus = data;
2487 struct pci_dev *pci, *master;
2488
2489 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2490 return 0;
2491 master = to_pci_dev(bus->dev);
2492 pci = to_pci_dev(dev);
2493 return master->bus == pci->bus;
2494}
2495
2496/* audio component notifier for AMD/Nvidia HDMI codecs */
2497static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2498{
2499 struct hda_codec *codec = audio_ptr;
2500 struct hdmi_spec *spec = codec->spec;
2501 hda_nid_t pin_nid = spec->port2pin(codec, port);
2502
2503 if (!pin_nid)
2504 return;
2505 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2506 return;
2507 /* skip notification during system suspend (but not in runtime PM);
2508 * the state will be updated at resume
2509 */
2510 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2511 return;
2512 /* ditto during suspend/resume process itself */
2513 if (snd_hdac_is_in_pm(&codec->core))
2514 return;
2515
2516 check_presence_and_report(codec, pin_nid, dev_id);
2517}
2518
2519/* set up the private drm_audio_ops from the template */
2520static void setup_drm_audio_ops(struct hda_codec *codec,
2521 const struct drm_audio_component_audio_ops *ops)
2522{
2523 struct hdmi_spec *spec = codec->spec;
2524
2525 spec->drm_audio_ops.audio_ptr = codec;
2526 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2527 * will call pin_eld_notify with using audio_ptr pointer
2528 * We need make sure audio_ptr is really setup
2529 */
2530 wmb();
2531 spec->drm_audio_ops.pin2port = ops->pin2port;
2532 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2533 spec->drm_audio_ops.master_bind = ops->master_bind;
2534 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2535}
2536
2537/* initialize the generic HDMI audio component */
2538static void generic_acomp_init(struct hda_codec *codec,
2539 const struct drm_audio_component_audio_ops *ops,
2540 int (*port2pin)(struct hda_codec *, int))
2541{
2542 struct hdmi_spec *spec = codec->spec;
2543
2544 spec->port2pin = port2pin;
2545 setup_drm_audio_ops(codec, ops);
2546 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
dd23e1d5 2547 match_bound_vga, 0)) {
ade49db3 2548 spec->acomp_registered = true;
dd23e1d5
TI		 2549 codec->bus->keep_power = 0;
2550 }
ade49db3
TI		 2551}
2552
a686632f
TI		 2553/*
2554 * Intel codec parsers and helpers
2555 */
2556
c88d4e84
TI		 2557static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2558 hda_nid_t nid)
2559{
2560 struct hdmi_spec *spec = codec->spec;
2561 hda_nid_t conns[4];
2562 int nconns;
6ffe168f 2563
c88d4e84
TI		 2564 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2565 if (nconns == spec->num_cvts &&
2566 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2567 return;
2568
c88d4e84 2569 /* override pins connection list */
4e76a883 2570 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2571 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2572}
2573
b0d8bc50
JK		 2574#define INTEL_GET_VENDOR_VERB 0xf81
2575#define INTEL_SET_VENDOR_VERB 0x781
2576#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2577#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1611a9c9
ML		 2578
2579static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2580 bool update_tree)
1611a9c9
ML		 2581{
2582 unsigned int vendor_param;
a87a4d23 2583 struct hdmi_spec *spec = codec->spec;
1611a9c9 2584
a87a4d23 2585 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
1611a9c9
ML		 2586 INTEL_GET_VENDOR_VERB, 0);
2587 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2588 return;
2589
2590 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
a87a4d23 2591 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
1611a9c9
ML		 2592 INTEL_SET_VENDOR_VERB, vendor_param);
2593 if (vendor_param == -1)
2594 return;
2595
17df3f55
TI		 2596 if (update_tree)
2597 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2598}
2599
c88d4e84
TI		 2600static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2601{
2602 unsigned int vendor_param;
a87a4d23 2603 struct hdmi_spec *spec = codec->spec;
c88d4e84 2604
a87a4d23 2605 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
c88d4e84
TI		 2606 INTEL_GET_VENDOR_VERB, 0);
2607 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2608 return;
2609
2610 /* enable DP1.2 mode */
2611 vendor_param |= INTEL_EN_DP12;
a551d914 2612 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
a87a4d23 2613 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
c88d4e84
TI		 2614 INTEL_SET_VENDOR_VERB, vendor_param);
2615}
2616
17df3f55
TI		 2617/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2618 * Otherwise you may get severe h/w communication errors.
2619 */
2620static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2621 unsigned int power_state)
2622{
2623 if (power_state == AC_PWRST_D0) {
2624 intel_haswell_enable_all_pins(codec, false);
2625 intel_haswell_fixup_enable_dp12(codec);
2626 }
c88d4e84 2627
17df3f55
TI		 2628 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2629 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2630}
6ffe168f 2631
a57942bf
TI		 2632/* There is a fixed mapping between audio pin node and display port.
2633 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2634 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2635 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2636 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2637 *
2638 * on VLV, ILK:
2639 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2640 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2641 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2642 */
2643static int intel_base_nid(struct hda_codec *codec)
2644{
2645 switch (codec->core.vendor_id) {
2646 case 0x80860054: /* ILK */
2647 case 0x80862804: /* ILK */
2648 case 0x80862882: /* VLV */
2649 return 4;
2650 default:
2651 return 5;
2652 }
2653}
2654
2655static int intel_pin2port(void *audio_ptr, int pin_nid)
2656{
b0d8bc50
JK		 2657 struct hda_codec *codec = audio_ptr;
2658 struct hdmi_spec *spec = codec->spec;
2659 int base_nid, i;
a57942bf 2660
b0d8bc50
JK		 2661 if (!spec->port_num) {
2662 base_nid = intel_base_nid(codec);
2663 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2664 return -1;
2665 return pin_nid - base_nid + 1; /* intel port is 1-based */
2666 }
2667
2668 /*
2669 * looking for the pin number in the mapping table and return
2670 * the index which indicate the port number
2671 */
2672 for (i = 0; i < spec->port_num; i++) {
2673 if (pin_nid == spec->port_map[i])
2674 return i + 1;
2675 }
2676
2677 /* return -1 if pin number exceeds our expectation */
2678 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2679 return -1;
a57942bf
TI		 2680}
2681
3140aafb
TI		 2682static int intel_port2pin(struct hda_codec *codec, int port)
2683{
2684 struct hdmi_spec *spec = codec->spec;
2685
2686 if (!spec->port_num) {
2687 /* we assume only from port-B to port-D */
2688 if (port < 1 || port > 3)
2689 return 0;
2690 /* intel port is 1-based */
2691 return port + intel_base_nid(codec) - 1;
2692 }
2693
2694 if (port < 1 || port > spec->port_num)
2695 return 0;
2696 return spec->port_map[port - 1];
2697}
2698
f9318941 2699static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
25adc137
DH		 2700{
2701 struct hda_codec *codec = audio_ptr;
7ff652ff 2702 int pin_nid;
9152085d 2703 int dev_id = pipe;
25adc137 2704
3140aafb
TI		 2705 pin_nid = intel_port2pin(codec, port);
2706 if (!pin_nid)
4f8e4f35 2707 return;
8ae743e8
TI		 2708 /* skip notification during system suspend (but not in runtime PM);
2709 * the state will be updated at resume
2710 */
2711 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2712 return;
eb399d3c 2713 /* ditto during suspend/resume process itself */
feb20fae 2714 if (snd_hdac_is_in_pm(&codec->core))
eb399d3c 2715 return;
8ae743e8 2716
bb03ed21 2717 snd_hdac_i915_set_bclk(&codec->bus->core);
9152085d 2718 check_presence_and_report(codec, pin_nid, dev_id);
25adc137
DH		 2719}
2720
ade49db3
TI		 2721static const struct drm_audio_component_audio_ops intel_audio_ops = {
2722 .pin2port = intel_pin2port,
2723 .pin_eld_notify = intel_pin_eld_notify,
2724};
2725
a686632f
TI		 2726/* register i915 component pin_eld_notify callback */
2727static void register_i915_notifier(struct hda_codec *codec)
84eb01be 2728{
a686632f 2729 struct hdmi_spec *spec = codec->spec;
84eb01be 2730
a686632f 2731 spec->use_acomp_notifier = true;
ade49db3
TI		 2732 spec->port2pin = intel_port2pin;
2733 setup_drm_audio_ops(codec, &intel_audio_ops);
a57942bf 2734 snd_hdac_acomp_register_notifier(&codec->bus->core,
82887c0b 2735 &spec->drm_audio_ops);
4914da2f
TI		 2736 /* no need for forcible resume for jack check thanks to notifier */
2737 codec->relaxed_resume = 1;
a686632f 2738}
84eb01be 2739
2c1c9b86
TI		 2740/* setup_stream ops override for HSW+ */
2741static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2742 hda_nid_t pin_nid, u32 stream_tag, int format)
2743{
2744 haswell_verify_D0(codec, cvt_nid, pin_nid);
2745 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2746}
739ffee9 2747
4846a67e
TI		 2748/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2749static void i915_pin_cvt_fixup(struct hda_codec *codec,
2750 struct hdmi_spec_per_pin *per_pin,
2751 hda_nid_t cvt_nid)
2752{
2753 if (per_pin) {
9152085d
LY		 2754 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2755 per_pin->dev_id);
4846a67e
TI		 2756 intel_verify_pin_cvt_connect(codec, per_pin);
2757 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
9152085d 2758 per_pin->dev_id, per_pin->mux_idx);
4846a67e 2759 } else {
9152085d 2760 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
4846a67e
TI		 2761 }
2762}
739ffee9 2763
43f6c8d9
TI		 2764/* precondition and allocation for Intel codecs */
2765static int alloc_intel_hdmi(struct hda_codec *codec)
a686632f 2766{
f2dbe87c
TI		 2767 int err;
2768
43f6c8d9 2769 /* requires i915 binding */
a686632f
TI		 2770 if (!codec->bus->core.audio_component) {
2771 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
fdd49c51
TI		 2772 /* set probe_id here to prevent generic fallback binding */
2773 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
a686632f 2774 return -ENODEV;
691be973 2775 }
55913110 2776
f2dbe87c
TI		 2777 err = alloc_generic_hdmi(codec);
2778 if (err < 0)
2779 return err;
2780 /* no need to handle unsol events */
2781 codec->patch_ops.unsol_event = NULL;
2782 return 0;
43f6c8d9
TI		 2783}
2784
2785/* parse and post-process for Intel codecs */
2786static int parse_intel_hdmi(struct hda_codec *codec)
2787{
2788 int err;
2789
2790 err = hdmi_parse_codec(codec);
2791 if (err < 0) {
2792 generic_spec_free(codec);
2793 return err;
2794 }
2795
2796 generic_hdmi_init_per_pins(codec);
2797 register_i915_notifier(codec);
2798 return 0;
2799}
2800
2801/* Intel Haswell and onwards; audio component with eld notifier */
b0d8bc50
JK		 2802static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2803 const int *port_map, int port_num)
43f6c8d9
TI		 2804{
2805 struct hdmi_spec *spec;
2806 int err;
2807
2808 err = alloc_intel_hdmi(codec);
a686632f
TI		 2809 if (err < 0)
2810 return err;
2811 spec = codec->spec;
9152085d
LY		 2812 codec->dp_mst = true;
2813 spec->dyn_pcm_assign = true;
a87a4d23 2814 spec->vendor_nid = vendor_nid;
b0d8bc50
JK		 2815 spec->port_map = port_map;
2816 spec->port_num = port_num;
6ffe168f 2817
a686632f
TI		 2818 intel_haswell_enable_all_pins(codec, true);
2819 intel_haswell_fixup_enable_dp12(codec);
2820
46594d33 2821 codec->display_power_control = 1;
2bd1f73f 2822
a686632f 2823 codec->patch_ops.set_power_state = haswell_set_power_state;
a686632f
TI		 2824 codec->depop_delay = 0;
2825 codec->auto_runtime_pm = 1;
2826
2c1c9b86 2827 spec->ops.setup_stream = i915_hsw_setup_stream;
4846a67e 2828 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2c1c9b86 2829
43f6c8d9 2830 return parse_intel_hdmi(codec);
a686632f
TI		 2831}
2832
a87a4d23
ACDO		 2833static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2834{
b0d8bc50 2835 return intel_hsw_common_init(codec, 0x08, NULL, 0);
a87a4d23
ACDO		 2836}
2837
2838static int patch_i915_glk_hdmi(struct hda_codec *codec)
2839{
b0d8bc50
JK		 2840 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2841}
2842
2843static int patch_i915_icl_hdmi(struct hda_codec *codec)
2844{
2845 /*
2846 * pin to port mapping table where the value indicate the pin number and
2847 * the index indicate the port number with 1 base.
2848 */
2849 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb};
2850
2851 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
a87a4d23
ACDO		 2852}
2853
7ff652ff 2854/* Intel Baytrail and Braswell; with eld notifier */
a686632f
TI		 2855static int patch_i915_byt_hdmi(struct hda_codec *codec)
2856{
2857 struct hdmi_spec *spec;
2858 int err;
2859
43f6c8d9 2860 err = alloc_intel_hdmi(codec);
a686632f
TI		 2861 if (err < 0)
2862 return err;
2863 spec = codec->spec;
2377c3c3 2864
a686632f
TI		 2865 /* For Valleyview/Cherryview, only the display codec is in the display
2866 * power well and can use link_power ops to request/release the power.
2867 */
029d92c2 2868 codec->display_power_control = 1;
84eb01be 2869
a686632f
TI		 2870 codec->depop_delay = 0;
2871 codec->auto_runtime_pm = 1;
84eb01be 2872
4846a67e
TI		 2873 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2874
43f6c8d9 2875 return parse_intel_hdmi(codec);
84eb01be
TI		 2876}
2877
7ff652ff 2878/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
e85015a3
TI		 2879static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2880{
e85015a3
TI		 2881 int err;
2882
43f6c8d9 2883 err = alloc_intel_hdmi(codec);
e85015a3
TI		 2884 if (err < 0)
2885 return err;
43f6c8d9 2886 return parse_intel_hdmi(codec);
84eb01be
TI		 2887}
2888
3aaf8980
SW		 2889/*
2890 * Shared non-generic implementations
2891 */
2892
2893static int simple_playback_build_pcms(struct hda_codec *codec)
2894{
2895 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2896 struct hda_pcm *info;
8ceb332d
TI		 2897 unsigned int chans;
2898 struct hda_pcm_stream *pstr;
bce0d2a8 2899 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2900
bce0d2a8
TI		 2901 per_cvt = get_cvt(spec, 0);
2902 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2903 chans = get_wcaps_channels(chans);
3aaf8980 2904
bbbc7e85 2905 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2906 if (!info)
2907 return -ENOMEM;
2bea241a 2908 spec->pcm_rec[0].pcm = info;
8ceb332d
TI		 2909 info->pcm_type = HDA_PCM_TYPE_HDMI;
2910 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2911 *pstr = spec->pcm_playback;
bce0d2a8 2912 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2913 if (pstr->channels_max <= 2 && chans && chans <= 16)
2914 pstr->channels_max = chans;
3aaf8980
SW		 2915
2916 return 0;
2917}
2918
4b6ace9e
TI		 2919/* unsolicited event for jack sensing */
2920static void simple_hdmi_unsol_event(struct hda_codec *codec,
2921 unsigned int res)
2922{
9dd8cf12 2923 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2924 snd_hda_jack_report_sync(codec);
2925}
2926
2927/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2928 * as long as spec->pins[] is set correctly
2929 */
2930#define simple_hdmi_build_jack generic_hdmi_build_jack
2931
3aaf8980
SW		 2932static int simple_playback_build_controls(struct hda_codec *codec)
2933{
2934 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2935 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2936 int err;
3aaf8980 2937
bce0d2a8 2938 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2939 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2940 per_cvt->cvt_nid,
2941 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2942 if (err < 0)
2943 return err;
2944 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2945}
2946
4f0110ce
TI		 2947static int simple_playback_init(struct hda_codec *codec)
2948{
2949 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2950 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2951 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2952
2953 snd_hda_codec_write(codec, pin, 0,
2954 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2955 /* some codecs require to unmute the pin */
2956 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2957 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2958 AMP_OUT_UNMUTE);
62f949bf 2959 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 2960 return 0;
2961}
2962
3aaf8980
SW		 2963static void simple_playback_free(struct hda_codec *codec)
2964{
2965 struct hdmi_spec *spec = codec->spec;
2966
bce0d2a8 2967 hdmi_array_free(spec);
3aaf8980
SW		 2968 kfree(spec);
2969}
2970
84eb01be
TI		 2971/*
2972 * Nvidia specific implementations
2973 */
2974
2975#define Nv_VERB_SET_Channel_Allocation 0xF79
2976#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2977#define Nv_VERB_SET_Audio_Protection_On 0xF98
2978#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2979
2980#define nvhdmi_master_con_nid_7x 0x04
2981#define nvhdmi_master_pin_nid_7x 0x05
2982
fb79e1e0 2983static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2984 /*front, rear, clfe, rear_surr */
2985 0x6, 0x8, 0xa, 0xc,
2986};
2987
ceaa86ba
TI		 2988static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2989 /* set audio protect on */
2990 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2991 /* enable digital output on pin widget */
2992 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2993 {} /* terminator */
2994};
2995
2996static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2997 /* set audio protect on */
2998 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2999 /* enable digital output on pin widget */
3000 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3001 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3002 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3003 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3004 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3005 {} /* terminator */
3006};
3007
3008#ifdef LIMITED_RATE_FMT_SUPPORT
3009/* support only the safe format and rate */
3010#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3011#define SUPPORTED_MAXBPS 16
3012#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3013#else
3014/* support all rates and formats */
3015#define SUPPORTED_RATES \
3016 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3017 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3018 SNDRV_PCM_RATE_192000)
3019#define SUPPORTED_MAXBPS 24
3020#define SUPPORTED_FORMATS \
3021 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3022#endif
3023
ceaa86ba
TI		 3024static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3025{
3026 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3027 return 0;
3028}
3029
3030static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 3031{
ceaa86ba 3032 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 3033 return 0;
3034}
3035
50c697ad 3036static const unsigned int channels_2_6_8[] = {
393004b2
ND		 3037 2, 6, 8
3038};
3039
50c697ad 3040static const unsigned int channels_2_8[] = {
393004b2
ND		 3041 2, 8
3042};
3043
50c697ad 3044static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
393004b2
ND		 3045 .count = ARRAY_SIZE(channels_2_6_8),
3046 .list = channels_2_6_8,
3047 .mask = 0,
3048};
3049
50c697ad 3050static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
393004b2
ND		 3051 .count = ARRAY_SIZE(channels_2_8),
3052 .list = channels_2_8,
3053 .mask = 0,
3054};
3055
84eb01be
TI		 3056static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3057 struct hda_codec *codec,
3058 struct snd_pcm_substream *substream)
3059{
3060 struct hdmi_spec *spec = codec->spec;
50c697ad 3061 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
393004b2 3062
b9a94a9c 3063 switch (codec->preset->vendor_id) {
393004b2
ND		 3064 case 0x10de0002:
3065 case 0x10de0003:
3066 case 0x10de0005:
3067 case 0x10de0006:
3068 hw_constraints_channels = &hw_constraints_2_8_channels;
3069 break;
3070 case 0x10de0007:
3071 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3072 break;
3073 default:
3074 break;
3075 }
3076
3077 if (hw_constraints_channels != NULL) {
3078 snd_pcm_hw_constraint_list(substream->runtime, 0,
3079 SNDRV_PCM_HW_PARAM_CHANNELS,
3080 hw_constraints_channels);
ad09fc9d
TI		 3081 } else {
3082 snd_pcm_hw_constraint_step(substream->runtime, 0,
3083 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 3084 }
3085
84eb01be
TI		 3086 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3087}
3088
3089static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3090 struct hda_codec *codec,
3091 struct snd_pcm_substream *substream)
3092{
3093 struct hdmi_spec *spec = codec->spec;
3094 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3095}
3096
3097static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3098 struct hda_codec *codec,
3099 unsigned int stream_tag,
3100 unsigned int format,
3101 struct snd_pcm_substream *substream)
3102{
3103 struct hdmi_spec *spec = codec->spec;
3104 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3105 stream_tag, format, substream);
3106}
3107
d0b1252d
TI		 3108static const struct hda_pcm_stream simple_pcm_playback = {
3109 .substreams = 1,
3110 .channels_min = 2,
3111 .channels_max = 2,
3112 .ops = {
3113 .open = simple_playback_pcm_open,
3114 .close = simple_playback_pcm_close,
3115 .prepare = simple_playback_pcm_prepare
3116 },
3117};
3118
3119static const struct hda_codec_ops simple_hdmi_patch_ops = {
3120 .build_controls = simple_playback_build_controls,
3121 .build_pcms = simple_playback_build_pcms,
3122 .init = simple_playback_init,
3123 .free = simple_playback_free,
250e41ac 3124 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 3125};
3126
3127static int patch_simple_hdmi(struct hda_codec *codec,
3128 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3129{
3130 struct hdmi_spec *spec;
bce0d2a8
TI		 3131 struct hdmi_spec_per_cvt *per_cvt;
3132 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 3133
3134 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3135 if (!spec)
3136 return -ENOMEM;
3137
ade49db3 3138 spec->codec = codec;
d0b1252d 3139 codec->spec = spec;
bce0d2a8 3140 hdmi_array_init(spec, 1);
d0b1252d
TI		 3141
3142 spec->multiout.num_dacs = 0; /* no analog */
3143 spec->multiout.max_channels = 2;
3144 spec->multiout.dig_out_nid = cvt_nid;
3145 spec->num_cvts = 1;
3146 spec->num_pins = 1;
bce0d2a8
TI		 3147 per_pin = snd_array_new(&spec->pins);
3148 per_cvt = snd_array_new(&spec->cvts);
3149 if (!per_pin || !per_cvt) {
3150 simple_playback_free(codec);
3151 return -ENOMEM;
3152 }
3153 per_cvt->cvt_nid = cvt_nid;
3154 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 3155 spec->pcm_playback = simple_pcm_playback;
3156
3157 codec->patch_ops = simple_hdmi_patch_ops;
3158
3159 return 0;
3160}
3161
1f348522
AP		 3162static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3163 int channels)
3164{
3165 unsigned int chanmask;
3166 int chan = channels ? (channels - 1) : 1;
3167
3168 switch (channels) {
3169 default:
3170 case 0:
3171 case 2:
3172 chanmask = 0x00;
3173 break;
3174 case 4:
3175 chanmask = 0x08;
3176 break;
3177 case 6:
3178 chanmask = 0x0b;
3179 break;
3180 case 8:
3181 chanmask = 0x13;
3182 break;
3183 }
3184
3185 /* Set the audio infoframe channel allocation and checksum fields. The
3186 * channel count is computed implicitly by the hardware. */
3187 snd_hda_codec_write(codec, 0x1, 0,
3188 Nv_VERB_SET_Channel_Allocation, chanmask);
3189
3190 snd_hda_codec_write(codec, 0x1, 0,
3191 Nv_VERB_SET_Info_Frame_Checksum,
3192 (0x71 - chan - chanmask));
3193}
3194
84eb01be
TI		 3195static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3196 struct hda_codec *codec,
3197 struct snd_pcm_substream *substream)
3198{
3199 struct hdmi_spec *spec = codec->spec;
3200 int i;
3201
3202 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3203 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3204 for (i = 0; i < 4; i++) {
3205 /* set the stream id */
3206 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3207 AC_VERB_SET_CHANNEL_STREAMID, 0);
3208 /* set the stream format */
3209 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3210 AC_VERB_SET_STREAM_FORMAT, 0);
3211 }
3212
1f348522
AP		 3213 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3214 * streams are disabled. */
3215 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3216
84eb01be
TI		 3217 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3218}
3219
3220static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3221 struct hda_codec *codec,
3222 unsigned int stream_tag,
3223 unsigned int format,
3224 struct snd_pcm_substream *substream)
3225{
3226 int chs;
112daa7a 3227 unsigned int dataDCC2, channel_id;
84eb01be 3228 int i;
7c935976 3229 struct hdmi_spec *spec = codec->spec;
e3245cdd 3230 struct hda_spdif_out *spdif;
bce0d2a8 3231 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 3232
3233 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 3234 per_cvt = get_cvt(spec, 0);
3235 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 3236
3237 chs = substream->runtime->channels;
84eb01be 3238
84eb01be
TI		 3239 dataDCC2 = 0x2;
3240
84eb01be 3241 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 3242 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3243 snd_hda_codec_write(codec,
3244 nvhdmi_master_con_nid_7x,
3245 0,
3246 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3247 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3248
3249 /* set the stream id */
3250 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3251 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3252
3253 /* set the stream format */
3254 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3255 AC_VERB_SET_STREAM_FORMAT, format);
3256
3257 /* turn on again (if needed) */
3258 /* enable and set the channel status audio/data flag */
7c935976 3259 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3260 snd_hda_codec_write(codec,
3261 nvhdmi_master_con_nid_7x,
3262 0,
3263 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3264 spdif->ctls & 0xff);
84eb01be
TI		 3265 snd_hda_codec_write(codec,
3266 nvhdmi_master_con_nid_7x,
3267 0,
3268 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3269 }
3270
3271 for (i = 0; i < 4; i++) {
3272 if (chs == 2)
3273 channel_id = 0;
3274 else
3275 channel_id = i * 2;
3276
3277 /* turn off SPDIF once;
3278 *otherwise the IEC958 bits won't be updated
3279 */
3280 if (codec->spdif_status_reset &&
7c935976 3281 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3282 snd_hda_codec_write(codec,
3283 nvhdmi_con_nids_7x[i],
3284 0,
3285 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3286 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3287 /* set the stream id */
3288 snd_hda_codec_write(codec,
3289 nvhdmi_con_nids_7x[i],
3290 0,
3291 AC_VERB_SET_CHANNEL_STREAMID,
3292 (stream_tag << 4) | channel_id);
3293 /* set the stream format */
3294 snd_hda_codec_write(codec,
3295 nvhdmi_con_nids_7x[i],
3296 0,
3297 AC_VERB_SET_STREAM_FORMAT,
3298 format);
3299 /* turn on again (if needed) */
3300 /* enable and set the channel status audio/data flag */
3301 if (codec->spdif_status_reset &&
7c935976 3302 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3303 snd_hda_codec_write(codec,
3304 nvhdmi_con_nids_7x[i],
3305 0,
3306 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3307 spdif->ctls & 0xff);
84eb01be
TI		 3308 snd_hda_codec_write(codec,
3309 nvhdmi_con_nids_7x[i],
3310 0,
3311 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3312 }
3313 }
3314
1f348522 3315 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 3316
3317 mutex_unlock(&codec->spdif_mutex);
3318 return 0;
3319}
3320
fb79e1e0 3321static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 3322 .substreams = 1,
3323 .channels_min = 2,
3324 .channels_max = 8,
3325 .nid = nvhdmi_master_con_nid_7x,
3326 .rates = SUPPORTED_RATES,
3327 .maxbps = SUPPORTED_MAXBPS,
3328 .formats = SUPPORTED_FORMATS,
3329 .ops = {
3330 .open = simple_playback_pcm_open,
3331 .close = nvhdmi_8ch_7x_pcm_close,
3332 .prepare = nvhdmi_8ch_7x_pcm_prepare
3333 },
3334};
3335
84eb01be
TI		 3336static int patch_nvhdmi_2ch(struct hda_codec *codec)
3337{
3338 struct hdmi_spec *spec;
d0b1252d
TI		 3339 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3340 nvhdmi_master_pin_nid_7x);
3341 if (err < 0)
3342 return err;
84eb01be 3343
ceaa86ba 3344 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 3345 /* override the PCM rates, etc, as the codec doesn't give full list */
3346 spec = codec->spec;
3347 spec->pcm_playback.rates = SUPPORTED_RATES;
3348 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3349 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 3350 return 0;
3351}
3352
53775b0d
TI		 3353static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3354{
3355 struct hdmi_spec *spec = codec->spec;
3356 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 3357 if (!err) {
3358 struct hda_pcm *info = get_pcm_rec(spec, 0);
3359 info->own_chmap = true;
3360 }
53775b0d
TI		 3361 return err;
3362}
3363
3364static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3365{
3366 struct hdmi_spec *spec = codec->spec;
bce0d2a8 3367 struct hda_pcm *info;
53775b0d
TI		 3368 struct snd_pcm_chmap *chmap;
3369 int err;
3370
3371 err = simple_playback_build_controls(codec);
3372 if (err < 0)
3373 return err;
3374
3375 /* add channel maps */
bce0d2a8
TI		 3376 info = get_pcm_rec(spec, 0);
3377 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 3378 SNDRV_PCM_STREAM_PLAYBACK,
3379 snd_pcm_alt_chmaps, 8, 0, &chmap);
3380 if (err < 0)
3381 return err;
b9a94a9c 3382 switch (codec->preset->vendor_id) {
53775b0d
TI		 3383 case 0x10de0002:
3384 case 0x10de0003:
3385 case 0x10de0005:
3386 case 0x10de0006:
3387 chmap->channel_mask = (1U << 2) | (1U << 8);
3388 break;
3389 case 0x10de0007:
3390 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3391 }
3392 return 0;
3393}
3394
84eb01be
TI		 3395static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3396{
3397 struct hdmi_spec *spec;
3398 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 3399 if (err < 0)
3400 return err;
3401 spec = codec->spec;
3402 spec->multiout.max_channels = 8;
d0b1252d 3403 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 3404 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 3405 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3406 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 3407
3408 /* Initialize the audio infoframe channel mask and checksum to something
3409 * valid */
3410 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3411
84eb01be
TI		 3412 return 0;
3413}
3414
611885bc
AH		 3415/*
3416 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3417 * - 0x10de0015
3418 * - 0x10de0040
3419 */
67b90cb8 3420static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
f302240d 3421 struct hdac_cea_channel_speaker_allocation *cap, int channels)
611885bc
AH		 3422{
3423 if (cap->ca_index == 0x00 && channels == 2)
3424 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3425
028cb68e
SP		 3426 /* If the speaker allocation matches the channel count, it is OK. */
3427 if (cap->channels != channels)
3428 return -1;
3429
3430 /* all channels are remappable freely */
3431 return SNDRV_CTL_TLVT_CHMAP_VAR;
611885bc
AH		 3432}
3433
828cb4ed
SP		 3434static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3435 int ca, int chs, unsigned char *map)
611885bc
AH		 3436{
3437 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3438 return -EINVAL;
3439
3440 return 0;
3441}
3442
ade49db3
TI		 3443/* map from pin NID to port; port is 0-based */
3444/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3445static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3446{
3447 return pin_nid - 4;
3448}
3449
3450/* reverse-map from port to pin NID: see above */
3451static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3452{
3453 return port + 4;
3454}
3455
3456static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3457 .pin2port = nvhdmi_pin2port,
3458 .pin_eld_notify = generic_acomp_pin_eld_notify,
3459 .master_bind = generic_acomp_master_bind,
3460 .master_unbind = generic_acomp_master_unbind,
3461};
3462
611885bc
AH		 3463static int patch_nvhdmi(struct hda_codec *codec)
3464{
3465 struct hdmi_spec *spec;
3466 int err;
3467
3468 err = patch_generic_hdmi(codec);
3469 if (err)
3470 return err;
3471
3472 spec = codec->spec;
75fae117 3473 spec->dyn_pin_out = true;
611885bc 3474
67b90cb8 3475 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
611885bc 3476 nvhdmi_chmap_cea_alloc_validate_get_type;
67b90cb8 3477 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
611885bc 3478
94989e31
LW		 3479 codec->link_down_at_suspend = 1;
3480
ade49db3
TI		 3481 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3482
611885bc
AH		 3483 return 0;
3484}
3485
26e9a960
TR		 3486/*
3487 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3488 * accessed using vendor-defined verbs. These registers can be used for
3489 * interoperability between the HDA and HDMI drivers.
3490 */
3491
3492/* Audio Function Group node */
3493#define NVIDIA_AFG_NID 0x01
3494
3495/*
3496 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3497 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3498 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3499 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3500 * additional bit (at position 30) to signal the validity of the format.
3501 *
3502 * | 31 | 30 | 29 16 | 15 0 |
3503 * +---------+-------+--------+--------+
3504 * | TRIGGER | VALID | UNUSED | FORMAT |
3505 * +-----------------------------------|
3506 *
3507 * Note that for the trigger bit to take effect it needs to change value
3508 * (i.e. it needs to be toggled).
3509 */
3510#define NVIDIA_GET_SCRATCH0 0xfa6
3511#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3512#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3513#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3514#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3515#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3516#define NVIDIA_SCRATCH_VALID (1 << 6)
3517
3518#define NVIDIA_GET_SCRATCH1 0xfab
3519#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3520#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3521#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3522#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3523
3524/*
3525 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3526 * the format is invalidated so that the HDMI codec can be disabled.
3527 */
3528static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3529{
3530 unsigned int value;
3531
3532 /* bits [31:30] contain the trigger and valid bits */
3533 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3534 NVIDIA_GET_SCRATCH0, 0);
3535 value = (value >> 24) & 0xff;
3536
3537 /* bits [15:0] are used to store the HDA format */
3538 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3539 NVIDIA_SET_SCRATCH0_BYTE0,
3540 (format >> 0) & 0xff);
3541 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3542 NVIDIA_SET_SCRATCH0_BYTE1,
3543 (format >> 8) & 0xff);
3544
3545 /* bits [16:24] are unused */
3546 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3547 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3548
3549 /*
3550 * Bit 30 signals that the data is valid and hence that HDMI audio can
3551 * be enabled.
3552 */
3553 if (format == 0)
3554 value &= ~NVIDIA_SCRATCH_VALID;
3555 else
3556 value |= NVIDIA_SCRATCH_VALID;
3557
3558 /*
3559 * Whenever the trigger bit is toggled, an interrupt is raised in the
3560 * HDMI codec. The HDMI driver will use that as trigger to update its
3561 * configuration.
3562 */
3563 value ^= NVIDIA_SCRATCH_TRIGGER;
3564
3565 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3566 NVIDIA_SET_SCRATCH0_BYTE3, value);
3567}
3568
3569static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3570 struct hda_codec *codec,
3571 unsigned int stream_tag,
3572 unsigned int format,
3573 struct snd_pcm_substream *substream)
3574{
3575 int err;
3576
3577 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3578 format, substream);
3579 if (err < 0)
3580 return err;
3581
3582 /* notify the HDMI codec of the format change */
3583 tegra_hdmi_set_format(codec, format);
3584
3585 return 0;
3586}
3587
3588static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3589 struct hda_codec *codec,
3590 struct snd_pcm_substream *substream)
3591{
3592 /* invalidate the format in the HDMI codec */
3593 tegra_hdmi_set_format(codec, 0);
3594
3595 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3596}
3597
3598static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3599{
3600 struct hdmi_spec *spec = codec->spec;
3601 unsigned int i;
3602
3603 for (i = 0; i < spec->num_pins; i++) {
3604 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3605
3606 if (pcm->pcm_type == type)
3607 return pcm;
3608 }
3609
3610 return NULL;
3611}
3612
3613static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3614{
3615 struct hda_pcm_stream *stream;
3616 struct hda_pcm *pcm;
3617 int err;
3618
3619 err = generic_hdmi_build_pcms(codec);
3620 if (err < 0)
3621 return err;
3622
3623 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3624 if (!pcm)
3625 return -ENODEV;
3626
3627 /*
3628 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3629 * codec about format changes.
3630 */
3631 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3632 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3633 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3634
3635 return 0;
3636}
3637
3638static int patch_tegra_hdmi(struct hda_codec *codec)
3639{
3640 int err;
3641
3642 err = patch_generic_hdmi(codec);
3643 if (err)
3644 return err;
3645
3646 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3647
3648 return 0;
3649}
3650
84eb01be 3651/*
5a613584 3652 * ATI/AMD-specific implementations
84eb01be
TI		 3653 */
3654
5a613584 3655#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3656 ((codec)->core.vendor_id == 0x1002aa01 && \
3657 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3658#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3659
3660/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3661#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3662#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3663#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3664#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3665#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3666#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3667#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3668#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3669#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3670#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3671#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3672#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3673#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3674#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3675#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3676#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3677#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3678#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3679#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3680#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3681#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3682#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3683#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3684#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3685
84d69e79
AH		 3686/* AMD specific HDA cvt verbs */
3687#define ATI_VERB_SET_RAMP_RATE 0x770
3688#define ATI_VERB_GET_RAMP_RATE 0xf70
3689
5a613584
AH		 3690#define ATI_OUT_ENABLE 0x1
3691
3692#define ATI_MULTICHANNEL_MODE_PAIRED 0
3693#define ATI_MULTICHANNEL_MODE_SINGLE 1
3694
461cf6b3
AH		 3695#define ATI_HBR_CAPABLE 0x01
3696#define ATI_HBR_ENABLE 0x10
3697
89250f84
AH		 3698static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3699 unsigned char *buf, int *eld_size)
3700{
3701 /* call hda_eld.c ATI/AMD-specific function */
3702 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3703 is_amdhdmi_rev3_or_later(codec));
3704}
3705
5a613584
AH		 3706static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3707 int active_channels, int conn_type)
3708{
3709 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3710}
3711
3712static int atihdmi_paired_swap_fc_lfe(int pos)
3713{
3714 /*
3715 * ATI/AMD have automatic FC/LFE swap built-in
3716 * when in pairwise mapping mode.
3717 */
3718
3719 switch (pos) {
3720 /* see channel_allocations[].speakers[] */
3721 case 2: return 3;
3722 case 3: return 2;
3723 default: break;
3724 }
3725
3726 return pos;
3727}
3728
828cb4ed
SP		 3729static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3730 int ca, int chs, unsigned char *map)
5a613584 3731{
f302240d 3732 struct hdac_cea_channel_speaker_allocation *cap;
5a613584
AH		 3733 int i, j;
3734
3735 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3736
bb63f726 3737 cap = snd_hdac_get_ch_alloc_from_ca(ca);
5a613584 3738 for (i = 0; i < chs; ++i) {
bb63f726 3739 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
5a613584
AH		 3740 bool ok = false;
3741 bool companion_ok = false;
3742
3743 if (!mask)
3744 continue;
3745
3746 for (j = 0 + i % 2; j < 8; j += 2) {
3747 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3748 if (cap->speakers[chan_idx] == mask) {
3749 /* channel is in a supported position */
3750 ok = true;
3751
3752 if (i % 2 == 0 && i + 1 < chs) {
3753 /* even channel, check the odd companion */
3754 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
bb63f726 3755 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
5a613584
AH		 3756 int comp_mask_act = cap->speakers[comp_chan_idx];
3757
3758 if (comp_mask_req == comp_mask_act)
3759 companion_ok = true;
3760 else
3761 return -EINVAL;
3762 }
3763 break;
3764 }
3765 }
3766
3767 if (!ok)
3768 return -EINVAL;
3769
3770 if (companion_ok)
3771 i++; /* companion channel already checked */
3772 }
3773
3774 return 0;
3775}
3776
739ffee9
SP		 3777static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3778 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
5a613584 3779{
739ffee9 3780 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3781 int verb;
3782 int ati_channel_setup = 0;
3783
3784 if (hdmi_slot > 7)
3785 return -EINVAL;
3786
3787 if (!has_amd_full_remap_support(codec)) {
3788 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3789
3790 /* In case this is an odd slot but without stream channel, do not
3791 * disable the slot since the corresponding even slot could have a
3792 * channel. In case neither have a channel, the slot pair will be
3793 * disabled when this function is called for the even slot. */
3794 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3795 return 0;
3796
3797 hdmi_slot -= hdmi_slot % 2;
3798
3799 if (stream_channel != 0xf)
3800 stream_channel -= stream_channel % 2;
3801 }
3802
3803 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3804
3805 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3806
3807 if (stream_channel != 0xf)
3808 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3809
3810 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3811}
3812
739ffee9
SP		 3813static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3814 hda_nid_t pin_nid, int asp_slot)
5a613584 3815{
739ffee9 3816 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3817 bool was_odd = false;
3818 int ati_asp_slot = asp_slot;
3819 int verb;
3820 int ati_channel_setup;
3821
3822 if (asp_slot > 7)
3823 return -EINVAL;
3824
3825 if (!has_amd_full_remap_support(codec)) {
3826 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3827 if (ati_asp_slot % 2 != 0) {
3828 ati_asp_slot -= 1;
3829 was_odd = true;
3830 }
3831 }
3832
3833 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3834
3835 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3836
3837 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3838 return 0xf;
3839
3840 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3841}
84eb01be 3842
67b90cb8
SP		 3843static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3844 struct hdac_chmap *chmap,
f302240d 3845 struct hdac_cea_channel_speaker_allocation *cap,
67b90cb8 3846 int channels)
5a613584
AH		 3847{
3848 int c;
3849
3850 /*
3851 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3852 * we need to take that into account (a single channel may take 2
3853 * channel slots if we need to carry a silent channel next to it).
3854 * On Rev3+ AMD codecs this function is not used.
3855 */
3856 int chanpairs = 0;
3857
3858 /* We only produce even-numbered channel count TLVs */
3859 if ((channels % 2) != 0)
3860 return -1;
3861
3862 for (c = 0; c < 7; c += 2) {
3863 if (cap->speakers[c] || cap->speakers[c+1])
3864 chanpairs++;
3865 }
3866
3867 if (chanpairs * 2 != channels)
3868 return -1;
3869
3870 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3871}
3872
828cb4ed 3873static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
f302240d
SP		 3874 struct hdac_cea_channel_speaker_allocation *cap,
3875 unsigned int *chmap, int channels)
5a613584
AH		 3876{
3877 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3878 int count = 0;
3879 int c;
3880
3881 for (c = 7; c >= 0; c--) {
3882 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3883 int spk = cap->speakers[chan];
3884 if (!spk) {
3885 /* add N/A channel if the companion channel is occupied */
3886 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3887 chmap[count++] = SNDRV_CHMAP_NA;
3888
3889 continue;
3890 }
3891
bb63f726 3892 chmap[count++] = snd_hdac_spk_to_chmap(spk);
5a613584
AH		 3893 }
3894
3895 WARN_ON(count != channels);
3896}
3897
461cf6b3
AH		 3898static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3899 bool hbr)
3900{
3901 int hbr_ctl, hbr_ctl_new;
3902
3903 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3904 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3905 if (hbr)
3906 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3907 else
3908 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3909
4e76a883
TI		 3910 codec_dbg(codec,
3911 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3912 pin_nid,
3913 hbr_ctl == hbr_ctl_new ? "" : "new-",
3914 hbr_ctl_new);
3915
3916 if (hbr_ctl != hbr_ctl_new)
3917 snd_hda_codec_write(codec, pin_nid, 0,
3918 ATI_VERB_SET_HBR_CONTROL,
3919 hbr_ctl_new);
3920
3921 } else if (hbr)
3922 return -EINVAL;
3923
3924 return 0;
3925}
3926
84d69e79
AH		 3927static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3928 hda_nid_t pin_nid, u32 stream_tag, int format)
3929{
3930
3931 if (is_amdhdmi_rev3_or_later(codec)) {
3932 int ramp_rate = 180; /* default as per AMD spec */
3933 /* disable ramp-up/down for non-pcm as per AMD spec */
3934 if (format & AC_FMT_TYPE_NON_PCM)
3935 ramp_rate = 0;
3936
3937 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3938 }
3939
3940 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3941}
3942
3943
5a613584 3944static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3945{
3946 struct hdmi_spec *spec = codec->spec;
5a613584 3947 int pin_idx, err;
84eb01be 3948
5a613584
AH		 3949 err = generic_hdmi_init(codec);
3950
3951 if (err)
84eb01be 3952 return err;
5a613584
AH		 3953
3954 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3955 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3956
3957 /* make sure downmix information in infoframe is zero */
3958 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3959
3960 /* enable channel-wise remap mode if supported */
3961 if (has_amd_full_remap_support(codec))
3962 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3963 ATI_VERB_SET_MULTICHANNEL_MODE,
3964 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3965 }
5a613584 3966
84eb01be
TI		 3967 return 0;
3968}
3969
ade49db3
TI		 3970/* map from pin NID to port; port is 0-based */
3971/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
3972static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
3973{
3974 return pin_nid / 2 - 1;
3975}
3976
3977/* reverse-map from port to pin NID: see above */
3978static int atihdmi_port2pin(struct hda_codec *codec, int port)
3979{
3980 return port * 2 + 3;
3981}
3982
3983static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
3984 .pin2port = atihdmi_pin2port,
3985 .pin_eld_notify = generic_acomp_pin_eld_notify,
3986 .master_bind = generic_acomp_master_bind,
3987 .master_unbind = generic_acomp_master_unbind,
3988};
3989
84eb01be
TI		 3990static int patch_atihdmi(struct hda_codec *codec)
3991{
3992 struct hdmi_spec *spec;
5a613584
AH		 3993 struct hdmi_spec_per_cvt *per_cvt;
3994 int err, cvt_idx;
3995
3996 err = patch_generic_hdmi(codec);
3997
3998 if (err)
d0b1252d 3999 return err;
5a613584
AH		 4000
4001 codec->patch_ops.init = atihdmi_init;
4002
d0b1252d 4003 spec = codec->spec;
5a613584 4004
89250f84 4005 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584 4006 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 4007 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 4008 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584 4009
39669225
TI		 4010 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4011 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4012
5a613584
AH		 4013 if (!has_amd_full_remap_support(codec)) {
4014 /* override to ATI/AMD-specific versions with pairwise mapping */
67b90cb8 4015 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
5a613584 4016 atihdmi_paired_chmap_cea_alloc_validate_get_type;
67b90cb8
SP		 4017 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4018 atihdmi_paired_cea_alloc_to_tlv_chmap;
4019 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
5a613584
AH		 4020 }
4021
4022 /* ATI/AMD converters do not advertise all of their capabilities */
4023 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4024 per_cvt = get_cvt(spec, cvt_idx);
4025 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4026 per_cvt->rates |= SUPPORTED_RATES;
4027 per_cvt->formats |= SUPPORTED_FORMATS;
4028 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4029 }
4030
67b90cb8 4031 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
5a613584 4032
57cb54e5
TI		 4033 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4034 * the link-down as is. Tell the core to allow it.
4035 */
4036 codec->link_down_at_suspend = 1;
4037
ade49db3
TI		 4038 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4039
84eb01be
TI		 4040 return 0;
4041}
4042
3de5ff88
AL		 4043/* VIA HDMI Implementation */
4044#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4045#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4046
3de5ff88
AL		 4047static int patch_via_hdmi(struct hda_codec *codec)
4048{
250e41ac 4049 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 4050}
84eb01be
TI		 4051
4052/*
4053 * patch entries
4054 */
b9a94a9c
TI		 4055static const struct hda_device_id snd_hda_id_hdmi[] = {
4056HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4057HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4058HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4059HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4060HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4061HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4062HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
74ec1181 4063HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
b9a94a9c
TI		 4064HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4065HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
74ec1181 4066HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
b9a94a9c
TI		 4067HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4068HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4069HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
74ec1181
DD		 4070HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
4071HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 4072HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
4073HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
4074HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
4075HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
4076HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
4077HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
4078HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
4079HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
4080HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
4081HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
4082HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 4083/* 17 is known to be absent */
b9a94a9c
TI		 4084HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
4085HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
4086HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
4087HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
4088HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
4089HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4090HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4091HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4092HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
917bb90c
TR		 4093HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4094HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4095HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4096HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
b9a94a9c
TI		 4097HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4098HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4099HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4100HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4101HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 4102HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4103HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
b9a94a9c 4104HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
74ec1181 4105HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
b9a94a9c 4106HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 4107HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4108HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 4109HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4110HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4111HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4112HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 4113HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4114HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4115HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4116HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4117HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
b9a94a9c 4118HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
74ec1181 4119HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
af677166 4120HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
74ec1181 4121HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
2d369c74 4122HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3ec622f4 4123HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 4124HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4125HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4126HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4127HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4128HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4129HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4130HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4131HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4132HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4133HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
b9a94a9c 4134HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
74ec1181 4135HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
b9a94a9c
TI		 4136HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4137HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4138HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4139HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
7ff652ff 4140HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
b0d8bc50 4141HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
b9a94a9c
TI		 4142HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4143HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4144HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
7ff652ff 4145HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
e85015a3
TI		 4146HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4147HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
a686632f
TI		 4148HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4149HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4150HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4151HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4152HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
2b4584d0 4153HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
a87a4d23 4154HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
b0d8bc50 4155HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
b9a94a9c 4156HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
a686632f
TI		 4157HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4158HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
b9a94a9c 4159HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 4160/* special ID for generic HDMI */
b9a94a9c 4161HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 4162{} /* terminator */
4163};
b9a94a9c 4164MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 4165
4166MODULE_LICENSE("GPL");
4167MODULE_DESCRIPTION("HDMI HD-audio codec");
4168MODULE_ALIAS("snd-hda-codec-intelhdmi");
4169MODULE_ALIAS("snd-hda-codec-nvhdmi");
4170MODULE_ALIAS("snd-hda-codec-atihdmi");
4171
d8a766a1 4172static struct hda_codec_driver hdmi_driver = {
b9a94a9c 4173 .id = snd_hda_id_hdmi,
84eb01be
TI		 4174};
4175
d8a766a1 4176module_hda_codec_driver(hdmi_driver);
Linux 6.x block layer and io_uring tree(s)