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ALSA: hda/ca0132 - Clean up patch_ca0132()
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb 34#include <sound/core.h>
be57bfff 35#include <sound/hda_codec.h>
95c6e9cb 36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
38ba69ff 52#define FLOAT_THREE 0x40400000
7cb9d94c 53#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 54#define FLOAT_MINUS_5 0xc0a00000
55
ef6b2ead
IM		 56#define UNSOL_TAG_DSP 0x16
57
4aa3bb0c
IM		 58#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
ef6b2ead
IM		 66#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 68
95c6e9cb
IM		 69#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
4aa3bb0c
IM		 72#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
01ef7dbf 83#define EFX_FILE "ctefx.bin"
7a928186 84#define DESKTOP_EFX_FILE "ctefx-desktop.bin"
8a19bcee 85#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 86
24f3cede 87#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 88MODULE_FIRMWARE(EFX_FILE);
7a928186 89MODULE_FIRMWARE(DESKTOP_EFX_FILE);
8a19bcee 90MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 91#endif
01ef7dbf 92
3a03f83b 93static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 94
7cb9d94c 95#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 96enum {
97 SPEAKER_OUT,
7cb9d94c
CM		 98 HEADPHONE_OUT,
99 SURROUND_OUT
ef6b2ead
IM		 100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
7cb9d94c 107/* Strings for Input Source Enum Control */
3a03f83b 108static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
ef6b2ead
IM		 116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
7cb9d94c
CM		 149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
212de2e7
CM		 155 MIC_BOOST_ENUM,
156 AE5_HEADPHONE_GAIN_ENUM,
d51434d4
CM		 157 AE5_SOUND_FILTER_ENUM,
158 ZXR_HEADPHONE_GAIN
ef6b2ead
IM		 159#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
160};
161
162/* Effects values size*/
163#define EFFECT_VALS_MAX_COUNT 12
164
47cdf76e
CM		 165/*
166 * Default values for the effect slider controls, they are in order of their
167 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
168 * X-bass.
169 */
170static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
171/* Amount of effect level sliders for ca0132_alt controls. */
172#define EFFECT_LEVEL_SLIDERS 5
173
e8412ca4
DR		 174/* Latency introduced by DSP blocks in milliseconds. */
175#define DSP_CAPTURE_INIT_LATENCY 0
176#define DSP_CRYSTAL_VOICE_LATENCY 124
177#define DSP_PLAYBACK_INIT_LATENCY 13
178#define DSP_PLAY_ENHANCEMENT_LATENCY 30
179#define DSP_SPEAKER_OUT_LATENCY 7
180
ef6b2ead 181struct ct_effect {
975cc02a 182 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 183 hda_nid_t nid;
184 int mid; /*effect module ID*/
185 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
186 int direct; /* 0:output; 1:input*/
187 int params; /* number of default non-on/off params */
188 /*effect default values, 1st is on/off. */
189 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
190};
191
192#define EFX_DIR_OUT 0
193#define EFX_DIR_IN 1
194
862154bb 195static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 196 { .name = "Surround",
197 .nid = SURROUND,
198 .mid = 0x96,
199 .reqs = {0, 1},
200 .direct = EFX_DIR_OUT,
201 .params = 1,
202 .def_vals = {0x3F800000, 0x3F2B851F}
203 },
204 { .name = "Crystalizer",
205 .nid = CRYSTALIZER,
206 .mid = 0x96,
207 .reqs = {7, 8},
208 .direct = EFX_DIR_OUT,
209 .params = 1,
210 .def_vals = {0x3F800000, 0x3F266666}
211 },
212 { .name = "Dialog Plus",
213 .nid = DIALOG_PLUS,
214 .mid = 0x96,
215 .reqs = {2, 3},
216 .direct = EFX_DIR_OUT,
217 .params = 1,
218 .def_vals = {0x00000000, 0x3F000000}
219 },
220 { .name = "Smart Volume",
221 .nid = SMART_VOLUME,
222 .mid = 0x96,
223 .reqs = {4, 5, 6},
224 .direct = EFX_DIR_OUT,
225 .params = 2,
226 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
227 },
228 { .name = "X-Bass",
229 .nid = X_BASS,
230 .mid = 0x96,
231 .reqs = {24, 23, 25},
232 .direct = EFX_DIR_OUT,
233 .params = 2,
234 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
235 },
236 { .name = "Equalizer",
237 .nid = EQUALIZER,
238 .mid = 0x96,
239 .reqs = {9, 10, 11, 12, 13, 14,
240 15, 16, 17, 18, 19, 20},
241 .direct = EFX_DIR_OUT,
242 .params = 11,
243 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
244 0x00000000, 0x00000000, 0x00000000, 0x00000000,
245 0x00000000, 0x00000000, 0x00000000, 0x00000000}
246 },
247 { .name = "Echo Cancellation",
248 .nid = ECHO_CANCELLATION,
249 .mid = 0x95,
250 .reqs = {0, 1, 2, 3},
251 .direct = EFX_DIR_IN,
252 .params = 3,
253 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
254 },
255 { .name = "Voice Focus",
256 .nid = VOICE_FOCUS,
257 .mid = 0x95,
258 .reqs = {6, 7, 8, 9},
259 .direct = EFX_DIR_IN,
260 .params = 3,
261 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
262 },
263 { .name = "Mic SVM",
264 .nid = MIC_SVM,
265 .mid = 0x95,
266 .reqs = {44, 45},
267 .direct = EFX_DIR_IN,
268 .params = 1,
269 .def_vals = {0x00000000, 0x3F3D70A4}
270 },
271 { .name = "Noise Reduction",
272 .nid = NOISE_REDUCTION,
273 .mid = 0x95,
274 .reqs = {4, 5},
275 .direct = EFX_DIR_IN,
276 .params = 1,
277 .def_vals = {0x3F800000, 0x3F000000}
278 },
279 { .name = "VoiceFX",
280 .nid = VOICEFX,
281 .mid = 0x95,
282 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
283 .direct = EFX_DIR_IN,
284 .params = 8,
285 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
286 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
287 0x00000000}
288 }
289};
290
291/* Tuning controls */
292#ifdef ENABLE_TUNING_CONTROLS
293
294enum {
295#define TUNING_CTL_START_NID 0xC0
296 WEDGE_ANGLE = TUNING_CTL_START_NID,
297 SVM_LEVEL,
298 EQUALIZER_BAND_0,
299 EQUALIZER_BAND_1,
300 EQUALIZER_BAND_2,
301 EQUALIZER_BAND_3,
302 EQUALIZER_BAND_4,
303 EQUALIZER_BAND_5,
304 EQUALIZER_BAND_6,
305 EQUALIZER_BAND_7,
306 EQUALIZER_BAND_8,
307 EQUALIZER_BAND_9,
308 TUNING_CTL_END_NID
309#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
310};
311
312struct ct_tuning_ctl {
975cc02a 313 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 314 hda_nid_t parent_nid;
315 hda_nid_t nid;
316 int mid; /*effect module ID*/
317 int req; /*effect module request*/
318 int direct; /* 0:output; 1:input*/
319 unsigned int def_val;/*effect default values*/
320};
321
862154bb 322static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 323 { .name = "Wedge Angle",
324 .parent_nid = VOICE_FOCUS,
325 .nid = WEDGE_ANGLE,
326 .mid = 0x95,
327 .req = 8,
328 .direct = EFX_DIR_IN,
329 .def_val = 0x41F00000
330 },
331 { .name = "SVM Level",
332 .parent_nid = MIC_SVM,
333 .nid = SVM_LEVEL,
334 .mid = 0x95,
335 .req = 45,
336 .direct = EFX_DIR_IN,
337 .def_val = 0x3F3D70A4
338 },
339 { .name = "EQ Band0",
340 .parent_nid = EQUALIZER,
341 .nid = EQUALIZER_BAND_0,
342 .mid = 0x96,
343 .req = 11,
344 .direct = EFX_DIR_OUT,
345 .def_val = 0x00000000
346 },
347 { .name = "EQ Band1",
348 .parent_nid = EQUALIZER,
349 .nid = EQUALIZER_BAND_1,
350 .mid = 0x96,
351 .req = 12,
352 .direct = EFX_DIR_OUT,
353 .def_val = 0x00000000
354 },
355 { .name = "EQ Band2",
356 .parent_nid = EQUALIZER,
357 .nid = EQUALIZER_BAND_2,
358 .mid = 0x96,
359 .req = 13,
360 .direct = EFX_DIR_OUT,
361 .def_val = 0x00000000
362 },
363 { .name = "EQ Band3",
364 .parent_nid = EQUALIZER,
365 .nid = EQUALIZER_BAND_3,
366 .mid = 0x96,
367 .req = 14,
368 .direct = EFX_DIR_OUT,
369 .def_val = 0x00000000
370 },
371 { .name = "EQ Band4",
372 .parent_nid = EQUALIZER,
373 .nid = EQUALIZER_BAND_4,
374 .mid = 0x96,
375 .req = 15,
376 .direct = EFX_DIR_OUT,
377 .def_val = 0x00000000
378 },
379 { .name = "EQ Band5",
380 .parent_nid = EQUALIZER,
381 .nid = EQUALIZER_BAND_5,
382 .mid = 0x96,
383 .req = 16,
384 .direct = EFX_DIR_OUT,
385 .def_val = 0x00000000
386 },
387 { .name = "EQ Band6",
388 .parent_nid = EQUALIZER,
389 .nid = EQUALIZER_BAND_6,
390 .mid = 0x96,
391 .req = 17,
392 .direct = EFX_DIR_OUT,
393 .def_val = 0x00000000
394 },
395 { .name = "EQ Band7",
396 .parent_nid = EQUALIZER,
397 .nid = EQUALIZER_BAND_7,
398 .mid = 0x96,
399 .req = 18,
400 .direct = EFX_DIR_OUT,
401 .def_val = 0x00000000
402 },
403 { .name = "EQ Band8",
404 .parent_nid = EQUALIZER,
405 .nid = EQUALIZER_BAND_8,
406 .mid = 0x96,
407 .req = 19,
408 .direct = EFX_DIR_OUT,
409 .def_val = 0x00000000
410 },
411 { .name = "EQ Band9",
412 .parent_nid = EQUALIZER,
413 .nid = EQUALIZER_BAND_9,
414 .mid = 0x96,
415 .req = 20,
416 .direct = EFX_DIR_OUT,
417 .def_val = 0x00000000
418 }
419};
420#endif
421
422/* Voice FX Presets */
423#define VOICEFX_MAX_PARAM_COUNT 9
424
425struct ct_voicefx {
426 char *name;
427 hda_nid_t nid;
428 int mid;
429 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
430};
431
432struct ct_voicefx_preset {
433 char *name; /*preset name*/
434 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
435};
436
862154bb 437static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 438 .name = "VoiceFX Capture Switch",
439 .nid = VOICEFX,
440 .mid = 0x95,
441 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
442};
443
862154bb 444static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 445 { .name = "Neutral",
446 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
447 0x44FA0000, 0x3F800000, 0x3F800000,
448 0x3F800000, 0x00000000, 0x00000000 }
449 },
450 { .name = "Female2Male",
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x44FA0000, 0x3F19999A, 0x3F866666,
453 0x3F800000, 0x00000000, 0x00000000 }
454 },
455 { .name = "Male2Female",
456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 0x450AC000, 0x4017AE14, 0x3F6B851F,
458 0x3F800000, 0x00000000, 0x00000000 }
459 },
460 { .name = "ScrappyKid",
461 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
462 0x44FA0000, 0x40400000, 0x3F28F5C3,
463 0x3F800000, 0x00000000, 0x00000000 }
464 },
465 { .name = "Elderly",
466 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
467 0x44E10000, 0x3FB33333, 0x3FB9999A,
468 0x3F800000, 0x3E3A2E43, 0x00000000 }
469 },
470 { .name = "Orc",
471 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
472 0x45098000, 0x3F266666, 0x3FC00000,
473 0x3F800000, 0x00000000, 0x00000000 }
474 },
475 { .name = "Elf",
476 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
477 0x45193000, 0x3F8E147B, 0x3F75C28F,
478 0x3F800000, 0x00000000, 0x00000000 }
479 },
480 { .name = "Dwarf",
481 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
482 0x45007000, 0x3F451EB8, 0x3F7851EC,
483 0x3F800000, 0x00000000, 0x00000000 }
484 },
485 { .name = "AlienBrute",
486 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
487 0x451F6000, 0x3F266666, 0x3FA7D945,
488 0x3F800000, 0x3CF5C28F, 0x00000000 }
489 },
490 { .name = "Robot",
491 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
492 0x44FA0000, 0x3FB2718B, 0x3F800000,
493 0xBC07010E, 0x00000000, 0x00000000 }
494 },
495 { .name = "Marine",
496 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
497 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
498 0x3F0A3D71, 0x00000000, 0x00000000 }
499 },
500 { .name = "Emo",
501 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
502 0x44FA0000, 0x3F800000, 0x3F800000,
503 0x3E4CCCCD, 0x00000000, 0x00000000 }
504 },
505 { .name = "DeepVoice",
506 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
507 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
508 0x3F800000, 0x00000000, 0x00000000 }
509 },
510 { .name = "Munchkin",
511 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
512 0x44FA0000, 0x3F800000, 0x3F1A043C,
513 0x3F800000, 0x00000000, 0x00000000 }
514 }
515};
516
47cdf76e
CM		 517/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
518
519#define EQ_PRESET_MAX_PARAM_COUNT 11
520
521struct ct_eq {
522 char *name;
523 hda_nid_t nid;
524 int mid;
525 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
526};
527
528struct ct_eq_preset {
529 char *name; /*preset name*/
530 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
531};
532
862154bb 533static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 534 .name = "FX: Equalizer Preset Switch",
535 .nid = EQ_PRESET_ENUM,
536 .mid = 0x96,
537 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
538};
539
540
862154bb 541static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 542 { .name = "Flat",
543 .vals = { 0x00000000, 0x00000000, 0x00000000,
544 0x00000000, 0x00000000, 0x00000000,
545 0x00000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000 }
547 },
548 { .name = "Acoustic",
549 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
550 0x40000000, 0x00000000, 0x00000000,
551 0x00000000, 0x00000000, 0x40000000,
552 0x40000000, 0x40000000 }
553 },
554 { .name = "Classical",
555 .vals = { 0x00000000, 0x00000000, 0x40C00000,
556 0x40C00000, 0x40466666, 0x00000000,
557 0x00000000, 0x00000000, 0x00000000,
558 0x40466666, 0x40466666 }
559 },
560 { .name = "Country",
561 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
562 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
563 0x00000000, 0x00000000, 0x40000000,
564 0x40466666, 0x40800000 }
565 },
566 { .name = "Dance",
567 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
568 0x40466666, 0x40866666, 0xBF99999A,
569 0xBF99999A, 0x00000000, 0x00000000,
570 0x40800000, 0x40800000 }
571 },
572 { .name = "Jazz",
573 .vals = { 0x00000000, 0x00000000, 0x00000000,
574 0x3F8CCCCD, 0x40800000, 0x40800000,
575 0x40800000, 0x00000000, 0x3F8CCCCD,
576 0x40466666, 0x40466666 }
577 },
578 { .name = "New Age",
579 .vals = { 0x00000000, 0x00000000, 0x40000000,
580 0x40000000, 0x00000000, 0x00000000,
581 0x00000000, 0x3F8CCCCD, 0x40000000,
582 0x40000000, 0x40000000 }
583 },
584 { .name = "Pop",
585 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
586 0x40000000, 0x40000000, 0x00000000,
587 0xBF99999A, 0xBF99999A, 0x00000000,
588 0x40466666, 0x40C00000 }
589 },
590 { .name = "Rock",
591 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
592 0x3F8CCCCD, 0x40000000, 0xBF99999A,
593 0xBF99999A, 0x00000000, 0x00000000,
594 0x40800000, 0x40800000 }
595 },
596 { .name = "Vocal",
597 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
598 0xBF99999A, 0x00000000, 0x40466666,
599 0x40800000, 0x40466666, 0x00000000,
600 0x00000000, 0x3F8CCCCD }
601 }
602};
603
7cb9d94c
CM		 604/* DSP command sequences for ca0132_alt_select_out */
605#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
606struct ca0132_alt_out_set {
607 char *name; /*preset name*/
608 unsigned char commands;
609 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
610 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
611 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
612};
613
614static const struct ca0132_alt_out_set alt_out_presets[] = {
615 { .name = "Line Out",
616 .commands = 7,
617 .mids = { 0x96, 0x96, 0x96, 0x8F,
618 0x96, 0x96, 0x96 },
619 .reqs = { 0x19, 0x17, 0x18, 0x01,
620 0x1F, 0x15, 0x3A },
621 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
622 0x00000000, 0x00000000, 0x00000000,
623 0x00000000 }
624 },
625 { .name = "Headphone",
626 .commands = 7,
627 .mids = { 0x96, 0x96, 0x96, 0x8F,
628 0x96, 0x96, 0x96 },
629 .reqs = { 0x19, 0x17, 0x18, 0x01,
630 0x1F, 0x15, 0x3A },
631 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
632 0x00000000, 0x00000000, 0x00000000,
633 0x00000000 }
634 },
635 { .name = "Surround",
636 .commands = 8,
637 .mids = { 0x96, 0x8F, 0x96, 0x96,
638 0x96, 0x96, 0x96, 0x96 },
639 .reqs = { 0x18, 0x01, 0x1F, 0x15,
640 0x3A, 0x1A, 0x1B, 0x1C },
641 .vals = { 0x00000000, 0x00000000, 0x00000000,
642 0x00000000, 0x00000000, 0x00000000,
643 0x00000000, 0x00000000 }
644 }
645};
646
017310fb
CM		 647/*
648 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
649 * and I don't know what the third req is, but it's always zero. I assume it's
650 * some sort of update or set command to tell the DSP there's new volume info.
651 */
652#define DSP_VOL_OUT 0
653#define DSP_VOL_IN 1
654
655struct ct_dsp_volume_ctl {
656 hda_nid_t vnid;
657 int mid; /* module ID*/
658 unsigned int reqs[3]; /* scp req ID */
659};
660
862154bb 661static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 662 { .vnid = VNID_SPK,
663 .mid = 0x32,
664 .reqs = {3, 4, 2}
665 },
666 { .vnid = VNID_MIC,
667 .mid = 0x37,
668 .reqs = {2, 3, 1}
669 }
670};
671
2283c85b
CM		 672/* Values for ca0113_mmio_command_set for selecting output. */
673#define AE5_CA0113_OUT_SET_COMMANDS 6
674struct ae5_ca0113_output_set {
675 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS];
676 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS];
677 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS];
678};
679
680static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = {
681 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
682 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
683 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
684 },
685 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
686 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
687 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 }
688 },
689 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
690 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
691 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
692 }
693};
694
212de2e7
CM		 695/* ae5 ca0113 command sequences to set headphone gain levels. */
696#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
697struct ae5_headphone_gain_set {
698 char *name;
699 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
700};
701
702static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
703 { .name = "Low (16-31",
704 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
705 },
706 { .name = "Medium (32-149",
707 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
708 },
709 { .name = "High (150-600",
710 .vals = { 0xff, 0xff, 0xff, 0x7f }
711 }
712};
713
714struct ae5_filter_set {
715 char *name;
716 unsigned int val;
717};
718
719static const struct ae5_filter_set ae5_filter_presets[] = {
720 { .name = "Slow Roll Off",
721 .val = 0xa0
722 },
723 { .name = "Minimum Phase",
724 .val = 0xc0
725 },
726 { .name = "Fast Roll Off",
727 .val = 0x80
728 }
729};
730
95c6e9cb
IM		 731enum hda_cmd_vendor_io {
732 /* for DspIO node */
733 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
734 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
735
736 VENDOR_DSPIO_STATUS = 0xF01,
737 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
738 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
739 VENDOR_DSPIO_DSP_INIT = 0x703,
740 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
741 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
742
743 /* for ChipIO node */
744 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
745 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
746 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
747 VENDOR_CHIPIO_DATA_LOW = 0x300,
748 VENDOR_CHIPIO_DATA_HIGH = 0x400,
749
bf85a91c
CM		 750 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
751 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
752
95c6e9cb
IM		 753 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
754 VENDOR_CHIPIO_STATUS = 0xF01,
755 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
756 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
757
4aa3bb0c
IM		 758 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
759 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
bf85a91c
CM		 760 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
761 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
762 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
4aa3bb0c 763
95c6e9cb 764 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 765 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 766
767 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
768 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
769 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
770 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
771 VENDOR_CHIPIO_FLAG_SET = 0x70F,
772 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 773 VENDOR_CHIPIO_PARAM_SET = 0x710,
774 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 775
776 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
777 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
778 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
779 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
780
4aa3bb0c
IM		 781 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
782 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
783 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
784 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
785
786 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
787 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
788 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
789 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
790 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
791 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
792
793 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 794};
795
796/*
797 * Control flag IDs
798 */
799enum control_flag_id {
800 /* Connection manager stream setup is bypassed/enabled */
801 CONTROL_FLAG_C_MGR = 0,
802 /* DSP DMA is bypassed/enabled */
803 CONTROL_FLAG_DMA = 1,
804 /* 8051 'idle' mode is disabled/enabled */
805 CONTROL_FLAG_IDLE_ENABLE = 2,
806 /* Tracker for the SPDIF-in path is bypassed/enabled */
807 CONTROL_FLAG_TRACKER = 3,
808 /* DigitalOut to Spdif2Out connection is disabled/enabled */
809 CONTROL_FLAG_SPDIF2OUT = 4,
810 /* Digital Microphone is disabled/enabled */
811 CONTROL_FLAG_DMIC = 5,
812 /* ADC_B rate is 48 kHz/96 kHz */
813 CONTROL_FLAG_ADC_B_96KHZ = 6,
814 /* ADC_C rate is 48 kHz/96 kHz */
815 CONTROL_FLAG_ADC_C_96KHZ = 7,
816 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
817 CONTROL_FLAG_DAC_96KHZ = 8,
818 /* DSP rate is 48 kHz/96 kHz */
819 CONTROL_FLAG_DSP_96KHZ = 9,
820 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
821 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
822 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
823 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
824 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
825 CONTROL_FLAG_DECODE_LOOP = 12,
826 /* De-emphasis filter on DAC-1 disabled/enabled */
827 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
828 /* De-emphasis filter on DAC-2 disabled/enabled */
829 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
830 /* De-emphasis filter on DAC-3 disabled/enabled */
831 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
832 /* High-pass filter on ADC_B disabled/enabled */
833 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
834 /* High-pass filter on ADC_C disabled/enabled */
835 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
836 /* Common mode on Port_A disabled/enabled */
837 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
838 /* Common mode on Port_D disabled/enabled */
839 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
840 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
841 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
842 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 843 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 844 /* ASI rate is 48kHz/96kHz */
845 CONTROL_FLAG_ASI_96KHZ = 22,
846 /* DAC power settings able to control attached ports no/yes */
847 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
848 /* Clock Stop OK reporting is disabled/enabled */
849 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
850 /* Number of control flags */
851 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
852};
853
854/*
855 * Control parameter IDs
856 */
4aa3bb0c 857enum control_param_id {
ef6b2ead
IM		 858 /* 0: None, 1: Mic1In*/
859 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 860 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
861 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 862 /* Port A output stage gain setting to use when 16 Ohm output
863 * impedance is selected*/
864 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
865 /* Port D output stage gain setting to use when 16 Ohm output
866 * impedance is selected*/
867 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb 868
bf85a91c
CM		 869 /*
870 * This control param name was found in the 8051 memory, and makes
871 * sense given the fact the AE-5 uses it and has the ASI flag set.
872 */
873 CONTROL_PARAM_ASI = 23,
874
95c6e9cb
IM		 875 /* Stream Control */
876
877 /* Select stream with the given ID */
878 CONTROL_PARAM_STREAM_ID = 24,
879 /* Source connection point for the selected stream */
880 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
881 /* Destination connection point for the selected stream */
882 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
883 /* Number of audio channels in the selected stream */
884 CONTROL_PARAM_STREAMS_CHANNELS = 27,
885 /*Enable control for the selected stream */
886 CONTROL_PARAM_STREAM_CONTROL = 28,
887
888 /* Connection Point Control */
889
890 /* Select connection point with the given ID */
891 CONTROL_PARAM_CONN_POINT_ID = 29,
892 /* Connection point sample rate */
893 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
894
895 /* Node Control */
896
897 /* Select HDA node with the given ID */
898 CONTROL_PARAM_NODE_ID = 31
899};
900
901/*
902 * Dsp Io Status codes
903 */
904enum hda_vendor_status_dspio {
905 /* Success */
906 VENDOR_STATUS_DSPIO_OK = 0x00,
907 /* Busy, unable to accept new command, the host must retry */
908 VENDOR_STATUS_DSPIO_BUSY = 0x01,
909 /* SCP command queue is full */
910 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
911 /* SCP response queue is empty */
912 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
913};
914
915/*
916 * Chip Io Status codes
917 */
918enum hda_vendor_status_chipio {
919 /* Success */
920 VENDOR_STATUS_CHIPIO_OK = 0x00,
921 /* Busy, unable to accept new command, the host must retry */
922 VENDOR_STATUS_CHIPIO_BUSY = 0x01
923};
924
925/*
926 * CA0132 sample rate
927 */
928enum ca0132_sample_rate {
929 SR_6_000 = 0x00,
930 SR_8_000 = 0x01,
931 SR_9_600 = 0x02,
932 SR_11_025 = 0x03,
933 SR_16_000 = 0x04,
934 SR_22_050 = 0x05,
935 SR_24_000 = 0x06,
936 SR_32_000 = 0x07,
937 SR_44_100 = 0x08,
938 SR_48_000 = 0x09,
939 SR_88_200 = 0x0A,
940 SR_96_000 = 0x0B,
941 SR_144_000 = 0x0C,
942 SR_176_400 = 0x0D,
943 SR_192_000 = 0x0E,
944 SR_384_000 = 0x0F,
945
946 SR_COUNT = 0x10,
947
948 SR_RATE_UNKNOWN = 0x1F
949};
950
01ef7dbf
IM		 951enum dsp_download_state {
952 DSP_DOWNLOAD_FAILED = -1,
953 DSP_DOWNLOAD_INIT = 0,
954 DSP_DOWNLOADING = 1,
955 DSP_DOWNLOADED = 2
956};
957
01ef7dbf
IM		 958/* retrieve parameters from hda format */
959#define get_hdafmt_chs(fmt) (fmt & 0xf)
960#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
961#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
962#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
963
964/*
965 * CA0132 specific
966 */
967
968struct ca0132_spec {
b0eaa072 969 const struct snd_kcontrol_new *mixers[5];
a7e76271 970 unsigned int num_mixers;
5aaca44d
IM		 971 const struct hda_verb *base_init_verbs;
972 const struct hda_verb *base_exit_verbs;
d5c016b5 973 const struct hda_verb *chip_init_verbs;
e42c7c73 974 const struct hda_verb *desktop_init_verbs;
d5c016b5 975 struct hda_verb *spec_init_verbs;
01ef7dbf 976 struct auto_pin_cfg autocfg;
5aaca44d
IM		 977
978 /* Nodes configurations */
01ef7dbf
IM		 979 struct hda_multi_out multiout;
980 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
981 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 982 unsigned int num_outputs;
01ef7dbf
IM		 983 hda_nid_t input_pins[AUTO_PIN_LAST];
984 hda_nid_t adcs[AUTO_PIN_LAST];
985 hda_nid_t dig_out;
986 hda_nid_t dig_in;
987 unsigned int num_inputs;
a7e76271
IM		 988 hda_nid_t shared_mic_nid;
989 hda_nid_t shared_out_nid;
d5c016b5 990 hda_nid_t unsol_tag_hp;
63177afc 991 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 992 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 993
994 /* chip access */
995 struct mutex chipio_mutex; /* chip access mutex */
996 u32 curr_chip_addx;
997
998 /* DSP download related */
999 enum dsp_download_state dsp_state;
1000 unsigned int dsp_stream_id;
1001 unsigned int wait_scp;
1002 unsigned int wait_scp_header;
1003 unsigned int wait_num_data;
1004 unsigned int scp_resp_header;
1005 unsigned int scp_resp_data[4];
1006 unsigned int scp_resp_count;
8a19bcee 1007 bool alt_firmware_present;
38ba69ff 1008 bool startup_check_entered;
e93ac30a 1009 bool dsp_reload;
5aaca44d
IM		 1010
1011 /* mixer and effects related */
1012 unsigned char dmic_ctl;
1013 int cur_out_type;
1014 int cur_mic_type;
1015 long vnode_lvol[VNODES_COUNT];
1016 long vnode_rvol[VNODES_COUNT];
1017 long vnode_lswitch[VNODES_COUNT];
1018 long vnode_rswitch[VNODES_COUNT];
1019 long effects_switch[EFFECTS_COUNT];
1020 long voicefx_val;
1021 long cur_mic_boost;
7cb9d94c
CM		 1022 /* ca0132_alt control related values */
1023 unsigned char in_enum_val;
1024 unsigned char out_enum_val;
47cdf76e
CM		 1025 unsigned char mic_boost_enum_val;
1026 unsigned char smart_volume_setting;
1027 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1028 long xbass_xover_freq;
1029 long eq_preset_val;
1030 unsigned int tlv[4];
1031 struct hda_vmaster_mute_hook vmaster_mute;
212de2e7
CM		 1032 /* AE-5 Control values */
1033 unsigned char ae5_headphone_gain_val;
1034 unsigned char ae5_filter_val;
d51434d4
CM		 1035 /* ZxR Control Values */
1036 unsigned char zxr_gain_set;
44f0c978 1037
993884f6
CCC		 1038 struct hda_codec *codec;
1039 struct delayed_work unsol_hp_work;
d5c016b5 1040 int quirk;
993884f6 1041
44f0c978
IM		 1042#ifdef ENABLE_TUNING_CONTROLS
1043 long cur_ctl_vals[TUNING_CTLS_COUNT];
1044#endif
aa31704f 1045 /*
08eca6b1
CM		 1046 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1047 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1048 * things.
aa31704f 1049 */
08eca6b1 1050 bool use_pci_mmio;
aa31704f 1051 void __iomem *mem_base;
009b8f97
CM		 1052
1053 /*
1054 * Whether or not to use the alt functions like alt_select_out,
1055 * alt_select_in, etc. Only used on desktop codecs for now, because of
1056 * surround sound support.
1057 */
1058 bool use_alt_functions;
47cdf76e
CM		 1059
1060 /*
1061 * Whether or not to use alt controls: volume effect sliders, EQ
1062 * presets, smart volume presets, and new control names with FX prefix.
1063 * Renames PlayEnhancement and CrystalVoice too.
1064 */
1065 bool use_alt_controls;
01ef7dbf
IM		 1066};
1067
d5c016b5
GM		 1068/*
1069 * CA0132 quirks table
1070 */
1071enum {
1072 QUIRK_NONE,
1073 QUIRK_ALIENWARE,
a57a46b9 1074 QUIRK_ALIENWARE_M17XR4,
8a19bcee 1075 QUIRK_SBZ,
b29733db
CM		 1076 QUIRK_ZXR,
1077 QUIRK_ZXR_DBPRO,
8a19bcee 1078 QUIRK_R3DI,
8f8c523c 1079 QUIRK_R3D,
f6276463 1080 QUIRK_AE5,
d5c016b5
GM		 1081};
1082
fe14f39e
TI		 1083static const struct hda_pintbl alienware_pincfgs[] = {
1084 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1085 { 0x0c, 0x411111f0 }, /* N/A */
1086 { 0x0d, 0x411111f0 }, /* N/A */
1087 { 0x0e, 0x411111f0 }, /* N/A */
1088 { 0x0f, 0x0321101f }, /* HP */
1089 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1090 { 0x11, 0x03a11021 }, /* Mic */
1091 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1092 { 0x13, 0x411111f0 }, /* N/A */
1093 { 0x18, 0x411111f0 }, /* N/A */
1094 {}
1095};
1096
63177afc
CM		 1097/* Sound Blaster Z pin configs taken from Windows Driver */
1098static const struct hda_pintbl sbz_pincfgs[] = {
1099 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1100 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1101 { 0x0d, 0x014510f0 }, /* Digital Out */
1102 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1103 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1104 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1105 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1106 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1107 { 0x13, 0x908700f0 }, /* What U Hear In*/
1108 { 0x18, 0x50d000f0 }, /* N/A */
1109 {}
1110};
1111
6dcd7244
CM		 1112/* Sound Blaster ZxR pin configs taken from Windows Driver */
1113static const struct hda_pintbl zxr_pincfgs[] = {
1114 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1115 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1116 { 0x0d, 0x014510f0 }, /* Digital Out */
1117 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1118 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1119 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1120 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1121 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1122 { 0x13, 0x908700f0 }, /* What U Hear In*/
1123 { 0x18, 0x50d000f0 }, /* N/A */
1124 {}
1125};
1126
7f73df95
CM		 1127/* Recon3D pin configs taken from Windows Driver */
1128static const struct hda_pintbl r3d_pincfgs[] = {
1129 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1130 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1131 { 0x0d, 0x014510f0 }, /* Digital Out */
1132 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1133 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1134 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1135 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1136 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1137 { 0x13, 0x908700f0 }, /* What U Hear In*/
1138 { 0x18, 0x50d000f0 }, /* N/A */
1139 {}
1140};
1141
d06feaf0
CM		 1142/* Sound Blaster AE-5 pin configs taken from Windows Driver */
1143static const struct hda_pintbl ae5_pincfgs[] = {
1144 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1145 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1146 { 0x0d, 0x014510f0 }, /* Digital Out */
1147 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1148 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1149 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1150 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1151 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1152 { 0x13, 0x908700f0 }, /* What U Hear In*/
1153 { 0x18, 0x50d000f0 }, /* N/A */
1154 {}
1155};
1156
63177afc
CM		 1157/* Recon3D integrated pin configs taken from Windows Driver */
1158static const struct hda_pintbl r3di_pincfgs[] = {
1159 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1160 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1161 { 0x0d, 0x014510f0 }, /* Digital Out */
1162 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1163 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1164 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1165 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1166 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1167 { 0x13, 0x908700f0 }, /* What U Hear In*/
1168 { 0x18, 0x500000f0 }, /* N/A */
1169 {}
1170};
1171
d5c016b5 1172static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1173 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1174 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1175 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1176 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1177 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1178 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1179 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1180 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1181 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
8f8c523c 1182 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
f6276463 1183 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
d5c016b5
GM		 1184 {}
1185};
1186
01ef7dbf
IM		 1187/*
1188 * CA0132 codec access
1189 */
399ae725 1190static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1191 unsigned int verb, unsigned int parm, unsigned int *res)
1192{
1193 unsigned int response;
1194 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1195 *res = response;
1196
1197 return ((response == -1) ? -1 : 0);
1198}
1199
1200static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1201 unsigned short converter_format, unsigned int *res)
1202{
1203 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1204 converter_format & 0xffff, res);
1205}
1206
1207static int codec_set_converter_stream_channel(struct hda_codec *codec,
1208 hda_nid_t nid, unsigned char stream,
1209 unsigned char channel, unsigned int *res)
1210{
1211 unsigned char converter_stream_channel = 0;
1212
1213 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1214 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1215 converter_stream_channel, res);
1216}
1217
1218/* Chip access helper function */
1219static int chipio_send(struct hda_codec *codec,
1220 unsigned int reg,
1221 unsigned int data)
1222{
1223 unsigned int res;
6d67530e 1224 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1225
1226 /* send bits of data specified by reg */
1227 do {
1228 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1229 reg, data);
1230 if (res == VENDOR_STATUS_CHIPIO_OK)
1231 return 0;
6d67530e
IM		 1232 msleep(20);
1233 } while (time_before(jiffies, timeout));
1234
01ef7dbf
IM		 1235 return -EIO;
1236}
1237
1238/*
1239 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1240 */
1241static int chipio_write_address(struct hda_codec *codec,
1242 unsigned int chip_addx)
1243{
4861af80 1244 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1245 int res;
1246
4861af80
IM		 1247 if (spec->curr_chip_addx == chip_addx)
1248 return 0;
1249
01ef7dbf
IM		 1250 /* send low 16 bits of the address */
1251 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1252 chip_addx & 0xffff);
1253
1254 if (res != -EIO) {
1255 /* send high 16 bits of the address */
1256 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1257 chip_addx >> 16);
1258 }
1259
d1600401 1260 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1261
4861af80 1262 return res;
01ef7dbf
IM		 1263}
1264
1265/*
1266 * Write data through the vendor widget -- NOT protected by the Mutex!
1267 */
01ef7dbf
IM		 1268static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1269{
5aaca44d 1270 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1271 int res;
1272
1273 /* send low 16 bits of the data */
1274 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1275
1276 if (res != -EIO) {
1277 /* send high 16 bits of the data */
1278 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1279 data >> 16);
1280 }
1281
5aaca44d
IM		 1282 /*If no error encountered, automatically increment the address
1283 as per chip behaviour*/
1284 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1285 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1286 return res;
1287}
1288
d5c21b88
IM		 1289/*
1290 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1291 */
01ef7dbf
IM		 1292static int chipio_write_data_multiple(struct hda_codec *codec,
1293 const u32 *data,
1294 unsigned int count)
1295{
1296 int status = 0;
1297
1298 if (data == NULL) {
4e76a883 1299 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1300 return -EINVAL;
1301 }
1302
1303 while ((count-- != 0) && (status == 0))
1304 status = chipio_write_data(codec, *data++);
1305
1306 return status;
1307}
1308
1309
1310/*
1311 * Read data through the vendor widget -- NOT protected by the Mutex!
1312 */
1313static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1314{
5aaca44d 1315 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1316 int res;
1317
1318 /* post read */
1319 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1320
1321 if (res != -EIO) {
1322 /* read status */
1323 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1324 }
1325
1326 if (res != -EIO) {
1327 /* read data */
1328 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1329 VENDOR_CHIPIO_HIC_READ_DATA,
1330 0);
1331 }
1332
5aaca44d
IM		 1333 /*If no error encountered, automatically increment the address
1334 as per chip behaviour*/
1335 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1336 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1337 return res;
1338}
1339
1340/*
1341 * Write given value to the given address through the chip I/O widget.
1342 * protected by the Mutex
1343 */
1344static int chipio_write(struct hda_codec *codec,
1345 unsigned int chip_addx, const unsigned int data)
1346{
1347 struct ca0132_spec *spec = codec->spec;
1348 int err;
1349
1350 mutex_lock(&spec->chipio_mutex);
1351
1352 /* write the address, and if successful proceed to write data */
1353 err = chipio_write_address(codec, chip_addx);
1354 if (err < 0)
1355 goto exit;
1356
1357 err = chipio_write_data(codec, data);
1358 if (err < 0)
1359 goto exit;
1360
1361exit:
1362 mutex_unlock(&spec->chipio_mutex);
1363 return err;
1364}
1365
38ba69ff
CM		 1366/*
1367 * Write given value to the given address through the chip I/O widget.
1368 * not protected by the Mutex
1369 */
1370static int chipio_write_no_mutex(struct hda_codec *codec,
1371 unsigned int chip_addx, const unsigned int data)
1372{
1373 int err;
1374
1375
1376 /* write the address, and if successful proceed to write data */
1377 err = chipio_write_address(codec, chip_addx);
1378 if (err < 0)
1379 goto exit;
1380
1381 err = chipio_write_data(codec, data);
1382 if (err < 0)
1383 goto exit;
1384
1385exit:
1386 return err;
1387}
1388
d5c21b88
IM		 1389/*
1390 * Write multiple values to the given address through the chip I/O widget.
1391 * protected by the Mutex
1392 */
01ef7dbf
IM		 1393static int chipio_write_multiple(struct hda_codec *codec,
1394 u32 chip_addx,
1395 const u32 *data,
1396 unsigned int count)
1397{
1398 struct ca0132_spec *spec = codec->spec;
1399 int status;
1400
1401 mutex_lock(&spec->chipio_mutex);
4861af80 1402 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1403 if (status < 0)
1404 goto error;
1405
1406 status = chipio_write_data_multiple(codec, data, count);
1407error:
1408 mutex_unlock(&spec->chipio_mutex);
1409
1410 return status;
1411}
1412
1413/*
1414 * Read the given address through the chip I/O widget
1415 * protected by the Mutex
1416 */
1417static int chipio_read(struct hda_codec *codec,
1418 unsigned int chip_addx, unsigned int *data)
1419{
1420 struct ca0132_spec *spec = codec->spec;
1421 int err;
1422
1423 mutex_lock(&spec->chipio_mutex);
1424
1425 /* write the address, and if successful proceed to write data */
1426 err = chipio_write_address(codec, chip_addx);
1427 if (err < 0)
1428 goto exit;
1429
1430 err = chipio_read_data(codec, data);
1431 if (err < 0)
1432 goto exit;
1433
1434exit:
1435 mutex_unlock(&spec->chipio_mutex);
1436 return err;
1437}
1438
d5c21b88
IM		 1439/*
1440 * Set chip control flags through the chip I/O widget.
1441 */
01ef7dbf
IM		 1442static void chipio_set_control_flag(struct hda_codec *codec,
1443 enum control_flag_id flag_id,
1444 bool flag_state)
1445{
1446 unsigned int val;
1447 unsigned int flag_bit;
1448
1449 flag_bit = (flag_state ? 1 : 0);
1450 val = (flag_bit << 7) | (flag_id);
1451 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1452 VENDOR_CHIPIO_FLAG_SET, val);
1453}
1454
d5c21b88
IM		 1455/*
1456 * Set chip parameters through the chip I/O widget.
1457 */
01ef7dbf
IM		 1458static void chipio_set_control_param(struct hda_codec *codec,
1459 enum control_param_id param_id, int param_val)
1460{
1461 struct ca0132_spec *spec = codec->spec;
1462 int val;
1463
1464 if ((param_id < 32) && (param_val < 8)) {
1465 val = (param_val << 5) | (param_id);
1466 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1467 VENDOR_CHIPIO_PARAM_SET, val);
1468 } else {
1469 mutex_lock(&spec->chipio_mutex);
1470 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1471 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1472 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1473 param_id);
1474 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1475 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1476 param_val);
1477 }
1478 mutex_unlock(&spec->chipio_mutex);
1479 }
1480}
1481
009b8f97
CM		 1482/*
1483 * Set chip parameters through the chip I/O widget. NO MUTEX.
1484 */
1485static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1486 enum control_param_id param_id, int param_val)
1487{
1488 int val;
1489
1490 if ((param_id < 32) && (param_val < 8)) {
1491 val = (param_val << 5) | (param_id);
1492 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1493 VENDOR_CHIPIO_PARAM_SET, val);
1494 } else {
1495 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1496 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1497 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1498 param_id);
1499 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1500 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1501 param_val);
1502 }
1503 }
1504}
38ba69ff
CM		 1505/*
1506 * Connect stream to a source point, and then connect
1507 * that source point to a destination point.
1508 */
1509static void chipio_set_stream_source_dest(struct hda_codec *codec,
1510 int streamid, int source_point, int dest_point)
1511{
1512 chipio_set_control_param_no_mutex(codec,
1513 CONTROL_PARAM_STREAM_ID, streamid);
1514 chipio_set_control_param_no_mutex(codec,
1515 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1516 chipio_set_control_param_no_mutex(codec,
1517 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1518}
1519
1520/*
1521 * Set number of channels in the selected stream.
1522 */
1523static void chipio_set_stream_channels(struct hda_codec *codec,
1524 int streamid, unsigned int channels)
1525{
1526 chipio_set_control_param_no_mutex(codec,
1527 CONTROL_PARAM_STREAM_ID, streamid);
1528 chipio_set_control_param_no_mutex(codec,
1529 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1530}
009b8f97
CM		 1531
1532/*
1533 * Enable/Disable audio stream.
1534 */
1535static void chipio_set_stream_control(struct hda_codec *codec,
1536 int streamid, int enable)
1537{
1538 chipio_set_control_param_no_mutex(codec,
1539 CONTROL_PARAM_STREAM_ID, streamid);
1540 chipio_set_control_param_no_mutex(codec,
1541 CONTROL_PARAM_STREAM_CONTROL, enable);
1542}
1543
38ba69ff
CM		 1544
1545/*
1546 * Set sampling rate of the connection point. NO MUTEX.
1547 */
1548static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1549 int connid, enum ca0132_sample_rate rate)
1550{
1551 chipio_set_control_param_no_mutex(codec,
1552 CONTROL_PARAM_CONN_POINT_ID, connid);
1553 chipio_set_control_param_no_mutex(codec,
1554 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1555}
1556
d5c21b88
IM		 1557/*
1558 * Set sampling rate of the connection point.
1559 */
01ef7dbf
IM		 1560static void chipio_set_conn_rate(struct hda_codec *codec,
1561 int connid, enum ca0132_sample_rate rate)
1562{
1563 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1564 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1565 rate);
1566}
1567
b9b41345
CM		 1568/*
1569 * Writes to the 8051's internal address space directly instead of indirectly,
1570 * giving access to the special function registers located at addresses
1571 * 0x80-0xFF.
1572 */
1573static void chipio_8051_write_direct(struct hda_codec *codec,
1574 unsigned int addr, unsigned int data)
1575{
1576 unsigned int verb;
1577
1578 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1579 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1580}
1581
d5c21b88
IM		 1582/*
1583 * Enable clocks.
1584 */
01ef7dbf
IM		 1585static void chipio_enable_clocks(struct hda_codec *codec)
1586{
1587 struct ca0132_spec *spec = codec->spec;
1588
1589 mutex_lock(&spec->chipio_mutex);
1590 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1591 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1592 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1593 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1594 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1595 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1596 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1597 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1598 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1599 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1600 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1601 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1602 mutex_unlock(&spec->chipio_mutex);
1603}
1604
1605/*
1606 * CA0132 DSP IO stuffs
1607 */
1608static int dspio_send(struct hda_codec *codec, unsigned int reg,
1609 unsigned int data)
1610{
b645d796 1611 int res;
6d67530e 1612 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1613
1614 /* send bits of data specified by reg to dsp */
1615 do {
1616 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1617 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1618 return res;
6d67530e
IM		 1619 msleep(20);
1620 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1621
1622 return -EIO;
1623}
1624
d5c21b88
IM		 1625/*
1626 * Wait for DSP to be ready for commands
1627 */
01ef7dbf
IM		 1628static void dspio_write_wait(struct hda_codec *codec)
1629{
4861af80
IM		 1630 int status;
1631 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1632
01ef7dbf 1633 do {
4861af80
IM		 1634 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1635 VENDOR_DSPIO_STATUS, 0);
1636 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1637 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1638 break;
1639 msleep(1);
1640 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1641}
1642
d5c21b88
IM		 1643/*
1644 * Write SCP data to DSP
1645 */
01ef7dbf
IM		 1646static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1647{
1648 struct ca0132_spec *spec = codec->spec;
1649 int status;
1650
1651 dspio_write_wait(codec);
1652
1653 mutex_lock(&spec->chipio_mutex);
1654 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1655 scp_data & 0xffff);
1656 if (status < 0)
1657 goto error;
1658
1659 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1660 scp_data >> 16);
1661 if (status < 0)
1662 goto error;
1663
1664 /* OK, now check if the write itself has executed*/
1665 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1666 VENDOR_DSPIO_STATUS, 0);
1667error:
1668 mutex_unlock(&spec->chipio_mutex);
1669
1670 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1671 -EIO : 0;
1672}
1673
d5c21b88
IM		 1674/*
1675 * Write multiple SCP data to DSP
1676 */
01ef7dbf
IM		 1677static int dspio_write_multiple(struct hda_codec *codec,
1678 unsigned int *buffer, unsigned int size)
1679{
1680 int status = 0;
1681 unsigned int count;
1682
a16fbb85 1683 if (buffer == NULL)
01ef7dbf
IM		 1684 return -EINVAL;
1685
1686 count = 0;
1687 while (count < size) {
1688 status = dspio_write(codec, *buffer++);
1689 if (status != 0)
1690 break;
1691 count++;
1692 }
1693
1694 return status;
1695}
1696
a73d511c
IM		 1697static int dspio_read(struct hda_codec *codec, unsigned int *data)
1698{
1699 int status;
1700
1701 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1702 if (status == -EIO)
1703 return status;
1704
1705 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1706 if (status == -EIO ||
1707 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1708 return -EIO;
1709
1710 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1711 VENDOR_DSPIO_SCP_READ_DATA, 0);
1712
1713 return 0;
1714}
1715
1716static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1717 unsigned int *buf_size, unsigned int size_count)
1718{
1719 int status = 0;
1720 unsigned int size = *buf_size;
1721 unsigned int count;
1722 unsigned int skip_count;
1723 unsigned int dummy;
1724
a16fbb85 1725 if (buffer == NULL)
a73d511c
IM		 1726 return -1;
1727
1728 count = 0;
1729 while (count < size && count < size_count) {
1730 status = dspio_read(codec, buffer++);
1731 if (status != 0)
1732 break;
1733 count++;
1734 }
1735
1736 skip_count = count;
1737 if (status == 0) {
1738 while (skip_count < size) {
1739 status = dspio_read(codec, &dummy);
1740 if (status != 0)
1741 break;
1742 skip_count++;
1743 }
1744 }
1745 *buf_size = count;
1746
1747 return status;
1748}
1749
d5c21b88
IM		 1750/*
1751 * Construct the SCP header using corresponding fields
1752 */
01ef7dbf
IM		 1753static inline unsigned int
1754make_scp_header(unsigned int target_id, unsigned int source_id,
1755 unsigned int get_flag, unsigned int req,
1756 unsigned int device_flag, unsigned int resp_flag,
1757 unsigned int error_flag, unsigned int data_size)
1758{
1759 unsigned int header = 0;
1760
1761 header = (data_size & 0x1f) << 27;
1762 header |= (error_flag & 0x01) << 26;
1763 header |= (resp_flag & 0x01) << 25;
1764 header |= (device_flag & 0x01) << 24;
1765 header |= (req & 0x7f) << 17;
1766 header |= (get_flag & 0x01) << 16;
1767 header |= (source_id & 0xff) << 8;
1768 header |= target_id & 0xff;
1769
1770 return header;
1771}
1772
d5c21b88
IM		 1773/*
1774 * Extract corresponding fields from SCP header
1775 */
01ef7dbf
IM		 1776static inline void
1777extract_scp_header(unsigned int header,
1778 unsigned int *target_id, unsigned int *source_id,
1779 unsigned int *get_flag, unsigned int *req,
1780 unsigned int *device_flag, unsigned int *resp_flag,
1781 unsigned int *error_flag, unsigned int *data_size)
1782{
1783 if (data_size)
1784 *data_size = (header >> 27) & 0x1f;
1785 if (error_flag)
1786 *error_flag = (header >> 26) & 0x01;
1787 if (resp_flag)
1788 *resp_flag = (header >> 25) & 0x01;
1789 if (device_flag)
1790 *device_flag = (header >> 24) & 0x01;
1791 if (req)
1792 *req = (header >> 17) & 0x7f;
1793 if (get_flag)
1794 *get_flag = (header >> 16) & 0x01;
1795 if (source_id)
1796 *source_id = (header >> 8) & 0xff;
1797 if (target_id)
1798 *target_id = header & 0xff;
1799}
1800
1801#define SCP_MAX_DATA_WORDS (16)
1802
1803/* Structure to contain any SCP message */
1804struct scp_msg {
1805 unsigned int hdr;
1806 unsigned int data[SCP_MAX_DATA_WORDS];
1807};
1808
a73d511c
IM		 1809static void dspio_clear_response_queue(struct hda_codec *codec)
1810{
1811 unsigned int dummy = 0;
1812 int status = -1;
1813
1814 /* clear all from the response queue */
1815 do {
1816 status = dspio_read(codec, &dummy);
1817 } while (status == 0);
1818}
1819
1820static int dspio_get_response_data(struct hda_codec *codec)
1821{
1822 struct ca0132_spec *spec = codec->spec;
1823 unsigned int data = 0;
1824 unsigned int count;
1825
1826 if (dspio_read(codec, &data) < 0)
1827 return -EIO;
1828
1829 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1830 spec->scp_resp_header = data;
1831 spec->scp_resp_count = data >> 27;
1832 count = spec->wait_num_data;
1833 dspio_read_multiple(codec, spec->scp_resp_data,
1834 &spec->scp_resp_count, count);
1835 return 0;
1836 }
1837
1838 return -EIO;
1839}
1840
d5c21b88
IM		 1841/*
1842 * Send SCP message to DSP
1843 */
01ef7dbf
IM		 1844static int dspio_send_scp_message(struct hda_codec *codec,
1845 unsigned char *send_buf,
1846 unsigned int send_buf_size,
1847 unsigned char *return_buf,
1848 unsigned int return_buf_size,
1849 unsigned int *bytes_returned)
1850{
1851 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1852 int status = -1;
1853 unsigned int scp_send_size = 0;
1854 unsigned int total_size;
1855 bool waiting_for_resp = false;
1856 unsigned int header;
1857 struct scp_msg *ret_msg;
1858 unsigned int resp_src_id, resp_target_id;
1859 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1860
1861 if (bytes_returned)
1862 *bytes_returned = 0;
1863
1864 /* get scp header from buffer */
1865 header = *((unsigned int *)send_buf);
1866 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1867 &device_flag, NULL, NULL, &data_size);
1868 scp_send_size = data_size + 1;
1869 total_size = (scp_send_size * 4);
1870
1871 if (send_buf_size < total_size)
1872 return -EINVAL;
1873
1874 if (get_flag || device_flag) {
1875 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1876 return -EINVAL;
1877
1878 spec->wait_scp_header = *((unsigned int *)send_buf);
1879
1880 /* swap source id with target id */
1881 resp_target_id = src_id;
1882 resp_src_id = target_id;
1883 spec->wait_scp_header &= 0xffff0000;
1884 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1885 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1886 spec->wait_scp = 1;
1887 waiting_for_resp = true;
1888 }
1889
1890 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1891 scp_send_size);
1892 if (status < 0) {
1893 spec->wait_scp = 0;
1894 return status;
1895 }
1896
1897 if (waiting_for_resp) {
6d67530e 1898 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1899 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1900 do {
1901 msleep(20);
6d67530e 1902 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1903 waiting_for_resp = false;
6d67530e 1904 if (!spec->wait_scp) {
01ef7dbf
IM		 1905 ret_msg = (struct scp_msg *)return_buf;
1906 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1907 memcpy(&ret_msg->data, spec->scp_resp_data,
1908 spec->wait_num_data);
1909 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1910 status = 0;
1911 } else {
1912 status = -EIO;
1913 }
1914 spec->wait_scp = 0;
1915 }
1916
1917 return status;
1918}
1919
d5c21b88
IM		 1920/**
1921 * Prepare and send the SCP message to DSP
1922 * @codec: the HDA codec
1923 * @mod_id: ID of the DSP module to send the command
1924 * @req: ID of request to send to the DSP module
1925 * @dir: SET or GET
1926 * @data: pointer to the data to send with the request, request specific
1927 * @len: length of the data, in bytes
1928 * @reply: point to the buffer to hold data returned for a reply
1929 * @reply_len: length of the reply buffer returned from GET
1930 *
1931 * Returns zero or a negative error code.
1932 */
01ef7dbf 1933static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1934 int mod_id, int src_id, int req, int dir, const void *data,
1935 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1936{
1937 int status = 0;
1938 struct scp_msg scp_send, scp_reply;
1939 unsigned int ret_bytes, send_size, ret_size;
1940 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1941 unsigned int reply_data_size;
1942
1943 memset(&scp_send, 0, sizeof(scp_send));
1944 memset(&scp_reply, 0, sizeof(scp_reply));
1945
1946 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1947 return -EINVAL;
1948
1949 if (dir == SCP_GET && reply == NULL) {
4e76a883 1950 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1951 return -EINVAL;
1952 }
1953
1954 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1955 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1956 return -EINVAL;
1957 }
1958
447fd8e9 1959 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1960 0, 0, 0, len/sizeof(unsigned int));
1961 if (data != NULL && len > 0) {
1962 len = min((unsigned int)(sizeof(scp_send.data)), len);
1963 memcpy(scp_send.data, data, len);
1964 }
1965
1966 ret_bytes = 0;
1967 send_size = sizeof(unsigned int) + len;
1968 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1969 send_size, (unsigned char *)&scp_reply,
1970 sizeof(scp_reply), &ret_bytes);
1971
1972 if (status < 0) {
4e76a883 1973 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1974 return status;
1975 }
1976
1977 /* extract send and reply headers members */
1978 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1979 NULL, NULL, NULL, NULL, NULL);
1980 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1981 &reply_resp_flag, &reply_error_flag,
1982 &reply_data_size);
1983
1984 if (!send_get_flag)
1985 return 0;
1986
1987 if (reply_resp_flag && !reply_error_flag) {
1988 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1989 / sizeof(unsigned int);
1990
1991 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1992 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1993 return -EINVAL;
1994 } else if (ret_size != reply_data_size) {
4e76a883 1995 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1996 return -EINVAL;
46a049da
AB		 1997 } else if (!reply) {
1998 codec_dbg(codec, "NULL reply\n");
1999 return -EINVAL;
01ef7dbf
IM		 2000 } else {
2001 *reply_len = ret_size*sizeof(unsigned int);
2002 memcpy(reply, scp_reply.data, *reply_len);
2003 }
2004 } else {
4e76a883 2005 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 2006 return -EIO;
2007 }
2008
2009 return status;
2010}
2011
5aaca44d
IM		 2012/*
2013 * Set DSP parameters
2014 */
2015static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 2016 int src_id, int req, const void *data, unsigned int len)
5aaca44d 2017{
447fd8e9
CM		 2018 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2019 NULL);
5aaca44d
IM		 2020}
2021
2022static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 2023 int req, const unsigned int data)
5aaca44d 2024{
447fd8e9
CM		 2025 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2026 sizeof(unsigned int));
2027}
2028
2029static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2030 int req, const unsigned int data)
2031{
2032 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2033 sizeof(unsigned int));
5aaca44d
IM		 2034}
2035
d5c21b88
IM		 2036/*
2037 * Allocate a DSP DMA channel via an SCP message
2038 */
01ef7dbf
IM		 2039static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2040{
2041 int status = 0;
2042 unsigned int size = sizeof(dma_chan);
2043
4e76a883 2044 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 2045 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2046 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2047 dma_chan, &size);
01ef7dbf
IM		 2048
2049 if (status < 0) {
4e76a883 2050 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2051 return status;
2052 }
2053
2054 if ((*dma_chan + 1) == 0) {
4e76a883 2055 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 2056 return -EBUSY;
2057 }
2058
4e76a883
TI		 2059 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2060 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 2061
2062 return status;
2063}
2064
d5c21b88
IM		 2065/*
2066 * Free a DSP DMA via an SCP message
2067 */
01ef7dbf
IM		 2068static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2069{
2070 int status = 0;
2071 unsigned int dummy = 0;
2072
4e76a883
TI		 2073 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2074 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 2075
447fd8e9
CM		 2076 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2077 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2078 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 2079
2080 if (status < 0) {
4e76a883 2081 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2082 return status;
2083 }
2084
4e76a883 2085 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 2086
2087 return status;
2088}
2089
2090/*
d5c21b88 2091 * (Re)start the DSP
01ef7dbf
IM		 2092 */
2093static int dsp_set_run_state(struct hda_codec *codec)
2094{
2095 unsigned int dbg_ctrl_reg;
2096 unsigned int halt_state;
2097 int err;
2098
2099 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2100 if (err < 0)
2101 return err;
2102
2103 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2104 DSP_DBGCNTL_STATE_LOBIT;
2105
2106 if (halt_state != 0) {
2107 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2108 DSP_DBGCNTL_SS_MASK);
2109 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2110 dbg_ctrl_reg);
2111 if (err < 0)
2112 return err;
2113
2114 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2115 DSP_DBGCNTL_EXEC_MASK;
2116 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2117 dbg_ctrl_reg);
2118 if (err < 0)
2119 return err;
2120 }
2121
2122 return 0;
2123}
2124
d5c21b88
IM		 2125/*
2126 * Reset the DSP
2127 */
01ef7dbf
IM		 2128static int dsp_reset(struct hda_codec *codec)
2129{
2130 unsigned int res;
2131 int retry = 20;
2132
4e76a883 2133 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 2134 do {
2135 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2136 retry--;
2137 } while (res == -EIO && retry);
2138
2139 if (!retry) {
4e76a883 2140 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 2141 return -EIO;
2142 }
2143
2144 return 0;
2145}
2146
d5c21b88
IM		 2147/*
2148 * Convert chip address to DSP address
2149 */
01ef7dbf
IM		 2150static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2151 bool *code, bool *yram)
2152{
2153 *code = *yram = false;
2154
2155 if (UC_RANGE(chip_addx, 1)) {
2156 *code = true;
2157 return UC_OFF(chip_addx);
2158 } else if (X_RANGE_ALL(chip_addx, 1)) {
2159 return X_OFF(chip_addx);
2160 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2161 *yram = true;
2162 return Y_OFF(chip_addx);
2163 }
2164
4a8b89f9 2165 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2166}
2167
d5c21b88
IM		 2168/*
2169 * Check if the DSP DMA is active
2170 */
01ef7dbf
IM		 2171static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2172{
2173 unsigned int dma_chnlstart_reg;
2174
2175 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2176
2177 return ((dma_chnlstart_reg & (1 <<
2178 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2179}
2180
2181static int dsp_dma_setup_common(struct hda_codec *codec,
2182 unsigned int chip_addx,
2183 unsigned int dma_chan,
2184 unsigned int port_map_mask,
2185 bool ovly)
2186{
2187 int status = 0;
2188 unsigned int chnl_prop;
2189 unsigned int dsp_addx;
2190 unsigned int active;
2191 bool code, yram;
2192
4e76a883 2193 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2194
2195 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2196 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2197 return -EINVAL;
2198 }
2199
2200 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2201 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2202 return -EBUSY;
2203 }
2204
2205 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2206
2207 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2208 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2209 return -ENXIO;
2210 }
2211
2212 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2213 active = 0;
2214
4e76a883 2215 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2216
2217 if (ovly) {
2218 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2219 &chnl_prop);
2220
2221 if (status < 0) {
4e76a883 2222 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2223 return status;
2224 }
4e76a883 2225 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2226 }
2227
2228 if (!code)
2229 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2230 else
2231 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2232
2233 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2234
2235 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2236 if (status < 0) {
4e76a883 2237 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2238 return status;
2239 }
4e76a883 2240 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2241
2242 if (ovly) {
2243 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2244 &active);
2245
2246 if (status < 0) {
4e76a883 2247 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2248 return status;
2249 }
4e76a883 2250 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2251 }
2252
2253 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2254 DSPDMAC_ACTIVE_AAR_MASK;
2255
2256 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2257 if (status < 0) {
4e76a883 2258 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2259 return status;
2260 }
2261
4e76a883 2262 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2263
2264 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2265 port_map_mask);
2266 if (status < 0) {
4e76a883 2267 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2268 return status;
2269 }
4e76a883 2270 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2271
2272 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2273 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2274 if (status < 0) {
4e76a883 2275 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2276 return status;
2277 }
4e76a883 2278 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2279
4e76a883 2280 codec_dbg(codec,
01ef7dbf
IM		 2281 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2282 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2283 chip_addx, dsp_addx, dma_chan,
2284 port_map_mask, chnl_prop, active);
2285
4e76a883 2286 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2287
2288 return 0;
2289}
2290
d5c21b88
IM		 2291/*
2292 * Setup the DSP DMA per-transfer-specific registers
2293 */
01ef7dbf
IM		 2294static int dsp_dma_setup(struct hda_codec *codec,
2295 unsigned int chip_addx,
2296 unsigned int count,
2297 unsigned int dma_chan)
2298{
2299 int status = 0;
2300 bool code, yram;
2301 unsigned int dsp_addx;
2302 unsigned int addr_field;
2303 unsigned int incr_field;
2304 unsigned int base_cnt;
2305 unsigned int cur_cnt;
2306 unsigned int dma_cfg = 0;
2307 unsigned int adr_ofs = 0;
2308 unsigned int xfr_cnt = 0;
2309 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2310 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2311
4e76a883 2312 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2313
2314 if (count > max_dma_count) {
4e76a883 2315 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2316 return -EINVAL;
2317 }
2318
2319 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2320 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2321 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2322 return -ENXIO;
2323 }
2324
4e76a883 2325 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2326
2327 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2328 incr_field = 0;
2329
2330 if (!code) {
2331 addr_field <<= 1;
2332 if (yram)
2333 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2334
2335 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2336 }
2337
2338 dma_cfg = addr_field + incr_field;
2339 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2340 dma_cfg);
2341 if (status < 0) {
4e76a883 2342 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2343 return status;
2344 }
4e76a883 2345 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2346
2347 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2348 (code ? 0 : 1));
2349
2350 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2351 adr_ofs);
2352 if (status < 0) {
4e76a883 2353 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2354 return status;
2355 }
4e76a883 2356 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2357
2358 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2359
2360 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2361
2362 xfr_cnt = base_cnt | cur_cnt;
2363
2364 status = chipio_write(codec,
2365 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2366 if (status < 0) {
4e76a883 2367 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2368 return status;
2369 }
4e76a883 2370 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2371
4e76a883 2372 codec_dbg(codec,
01ef7dbf
IM		 2373 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2374 "ADROFS=0x%x, XFRCNT=0x%x\n",
2375 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2376
4e76a883 2377 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2378
2379 return 0;
2380}
2381
d5c21b88
IM		 2382/*
2383 * Start the DSP DMA
2384 */
01ef7dbf
IM		 2385static int dsp_dma_start(struct hda_codec *codec,
2386 unsigned int dma_chan, bool ovly)
2387{
2388 unsigned int reg = 0;
2389 int status = 0;
2390
4e76a883 2391 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2392
2393 if (ovly) {
2394 status = chipio_read(codec,
2395 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2396
2397 if (status < 0) {
4e76a883 2398 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2399 return status;
2400 }
4e76a883 2401 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2402
2403 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2404 DSPDMAC_CHNLSTART_DIS_MASK);
2405 }
2406
2407 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2408 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2409 if (status < 0) {
4e76a883 2410 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2411 return status;
2412 }
4e76a883 2413 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2414
2415 return status;
2416}
2417
d5c21b88
IM		 2418/*
2419 * Stop the DSP DMA
2420 */
01ef7dbf
IM		 2421static int dsp_dma_stop(struct hda_codec *codec,
2422 unsigned int dma_chan, bool ovly)
2423{
2424 unsigned int reg = 0;
2425 int status = 0;
2426
4e76a883 2427 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2428
2429 if (ovly) {
2430 status = chipio_read(codec,
2431 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2432
2433 if (status < 0) {
4e76a883 2434 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2435 return status;
2436 }
4e76a883 2437 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2438 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2439 DSPDMAC_CHNLSTART_DIS_MASK);
2440 }
2441
2442 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2443 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2444 if (status < 0) {
4e76a883 2445 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2446 return status;
2447 }
4e76a883 2448 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2449
2450 return status;
2451}
2452
d5c21b88
IM		 2453/**
2454 * Allocate router ports
2455 *
2456 * @codec: the HDA codec
2457 * @num_chans: number of channels in the stream
2458 * @ports_per_channel: number of ports per channel
2459 * @start_device: start device
2460 * @port_map: pointer to the port list to hold the allocated ports
2461 *
2462 * Returns zero or a negative error code.
2463 */
01ef7dbf
IM		 2464static int dsp_allocate_router_ports(struct hda_codec *codec,
2465 unsigned int num_chans,
2466 unsigned int ports_per_channel,
2467 unsigned int start_device,
2468 unsigned int *port_map)
2469{
2470 int status = 0;
2471 int res;
2472 u8 val;
2473
2474 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2475 if (status < 0)
2476 return status;
2477
2478 val = start_device << 6;
2479 val |= (ports_per_channel - 1) << 4;
2480 val |= num_chans - 1;
2481
2482 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2483 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2484 val);
2485
2486 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2487 VENDOR_CHIPIO_PORT_ALLOC_SET,
2488 MEM_CONNID_DSP);
2489
2490 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2491 if (status < 0)
2492 return status;
2493
2494 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2495 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2496
2497 *port_map = res;
2498
2499 return (res < 0) ? res : 0;
2500}
2501
d5c21b88
IM		 2502/*
2503 * Free router ports
2504 */
01ef7dbf
IM		 2505static int dsp_free_router_ports(struct hda_codec *codec)
2506{
2507 int status = 0;
2508
2509 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2510 if (status < 0)
2511 return status;
2512
2513 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2514 VENDOR_CHIPIO_PORT_FREE_SET,
2515 MEM_CONNID_DSP);
2516
2517 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2518
2519 return status;
2520}
2521
d5c21b88
IM		 2522/*
2523 * Allocate DSP ports for the download stream
2524 */
01ef7dbf
IM		 2525static int dsp_allocate_ports(struct hda_codec *codec,
2526 unsigned int num_chans,
2527 unsigned int rate_multi, unsigned int *port_map)
2528{
2529 int status;
2530
4e76a883 2531 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2532
2533 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2534 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2535 return -EINVAL;
2536 }
2537
2538 status = dsp_allocate_router_ports(codec, num_chans,
2539 rate_multi, 0, port_map);
2540
4e76a883 2541 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2542
2543 return status;
2544}
2545
01ef7dbf
IM		 2546static int dsp_allocate_ports_format(struct hda_codec *codec,
2547 const unsigned short fmt,
2548 unsigned int *port_map)
2549{
2550 int status;
2551 unsigned int num_chans;
2552
2553 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2554 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2555 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2556
2557 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2558 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2559 return -EINVAL;
2560 }
2561
2562 num_chans = get_hdafmt_chs(fmt) + 1;
2563
2564 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2565
2566 return status;
2567}
2568
d5c21b88
IM		 2569/*
2570 * free DSP ports
2571 */
2572static int dsp_free_ports(struct hda_codec *codec)
2573{
2574 int status;
2575
4e76a883 2576 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2577
2578 status = dsp_free_router_ports(codec);
2579 if (status < 0) {
4e76a883 2580 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2581 return status;
2582 }
4e76a883 2583 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2584
2585 return status;
2586}
2587
01ef7dbf
IM		 2588/*
2589 * HDA DMA engine stuffs for DSP code download
2590 */
2591struct dma_engine {
2592 struct hda_codec *codec;
2593 unsigned short m_converter_format;
2594 struct snd_dma_buffer *dmab;
2595 unsigned int buf_size;
2596};
2597
2598
2599enum dma_state {
2600 DMA_STATE_STOP = 0,
2601 DMA_STATE_RUN = 1
2602};
2603
6194b99d 2604static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2605 unsigned int sample_rate,
2606 unsigned short channels,
01ef7dbf
IM		 2607 unsigned short *hda_format)
2608{
2609 unsigned int format_val;
2610
b7d023e1
TI		 2611 format_val = snd_hdac_calc_stream_format(sample_rate,
2612 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2613
2614 if (hda_format)
2615 *hda_format = (unsigned short)format_val;
2616
2617 return 0;
2618}
2619
d5c21b88
IM		 2620/*
2621 * Reset DMA for DSP download
2622 */
01ef7dbf
IM		 2623static int dma_reset(struct dma_engine *dma)
2624{
2625 struct hda_codec *codec = dma->codec;
2626 struct ca0132_spec *spec = codec->spec;
2627 int status;
2628
b3667bd7 2629 if (dma->dmab->area)
01ef7dbf
IM		 2630 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2631
2632 status = snd_hda_codec_load_dsp_prepare(codec,
2633 dma->m_converter_format,
2634 dma->buf_size,
2635 dma->dmab);
2636 if (status < 0)
2637 return status;
2638 spec->dsp_stream_id = status;
2639 return 0;
2640}
2641
2642static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2643{
01ef7dbf
IM		 2644 bool cmd;
2645
01ef7dbf
IM		 2646 switch (state) {
2647 case DMA_STATE_STOP:
2648 cmd = false;
2649 break;
2650 case DMA_STATE_RUN:
2651 cmd = true;
2652 break;
2653 default:
c41999a2
DH		 2654 return 0;
2655 }
01ef7dbf
IM		 2656
2657 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2658 return 0;
95c6e9cb
IM		 2659}
2660
01ef7dbf
IM		 2661static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2662{
2663 return dma->dmab->bytes;
2664}
95c6e9cb 2665
01ef7dbf
IM		 2666static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2667{
2668 return dma->dmab->area;
2669}
95c6e9cb 2670
01ef7dbf
IM		 2671static int dma_xfer(struct dma_engine *dma,
2672 const unsigned int *data,
2673 unsigned int count)
2674{
2675 memcpy(dma->dmab->area, data, count);
2676 return 0;
2677}
95c6e9cb 2678
01ef7dbf
IM		 2679static void dma_get_converter_format(
2680 struct dma_engine *dma,
2681 unsigned short *format)
2682{
2683 if (format)
2684 *format = dma->m_converter_format;
2685}
95c6e9cb 2686
01ef7dbf 2687static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2688{
01ef7dbf 2689 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2690
01ef7dbf 2691 return spec->dsp_stream_id;
95c6e9cb
IM		 2692}
2693
01ef7dbf
IM		 2694struct dsp_image_seg {
2695 u32 magic;
2696 u32 chip_addr;
2697 u32 count;
2698 u32 data[0];
2699};
2700
2701static const u32 g_magic_value = 0x4c46584d;
2702static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2703
2704static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2705{
01ef7dbf
IM		 2706 return p->magic == g_magic_value;
2707}
95c6e9cb 2708
01ef7dbf
IM		 2709static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2710{
2711 return g_chip_addr_magic_value == p->chip_addr;
2712}
95c6e9cb 2713
01ef7dbf
IM		 2714static bool is_last(const struct dsp_image_seg *p)
2715{
2716 return p->count == 0;
2717}
95c6e9cb 2718
01ef7dbf
IM		 2719static size_t dsp_sizeof(const struct dsp_image_seg *p)
2720{
2721 return sizeof(*p) + p->count*sizeof(u32);
2722}
2723
2724static const struct dsp_image_seg *get_next_seg_ptr(
2725 const struct dsp_image_seg *p)
2726{
2727 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2728}
2729
2730/*
01ef7dbf 2731 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2732 */
8ae3124b 2733#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2734
d5c21b88
IM		 2735/*
2736 * Program a list of address/data pairs via the ChipIO widget.
2737 * The segment data is in the format of successive pairs of words.
2738 * These are repeated as indicated by the segment's count field.
2739 */
01ef7dbf
IM		 2740static int dspxfr_hci_write(struct hda_codec *codec,
2741 const struct dsp_image_seg *fls)
95c6e9cb 2742{
01ef7dbf
IM		 2743 int status;
2744 const u32 *data;
2745 unsigned int count;
95c6e9cb 2746
01ef7dbf 2747 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2748 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2749 return -EINVAL;
95c6e9cb
IM		 2750 }
2751
01ef7dbf
IM		 2752 count = fls->count;
2753 data = (u32 *)(fls->data);
2754 while (count >= 2) {
2755 status = chipio_write(codec, data[0], data[1]);
2756 if (status < 0) {
4e76a883 2757 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2758 return status;
2759 }
2760 count -= 2;
2761 data += 2;
2762 }
2763 return 0;
95c6e9cb
IM		 2764}
2765
d5c21b88
IM		 2766/**
2767 * Write a block of data into DSP code or data RAM using pre-allocated
2768 * DMA engine.
2769 *
2770 * @codec: the HDA codec
2771 * @fls: pointer to a fast load image
2772 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2773 * no relocation
2774 * @dma_engine: pointer to DMA engine to be used for DSP download
2775 * @dma_chan: The number of DMA channels used for DSP download
2776 * @port_map_mask: port mapping
2777 * @ovly: TRUE if overlay format is required
2778 *
2779 * Returns zero or a negative error code.
2780 */
01ef7dbf
IM		 2781static int dspxfr_one_seg(struct hda_codec *codec,
2782 const struct dsp_image_seg *fls,
2783 unsigned int reloc,
2784 struct dma_engine *dma_engine,
2785 unsigned int dma_chan,
2786 unsigned int port_map_mask,
2787 bool ovly)
95c6e9cb 2788{
406261ce 2789 int status = 0;
01ef7dbf
IM		 2790 bool comm_dma_setup_done = false;
2791 const unsigned int *data;
2792 unsigned int chip_addx;
2793 unsigned int words_to_write;
2794 unsigned int buffer_size_words;
2795 unsigned char *buffer_addx;
2796 unsigned short hda_format;
2797 unsigned int sample_rate_div;
2798 unsigned int sample_rate_mul;
2799 unsigned int num_chans;
2800 unsigned int hda_frame_size_words;
2801 unsigned int remainder_words;
2802 const u32 *data_remainder;
2803 u32 chip_addx_remainder;
2804 unsigned int run_size_words;
2805 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2806 unsigned long timeout;
2807 bool dma_active;
01ef7dbf
IM		 2808
2809 if (fls == NULL)
2810 return -EINVAL;
2811 if (is_hci_prog_list_seg(fls)) {
2812 hci_write = fls;
2813 fls = get_next_seg_ptr(fls);
2814 }
95c6e9cb 2815
01ef7dbf 2816 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2817 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2818 return dspxfr_hci_write(codec, hci_write);
2819 }
95c6e9cb 2820
01ef7dbf 2821 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2822 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2823 return -EINVAL;
95c6e9cb
IM		 2824 }
2825
01ef7dbf
IM		 2826 data = fls->data;
2827 chip_addx = fls->chip_addr,
2828 words_to_write = fls->count;
2829
2830 if (!words_to_write)
2831 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2832 if (reloc)
2833 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2834
2835 if (!UC_RANGE(chip_addx, words_to_write) &&
2836 !X_RANGE_ALL(chip_addx, words_to_write) &&
2837 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2838 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2839 return -EINVAL;
95c6e9cb
IM		 2840 }
2841
01ef7dbf
IM		 2842 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2843 sizeof(u32);
2844
2845 buffer_addx = dma_get_buffer_addr(dma_engine);
2846
2847 if (buffer_addx == NULL) {
4e76a883 2848 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2849 return -EINVAL;
2850 }
2851
2852 dma_get_converter_format(dma_engine, &hda_format);
2853 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2854 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2855 num_chans = get_hdafmt_chs(hda_format) + 1;
2856
2857 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2858 (num_chans * sample_rate_mul / sample_rate_div));
2859
3bc085a1 2860 if (hda_frame_size_words == 0) {
4e76a883 2861 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2862 return -EINVAL;
2863 }
2864
01ef7dbf
IM		 2865 buffer_size_words = min(buffer_size_words,
2866 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2867 65536 : 32768));
2868 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2869 codec_dbg(codec,
01ef7dbf
IM		 2870 "chpadr=0x%08x frmsz=%u nchan=%u "
2871 "rate_mul=%u div=%u bufsz=%u\n",
2872 chip_addx, hda_frame_size_words, num_chans,
2873 sample_rate_mul, sample_rate_div, buffer_size_words);
2874
3bc085a1 2875 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2876 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2877 return -EINVAL;
2878 }
2879
2880 remainder_words = words_to_write % hda_frame_size_words;
2881 data_remainder = data;
2882 chip_addx_remainder = chip_addx;
2883
2884 data += remainder_words;
2885 chip_addx += remainder_words*sizeof(u32);
2886 words_to_write -= remainder_words;
2887
2888 while (words_to_write != 0) {
2889 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2890 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2891 words_to_write, run_size_words, remainder_words);
2892 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2893 if (!comm_dma_setup_done) {
2894 status = dsp_dma_stop(codec, dma_chan, ovly);
2895 if (status < 0)
425a7880 2896 return status;
01ef7dbf
IM		 2897 status = dsp_dma_setup_common(codec, chip_addx,
2898 dma_chan, port_map_mask, ovly);
2899 if (status < 0)
2900 return status;
2901 comm_dma_setup_done = true;
2902 }
2903
2904 status = dsp_dma_setup(codec, chip_addx,
2905 run_size_words, dma_chan);
2906 if (status < 0)
2907 return status;
2908 status = dsp_dma_start(codec, dma_chan, ovly);
2909 if (status < 0)
2910 return status;
2911 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2912 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2913 return -EIO;
2914 }
2915 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2916 if (status < 0)
2917 return status;
2918 if (remainder_words != 0) {
2919 status = chipio_write_multiple(codec,
2920 chip_addx_remainder,
2921 data_remainder,
2922 remainder_words);
b3667bd7
TI		 2923 if (status < 0)
2924 return status;
01ef7dbf
IM		 2925 remainder_words = 0;
2926 }
2927 if (hci_write) {
2928 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2929 if (status < 0)
2930 return status;
01ef7dbf
IM		 2931 hci_write = NULL;
2932 }
6d67530e
IM		 2933
2934 timeout = jiffies + msecs_to_jiffies(2000);
2935 do {
2936 dma_active = dsp_is_dma_active(codec, dma_chan);
2937 if (!dma_active)
01ef7dbf 2938 break;
6d67530e
IM		 2939 msleep(20);
2940 } while (time_before(jiffies, timeout));
2941 if (dma_active)
2942 break;
2943
4e76a883 2944 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2945 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2946 status = dma_reset(dma_engine);
01ef7dbf
IM		 2947
2948 if (status < 0)
2949 return status;
2950
2951 data += run_size_words;
2952 chip_addx += run_size_words*sizeof(u32);
2953 words_to_write -= run_size_words;
2954 }
2955
2956 if (remainder_words != 0) {
2957 status = chipio_write_multiple(codec, chip_addx_remainder,
2958 data_remainder, remainder_words);
2959 }
2960
2961 return status;
95c6e9cb
IM		 2962}
2963
d5c21b88
IM		 2964/**
2965 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2966 *
2967 * @codec: the HDA codec
2968 * @fls_data: pointer to a fast load image
2969 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2970 * no relocation
e97249dd 2971 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2972 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2973 * @ovly: TRUE if overlay format is required
2974 *
2975 * Returns zero or a negative error code.
2976 */
01ef7dbf
IM		 2977static int dspxfr_image(struct hda_codec *codec,
2978 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2979 unsigned int reloc,
2980 unsigned int sample_rate,
2981 unsigned short channels,
01ef7dbf 2982 bool ovly)
95c6e9cb
IM		 2983{
2984 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2985 int status;
2986 unsigned short hda_format = 0;
2987 unsigned int response;
2988 unsigned char stream_id = 0;
2989 struct dma_engine *dma_engine;
2990 unsigned int dma_chan;
2991 unsigned int port_map_mask;
2992
2993 if (fls_data == NULL)
2994 return -EINVAL;
2995
2996 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2997 if (!dma_engine)
2998 return -ENOMEM;
95c6e9cb 2999
01ef7dbf
IM		 3000 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3001 if (!dma_engine->dmab) {
549e8292
TI		 3002 kfree(dma_engine);
3003 return -ENOMEM;
01ef7dbf 3004 }
95c6e9cb 3005
01ef7dbf 3006 dma_engine->codec = codec;
6194b99d 3007 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 3008 dma_engine->m_converter_format = hda_format;
3009 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3010 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3011
8ae3124b 3012 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 3013
3014 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3015 hda_format, &response);
3016
3017 if (status < 0) {
4e76a883 3018 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 3019 goto exit;
3020 }
3021
3022 status = snd_hda_codec_load_dsp_prepare(codec,
3023 dma_engine->m_converter_format,
3024 dma_engine->buf_size,
3025 dma_engine->dmab);
3026 if (status < 0)
95c6e9cb 3027 goto exit;
01ef7dbf
IM		 3028 spec->dsp_stream_id = status;
3029
3030 if (ovly) {
3031 status = dspio_alloc_dma_chan(codec, &dma_chan);
3032 if (status < 0) {
4e76a883 3033 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 3034 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 3035 goto exit;
3036 }
3037 }
95c6e9cb 3038
01ef7dbf
IM		 3039 port_map_mask = 0;
3040 status = dsp_allocate_ports_format(codec, hda_format,
3041 &port_map_mask);
3042 if (status < 0) {
4e76a883 3043 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 3044 goto exit;
3045 }
3046
3047 stream_id = dma_get_stream_id(dma_engine);
3048 status = codec_set_converter_stream_channel(codec,
3049 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3050 if (status < 0) {
4e76a883 3051 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 3052 goto exit;
3053 }
3054
3055 while ((fls_data != NULL) && !is_last(fls_data)) {
3056 if (!is_valid(fls_data)) {
4e76a883 3057 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 3058 status = -EINVAL;
3059 goto exit;
3060 }
3061 status = dspxfr_one_seg(codec, fls_data, reloc,
3062 dma_engine, dma_chan,
3063 port_map_mask, ovly);
3064 if (status < 0)
3065 break;
3066
3067 if (is_hci_prog_list_seg(fls_data))
3068 fls_data = get_next_seg_ptr(fls_data);
3069
3070 if ((fls_data != NULL) && !is_last(fls_data))
3071 fls_data = get_next_seg_ptr(fls_data);
3072 }
3073
3074 if (port_map_mask != 0)
3075 status = dsp_free_ports(codec);
3076
3077 if (status < 0)
95c6e9cb
IM		 3078 goto exit;
3079
01ef7dbf
IM		 3080 status = codec_set_converter_stream_channel(codec,
3081 WIDGET_CHIP_CTRL, 0, 0, &response);
3082
95c6e9cb 3083exit:
01ef7dbf
IM		 3084 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3085 dspio_free_dma_chan(codec, dma_chan);
3086
b3667bd7 3087 if (dma_engine->dmab->area)
01ef7dbf
IM		 3088 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3089 kfree(dma_engine->dmab);
3090 kfree(dma_engine);
3091
3092 return status;
95c6e9cb
IM		 3093}
3094
3095/*
01ef7dbf 3096 * CA0132 DSP download stuffs.
95c6e9cb 3097 */
01ef7dbf 3098static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 3099{
009b8f97 3100 struct ca0132_spec *spec = codec->spec;
4e76a883 3101 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 3102 if (!spec->use_alt_functions) {
3103 /*set DSP speaker to 2.0 configuration*/
3104 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3105 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 3106
009b8f97
CM		 3107 /*update write pointer*/
3108 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3109 }
01ef7dbf 3110}
95c6e9cb 3111
d5c21b88 3112/**
e60b2c7f 3113 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 3114 *
3115 * @codec: the HDA codec
3116 * @fls: pointer to a fast load image
3117 * @ovly: TRUE if overlay format is required
3118 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3119 * no relocation
3120 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3121 * @router_chans: number of audio router channels to be allocated (0 means use
3122 * internal defaults; max is 32)
3123 *
e60b2c7f
TI		 3124 * Download DSP from a DSP Image Fast Load structure. This structure is a
3125 * linear, non-constant sized element array of structures, each of which
3126 * contain the count of the data to be loaded, the data itself, and the
3127 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 3128 * Returns zero or a negative error code.
3129 */
01ef7dbf
IM		 3130static int dspload_image(struct hda_codec *codec,
3131 const struct dsp_image_seg *fls,
3132 bool ovly,
3133 unsigned int reloc,
3134 bool autostart,
3135 int router_chans)
3136{
3137 int status = 0;
e97249dd
IM		 3138 unsigned int sample_rate;
3139 unsigned short channels;
01ef7dbf 3140
4e76a883 3141 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 3142 if (router_chans == 0) {
3143 if (!ovly)
3144 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3145 else
3146 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3147 }
95c6e9cb 3148
e97249dd
IM		 3149 sample_rate = 48000;
3150 channels = (unsigned short)router_chans;
01ef7dbf 3151
e97249dd
IM		 3152 while (channels > 16) {
3153 sample_rate *= 2;
3154 channels /= 2;
01ef7dbf
IM		 3155 }
3156
01ef7dbf 3157 do {
4e76a883 3158 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3159 if (!ovly)
3160 status = dsp_reset(codec);
3161
3162 if (status < 0)
3163 break;
3164
4e76a883 3165 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3166 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3167 ovly);
01ef7dbf
IM		 3168
3169 if (status < 0)
3170 break;
3171
4e76a883 3172 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3173 if (autostart && !ovly) {
3174 dspload_post_setup(codec);
3175 status = dsp_set_run_state(codec);
3176 }
3177
4e76a883 3178 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3179 } while (0);
3180
3181 return status;
3182}
3183
f664417e 3184#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3185static bool dspload_is_loaded(struct hda_codec *codec)
3186{
3187 unsigned int data = 0;
3188 int status = 0;
3189
3190 status = chipio_read(codec, 0x40004, &data);
3191 if ((status < 0) || (data != 1))
3192 return false;
3193
3194 return true;
3195}
f664417e
TI		 3196#else
3197#define dspload_is_loaded(codec) false
3198#endif
01ef7dbf
IM		 3199
3200static bool dspload_wait_loaded(struct hda_codec *codec)
3201{
6d67530e 3202 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3203
3204 do {
01ef7dbf 3205 if (dspload_is_loaded(codec)) {
d9684bb5 3206 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3207 return true;
3208 }
6d67530e
IM		 3209 msleep(20);
3210 } while (time_before(jiffies, timeout));
01ef7dbf 3211
d9684bb5 3212 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3213 return false;
95c6e9cb
IM		 3214}
3215
e93ac30a 3216/*
b9b41345
CM		 3217 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3218 * based cards, and has a second mmio region, region2, that's used for special
3219 * commands.
e93ac30a
CM		 3220 */
3221
a62e4739
CM		 3222/*
3223 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3224 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3225 * The first eight bits are just the number of the pin. So far, I've only seen
3226 * this number go to 7.
b9b41345
CM		 3227 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3228 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3229 * then off to send that bit.
a62e4739 3230 */
b9b41345 3231static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
a62e4739
CM		 3232 bool enable)
3233{
3234 struct ca0132_spec *spec = codec->spec;
3235 unsigned short gpio_data;
3236
3237 gpio_data = gpio_pin & 0xF;
3238 gpio_data |= ((enable << 8) & 0x100);
3239
3240 writew(gpio_data, spec->mem_base + 0x320);
3241}
3242
b9b41345
CM		 3243/*
3244 * Special pci region2 commands that are only used by the AE-5. They follow
3245 * a set format, and require reads at certain points to seemingly 'clear'
3246 * the response data. My first tests didn't do these reads, and would cause
3247 * the card to get locked up until the memory was read. These commands
3248 * seem to work with three distinct values that I've taken to calling group,
3249 * target-id, and value.
3250 */
3251static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3252 unsigned int target, unsigned int value)
3253{
3254 struct ca0132_spec *spec = codec->spec;
3255 unsigned int write_val;
3256
3257 writel(0x0000007e, spec->mem_base + 0x210);
3258 readl(spec->mem_base + 0x210);
3259 writel(0x0000005a, spec->mem_base + 0x210);
3260 readl(spec->mem_base + 0x210);
3261 readl(spec->mem_base + 0x210);
3262
3263 writel(0x00800005, spec->mem_base + 0x20c);
3264 writel(group, spec->mem_base + 0x804);
3265
3266 writel(0x00800005, spec->mem_base + 0x20c);
3267 write_val = (target & 0xff);
3268 write_val |= (value << 8);
3269
3270
3271 writel(write_val, spec->mem_base + 0x204);
3272 /*
3273 * Need delay here or else it goes too fast and works inconsistently.
3274 */
3275 msleep(20);
3276
3277 readl(spec->mem_base + 0x860);
3278 readl(spec->mem_base + 0x854);
3279 readl(spec->mem_base + 0x840);
3280
3281 writel(0x00800004, spec->mem_base + 0x20c);
3282 writel(0x00000000, spec->mem_base + 0x210);
3283 readl(spec->mem_base + 0x210);
3284 readl(spec->mem_base + 0x210);
3285}
3286
212de2e7
CM		 3287/*
3288 * This second type of command is used for setting the sound filter type.
3289 */
3290static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3291 unsigned int group, unsigned int target, unsigned int value)
3292{
3293 struct ca0132_spec *spec = codec->spec;
3294 unsigned int write_val;
3295
3296 writel(0x0000007e, spec->mem_base + 0x210);
3297 readl(spec->mem_base + 0x210);
3298 writel(0x0000005a, spec->mem_base + 0x210);
3299 readl(spec->mem_base + 0x210);
3300 readl(spec->mem_base + 0x210);
3301
3302 writel(0x00800003, spec->mem_base + 0x20c);
3303 writel(group, spec->mem_base + 0x804);
3304
3305 writel(0x00800005, spec->mem_base + 0x20c);
3306 write_val = (target & 0xff);
3307 write_val |= (value << 8);
3308
3309
3310 writel(write_val, spec->mem_base + 0x204);
3311 msleep(20);
3312 readl(spec->mem_base + 0x860);
3313 readl(spec->mem_base + 0x854);
3314 readl(spec->mem_base + 0x840);
3315
3316 writel(0x00800004, spec->mem_base + 0x20c);
3317 writel(0x00000000, spec->mem_base + 0x210);
3318 readl(spec->mem_base + 0x210);
3319 readl(spec->mem_base + 0x210);
3320}
3321
b9b41345
CM		 3322/*
3323 * Setup GPIO for the other variants of Core3D.
3324 */
3325
e93ac30a
CM		 3326/*
3327 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3328 * the card shows as having no GPIO pins.
3329 */
3330static void ca0132_gpio_init(struct hda_codec *codec)
3331{
3332 struct ca0132_spec *spec = codec->spec;
3333
3334 switch (spec->quirk) {
3335 case QUIRK_SBZ:
03c9b6b1 3336 case QUIRK_AE5:
e93ac30a
CM		 3337 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3338 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3339 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3340 break;
3341 case QUIRK_R3DI:
3342 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3343 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3344 break;
3345 }
3346
3347}
3348
3349/* Sets the GPIO for audio output. */
3350static void ca0132_gpio_setup(struct hda_codec *codec)
3351{
3352 struct ca0132_spec *spec = codec->spec;
3353
3354 switch (spec->quirk) {
3355 case QUIRK_SBZ:
3356 snd_hda_codec_write(codec, 0x01, 0,
3357 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3358 snd_hda_codec_write(codec, 0x01, 0,
3359 AC_VERB_SET_GPIO_MASK, 0x07);
3360 snd_hda_codec_write(codec, 0x01, 0,
3361 AC_VERB_SET_GPIO_DATA, 0x04);
3362 snd_hda_codec_write(codec, 0x01, 0,
3363 AC_VERB_SET_GPIO_DATA, 0x06);
3364 break;
3365 case QUIRK_R3DI:
3366 snd_hda_codec_write(codec, 0x01, 0,
3367 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3368 snd_hda_codec_write(codec, 0x01, 0,
3369 AC_VERB_SET_GPIO_MASK, 0x1F);
3370 snd_hda_codec_write(codec, 0x01, 0,
3371 AC_VERB_SET_GPIO_DATA, 0x0C);
3372 break;
3373 }
3374}
3375
7e6ed62e
CM		 3376/*
3377 * GPIO control functions for the Recon3D integrated.
3378 */
3379
3380enum r3di_gpio_bit {
3381 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3382 R3DI_MIC_SELECT_BIT = 1,
3383 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3384 R3DI_OUT_SELECT_BIT = 2,
3385 /*
3386 * I dunno what this actually does, but it stays on until the dsp
3387 * is downloaded.
3388 */
3389 R3DI_GPIO_DSP_DOWNLOADING = 3,
3390 /*
3391 * Same as above, no clue what it does, but it comes on after the dsp
3392 * is downloaded.
3393 */
3394 R3DI_GPIO_DSP_DOWNLOADED = 4
3395};
3396
3397enum r3di_mic_select {
3398 /* Set GPIO bit 1 to 0 for rear mic */
3399 R3DI_REAR_MIC = 0,
3400 /* Set GPIO bit 1 to 1 for front microphone*/
3401 R3DI_FRONT_MIC = 1
3402};
3403
3404enum r3di_out_select {
3405 /* Set GPIO bit 2 to 0 for headphone */
3406 R3DI_HEADPHONE_OUT = 0,
3407 /* Set GPIO bit 2 to 1 for speaker */
3408 R3DI_LINE_OUT = 1
3409};
3410enum r3di_dsp_status {
3411 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3412 R3DI_DSP_DOWNLOADING = 0,
3413 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3414 R3DI_DSP_DOWNLOADED = 1
3415};
3416
7cb9d94c
CM		 3417
3418static void r3di_gpio_mic_set(struct hda_codec *codec,
3419 enum r3di_mic_select cur_mic)
3420{
3421 unsigned int cur_gpio;
3422
3423 /* Get the current GPIO Data setup */
3424 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3425
3426 switch (cur_mic) {
3427 case R3DI_REAR_MIC:
3428 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3429 break;
3430 case R3DI_FRONT_MIC:
3431 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3432 break;
3433 }
3434 snd_hda_codec_write(codec, codec->core.afg, 0,
3435 AC_VERB_SET_GPIO_DATA, cur_gpio);
3436}
3437
3438static void r3di_gpio_out_set(struct hda_codec *codec,
3439 enum r3di_out_select cur_out)
3440{
3441 unsigned int cur_gpio;
3442
3443 /* Get the current GPIO Data setup */
3444 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3445
3446 switch (cur_out) {
3447 case R3DI_HEADPHONE_OUT:
3448 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3449 break;
3450 case R3DI_LINE_OUT:
3451 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3452 break;
3453 }
3454 snd_hda_codec_write(codec, codec->core.afg, 0,
3455 AC_VERB_SET_GPIO_DATA, cur_gpio);
3456}
3457
7e6ed62e
CM		 3458static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3459 enum r3di_dsp_status dsp_status)
3460{
3461 unsigned int cur_gpio;
3462
3463 /* Get the current GPIO Data setup */
3464 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3465
3466 switch (dsp_status) {
3467 case R3DI_DSP_DOWNLOADING:
3468 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3469 snd_hda_codec_write(codec, codec->core.afg, 0,
3470 AC_VERB_SET_GPIO_DATA, cur_gpio);
3471 break;
3472 case R3DI_DSP_DOWNLOADED:
3473 /* Set DOWNLOADING bit to 0. */
3474 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3475
3476 snd_hda_codec_write(codec, codec->core.afg, 0,
3477 AC_VERB_SET_GPIO_DATA, cur_gpio);
3478
3479 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3480 break;
3481 }
3482
3483 snd_hda_codec_write(codec, codec->core.afg, 0,
3484 AC_VERB_SET_GPIO_DATA, cur_gpio);
3485}
3486
825315bc
IM		 3487/*
3488 * PCM callbacks
3489 */
95c6e9cb
IM		 3490static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3491 struct hda_codec *codec,
3492 unsigned int stream_tag,
3493 unsigned int format,
3494 struct snd_pcm_substream *substream)
3495{
3496 struct ca0132_spec *spec = codec->spec;
825315bc 3497
28fba950 3498 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3499
3500 return 0;
95c6e9cb
IM		 3501}
3502
3503static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3504 struct hda_codec *codec,
3505 struct snd_pcm_substream *substream)
3506{
3507 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3508
3509 if (spec->dsp_state == DSP_DOWNLOADING)
3510 return 0;
3511
3512 /*If Playback effects are on, allow stream some time to flush
3513 *effects tail*/
3514 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3515 msleep(50);
3516
28fba950 3517 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3518
3519 return 0;
95c6e9cb
IM		 3520}
3521
e8412ca4
DR		 3522static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3523 struct hda_codec *codec,
3524 struct snd_pcm_substream *substream)
3525{
3526 struct ca0132_spec *spec = codec->spec;
3527 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3528 struct snd_pcm_runtime *runtime = substream->runtime;
3529
3530 if (spec->dsp_state != DSP_DOWNLOADED)
3531 return 0;
3532
3533 /* Add latency if playback enhancement and either effect is enabled. */
3534 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3535 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3536 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3537 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3538 }
3539
3540 /* Applying Speaker EQ adds latency as well. */
3541 if (spec->cur_out_type == SPEAKER_OUT)
3542 latency += DSP_SPEAKER_OUT_LATENCY;
3543
3544 return (latency * runtime->rate) / 1000;
3545}
3546
95c6e9cb
IM		 3547/*
3548 * Digital out
3549 */
27ebeb0b
TI		 3550static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3551 struct hda_codec *codec,
3552 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3553{
3554 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3555 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3556}
3557
27ebeb0b 3558static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3559 struct hda_codec *codec,
3560 unsigned int stream_tag,
3561 unsigned int format,
3562 struct snd_pcm_substream *substream)
3563{
3564 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3565 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3566 stream_tag, format, substream);
95c6e9cb
IM		 3567}
3568
27ebeb0b 3569static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3570 struct hda_codec *codec,
95c6e9cb
IM		 3571 struct snd_pcm_substream *substream)
3572{
3573 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3574 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3575}
3576
27ebeb0b
TI		 3577static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3578 struct hda_codec *codec,
3579 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3580{
3581 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3582 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3583}
3584
825315bc
IM		 3585/*
3586 * Analog capture
3587 */
3588static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3589 struct hda_codec *codec,
3590 unsigned int stream_tag,
3591 unsigned int format,
3592 struct snd_pcm_substream *substream)
3593{
13c12dbe 3594 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3595 stream_tag, 0, format);
825315bc
IM		 3596
3597 return 0;
3598}
3599
3600static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3601 struct hda_codec *codec,
3602 struct snd_pcm_substream *substream)
3603{
3604 struct ca0132_spec *spec = codec->spec;
3605
3606 if (spec->dsp_state == DSP_DOWNLOADING)
3607 return 0;
3608
28fba950 3609 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3610 return 0;
3611}
3612
e8412ca4
DR		 3613static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3614 struct hda_codec *codec,
3615 struct snd_pcm_substream *substream)
3616{
3617 struct ca0132_spec *spec = codec->spec;
3618 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3619 struct snd_pcm_runtime *runtime = substream->runtime;
3620
3621 if (spec->dsp_state != DSP_DOWNLOADED)
3622 return 0;
3623
3624 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3625 latency += DSP_CRYSTAL_VOICE_LATENCY;
3626
3627 return (latency * runtime->rate) / 1000;
3628}
3629
e90f29e4
IM		 3630/*
3631 * Controls stuffs.
3632 */
3633
3634/*
3635 * Mixer controls helpers.
3636 */
3637#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3638 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3639 .name = xname, \
3640 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3641 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3642 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3643 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3644 .info = ca0132_volume_info, \
3645 .get = ca0132_volume_get, \
3646 .put = ca0132_volume_put, \
3647 .tlv = { .c = ca0132_volume_tlv }, \
3648 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3649
017310fb
CM		 3650/*
3651 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3652 * volume put, which is used for setting the DSP volume. This was done because
3653 * the ca0132 functions were taking too much time and causing lag.
3654 */
3655#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3656 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3657 .name = xname, \
3658 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3659 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3660 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3661 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3662 .info = snd_hda_mixer_amp_volume_info, \
3663 .get = snd_hda_mixer_amp_volume_get, \
3664 .put = ca0132_alt_volume_put, \
3665 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3666 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3667
e90f29e4
IM		 3668#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3669 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3670 .name = xname, \
3671 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3672 .info = snd_hda_mixer_amp_switch_info, \
3673 .get = ca0132_switch_get, \
3674 .put = ca0132_switch_put, \
3675 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3676
3677/* stereo */
3678#define CA0132_CODEC_VOL(xname, nid, dir) \
3679 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3680#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3681 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3682#define CA0132_CODEC_MUTE(xname, nid, dir) \
3683 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3684
017310fb
CM		 3685/* lookup tables */
3686/*
3687 * Lookup table with decibel values for the DSP. When volume is changed in
3688 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3689 * these values have decimal points, probably because the Windows driver
3690 * actually uses floating point. We can't here, so I made a lookup table of
3691 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3692 * DAC's, and 9 is the maximum.
3693 */
3694static const unsigned int float_vol_db_lookup[] = {
36950xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
36960xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
36970xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
36980xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
36990xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
37000xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
37010xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
37020xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
37030xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
37040xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
37050xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
37060xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
37070xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
37080xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
37090xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
37100x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
37110x40C00000, 0x40E00000, 0x41000000, 0x41100000
3712};
3713
47cdf76e
CM		 3714/*
3715 * This table counts from float 0 to 1 in increments of .01, which is
3716 * useful for a few different sliders.
3717 */
3718static const unsigned int float_zero_to_one_lookup[] = {
37190x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37200x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37210x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37220x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
37230x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
37240x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
37250x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
37260x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
37270x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
37280x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
37290x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
37300x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
37310x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
37320x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
37330x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
37340x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
37350x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3736};
3737
3738/*
3739 * This table counts from float 10 to 1000, which is the range of the x-bass
3740 * crossover slider in Windows.
3741 */
3742static const unsigned int float_xbass_xover_lookup[] = {
37430x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
37440x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
37450x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
37460x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
37470x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
37480x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
37490x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
37500x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
37510x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
37520x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
37530x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
37540x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
37550x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
37560x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
37570x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
37580x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
37590x44728000, 0x44750000, 0x44778000, 0x447A0000
3760};
3761
4091fb95 3762/* The following are for tuning of products */
44f0c978
IM		 3763#ifdef ENABLE_TUNING_CONTROLS
3764
3765static unsigned int voice_focus_vals_lookup[] = {
37660x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
37670x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
37680x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
37690x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
37700x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
37710x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
37720x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
37730x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
37740x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
37750x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
37760x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
37770x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
37780x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
37790x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
37800x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
37810x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
37820x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
37830x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
37840x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
37850x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
37860x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
37870x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
37880x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
37890x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
37900x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
37910x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
37920x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3793};
3794
3795static unsigned int mic_svm_vals_lookup[] = {
37960x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37970x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37980x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37990x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
38000x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
38010x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
38020x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
38030x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
38040x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
38050x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
38060x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
38070x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
38080x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
38090x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
38100x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
38110x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
38120x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3813};
3814
3815static unsigned int equalizer_vals_lookup[] = {
38160xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
38170xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
38180xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
38190xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
38200x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
38210x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
38220x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
38230x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
38240x41C00000
3825};
3826
3827static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3828 unsigned int *lookup, int idx)
3829{
3830 int i = 0;
3831
3832 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3833 if (nid == ca0132_tuning_ctls[i].nid)
3834 break;
3835
3836 snd_hda_power_up(codec);
447fd8e9 3837 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3838 ca0132_tuning_ctls[i].req,
3839 &(lookup[idx]), sizeof(unsigned int));
3840 snd_hda_power_down(codec);
3841
3842 return 1;
3843}
3844
3845static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3846 struct snd_ctl_elem_value *ucontrol)
3847{
3848 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3849 struct ca0132_spec *spec = codec->spec;
3850 hda_nid_t nid = get_amp_nid(kcontrol);
3851 long *valp = ucontrol->value.integer.value;
3852 int idx = nid - TUNING_CTL_START_NID;
3853
3854 *valp = spec->cur_ctl_vals[idx];
3855 return 0;
3856}
3857
3858static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3859 struct snd_ctl_elem_info *uinfo)
3860{
3861 int chs = get_amp_channels(kcontrol);
3862 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3863 uinfo->count = chs == 3 ? 2 : 1;
3864 uinfo->value.integer.min = 20;
3865 uinfo->value.integer.max = 180;
3866 uinfo->value.integer.step = 1;
3867
3868 return 0;
3869}
3870
3871static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3872 struct snd_ctl_elem_value *ucontrol)
3873{
3874 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3875 struct ca0132_spec *spec = codec->spec;
3876 hda_nid_t nid = get_amp_nid(kcontrol);
3877 long *valp = ucontrol->value.integer.value;
3878 int idx;
3879
3880 idx = nid - TUNING_CTL_START_NID;
3881 /* any change? */
3882 if (spec->cur_ctl_vals[idx] == *valp)
3883 return 0;
3884
3885 spec->cur_ctl_vals[idx] = *valp;
3886
3887 idx = *valp - 20;
3888 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3889
3890 return 1;
3891}
3892
3893static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3894 struct snd_ctl_elem_info *uinfo)
3895{
3896 int chs = get_amp_channels(kcontrol);
3897 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3898 uinfo->count = chs == 3 ? 2 : 1;
3899 uinfo->value.integer.min = 0;
3900 uinfo->value.integer.max = 100;
3901 uinfo->value.integer.step = 1;
3902
3903 return 0;
3904}
3905
3906static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3907 struct snd_ctl_elem_value *ucontrol)
3908{
3909 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3910 struct ca0132_spec *spec = codec->spec;
3911 hda_nid_t nid = get_amp_nid(kcontrol);
3912 long *valp = ucontrol->value.integer.value;
3913 int idx;
3914
3915 idx = nid - TUNING_CTL_START_NID;
3916 /* any change? */
3917 if (spec->cur_ctl_vals[idx] == *valp)
3918 return 0;
3919
3920 spec->cur_ctl_vals[idx] = *valp;
3921
3922 idx = *valp;
3923 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3924
3925 return 0;
3926}
3927
3928static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3929 struct snd_ctl_elem_info *uinfo)
3930{
3931 int chs = get_amp_channels(kcontrol);
3932 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3933 uinfo->count = chs == 3 ? 2 : 1;
3934 uinfo->value.integer.min = 0;
3935 uinfo->value.integer.max = 48;
3936 uinfo->value.integer.step = 1;
3937
3938 return 0;
3939}
3940
3941static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3942 struct snd_ctl_elem_value *ucontrol)
3943{
3944 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3945 struct ca0132_spec *spec = codec->spec;
3946 hda_nid_t nid = get_amp_nid(kcontrol);
3947 long *valp = ucontrol->value.integer.value;
3948 int idx;
3949
3950 idx = nid - TUNING_CTL_START_NID;
3951 /* any change? */
3952 if (spec->cur_ctl_vals[idx] == *valp)
3953 return 0;
3954
3955 spec->cur_ctl_vals[idx] = *valp;
3956
3957 idx = *valp;
3958 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3959
3960 return 1;
3961}
3962
8e142e9e
TS		 3963static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3964static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3965
3966static int add_tuning_control(struct hda_codec *codec,
3967 hda_nid_t pnid, hda_nid_t nid,
3968 const char *name, int dir)
3969{
975cc02a 3970 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3971 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3972 struct snd_kcontrol_new knew =
3973 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3974
3975 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3976 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3977 knew.tlv.c = 0;
3978 knew.tlv.p = 0;
3979 switch (pnid) {
3980 case VOICE_FOCUS:
3981 knew.info = voice_focus_ctl_info;
3982 knew.get = tuning_ctl_get;
3983 knew.put = voice_focus_ctl_put;
3984 knew.tlv.p = voice_focus_db_scale;
3985 break;
3986 case MIC_SVM:
3987 knew.info = mic_svm_ctl_info;
3988 knew.get = tuning_ctl_get;
3989 knew.put = mic_svm_ctl_put;
3990 break;
3991 case EQUALIZER:
3992 knew.info = equalizer_ctl_info;
3993 knew.get = tuning_ctl_get;
3994 knew.put = equalizer_ctl_put;
3995 knew.tlv.p = eq_db_scale;
3996 break;
3997 default:
3998 return 0;
3999 }
4000 knew.private_value =
4001 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4002 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4003 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4004}
4005
4006static int add_tuning_ctls(struct hda_codec *codec)
4007{
4008 int i;
4009 int err;
4010
4011 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4012 err = add_tuning_control(codec,
4013 ca0132_tuning_ctls[i].parent_nid,
4014 ca0132_tuning_ctls[i].nid,
4015 ca0132_tuning_ctls[i].name,
4016 ca0132_tuning_ctls[i].direct);
4017 if (err < 0)
4018 return err;
4019 }
4020
4021 return 0;
4022}
4023
4024static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4025{
4026 struct ca0132_spec *spec = codec->spec;
4027 int i;
4028
4029 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4030 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4031 /* SVM level defaults to 0.74. */
4032 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4033
4034 /* EQ defaults to 0dB. */
4035 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4036 spec->cur_ctl_vals[i] = 24;
4037}
4038#endif /*ENABLE_TUNING_CONTROLS*/
4039
5aaca44d
IM		 4040/*
4041 * Select the active output.
4042 * If autodetect is enabled, output will be selected based on jack detection.
4043 * If jack inserted, headphone will be selected, else built-in speakers
4044 * If autodetect is disabled, output will be selected based on selection.
4045 */
4046static int ca0132_select_out(struct hda_codec *codec)
4047{
4048 struct ca0132_spec *spec = codec->spec;
4049 unsigned int pin_ctl;
4050 int jack_present;
4051 int auto_jack;
4052 unsigned int tmp;
4053 int err;
4054
4e76a883 4055 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 4056
664c7155 4057 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4058
4059 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4060
4061 if (auto_jack)
fe14f39e 4062 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 4063 else
4064 jack_present =
4065 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4066
4067 if (jack_present)
4068 spec->cur_out_type = HEADPHONE_OUT;
4069 else
4070 spec->cur_out_type = SPEAKER_OUT;
4071
4072 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 4073 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 4074 /*speaker out config*/
4075 tmp = FLOAT_ONE;
4076 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4077 if (err < 0)
4078 goto exit;
4079 /*enable speaker EQ*/
4080 tmp = FLOAT_ONE;
4081 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4082 if (err < 0)
4083 goto exit;
4084
4085 /* Setup EAPD */
4086 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4087 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4088 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4089 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4090 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4091 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4092 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4093 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4094
4095 /* disable headphone node */
4096 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4097 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4098 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4099 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4100 /* enable speaker node */
4101 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 4102 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4103 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4104 pin_ctl | PIN_OUT);
5aaca44d 4105 } else {
4e76a883 4106 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 4107 /*headphone out config*/
4108 tmp = FLOAT_ZERO;
4109 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4110 if (err < 0)
4111 goto exit;
4112 /*disable speaker EQ*/
4113 tmp = FLOAT_ZERO;
4114 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4115 if (err < 0)
4116 goto exit;
4117
4118 /* Setup EAPD */
4119 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4120 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4121 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4122 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4123 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4124 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4125 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4126 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4127
4128 /* disable speaker*/
4129 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4130 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4131 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4132 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4133 /* enable headphone*/
4134 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4135 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4136 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4137 pin_ctl | PIN_HP);
5aaca44d
IM		 4138 }
4139
4140exit:
664c7155 4141 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4142
4143 return err < 0 ? err : 0;
4144}
4145
212de2e7 4146static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
d51434d4 4147static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
8e6bc6b3 4148static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
212de2e7 4149
2283c85b
CM		 4150static void ae5_mmio_select_out(struct hda_codec *codec)
4151{
4152 struct ca0132_spec *spec = codec->spec;
4153 unsigned int i;
4154
4155 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++)
4156 ca0113_mmio_command_set(codec,
4157 ae5_ca0113_output_presets[spec->cur_out_type].group[i],
4158 ae5_ca0113_output_presets[spec->cur_out_type].target[i],
4159 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]);
4160}
4161
746fc9de
CM		 4162/*
4163 * These are the commands needed to setup output on each of the different card
4164 * types.
4165 */
4166static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4167{
4168 struct ca0132_spec *spec = codec->spec;
2283c85b 4169 unsigned int tmp;
746fc9de
CM		 4170
4171 switch (spec->cur_out_type) {
4172 case SPEAKER_OUT:
4173 switch (spec->quirk) {
4174 case QUIRK_SBZ:
4175 ca0113_mmio_gpio_set(codec, 7, false);
4176 ca0113_mmio_gpio_set(codec, 4, true);
4177 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4178 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de 4179 break;
55845949
CM		 4180 case QUIRK_ZXR:
4181 ca0113_mmio_gpio_set(codec, 2, true);
4182 ca0113_mmio_gpio_set(codec, 3, true);
4183 ca0113_mmio_gpio_set(codec, 5, false);
d51434d4 4184 zxr_headphone_gain_set(codec, 0);
55845949
CM		 4185 chipio_set_control_param(codec, 0x0d, 0x24);
4186 break;
746fc9de 4187 case QUIRK_R3DI:
2283c85b 4188 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4189 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4190 break;
4191 case QUIRK_R3D:
2283c85b 4192 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4193 ca0113_mmio_gpio_set(codec, 1, true);
4194 break;
2283c85b
CM		 4195 case QUIRK_AE5:
4196 ae5_mmio_select_out(codec);
212de2e7 4197 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4198 tmp = FLOAT_ZERO;
4199 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4200 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4201 chipio_set_control_param(codec, 0x0d, 0xa4);
4202 chipio_write(codec, 0x18b03c, 0x00000012);
4203 break;
746fc9de
CM		 4204 }
4205 break;
4206 case HEADPHONE_OUT:
4207 switch (spec->quirk) {
4208 case QUIRK_SBZ:
4209 ca0113_mmio_gpio_set(codec, 7, true);
4210 ca0113_mmio_gpio_set(codec, 4, true);
4211 ca0113_mmio_gpio_set(codec, 1, false);
2283c85b 4212 chipio_set_control_param(codec, 0x0d, 0x12);
746fc9de 4213 break;
55845949
CM		 4214 case QUIRK_ZXR:
4215 ca0113_mmio_gpio_set(codec, 2, false);
4216 ca0113_mmio_gpio_set(codec, 3, false);
4217 ca0113_mmio_gpio_set(codec, 5, true);
d51434d4 4218 zxr_headphone_gain_set(codec, spec->zxr_gain_set);
55845949
CM		 4219 chipio_set_control_param(codec, 0x0d, 0x21);
4220 break;
746fc9de 4221 case QUIRK_R3DI:
2283c85b 4222 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4223 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4224 break;
4225 case QUIRK_R3D:
2283c85b 4226 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4227 ca0113_mmio_gpio_set(codec, 0x1, false);
4228 break;
2283c85b
CM		 4229 case QUIRK_AE5:
4230 ae5_mmio_select_out(codec);
212de2e7
CM		 4231 ae5_headphone_gain_set(codec,
4232 spec->ae5_headphone_gain_val);
2283c85b
CM		 4233 tmp = FLOAT_ONE;
4234 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4235 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4236 chipio_set_control_param(codec, 0x0d, 0xa1);
4237 chipio_write(codec, 0x18b03c, 0x00000012);
4238 break;
746fc9de
CM		 4239 }
4240 break;
4241 case SURROUND_OUT:
4242 switch (spec->quirk) {
4243 case QUIRK_SBZ:
4244 ca0113_mmio_gpio_set(codec, 7, false);
4245 ca0113_mmio_gpio_set(codec, 4, true);
4246 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4247 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de 4248 break;
55845949
CM		 4249 case QUIRK_ZXR:
4250 ca0113_mmio_gpio_set(codec, 2, true);
4251 ca0113_mmio_gpio_set(codec, 3, true);
4252 ca0113_mmio_gpio_set(codec, 5, false);
d51434d4 4253 zxr_headphone_gain_set(codec, 0);
55845949
CM		 4254 chipio_set_control_param(codec, 0x0d, 0x24);
4255 break;
746fc9de 4256 case QUIRK_R3DI:
2283c85b 4257 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4258 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4259 break;
4260 case QUIRK_R3D:
4261 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b
CM		 4262 chipio_set_control_param(codec, 0x0d, 0x24);
4263 break;
4264 case QUIRK_AE5:
4265 ae5_mmio_select_out(codec);
212de2e7 4266 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4267 tmp = FLOAT_ZERO;
4268 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4269 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4270 chipio_set_control_param(codec, 0x0d, 0xa4);
4271 chipio_write(codec, 0x18b03c, 0x00000012);
746fc9de
CM		 4272 break;
4273 }
4274 break;
4275 }
4276}
4277
7cb9d94c
CM		 4278/*
4279 * This function behaves similarly to the ca0132_select_out funciton above,
4280 * except with a few differences. It adds the ability to select the current
4281 * output with an enumerated control "output source" if the auto detect
4282 * mute switch is set to off. If the auto detect mute switch is enabled, it
4283 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4284 * It also adds the ability to auto-detect the front headphone port. The only
4285 * way to select surround is to disable auto detect, and set Surround with the
4286 * enumerated control.
4287 */
4288static int ca0132_alt_select_out(struct hda_codec *codec)
4289{
4290 struct ca0132_spec *spec = codec->spec;
4291 unsigned int pin_ctl;
4292 int jack_present;
4293 int auto_jack;
4294 unsigned int i;
4295 unsigned int tmp;
4296 int err;
4297 /* Default Headphone is rear headphone */
4298 hda_nid_t headphone_nid = spec->out_pins[1];
4299
4300 codec_dbg(codec, "%s\n", __func__);
4301
4302 snd_hda_power_up_pm(codec);
4303
4304 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4305
4306 /*
4307 * If headphone rear or front is plugged in, set to headphone.
4308 * If neither is plugged in, set to rear line out. Only if
4309 * hp/speaker auto detect is enabled.
4310 */
4311 if (auto_jack) {
4312 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4313 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4314
4315 if (jack_present)
4316 spec->cur_out_type = HEADPHONE_OUT;
4317 else
4318 spec->cur_out_type = SPEAKER_OUT;
4319 } else
4320 spec->cur_out_type = spec->out_enum_val;
4321
4322 /* Begin DSP output switch */
4323 tmp = FLOAT_ONE;
4324 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4325 if (err < 0)
4326 goto exit;
4327
746fc9de
CM		 4328 ca0132_alt_select_out_quirk_handler(codec);
4329
7cb9d94c
CM		 4330 switch (spec->cur_out_type) {
4331 case SPEAKER_OUT:
4332 codec_dbg(codec, "%s speaker\n", __func__);
7cb9d94c
CM		 4333
4334 /* disable headphone node */
4335 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4336 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4337 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4338 pin_ctl & ~PIN_HP);
4339 /* enable line-out node */
4340 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4341 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4342 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4343 pin_ctl | PIN_OUT);
4344 /* Enable EAPD */
4345 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4346 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4347
4348 /* If PlayEnhancement is enabled, set different source */
4349 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4350 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4351 else
4352 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4353 break;
4354 case HEADPHONE_OUT:
4355 codec_dbg(codec, "%s hp\n", __func__);
7cb9d94c
CM		 4356
4357 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4358 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4359
4360 /* disable speaker*/
4361 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4362 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4363 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4364 pin_ctl & ~PIN_HP);
4365
4366 /* enable headphone, either front or rear */
4367
4368 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4369 headphone_nid = spec->out_pins[2];
4370 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4371 headphone_nid = spec->out_pins[1];
4372
4373 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4374 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4375 snd_hda_set_pin_ctl(codec, headphone_nid,
4376 pin_ctl | PIN_HP);
4377
4378 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4379 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4380 else
4381 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4382 break;
4383 case SURROUND_OUT:
4384 codec_dbg(codec, "%s surround\n", __func__);
746fc9de 4385
7cb9d94c
CM		 4386 /* enable line out node */
4387 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4388 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4389 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4390 pin_ctl | PIN_OUT);
4391 /* Disable headphone out */
4392 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4393 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4394 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4395 pin_ctl & ~PIN_HP);
4396 /* Enable EAPD on line out */
4397 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4398 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4399 /* enable center/lfe out node */
4400 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4401 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4402 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4403 pin_ctl | PIN_OUT);
4404 /* Now set rear surround node as out. */
4405 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4406 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4407 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4408 pin_ctl | PIN_OUT);
4409
8e6bc6b3 4410 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
7cb9d94c
CM		 4411 break;
4412 }
8e6bc6b3
CM		 4413 /*
4414 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT.
4415 * With this set though, X_BASS cannot be enabled. So, if we have OutFX
4416 * enabled, we need to make sure X_BASS is off, otherwise everything
4417 * sounds all muffled. Running ca0132_effects_set with X_BASS as the
4418 * effect should sort this out.
4419 */
4420 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4421 ca0132_effects_set(codec, X_BASS,
4422 spec->effects_switch[X_BASS - EFFECT_START_NID]);
7cb9d94c 4423
2283c85b 4424 /* run through the output dsp commands for the selected output. */
7cb9d94c
CM		 4425 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4426 err = dspio_set_uint_param(codec,
4427 alt_out_presets[spec->cur_out_type].mids[i],
4428 alt_out_presets[spec->cur_out_type].reqs[i],
4429 alt_out_presets[spec->cur_out_type].vals[i]);
4430
4431 if (err < 0)
4432 goto exit;
4433 }
4434
4435exit:
4436 snd_hda_power_down_pm(codec);
4437
4438 return err < 0 ? err : 0;
4439}
4440
993884f6
CCC		 4441static void ca0132_unsol_hp_delayed(struct work_struct *work)
4442{
4443 struct ca0132_spec *spec = container_of(
4444 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4445 struct hda_jack_tbl *jack;
4446
7cb9d94c
CM		 4447 if (spec->use_alt_functions)
4448 ca0132_alt_select_out(spec->codec);
4449 else
4450 ca0132_select_out(spec->codec);
4451
d5c016b5 4452 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4453 if (jack) {
4454 jack->block_report = 0;
4455 snd_hda_jack_report_sync(spec->codec);
4456 }
993884f6
CCC		 4457}
4458
5aaca44d
IM		 4459static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4460static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
e0026d03
CM		 4461static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4462static int stop_mic1(struct hda_codec *codec);
4463static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4464static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4465
4466/*
4467 * Select the active VIP source
4468 */
4469static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4470{
4471 struct ca0132_spec *spec = codec->spec;
4472 unsigned int tmp;
4473
e8f1bd5d 4474 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4475 return 0;
4476
4477 /* if CrystalVoice if off, vipsource should be 0 */
4478 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4479 (val == 0)) {
4480 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4481 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4482 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4483 if (spec->cur_mic_type == DIGITAL_MIC)
4484 tmp = FLOAT_TWO;
4485 else
4486 tmp = FLOAT_ONE;
4487 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4488 tmp = FLOAT_ZERO;
4489 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4490 } else {
4491 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4492 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4493 if (spec->cur_mic_type == DIGITAL_MIC)
4494 tmp = FLOAT_TWO;
4495 else
4496 tmp = FLOAT_ONE;
4497 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4498 tmp = FLOAT_ONE;
4499 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4500 msleep(20);
4501 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4502 }
4503
4504 return 1;
4505}
4506
e0026d03
CM		 4507static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4508{
4509 struct ca0132_spec *spec = codec->spec;
4510 unsigned int tmp;
4511
4512 if (spec->dsp_state != DSP_DOWNLOADED)
4513 return 0;
4514
4515 codec_dbg(codec, "%s\n", __func__);
4516
4517 chipio_set_stream_control(codec, 0x03, 0);
4518 chipio_set_stream_control(codec, 0x04, 0);
4519
4520 /* if CrystalVoice is off, vipsource should be 0 */
4521 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4522 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4523 codec_dbg(codec, "%s: off.", __func__);
4524 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4525
4526 tmp = FLOAT_ZERO;
4527 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4528
4529 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4530 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4531 if (spec->quirk == QUIRK_R3DI)
4532 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4533
4534
4535 if (spec->in_enum_val == REAR_LINE_IN)
4536 tmp = FLOAT_ZERO;
4537 else {
4538 if (spec->quirk == QUIRK_SBZ)
4539 tmp = FLOAT_THREE;
4540 else
4541 tmp = FLOAT_ONE;
4542 }
4543
4544 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4545
4546 } else {
4547 codec_dbg(codec, "%s: on.", __func__);
4548 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4549 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4550 if (spec->quirk == QUIRK_R3DI)
4551 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4552
4553 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4554 tmp = FLOAT_TWO;
4555 else
4556 tmp = FLOAT_ONE;
4557 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4558
4559 tmp = FLOAT_ONE;
4560 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4561
4562 msleep(20);
4563 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4564 }
4565
4566 chipio_set_stream_control(codec, 0x03, 1);
4567 chipio_set_stream_control(codec, 0x04, 1);
4568
4569 return 1;
4570}
4571
5aaca44d
IM		 4572/*
4573 * Select the active microphone.
4574 * If autodetect is enabled, mic will be selected based on jack detection.
4575 * If jack inserted, ext.mic will be selected, else built-in mic
4576 * If autodetect is disabled, mic will be selected based on selection.
4577 */
4578static int ca0132_select_mic(struct hda_codec *codec)
4579{
4580 struct ca0132_spec *spec = codec->spec;
4581 int jack_present;
4582 int auto_jack;
4583
4e76a883 4584 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4585
664c7155 4586 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4587
4588 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4589
4590 if (auto_jack)
fe14f39e 4591 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4592 else
4593 jack_present =
4594 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4595
4596 if (jack_present)
4597 spec->cur_mic_type = LINE_MIC_IN;
4598 else
4599 spec->cur_mic_type = DIGITAL_MIC;
4600
4601 if (spec->cur_mic_type == DIGITAL_MIC) {
4602 /* enable digital Mic */
4603 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4604 ca0132_set_dmic(codec, 1);
4605 ca0132_mic_boost_set(codec, 0);
4606 /* set voice focus */
4607 ca0132_effects_set(codec, VOICE_FOCUS,
4608 spec->effects_switch
4609 [VOICE_FOCUS - EFFECT_START_NID]);
4610 } else {
4611 /* disable digital Mic */
4612 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4613 ca0132_set_dmic(codec, 0);
4614 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4615 /* disable voice focus */
4616 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4617 }
4618
664c7155 4619 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4620
4621 return 0;
4622}
4623
7cb9d94c
CM		 4624/*
4625 * Select the active input.
4626 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4627 * The front mic has no jack-detection, so the only way to switch to it
4628 * is to do it manually in alsamixer.
4629 */
4630static int ca0132_alt_select_in(struct hda_codec *codec)
4631{
4632 struct ca0132_spec *spec = codec->spec;
4633 unsigned int tmp;
4634
4635 codec_dbg(codec, "%s\n", __func__);
4636
4637 snd_hda_power_up_pm(codec);
4638
4639 chipio_set_stream_control(codec, 0x03, 0);
4640 chipio_set_stream_control(codec, 0x04, 0);
4641
4642 spec->cur_mic_type = spec->in_enum_val;
4643
4644 switch (spec->cur_mic_type) {
4645 case REAR_MIC:
4646 switch (spec->quirk) {
4647 case QUIRK_SBZ:
42aa3a16 4648 case QUIRK_R3D:
b9b41345 4649 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4650 tmp = FLOAT_THREE;
4651 break;
55845949
CM		 4652 case QUIRK_ZXR:
4653 tmp = FLOAT_THREE;
4654 break;
7cb9d94c
CM		 4655 case QUIRK_R3DI:
4656 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4657 tmp = FLOAT_ONE;
4658 break;
f231daaf
CM		 4659 case QUIRK_AE5:
4660 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4661 tmp = FLOAT_THREE;
4662 break;
7cb9d94c
CM		 4663 default:
4664 tmp = FLOAT_ONE;
4665 break;
4666 }
4667
4668 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4669 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4670 if (spec->quirk == QUIRK_R3DI)
4671 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4672
4673 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4674
4675 chipio_set_stream_control(codec, 0x03, 1);
4676 chipio_set_stream_control(codec, 0x04, 1);
f231daaf
CM		 4677 switch (spec->quirk) {
4678 case QUIRK_SBZ:
7cb9d94c
CM		 4679 chipio_write(codec, 0x18B098, 0x0000000C);
4680 chipio_write(codec, 0x18B09C, 0x0000000C);
f231daaf 4681 break;
55845949
CM		 4682 case QUIRK_ZXR:
4683 chipio_write(codec, 0x18B098, 0x0000000C);
4684 chipio_write(codec, 0x18B09C, 0x000000CC);
4685 break;
f231daaf
CM		 4686 case QUIRK_AE5:
4687 chipio_write(codec, 0x18B098, 0x0000000C);
4688 chipio_write(codec, 0x18B09C, 0x0000004C);
4689 break;
7cb9d94c 4690 }
47cdf76e 4691 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4692 break;
4693 case REAR_LINE_IN:
4694 ca0132_mic_boost_set(codec, 0);
4695 switch (spec->quirk) {
4696 case QUIRK_SBZ:
42aa3a16 4697 case QUIRK_R3D:
b9b41345 4698 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4699 break;
4700 case QUIRK_R3DI:
4701 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4702 break;
f231daaf
CM		 4703 case QUIRK_AE5:
4704 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4705 break;
7cb9d94c
CM		 4706 }
4707
4708 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4709 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4710 if (spec->quirk == QUIRK_R3DI)
4711 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4712
4713 tmp = FLOAT_ZERO;
4714 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4715
f231daaf
CM		 4716 switch (spec->quirk) {
4717 case QUIRK_SBZ:
4718 case QUIRK_AE5:
7cb9d94c
CM		 4719 chipio_write(codec, 0x18B098, 0x00000000);
4720 chipio_write(codec, 0x18B09C, 0x00000000);
f231daaf 4721 break;
7cb9d94c 4722 }
7cb9d94c
CM		 4723 chipio_set_stream_control(codec, 0x03, 1);
4724 chipio_set_stream_control(codec, 0x04, 1);
4725 break;
4726 case FRONT_MIC:
4727 switch (spec->quirk) {
4728 case QUIRK_SBZ:
42aa3a16 4729 case QUIRK_R3D:
b9b41345
CM		 4730 ca0113_mmio_gpio_set(codec, 0, true);
4731 ca0113_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4732 tmp = FLOAT_THREE;
4733 break;
4734 case QUIRK_R3DI:
4735 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4736 tmp = FLOAT_ONE;
4737 break;
f231daaf
CM		 4738 case QUIRK_AE5:
4739 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f);
4740 tmp = FLOAT_THREE;
4741 break;
7cb9d94c
CM		 4742 default:
4743 tmp = FLOAT_ONE;
4744 break;
4745 }
4746
4747 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4748 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4749 if (spec->quirk == QUIRK_R3DI)
4750 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4751
4752 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4753
4754 chipio_set_stream_control(codec, 0x03, 1);
4755 chipio_set_stream_control(codec, 0x04, 1);
4756
f231daaf
CM		 4757 switch (spec->quirk) {
4758 case QUIRK_SBZ:
7cb9d94c
CM		 4759 chipio_write(codec, 0x18B098, 0x0000000C);
4760 chipio_write(codec, 0x18B09C, 0x000000CC);
f231daaf
CM		 4761 break;
4762 case QUIRK_AE5:
4763 chipio_write(codec, 0x18B098, 0x0000000C);
4764 chipio_write(codec, 0x18B09C, 0x0000004C);
4765 break;
7cb9d94c 4766 }
47cdf76e 4767 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4768 break;
4769 }
e0026d03 4770 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4771
4772 snd_hda_power_down_pm(codec);
4773 return 0;
7cb9d94c
CM		 4774}
4775
a7e76271
IM		 4776/*
4777 * Check if VNODE settings take effect immediately.
4778 */
4779static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4780 hda_nid_t vnid,
4781 hda_nid_t *shared_nid)
4782{
4783 struct ca0132_spec *spec = codec->spec;
4784 hda_nid_t nid;
a7e76271
IM		 4785
4786 switch (vnid) {
4787 case VNID_SPK:
4788 nid = spec->shared_out_nid;
a7e76271
IM		 4789 break;
4790 case VNID_MIC:
4791 nid = spec->shared_mic_nid;
a7e76271
IM		 4792 break;
4793 default:
9a0869f4 4794 return false;
a7e76271
IM		 4795 }
4796
9a0869f4 4797 if (shared_nid)
a7e76271
IM		 4798 *shared_nid = nid;
4799
9a0869f4 4800 return true;
a7e76271
IM		 4801}
4802
4803/*
4804* The following functions are control change helpers.
4805* They return 0 if no changed. Return 1 if changed.
4806*/
4807static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4808{
4809 struct ca0132_spec *spec = codec->spec;
4810 unsigned int tmp;
4811
4812 /* based on CrystalVoice state to enable VoiceFX. */
4813 if (enable) {
4814 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4815 FLOAT_ONE : FLOAT_ZERO;
4816 } else {
4817 tmp = FLOAT_ZERO;
4818 }
4819
4820 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4821 ca0132_voicefx.reqs[0], tmp);
4822
4823 return 1;
4824}
4825
5aaca44d
IM		 4826/*
4827 * Set the effects parameters
4828 */
4829static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4830{
4831 struct ca0132_spec *spec = codec->spec;
009b8f97 4832 unsigned int on, tmp;
5aaca44d
IM		 4833 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4834 int err = 0;
4835 int idx = nid - EFFECT_START_NID;
4836
4837 if ((idx < 0) || (idx >= num_fx))
4838 return 0; /* no changed */
4839
4840 /* for out effect, qualify with PE */
4841 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4842 /* if PE if off, turn off out effects. */
4843 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4844 val = 0;
8e6bc6b3
CM		 4845 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS)
4846 val = 0;
5aaca44d
IM		 4847 }
4848
4849 /* for in effect, qualify with CrystalVoice */
4850 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4851 /* if CrystalVoice if off, turn off in effects. */
4852 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4853 val = 0;
4854
4855 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4856 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4857 val = 0;
009b8f97
CM		 4858
4859 /* If Voice Focus on SBZ, set to two channel. */
7cb9d94c
CM		 4860 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4861 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4862 if (spec->effects_switch[CRYSTAL_VOICE -
4863 EFFECT_START_NID]) {
4864
4865 if (spec->effects_switch[VOICE_FOCUS -
4866 EFFECT_START_NID]) {
4867 tmp = FLOAT_TWO;
4868 val = 1;
4869 } else
4870 tmp = FLOAT_ONE;
4871
4872 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4873 }
4874 }
4875 /*
4876 * For SBZ noise reduction, there's an extra command
4877 * to module ID 0x47. No clue why.
4878 */
7cb9d94c
CM		 4879 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4880 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4881 if (spec->effects_switch[CRYSTAL_VOICE -
4882 EFFECT_START_NID]) {
4883 if (spec->effects_switch[NOISE_REDUCTION -
4884 EFFECT_START_NID])
4885 tmp = FLOAT_ONE;
4886 else
4887 tmp = FLOAT_ZERO;
4888 } else
4889 tmp = FLOAT_ZERO;
4890
4891 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4892 }
7cb9d94c
CM		 4893
4894 /* If rear line in disable effects. */
4895 if (spec->use_alt_functions &&
4896 spec->in_enum_val == REAR_LINE_IN)
4897 val = 0;
5aaca44d
IM		 4898 }
4899
4e76a883 4900 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4901 nid, val);
4902
4903 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4904 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4905 ca0132_effects[idx].reqs[0], on);
4906
4907 if (err < 0)
4908 return 0; /* no changed */
4909
4910 return 1;
4911}
4912
a7e76271
IM		 4913/*
4914 * Turn on/off Playback Enhancements
4915 */
4916static int ca0132_pe_switch_set(struct hda_codec *codec)
4917{
4918 struct ca0132_spec *spec = codec->spec;
4919 hda_nid_t nid;
4920 int i, ret = 0;
4921
4e76a883 4922 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4923 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4924
7cb9d94c
CM		 4925 if (spec->use_alt_functions)
4926 ca0132_alt_select_out(codec);
4927
a7e76271
IM		 4928 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4929 nid = OUT_EFFECT_START_NID;
4930 /* PE affects all out effects */
4931 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4932 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4933
4934 return ret;
4935}
4936
5aaca44d
IM		 4937/* Check if Mic1 is streaming, if so, stop streaming */
4938static int stop_mic1(struct hda_codec *codec)
4939{
4940 struct ca0132_spec *spec = codec->spec;
4941 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4942 AC_VERB_GET_CONV, 0);
4943 if (oldval != 0)
4944 snd_hda_codec_write(codec, spec->adcs[0], 0,
4945 AC_VERB_SET_CHANNEL_STREAMID,
4946 0);
4947 return oldval;
4948}
4949
4950/* Resume Mic1 streaming if it was stopped. */
4951static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4952{
4953 struct ca0132_spec *spec = codec->spec;
4954 /* Restore the previous stream and channel */
4955 if (oldval != 0)
4956 snd_hda_codec_write(codec, spec->adcs[0], 0,
4957 AC_VERB_SET_CHANNEL_STREAMID,
4958 oldval);
4959}
4960
4961/*
a7e76271 4962 * Turn on/off CrystalVoice
5aaca44d 4963 */
a7e76271
IM		 4964static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4965{
4966 struct ca0132_spec *spec = codec->spec;
4967 hda_nid_t nid;
4968 int i, ret = 0;
4969 unsigned int oldval;
4970
4e76a883 4971 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4972 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4973
4974 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4975 nid = IN_EFFECT_START_NID;
4976 /* CrystalVoice affects all in effects */
4977 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4978 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4979
4980 /* including VoiceFX */
4981 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4982
4983 /* set correct vipsource */
4984 oldval = stop_mic1(codec);
e0026d03
CM		 4985 if (spec->use_alt_functions)
4986 ret |= ca0132_alt_set_vipsource(codec, 1);
4987 else
4988 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 4989 resume_mic1(codec, oldval);
4990 return ret;
4991}
4992
5aaca44d
IM		 4993static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4994{
4995 struct ca0132_spec *spec = codec->spec;
4996 int ret = 0;
4997
4998 if (val) /* on */
4999 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5000 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5001 else /* off */
5002 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5003 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5004
5005 return ret;
5006}
5007
47cdf76e
CM		 5008static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5009{
5010 struct ca0132_spec *spec = codec->spec;
5011 int ret = 0;
5012
5013 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5014 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5015 return ret;
5016}
5017
212de2e7
CM		 5018static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5019{
5020 unsigned int i;
5021
5022 for (i = 0; i < 4; i++)
5023 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5024 ae5_headphone_gain_presets[val].vals[i]);
5025 return 0;
5026}
5027
d51434d4
CM		 5028/*
5029 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5030 * amplifier to handle a 600 ohm load.
5031 */
5032static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5033{
5034 ca0113_mmio_gpio_set(codec, 1, val);
5035
5036 return 0;
5037}
5038
a7e76271
IM		 5039static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5040 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 5041{
a7e76271
IM		 5042 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5043 hda_nid_t nid = get_amp_nid(kcontrol);
5044 hda_nid_t shared_nid = 0;
5045 bool effective;
5046 int ret = 0;
95c6e9cb 5047 struct ca0132_spec *spec = codec->spec;
a7e76271 5048 int auto_jack;
95c6e9cb 5049
a7e76271
IM		 5050 if (nid == VNID_HP_SEL) {
5051 auto_jack =
5052 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 5053 if (!auto_jack) {
5054 if (spec->use_alt_functions)
5055 ca0132_alt_select_out(codec);
5056 else
5057 ca0132_select_out(codec);
5058 }
a7e76271
IM		 5059 return 1;
5060 }
95c6e9cb 5061
a7e76271
IM		 5062 if (nid == VNID_AMIC1_SEL) {
5063 auto_jack =
5064 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5065 if (!auto_jack)
5066 ca0132_select_mic(codec);
5067 return 1;
5068 }
95c6e9cb 5069
a7e76271 5070 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 5071 if (spec->use_alt_functions)
5072 ca0132_alt_select_out(codec);
5073 else
5074 ca0132_select_out(codec);
a7e76271
IM		 5075 return 1;
5076 }
95c6e9cb 5077
a7e76271
IM		 5078 if (nid == VNID_AMIC1_ASEL) {
5079 ca0132_select_mic(codec);
5080 return 1;
95c6e9cb 5081 }
a7e76271
IM		 5082
5083 /* if effective conditions, then update hw immediately. */
5084 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5085 if (effective) {
5086 int dir = get_amp_direction(kcontrol);
5087 int ch = get_amp_channels(kcontrol);
5088 unsigned long pval;
5089
5090 mutex_lock(&codec->control_mutex);
5091 pval = kcontrol->private_value;
5092 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5093 0, dir);
5094 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5095 kcontrol->private_value = pval;
5096 mutex_unlock(&codec->control_mutex);
95c6e9cb 5097 }
95c6e9cb 5098
a7e76271 5099 return ret;
95c6e9cb 5100}
a7e76271 5101/* End of control change helpers. */
47cdf76e
CM		 5102/*
5103 * Below I've added controls to mess with the effect levels, I've only enabled
5104 * them on the Sound Blaster Z, but they would probably also work on the
5105 * Chromebook. I figured they were probably tuned specifically for it, and left
5106 * out for a reason.
5107 */
5108
5109/* Sets DSP effect level from the sliders above the controls */
5110static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5111 const unsigned int *lookup, int idx)
5112{
5113 int i = 0;
5114 unsigned int y;
5115 /*
5116 * For X_BASS, req 2 is actually crossover freq instead of
5117 * effect level
5118 */
5119 if (nid == X_BASS)
5120 y = 2;
5121 else
5122 y = 1;
5123
5124 snd_hda_power_up(codec);
5125 if (nid == XBASS_XOVER) {
5126 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5127 if (ca0132_effects[i].nid == X_BASS)
5128 break;
5129
5130 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5131 ca0132_effects[i].reqs[1],
5132 &(lookup[idx - 1]), sizeof(unsigned int));
5133 } else {
5134 /* Find the actual effect structure */
5135 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5136 if (nid == ca0132_effects[i].nid)
5137 break;
5138
5139 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5140 ca0132_effects[i].reqs[y],
5141 &(lookup[idx]), sizeof(unsigned int));
5142 }
5143
5144 snd_hda_power_down(codec);
5145
5146 return 0;
5147}
5148
5149static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5150 struct snd_ctl_elem_value *ucontrol)
5151{
5152 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5153 struct ca0132_spec *spec = codec->spec;
5154 long *valp = ucontrol->value.integer.value;
5155
5156 *valp = spec->xbass_xover_freq;
5157 return 0;
5158}
5159
5160static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5161 struct snd_ctl_elem_value *ucontrol)
5162{
5163 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5164 struct ca0132_spec *spec = codec->spec;
5165 hda_nid_t nid = get_amp_nid(kcontrol);
5166 long *valp = ucontrol->value.integer.value;
5167 int idx = nid - OUT_EFFECT_START_NID;
5168
5169 *valp = spec->fx_ctl_val[idx];
5170 return 0;
5171}
5172
5173/*
5174 * The X-bass crossover starts at 10hz, so the min is 1. The
5175 * frequency is set in multiples of 10.
5176 */
5177static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5178 struct snd_ctl_elem_info *uinfo)
5179{
5180 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5181 uinfo->count = 1;
5182 uinfo->value.integer.min = 1;
5183 uinfo->value.integer.max = 100;
5184 uinfo->value.integer.step = 1;
5185
5186 return 0;
5187}
5188
5189static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5190 struct snd_ctl_elem_info *uinfo)
5191{
5192 int chs = get_amp_channels(kcontrol);
5193
5194 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5195 uinfo->count = chs == 3 ? 2 : 1;
5196 uinfo->value.integer.min = 0;
5197 uinfo->value.integer.max = 100;
5198 uinfo->value.integer.step = 1;
5199
5200 return 0;
5201}
5202
5203static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5204 struct snd_ctl_elem_value *ucontrol)
5205{
5206 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5207 struct ca0132_spec *spec = codec->spec;
5208 hda_nid_t nid = get_amp_nid(kcontrol);
5209 long *valp = ucontrol->value.integer.value;
5210 int idx;
5211
5212 /* any change? */
5213 if (spec->xbass_xover_freq == *valp)
5214 return 0;
5215
5216 spec->xbass_xover_freq = *valp;
5217
5218 idx = *valp;
5219 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5220
5221 return 0;
5222}
5223
5224static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5225 struct snd_ctl_elem_value *ucontrol)
5226{
5227 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5228 struct ca0132_spec *spec = codec->spec;
5229 hda_nid_t nid = get_amp_nid(kcontrol);
5230 long *valp = ucontrol->value.integer.value;
5231 int idx;
5232
5233 idx = nid - EFFECT_START_NID;
5234 /* any change? */
5235 if (spec->fx_ctl_val[idx] == *valp)
5236 return 0;
5237
5238 spec->fx_ctl_val[idx] = *valp;
5239
5240 idx = *valp;
5241 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5242
5243 return 0;
5244}
5245
5246
5247/*
5248 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5249 * only has off or full 30 dB, and didn't like making a volume slider that has
5250 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5251 */
5252#define MIC_BOOST_NUM_OF_STEPS 4
5253#define MIC_BOOST_ENUM_MAX_STRLEN 10
5254
5255static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5256 struct snd_ctl_elem_info *uinfo)
5257{
5258 char *sfx = "dB";
5259 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5260
5261 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5262 uinfo->count = 1;
5263 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5264 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5265 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5266 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5267 strcpy(uinfo->value.enumerated.name, namestr);
5268 return 0;
5269}
5270
5271static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5272 struct snd_ctl_elem_value *ucontrol)
5273{
5274 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5275 struct ca0132_spec *spec = codec->spec;
5276
5277 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5278 return 0;
5279}
5280
5281static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5282 struct snd_ctl_elem_value *ucontrol)
5283{
5284 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5285 struct ca0132_spec *spec = codec->spec;
5286 int sel = ucontrol->value.enumerated.item[0];
5287 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5288
5289 if (sel >= items)
5290 return 0;
5291
5292 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5293 sel);
5294
5295 spec->mic_boost_enum_val = sel;
5296
5297 if (spec->in_enum_val != REAR_LINE_IN)
5298 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5299
5300 return 1;
5301}
5302
212de2e7
CM		 5303/*
5304 * Sound BlasterX AE-5 Headphone Gain Controls.
5305 */
5306#define AE5_HEADPHONE_GAIN_MAX 3
5307static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5308 struct snd_ctl_elem_info *uinfo)
5309{
5310 char *sfx = " Ohms)";
5311 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5312
5313 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5314 uinfo->count = 1;
5315 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5316 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5317 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5318 sprintf(namestr, "%s %s",
5319 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5320 sfx);
5321 strcpy(uinfo->value.enumerated.name, namestr);
5322 return 0;
5323}
5324
5325static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5326 struct snd_ctl_elem_value *ucontrol)
5327{
5328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5329 struct ca0132_spec *spec = codec->spec;
5330
5331 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5332 return 0;
5333}
5334
5335static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5336 struct snd_ctl_elem_value *ucontrol)
5337{
5338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5339 struct ca0132_spec *spec = codec->spec;
5340 int sel = ucontrol->value.enumerated.item[0];
5341 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5342
5343 if (sel >= items)
5344 return 0;
5345
5346 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5347 sel);
5348
5349 spec->ae5_headphone_gain_val = sel;
5350
5351 if (spec->out_enum_val == HEADPHONE_OUT)
5352 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5353
5354 return 1;
5355}
5356
5357/*
5358 * Sound BlasterX AE-5 sound filter enumerated control.
5359 */
5360#define AE5_SOUND_FILTER_MAX 3
5361
5362static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5363 struct snd_ctl_elem_info *uinfo)
5364{
5365 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5366
5367 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5368 uinfo->count = 1;
5369 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5370 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5371 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5372 sprintf(namestr, "%s",
5373 ae5_filter_presets[uinfo->value.enumerated.item].name);
5374 strcpy(uinfo->value.enumerated.name, namestr);
5375 return 0;
5376}
5377
5378static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5379 struct snd_ctl_elem_value *ucontrol)
5380{
5381 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5382 struct ca0132_spec *spec = codec->spec;
5383
5384 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5385 return 0;
5386}
5387
5388static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5389 struct snd_ctl_elem_value *ucontrol)
5390{
5391 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5392 struct ca0132_spec *spec = codec->spec;
5393 int sel = ucontrol->value.enumerated.item[0];
5394 unsigned int items = AE5_SOUND_FILTER_MAX;
5395
5396 if (sel >= items)
5397 return 0;
5398
5399 codec_dbg(codec, "ae5_sound_filter: %s\n",
5400 ae5_filter_presets[sel].name);
5401
5402 spec->ae5_filter_val = sel;
5403
5404 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5405 ae5_filter_presets[sel].val);
5406
5407 return 1;
5408}
95c6e9cb 5409
7cb9d94c
CM		 5410/*
5411 * Input Select Control for alternative ca0132 codecs. This exists because
5412 * front microphone has no auto-detect, and we need a way to set the rear
5413 * as line-in
5414 */
5415static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5416 struct snd_ctl_elem_info *uinfo)
5417{
5418 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5419 uinfo->count = 1;
5420 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5421 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5422 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5423 strcpy(uinfo->value.enumerated.name,
5424 in_src_str[uinfo->value.enumerated.item]);
5425 return 0;
5426}
5427
5428static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5429 struct snd_ctl_elem_value *ucontrol)
5430{
5431 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5432 struct ca0132_spec *spec = codec->spec;
5433
5434 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5435 return 0;
5436}
5437
5438static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5439 struct snd_ctl_elem_value *ucontrol)
5440{
5441 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5442 struct ca0132_spec *spec = codec->spec;
5443 int sel = ucontrol->value.enumerated.item[0];
5444 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5445
5446 if (sel >= items)
5447 return 0;
5448
5449 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5450 sel, in_src_str[sel]);
5451
5452 spec->in_enum_val = sel;
5453
5454 ca0132_alt_select_in(codec);
5455
5456 return 1;
5457}
5458
5459/* Sound Blaster Z Output Select Control */
5460static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5461 struct snd_ctl_elem_info *uinfo)
5462{
5463 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5464 uinfo->count = 1;
5465 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5466 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5467 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5468 strcpy(uinfo->value.enumerated.name,
5469 alt_out_presets[uinfo->value.enumerated.item].name);
5470 return 0;
5471}
5472
5473static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5474 struct snd_ctl_elem_value *ucontrol)
5475{
5476 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5477 struct ca0132_spec *spec = codec->spec;
5478
5479 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5480 return 0;
5481}
5482
5483static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5484 struct snd_ctl_elem_value *ucontrol)
5485{
5486 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5487 struct ca0132_spec *spec = codec->spec;
5488 int sel = ucontrol->value.enumerated.item[0];
5489 unsigned int items = NUM_OF_OUTPUTS;
5490 unsigned int auto_jack;
5491
5492 if (sel >= items)
5493 return 0;
5494
5495 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5496 sel, alt_out_presets[sel].name);
5497
5498 spec->out_enum_val = sel;
5499
5500 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5501
5502 if (!auto_jack)
5503 ca0132_alt_select_out(codec);
5504
5505 return 1;
5506}
5507
47cdf76e
CM		 5508/*
5509 * Smart Volume output setting control. Three different settings, Normal,
5510 * which takes the value from the smart volume slider. The two others, loud
5511 * and night, disregard the slider value and have uneditable values.
5512 */
5513#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5514static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5515
5516static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5517 struct snd_ctl_elem_info *uinfo)
5518{
5519 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5520 uinfo->count = 1;
5521 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5522 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5523 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5524 strcpy(uinfo->value.enumerated.name,
5525 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5526 return 0;
5527}
5528
5529static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5530 struct snd_ctl_elem_value *ucontrol)
5531{
5532 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5533 struct ca0132_spec *spec = codec->spec;
5534
5535 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5536 return 0;
5537}
5538
5539static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5540 struct snd_ctl_elem_value *ucontrol)
5541{
5542 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5543 struct ca0132_spec *spec = codec->spec;
5544 int sel = ucontrol->value.enumerated.item[0];
5545 unsigned int items = NUM_OF_SVM_SETTINGS;
5546 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5547 unsigned int tmp;
5548
5549 if (sel >= items)
5550 return 0;
5551
5552 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5553 sel, out_svm_set_enum_str[sel]);
5554
5555 spec->smart_volume_setting = sel;
5556
5557 switch (sel) {
5558 case 0:
5559 tmp = FLOAT_ZERO;
5560 break;
5561 case 1:
5562 tmp = FLOAT_ONE;
5563 break;
5564 case 2:
5565 tmp = FLOAT_TWO;
5566 break;
5567 default:
5568 tmp = FLOAT_ZERO;
5569 break;
5570 }
5571 /* Req 2 is the Smart Volume Setting req. */
5572 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5573 ca0132_effects[idx].reqs[2], tmp);
5574 return 1;
5575}
5576
5577/* Sound Blaster Z EQ preset controls */
5578static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5579 struct snd_ctl_elem_info *uinfo)
5580{
c5f13d75 5581 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5582
5583 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5584 uinfo->count = 1;
5585 uinfo->value.enumerated.items = items;
5586 if (uinfo->value.enumerated.item >= items)
5587 uinfo->value.enumerated.item = items - 1;
5588 strcpy(uinfo->value.enumerated.name,
5589 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5590 return 0;
5591}
5592
5593static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5594 struct snd_ctl_elem_value *ucontrol)
5595{
5596 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5597 struct ca0132_spec *spec = codec->spec;
5598
5599 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5600 return 0;
5601}
5602
5603static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5604 struct snd_ctl_elem_value *ucontrol)
5605{
5606 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5607 struct ca0132_spec *spec = codec->spec;
5608 int i, err = 0;
5609 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5610 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5611
5612 if (sel >= items)
5613 return 0;
5614
5615 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5616 ca0132_alt_eq_presets[sel].name);
5617 /*
5618 * Idx 0 is default.
5619 * Default needs to qualify with CrystalVoice state.
5620 */
5621 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5622 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5623 ca0132_alt_eq_enum.reqs[i],
5624 ca0132_alt_eq_presets[sel].vals[i]);
5625 if (err < 0)
5626 break;
5627 }
5628
5629 if (err >= 0)
5630 spec->eq_preset_val = sel;
5631
5632 return 1;
5633}
5634
a7e76271
IM		 5635static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5636 struct snd_ctl_elem_info *uinfo)
5637{
a9291f46 5638 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5639
5640 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5641 uinfo->count = 1;
5642 uinfo->value.enumerated.items = items;
5643 if (uinfo->value.enumerated.item >= items)
5644 uinfo->value.enumerated.item = items - 1;
5645 strcpy(uinfo->value.enumerated.name,
5646 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5647 return 0;
5648}
95c6e9cb 5649
a7e76271 5650static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5651 struct snd_ctl_elem_value *ucontrol)
5652{
5653 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5654 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5655
a7e76271 5656 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5657 return 0;
5658}
5659
a7e76271 5660static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5661 struct snd_ctl_elem_value *ucontrol)
5662{
5663 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5664 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5665 int i, err = 0;
5666 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5667
a9291f46 5668 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5669 return 0;
5670
4e76a883 5671 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5672 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5673
a7e76271
IM		 5674 /*
5675 * Idx 0 is default.
5676 * Default needs to qualify with CrystalVoice state.
5677 */
5678 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5679 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5680 ca0132_voicefx.reqs[i],
5681 ca0132_voicefx_presets[sel].vals[i]);
5682 if (err < 0)
5683 break;
5684 }
95c6e9cb 5685
a7e76271
IM		 5686 if (err >= 0) {
5687 spec->voicefx_val = sel;
5688 /* enable voice fx */
5689 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5690 }
95c6e9cb 5691
a7e76271 5692 return 1;
95c6e9cb
IM		 5693}
5694
a7e76271
IM		 5695static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5696 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5697{
5698 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5699 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5700 hda_nid_t nid = get_amp_nid(kcontrol);
5701 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5702 long *valp = ucontrol->value.integer.value;
5703
a7e76271
IM		 5704 /* vnode */
5705 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5706 if (ch & 1) {
5707 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5708 valp++;
5709 }
5710 if (ch & 2) {
5711 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5712 valp++;
5713 }
5714 return 0;
5715 }
5716
5717 /* effects, include PE and CrystalVoice */
5718 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5719 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5720 return 0;
5721 }
5722
5723 /* mic boost */
5724 if (nid == spec->input_pins[0]) {
5725 *valp = spec->cur_mic_boost;
5726 return 0;
5727 }
5728
95c6e9cb
IM		 5729 return 0;
5730}
5731
a7e76271
IM		 5732static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5733 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5734{
5735 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5736 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5737 hda_nid_t nid = get_amp_nid(kcontrol);
5738 int ch = get_amp_channels(kcontrol);
95c6e9cb 5739 long *valp = ucontrol->value.integer.value;
a7e76271 5740 int changed = 1;
95c6e9cb 5741
4e76a883 5742 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5743 nid, *valp);
95c6e9cb
IM		 5744
5745 snd_hda_power_up(codec);
a7e76271
IM		 5746 /* vnode */
5747 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5748 if (ch & 1) {
5749 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5750 valp++;
5751 }
5752 if (ch & 2) {
5753 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5754 valp++;
5755 }
5756 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5757 goto exit;
5758 }
95c6e9cb 5759
a7e76271
IM		 5760 /* PE */
5761 if (nid == PLAY_ENHANCEMENT) {
5762 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5763 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5764 goto exit;
a7e76271 5765 }
95c6e9cb 5766
a7e76271
IM		 5767 /* CrystalVoice */
5768 if (nid == CRYSTAL_VOICE) {
5769 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5770 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5771 goto exit;
a7e76271 5772 }
95c6e9cb 5773
a7e76271
IM		 5774 /* out and in effects */
5775 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5776 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5777 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5778 changed = ca0132_effects_set(codec, nid, *valp);
5779 goto exit;
5780 }
5781
5782 /* mic boost */
5783 if (nid == spec->input_pins[0]) {
5784 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 5785 if (spec->use_alt_functions) {
5786 if (spec->in_enum_val != REAR_LINE_IN)
5787 changed = ca0132_mic_boost_set(codec, *valp);
5788 } else {
5789 /* Mic boost does not apply to Digital Mic */
5790 if (spec->cur_mic_type != DIGITAL_MIC)
5791 changed = ca0132_mic_boost_set(codec, *valp);
5792 }
a7e76271 5793
a7e76271
IM		 5794 goto exit;
5795 }
95c6e9cb 5796
d51434d4
CM		 5797 if (nid == ZXR_HEADPHONE_GAIN) {
5798 spec->zxr_gain_set = *valp;
5799 if (spec->cur_out_type == HEADPHONE_OUT)
5800 changed = zxr_headphone_gain_set(codec, *valp);
5801 else
5802 changed = 0;
5803
5804 goto exit;
5805 }
5806
a7e76271 5807exit:
95c6e9cb 5808 snd_hda_power_down(codec);
a7e76271 5809 return changed;
95c6e9cb
IM		 5810}
5811
a7e76271
IM		 5812/*
5813 * Volume related
5814 */
017310fb
CM		 5815/*
5816 * Sets the internal DSP decibel level to match the DAC for output, and the
5817 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5818 * all alternative codecs set DSP playback volume.
5819 */
5820static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5821{
5822 struct ca0132_spec *spec = codec->spec;
5823 unsigned int dsp_dir;
5824 unsigned int lookup_val;
5825
5826 if (nid == VNID_SPK)
5827 dsp_dir = DSP_VOL_OUT;
5828 else
5829 dsp_dir = DSP_VOL_IN;
5830
5831 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5832
5833 dspio_set_uint_param(codec,
5834 ca0132_alt_vol_ctls[dsp_dir].mid,
5835 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5836 float_vol_db_lookup[lookup_val]);
5837
5838 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5839
5840 dspio_set_uint_param(codec,
5841 ca0132_alt_vol_ctls[dsp_dir].mid,
5842 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5843 float_vol_db_lookup[lookup_val]);
5844
5845 dspio_set_uint_param(codec,
5846 ca0132_alt_vol_ctls[dsp_dir].mid,
5847 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5848}
5849
a7e76271
IM		 5850static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5851 struct snd_ctl_elem_info *uinfo)
5852{
5853 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5854 struct ca0132_spec *spec = codec->spec;
5855 hda_nid_t nid = get_amp_nid(kcontrol);
5856 int ch = get_amp_channels(kcontrol);
5857 int dir = get_amp_direction(kcontrol);
5858 unsigned long pval;
5859 int err;
5860
5861 switch (nid) {
5862 case VNID_SPK:
5863 /* follow shared_out info */
5864 nid = spec->shared_out_nid;
5865 mutex_lock(&codec->control_mutex);
5866 pval = kcontrol->private_value;
5867 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5868 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5869 kcontrol->private_value = pval;
5870 mutex_unlock(&codec->control_mutex);
5871 break;
5872 case VNID_MIC:
5873 /* follow shared_mic info */
5874 nid = spec->shared_mic_nid;
5875 mutex_lock(&codec->control_mutex);
5876 pval = kcontrol->private_value;
5877 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5878 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5879 kcontrol->private_value = pval;
5880 mutex_unlock(&codec->control_mutex);
5881 break;
5882 default:
5883 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5884 }
5885 return err;
5886}
5887
5888static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5889 struct snd_ctl_elem_value *ucontrol)
5890{
5891 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5892 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5893 hda_nid_t nid = get_amp_nid(kcontrol);
5894 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5895 long *valp = ucontrol->value.integer.value;
5896
a7e76271
IM		 5897 /* store the left and right volume */
5898 if (ch & 1) {
5899 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5900 valp++;
5901 }
5902 if (ch & 2) {
5903 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5904 valp++;
5905 }
95c6e9cb
IM		 5906 return 0;
5907}
5908
a7e76271 5909static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5910 struct snd_ctl_elem_value *ucontrol)
5911{
5912 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5913 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5914 hda_nid_t nid = get_amp_nid(kcontrol);
5915 int ch = get_amp_channels(kcontrol);
95c6e9cb 5916 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5917 hda_nid_t shared_nid = 0;
5918 bool effective;
5919 int changed = 1;
5920
5921 /* store the left and right volume */
5922 if (ch & 1) {
5923 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5924 valp++;
5925 }
5926 if (ch & 2) {
5927 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5928 valp++;
5929 }
95c6e9cb 5930
a7e76271
IM		 5931 /* if effective conditions, then update hw immediately. */
5932 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5933 if (effective) {
5934 int dir = get_amp_direction(kcontrol);
5935 unsigned long pval;
5936
5937 snd_hda_power_up(codec);
5938 mutex_lock(&codec->control_mutex);
5939 pval = kcontrol->private_value;
5940 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5941 0, dir);
5942 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5943 kcontrol->private_value = pval;
5944 mutex_unlock(&codec->control_mutex);
5945 snd_hda_power_down(codec);
5946 }
95c6e9cb 5947
a7e76271 5948 return changed;
95c6e9cb
IM		 5949}
5950
017310fb
CM		 5951/*
5952 * This function is the same as the one above, because using an if statement
5953 * inside of the above volume control for the DSP volume would cause too much
5954 * lag. This is a lot more smooth.
5955 */
5956static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5957 struct snd_ctl_elem_value *ucontrol)
5958{
5959 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5960 struct ca0132_spec *spec = codec->spec;
5961 hda_nid_t nid = get_amp_nid(kcontrol);
5962 int ch = get_amp_channels(kcontrol);
5963 long *valp = ucontrol->value.integer.value;
5964 hda_nid_t vnid = 0;
5965 int changed = 1;
5966
5967 switch (nid) {
5968 case 0x02:
5969 vnid = VNID_SPK;
5970 break;
5971 case 0x07:
5972 vnid = VNID_MIC;
5973 break;
5974 }
5975
5976 /* store the left and right volume */
5977 if (ch & 1) {
5978 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5979 valp++;
5980 }
5981 if (ch & 2) {
5982 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5983 valp++;
5984 }
5985
5986 snd_hda_power_up(codec);
5987 ca0132_alt_dsp_volume_put(codec, vnid);
5988 mutex_lock(&codec->control_mutex);
5989 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5990 mutex_unlock(&codec->control_mutex);
5991 snd_hda_power_down(codec);
5992
5993 return changed;
5994}
5995
a7e76271
IM		 5996static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5997 unsigned int size, unsigned int __user *tlv)
95c6e9cb 5998{
a7e76271
IM		 5999 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6000 struct ca0132_spec *spec = codec->spec;
6001 hda_nid_t nid = get_amp_nid(kcontrol);
6002 int ch = get_amp_channels(kcontrol);
6003 int dir = get_amp_direction(kcontrol);
6004 unsigned long pval;
6005 int err;
6006
6007 switch (nid) {
6008 case VNID_SPK:
6009 /* follow shared_out tlv */
6010 nid = spec->shared_out_nid;
6011 mutex_lock(&codec->control_mutex);
6012 pval = kcontrol->private_value;
6013 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6014 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6015 kcontrol->private_value = pval;
6016 mutex_unlock(&codec->control_mutex);
6017 break;
6018 case VNID_MIC:
6019 /* follow shared_mic tlv */
6020 nid = spec->shared_mic_nid;
6021 mutex_lock(&codec->control_mutex);
6022 pval = kcontrol->private_value;
6023 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6024 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6025 kcontrol->private_value = pval;
6026 mutex_unlock(&codec->control_mutex);
6027 break;
6028 default:
6029 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6030 }
6031 return err;
95c6e9cb
IM		 6032}
6033
47cdf76e
CM		 6034/* Add volume slider control for effect level */
6035static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6036 const char *pfx, int dir)
6037{
47cdf76e
CM		 6038 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6039 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6040 struct snd_kcontrol_new knew =
6041 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6042
0cc1aa71 6043 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 6044
bb86124c 6045 knew.tlv.c = NULL;
47cdf76e
CM		 6046
6047 switch (nid) {
6048 case XBASS_XOVER:
6049 knew.info = ca0132_alt_xbass_xover_slider_info;
6050 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6051 knew.put = ca0132_alt_xbass_xover_slider_put;
6052 break;
6053 default:
6054 knew.info = ca0132_alt_effect_slider_info;
6055 knew.get = ca0132_alt_slider_ctl_get;
6056 knew.put = ca0132_alt_effect_slider_put;
6057 knew.private_value =
6058 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6059 break;
6060 }
6061
6062 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6063}
6064
6065/*
6066 * Added FX: prefix for the alternative codecs, because otherwise the surround
6067 * effect would conflict with the Surround sound volume control. Also seems more
6068 * clear as to what the switches do. Left alone for others.
6069 */
a7e76271
IM		 6070static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6071 const char *pfx, int dir)
95c6e9cb 6072{
47cdf76e 6073 struct ca0132_spec *spec = codec->spec;
975cc02a 6074 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 6075 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 6076 struct snd_kcontrol_new knew =
a7e76271 6077 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 6078 /* If using alt_controls, add FX: prefix. But, don't add FX:
6079 * prefix to OutFX or InFX enable controls.
6080 */
6081 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 6082 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 6083 else
6084 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6085
95c6e9cb
IM		 6086 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6087}
6088
a7e76271 6089static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 6090{
6091 struct snd_kcontrol_new knew =
a7e76271
IM		 6092 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6093 VOICEFX, 1, 0, HDA_INPUT);
6094 knew.info = ca0132_voicefx_info;
6095 knew.get = ca0132_voicefx_get;
6096 knew.put = ca0132_voicefx_put;
6097 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 6098}
6099
47cdf76e
CM		 6100/* Create the EQ Preset control */
6101static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6102{
6103 struct snd_kcontrol_new knew =
6104 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6105 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6106 knew.info = ca0132_alt_eq_preset_info;
6107 knew.get = ca0132_alt_eq_preset_get;
6108 knew.put = ca0132_alt_eq_preset_put;
6109 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6110 snd_ctl_new1(&knew, codec));
6111}
6112
6113/*
6114 * Add enumerated control for the three different settings of the smart volume
6115 * output effect. Normal just uses the slider value, and loud and night are
6116 * their own things that ignore that value.
6117 */
6118static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6119{
6120 struct snd_kcontrol_new knew =
6121 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6122 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6123 knew.info = ca0132_alt_svm_setting_info;
6124 knew.get = ca0132_alt_svm_setting_get;
6125 knew.put = ca0132_alt_svm_setting_put;
6126 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6127 snd_ctl_new1(&knew, codec));
6128
6129}
6130
7cb9d94c
CM		 6131/*
6132 * Create an Output Select enumerated control for codecs with surround
6133 * out capabilities.
6134 */
6135static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6136{
6137 struct snd_kcontrol_new knew =
6138 HDA_CODEC_MUTE_MONO("Output Select",
6139 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6140 knew.info = ca0132_alt_output_select_get_info;
6141 knew.get = ca0132_alt_output_select_get;
6142 knew.put = ca0132_alt_output_select_put;
6143 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6144 snd_ctl_new1(&knew, codec));
6145}
6146
6147/*
6148 * Create an Input Source enumerated control for the alternate ca0132 codecs
6149 * because the front microphone has no auto-detect, and Line-in has to be set
6150 * somehow.
6151 */
6152static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6153{
6154 struct snd_kcontrol_new knew =
6155 HDA_CODEC_MUTE_MONO("Input Source",
6156 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6157 knew.info = ca0132_alt_input_source_info;
6158 knew.get = ca0132_alt_input_source_get;
6159 knew.put = ca0132_alt_input_source_put;
6160 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6161 snd_ctl_new1(&knew, codec));
6162}
6163
47cdf76e
CM		 6164/*
6165 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6166 * more control than the original mic boost, which is either full 30dB or off.
6167 */
6168static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6169{
6170 struct snd_kcontrol_new knew =
6171 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6172 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6173 knew.info = ca0132_alt_mic_boost_info;
6174 knew.get = ca0132_alt_mic_boost_get;
6175 knew.put = ca0132_alt_mic_boost_put;
6176 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6177 snd_ctl_new1(&knew, codec));
6178
6179}
6180
212de2e7
CM		 6181/*
6182 * Add headphone gain enumerated control for the AE-5. This switches between
6183 * three modes, low, medium, and high. When non-headphone outputs are selected,
6184 * it is automatically set to high. This is the same behavior as Windows.
6185 */
6186static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6187{
6188 struct snd_kcontrol_new knew =
6189 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
4b432ad4 6190 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6191 knew.info = ae5_headphone_gain_info;
6192 knew.get = ae5_headphone_gain_get;
6193 knew.put = ae5_headphone_gain_put;
6194 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6195 snd_ctl_new1(&knew, codec));
6196}
6197
6198/*
6199 * Add sound filter enumerated control for the AE-5. This adds three different
6200 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6201 * read into it, it changes the DAC's interpolation filter.
6202 */
6203static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6204{
6205 struct snd_kcontrol_new knew =
6206 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
4b432ad4 6207 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6208 knew.info = ae5_sound_filter_info;
6209 knew.get = ae5_sound_filter_get;
6210 knew.put = ae5_sound_filter_put;
6211 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6212 snd_ctl_new1(&knew, codec));
6213}
6214
d51434d4
CM		 6215static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6216{
6217 struct snd_kcontrol_new knew =
6218 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6219 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6220
6221 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6222 snd_ctl_new1(&knew, codec));
6223}
6224
47cdf76e
CM		 6225/*
6226 * Need to create slave controls for the alternate codecs that have surround
6227 * capabilities.
6228 */
6229static const char * const ca0132_alt_slave_pfxs[] = {
6230 "Front", "Surround", "Center", "LFE", NULL,
6231};
6232
6233/*
6234 * Also need special channel map, because the default one is incorrect.
6235 * I think this has to do with the pin for rear surround being 0x11,
6236 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6237 */
9c4a665e 6238static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 6239 { .channels = 2,
6240 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6241 { .channels = 4,
6242 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6243 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6244 { .channels = 6,
6245 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6246 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6247 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6248 { }
6249};
6250
6251/* Add the correct chmap for streams with 6 channels. */
6252static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6253{
6254 int err = 0;
6255 struct hda_pcm *pcm;
6256
6257 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6258 struct hda_pcm_stream *hinfo =
6259 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6260 struct snd_pcm_chmap *chmap;
6261 const struct snd_pcm_chmap_elem *elem;
6262
6263 elem = ca0132_alt_chmaps;
6264 if (hinfo->channels_max == 6) {
6265 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6266 SNDRV_PCM_STREAM_PLAYBACK,
6267 elem, hinfo->channels_max, 0, &chmap);
6268 if (err < 0)
6269 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6270 }
6271 }
6272}
6273
a7e76271
IM		 6274/*
6275 * When changing Node IDs for Mixer Controls below, make sure to update
6276 * Node IDs in ca0132_config() as well.
6277 */
b0eaa072 6278static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 6279 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6280 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6281 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6282 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6283 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6284 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6285 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6286 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6287 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6288 0x12, 1, HDA_INPUT),
6289 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6290 VNID_HP_SEL, 1, HDA_OUTPUT),
6291 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6292 VNID_AMIC1_SEL, 1, HDA_INPUT),
6293 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6294 VNID_HP_ASEL, 1, HDA_OUTPUT),
6295 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6296 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6297 { } /* end */
6298};
6299
017310fb 6300/*
e25e3445
CM		 6301 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6302 * surround controls. Also sets both the Front Playback and Capture Volume
6303 * controls to alt so they set the DSP's decibel level.
017310fb 6304 */
e25e3445 6305static const struct snd_kcontrol_new desktop_mixer[] = {
017310fb
CM		 6306 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6307 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6308 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6309 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6310 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6311 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6312 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6313 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6314 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6315 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6316 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6317 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6318 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6319 VNID_HP_ASEL, 1, HDA_OUTPUT),
6320 { } /* end */
6321};
6322
6323/*
6324 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6325 * because it doesn't set decibel levels for the DSP for capture.
6326 */
b0eaa072 6327static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 6328 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6329 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6330 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6331 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6332 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6333 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6334 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6335 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6336 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6337 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6338 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6339 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6340 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6341 VNID_HP_ASEL, 1, HDA_OUTPUT),
6342 { } /* end */
6343};
6344
e90f29e4
IM		 6345static int ca0132_build_controls(struct hda_codec *codec)
6346{
6347 struct ca0132_spec *spec = codec->spec;
47cdf76e 6348 int i, num_fx, num_sliders;
e90f29e4
IM		 6349 int err = 0;
6350
6351 /* Add Mixer controls */
6352 for (i = 0; i < spec->num_mixers; i++) {
6353 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6354 if (err < 0)
6355 return err;
6356 }
47cdf76e
CM		 6357 /* Setup vmaster with surround slaves for desktop ca0132 devices */
6358 if (spec->use_alt_functions) {
6359 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6360 spec->tlv);
6361 snd_hda_add_vmaster(codec, "Master Playback Volume",
6362 spec->tlv, ca0132_alt_slave_pfxs,
6363 "Playback Volume");
6364 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6365 NULL, ca0132_alt_slave_pfxs,
6366 "Playback Switch",
6367 true, &spec->vmaster_mute.sw_kctl);
6368
6369 }
e90f29e4
IM		 6370
6371 /* Add in and out effects controls.
6372 * VoiceFX, PE and CrystalVoice are added separately.
6373 */
6374 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6375 for (i = 0; i < num_fx; i++) {
e25e3445
CM		 6376 /* SBZ and R3D break if Echo Cancellation is used. */
6377 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D) {
47cdf76e
CM		 6378 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6379 OUT_EFFECTS_COUNT))
6380 continue;
6381 }
6382
e90f29e4
IM		 6383 err = add_fx_switch(codec, ca0132_effects[i].nid,
6384 ca0132_effects[i].name,
6385 ca0132_effects[i].direct);
6386 if (err < 0)
6387 return err;
6388 }
47cdf76e
CM		 6389 /*
6390 * If codec has use_alt_controls set to true, add effect level sliders,
6391 * EQ presets, and Smart Volume presets. Also, change names to add FX
6392 * prefix, and change PlayEnhancement and CrystalVoice to match.
6393 */
6394 if (spec->use_alt_controls) {
6395 ca0132_alt_add_svm_enum(codec);
6396 add_ca0132_alt_eq_presets(codec);
6397 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6398 "Enable OutFX", 0);
6399 if (err < 0)
6400 return err;
e90f29e4 6401
47cdf76e
CM		 6402 err = add_fx_switch(codec, CRYSTAL_VOICE,
6403 "Enable InFX", 1);
6404 if (err < 0)
6405 return err;
e90f29e4 6406
47cdf76e
CM		 6407 num_sliders = OUT_EFFECTS_COUNT - 1;
6408 for (i = 0; i < num_sliders; i++) {
6409 err = ca0132_alt_add_effect_slider(codec,
6410 ca0132_effects[i].nid,
6411 ca0132_effects[i].name,
6412 ca0132_effects[i].direct);
6413 if (err < 0)
6414 return err;
6415 }
6416
6417 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6418 "X-Bass Crossover", EFX_DIR_OUT);
6419
6420 if (err < 0)
6421 return err;
6422 } else {
6423 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6424 "PlayEnhancement", 0);
6425 if (err < 0)
6426 return err;
e90f29e4 6427
47cdf76e
CM		 6428 err = add_fx_switch(codec, CRYSTAL_VOICE,
6429 "CrystalVoice", 1);
6430 if (err < 0)
6431 return err;
6432 }
e90f29e4
IM		 6433 add_voicefx(codec);
6434
7cb9d94c
CM		 6435 /*
6436 * If the codec uses alt_functions, you need the enumerated controls
6437 * to select the new outputs and inputs, plus add the new mic boost
6438 * setting control.
6439 */
6440 if (spec->use_alt_functions) {
6441 ca0132_alt_add_output_enum(codec);
47cdf76e 6442 ca0132_alt_add_mic_boost_enum(codec);
76dea4db
CM		 6443 /*
6444 * ZxR only has microphone input, there is no front panel
6445 * header on the card, and aux-in is handled by the DBPro board.
6446 */
6447 if (spec->quirk != QUIRK_ZXR)
6448 ca0132_alt_add_input_enum(codec);
7cb9d94c 6449 }
212de2e7
CM		 6450
6451 if (spec->quirk == QUIRK_AE5) {
6452 ae5_add_headphone_gain_enum(codec);
6453 ae5_add_sound_filter_enum(codec);
6454 }
d51434d4
CM		 6455
6456 if (spec->quirk == QUIRK_ZXR)
6457 zxr_add_headphone_gain_switch(codec);
e90f29e4
IM		 6458#ifdef ENABLE_TUNING_CONTROLS
6459 add_tuning_ctls(codec);
6460#endif
6461
6462 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6463 if (err < 0)
6464 return err;
6465
6466 if (spec->dig_out) {
6467 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6468 spec->dig_out);
6469 if (err < 0)
6470 return err;
6471 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6472 if (err < 0)
6473 return err;
6474 /* spec->multiout.share_spdif = 1; */
6475 }
6476
6477 if (spec->dig_in) {
6478 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6479 if (err < 0)
6480 return err;
6481 }
47cdf76e
CM		 6482
6483 if (spec->use_alt_functions)
6484 ca0132_alt_add_chmap_ctls(codec);
6485
e90f29e4
IM		 6486 return 0;
6487}
6488
7675a2a9
CM		 6489static int dbpro_build_controls(struct hda_codec *codec)
6490{
6491 struct ca0132_spec *spec = codec->spec;
6492 int err = 0;
6493
6494 if (spec->dig_out) {
6495 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6496 spec->dig_out);
6497 if (err < 0)
6498 return err;
6499 }
6500
6501 if (spec->dig_in) {
6502 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6503 if (err < 0)
6504 return err;
6505 }
6506
6507 return 0;
6508}
6509
a7e76271 6510/*
e90f29e4 6511 * PCM
a7e76271 6512 */
071f1344 6513static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 6514 .substreams = 1,
6515 .channels_min = 2,
825315bc 6516 .channels_max = 6,
a7e76271 6517 .ops = {
a7e76271 6518 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 6519 .cleanup = ca0132_playback_pcm_cleanup,
6520 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 6521 },
6522};
6523
071f1344 6524static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 6525 .substreams = 1,
6526 .channels_min = 2,
6527 .channels_max = 2,
825315bc
IM		 6528 .ops = {
6529 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 6530 .cleanup = ca0132_capture_pcm_cleanup,
6531 .get_delay = ca0132_capture_pcm_delay,
825315bc 6532 },
a7e76271
IM		 6533};
6534
071f1344 6535static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 6536 .substreams = 1,
6537 .channels_min = 2,
6538 .channels_max = 2,
6539 .ops = {
6540 .open = ca0132_dig_playback_pcm_open,
6541 .close = ca0132_dig_playback_pcm_close,
6542 .prepare = ca0132_dig_playback_pcm_prepare,
6543 .cleanup = ca0132_dig_playback_pcm_cleanup
6544 },
6545};
6546
071f1344 6547static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 6548 .substreams = 1,
6549 .channels_min = 2,
6550 .channels_max = 2,
6551};
6552
6553static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 6554{
6555 struct ca0132_spec *spec = codec->spec;
bbbc7e85 6556 struct hda_pcm *info;
a7e76271 6557
bbbc7e85
TI		 6558 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6559 if (!info)
6560 return -ENOMEM;
47cdf76e
CM		 6561 if (spec->use_alt_functions) {
6562 info->own_chmap = true;
6563 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6564 = ca0132_alt_chmaps;
6565 }
a7e76271
IM		 6566 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6567 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6568 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6569 spec->multiout.max_channels;
6570 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 6571 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 6572 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 6573
009b8f97 6574 /* With the DSP enabled, desktops don't use this ADC. */
5f8ddc6e 6575 if (!spec->use_alt_functions) {
009b8f97
CM		 6576 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6577 if (!info)
6578 return -ENOMEM;
6579 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6580 ca0132_pcm_analog_capture;
6581 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6582 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6583 }
825315bc 6584
bbbc7e85
TI		 6585 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6586 if (!info)
6587 return -ENOMEM;
825315bc
IM		 6588 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6589 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6590 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6591
a7e76271
IM		 6592 if (!spec->dig_out && !spec->dig_in)
6593 return 0;
6594
bbbc7e85
TI		 6595 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6596 if (!info)
6597 return -ENOMEM;
a7e76271
IM		 6598 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6599 if (spec->dig_out) {
6600 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6601 ca0132_pcm_digital_playback;
6602 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6603 }
6604 if (spec->dig_in) {
6605 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6606 ca0132_pcm_digital_capture;
6607 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6608 }
95c6e9cb 6609
a7e76271 6610 return 0;
95c6e9cb
IM		 6611}
6612
7675a2a9
CM		 6613static int dbpro_build_pcms(struct hda_codec *codec)
6614{
6615 struct ca0132_spec *spec = codec->spec;
6616 struct hda_pcm *info;
6617
6618 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
6619 if (!info)
6620 return -ENOMEM;
6621 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6622 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6623 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6624
6625
6626 if (!spec->dig_out && !spec->dig_in)
6627 return 0;
6628
6629 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6630 if (!info)
6631 return -ENOMEM;
6632 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6633 if (spec->dig_out) {
6634 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6635 ca0132_pcm_digital_playback;
6636 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6637 }
6638 if (spec->dig_in) {
6639 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6640 ca0132_pcm_digital_capture;
6641 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6642 }
6643
6644 return 0;
6645}
6646
441aa6a0
IM		 6647static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6648{
6649 if (pin) {
a0c041cb 6650 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6651 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6652 snd_hda_codec_write(codec, pin, 0,
6653 AC_VERB_SET_AMP_GAIN_MUTE,
6654 AMP_OUT_UNMUTE);
6655 }
6656 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6657 snd_hda_codec_write(codec, dac, 0,
6658 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6659}
6660
6661static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6662{
6663 if (pin) {
a0c041cb 6664 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6665 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6666 snd_hda_codec_write(codec, pin, 0,
6667 AC_VERB_SET_AMP_GAIN_MUTE,
6668 AMP_IN_UNMUTE(0));
6669 }
6670 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6671 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6672 AMP_IN_UNMUTE(0));
6673
6674 /* init to 0 dB and unmute. */
6675 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6676 HDA_AMP_VOLMASK, 0x5a);
6677 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6678 HDA_AMP_MUTE, 0);
6679 }
6680}
6681
5aaca44d
IM		 6682static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6683{
6684 unsigned int caps;
6685
6686 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6687 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6688 snd_hda_override_amp_caps(codec, nid, dir, caps);
6689}
6690
6691/*
6692 * Switch between Digital built-in mic and analog mic.
6693 */
6694static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6695{
6696 struct ca0132_spec *spec = codec->spec;
6697 unsigned int tmp;
6698 u8 val;
6699 unsigned int oldval;
6700
4e76a883 6701 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6702
6703 oldval = stop_mic1(codec);
6704 ca0132_set_vipsource(codec, 0);
6705 if (enable) {
6706 /* set DMic input as 2-ch */
6707 tmp = FLOAT_TWO;
6708 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6709
6710 val = spec->dmic_ctl;
6711 val |= 0x80;
6712 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6713 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6714
6715 if (!(spec->dmic_ctl & 0x20))
6716 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6717 } else {
6718 /* set AMic input as mono */
6719 tmp = FLOAT_ONE;
6720 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6721
6722 val = spec->dmic_ctl;
6723 /* clear bit7 and bit5 to disable dmic */
6724 val &= 0x5f;
6725 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6726 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6727
6728 if (!(spec->dmic_ctl & 0x20))
6729 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6730 }
6731 ca0132_set_vipsource(codec, 1);
6732 resume_mic1(codec, oldval);
6733}
6734
6735/*
6736 * Initialization for Digital Mic.
6737 */
6738static void ca0132_init_dmic(struct hda_codec *codec)
6739{
6740 struct ca0132_spec *spec = codec->spec;
6741 u8 val;
6742
6743 /* Setup Digital Mic here, but don't enable.
6744 * Enable based on jack detect.
6745 */
6746
6747 /* MCLK uses MPIO1, set to enable.
6748 * Bit 2-0: MPIO select
6749 * Bit 3: set to disable
6750 * Bit 7-4: reserved
6751 */
6752 val = 0x01;
6753 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6754 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6755
6756 /* Data1 uses MPIO3. Data2 not use
6757 * Bit 2-0: Data1 MPIO select
6758 * Bit 3: set disable Data1
6759 * Bit 6-4: Data2 MPIO select
6760 * Bit 7: set disable Data2
6761 */
6762 val = 0x83;
6763 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6764 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6765
6766 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6767 * Bit 3-0: Channel mask
6768 * Bit 4: set for 48KHz, clear for 32KHz
6769 * Bit 5: mode
6770 * Bit 6: set to select Data2, clear for Data1
6771 * Bit 7: set to enable DMic, clear for AMic
6772 */
a57a46b9
AB		 6773 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6774 val = 0x33;
6775 else
6776 val = 0x23;
5aaca44d
IM		 6777 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6778 spec->dmic_ctl = val;
6779 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6780 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6781}
6782
6783/*
6784 * Initialization for Analog Mic 2
6785 */
6786static void ca0132_init_analog_mic2(struct hda_codec *codec)
6787{
6788 struct ca0132_spec *spec = codec->spec;
6789
6790 mutex_lock(&spec->chipio_mutex);
6791 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6792 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6793 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6794 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6795 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6796 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6797 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6798 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6799 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6800 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6801 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6802 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6803 mutex_unlock(&spec->chipio_mutex);
6804}
6805
6806static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6807{
6808 struct ca0132_spec *spec = codec->spec;
6809 int i;
5aaca44d 6810
4e76a883 6811 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6812 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6813
6814 for (i = 0; i < spec->multiout.num_dacs; i++)
6815 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6816
6817 for (i = 0; i < spec->num_outputs; i++)
6818 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6819
6820 for (i = 0; i < spec->num_inputs; i++) {
6821 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6822 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6823 }
6824}
6825
7e6ed62e 6826/*
6ef0e91e
CM		 6827 * Creates a dummy stream to bind the output to. This seems to have to be done
6828 * after changing the main outputs source and destination streams.
7e6ed62e 6829 */
6ef0e91e 6830static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
447fd8e9 6831{
6ef0e91e
CM		 6832 struct ca0132_spec *spec = codec->spec;
6833 unsigned int stream_format;
447fd8e9 6834
6ef0e91e
CM		 6835 stream_format = snd_hdac_calc_stream_format(48000, 2,
6836 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7e6ed62e 6837
6ef0e91e
CM		 6838 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6839 0, stream_format);
7e6ed62e 6840
6ef0e91e 6841 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7e6ed62e
CM		 6842}
6843
38ba69ff 6844/*
6ef0e91e 6845 * Initialize mic for non-chromebook ca0132 implementations.
38ba69ff 6846 */
6ef0e91e 6847static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
38ba69ff 6848{
6ef0e91e 6849 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6850 unsigned int tmp;
6851
6852 /* Mic 1 Setup */
6853 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6854 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6ef0e91e
CM		 6855 if (spec->quirk == QUIRK_R3DI) {
6856 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6857 tmp = FLOAT_ONE;
6858 } else
6859 tmp = FLOAT_THREE;
38ba69ff
CM		 6860 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6861
6ef0e91e 6862 /* Mic 2 setup (not present on desktop cards) */
38ba69ff
CM		 6863 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6864 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6ef0e91e
CM		 6865 if (spec->quirk == QUIRK_R3DI)
6866 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
38ba69ff
CM		 6867 tmp = FLOAT_ZERO;
6868 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
38ba69ff
CM		 6869}
6870
6871/*
6872 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6873 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6874 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6875 * having an updated DAC, which changes the destination to that DAC.
6876 */
6877static void sbz_connect_streams(struct hda_codec *codec)
6878{
6879 struct ca0132_spec *spec = codec->spec;
6880
6881 mutex_lock(&spec->chipio_mutex);
6882
6883 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6884
6885 chipio_set_stream_channels(codec, 0x0C, 6);
6886 chipio_set_stream_control(codec, 0x0C, 1);
6887
6888 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6889 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6890
6891 /* Setup stream 0x14 with it's source and destination points */
6892 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6893 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6894 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6895 chipio_set_stream_channels(codec, 0x14, 2);
6896 chipio_set_stream_control(codec, 0x14, 1);
6897
6898 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6899
6900 mutex_unlock(&spec->chipio_mutex);
38ba69ff
CM		 6901}
6902
6903/*
6904 * Write data through ChipIO to setup proper stream destinations.
6905 * Not sure how it exactly works, but it seems to direct data
6906 * to different destinations. Example is f8 to c0, e0 to c0.
6907 * All I know is, if you don't set these, you get no sound.
6908 */
6909static void sbz_chipio_startup_data(struct hda_codec *codec)
6910{
6911 struct ca0132_spec *spec = codec->spec;
6912
6913 mutex_lock(&spec->chipio_mutex);
6914 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6915
6916 /* These control audio output */
6917 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6918 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6919 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6920 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6921 /* Signal to update I think */
6922 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6923
6924 chipio_set_stream_channels(codec, 0x0C, 6);
6925 chipio_set_stream_control(codec, 0x0C, 1);
6926 /* No clue what these control */
c25c73e0
CM		 6927 if (spec->quirk == QUIRK_SBZ) {
6928 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6929 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6930 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6931 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6932 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6933 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6934 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6935 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6936 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6937 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6938 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6939 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6940 } else if (spec->quirk == QUIRK_ZXR) {
6941 chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
6942 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
6943 chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
6944 chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
6945 chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
6946 chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
6947 chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
6948 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
6949 }
38ba69ff
CM		 6950 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6951
6952 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6953 mutex_unlock(&spec->chipio_mutex);
6954}
6955
447fd8e9 6956/*
6ef0e91e
CM		 6957 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
6958 * done after the DSP is loaded.
447fd8e9 6959 */
6ef0e91e 6960static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
447fd8e9 6961{
6ef0e91e 6962 struct ca0132_spec *spec = codec->spec;
447fd8e9
CM		 6963 unsigned int tmp;
6964
6ef0e91e
CM		 6965 switch (spec->quirk) {
6966 case QUIRK_SBZ:
6967 case QUIRK_AE5:
6968 tmp = 0x00000003;
6969 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6970 tmp = 0x00000000;
6971 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6972 tmp = 0x00000001;
6973 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6974 tmp = 0x00000004;
6975 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6976 tmp = 0x00000005;
6977 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6978 tmp = 0x00000000;
6979 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6980 break;
6981 case QUIRK_R3D:
6982 case QUIRK_R3DI:
6983 tmp = 0x00000000;
6984 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6985 tmp = 0x00000001;
6986 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6987 tmp = 0x00000004;
6988 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6989 tmp = 0x00000005;
6990 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6991 tmp = 0x00000000;
6992 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6993 break;
6994 }
447fd8e9
CM		 6995}
6996
6ef0e91e 6997static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
38ba69ff 6998{
6ef0e91e 6999 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 7000 unsigned int tmp;
7001
7002 chipio_set_stream_control(codec, 0x03, 0);
7003 chipio_set_stream_control(codec, 0x04, 0);
7004
7005 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7006 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7007
7008 tmp = FLOAT_THREE;
7009 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7010
7011 chipio_set_stream_control(codec, 0x03, 1);
7012 chipio_set_stream_control(codec, 0x04, 1);
7013
6ef0e91e
CM		 7014 switch (spec->quirk) {
7015 case QUIRK_SBZ:
7016 chipio_write(codec, 0x18b098, 0x0000000c);
7017 chipio_write(codec, 0x18b09C, 0x0000000c);
7018 break;
7019 case QUIRK_AE5:
7020 chipio_write(codec, 0x18b098, 0x0000000c);
7021 chipio_write(codec, 0x18b09c, 0x0000004c);
7022 break;
7023 }
38ba69ff
CM		 7024}
7025
415cd844
CM		 7026static void ae5_post_dsp_register_set(struct hda_codec *codec)
7027{
7028 struct ca0132_spec *spec = codec->spec;
7029
7030 chipio_8051_write_direct(codec, 0x93, 0x10);
7031 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7032 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7033 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7034 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7035
7036 writeb(0xff, spec->mem_base + 0x304);
7037 writeb(0xff, spec->mem_base + 0x304);
7038 writeb(0xff, spec->mem_base + 0x304);
7039 writeb(0xff, spec->mem_base + 0x304);
7040 writeb(0x00, spec->mem_base + 0x100);
7041 writeb(0xff, spec->mem_base + 0x304);
7042 writeb(0x00, spec->mem_base + 0x100);
7043 writeb(0xff, spec->mem_base + 0x304);
7044 writeb(0x00, spec->mem_base + 0x100);
7045 writeb(0xff, spec->mem_base + 0x304);
7046 writeb(0x00, spec->mem_base + 0x100);
7047 writeb(0xff, spec->mem_base + 0x304);
7048
7049 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7050 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7051 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7052}
7053
7054static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7055{
7056 /*
7057 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7058 * which seems to be 'multichannel'. This is also mentioned in the
7059 * AE-5's registry values in Windows.
7060 */
7061 chipio_set_control_param(codec, 3, 0);
7062 /*
7063 * I believe ASI is 'audio serial interface' and that it's used to
7064 * change colors on the external LED strip connected to the AE-5.
7065 */
7066 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7067
7068 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7069 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7070
7071 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7072 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
7073 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7074 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
7075 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7076 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
7077}
7078
7079static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7080{
7081 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7082 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7083 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7084 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7085
7086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7087 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7088 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7089 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7090
7091 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7092 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7093 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7094 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7095
7096 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7097 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7098 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7099 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7100
7101 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7102 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7103 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7104 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7105}
7106
7107static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7108{
7109 struct ca0132_spec *spec = codec->spec;
7110
7111 mutex_lock(&spec->chipio_mutex);
7112
7113 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7114
7115 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7116
7117 chipio_set_stream_channels(codec, 0x0C, 6);
7118 chipio_set_stream_control(codec, 0x0C, 1);
7119
7120 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7121
7122 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7123 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7124 chipio_set_stream_channels(codec, 0x18, 6);
7125 chipio_set_stream_control(codec, 0x18, 1);
7126
7127 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7128
7129 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7130 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7131 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7132 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7133
7134 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7135
7136 mutex_unlock(&spec->chipio_mutex);
7137}
7138
7139static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7140{
7141 struct ca0132_spec *spec = codec->spec;
7142
7143 mutex_lock(&spec->chipio_mutex);
7144
7145 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7146 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7147 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7148 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7149
7150 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7151 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7152 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7153 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7154 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7155 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7156 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7157 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7158 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7159 ca0113_mmio_gpio_set(codec, 0, true);
7160 ca0113_mmio_gpio_set(codec, 1, true);
7161 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7162
7163 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7164
7165 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7166 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7167
7168 mutex_unlock(&spec->chipio_mutex);
7169}
7170
5aaca44d
IM		 7171/*
7172 * Setup default parameters for DSP
7173 */
7174static void ca0132_setup_defaults(struct hda_codec *codec)
7175{
e8f1bd5d 7176 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7177 unsigned int tmp;
7178 int num_fx;
7179 int idx, i;
7180
e8f1bd5d 7181 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 7182 return;
7183
7184 /* out, in effects + voicefx */
7185 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7186 for (idx = 0; idx < num_fx; idx++) {
7187 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7188 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
7189 ca0132_effects[idx].reqs[i],
7190 ca0132_effects[idx].def_vals[i]);
7191 }
7192 }
7193
7194 /*remove DSP headroom*/
7195 tmp = FLOAT_ZERO;
7196 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7197
7198 /*set speaker EQ bypass attenuation*/
7199 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
7200
7201 /* set AMic1 and AMic2 as mono mic */
7202 tmp = FLOAT_ONE;
7203 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7204 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7205
7206 /* set AMic1 as CrystalVoice input */
7207 tmp = FLOAT_ONE;
7208 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
7209
7210 /* set WUH source */
7211 tmp = FLOAT_TWO;
7212 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7213}
7214
7e6ed62e 7215/*
c986f50c 7216 * Setup default parameters for Recon3D/Recon3Di DSP.
7e6ed62e
CM		 7217 */
7218
c986f50c 7219static void r3d_setup_defaults(struct hda_codec *codec)
7e6ed62e
CM		 7220{
7221 struct ca0132_spec *spec = codec->spec;
7222 unsigned int tmp;
7223 int num_fx;
7224 int idx, i;
7225
a88bcc8d
CM		 7226 msleep(100);
7227
7e6ed62e
CM		 7228 if (spec->dsp_state != DSP_DOWNLOADED)
7229 return;
7230
6ef0e91e
CM		 7231 ca0132_alt_dsp_scp_startup(codec);
7232 ca0132_alt_init_analog_mics(codec);
7e6ed62e
CM		 7233
7234 /*remove DSP headroom*/
7235 tmp = FLOAT_ZERO;
7236 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7237
7238 /* set WUH source */
7239 tmp = FLOAT_TWO;
7240 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7241 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7242
7243 /* Set speaker source? */
7244 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7245
c986f50c
CM		 7246 if (spec->quirk == QUIRK_R3DI)
7247 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7e6ed62e
CM		 7248
7249 /* Setup effect defaults */
7250 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7251 for (idx = 0; idx < num_fx; idx++) {
7252 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7253 dspio_set_uint_param(codec,
7254 ca0132_effects[idx].mid,
7255 ca0132_effects[idx].reqs[i],
7256 ca0132_effects[idx].def_vals[i]);
7257 }
7258 }
7e6ed62e
CM		 7259}
7260
38ba69ff
CM		 7261/*
7262 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
7263 * than the Chromebook setup.
7264 */
7265static void sbz_setup_defaults(struct hda_codec *codec)
7266{
7267 struct ca0132_spec *spec = codec->spec;
6ef0e91e 7268 unsigned int tmp;
38ba69ff
CM		 7269 int num_fx;
7270 int idx, i;
7271
a88bcc8d
CM		 7272 msleep(100);
7273
38ba69ff
CM		 7274 if (spec->dsp_state != DSP_DOWNLOADED)
7275 return;
7276
6ef0e91e
CM		 7277 ca0132_alt_dsp_scp_startup(codec);
7278 ca0132_alt_init_analog_mics(codec);
38ba69ff 7279 sbz_connect_streams(codec);
38ba69ff
CM		 7280 sbz_chipio_startup_data(codec);
7281
7282 chipio_set_stream_control(codec, 0x03, 1);
7283 chipio_set_stream_control(codec, 0x04, 1);
7284
7285 /*
7286 * Sets internal input loopback to off, used to have a switch to
7287 * enable input loopback, but turned out to be way too buggy.
7288 */
7289 tmp = FLOAT_ONE;
7290 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7291 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7292
7293 /*remove DSP headroom*/
7294 tmp = FLOAT_ZERO;
7295 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7296
7297 /* set WUH source */
7298 tmp = FLOAT_TWO;
7299 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7300 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7301
7302 /* Set speaker source? */
7303 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7304
6ef0e91e 7305 ca0132_alt_dsp_initial_mic_setup(codec);
38ba69ff
CM		 7306
7307 /* out, in effects + voicefx */
7308 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7309 for (idx = 0; idx < num_fx; idx++) {
7310 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7311 dspio_set_uint_param(codec,
7312 ca0132_effects[idx].mid,
7313 ca0132_effects[idx].reqs[i],
7314 ca0132_effects[idx].def_vals[i]);
7315 }
7316 }
7317
6ef0e91e 7318 ca0132_alt_create_dummy_stream(codec);
38ba69ff
CM		 7319}
7320
415cd844
CM		 7321/*
7322 * Setup default parameters for the Sound BlasterX AE-5 DSP.
7323 */
7324static void ae5_setup_defaults(struct hda_codec *codec)
7325{
7326 struct ca0132_spec *spec = codec->spec;
7327 unsigned int tmp;
7328 int num_fx;
7329 int idx, i;
7330
a88bcc8d
CM		 7331 msleep(100);
7332
415cd844
CM		 7333 if (spec->dsp_state != DSP_DOWNLOADED)
7334 return;
7335
7336 ca0132_alt_dsp_scp_startup(codec);
7337 ca0132_alt_init_analog_mics(codec);
7338 chipio_set_stream_control(codec, 0x03, 1);
7339 chipio_set_stream_control(codec, 0x04, 1);
7340
7341 /* New, unknown SCP req's */
7342 tmp = FLOAT_ZERO;
7343 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
7344 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
7345 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
7346 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
7347
7348 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
7349 ca0113_mmio_gpio_set(codec, 0, false);
7350 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
7351
7352 /* Internal loopback off */
7353 tmp = FLOAT_ONE;
7354 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7355 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7356
7357 /*remove DSP headroom*/
7358 tmp = FLOAT_ZERO;
7359 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7360
7361 /* set WUH source */
7362 tmp = FLOAT_TWO;
7363 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7364 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7365
7366 /* Set speaker source? */
7367 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7368
7369 ca0132_alt_dsp_initial_mic_setup(codec);
7370 ae5_post_dsp_register_set(codec);
7371 ae5_post_dsp_param_setup(codec);
7372 ae5_post_dsp_pll_setup(codec);
7373 ae5_post_dsp_stream_setup(codec);
7374 ae5_post_dsp_startup_data(codec);
7375
7376 /* out, in effects + voicefx */
7377 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7378 for (idx = 0; idx < num_fx; idx++) {
7379 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7380 dspio_set_uint_param(codec,
7381 ca0132_effects[idx].mid,
7382 ca0132_effects[idx].reqs[i],
7383 ca0132_effects[idx].def_vals[i]);
7384 }
7385 }
7386
7387 ca0132_alt_create_dummy_stream(codec);
7388}
7389
5aaca44d
IM		 7390/*
7391 * Initialization of flags in chip
7392 */
7393static void ca0132_init_flags(struct hda_codec *codec)
7394{
009b8f97
CM		 7395 struct ca0132_spec *spec = codec->spec;
7396
7397 if (spec->use_alt_functions) {
7398 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
7399 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
7400 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
7401 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
7402 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
7403 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7404 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
7405 chipio_set_control_flag(codec,
7406 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7407 chipio_set_control_flag(codec,
7408 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
7409 } else {
7410 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7411 chipio_set_control_flag(codec,
7412 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
7413 chipio_set_control_flag(codec,
7414 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
7415 chipio_set_control_flag(codec,
7416 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
7417 chipio_set_control_flag(codec,
7418 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7419 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
7420 }
5aaca44d
IM		 7421}
7422
7423/*
7424 * Initialization of parameters in chip
7425 */
7426static void ca0132_init_params(struct hda_codec *codec)
7427{
009b8f97
CM		 7428 struct ca0132_spec *spec = codec->spec;
7429
7430 if (spec->use_alt_functions) {
7431 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7432 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
7433 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
7434 chipio_set_control_param(codec, 0, 0);
7435 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
7436 }
7437
5aaca44d
IM		 7438 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
7439 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
7440}
95c6e9cb 7441
e90f29e4
IM		 7442static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
7443{
7444 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
7445 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
7446 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
7447 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
7448 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
7449 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
7450
406261ce
IM		 7451 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7452 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 7453 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7454}
7455
7456static bool ca0132_download_dsp_images(struct hda_codec *codec)
7457{
7458 bool dsp_loaded = false;
8a19bcee 7459 struct ca0132_spec *spec = codec->spec;
e90f29e4 7460 const struct dsp_image_seg *dsp_os_image;
15e4ba66 7461 const struct firmware *fw_entry;
8a19bcee
CM		 7462 /*
7463 * Alternate firmwares for different variants. The Recon3Di apparently
7464 * can use the default firmware, but I'll leave the option in case
7465 * it needs it again.
7466 */
7467 switch (spec->quirk) {
7468 case QUIRK_SBZ:
7a928186
CM		 7469 case QUIRK_R3D:
7470 case QUIRK_AE5:
7471 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8a19bcee 7472 codec->card->dev) != 0) {
6ef0e91e 7473 codec_dbg(codec, "Desktop firmware not found.");
8a19bcee
CM		 7474 spec->alt_firmware_present = false;
7475 } else {
7a928186 7476 codec_dbg(codec, "Desktop firmware selected.");
8a19bcee
CM		 7477 spec->alt_firmware_present = true;
7478 }
7479 break;
7480 case QUIRK_R3DI:
7481 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
7482 codec->card->dev) != 0) {
7483 codec_dbg(codec, "Recon3Di alt firmware not detected.");
7484 spec->alt_firmware_present = false;
7485 } else {
7486 codec_dbg(codec, "Recon3Di firmware selected.");
7487 spec->alt_firmware_present = true;
7488 }
7489 break;
7490 default:
7491 spec->alt_firmware_present = false;
7492 break;
7493 }
7494 /*
7495 * Use default ctefx.bin if no alt firmware is detected, or if none
7496 * exists for your particular codec.
7497 */
7498 if (!spec->alt_firmware_present) {
7499 codec_dbg(codec, "Default firmware selected.");
7500 if (request_firmware(&fw_entry, EFX_FILE,
7501 codec->card->dev) != 0)
7502 return false;
7503 }
e90f29e4 7504
15e4ba66 7505 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 7506 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 7507 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 7508 goto exit_download;
7509 }
7510
e90f29e4
IM		 7511 dsp_loaded = dspload_wait_loaded(codec);
7512
d1d28500 7513exit_download:
15e4ba66
TI		 7514 release_firmware(fw_entry);
7515
e90f29e4
IM		 7516 return dsp_loaded;
7517}
7518
7519static void ca0132_download_dsp(struct hda_codec *codec)
7520{
7521 struct ca0132_spec *spec = codec->spec;
7522
9a0869f4
TI		 7523#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7524 return; /* NOP */
7525#endif
e90f29e4 7526
e24aa0a4
TI		 7527 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7528 return; /* don't retry failures */
7529
b714a710 7530 chipio_enable_clocks(codec);
e93ac30a
CM		 7531 if (spec->dsp_state != DSP_DOWNLOADED) {
7532 spec->dsp_state = DSP_DOWNLOADING;
7533
7534 if (!ca0132_download_dsp_images(codec))
7535 spec->dsp_state = DSP_DOWNLOAD_FAILED;
7536 else
7537 spec->dsp_state = DSP_DOWNLOADED;
7538 }
e90f29e4 7539
009b8f97
CM		 7540 /* For codecs using alt functions, this is already done earlier */
7541 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 7542 ca0132_set_dsp_msr(codec, true);
7543}
7544
f8fb1170
TI		 7545static void ca0132_process_dsp_response(struct hda_codec *codec,
7546 struct hda_jack_callback *callback)
e90f29e4
IM		 7547{
7548 struct ca0132_spec *spec = codec->spec;
7549
4e76a883 7550 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 7551 if (spec->wait_scp) {
7552 if (dspio_get_response_data(codec) >= 0)
7553 spec->wait_scp = 0;
7554 }
7555
7556 dspio_clear_response_queue(codec);
7557}
7558
f8fb1170 7559static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 7560{
993884f6 7561 struct ca0132_spec *spec = codec->spec;
2ebab40e 7562 struct hda_jack_tbl *tbl;
e90f29e4 7563
f8fb1170
TI		 7564 /* Delay enabling the HP amp, to let the mic-detection
7565 * state machine run.
7566 */
7567 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 7568 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 7569 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7570 if (tbl)
7571 tbl->block_report = 1;
f8fb1170
TI		 7572}
7573
7574static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7575{
a1b7f016
CM		 7576 struct ca0132_spec *spec = codec->spec;
7577
7578 if (spec->use_alt_functions)
7579 ca0132_alt_select_in(codec);
7580 else
7581 ca0132_select_mic(codec);
f8fb1170
TI		 7582}
7583
7584static void ca0132_init_unsol(struct hda_codec *codec)
7585{
d5c016b5
GM		 7586 struct ca0132_spec *spec = codec->spec;
7587 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7588 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 7589 amic_callback);
7590 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7591 ca0132_process_dsp_response);
63177afc 7592 /* Front headphone jack detection */
009b8f97 7593 if (spec->use_alt_functions)
63177afc
CM		 7594 snd_hda_jack_detect_enable_callback(codec,
7595 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 7596}
7597
5aaca44d
IM		 7598/*
7599 * Verbs tables.
7600 */
7601
7602/* Sends before DSP download. */
7603static struct hda_verb ca0132_base_init_verbs[] = {
7604 /*enable ct extension*/
7605 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 7606 {}
7607};
7608
7609/* Send at exit. */
7610static struct hda_verb ca0132_base_exit_verbs[] = {
7611 /*set afg to D3*/
7612 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7613 /*disable ct extension*/
7614 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7615 {}
7616};
7617
8a19bcee 7618/* Other verbs tables. Sends after DSP download. */
e93ac30a 7619
5aaca44d
IM		 7620static struct hda_verb ca0132_init_verbs0[] = {
7621 /* chip init verbs */
7622 {0x15, 0x70D, 0xF0},
7623 {0x15, 0x70E, 0xFE},
7624 {0x15, 0x707, 0x75},
7625 {0x15, 0x707, 0xD3},
7626 {0x15, 0x707, 0x09},
7627 {0x15, 0x707, 0x53},
7628 {0x15, 0x707, 0xD4},
7629 {0x15, 0x707, 0xEF},
7630 {0x15, 0x707, 0x75},
7631 {0x15, 0x707, 0xD3},
7632 {0x15, 0x707, 0x09},
7633 {0x15, 0x707, 0x02},
7634 {0x15, 0x707, 0x37},
7635 {0x15, 0x707, 0x78},
7636 {0x15, 0x53C, 0xCE},
7637 {0x15, 0x575, 0xC9},
7638 {0x15, 0x53D, 0xCE},
7639 {0x15, 0x5B7, 0xC9},
7640 {0x15, 0x70D, 0xE8},
7641 {0x15, 0x70E, 0xFE},
7642 {0x15, 0x707, 0x02},
7643 {0x15, 0x707, 0x68},
7644 {0x15, 0x707, 0x62},
7645 {0x15, 0x53A, 0xCE},
7646 {0x15, 0x546, 0xC9},
7647 {0x15, 0x53B, 0xCE},
7648 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 7649 {}
7650};
7651
e42c7c73
CM		 7652/* Extra init verbs for desktop cards. */
7653static struct hda_verb ca0132_init_verbs1[] = {
e93ac30a
CM		 7654 {0x15, 0x70D, 0x20},
7655 {0x15, 0x70E, 0x19},
7656 {0x15, 0x707, 0x00},
7657 {0x15, 0x539, 0xCE},
7658 {0x15, 0x546, 0xC9},
7659 {0x15, 0x70D, 0xB7},
7660 {0x15, 0x70E, 0x09},
7661 {0x15, 0x707, 0x10},
7662 {0x15, 0x70D, 0xAF},
7663 {0x15, 0x70E, 0x09},
7664 {0x15, 0x707, 0x01},
7665 {0x15, 0x707, 0x05},
7666 {0x15, 0x70D, 0x73},
7667 {0x15, 0x70E, 0x09},
7668 {0x15, 0x707, 0x14},
7669 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 7670 {}
7671};
7672
95c6e9cb
IM		 7673static void ca0132_init_chip(struct hda_codec *codec)
7674{
7675 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7676 int num_fx;
7677 int i;
7678 unsigned int on;
95c6e9cb
IM		 7679
7680 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 7681
7682 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 7683 if (!spec->use_alt_functions)
7684 spec->cur_mic_type = DIGITAL_MIC;
7685 else
7686 spec->cur_mic_type = REAR_MIC;
7687
5aaca44d
IM		 7688 spec->cur_mic_boost = 0;
7689
7690 for (i = 0; i < VNODES_COUNT; i++) {
7691 spec->vnode_lvol[i] = 0x5a;
7692 spec->vnode_rvol[i] = 0x5a;
7693 spec->vnode_lswitch[i] = 0;
7694 spec->vnode_rswitch[i] = 0;
7695 }
7696
7697 /*
7698 * Default states for effects are in ca0132_effects[].
7699 */
7700 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7701 for (i = 0; i < num_fx; i++) {
7702 on = (unsigned int)ca0132_effects[i].reqs[0];
7703 spec->effects_switch[i] = on ? 1 : 0;
7704 }
47cdf76e
CM		 7705 /*
7706 * Sets defaults for the effect slider controls, only for alternative
7707 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7708 */
7709 if (spec->use_alt_controls) {
7710 spec->xbass_xover_freq = 8;
7711 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7712 spec->fx_ctl_val[i] = effect_slider_defaults[i];
7713 }
5aaca44d
IM		 7714
7715 spec->voicefx_val = 0;
7716 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7717 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7718
76dea4db
CM		 7719 /*
7720 * The ZxR doesn't have a front panel header, and it's line-in is on
7721 * the daughter board. So, there is no input enum control, and we need
7722 * to make sure that spec->in_enum_val is set properly.
7723 */
7724 if (spec->quirk == QUIRK_ZXR)
7725 spec->in_enum_val = REAR_MIC;
7726
44f0c978
IM		 7727#ifdef ENABLE_TUNING_CONTROLS
7728 ca0132_init_tuning_defaults(codec);
7729#endif
95c6e9cb
IM		 7730}
7731
2e48b2b7
CM		 7732/*
7733 * Recon3Di exit specific commands.
7734 */
7735/* prevents popping noise on shutdown */
7736static void r3di_gpio_shutdown(struct hda_codec *codec)
7737{
7738 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7739}
7740
7741/*
7742 * Sound Blaster Z exit specific commands.
7743 */
7744static void sbz_region2_exit(struct hda_codec *codec)
7745{
7746 struct ca0132_spec *spec = codec->spec;
7747 unsigned int i;
7748
7749 for (i = 0; i < 4; i++)
7750 writeb(0x0, spec->mem_base + 0x100);
7751 for (i = 0; i < 8; i++)
7752 writeb(0xb3, spec->mem_base + 0x304);
a62e4739 7753
b9b41345
CM		 7754 ca0113_mmio_gpio_set(codec, 0, false);
7755 ca0113_mmio_gpio_set(codec, 1, false);
7756 ca0113_mmio_gpio_set(codec, 4, true);
7757 ca0113_mmio_gpio_set(codec, 5, false);
7758 ca0113_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 7759}
7760
7761static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7762{
7763 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7764 unsigned int i;
7765
7766 snd_hda_codec_write(codec, 0x11, 0,
7767 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7768
7769 for (i = 0; i < 5; i++)
7770 snd_hda_codec_write(codec, pins[i], 0,
7771 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7772}
7773
2f295f91 7774static void ca0132_clear_unsolicited(struct hda_codec *codec)
2e48b2b7
CM		 7775{
7776 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7777 unsigned int i;
7778
7779 for (i = 0; i < 7; i++) {
7780 snd_hda_codec_write(codec, pins[i], 0,
7781 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7782 }
7783}
7784
7785/* On shutdown, sends commands in sets of three */
7786static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7787 int mask, int data)
7788{
7789 if (dir >= 0)
7790 snd_hda_codec_write(codec, 0x01, 0,
7791 AC_VERB_SET_GPIO_DIRECTION, dir);
7792 if (mask >= 0)
7793 snd_hda_codec_write(codec, 0x01, 0,
7794 AC_VERB_SET_GPIO_MASK, mask);
7795
7796 if (data >= 0)
7797 snd_hda_codec_write(codec, 0x01, 0,
7798 AC_VERB_SET_GPIO_DATA, data);
7799}
7800
7675a2a9
CM		 7801static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
7802{
7803 hda_nid_t pins[7] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
7804 unsigned int i;
7805
7806 for (i = 0; i < 7; i++)
7807 snd_hda_codec_write(codec, pins[i], 0,
7808 AC_VERB_SET_POWER_STATE, 0x03);
7809}
7810
2e48b2b7
CM		 7811static void sbz_exit_chip(struct hda_codec *codec)
7812{
009b8f97
CM		 7813 chipio_set_stream_control(codec, 0x03, 0);
7814 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 7815
7816 /* Mess with GPIO */
7817 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7818 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7819 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7820
009b8f97
CM		 7821 chipio_set_stream_control(codec, 0x14, 0);
7822 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7823
7824 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7825 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7826
7827 chipio_write(codec, 0x18a020, 0x00000083);
7828
7829 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7830 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7831 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7832
009b8f97 7833 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7834
7835 chipio_set_control_param(codec, 0x0D, 0x24);
7836
2f295f91 7837 ca0132_clear_unsolicited(codec);
2e48b2b7
CM		 7838 sbz_set_pin_ctl_default(codec);
7839
7840 snd_hda_codec_write(codec, 0x0B, 0,
7841 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7842
2e48b2b7
CM		 7843 sbz_region2_exit(codec);
7844}
7845
2f295f91
CM		 7846static void r3d_exit_chip(struct hda_codec *codec)
7847{
7848 ca0132_clear_unsolicited(codec);
7849 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7850 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7851}
7852
edb1b3ab
CM		 7853static void ae5_exit_chip(struct hda_codec *codec)
7854{
7855 chipio_set_stream_control(codec, 0x03, 0);
7856 chipio_set_stream_control(codec, 0x04, 0);
7857
7858 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7859 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7860 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7861 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7862 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7863 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
7864 ca0113_mmio_gpio_set(codec, 0, false);
7865 ca0113_mmio_gpio_set(codec, 1, false);
7866
7867 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7868 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7869
7870 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7871
7872 chipio_set_stream_control(codec, 0x18, 0);
7873 chipio_set_stream_control(codec, 0x0c, 0);
7874
7875 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
7876}
7877
96395e86
CM		 7878static void zxr_exit_chip(struct hda_codec *codec)
7879{
7880 chipio_set_stream_control(codec, 0x03, 0);
7881 chipio_set_stream_control(codec, 0x04, 0);
7882 chipio_set_stream_control(codec, 0x14, 0);
7883 chipio_set_stream_control(codec, 0x0C, 0);
7884
7885 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7886 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7887
7888 chipio_write(codec, 0x18a020, 0x00000083);
7889
7890 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7891 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7892
7893 ca0132_clear_unsolicited(codec);
7894 sbz_set_pin_ctl_default(codec);
7895 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7896
7897 ca0113_mmio_gpio_set(codec, 5, false);
7898 ca0113_mmio_gpio_set(codec, 2, false);
7899 ca0113_mmio_gpio_set(codec, 3, false);
7900 ca0113_mmio_gpio_set(codec, 0, false);
7901 ca0113_mmio_gpio_set(codec, 4, true);
7902 ca0113_mmio_gpio_set(codec, 0, true);
7903 ca0113_mmio_gpio_set(codec, 5, true);
7904 ca0113_mmio_gpio_set(codec, 2, false);
7905 ca0113_mmio_gpio_set(codec, 3, false);
7906}
7907
95c6e9cb
IM		 7908static void ca0132_exit_chip(struct hda_codec *codec)
7909{
7910 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7911
7912 if (dspload_is_loaded(codec))
7913 dsp_reset(codec);
95c6e9cb
IM		 7914}
7915
38ba69ff
CM		 7916/*
7917 * This fixes a problem that was hard to reproduce. Very rarely, I would
7918 * boot up, and there would be no sound, but the DSP indicated it had loaded
7919 * properly. I did a few memory dumps to see if anything was different, and
7920 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7921 * checks if those areas are uninitialized, and if they are, it'll attempt to
7922 * reload the card 3 times. Usually it fixes by the second.
7923 */
7924static void sbz_dsp_startup_check(struct hda_codec *codec)
7925{
7926 struct ca0132_spec *spec = codec->spec;
7927 unsigned int dsp_data_check[4];
7928 unsigned int cur_address = 0x390;
7929 unsigned int i;
7930 unsigned int failure = 0;
7931 unsigned int reload = 3;
7932
7933 if (spec->startup_check_entered)
7934 return;
7935
7936 spec->startup_check_entered = true;
7937
7938 for (i = 0; i < 4; i++) {
7939 chipio_read(codec, cur_address, &dsp_data_check[i]);
7940 cur_address += 0x4;
7941 }
7942 for (i = 0; i < 4; i++) {
7943 if (dsp_data_check[i] == 0xa1a2a3a4)
7944 failure = 1;
7945 }
7946
7947 codec_dbg(codec, "Startup Check: %d ", failure);
7948 if (failure)
7949 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7950 /*
7951 * While the failure condition is true, and we haven't reached our
7952 * three reload limit, continue trying to reload the driver and
7953 * fix the issue.
7954 */
7955 while (failure && (reload != 0)) {
7956 codec_info(codec, "Reloading... Tries left: %d", reload);
7957 sbz_exit_chip(codec);
7958 spec->dsp_state = DSP_DOWNLOAD_INIT;
7959 codec->patch_ops.init(codec);
7960 failure = 0;
7961 for (i = 0; i < 4; i++) {
7962 chipio_read(codec, cur_address, &dsp_data_check[i]);
7963 cur_address += 0x4;
7964 }
7965 for (i = 0; i < 4; i++) {
7966 if (dsp_data_check[i] == 0xa1a2a3a4)
7967 failure = 1;
7968 }
7969 reload--;
7970 }
7971
7972 if (!failure && reload < 3)
7973 codec_info(codec, "DSP fixed.");
7974
7975 if (!failure)
7976 return;
7977
7978 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7979}
7980
e93ac30a
CM		 7981/*
7982 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7983 * extra precision for decibel values. If you had the dB value in floating point
7984 * you would take the value after the decimal point, multiply by 64, and divide
7985 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7986 * implement fixed point or floating point dB volumes. For now, I'll set them
7987 * to 0 just incase a value has lingered from a boot into Windows.
7988 */
7989static void ca0132_alt_vol_setup(struct hda_codec *codec)
7990{
7991 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7992 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7993 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7994 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7995 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7996 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7997 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7998 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7999}
8000
8001/*
8002 * Extra commands that don't really fit anywhere else.
8003 */
8004static void sbz_pre_dsp_setup(struct hda_codec *codec)
8005{
8006 struct ca0132_spec *spec = codec->spec;
8007
8008 writel(0x00820680, spec->mem_base + 0x01C);
8009 writel(0x00820680, spec->mem_base + 0x01C);
8010
e93ac30a
CM		 8011 chipio_write(codec, 0x18b0a4, 0x000000c2);
8012
8013 snd_hda_codec_write(codec, 0x11, 0,
8014 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8015}
8016
e42c7c73
CM		 8017static void r3d_pre_dsp_setup(struct hda_codec *codec)
8018{
e42c7c73
CM		 8019 chipio_write(codec, 0x18b0a4, 0x000000c2);
8020
8021 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8022 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8023 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8024 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8025 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8026 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8027
8028 snd_hda_codec_write(codec, 0x11, 0,
8029 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8030}
8031
e93ac30a
CM		 8032static void r3di_pre_dsp_setup(struct hda_codec *codec)
8033{
8034 chipio_write(codec, 0x18b0a4, 0x000000c2);
8035
8036 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8037 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8039 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8041 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8042
8043 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8044 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
8045 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8046 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
8047 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8048 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
8049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8050 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
8051
8052 snd_hda_codec_write(codec, 0x11, 0,
8053 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
8054}
8055
e93ac30a
CM		 8056/*
8057 * These are sent before the DSP is downloaded. Not sure
8058 * what they do, or if they're necessary. Could possibly
8059 * be removed. Figure they're better to leave in.
8060 */
e42c7c73 8061static void ca0132_mmio_init(struct hda_codec *codec)
e93ac30a
CM		 8062{
8063 struct ca0132_spec *spec = codec->spec;
8064
ce715448
CM		 8065 if (spec->quirk == QUIRK_AE5)
8066 writel(0x00000001, spec->mem_base + 0x400);
8067 else
8068 writel(0x00000000, spec->mem_base + 0x400);
8069
8070 if (spec->quirk == QUIRK_AE5)
8071 writel(0x00000001, spec->mem_base + 0x408);
8072 else
8073 writel(0x00000000, spec->mem_base + 0x408);
8074
8075 if (spec->quirk == QUIRK_AE5)
8076 writel(0x00000001, spec->mem_base + 0x40c);
8077 else
8078 writel(0x00000000, spec->mem_base + 0x40C);
8079
2e492b8e
CM		 8080 if (spec->quirk == QUIRK_ZXR)
8081 writel(0x00880640, spec->mem_base + 0x01C);
8082 else
8083 writel(0x00880680, spec->mem_base + 0x01C);
ce715448
CM		 8084
8085 if (spec->quirk == QUIRK_AE5)
8086 writel(0x00000080, spec->mem_base + 0xC0C);
8087 else
8088 writel(0x00000083, spec->mem_base + 0xC0C);
8089
e93ac30a
CM		 8090 writel(0x00000030, spec->mem_base + 0xC00);
8091 writel(0x00000000, spec->mem_base + 0xC04);
ce715448
CM		 8092
8093 if (spec->quirk == QUIRK_AE5)
8094 writel(0x00000000, spec->mem_base + 0xC0C);
8095 else
8096 writel(0x00000003, spec->mem_base + 0xC0C);
8097
e93ac30a
CM		 8098 writel(0x00000003, spec->mem_base + 0xC0C);
8099 writel(0x00000003, spec->mem_base + 0xC0C);
8100 writel(0x00000003, spec->mem_base + 0xC0C);
ce715448
CM		 8101
8102 if (spec->quirk == QUIRK_AE5)
8103 writel(0x00000001, spec->mem_base + 0xC08);
8104 else
8105 writel(0x000000C1, spec->mem_base + 0xC08);
8106
e93ac30a
CM		 8107 writel(0x000000F1, spec->mem_base + 0xC08);
8108 writel(0x00000001, spec->mem_base + 0xC08);
8109 writel(0x000000C7, spec->mem_base + 0xC08);
8110 writel(0x000000C1, spec->mem_base + 0xC08);
8111 writel(0x00000080, spec->mem_base + 0xC04);
ce715448
CM		 8112
8113 if (spec->quirk == QUIRK_AE5) {
8114 writel(0x00000000, spec->mem_base + 0x42c);
8115 writel(0x00000000, spec->mem_base + 0x46c);
8116 writel(0x00000000, spec->mem_base + 0x4ac);
8117 writel(0x00000000, spec->mem_base + 0x4ec);
8118 writel(0x00000000, spec->mem_base + 0x43c);
8119 writel(0x00000000, spec->mem_base + 0x47c);
8120 writel(0x00000000, spec->mem_base + 0x4bc);
8121 writel(0x00000000, spec->mem_base + 0x4fc);
8122 writel(0x00000600, spec->mem_base + 0x100);
8123 writel(0x00000014, spec->mem_base + 0x410);
8124 writel(0x0000060f, spec->mem_base + 0x100);
8125 writel(0x0000070f, spec->mem_base + 0x100);
8126 writel(0x00000aff, spec->mem_base + 0x830);
8127 writel(0x00000000, spec->mem_base + 0x86c);
8128 writel(0x0000006b, spec->mem_base + 0x800);
8129 writel(0x00000001, spec->mem_base + 0x86c);
8130 writel(0x0000006b, spec->mem_base + 0x800);
8131 writel(0x00000057, spec->mem_base + 0x804);
8132 writel(0x00800000, spec->mem_base + 0x20c);
8133 }
e93ac30a
CM		 8134}
8135
b9b41345
CM		 8136/*
8137 * This function writes to some SFR's, does some region2 writes, and then
8138 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
8139 * what it does.
8140 */
8141static void ae5_register_set(struct hda_codec *codec)
8142{
8143 struct ca0132_spec *spec = codec->spec;
8144
8145 chipio_8051_write_direct(codec, 0x93, 0x10);
8146 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8147 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8148 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8149 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8150
8151 writeb(0x0f, spec->mem_base + 0x304);
8152 writeb(0x0f, spec->mem_base + 0x304);
8153 writeb(0x0f, spec->mem_base + 0x304);
8154 writeb(0x0f, spec->mem_base + 0x304);
8155 writeb(0x0e, spec->mem_base + 0x100);
8156 writeb(0x1f, spec->mem_base + 0x304);
8157 writeb(0x0c, spec->mem_base + 0x100);
8158 writeb(0x3f, spec->mem_base + 0x304);
8159 writeb(0x08, spec->mem_base + 0x100);
8160 writeb(0x7f, spec->mem_base + 0x304);
8161 writeb(0x00, spec->mem_base + 0x100);
8162 writeb(0xff, spec->mem_base + 0x304);
8163
8164 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
8165
8166 chipio_8051_write_direct(codec, 0x90, 0x00);
8167 chipio_8051_write_direct(codec, 0x90, 0x10);
8168
8169 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8170
8171 chipio_write(codec, 0x18b0a4, 0x000000c2);
8172
8173 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8174 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8175}
8176
e93ac30a
CM		 8177/*
8178 * Extra init functions for alternative ca0132 codecs. Done
8179 * here so they don't clutter up the main ca0132_init function
8180 * anymore than they have to.
8181 */
8182static void ca0132_alt_init(struct hda_codec *codec)
8183{
8184 struct ca0132_spec *spec = codec->spec;
8185
8186 ca0132_alt_vol_setup(codec);
8187
8188 switch (spec->quirk) {
8189 case QUIRK_SBZ:
8190 codec_dbg(codec, "SBZ alt_init");
8191 ca0132_gpio_init(codec);
8192 sbz_pre_dsp_setup(codec);
8193 snd_hda_sequence_write(codec, spec->chip_init_verbs);
e42c7c73 8194 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
e93ac30a
CM		 8195 break;
8196 case QUIRK_R3DI:
8197 codec_dbg(codec, "R3DI alt_init");
8198 ca0132_gpio_init(codec);
8199 ca0132_gpio_setup(codec);
7e6ed62e 8200 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 8201 r3di_pre_dsp_setup(codec);
8202 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8203 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
8204 break;
e42c7c73
CM		 8205 case QUIRK_R3D:
8206 r3d_pre_dsp_setup(codec);
8207 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8208 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8209 break;
03c9b6b1
CM		 8210 case QUIRK_AE5:
8211 ca0132_gpio_init(codec);
8212 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8213 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
8214 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8215 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
8216 chipio_write(codec, 0x18b030, 0x00000020);
8217 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8218 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8219 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8220 break;
2e492b8e
CM		 8221 case QUIRK_ZXR:
8222 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8223 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8224 break;
e93ac30a
CM		 8225 }
8226}
8227
95c6e9cb
IM		 8228static int ca0132_init(struct hda_codec *codec)
8229{
8230 struct ca0132_spec *spec = codec->spec;
8231 struct auto_pin_cfg *cfg = &spec->autocfg;
8232 int i;
e93ac30a
CM		 8233 bool dsp_loaded;
8234
8235 /*
8236 * If the DSP is already downloaded, and init has been entered again,
8237 * there's only two reasons for it. One, the codec has awaken from a
8238 * suspended state, and in that case dspload_is_loaded will return
8239 * false, and the init will be ran again. The other reason it gets
8240 * re entered is on startup for some reason it triggers a suspend and
8241 * resume state. In this case, it will check if the DSP is downloaded,
8242 * and not run the init function again. For codecs using alt_functions,
8243 * it will check if the DSP is loaded properly.
8244 */
8245 if (spec->dsp_state == DSP_DOWNLOADED) {
8246 dsp_loaded = dspload_is_loaded(codec);
8247 if (!dsp_loaded) {
8248 spec->dsp_reload = true;
8249 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 8250 } else {
8251 if (spec->quirk == QUIRK_SBZ)
8252 sbz_dsp_startup_check(codec);
e93ac30a 8253 return 0;
38ba69ff 8254 }
e93ac30a 8255 }
95c6e9cb 8256
e24aa0a4
TI		 8257 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
8258 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 8259 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 8260
e42c7c73
CM		 8261 if (spec->use_pci_mmio)
8262 ca0132_mmio_init(codec);
e93ac30a 8263
664c7155 8264 snd_hda_power_up_pm(codec);
5aaca44d 8265
b9b41345
CM		 8266 if (spec->quirk == QUIRK_AE5)
8267 ae5_register_set(codec);
8268
f8fb1170 8269 ca0132_init_unsol(codec);
5aaca44d
IM		 8270 ca0132_init_params(codec);
8271 ca0132_init_flags(codec);
7e6ed62e 8272
5aaca44d 8273 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 8274
365c7f25 8275 if (spec->use_alt_functions)
e93ac30a
CM		 8276 ca0132_alt_init(codec);
8277
01ef7dbf 8278 ca0132_download_dsp(codec);
7e6ed62e 8279
5aaca44d 8280 ca0132_refresh_widget_caps(codec);
e93ac30a 8281
7e6ed62e
CM		 8282 switch (spec->quirk) {
8283 case QUIRK_R3DI:
c986f50c
CM		 8284 case QUIRK_R3D:
8285 r3d_setup_defaults(codec);
7e6ed62e 8286 break;
126b75e0 8287 case QUIRK_SBZ:
c25c73e0 8288 case QUIRK_ZXR:
d97420d2 8289 sbz_setup_defaults(codec);
126b75e0 8290 break;
415cd844
CM		 8291 case QUIRK_AE5:
8292 ae5_setup_defaults(codec);
8293 break;
126b75e0 8294 default:
38ba69ff
CM		 8295 ca0132_setup_defaults(codec);
8296 ca0132_init_analog_mic2(codec);
8297 ca0132_init_dmic(codec);
7e6ed62e 8298 break;
38ba69ff 8299 }
5aaca44d
IM		 8300
8301 for (i = 0; i < spec->num_outputs; i++)
8302 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 8303
95c6e9cb
IM		 8304 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8305
8306 for (i = 0; i < spec->num_inputs; i++)
8307 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8308
8309 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8310
009b8f97 8311 if (!spec->use_alt_functions) {
e93ac30a
CM		 8312 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8313 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8314 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
8315 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8316 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
8317 }
8318
7cb9d94c 8319 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 8320 ca0132_gpio_setup(codec);
8321
d5c016b5 8322 snd_hda_sequence_write(codec, spec->spec_init_verbs);
d97420d2 8323 if (spec->use_alt_functions) {
7cb9d94c
CM		 8324 ca0132_alt_select_out(codec);
8325 ca0132_alt_select_in(codec);
d97420d2 8326 } else {
7cb9d94c
CM		 8327 ca0132_select_out(codec);
8328 ca0132_select_mic(codec);
7cb9d94c 8329 }
5aaca44d 8330
a73d511c
IM		 8331 snd_hda_jack_report_sync(codec);
8332
e93ac30a
CM		 8333 /*
8334 * Re set the PlayEnhancement switch on a resume event, because the
8335 * controls will not be reloaded.
8336 */
8337 if (spec->dsp_reload) {
8338 spec->dsp_reload = false;
8339 ca0132_pe_switch_set(codec);
8340 }
8341
664c7155 8342 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 8343
8344 return 0;
8345}
8346
7675a2a9
CM		 8347static int dbpro_init(struct hda_codec *codec)
8348{
8349 struct ca0132_spec *spec = codec->spec;
8350 struct auto_pin_cfg *cfg = &spec->autocfg;
8351 unsigned int i;
8352
8353 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8354 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8355
8356 for (i = 0; i < spec->num_inputs; i++)
8357 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8358
8359 return 0;
8360}
8361
95c6e9cb
IM		 8362static void ca0132_free(struct hda_codec *codec)
8363{
5aaca44d
IM		 8364 struct ca0132_spec *spec = codec->spec;
8365
993884f6 8366 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 8367 snd_hda_power_up(codec);
2e48b2b7
CM		 8368 switch (spec->quirk) {
8369 case QUIRK_SBZ:
8370 sbz_exit_chip(codec);
8371 break;
96395e86
CM		 8372 case QUIRK_ZXR:
8373 zxr_exit_chip(codec);
8374 break;
2f295f91
CM		 8375 case QUIRK_R3D:
8376 r3d_exit_chip(codec);
8377 break;
edb1b3ab
CM		 8378 case QUIRK_AE5:
8379 ae5_exit_chip(codec);
8380 break;
2e48b2b7
CM		 8381 case QUIRK_R3DI:
8382 r3di_gpio_shutdown(codec);
2e48b2b7
CM		 8383 break;
8384 }
2f295f91
CM		 8385
8386 snd_hda_sequence_write(codec, spec->base_exit_verbs);
8387 ca0132_exit_chip(codec);
8388
5aaca44d 8389 snd_hda_power_down(codec);
aa31704f
CM		 8390 if (spec->mem_base)
8391 iounmap(spec->mem_base);
d5c016b5 8392 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 8393 kfree(codec->spec);
8394}
8395
7675a2a9
CM		 8396static void dbpro_free(struct hda_codec *codec)
8397{
8398 struct ca0132_spec *spec = codec->spec;
8399
8400 zxr_dbpro_power_state_shutdown(codec);
8401
8402 kfree(spec->spec_init_verbs);
8403 kfree(codec->spec);
8404}
8405
2e48b2b7
CM		 8406static void ca0132_reboot_notify(struct hda_codec *codec)
8407{
8408 codec->patch_ops.free(codec);
8409}
8410
071f1344 8411static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 8412 .build_controls = ca0132_build_controls,
8413 .build_pcms = ca0132_build_pcms,
8414 .init = ca0132_init,
8415 .free = ca0132_free,
f8fb1170 8416 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 8417 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 8418};
8419
7675a2a9
CM		 8420static const struct hda_codec_ops dbpro_patch_ops = {
8421 .build_controls = dbpro_build_controls,
8422 .build_pcms = dbpro_build_pcms,
8423 .init = dbpro_init,
8424 .free = dbpro_free,
8425};
8426
441aa6a0
IM		 8427static void ca0132_config(struct hda_codec *codec)
8428{
8429 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 8430
8431 spec->dacs[0] = 0x2;
8432 spec->dacs[1] = 0x3;
8433 spec->dacs[2] = 0x4;
8434
8435 spec->multiout.dac_nids = spec->dacs;
8436 spec->multiout.num_dacs = 3;
441aa6a0 8437
009b8f97 8438 if (!spec->use_alt_functions)
63177afc
CM		 8439 spec->multiout.max_channels = 2;
8440 else
8441 spec->multiout.max_channels = 6;
8442
8443 switch (spec->quirk) {
8444 case QUIRK_ALIENWARE:
d06feaf0 8445 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
fe14f39e 8446 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
d06feaf0
CM		 8447 break;
8448 case QUIRK_SBZ:
8449 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
8450 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
8451 break;
6dcd7244
CM		 8452 case QUIRK_ZXR:
8453 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
8454 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
8455 break;
d06feaf0
CM		 8456 case QUIRK_R3D:
8457 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
8458 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
8459 break;
8460 case QUIRK_R3DI:
8461 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
8462 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8463 break;
8464 case QUIRK_AE5:
8465 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
8466 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8467 break;
8468 }
fe14f39e 8469
d06feaf0
CM		 8470 switch (spec->quirk) {
8471 case QUIRK_ALIENWARE:
fe14f39e
TI		 8472 spec->num_outputs = 2;
8473 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8474 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 8475 spec->shared_out_nid = 0x2;
8476 spec->unsol_tag_hp = 0x0f;
8477
8478 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8479 spec->adcs[1] = 0x8; /* analog mic2 */
8480 spec->adcs[2] = 0xa; /* what u hear */
8481
8482 spec->num_inputs = 3;
8483 spec->input_pins[0] = 0x12;
8484 spec->input_pins[1] = 0x11;
8485 spec->input_pins[2] = 0x13;
8486 spec->shared_mic_nid = 0x7;
8487 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 8488 break;
8489 case QUIRK_SBZ:
7f73df95 8490 case QUIRK_R3D:
63177afc
CM		 8491 spec->num_outputs = 2;
8492 spec->out_pins[0] = 0x0B; /* Line out */
8493 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8494 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8495 spec->out_pins[3] = 0x11; /* Rear surround */
8496 spec->shared_out_nid = 0x2;
8497 spec->unsol_tag_hp = spec->out_pins[1];
8498 spec->unsol_tag_front_hp = spec->out_pins[2];
8499
8500 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8501 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8502 spec->adcs[2] = 0xa; /* what u hear */
8503
8504 spec->num_inputs = 2;
8505 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8506 spec->input_pins[1] = 0x13; /* What U Hear */
8507 spec->shared_mic_nid = 0x7;
8508 spec->unsol_tag_amic1 = spec->input_pins[0];
8509
8510 /* SPDIF I/O */
8511 spec->dig_out = 0x05;
8512 spec->multiout.dig_out_nid = spec->dig_out;
6dcd7244
CM		 8513 spec->dig_in = 0x09;
8514 break;
8515 case QUIRK_ZXR:
8516 spec->num_outputs = 2;
8517 spec->out_pins[0] = 0x0B; /* Line out */
8518 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8519 spec->out_pins[2] = 0x10; /* Center/LFE */
8520 spec->out_pins[3] = 0x11; /* Rear surround */
8521 spec->shared_out_nid = 0x2;
8522 spec->unsol_tag_hp = spec->out_pins[1];
8523 spec->unsol_tag_front_hp = spec->out_pins[2];
8524
8525 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8526 spec->adcs[1] = 0x8; /* Not connected, no front mic */
8527 spec->adcs[2] = 0xa; /* what u hear */
8528
8529 spec->num_inputs = 2;
8530 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8531 spec->input_pins[1] = 0x13; /* What U Hear */
8532 spec->shared_mic_nid = 0x7;
8533 spec->unsol_tag_amic1 = spec->input_pins[0];
8534 break;
8535 case QUIRK_ZXR_DBPRO:
8536 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
8537
8538 spec->num_inputs = 1;
8539 spec->input_pins[0] = 0x11; /* RCA Line-in */
8540
8541 spec->dig_out = 0x05;
8542 spec->multiout.dig_out_nid = spec->dig_out;
8543
63177afc 8544 spec->dig_in = 0x09;
63177afc 8545 break;
d06feaf0
CM		 8546 case QUIRK_AE5:
8547 spec->num_outputs = 2;
8548 spec->out_pins[0] = 0x0B; /* Line out */
8549 spec->out_pins[1] = 0x11; /* Rear headphone out */
8550 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8551 spec->out_pins[3] = 0x0F; /* Rear surround */
8552 spec->shared_out_nid = 0x2;
8553 spec->unsol_tag_hp = spec->out_pins[1];
8554 spec->unsol_tag_front_hp = spec->out_pins[2];
8555
8556 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8557 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8558 spec->adcs[2] = 0xa; /* what u hear */
63177afc 8559
d06feaf0
CM		 8560 spec->num_inputs = 2;
8561 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8562 spec->input_pins[1] = 0x13; /* What U Hear */
8563 spec->shared_mic_nid = 0x7;
8564 spec->unsol_tag_amic1 = spec->input_pins[0];
8565
8566 /* SPDIF I/O */
8567 spec->dig_out = 0x05;
8568 spec->multiout.dig_out_nid = spec->dig_out;
8569 break;
8570 case QUIRK_R3DI:
63177afc
CM		 8571 spec->num_outputs = 2;
8572 spec->out_pins[0] = 0x0B; /* Line out */
8573 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8574 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8575 spec->out_pins[3] = 0x11; /* Rear surround */
8576 spec->shared_out_nid = 0x2;
8577 spec->unsol_tag_hp = spec->out_pins[1];
8578 spec->unsol_tag_front_hp = spec->out_pins[2];
8579
8580 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
8581 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
8582 spec->adcs[2] = 0x0a; /* what u hear */
8583
8584 spec->num_inputs = 2;
8585 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8586 spec->input_pins[1] = 0x13; /* What U Hear */
8587 spec->shared_mic_nid = 0x7;
8588 spec->unsol_tag_amic1 = spec->input_pins[0];
8589
8590 /* SPDIF I/O */
8591 spec->dig_out = 0x05;
8592 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 8593 break;
8594 default:
fe14f39e
TI		 8595 spec->num_outputs = 2;
8596 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8597 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 8598 spec->shared_out_nid = 0x2;
8599 spec->unsol_tag_hp = spec->out_pins[1];
8600
8601 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8602 spec->adcs[1] = 0x8; /* analog mic2 */
8603 spec->adcs[2] = 0xa; /* what u hear */
8604
8605 spec->num_inputs = 3;
8606 spec->input_pins[0] = 0x12;
8607 spec->input_pins[1] = 0x11;
8608 spec->input_pins[2] = 0x13;
8609 spec->shared_mic_nid = 0x7;
8610 spec->unsol_tag_amic1 = spec->input_pins[0];
8611
8612 /* SPDIF I/O */
8613 spec->dig_out = 0x05;
8614 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 8615 spec->dig_in = 0x09;
63177afc 8616 break;
d5c016b5 8617 }
441aa6a0
IM		 8618}
8619
d5c016b5
GM		 8620static int ca0132_prepare_verbs(struct hda_codec *codec)
8621{
8622/* Verbs + terminator (an empty element) */
a3d90d67 8623#define NUM_SPEC_VERBS 2
d5c016b5
GM		 8624 struct ca0132_spec *spec = codec->spec;
8625
8626 spec->chip_init_verbs = ca0132_init_verbs0;
88268ce8
CM		 8627 /*
8628 * Since desktop cards use pci_mmio, this can be used to determine
8629 * whether or not to use these verbs instead of a separate bool.
8630 */
8631 if (spec->use_pci_mmio)
e42c7c73 8632 spec->desktop_init_verbs = ca0132_init_verbs1;
6396bb22
KC		 8633 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
8634 sizeof(struct hda_verb),
8635 GFP_KERNEL);
d5c016b5
GM		 8636 if (!spec->spec_init_verbs)
8637 return -ENOMEM;
8638
d5c016b5 8639 /* config EAPD */
a3d90d67
AB		 8640 spec->spec_init_verbs[0].nid = 0x0b;
8641 spec->spec_init_verbs[0].param = 0x78D;
8642 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 8643
8644 /* Previously commented configuration */
8645 /*
a3d90d67
AB		 8646 spec->spec_init_verbs[2].nid = 0x0b;
8647 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8648 spec->spec_init_verbs[2].verb = 0x02;
8649
8650 spec->spec_init_verbs[3].nid = 0x10;
8651 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 8652 spec->spec_init_verbs[3].verb = 0x02;
8653
8654 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 8655 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 8656 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 8657 */
8658
8659 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8660 return 0;
8661}
8662
b29733db
CM		 8663/*
8664 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
8665 * Sound Blaster Z cards. However, they have different HDA codec subsystem
8666 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
8667 * daughter boards ID.
8668 */
8669static void sbz_detect_quirk(struct hda_codec *codec)
8670{
8671 struct ca0132_spec *spec = codec->spec;
8672
8673 switch (codec->core.subsystem_id) {
8674 case 0x11020033:
8675 spec->quirk = QUIRK_ZXR;
8676 break;
8677 case 0x1102003f:
8678 spec->quirk = QUIRK_ZXR_DBPRO;
8679 break;
8680 default:
8681 spec->quirk = QUIRK_SBZ;
8682 break;
8683 }
8684}
8685
95c6e9cb
IM		 8686static int patch_ca0132(struct hda_codec *codec)
8687{
8688 struct ca0132_spec *spec;
a73d511c 8689 int err;
d5c016b5 8690 const struct snd_pci_quirk *quirk;
95c6e9cb 8691
4e76a883 8692 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 8693
8694 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8695 if (!spec)
8696 return -ENOMEM;
8697 codec->spec = spec;
993884f6 8698 spec->codec = codec;
95c6e9cb 8699
d5c016b5
GM		 8700 /* Detect codec quirk */
8701 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8702 if (quirk)
8703 spec->quirk = quirk->value;
8704 else
8705 spec->quirk = QUIRK_NONE;
8706
b29733db
CM		 8707 if (spec->quirk == QUIRK_SBZ)
8708 sbz_detect_quirk(codec);
8709
ebabde1e
CM		 8710 if (spec->quirk == QUIRK_ZXR_DBPRO)
8711 codec->patch_ops = dbpro_patch_ops;
8712 else
8713 codec->patch_ops = ca0132_patch_ops;
8714
8715 codec->pcm_format_first = 1;
8716 codec->no_sticky_stream = 1;
8717
8718
e24aa0a4 8719 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 8720 spec->num_mixers = 1;
017310fb
CM		 8721
8722 /* Set which mixers each quirk uses. */
8723 switch (spec->quirk) {
8724 case QUIRK_SBZ:
e25e3445 8725 spec->mixers[0] = desktop_mixer;
017310fb
CM		 8726 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8727 break;
2e492b8e
CM		 8728 case QUIRK_ZXR:
8729 spec->mixers[0] = desktop_mixer;
8730 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
8731 break;
7675a2a9 8732 case QUIRK_ZXR_DBPRO:
7675a2a9 8733 break;
e25e3445
CM		 8734 case QUIRK_R3D:
8735 spec->mixers[0] = desktop_mixer;
8736 snd_hda_codec_set_name(codec, "Recon3D");
8737 break;
017310fb
CM		 8738 case QUIRK_R3DI:
8739 spec->mixers[0] = r3di_mixer;
8740 snd_hda_codec_set_name(codec, "Recon3Di");
8741 break;
88268ce8
CM		 8742 case QUIRK_AE5:
8743 spec->mixers[0] = desktop_mixer;
8744 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8745 break;
017310fb
CM		 8746 default:
8747 spec->mixers[0] = ca0132_mixer;
8748 break;
8749 }
a7e76271 8750
08eca6b1 8751 /* Setup whether or not to use alt functions/controls/pci_mmio */
009b8f97
CM		 8752 switch (spec->quirk) {
8753 case QUIRK_SBZ:
e42c7c73 8754 case QUIRK_R3D:
88268ce8 8755 case QUIRK_AE5:
2e492b8e 8756 case QUIRK_ZXR:
08eca6b1
CM		 8757 spec->use_alt_controls = true;
8758 spec->use_alt_functions = true;
8759 spec->use_pci_mmio = true;
8760 break;
009b8f97 8761 case QUIRK_R3DI:
47cdf76e 8762 spec->use_alt_controls = true;
009b8f97 8763 spec->use_alt_functions = true;
08eca6b1 8764 spec->use_pci_mmio = false;
009b8f97
CM		 8765 break;
8766 default:
47cdf76e 8767 spec->use_alt_controls = false;
009b8f97 8768 spec->use_alt_functions = false;
08eca6b1 8769 spec->use_pci_mmio = false;
009b8f97
CM		 8770 break;
8771 }
8772
08eca6b1
CM		 8773 if (spec->use_pci_mmio) {
8774 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8775 if (spec->mem_base == NULL) {
8776 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8777 spec->quirk = QUIRK_NONE;
8778 }
8779 }
8780
5aaca44d
IM		 8781 spec->base_init_verbs = ca0132_base_init_verbs;
8782 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 8783
993884f6
CCC		 8784 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8785
95c6e9cb
IM		 8786 ca0132_init_chip(codec);
8787
8788 ca0132_config(codec);
8789
d5c016b5
GM		 8790 err = ca0132_prepare_verbs(codec);
8791 if (err < 0)
cc91ceaf 8792 goto error;
d5c016b5 8793
a73d511c
IM		 8794 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8795 if (err < 0)
cc91ceaf 8796 goto error;
a73d511c 8797
95c6e9cb 8798 return 0;
cc91ceaf
TI		 8799
8800 error:
8801 ca0132_free(codec);
8802 return err;
95c6e9cb
IM		 8803}
8804
8805/*
8806 * patch entries
8807 */
b9a94a9c
TI		 8808static struct hda_device_id snd_hda_id_ca0132[] = {
8809 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 8810 {} /* terminator */
8811};
b9a94a9c 8812MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 8813
8814MODULE_LICENSE("GPL");
406261ce 8815MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 8816
d8a766a1 8817static struct hda_codec_driver ca0132_driver = {
b9a94a9c 8818 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 8819};
8820
d8a766a1 8821module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)