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ALSA: hda - Remove superfluous zero-clear memset in patch_ca0132.c
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/pci.h>
28#include <linux/mutex.h>
da155d5b 29#include <linux/module.h>
4aa3bb0c 30#include <linux/firmware.h>
95c6e9cb
IM		 31#include <sound/core.h>
32#include "hda_codec.h"
33#include "hda_local.h"
128bc4ba 34#include "hda_auto_parser.h"
95c6e9cb 35
bcd109c0
IM		 36#include "ca0132_regs.h"
37
4aa3bb0c
IM		 38#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
39#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
40
41#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
42#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
43#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
44
45#define MASTERCONTROL 0x80
46#define MASTERCONTROL_ALLOC_DMA_CHAN 9
47
95c6e9cb
IM		 48#define WIDGET_CHIP_CTRL 0x15
49#define WIDGET_DSP_CTRL 0x16
50
4aa3bb0c
IM		 51#define MEM_CONNID_MICIN1 3
52#define MEM_CONNID_MICIN2 5
53#define MEM_CONNID_MICOUT1 12
54#define MEM_CONNID_MICOUT2 14
55#define MEM_CONNID_WUH 10
56#define MEM_CONNID_DSP 16
57#define MEM_CONNID_DMIC 100
58
59#define SCP_SET 0
60#define SCP_GET 1
61
01ef7dbf
IM		 62#define EFX_FILE "ctefx.bin"
63
64MODULE_FIRMWARE(EFX_FILE);
65
95c6e9cb
IM		 66enum hda_cmd_vendor_io {
67 /* for DspIO node */
68 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
69 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
70
71 VENDOR_DSPIO_STATUS = 0xF01,
72 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
73 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
74 VENDOR_DSPIO_DSP_INIT = 0x703,
75 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
76 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
77
78 /* for ChipIO node */
79 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
80 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
81 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
82 VENDOR_CHIPIO_DATA_LOW = 0x300,
83 VENDOR_CHIPIO_DATA_HIGH = 0x400,
84
85 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
86 VENDOR_CHIPIO_STATUS = 0xF01,
87 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
88 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
89
4aa3bb0c
IM		 90 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
91 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
92
95c6e9cb 93 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 94 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 95
96 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
97 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
98 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
99 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
100 VENDOR_CHIPIO_FLAG_SET = 0x70F,
101 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 102 VENDOR_CHIPIO_PARAM_SET = 0x710,
103 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 104
105 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
106 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
107 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
108 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
109
4aa3bb0c
IM		 110 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
111 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
112 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
113 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
114
115 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
116 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
117 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
118 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
119 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
120 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
121
122 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 123};
124
125/*
126 * Control flag IDs
127 */
128enum control_flag_id {
129 /* Connection manager stream setup is bypassed/enabled */
130 CONTROL_FLAG_C_MGR = 0,
131 /* DSP DMA is bypassed/enabled */
132 CONTROL_FLAG_DMA = 1,
133 /* 8051 'idle' mode is disabled/enabled */
134 CONTROL_FLAG_IDLE_ENABLE = 2,
135 /* Tracker for the SPDIF-in path is bypassed/enabled */
136 CONTROL_FLAG_TRACKER = 3,
137 /* DigitalOut to Spdif2Out connection is disabled/enabled */
138 CONTROL_FLAG_SPDIF2OUT = 4,
139 /* Digital Microphone is disabled/enabled */
140 CONTROL_FLAG_DMIC = 5,
141 /* ADC_B rate is 48 kHz/96 kHz */
142 CONTROL_FLAG_ADC_B_96KHZ = 6,
143 /* ADC_C rate is 48 kHz/96 kHz */
144 CONTROL_FLAG_ADC_C_96KHZ = 7,
145 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
146 CONTROL_FLAG_DAC_96KHZ = 8,
147 /* DSP rate is 48 kHz/96 kHz */
148 CONTROL_FLAG_DSP_96KHZ = 9,
149 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
150 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
151 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
152 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
153 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
154 CONTROL_FLAG_DECODE_LOOP = 12,
155 /* De-emphasis filter on DAC-1 disabled/enabled */
156 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
157 /* De-emphasis filter on DAC-2 disabled/enabled */
158 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
159 /* De-emphasis filter on DAC-3 disabled/enabled */
160 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
161 /* High-pass filter on ADC_B disabled/enabled */
162 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
163 /* High-pass filter on ADC_C disabled/enabled */
164 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
165 /* Common mode on Port_A disabled/enabled */
166 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
167 /* Common mode on Port_D disabled/enabled */
168 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
169 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
170 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
171 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 172 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 173 /* ASI rate is 48kHz/96kHz */
174 CONTROL_FLAG_ASI_96KHZ = 22,
175 /* DAC power settings able to control attached ports no/yes */
176 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
177 /* Clock Stop OK reporting is disabled/enabled */
178 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
179 /* Number of control flags */
180 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
181};
182
183/*
184 * Control parameter IDs
185 */
4aa3bb0c 186enum control_param_id {
95c6e9cb
IM		 187 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
188 CONTROL_PARAM_SPDIF1_SOURCE = 2,
189
190 /* Stream Control */
191
192 /* Select stream with the given ID */
193 CONTROL_PARAM_STREAM_ID = 24,
194 /* Source connection point for the selected stream */
195 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
196 /* Destination connection point for the selected stream */
197 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
198 /* Number of audio channels in the selected stream */
199 CONTROL_PARAM_STREAMS_CHANNELS = 27,
200 /*Enable control for the selected stream */
201 CONTROL_PARAM_STREAM_CONTROL = 28,
202
203 /* Connection Point Control */
204
205 /* Select connection point with the given ID */
206 CONTROL_PARAM_CONN_POINT_ID = 29,
207 /* Connection point sample rate */
208 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
209
210 /* Node Control */
211
212 /* Select HDA node with the given ID */
213 CONTROL_PARAM_NODE_ID = 31
214};
215
216/*
217 * Dsp Io Status codes
218 */
219enum hda_vendor_status_dspio {
220 /* Success */
221 VENDOR_STATUS_DSPIO_OK = 0x00,
222 /* Busy, unable to accept new command, the host must retry */
223 VENDOR_STATUS_DSPIO_BUSY = 0x01,
224 /* SCP command queue is full */
225 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
226 /* SCP response queue is empty */
227 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
228};
229
230/*
231 * Chip Io Status codes
232 */
233enum hda_vendor_status_chipio {
234 /* Success */
235 VENDOR_STATUS_CHIPIO_OK = 0x00,
236 /* Busy, unable to accept new command, the host must retry */
237 VENDOR_STATUS_CHIPIO_BUSY = 0x01
238};
239
240/*
241 * CA0132 sample rate
242 */
243enum ca0132_sample_rate {
244 SR_6_000 = 0x00,
245 SR_8_000 = 0x01,
246 SR_9_600 = 0x02,
247 SR_11_025 = 0x03,
248 SR_16_000 = 0x04,
249 SR_22_050 = 0x05,
250 SR_24_000 = 0x06,
251 SR_32_000 = 0x07,
252 SR_44_100 = 0x08,
253 SR_48_000 = 0x09,
254 SR_88_200 = 0x0A,
255 SR_96_000 = 0x0B,
256 SR_144_000 = 0x0C,
257 SR_176_400 = 0x0D,
258 SR_192_000 = 0x0E,
259 SR_384_000 = 0x0F,
260
261 SR_COUNT = 0x10,
262
263 SR_RATE_UNKNOWN = 0x1F
264};
265
266/*
267 * Scp Helper function
268 */
269enum get_set {
270 IS_SET = 0,
271 IS_GET = 1,
272};
273
274/*
275 * Duplicated from ca0110 codec
276 */
277
278static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
279{
280 if (pin) {
cdd03ced 281 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
95c6e9cb
IM		 282 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
283 snd_hda_codec_write(codec, pin, 0,
284 AC_VERB_SET_AMP_GAIN_MUTE,
285 AMP_OUT_UNMUTE);
286 }
8e13fc1c 287 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
95c6e9cb
IM		 288 snd_hda_codec_write(codec, dac, 0,
289 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
290}
291
292static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
293{
294 if (pin) {
4740860b
TI		 295 snd_hda_set_pin_ctl(codec, pin, PIN_IN |
296 snd_hda_get_default_vref(codec, pin));
95c6e9cb
IM		 297 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
298 snd_hda_codec_write(codec, pin, 0,
299 AC_VERB_SET_AMP_GAIN_MUTE,
300 AMP_IN_UNMUTE(0));
301 }
8e13fc1c 302 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP))
95c6e9cb
IM		 303 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
304 AMP_IN_UNMUTE(0));
305}
306
307static char *dirstr[2] = { "Playback", "Capture" };
308
309static int _add_switch(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
310 int chan, int dir)
311{
312 char namestr[44];
313 int type = dir ? HDA_INPUT : HDA_OUTPUT;
314 struct snd_kcontrol_new knew =
315 HDA_CODEC_MUTE_MONO(namestr, nid, chan, 0, type);
c41999a2
DH		 316 if ((query_amp_caps(codec, nid, type) & AC_AMPCAP_MUTE) == 0) {
317 snd_printdd("Skipping '%s %s Switch' (no mute on node 0x%x)\n", pfx, dirstr[dir], nid);
318 return 0;
319 }
95c6e9cb
IM		 320 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
321 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
322}
323
01ef7dbf
IM		 324static int _add_volume(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
325 int chan, int dir)
326{
327 char namestr[44];
328 int type = dir ? HDA_INPUT : HDA_OUTPUT;
329 struct snd_kcontrol_new knew =
330 HDA_CODEC_VOLUME_MONO(namestr, nid, chan, 0, type);
331 if ((query_amp_caps(codec, nid, type) & AC_AMPCAP_NUM_STEPS) == 0) {
332 snd_printdd("Skipping '%s %s Volume' (no amp on node 0x%x)\n", pfx, dirstr[dir], nid);
333 return 0;
334 }
335 sprintf(namestr, "%s %s Volume", pfx, dirstr[dir]);
336 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
337}
338
339#define add_out_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 0)
340#define add_out_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 0)
341#define add_in_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 1)
342#define add_in_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 1)
343#define add_mono_switch(codec, nid, pfx, chan) \
344 _add_switch(codec, nid, pfx, chan, 0)
345#define add_mono_volume(codec, nid, pfx, chan) \
346 _add_volume(codec, nid, pfx, chan, 0)
347#define add_in_mono_switch(codec, nid, pfx, chan) \
348 _add_switch(codec, nid, pfx, chan, 1)
349#define add_in_mono_volume(codec, nid, pfx, chan) \
350 _add_volume(codec, nid, pfx, chan, 1)
351
352enum dsp_download_state {
353 DSP_DOWNLOAD_FAILED = -1,
354 DSP_DOWNLOAD_INIT = 0,
355 DSP_DOWNLOADING = 1,
356 DSP_DOWNLOADED = 2
357};
358
01ef7dbf
IM		 359/* retrieve parameters from hda format */
360#define get_hdafmt_chs(fmt) (fmt & 0xf)
361#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
362#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
363#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
364
365/*
366 * CA0132 specific
367 */
368
369struct ca0132_spec {
370 struct auto_pin_cfg autocfg;
371 struct hda_multi_out multiout;
372 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
373 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
374 hda_nid_t hp_dac;
375 hda_nid_t input_pins[AUTO_PIN_LAST];
376 hda_nid_t adcs[AUTO_PIN_LAST];
377 hda_nid_t dig_out;
378 hda_nid_t dig_in;
379 unsigned int num_inputs;
380 long curr_hp_switch;
381 long curr_hp_volume[2];
382 long curr_speaker_switch;
383 const char *input_labels[AUTO_PIN_LAST];
384 struct hda_pcm pcm_rec[2]; /* PCM information */
385
386 /* chip access */
387 struct mutex chipio_mutex; /* chip access mutex */
388 u32 curr_chip_addx;
389
390 /* DSP download related */
391 enum dsp_download_state dsp_state;
392 unsigned int dsp_stream_id;
393 unsigned int wait_scp;
394 unsigned int wait_scp_header;
395 unsigned int wait_num_data;
396 unsigned int scp_resp_header;
397 unsigned int scp_resp_data[4];
398 unsigned int scp_resp_count;
399};
400
401/*
402 * CA0132 codec access
403 */
404unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
405 unsigned int verb, unsigned int parm, unsigned int *res)
406{
407 unsigned int response;
408 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
409 *res = response;
410
411 return ((response == -1) ? -1 : 0);
412}
413
414static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
415 unsigned short converter_format, unsigned int *res)
416{
417 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
418 converter_format & 0xffff, res);
419}
420
421static int codec_set_converter_stream_channel(struct hda_codec *codec,
422 hda_nid_t nid, unsigned char stream,
423 unsigned char channel, unsigned int *res)
424{
425 unsigned char converter_stream_channel = 0;
426
427 converter_stream_channel = (stream << 4) | (channel & 0x0f);
428 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
429 converter_stream_channel, res);
430}
431
432/* Chip access helper function */
433static int chipio_send(struct hda_codec *codec,
434 unsigned int reg,
435 unsigned int data)
436{
437 unsigned int res;
438 int retry = 50;
439
440 /* send bits of data specified by reg */
441 do {
442 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
443 reg, data);
444 if (res == VENDOR_STATUS_CHIPIO_OK)
445 return 0;
446 } while (--retry);
447 return -EIO;
448}
449
450/*
451 * Write chip address through the vendor widget -- NOT protected by the Mutex!
452 */
453static int chipio_write_address(struct hda_codec *codec,
454 unsigned int chip_addx)
455{
4861af80 456 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 457 int res;
458
4861af80
IM		 459 if (spec->curr_chip_addx == chip_addx)
460 return 0;
461
01ef7dbf
IM		 462 /* send low 16 bits of the address */
463 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
464 chip_addx & 0xffff);
465
466 if (res != -EIO) {
467 /* send high 16 bits of the address */
468 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
469 chip_addx >> 16);
470 }
471
4861af80 472 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
01ef7dbf 473
4861af80 474 return res;
01ef7dbf
IM		 475}
476
477/*
478 * Write data through the vendor widget -- NOT protected by the Mutex!
479 */
01ef7dbf
IM		 480static int chipio_write_data(struct hda_codec *codec, unsigned int data)
481{
482 int res;
483
484 /* send low 16 bits of the data */
485 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
486
487 if (res != -EIO) {
488 /* send high 16 bits of the data */
489 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
490 data >> 16);
491 }
492
493 return res;
494}
495
d5c21b88
IM		 496/*
497 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
498 */
01ef7dbf
IM		 499static int chipio_write_data_multiple(struct hda_codec *codec,
500 const u32 *data,
501 unsigned int count)
502{
503 int status = 0;
504
505 if (data == NULL) {
506 snd_printdd(KERN_ERR "chipio_write_data null ptr");
507 return -EINVAL;
508 }
509
510 while ((count-- != 0) && (status == 0))
511 status = chipio_write_data(codec, *data++);
512
513 return status;
514}
515
516
517/*
518 * Read data through the vendor widget -- NOT protected by the Mutex!
519 */
520static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
521{
522 int res;
523
524 /* post read */
525 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
526
527 if (res != -EIO) {
528 /* read status */
529 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
530 }
531
532 if (res != -EIO) {
533 /* read data */
534 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
535 VENDOR_CHIPIO_HIC_READ_DATA,
536 0);
537 }
538
539 return res;
540}
541
542/*
543 * Write given value to the given address through the chip I/O widget.
544 * protected by the Mutex
545 */
546static int chipio_write(struct hda_codec *codec,
547 unsigned int chip_addx, const unsigned int data)
548{
549 struct ca0132_spec *spec = codec->spec;
550 int err;
551
552 mutex_lock(&spec->chipio_mutex);
553
554 /* write the address, and if successful proceed to write data */
555 err = chipio_write_address(codec, chip_addx);
556 if (err < 0)
557 goto exit;
558
559 err = chipio_write_data(codec, data);
560 if (err < 0)
561 goto exit;
562
563exit:
564 mutex_unlock(&spec->chipio_mutex);
565 return err;
566}
567
d5c21b88
IM		 568/*
569 * Write multiple values to the given address through the chip I/O widget.
570 * protected by the Mutex
571 */
01ef7dbf
IM		 572static int chipio_write_multiple(struct hda_codec *codec,
573 u32 chip_addx,
574 const u32 *data,
575 unsigned int count)
576{
577 struct ca0132_spec *spec = codec->spec;
578 int status;
579
580 mutex_lock(&spec->chipio_mutex);
4861af80 581 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 582 if (status < 0)
583 goto error;
584
585 status = chipio_write_data_multiple(codec, data, count);
586error:
587 mutex_unlock(&spec->chipio_mutex);
588
589 return status;
590}
591
592/*
593 * Read the given address through the chip I/O widget
594 * protected by the Mutex
595 */
596static int chipio_read(struct hda_codec *codec,
597 unsigned int chip_addx, unsigned int *data)
598{
599 struct ca0132_spec *spec = codec->spec;
600 int err;
601
602 mutex_lock(&spec->chipio_mutex);
603
604 /* write the address, and if successful proceed to write data */
605 err = chipio_write_address(codec, chip_addx);
606 if (err < 0)
607 goto exit;
608
609 err = chipio_read_data(codec, data);
610 if (err < 0)
611 goto exit;
612
613exit:
614 mutex_unlock(&spec->chipio_mutex);
615 return err;
616}
617
d5c21b88
IM		 618/*
619 * Set chip control flags through the chip I/O widget.
620 */
01ef7dbf
IM		 621static void chipio_set_control_flag(struct hda_codec *codec,
622 enum control_flag_id flag_id,
623 bool flag_state)
624{
625 unsigned int val;
626 unsigned int flag_bit;
627
628 flag_bit = (flag_state ? 1 : 0);
629 val = (flag_bit << 7) | (flag_id);
630 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
631 VENDOR_CHIPIO_FLAG_SET, val);
632}
633
d5c21b88
IM		 634/*
635 * Set chip parameters through the chip I/O widget.
636 */
01ef7dbf
IM		 637static void chipio_set_control_param(struct hda_codec *codec,
638 enum control_param_id param_id, int param_val)
639{
640 struct ca0132_spec *spec = codec->spec;
641 int val;
642
643 if ((param_id < 32) && (param_val < 8)) {
644 val = (param_val << 5) | (param_id);
645 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
646 VENDOR_CHIPIO_PARAM_SET, val);
647 } else {
648 mutex_lock(&spec->chipio_mutex);
649 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
650 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
651 VENDOR_CHIPIO_PARAM_EX_ID_SET,
652 param_id);
653 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
654 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
655 param_val);
656 }
657 mutex_unlock(&spec->chipio_mutex);
658 }
659}
660
d5c21b88
IM		 661/*
662 * Set sampling rate of the connection point.
663 */
01ef7dbf
IM		 664static void chipio_set_conn_rate(struct hda_codec *codec,
665 int connid, enum ca0132_sample_rate rate)
666{
667 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
668 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
669 rate);
670}
671
d5c21b88
IM		 672/*
673 * Enable clocks.
674 */
01ef7dbf
IM		 675static void chipio_enable_clocks(struct hda_codec *codec)
676{
677 struct ca0132_spec *spec = codec->spec;
678
679 mutex_lock(&spec->chipio_mutex);
680 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
681 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
682 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
683 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
684 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
685 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
686 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
687 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
688 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
689 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
690 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
691 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
692 mutex_unlock(&spec->chipio_mutex);
693}
694
695/*
696 * CA0132 DSP IO stuffs
697 */
698static int dspio_send(struct hda_codec *codec, unsigned int reg,
699 unsigned int data)
700{
701 unsigned int res;
702 int retry = 50;
703
704 /* send bits of data specified by reg to dsp */
705 do {
706 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
707 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
708 return res;
709 } while (--retry);
710
711 return -EIO;
712}
713
d5c21b88
IM		 714/*
715 * Wait for DSP to be ready for commands
716 */
01ef7dbf
IM		 717static void dspio_write_wait(struct hda_codec *codec)
718{
4861af80
IM		 719 int status;
720 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 721
01ef7dbf 722 do {
4861af80
IM		 723 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
724 VENDOR_DSPIO_STATUS, 0);
725 if ((status == VENDOR_STATUS_DSPIO_OK) ||
726 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
727 break;
728 msleep(1);
729 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 730}
731
d5c21b88
IM		 732/*
733 * Write SCP data to DSP
734 */
01ef7dbf
IM		 735static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
736{
737 struct ca0132_spec *spec = codec->spec;
738 int status;
739
740 dspio_write_wait(codec);
741
742 mutex_lock(&spec->chipio_mutex);
743 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
744 scp_data & 0xffff);
745 if (status < 0)
746 goto error;
747
748 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
749 scp_data >> 16);
750 if (status < 0)
751 goto error;
752
753 /* OK, now check if the write itself has executed*/
754 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
755 VENDOR_DSPIO_STATUS, 0);
756error:
757 mutex_unlock(&spec->chipio_mutex);
758
759 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
760 -EIO : 0;
761}
762
d5c21b88
IM		 763/*
764 * Write multiple SCP data to DSP
765 */
01ef7dbf
IM		 766static int dspio_write_multiple(struct hda_codec *codec,
767 unsigned int *buffer, unsigned int size)
768{
769 int status = 0;
770 unsigned int count;
771
772 if ((buffer == NULL))
773 return -EINVAL;
774
775 count = 0;
776 while (count < size) {
777 status = dspio_write(codec, *buffer++);
778 if (status != 0)
779 break;
780 count++;
781 }
782
783 return status;
784}
785
d5c21b88
IM		 786/*
787 * Construct the SCP header using corresponding fields
788 */
01ef7dbf
IM		 789static inline unsigned int
790make_scp_header(unsigned int target_id, unsigned int source_id,
791 unsigned int get_flag, unsigned int req,
792 unsigned int device_flag, unsigned int resp_flag,
793 unsigned int error_flag, unsigned int data_size)
794{
795 unsigned int header = 0;
796
797 header = (data_size & 0x1f) << 27;
798 header |= (error_flag & 0x01) << 26;
799 header |= (resp_flag & 0x01) << 25;
800 header |= (device_flag & 0x01) << 24;
801 header |= (req & 0x7f) << 17;
802 header |= (get_flag & 0x01) << 16;
803 header |= (source_id & 0xff) << 8;
804 header |= target_id & 0xff;
805
806 return header;
807}
808
d5c21b88
IM		 809/*
810 * Extract corresponding fields from SCP header
811 */
01ef7dbf
IM		 812static inline void
813extract_scp_header(unsigned int header,
814 unsigned int *target_id, unsigned int *source_id,
815 unsigned int *get_flag, unsigned int *req,
816 unsigned int *device_flag, unsigned int *resp_flag,
817 unsigned int *error_flag, unsigned int *data_size)
818{
819 if (data_size)
820 *data_size = (header >> 27) & 0x1f;
821 if (error_flag)
822 *error_flag = (header >> 26) & 0x01;
823 if (resp_flag)
824 *resp_flag = (header >> 25) & 0x01;
825 if (device_flag)
826 *device_flag = (header >> 24) & 0x01;
827 if (req)
828 *req = (header >> 17) & 0x7f;
829 if (get_flag)
830 *get_flag = (header >> 16) & 0x01;
831 if (source_id)
832 *source_id = (header >> 8) & 0xff;
833 if (target_id)
834 *target_id = header & 0xff;
835}
836
837#define SCP_MAX_DATA_WORDS (16)
838
839/* Structure to contain any SCP message */
840struct scp_msg {
841 unsigned int hdr;
842 unsigned int data[SCP_MAX_DATA_WORDS];
843};
844
d5c21b88
IM		 845/*
846 * Send SCP message to DSP
847 */
01ef7dbf
IM		 848static int dspio_send_scp_message(struct hda_codec *codec,
849 unsigned char *send_buf,
850 unsigned int send_buf_size,
851 unsigned char *return_buf,
852 unsigned int return_buf_size,
853 unsigned int *bytes_returned)
854{
855 struct ca0132_spec *spec = codec->spec;
856 int retry;
857 int status = -1;
858 unsigned int scp_send_size = 0;
859 unsigned int total_size;
860 bool waiting_for_resp = false;
861 unsigned int header;
862 struct scp_msg *ret_msg;
863 unsigned int resp_src_id, resp_target_id;
864 unsigned int data_size, src_id, target_id, get_flag, device_flag;
865
866 if (bytes_returned)
867 *bytes_returned = 0;
868
869 /* get scp header from buffer */
870 header = *((unsigned int *)send_buf);
871 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
872 &device_flag, NULL, NULL, &data_size);
873 scp_send_size = data_size + 1;
874 total_size = (scp_send_size * 4);
875
876 if (send_buf_size < total_size)
877 return -EINVAL;
878
879 if (get_flag || device_flag) {
880 if (!return_buf || return_buf_size < 4 || !bytes_returned)
881 return -EINVAL;
882
883 spec->wait_scp_header = *((unsigned int *)send_buf);
884
885 /* swap source id with target id */
886 resp_target_id = src_id;
887 resp_src_id = target_id;
888 spec->wait_scp_header &= 0xffff0000;
889 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
890 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
891 spec->wait_scp = 1;
892 waiting_for_resp = true;
893 }
894
895 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
896 scp_send_size);
897 if (status < 0) {
898 spec->wait_scp = 0;
899 return status;
900 }
901
902 if (waiting_for_resp) {
903 memset(return_buf, 0, return_buf_size);
904 retry = 50;
905 do {
906 msleep(20);
907 } while (spec->wait_scp && (--retry != 0));
908 waiting_for_resp = false;
909 if (retry != 0) {
910 ret_msg = (struct scp_msg *)return_buf;
911 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
912 memcpy(&ret_msg->data, spec->scp_resp_data,
913 spec->wait_num_data);
914 *bytes_returned = (spec->scp_resp_count + 1) * 4;
915 status = 0;
916 } else {
917 status = -EIO;
918 }
919 spec->wait_scp = 0;
920 }
921
922 return status;
923}
924
d5c21b88
IM		 925/**
926 * Prepare and send the SCP message to DSP
927 * @codec: the HDA codec
928 * @mod_id: ID of the DSP module to send the command
929 * @req: ID of request to send to the DSP module
930 * @dir: SET or GET
931 * @data: pointer to the data to send with the request, request specific
932 * @len: length of the data, in bytes
933 * @reply: point to the buffer to hold data returned for a reply
934 * @reply_len: length of the reply buffer returned from GET
935 *
936 * Returns zero or a negative error code.
937 */
01ef7dbf
IM		 938static int dspio_scp(struct hda_codec *codec,
939 int mod_id, int req, int dir, void *data, unsigned int len,
940 void *reply, unsigned int *reply_len)
941{
942 int status = 0;
943 struct scp_msg scp_send, scp_reply;
944 unsigned int ret_bytes, send_size, ret_size;
945 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
946 unsigned int reply_data_size;
947
948 memset(&scp_send, 0, sizeof(scp_send));
949 memset(&scp_reply, 0, sizeof(scp_reply));
950
951 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
952 return -EINVAL;
953
954 if (dir == SCP_GET && reply == NULL) {
955 snd_printdd(KERN_ERR "dspio_scp get but has no buffer");
956 return -EINVAL;
957 }
958
959 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
960 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms");
961 return -EINVAL;
962 }
963
964 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
965 0, 0, 0, len/sizeof(unsigned int));
966 if (data != NULL && len > 0) {
967 len = min((unsigned int)(sizeof(scp_send.data)), len);
968 memcpy(scp_send.data, data, len);
969 }
970
971 ret_bytes = 0;
972 send_size = sizeof(unsigned int) + len;
973 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
974 send_size, (unsigned char *)&scp_reply,
975 sizeof(scp_reply), &ret_bytes);
976
977 if (status < 0) {
978 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed");
979 return status;
980 }
981
982 /* extract send and reply headers members */
983 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
984 NULL, NULL, NULL, NULL, NULL);
985 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
986 &reply_resp_flag, &reply_error_flag,
987 &reply_data_size);
988
989 if (!send_get_flag)
990 return 0;
991
992 if (reply_resp_flag && !reply_error_flag) {
993 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
994 / sizeof(unsigned int);
995
996 if (*reply_len < ret_size*sizeof(unsigned int)) {
997 snd_printdd(KERN_ERR "reply too long for buf");
998 return -EINVAL;
999 } else if (ret_size != reply_data_size) {
1000 snd_printdd(KERN_ERR "RetLen and HdrLen .NE.");
1001 return -EINVAL;
1002 } else {
1003 *reply_len = ret_size*sizeof(unsigned int);
1004 memcpy(reply, scp_reply.data, *reply_len);
1005 }
1006 } else {
1007 snd_printdd(KERN_ERR "reply ill-formed or errflag set");
1008 return -EIO;
1009 }
1010
1011 return status;
1012}
1013
d5c21b88
IM		 1014/*
1015 * Allocate a DSP DMA channel via an SCP message
1016 */
01ef7dbf
IM		 1017static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1018{
1019 int status = 0;
1020 unsigned int size = sizeof(dma_chan);
1021
1022 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin");
1023 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1024 SCP_GET, NULL, 0, dma_chan, &size);
1025
1026 if (status < 0) {
1027 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed");
1028 return status;
1029 }
1030
1031 if ((*dma_chan + 1) == 0) {
1032 snd_printdd(KERN_INFO "no free dma channels to allocate");
1033 return -EBUSY;
1034 }
1035
1036 snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1037 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete");
1038
1039 return status;
1040}
1041
d5c21b88
IM		 1042/*
1043 * Free a DSP DMA via an SCP message
1044 */
01ef7dbf
IM		 1045static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1046{
1047 int status = 0;
1048 unsigned int dummy = 0;
1049
1050 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin");
1051 snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan);
1052
1053 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1054 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1055
1056 if (status < 0) {
1057 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed");
1058 return status;
1059 }
1060
1061 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete");
1062
1063 return status;
1064}
1065
1066/*
d5c21b88 1067 * (Re)start the DSP
01ef7dbf
IM		 1068 */
1069static int dsp_set_run_state(struct hda_codec *codec)
1070{
1071 unsigned int dbg_ctrl_reg;
1072 unsigned int halt_state;
1073 int err;
1074
1075 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1076 if (err < 0)
1077 return err;
1078
1079 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1080 DSP_DBGCNTL_STATE_LOBIT;
1081
1082 if (halt_state != 0) {
1083 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1084 DSP_DBGCNTL_SS_MASK);
1085 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1086 dbg_ctrl_reg);
1087 if (err < 0)
1088 return err;
1089
1090 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1091 DSP_DBGCNTL_EXEC_MASK;
1092 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1093 dbg_ctrl_reg);
1094 if (err < 0)
1095 return err;
1096 }
1097
1098 return 0;
1099}
1100
d5c21b88
IM		 1101/*
1102 * Reset the DSP
1103 */
01ef7dbf
IM		 1104static int dsp_reset(struct hda_codec *codec)
1105{
1106 unsigned int res;
1107 int retry = 20;
1108
1109 snd_printdd("dsp_reset\n");
1110 do {
1111 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1112 retry--;
1113 } while (res == -EIO && retry);
1114
1115 if (!retry) {
1116 snd_printdd("dsp_reset timeout\n");
1117 return -EIO;
1118 }
1119
1120 return 0;
1121}
1122
d5c21b88
IM		 1123/*
1124 * Convert chip address to DSP address
1125 */
01ef7dbf
IM		 1126static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1127 bool *code, bool *yram)
1128{
1129 *code = *yram = false;
1130
1131 if (UC_RANGE(chip_addx, 1)) {
1132 *code = true;
1133 return UC_OFF(chip_addx);
1134 } else if (X_RANGE_ALL(chip_addx, 1)) {
1135 return X_OFF(chip_addx);
1136 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1137 *yram = true;
1138 return Y_OFF(chip_addx);
1139 }
1140
1141 return (unsigned int)INVALID_CHIP_ADDRESS;
1142}
1143
d5c21b88
IM		 1144/*
1145 * Check if the DSP DMA is active
1146 */
01ef7dbf
IM		 1147static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1148{
1149 unsigned int dma_chnlstart_reg;
1150
1151 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1152
1153 return ((dma_chnlstart_reg & (1 <<
1154 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1155}
1156
1157static int dsp_dma_setup_common(struct hda_codec *codec,
1158 unsigned int chip_addx,
1159 unsigned int dma_chan,
1160 unsigned int port_map_mask,
1161 bool ovly)
1162{
1163 int status = 0;
1164 unsigned int chnl_prop;
1165 unsigned int dsp_addx;
1166 unsigned int active;
1167 bool code, yram;
1168
1169 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------");
1170
1171 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1172 snd_printdd(KERN_ERR "dma chan num invalid");
1173 return -EINVAL;
1174 }
1175
1176 if (dsp_is_dma_active(codec, dma_chan)) {
1177 snd_printdd(KERN_ERR "dma already active");
1178 return -EBUSY;
1179 }
1180
1181 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1182
1183 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1184 snd_printdd(KERN_ERR "invalid chip addr");
1185 return -ENXIO;
1186 }
1187
1188 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1189 active = 0;
1190
1191 snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm");
1192
1193 if (ovly) {
1194 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1195 &chnl_prop);
1196
1197 if (status < 0) {
1198 snd_printdd(KERN_ERR "read CHNLPROP Reg fail");
1199 return status;
1200 }
1201 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP");
1202 }
1203
1204 if (!code)
1205 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1206 else
1207 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1208
1209 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1210
1211 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1212 if (status < 0) {
1213 snd_printdd(KERN_ERR "write CHNLPROP Reg fail");
1214 return status;
1215 }
1216 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP");
1217
1218 if (ovly) {
1219 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1220 &active);
1221
1222 if (status < 0) {
1223 snd_printdd(KERN_ERR "read ACTIVE Reg fail");
1224 return status;
1225 }
1226 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE");
1227 }
1228
1229 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1230 DSPDMAC_ACTIVE_AAR_MASK;
1231
1232 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1233 if (status < 0) {
1234 snd_printdd(KERN_ERR "write ACTIVE Reg fail");
1235 return status;
1236 }
1237
1238 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE");
1239
1240 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1241 port_map_mask);
1242 if (status < 0) {
1243 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail");
1244 return status;
1245 }
1246 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL");
1247
1248 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1249 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1250 if (status < 0) {
1251 snd_printdd(KERN_ERR "write IRQCNT Reg fail");
1252 return status;
1253 }
1254 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT");
1255
1256 snd_printdd(
1257 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1258 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1259 chip_addx, dsp_addx, dma_chan,
1260 port_map_mask, chnl_prop, active);
1261
1262 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------");
1263
1264 return 0;
1265}
1266
d5c21b88
IM		 1267/*
1268 * Setup the DSP DMA per-transfer-specific registers
1269 */
01ef7dbf
IM		 1270static int dsp_dma_setup(struct hda_codec *codec,
1271 unsigned int chip_addx,
1272 unsigned int count,
1273 unsigned int dma_chan)
1274{
1275 int status = 0;
1276 bool code, yram;
1277 unsigned int dsp_addx;
1278 unsigned int addr_field;
1279 unsigned int incr_field;
1280 unsigned int base_cnt;
1281 unsigned int cur_cnt;
1282 unsigned int dma_cfg = 0;
1283 unsigned int adr_ofs = 0;
1284 unsigned int xfr_cnt = 0;
1285 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1286 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1287
1288 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------");
1289
1290 if (count > max_dma_count) {
1291 snd_printdd(KERN_ERR "count too big");
1292 return -EINVAL;
1293 }
1294
1295 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1296 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1297 snd_printdd(KERN_ERR "invalid chip addr");
1298 return -ENXIO;
1299 }
1300
1301 snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm");
1302
1303 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1304 incr_field = 0;
1305
1306 if (!code) {
1307 addr_field <<= 1;
1308 if (yram)
1309 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1310
1311 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1312 }
1313
1314 dma_cfg = addr_field + incr_field;
1315 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1316 dma_cfg);
1317 if (status < 0) {
1318 snd_printdd(KERN_ERR "write DMACFG Reg fail");
1319 return status;
1320 }
1321 snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG");
1322
1323 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1324 (code ? 0 : 1));
1325
1326 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1327 adr_ofs);
1328 if (status < 0) {
1329 snd_printdd(KERN_ERR "write DSPADROFS Reg fail");
1330 return status;
1331 }
1332 snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS");
1333
1334 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1335
1336 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1337
1338 xfr_cnt = base_cnt | cur_cnt;
1339
1340 status = chipio_write(codec,
1341 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1342 if (status < 0) {
1343 snd_printdd(KERN_ERR "write XFRCNT Reg fail");
1344 return status;
1345 }
1346 snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT");
1347
1348 snd_printdd(
1349 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1350 "ADROFS=0x%x, XFRCNT=0x%x\n",
1351 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1352
1353 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------");
1354
1355 return 0;
1356}
1357
d5c21b88
IM		 1358/*
1359 * Start the DSP DMA
1360 */
01ef7dbf
IM		 1361static int dsp_dma_start(struct hda_codec *codec,
1362 unsigned int dma_chan, bool ovly)
1363{
1364 unsigned int reg = 0;
1365 int status = 0;
1366
1367 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------");
1368
1369 if (ovly) {
1370 status = chipio_read(codec,
1371 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1372
1373 if (status < 0) {
1374 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1375 return status;
1376 }
1377 snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART");
1378
1379 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1380 DSPDMAC_CHNLSTART_DIS_MASK);
1381 }
1382
1383 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1384 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1385 if (status < 0) {
1386 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1387 return status;
1388 }
1389 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------");
1390
1391 return status;
1392}
1393
d5c21b88
IM		 1394/*
1395 * Stop the DSP DMA
1396 */
01ef7dbf
IM		 1397static int dsp_dma_stop(struct hda_codec *codec,
1398 unsigned int dma_chan, bool ovly)
1399{
1400 unsigned int reg = 0;
1401 int status = 0;
1402
1403 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------");
1404
1405 if (ovly) {
1406 status = chipio_read(codec,
1407 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1408
1409 if (status < 0) {
1410 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1411 return status;
1412 }
1413 snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART");
1414 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1415 DSPDMAC_CHNLSTART_DIS_MASK);
1416 }
1417
1418 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1419 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1420 if (status < 0) {
1421 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1422 return status;
1423 }
1424 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------");
1425
1426 return status;
1427}
1428
d5c21b88
IM		 1429/**
1430 * Allocate router ports
1431 *
1432 * @codec: the HDA codec
1433 * @num_chans: number of channels in the stream
1434 * @ports_per_channel: number of ports per channel
1435 * @start_device: start device
1436 * @port_map: pointer to the port list to hold the allocated ports
1437 *
1438 * Returns zero or a negative error code.
1439 */
01ef7dbf
IM		 1440static int dsp_allocate_router_ports(struct hda_codec *codec,
1441 unsigned int num_chans,
1442 unsigned int ports_per_channel,
1443 unsigned int start_device,
1444 unsigned int *port_map)
1445{
1446 int status = 0;
1447 int res;
1448 u8 val;
1449
1450 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1451 if (status < 0)
1452 return status;
1453
1454 val = start_device << 6;
1455 val |= (ports_per_channel - 1) << 4;
1456 val |= num_chans - 1;
1457
1458 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1459 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1460 val);
1461
1462 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1463 VENDOR_CHIPIO_PORT_ALLOC_SET,
1464 MEM_CONNID_DSP);
1465
1466 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1467 if (status < 0)
1468 return status;
1469
1470 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1471 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1472
1473 *port_map = res;
1474
1475 return (res < 0) ? res : 0;
1476}
1477
d5c21b88
IM		 1478/*
1479 * Free router ports
1480 */
01ef7dbf
IM		 1481static int dsp_free_router_ports(struct hda_codec *codec)
1482{
1483 int status = 0;
1484
1485 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1486 if (status < 0)
1487 return status;
1488
1489 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1490 VENDOR_CHIPIO_PORT_FREE_SET,
1491 MEM_CONNID_DSP);
1492
1493 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1494
1495 return status;
1496}
1497
d5c21b88
IM		 1498/*
1499 * Allocate DSP ports for the download stream
1500 */
01ef7dbf
IM		 1501static int dsp_allocate_ports(struct hda_codec *codec,
1502 unsigned int num_chans,
1503 unsigned int rate_multi, unsigned int *port_map)
1504{
1505 int status;
1506
1507 snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin");
1508
1509 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1510 snd_printdd(KERN_ERR "bad rate multiple");
1511 return -EINVAL;
1512 }
1513
1514 status = dsp_allocate_router_ports(codec, num_chans,
1515 rate_multi, 0, port_map);
1516
1517 snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete");
1518
1519 return status;
1520}
1521
01ef7dbf
IM		 1522static int dsp_allocate_ports_format(struct hda_codec *codec,
1523 const unsigned short fmt,
1524 unsigned int *port_map)
1525{
1526 int status;
1527 unsigned int num_chans;
1528
1529 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1530 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1531 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
1532
1533 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1534 snd_printdd(KERN_ERR "bad rate multiple");
1535 return -EINVAL;
1536 }
1537
1538 num_chans = get_hdafmt_chs(fmt) + 1;
1539
1540 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
1541
1542 return status;
1543}
1544
d5c21b88
IM		 1545/*
1546 * free DSP ports
1547 */
1548static int dsp_free_ports(struct hda_codec *codec)
1549{
1550 int status;
1551
1552 snd_printdd(KERN_INFO " dsp_free_ports() -- begin");
1553
1554 status = dsp_free_router_ports(codec);
1555 if (status < 0) {
1556 snd_printdd(KERN_ERR "free router ports fail");
1557 return status;
1558 }
1559 snd_printdd(KERN_INFO " dsp_free_ports() -- complete");
1560
1561 return status;
1562}
1563
01ef7dbf
IM		 1564/*
1565 * HDA DMA engine stuffs for DSP code download
1566 */
1567struct dma_engine {
1568 struct hda_codec *codec;
1569 unsigned short m_converter_format;
1570 struct snd_dma_buffer *dmab;
1571 unsigned int buf_size;
1572};
1573
1574
1575enum dma_state {
1576 DMA_STATE_STOP = 0,
1577 DMA_STATE_RUN = 1
1578};
1579
1580static int dma_convert_to_hda_format(
e97249dd
IM		 1581 unsigned int sample_rate,
1582 unsigned short channels,
01ef7dbf
IM		 1583 unsigned short *hda_format)
1584{
1585 unsigned int format_val;
1586
1587 format_val = snd_hda_calc_stream_format(
e97249dd
IM		 1588 sample_rate,
1589 channels,
01ef7dbf 1590 SNDRV_PCM_FORMAT_S32_LE,
e97249dd 1591 32, 0);
01ef7dbf
IM		 1592
1593 if (hda_format)
1594 *hda_format = (unsigned short)format_val;
1595
1596 return 0;
1597}
1598
d5c21b88
IM		 1599/*
1600 * Reset DMA for DSP download
1601 */
01ef7dbf
IM		 1602static int dma_reset(struct dma_engine *dma)
1603{
1604 struct hda_codec *codec = dma->codec;
1605 struct ca0132_spec *spec = codec->spec;
1606 int status;
1607
1608 if (dma->dmab)
1609 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
1610
1611 status = snd_hda_codec_load_dsp_prepare(codec,
1612 dma->m_converter_format,
1613 dma->buf_size,
1614 dma->dmab);
1615 if (status < 0)
1616 return status;
1617 spec->dsp_stream_id = status;
1618 return 0;
1619}
1620
1621static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 1622{
01ef7dbf
IM		 1623 bool cmd;
1624
1625 snd_printdd("dma_set_state state=%d\n", state);
1626
1627 switch (state) {
1628 case DMA_STATE_STOP:
1629 cmd = false;
1630 break;
1631 case DMA_STATE_RUN:
1632 cmd = true;
1633 break;
1634 default:
c41999a2
DH		 1635 return 0;
1636 }
01ef7dbf
IM		 1637
1638 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
1639 return 0;
95c6e9cb
IM		 1640}
1641
01ef7dbf
IM		 1642static unsigned int dma_get_buffer_size(struct dma_engine *dma)
1643{
1644 return dma->dmab->bytes;
1645}
95c6e9cb 1646
01ef7dbf
IM		 1647static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
1648{
1649 return dma->dmab->area;
1650}
95c6e9cb 1651
01ef7dbf
IM		 1652static int dma_xfer(struct dma_engine *dma,
1653 const unsigned int *data,
1654 unsigned int count)
1655{
1656 memcpy(dma->dmab->area, data, count);
1657 return 0;
1658}
95c6e9cb 1659
01ef7dbf
IM		 1660static void dma_get_converter_format(
1661 struct dma_engine *dma,
1662 unsigned short *format)
1663{
1664 if (format)
1665 *format = dma->m_converter_format;
1666}
95c6e9cb 1667
01ef7dbf 1668static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 1669{
01ef7dbf 1670 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 1671
01ef7dbf 1672 return spec->dsp_stream_id;
95c6e9cb
IM		 1673}
1674
01ef7dbf
IM		 1675struct dsp_image_seg {
1676 u32 magic;
1677 u32 chip_addr;
1678 u32 count;
1679 u32 data[0];
1680};
1681
1682static const u32 g_magic_value = 0x4c46584d;
1683static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
1684
1685static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 1686{
01ef7dbf
IM		 1687 return p->magic == g_magic_value;
1688}
95c6e9cb 1689
01ef7dbf
IM		 1690static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
1691{
1692 return g_chip_addr_magic_value == p->chip_addr;
1693}
95c6e9cb 1694
01ef7dbf
IM		 1695static bool is_last(const struct dsp_image_seg *p)
1696{
1697 return p->count == 0;
1698}
95c6e9cb 1699
01ef7dbf
IM		 1700static size_t dsp_sizeof(const struct dsp_image_seg *p)
1701{
1702 return sizeof(*p) + p->count*sizeof(u32);
1703}
1704
1705static const struct dsp_image_seg *get_next_seg_ptr(
1706 const struct dsp_image_seg *p)
1707{
1708 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 1709}
1710
1711/*
01ef7dbf 1712 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 1713 */
01ef7dbf 1714#define INVALID_DMA_CHANNEL (~0UL)
95c6e9cb 1715
d5c21b88
IM		 1716/*
1717 * Program a list of address/data pairs via the ChipIO widget.
1718 * The segment data is in the format of successive pairs of words.
1719 * These are repeated as indicated by the segment's count field.
1720 */
01ef7dbf
IM		 1721static int dspxfr_hci_write(struct hda_codec *codec,
1722 const struct dsp_image_seg *fls)
95c6e9cb 1723{
01ef7dbf
IM		 1724 int status;
1725 const u32 *data;
1726 unsigned int count;
95c6e9cb 1727
01ef7dbf
IM		 1728 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
1729 snd_printdd(KERN_ERR "hci_write invalid params");
1730 return -EINVAL;
95c6e9cb
IM		 1731 }
1732
01ef7dbf
IM		 1733 count = fls->count;
1734 data = (u32 *)(fls->data);
1735 while (count >= 2) {
1736 status = chipio_write(codec, data[0], data[1]);
1737 if (status < 0) {
1738 snd_printdd(KERN_ERR "hci_write chipio failed");
1739 return status;
1740 }
1741 count -= 2;
1742 data += 2;
1743 }
1744 return 0;
95c6e9cb
IM		 1745}
1746
d5c21b88
IM		 1747/**
1748 * Write a block of data into DSP code or data RAM using pre-allocated
1749 * DMA engine.
1750 *
1751 * @codec: the HDA codec
1752 * @fls: pointer to a fast load image
1753 * @reloc: Relocation address for loading single-segment overlays, or 0 for
1754 * no relocation
1755 * @dma_engine: pointer to DMA engine to be used for DSP download
1756 * @dma_chan: The number of DMA channels used for DSP download
1757 * @port_map_mask: port mapping
1758 * @ovly: TRUE if overlay format is required
1759 *
1760 * Returns zero or a negative error code.
1761 */
01ef7dbf
IM		 1762static int dspxfr_one_seg(struct hda_codec *codec,
1763 const struct dsp_image_seg *fls,
1764 unsigned int reloc,
1765 struct dma_engine *dma_engine,
1766 unsigned int dma_chan,
1767 unsigned int port_map_mask,
1768 bool ovly)
95c6e9cb 1769{
01ef7dbf
IM		 1770 int status;
1771 bool comm_dma_setup_done = false;
1772 const unsigned int *data;
1773 unsigned int chip_addx;
1774 unsigned int words_to_write;
1775 unsigned int buffer_size_words;
1776 unsigned char *buffer_addx;
1777 unsigned short hda_format;
1778 unsigned int sample_rate_div;
1779 unsigned int sample_rate_mul;
1780 unsigned int num_chans;
1781 unsigned int hda_frame_size_words;
1782 unsigned int remainder_words;
1783 const u32 *data_remainder;
1784 u32 chip_addx_remainder;
1785 unsigned int run_size_words;
1786 const struct dsp_image_seg *hci_write = NULL;
1787 int retry;
1788
1789 if (fls == NULL)
1790 return -EINVAL;
1791 if (is_hci_prog_list_seg(fls)) {
1792 hci_write = fls;
1793 fls = get_next_seg_ptr(fls);
1794 }
95c6e9cb 1795
01ef7dbf
IM		 1796 if (hci_write && (!fls || is_last(fls))) {
1797 snd_printdd("hci_write\n");
1798 return dspxfr_hci_write(codec, hci_write);
1799 }
95c6e9cb 1800
01ef7dbf
IM		 1801 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
1802 snd_printdd("Invalid Params\n");
1803 return -EINVAL;
95c6e9cb
IM		 1804 }
1805
01ef7dbf
IM		 1806 data = fls->data;
1807 chip_addx = fls->chip_addr,
1808 words_to_write = fls->count;
1809
1810 if (!words_to_write)
1811 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
1812 if (reloc)
1813 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
1814
1815 if (!UC_RANGE(chip_addx, words_to_write) &&
1816 !X_RANGE_ALL(chip_addx, words_to_write) &&
1817 !Y_RANGE_ALL(chip_addx, words_to_write)) {
1818 snd_printdd("Invalid chip_addx Params\n");
1819 return -EINVAL;
95c6e9cb
IM		 1820 }
1821
01ef7dbf
IM		 1822 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
1823 sizeof(u32);
1824
1825 buffer_addx = dma_get_buffer_addr(dma_engine);
1826
1827 if (buffer_addx == NULL) {
1828 snd_printdd(KERN_ERR "dma_engine buffer NULL\n");
1829 return -EINVAL;
1830 }
1831
1832 dma_get_converter_format(dma_engine, &hda_format);
1833 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
1834 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
1835 num_chans = get_hdafmt_chs(hda_format) + 1;
1836
1837 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
1838 (num_chans * sample_rate_mul / sample_rate_div));
1839
1840 buffer_size_words = min(buffer_size_words,
1841 (unsigned int)(UC_RANGE(chip_addx, 1) ?
1842 65536 : 32768));
1843 buffer_size_words -= buffer_size_words % hda_frame_size_words;
1844 snd_printdd(
1845 "chpadr=0x%08x frmsz=%u nchan=%u "
1846 "rate_mul=%u div=%u bufsz=%u\n",
1847 chip_addx, hda_frame_size_words, num_chans,
1848 sample_rate_mul, sample_rate_div, buffer_size_words);
1849
1850 if ((buffer_addx == NULL) || (hda_frame_size_words == 0) ||
1851 (buffer_size_words < hda_frame_size_words)) {
1852 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n");
1853 return -EINVAL;
1854 }
1855
1856 remainder_words = words_to_write % hda_frame_size_words;
1857 data_remainder = data;
1858 chip_addx_remainder = chip_addx;
1859
1860 data += remainder_words;
1861 chip_addx += remainder_words*sizeof(u32);
1862 words_to_write -= remainder_words;
1863
1864 while (words_to_write != 0) {
1865 run_size_words = min(buffer_size_words, words_to_write);
1866 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
1867 words_to_write, run_size_words, remainder_words);
1868 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
1869 if (!comm_dma_setup_done) {
1870 status = dsp_dma_stop(codec, dma_chan, ovly);
1871 if (status < 0)
1872 return -EIO;
1873 status = dsp_dma_setup_common(codec, chip_addx,
1874 dma_chan, port_map_mask, ovly);
1875 if (status < 0)
1876 return status;
1877 comm_dma_setup_done = true;
1878 }
1879
1880 status = dsp_dma_setup(codec, chip_addx,
1881 run_size_words, dma_chan);
1882 if (status < 0)
1883 return status;
1884 status = dsp_dma_start(codec, dma_chan, ovly);
1885 if (status < 0)
1886 return status;
1887 if (!dsp_is_dma_active(codec, dma_chan)) {
1888 snd_printdd(KERN_ERR "dspxfr:DMA did not start");
1889 return -EIO;
1890 }
1891 status = dma_set_state(dma_engine, DMA_STATE_RUN);
1892 if (status < 0)
1893 return status;
1894 if (remainder_words != 0) {
1895 status = chipio_write_multiple(codec,
1896 chip_addx_remainder,
1897 data_remainder,
1898 remainder_words);
1899 remainder_words = 0;
1900 }
1901 if (hci_write) {
1902 status = dspxfr_hci_write(codec, hci_write);
1903 hci_write = NULL;
1904 }
1905 retry = 5000;
1906 while (dsp_is_dma_active(codec, dma_chan)) {
1907 if (--retry <= 0)
1908 break;
1909 }
1910 snd_printdd(KERN_INFO "+++++ DMA complete");
1911 dma_set_state(dma_engine, DMA_STATE_STOP);
1912 dma_reset(dma_engine);
1913
1914 if (status < 0)
1915 return status;
1916
1917 data += run_size_words;
1918 chip_addx += run_size_words*sizeof(u32);
1919 words_to_write -= run_size_words;
1920 }
1921
1922 if (remainder_words != 0) {
1923 status = chipio_write_multiple(codec, chip_addx_remainder,
1924 data_remainder, remainder_words);
1925 }
1926
1927 return status;
95c6e9cb
IM		 1928}
1929
d5c21b88
IM		 1930/**
1931 * Write the entire DSP image of a DSP code/data overlay to DSP memories
1932 *
1933 * @codec: the HDA codec
1934 * @fls_data: pointer to a fast load image
1935 * @reloc: Relocation address for loading single-segment overlays, or 0 for
1936 * no relocation
e97249dd
IM		 1937 * @sample_rate: sampling rate of the stream used for DSP download
1938 * @number_channels: channels of the stream used for DSP download
d5c21b88
IM		 1939 * @ovly: TRUE if overlay format is required
1940 *
1941 * Returns zero or a negative error code.
1942 */
01ef7dbf
IM		 1943static int dspxfr_image(struct hda_codec *codec,
1944 const struct dsp_image_seg *fls_data,
e97249dd
IM		 1945 unsigned int reloc,
1946 unsigned int sample_rate,
1947 unsigned short channels,
01ef7dbf 1948 bool ovly)
95c6e9cb
IM		 1949{
1950 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1951 int status;
1952 unsigned short hda_format = 0;
1953 unsigned int response;
1954 unsigned char stream_id = 0;
1955 struct dma_engine *dma_engine;
1956 unsigned int dma_chan;
1957 unsigned int port_map_mask;
1958
1959 if (fls_data == NULL)
1960 return -EINVAL;
1961
1962 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
063bca09
TI		 1963 if (!dma_engine)
1964 return -ENOMEM;
95c6e9cb 1965
01ef7dbf
IM		 1966 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
1967 if (!dma_engine->dmab) {
1968 status = -ENOMEM;
1969 goto exit;
1970 }
95c6e9cb 1971
01ef7dbf 1972 dma_engine->codec = codec;
e97249dd 1973 dma_convert_to_hda_format(sample_rate, channels, &hda_format);
01ef7dbf
IM		 1974 dma_engine->m_converter_format = hda_format;
1975 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
1976 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
1977
1978 dma_chan = 0;
1979
1980 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
1981 hda_format, &response);
1982
1983 if (status < 0) {
1984 snd_printdd(KERN_ERR "set converter format fail");
1985 goto exit;
1986 }
1987
1988 status = snd_hda_codec_load_dsp_prepare(codec,
1989 dma_engine->m_converter_format,
1990 dma_engine->buf_size,
1991 dma_engine->dmab);
1992 if (status < 0)
95c6e9cb 1993 goto exit;
01ef7dbf
IM		 1994 spec->dsp_stream_id = status;
1995
1996 if (ovly) {
1997 status = dspio_alloc_dma_chan(codec, &dma_chan);
1998 if (status < 0) {
1999 snd_printdd(KERN_ERR "alloc dmachan fail");
2000 dma_chan = (unsigned int)INVALID_DMA_CHANNEL;
2001 goto exit;
2002 }
2003 }
95c6e9cb 2004
01ef7dbf
IM		 2005 port_map_mask = 0;
2006 status = dsp_allocate_ports_format(codec, hda_format,
2007 &port_map_mask);
2008 if (status < 0) {
2009 snd_printdd(KERN_ERR "alloc ports fail");
2010 goto exit;
2011 }
2012
2013 stream_id = dma_get_stream_id(dma_engine);
2014 status = codec_set_converter_stream_channel(codec,
2015 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2016 if (status < 0) {
2017 snd_printdd(KERN_ERR "set stream chan fail");
2018 goto exit;
2019 }
2020
2021 while ((fls_data != NULL) && !is_last(fls_data)) {
2022 if (!is_valid(fls_data)) {
2023 snd_printdd(KERN_ERR "FLS check fail");
2024 status = -EINVAL;
2025 goto exit;
2026 }
2027 status = dspxfr_one_seg(codec, fls_data, reloc,
2028 dma_engine, dma_chan,
2029 port_map_mask, ovly);
2030 if (status < 0)
2031 break;
2032
2033 if (is_hci_prog_list_seg(fls_data))
2034 fls_data = get_next_seg_ptr(fls_data);
2035
2036 if ((fls_data != NULL) && !is_last(fls_data))
2037 fls_data = get_next_seg_ptr(fls_data);
2038 }
2039
2040 if (port_map_mask != 0)
2041 status = dsp_free_ports(codec);
2042
2043 if (status < 0)
95c6e9cb
IM		 2044 goto exit;
2045
01ef7dbf
IM		 2046 status = codec_set_converter_stream_channel(codec,
2047 WIDGET_CHIP_CTRL, 0, 0, &response);
2048
95c6e9cb 2049exit:
01ef7dbf
IM		 2050 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2051 dspio_free_dma_chan(codec, dma_chan);
2052
2053 if (dma_engine->dmab)
2054 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2055 kfree(dma_engine->dmab);
2056 kfree(dma_engine);
2057
2058 return status;
95c6e9cb
IM		 2059}
2060
2061/*
01ef7dbf 2062 * CA0132 DSP download stuffs.
95c6e9cb 2063 */
01ef7dbf 2064static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2065{
01ef7dbf 2066 snd_printdd(KERN_INFO "---- dspload_post_setup ------");
95c6e9cb 2067
01ef7dbf
IM		 2068 /*set DSP speaker to 2.0 configuration*/
2069 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2070 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2071
01ef7dbf
IM		 2072 /*update write pointer*/
2073 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2074}
95c6e9cb 2075
d5c21b88
IM		 2076/**
2077 * Download DSP from a DSP Image Fast Load structure. This structure is a
2078 * linear, non-constant sized element array of structures, each of which
2079 * contain the count of the data to be loaded, the data itself, and the
2080 * corresponding starting chip address of the starting data location.
2081 *
2082 * @codec: the HDA codec
2083 * @fls: pointer to a fast load image
2084 * @ovly: TRUE if overlay format is required
2085 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2086 * no relocation
2087 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2088 * @router_chans: number of audio router channels to be allocated (0 means use
2089 * internal defaults; max is 32)
2090 *
2091 * Returns zero or a negative error code.
2092 */
01ef7dbf
IM		 2093static int dspload_image(struct hda_codec *codec,
2094 const struct dsp_image_seg *fls,
2095 bool ovly,
2096 unsigned int reloc,
2097 bool autostart,
2098 int router_chans)
2099{
2100 int status = 0;
e97249dd
IM		 2101 unsigned int sample_rate;
2102 unsigned short channels;
01ef7dbf
IM		 2103
2104 snd_printdd(KERN_INFO "---- dspload_image begin ------");
2105 if (router_chans == 0) {
2106 if (!ovly)
2107 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2108 else
2109 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2110 }
95c6e9cb 2111
e97249dd
IM		 2112 sample_rate = 48000;
2113 channels = (unsigned short)router_chans;
01ef7dbf 2114
e97249dd
IM		 2115 while (channels > 16) {
2116 sample_rate *= 2;
2117 channels /= 2;
01ef7dbf
IM		 2118 }
2119
01ef7dbf
IM		 2120 do {
2121 snd_printdd(KERN_INFO "Ready to program DMA");
2122 if (!ovly)
2123 status = dsp_reset(codec);
2124
2125 if (status < 0)
2126 break;
2127
2128 snd_printdd(KERN_INFO "dsp_reset() complete");
e97249dd
IM		 2129 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2130 ovly);
01ef7dbf
IM		 2131
2132 if (status < 0)
2133 break;
2134
2135 snd_printdd(KERN_INFO "dspxfr_image() complete");
2136 if (autostart && !ovly) {
2137 dspload_post_setup(codec);
2138 status = dsp_set_run_state(codec);
2139 }
2140
2141 snd_printdd(KERN_INFO "LOAD FINISHED");
2142 } while (0);
2143
2144 return status;
2145}
2146
c3b4eea2
IM		 2147static const struct firmware *fw_efx;
2148
2149static int request_firmware_cached(const struct firmware **firmware_p,
2150 const char *name, struct device *device)
2151{
2152 if (*firmware_p)
2153 return 0; /* already loaded */
2154 return request_firmware(firmware_p, name, device);
2155}
2156
2157static void release_cached_firmware(void)
2158{
2159 if (fw_efx) {
2160 release_firmware(fw_efx);
2161 fw_efx = NULL;
2162 }
2163}
2164
01ef7dbf
IM		 2165static bool dspload_is_loaded(struct hda_codec *codec)
2166{
2167 unsigned int data = 0;
2168 int status = 0;
2169
2170 status = chipio_read(codec, 0x40004, &data);
2171 if ((status < 0) || (data != 1))
2172 return false;
2173
2174 return true;
2175}
2176
2177static bool dspload_wait_loaded(struct hda_codec *codec)
2178{
2179 int retry = 100;
2180
2181 do {
2182 msleep(20);
2183 if (dspload_is_loaded(codec)) {
2184 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2185 return true;
2186 }
2187 } while (--retry);
2188
2189 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2190 return false;
95c6e9cb
IM		 2191}
2192
2193/*
27ebeb0b 2194 * PCM callbacks
95c6e9cb 2195 */
27ebeb0b
TI		 2196static int ca0132_playback_pcm_open(struct hda_pcm_stream *hinfo,
2197 struct hda_codec *codec,
2198 struct snd_pcm_substream *substream)
95c6e9cb 2199{
27ebeb0b
TI		 2200 struct ca0132_spec *spec = codec->spec;
2201 return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream,
2202 hinfo);
95c6e9cb
IM		 2203}
2204
95c6e9cb
IM		 2205static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2206 struct hda_codec *codec,
2207 unsigned int stream_tag,
2208 unsigned int format,
2209 struct snd_pcm_substream *substream)
2210{
2211 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2212 return snd_hda_multi_out_analog_prepare(codec, &spec->multiout,
2213 stream_tag, format, substream);
95c6e9cb
IM		 2214}
2215
2216static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2217 struct hda_codec *codec,
2218 struct snd_pcm_substream *substream)
2219{
2220 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2221 return snd_hda_multi_out_analog_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2222}
2223
2224/*
2225 * Digital out
2226 */
27ebeb0b
TI		 2227static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2228 struct hda_codec *codec,
2229 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2230{
2231 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2232 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2233}
2234
27ebeb0b 2235static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2236 struct hda_codec *codec,
2237 unsigned int stream_tag,
2238 unsigned int format,
2239 struct snd_pcm_substream *substream)
2240{
2241 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2242 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2243 stream_tag, format, substream);
95c6e9cb
IM		 2244}
2245
27ebeb0b 2246static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2247 struct hda_codec *codec,
95c6e9cb
IM		 2248 struct snd_pcm_substream *substream)
2249{
2250 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2251 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2252}
2253
27ebeb0b
TI		 2254static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2255 struct hda_codec *codec,
2256 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2257{
2258 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2259 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2260}
2261
2262/*
2263 */
2264static struct hda_pcm_stream ca0132_pcm_analog_playback = {
2265 .substreams = 1,
2266 .channels_min = 2,
2267 .channels_max = 2,
2268 .ops = {
27ebeb0b 2269 .open = ca0132_playback_pcm_open,
95c6e9cb
IM		 2270 .prepare = ca0132_playback_pcm_prepare,
2271 .cleanup = ca0132_playback_pcm_cleanup
2272 },
2273};
2274
2275static struct hda_pcm_stream ca0132_pcm_analog_capture = {
2276 .substreams = 1,
2277 .channels_min = 2,
2278 .channels_max = 2,
95c6e9cb
IM		 2279};
2280
2281static struct hda_pcm_stream ca0132_pcm_digital_playback = {
2282 .substreams = 1,
2283 .channels_min = 2,
2284 .channels_max = 2,
2285 .ops = {
27ebeb0b
TI		 2286 .open = ca0132_dig_playback_pcm_open,
2287 .close = ca0132_dig_playback_pcm_close,
95c6e9cb
IM		 2288 .prepare = ca0132_dig_playback_pcm_prepare,
2289 .cleanup = ca0132_dig_playback_pcm_cleanup
2290 },
2291};
2292
2293static struct hda_pcm_stream ca0132_pcm_digital_capture = {
2294 .substreams = 1,
2295 .channels_min = 2,
2296 .channels_max = 2,
95c6e9cb
IM		 2297};
2298
2299static int ca0132_build_pcms(struct hda_codec *codec)
2300{
2301 struct ca0132_spec *spec = codec->spec;
2302 struct hda_pcm *info = spec->pcm_rec;
2303
2304 codec->pcm_info = info;
2305 codec->num_pcms = 0;
2306
2307 info->name = "CA0132 Analog";
2308 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
2309 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
2310 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
2311 spec->multiout.max_channels;
2312 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
2313 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_inputs;
2314 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
2315 codec->num_pcms++;
2316
2317 if (!spec->dig_out && !spec->dig_in)
2318 return 0;
2319
2320 info++;
2321 info->name = "CA0132 Digital";
2322 info->pcm_type = HDA_PCM_TYPE_SPDIF;
2323 if (spec->dig_out) {
2324 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
2325 ca0132_pcm_digital_playback;
2326 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
2327 }
2328 if (spec->dig_in) {
2329 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
2330 ca0132_pcm_digital_capture;
2331 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
2332 }
2333 codec->num_pcms++;
2334
2335 return 0;
2336}
2337
2338#define REG_CODEC_MUTE 0x18b014
2339#define REG_CODEC_HP_VOL_L 0x18b070
2340#define REG_CODEC_HP_VOL_R 0x18b074
2341
2342static int ca0132_hp_switch_get(struct snd_kcontrol *kcontrol,
2343 struct snd_ctl_elem_value *ucontrol)
2344{
2345 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2346 struct ca0132_spec *spec = codec->spec;
2347 long *valp = ucontrol->value.integer.value;
2348
2349 *valp = spec->curr_hp_switch;
2350 return 0;
2351}
2352
2353static int ca0132_hp_switch_put(struct snd_kcontrol *kcontrol,
2354 struct snd_ctl_elem_value *ucontrol)
2355{
2356 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2357 struct ca0132_spec *spec = codec->spec;
2358 long *valp = ucontrol->value.integer.value;
2359 unsigned int data;
2360 int err;
2361
2362 /* any change? */
2363 if (spec->curr_hp_switch == *valp)
2364 return 0;
2365
2366 snd_hda_power_up(codec);
2367
2368 err = chipio_read(codec, REG_CODEC_MUTE, &data);
2369 if (err < 0)
b97f6bfd 2370 goto exit;
95c6e9cb
IM		 2371
2372 /* *valp 0 is mute, 1 is unmute */
2373 data = (data & 0x7f) | (*valp ? 0 : 0x80);
b97f6bfd 2374 err = chipio_write(codec, REG_CODEC_MUTE, data);
95c6e9cb 2375 if (err < 0)
b97f6bfd 2376 goto exit;
95c6e9cb
IM		 2377
2378 spec->curr_hp_switch = *valp;
2379
b97f6bfd 2380 exit:
95c6e9cb 2381 snd_hda_power_down(codec);
b97f6bfd 2382 return err < 0 ? err : 1;
95c6e9cb
IM		 2383}
2384
2385static int ca0132_speaker_switch_get(struct snd_kcontrol *kcontrol,
2386 struct snd_ctl_elem_value *ucontrol)
2387{
2388 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2389 struct ca0132_spec *spec = codec->spec;
2390 long *valp = ucontrol->value.integer.value;
2391
2392 *valp = spec->curr_speaker_switch;
2393 return 0;
2394}
2395
2396static int ca0132_speaker_switch_put(struct snd_kcontrol *kcontrol,
2397 struct snd_ctl_elem_value *ucontrol)
2398{
2399 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2400 struct ca0132_spec *spec = codec->spec;
2401 long *valp = ucontrol->value.integer.value;
2402 unsigned int data;
2403 int err;
2404
2405 /* any change? */
2406 if (spec->curr_speaker_switch == *valp)
2407 return 0;
2408
2409 snd_hda_power_up(codec);
2410
2411 err = chipio_read(codec, REG_CODEC_MUTE, &data);
2412 if (err < 0)
b97f6bfd 2413 goto exit;
95c6e9cb
IM		 2414
2415 /* *valp 0 is mute, 1 is unmute */
2416 data = (data & 0xef) | (*valp ? 0 : 0x10);
b97f6bfd 2417 err = chipio_write(codec, REG_CODEC_MUTE, data);
95c6e9cb 2418 if (err < 0)
b97f6bfd 2419 goto exit;
95c6e9cb
IM		 2420
2421 spec->curr_speaker_switch = *valp;
2422
b97f6bfd 2423 exit:
95c6e9cb 2424 snd_hda_power_down(codec);
b97f6bfd 2425 return err < 0 ? err : 1;
95c6e9cb
IM		 2426}
2427
2428static int ca0132_hp_volume_get(struct snd_kcontrol *kcontrol,
2429 struct snd_ctl_elem_value *ucontrol)
2430{
2431 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2432 struct ca0132_spec *spec = codec->spec;
2433 long *valp = ucontrol->value.integer.value;
2434
2435 *valp++ = spec->curr_hp_volume[0];
2436 *valp = spec->curr_hp_volume[1];
2437 return 0;
2438}
2439
2440static int ca0132_hp_volume_put(struct snd_kcontrol *kcontrol,
2441 struct snd_ctl_elem_value *ucontrol)
2442{
2443 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2444 struct ca0132_spec *spec = codec->spec;
2445 long *valp = ucontrol->value.integer.value;
2446 long left_vol, right_vol;
2447 unsigned int data;
2448 int val;
2449 int err;
2450
2451 left_vol = *valp++;
2452 right_vol = *valp;
2453
2454 /* any change? */
2455 if ((spec->curr_hp_volume[0] == left_vol) &&
2456 (spec->curr_hp_volume[1] == right_vol))
2457 return 0;
2458
2459 snd_hda_power_up(codec);
2460
2461 err = chipio_read(codec, REG_CODEC_HP_VOL_L, &data);
2462 if (err < 0)
b97f6bfd 2463 goto exit;
95c6e9cb
IM		 2464
2465 val = 31 - left_vol;
2466 data = (data & 0xe0) | val;
b97f6bfd 2467 err = chipio_write(codec, REG_CODEC_HP_VOL_L, data);
95c6e9cb 2468 if (err < 0)
b97f6bfd 2469 goto exit;
95c6e9cb
IM		 2470
2471 val = 31 - right_vol;
2472 data = (data & 0xe0) | val;
b97f6bfd 2473 err = chipio_write(codec, REG_CODEC_HP_VOL_R, data);
95c6e9cb 2474 if (err < 0)
b97f6bfd 2475 goto exit;
95c6e9cb
IM		 2476
2477 spec->curr_hp_volume[0] = left_vol;
2478 spec->curr_hp_volume[1] = right_vol;
2479
b97f6bfd 2480 exit:
95c6e9cb 2481 snd_hda_power_down(codec);
b97f6bfd 2482 return err < 0 ? err : 1;
95c6e9cb
IM		 2483}
2484
2485static int add_hp_switch(struct hda_codec *codec, hda_nid_t nid)
2486{
2487 struct snd_kcontrol_new knew =
2488 HDA_CODEC_MUTE_MONO("Headphone Playback Switch",
2489 nid, 1, 0, HDA_OUTPUT);
2490 knew.get = ca0132_hp_switch_get;
2491 knew.put = ca0132_hp_switch_put;
2492 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
2493}
2494
2495static int add_hp_volume(struct hda_codec *codec, hda_nid_t nid)
2496{
2497 struct snd_kcontrol_new knew =
2498 HDA_CODEC_VOLUME_MONO("Headphone Playback Volume",
2499 nid, 3, 0, HDA_OUTPUT);
2500 knew.get = ca0132_hp_volume_get;
2501 knew.put = ca0132_hp_volume_put;
2502 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
2503}
2504
2505static int add_speaker_switch(struct hda_codec *codec, hda_nid_t nid)
2506{
2507 struct snd_kcontrol_new knew =
2508 HDA_CODEC_MUTE_MONO("Speaker Playback Switch",
2509 nid, 1, 0, HDA_OUTPUT);
2510 knew.get = ca0132_speaker_switch_get;
2511 knew.put = ca0132_speaker_switch_put;
2512 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
2513}
2514
2515static void ca0132_fix_hp_caps(struct hda_codec *codec)
2516{
2517 struct ca0132_spec *spec = codec->spec;
2518 struct auto_pin_cfg *cfg = &spec->autocfg;
2519 unsigned int caps;
2520
2521 /* set mute-capable, 1db step, 32 steps, ofs 6 */
2522 caps = 0x80031f06;
2523 snd_hda_override_amp_caps(codec, cfg->hp_pins[0], HDA_OUTPUT, caps);
2524}
2525
2526static int ca0132_build_controls(struct hda_codec *codec)
2527{
2528 struct ca0132_spec *spec = codec->spec;
2529 struct auto_pin_cfg *cfg = &spec->autocfg;
2530 int i, err;
2531
2532 if (spec->multiout.num_dacs) {
2533 err = add_speaker_switch(codec, spec->out_pins[0]);
2534 if (err < 0)
2535 return err;
2536 }
2537
2538 if (cfg->hp_outs) {
2539 ca0132_fix_hp_caps(codec);
2540 err = add_hp_switch(codec, cfg->hp_pins[0]);
2541 if (err < 0)
2542 return err;
2543 err = add_hp_volume(codec, cfg->hp_pins[0]);
2544 if (err < 0)
2545 return err;
2546 }
2547
2548 for (i = 0; i < spec->num_inputs; i++) {
2549 const char *label = spec->input_labels[i];
2550
2551 err = add_in_switch(codec, spec->adcs[i], label);
2552 if (err < 0)
2553 return err;
2554 err = add_in_volume(codec, spec->adcs[i], label);
2555 if (err < 0)
2556 return err;
2557 if (cfg->inputs[i].type == AUTO_PIN_MIC) {
2558 /* add Mic-Boost */
2559 err = add_in_mono_volume(codec, spec->input_pins[i],
2560 "Mic Boost", 1);
2561 if (err < 0)
2562 return err;
2563 }
2564 }
2565
2566 if (spec->dig_out) {
efb9f469
TI		 2567 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
2568 spec->dig_out);
95c6e9cb
IM		 2569 if (err < 0)
2570 return err;
8e13fc1c 2571 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
95c6e9cb
IM		 2572 if (err < 0)
2573 return err;
8e13fc1c 2574 /* spec->multiout.share_spdif = 1; */
95c6e9cb
IM		 2575 }
2576
2577 if (spec->dig_in) {
2578 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
2579 if (err < 0)
2580 return err;
95c6e9cb
IM		 2581 }
2582 return 0;
2583}
2584
2585
2586static void ca0132_set_ct_ext(struct hda_codec *codec, int enable)
2587{
2588 /* Set Creative extension */
2589 snd_printdd("SET CREATIVE EXTENSION\n");
2590 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2591 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE,
2592 enable);
2593 msleep(20);
2594}
2595
2596
2597static void ca0132_config(struct hda_codec *codec)
2598{
2599 struct ca0132_spec *spec = codec->spec;
2600 struct auto_pin_cfg *cfg = &spec->autocfg;
2601
27ebeb0b
TI		 2602 codec->pcm_format_first = 1;
2603 codec->no_sticky_stream = 1;
2604
95c6e9cb
IM		 2605 /* line-outs */
2606 cfg->line_outs = 1;
2607 cfg->line_out_pins[0] = 0x0b; /* front */
2608 cfg->line_out_type = AUTO_PIN_LINE_OUT;
2609
2610 spec->dacs[0] = 0x02;
2611 spec->out_pins[0] = 0x0b;
2612 spec->multiout.dac_nids = spec->dacs;
2613 spec->multiout.num_dacs = 1;
2614 spec->multiout.max_channels = 2;
2615
2616 /* headphone */
2617 cfg->hp_outs = 1;
2618 cfg->hp_pins[0] = 0x0f;
2619
2620 spec->hp_dac = 0;
2621 spec->multiout.hp_nid = 0;
2622
2623 /* inputs */
2624 cfg->num_inputs = 2; /* Mic-in and line-in */
2625 cfg->inputs[0].pin = 0x12;
2626 cfg->inputs[0].type = AUTO_PIN_MIC;
2627 cfg->inputs[1].pin = 0x11;
2628 cfg->inputs[1].type = AUTO_PIN_LINE_IN;
2629
2630 /* Mic-in */
2631 spec->input_pins[0] = 0x12;
55cf87fe 2632 spec->input_labels[0] = "Mic";
95c6e9cb
IM		 2633 spec->adcs[0] = 0x07;
2634
2635 /* Line-In */
2636 spec->input_pins[1] = 0x11;
55cf87fe 2637 spec->input_labels[1] = "Line";
95c6e9cb
IM		 2638 spec->adcs[1] = 0x08;
2639 spec->num_inputs = 2;
8e13fc1c
TI		 2640
2641 /* SPDIF I/O */
2642 spec->dig_out = 0x05;
2643 spec->multiout.dig_out_nid = spec->dig_out;
2644 cfg->dig_out_pins[0] = 0x0c;
2645 cfg->dig_outs = 1;
2646 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
2647 spec->dig_in = 0x09;
2648 cfg->dig_in_pin = 0x0e;
2649 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
95c6e9cb
IM		 2650}
2651
2652static void ca0132_init_chip(struct hda_codec *codec)
2653{
2654 struct ca0132_spec *spec = codec->spec;
2655
2656 mutex_init(&spec->chipio_mutex);
2657}
2658
2659static void ca0132_exit_chip(struct hda_codec *codec)
2660{
2661 /* put any chip cleanup stuffs here. */
2662}
2663
01ef7dbf
IM		 2664static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
2665{
2666 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
2667 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
2668 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
2669 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
2670 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
2671 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
2672
2673 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
2674 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
2675 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
2676}
2677
2678static bool ca0132_download_dsp_images(struct hda_codec *codec)
2679{
2680 bool dsp_loaded = false;
2681 const struct dsp_image_seg *dsp_os_image;
01ef7dbf 2682
c3b4eea2
IM		 2683 if (request_firmware_cached(&fw_efx, EFX_FILE,
2684 codec->bus->card->dev) != 0)
01ef7dbf
IM		 2685 return false;
2686
c3b4eea2 2687 dsp_os_image = (struct dsp_image_seg *)(fw_efx->data);
01ef7dbf
IM		 2688 dspload_image(codec, dsp_os_image, 0, 0, true, 0);
2689 dsp_loaded = dspload_wait_loaded(codec);
2690
01ef7dbf
IM		 2691 return dsp_loaded;
2692}
2693
2694static void ca0132_download_dsp(struct hda_codec *codec)
2695{
2696 struct ca0132_spec *spec = codec->spec;
2697
2698 spec->dsp_state = DSP_DOWNLOAD_INIT;
2699
2700 if (spec->dsp_state == DSP_DOWNLOAD_INIT) {
2701 chipio_enable_clocks(codec);
2702 spec->dsp_state = DSP_DOWNLOADING;
2703 if (!ca0132_download_dsp_images(codec))
2704 spec->dsp_state = DSP_DOWNLOAD_FAILED;
2705 else
2706 spec->dsp_state = DSP_DOWNLOADED;
2707 }
2708
2709 if (spec->dsp_state == DSP_DOWNLOADED)
2710 ca0132_set_dsp_msr(codec, true);
2711}
2712
95c6e9cb
IM		 2713static int ca0132_init(struct hda_codec *codec)
2714{
2715 struct ca0132_spec *spec = codec->spec;
2716 struct auto_pin_cfg *cfg = &spec->autocfg;
2717 int i;
2718
01ef7dbf
IM		 2719#ifdef CONFIG_SND_HDA_DSP_LOADER
2720 ca0132_download_dsp(codec);
2721#endif
2722
95c6e9cb
IM		 2723 for (i = 0; i < spec->multiout.num_dacs; i++) {
2724 init_output(codec, spec->out_pins[i],
2725 spec->multiout.dac_nids[i]);
2726 }
2727 init_output(codec, cfg->hp_pins[0], spec->hp_dac);
2728 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
2729
2730 for (i = 0; i < spec->num_inputs; i++)
2731 init_input(codec, spec->input_pins[i], spec->adcs[i]);
2732
2733 init_input(codec, cfg->dig_in_pin, spec->dig_in);
2734
2735 ca0132_set_ct_ext(codec, 1);
2736
2737 return 0;
2738}
2739
2740
2741static void ca0132_free(struct hda_codec *codec)
2742{
2743 ca0132_set_ct_ext(codec, 0);
2744 ca0132_exit_chip(codec);
2745 kfree(codec->spec);
2746}
2747
2748static struct hda_codec_ops ca0132_patch_ops = {
2749 .build_controls = ca0132_build_controls,
2750 .build_pcms = ca0132_build_pcms,
2751 .init = ca0132_init,
2752 .free = ca0132_free,
2753};
2754
2755
2756
2757static int patch_ca0132(struct hda_codec *codec)
2758{
2759 struct ca0132_spec *spec;
2760
2761 snd_printdd("patch_ca0132\n");
2762
2763 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2764 if (!spec)
2765 return -ENOMEM;
2766 codec->spec = spec;
2767
2768 ca0132_init_chip(codec);
2769
2770 ca0132_config(codec);
2771
2772 codec->patch_ops = ca0132_patch_ops;
2773
2774 return 0;
2775}
2776
2777/*
2778 * patch entries
2779 */
2780static struct hda_codec_preset snd_hda_preset_ca0132[] = {
2781 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
2782 {} /* terminator */
2783};
2784
2785MODULE_ALIAS("snd-hda-codec-id:11020011");
2786
2787MODULE_LICENSE("GPL");
2788MODULE_DESCRIPTION("Creative CA0132, CA0132 HD-audio codec");
2789
2790static struct hda_codec_preset_list ca0132_list = {
2791 .preset = snd_hda_preset_ca0132,
2792 .owner = THIS_MODULE,
2793};
2794
2795static int __init patch_ca0132_init(void)
2796{
2797 return snd_hda_add_codec_preset(&ca0132_list);
2798}
2799
2800static void __exit patch_ca0132_exit(void)
2801{
c3b4eea2 2802 release_cached_firmware();
95c6e9cb
IM		 2803 snd_hda_delete_codec_preset(&ca0132_list);
2804}
2805
2806module_init(patch_ca0132_init)
2807module_exit(patch_ca0132_exit)
Linux 6.x block layer and io_uring tree(s)