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ALSA: hda/ca0132: constify templates for control element set
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb
IM		 34#include <sound/core.h>
35#include "hda_codec.h"
36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
38ba69ff 52#define FLOAT_THREE 0x40400000
7cb9d94c 53#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 54#define FLOAT_MINUS_5 0xc0a00000
55
ef6b2ead
IM		 56#define UNSOL_TAG_DSP 0x16
57
4aa3bb0c
IM		 58#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
ef6b2ead
IM		 66#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 68
95c6e9cb
IM		 69#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
4aa3bb0c
IM		 72#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
01ef7dbf 83#define EFX_FILE "ctefx.bin"
8a19bcee
CM		 84#define SBZ_EFX_FILE "ctefx-sbz.bin"
85#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 86
24f3cede 87#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 88MODULE_FIRMWARE(EFX_FILE);
8a19bcee
CM		 89MODULE_FIRMWARE(SBZ_EFX_FILE);
90MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 91#endif
01ef7dbf 92
8a19bcee 93static const char *dirstr[2] = { "Playback", "Capture" };
ef6b2ead 94
7cb9d94c 95#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 96enum {
97 SPEAKER_OUT,
7cb9d94c
CM		 98 HEADPHONE_OUT,
99 SURROUND_OUT
ef6b2ead
IM		 100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
7cb9d94c
CM		 107/* Strings for Input Source Enum Control */
108static const char *in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
ef6b2ead
IM		 116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
7cb9d94c
CM		 149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
155 MIC_BOOST_ENUM
ef6b2ead
IM		 156#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
157};
158
159/* Effects values size*/
160#define EFFECT_VALS_MAX_COUNT 12
161
47cdf76e
CM		 162/*
163 * Default values for the effect slider controls, they are in order of their
164 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
165 * X-bass.
166 */
167static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
168/* Amount of effect level sliders for ca0132_alt controls. */
169#define EFFECT_LEVEL_SLIDERS 5
170
e8412ca4
DR		 171/* Latency introduced by DSP blocks in milliseconds. */
172#define DSP_CAPTURE_INIT_LATENCY 0
173#define DSP_CRYSTAL_VOICE_LATENCY 124
174#define DSP_PLAYBACK_INIT_LATENCY 13
175#define DSP_PLAY_ENHANCEMENT_LATENCY 30
176#define DSP_SPEAKER_OUT_LATENCY 7
177
ef6b2ead 178struct ct_effect {
975cc02a 179 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 180 hda_nid_t nid;
181 int mid; /*effect module ID*/
182 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
183 int direct; /* 0:output; 1:input*/
184 int params; /* number of default non-on/off params */
185 /*effect default values, 1st is on/off. */
186 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
187};
188
189#define EFX_DIR_OUT 0
190#define EFX_DIR_IN 1
191
192static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
193 { .name = "Surround",
194 .nid = SURROUND,
195 .mid = 0x96,
196 .reqs = {0, 1},
197 .direct = EFX_DIR_OUT,
198 .params = 1,
199 .def_vals = {0x3F800000, 0x3F2B851F}
200 },
201 { .name = "Crystalizer",
202 .nid = CRYSTALIZER,
203 .mid = 0x96,
204 .reqs = {7, 8},
205 .direct = EFX_DIR_OUT,
206 .params = 1,
207 .def_vals = {0x3F800000, 0x3F266666}
208 },
209 { .name = "Dialog Plus",
210 .nid = DIALOG_PLUS,
211 .mid = 0x96,
212 .reqs = {2, 3},
213 .direct = EFX_DIR_OUT,
214 .params = 1,
215 .def_vals = {0x00000000, 0x3F000000}
216 },
217 { .name = "Smart Volume",
218 .nid = SMART_VOLUME,
219 .mid = 0x96,
220 .reqs = {4, 5, 6},
221 .direct = EFX_DIR_OUT,
222 .params = 2,
223 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
224 },
225 { .name = "X-Bass",
226 .nid = X_BASS,
227 .mid = 0x96,
228 .reqs = {24, 23, 25},
229 .direct = EFX_DIR_OUT,
230 .params = 2,
231 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
232 },
233 { .name = "Equalizer",
234 .nid = EQUALIZER,
235 .mid = 0x96,
236 .reqs = {9, 10, 11, 12, 13, 14,
237 15, 16, 17, 18, 19, 20},
238 .direct = EFX_DIR_OUT,
239 .params = 11,
240 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
241 0x00000000, 0x00000000, 0x00000000, 0x00000000,
242 0x00000000, 0x00000000, 0x00000000, 0x00000000}
243 },
244 { .name = "Echo Cancellation",
245 .nid = ECHO_CANCELLATION,
246 .mid = 0x95,
247 .reqs = {0, 1, 2, 3},
248 .direct = EFX_DIR_IN,
249 .params = 3,
250 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
251 },
252 { .name = "Voice Focus",
253 .nid = VOICE_FOCUS,
254 .mid = 0x95,
255 .reqs = {6, 7, 8, 9},
256 .direct = EFX_DIR_IN,
257 .params = 3,
258 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
259 },
260 { .name = "Mic SVM",
261 .nid = MIC_SVM,
262 .mid = 0x95,
263 .reqs = {44, 45},
264 .direct = EFX_DIR_IN,
265 .params = 1,
266 .def_vals = {0x00000000, 0x3F3D70A4}
267 },
268 { .name = "Noise Reduction",
269 .nid = NOISE_REDUCTION,
270 .mid = 0x95,
271 .reqs = {4, 5},
272 .direct = EFX_DIR_IN,
273 .params = 1,
274 .def_vals = {0x3F800000, 0x3F000000}
275 },
276 { .name = "VoiceFX",
277 .nid = VOICEFX,
278 .mid = 0x95,
279 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
280 .direct = EFX_DIR_IN,
281 .params = 8,
282 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
283 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
284 0x00000000}
285 }
286};
287
288/* Tuning controls */
289#ifdef ENABLE_TUNING_CONTROLS
290
291enum {
292#define TUNING_CTL_START_NID 0xC0
293 WEDGE_ANGLE = TUNING_CTL_START_NID,
294 SVM_LEVEL,
295 EQUALIZER_BAND_0,
296 EQUALIZER_BAND_1,
297 EQUALIZER_BAND_2,
298 EQUALIZER_BAND_3,
299 EQUALIZER_BAND_4,
300 EQUALIZER_BAND_5,
301 EQUALIZER_BAND_6,
302 EQUALIZER_BAND_7,
303 EQUALIZER_BAND_8,
304 EQUALIZER_BAND_9,
305 TUNING_CTL_END_NID
306#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
307};
308
309struct ct_tuning_ctl {
975cc02a 310 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 311 hda_nid_t parent_nid;
312 hda_nid_t nid;
313 int mid; /*effect module ID*/
314 int req; /*effect module request*/
315 int direct; /* 0:output; 1:input*/
316 unsigned int def_val;/*effect default values*/
317};
318
319static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
320 { .name = "Wedge Angle",
321 .parent_nid = VOICE_FOCUS,
322 .nid = WEDGE_ANGLE,
323 .mid = 0x95,
324 .req = 8,
325 .direct = EFX_DIR_IN,
326 .def_val = 0x41F00000
327 },
328 { .name = "SVM Level",
329 .parent_nid = MIC_SVM,
330 .nid = SVM_LEVEL,
331 .mid = 0x95,
332 .req = 45,
333 .direct = EFX_DIR_IN,
334 .def_val = 0x3F3D70A4
335 },
336 { .name = "EQ Band0",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_0,
339 .mid = 0x96,
340 .req = 11,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
343 },
344 { .name = "EQ Band1",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_1,
347 .mid = 0x96,
348 .req = 12,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
351 },
352 { .name = "EQ Band2",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_2,
355 .mid = 0x96,
356 .req = 13,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
359 },
360 { .name = "EQ Band3",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_3,
363 .mid = 0x96,
364 .req = 14,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
367 },
368 { .name = "EQ Band4",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_4,
371 .mid = 0x96,
372 .req = 15,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
375 },
376 { .name = "EQ Band5",
377 .parent_nid = EQUALIZER,
378 .nid = EQUALIZER_BAND_5,
379 .mid = 0x96,
380 .req = 16,
381 .direct = EFX_DIR_OUT,
382 .def_val = 0x00000000
383 },
384 { .name = "EQ Band6",
385 .parent_nid = EQUALIZER,
386 .nid = EQUALIZER_BAND_6,
387 .mid = 0x96,
388 .req = 17,
389 .direct = EFX_DIR_OUT,
390 .def_val = 0x00000000
391 },
392 { .name = "EQ Band7",
393 .parent_nid = EQUALIZER,
394 .nid = EQUALIZER_BAND_7,
395 .mid = 0x96,
396 .req = 18,
397 .direct = EFX_DIR_OUT,
398 .def_val = 0x00000000
399 },
400 { .name = "EQ Band8",
401 .parent_nid = EQUALIZER,
402 .nid = EQUALIZER_BAND_8,
403 .mid = 0x96,
404 .req = 19,
405 .direct = EFX_DIR_OUT,
406 .def_val = 0x00000000
407 },
408 { .name = "EQ Band9",
409 .parent_nid = EQUALIZER,
410 .nid = EQUALIZER_BAND_9,
411 .mid = 0x96,
412 .req = 20,
413 .direct = EFX_DIR_OUT,
414 .def_val = 0x00000000
415 }
416};
417#endif
418
419/* Voice FX Presets */
420#define VOICEFX_MAX_PARAM_COUNT 9
421
422struct ct_voicefx {
423 char *name;
424 hda_nid_t nid;
425 int mid;
426 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
427};
428
429struct ct_voicefx_preset {
430 char *name; /*preset name*/
431 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
432};
433
ccd7bd3d 434static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 435 .name = "VoiceFX Capture Switch",
436 .nid = VOICEFX,
437 .mid = 0x95,
438 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
439};
440
ccd7bd3d 441static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 442 { .name = "Neutral",
443 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
444 0x44FA0000, 0x3F800000, 0x3F800000,
445 0x3F800000, 0x00000000, 0x00000000 }
446 },
447 { .name = "Female2Male",
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3F19999A, 0x3F866666,
450 0x3F800000, 0x00000000, 0x00000000 }
451 },
452 { .name = "Male2Female",
453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
454 0x450AC000, 0x4017AE14, 0x3F6B851F,
455 0x3F800000, 0x00000000, 0x00000000 }
456 },
457 { .name = "ScrappyKid",
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x40400000, 0x3F28F5C3,
460 0x3F800000, 0x00000000, 0x00000000 }
461 },
462 { .name = "Elderly",
463 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
464 0x44E10000, 0x3FB33333, 0x3FB9999A,
465 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 },
467 { .name = "Orc",
468 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
469 0x45098000, 0x3F266666, 0x3FC00000,
470 0x3F800000, 0x00000000, 0x00000000 }
471 },
472 { .name = "Elf",
473 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
474 0x45193000, 0x3F8E147B, 0x3F75C28F,
475 0x3F800000, 0x00000000, 0x00000000 }
476 },
477 { .name = "Dwarf",
478 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
479 0x45007000, 0x3F451EB8, 0x3F7851EC,
480 0x3F800000, 0x00000000, 0x00000000 }
481 },
482 { .name = "AlienBrute",
483 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
484 0x451F6000, 0x3F266666, 0x3FA7D945,
485 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 },
487 { .name = "Robot",
488 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
489 0x44FA0000, 0x3FB2718B, 0x3F800000,
490 0xBC07010E, 0x00000000, 0x00000000 }
491 },
492 { .name = "Marine",
493 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
494 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
495 0x3F0A3D71, 0x00000000, 0x00000000 }
496 },
497 { .name = "Emo",
498 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
499 0x44FA0000, 0x3F800000, 0x3F800000,
500 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 },
502 { .name = "DeepVoice",
503 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
504 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
505 0x3F800000, 0x00000000, 0x00000000 }
506 },
507 { .name = "Munchkin",
508 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
509 0x44FA0000, 0x3F800000, 0x3F1A043C,
510 0x3F800000, 0x00000000, 0x00000000 }
511 }
512};
513
47cdf76e
CM		 514/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
515
516#define EQ_PRESET_MAX_PARAM_COUNT 11
517
518struct ct_eq {
519 char *name;
520 hda_nid_t nid;
521 int mid;
522 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
523};
524
525struct ct_eq_preset {
526 char *name; /*preset name*/
527 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
528};
529
530static struct ct_eq ca0132_alt_eq_enum = {
531 .name = "FX: Equalizer Preset Switch",
532 .nid = EQ_PRESET_ENUM,
533 .mid = 0x96,
534 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
535};
536
537
538static struct ct_eq_preset ca0132_alt_eq_presets[] = {
539 { .name = "Flat",
540 .vals = { 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000, 0x00000000,
542 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000 }
544 },
545 { .name = "Acoustic",
546 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
547 0x40000000, 0x00000000, 0x00000000,
548 0x00000000, 0x00000000, 0x40000000,
549 0x40000000, 0x40000000 }
550 },
551 { .name = "Classical",
552 .vals = { 0x00000000, 0x00000000, 0x40C00000,
553 0x40C00000, 0x40466666, 0x00000000,
554 0x00000000, 0x00000000, 0x00000000,
555 0x40466666, 0x40466666 }
556 },
557 { .name = "Country",
558 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
559 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
560 0x00000000, 0x00000000, 0x40000000,
561 0x40466666, 0x40800000 }
562 },
563 { .name = "Dance",
564 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
565 0x40466666, 0x40866666, 0xBF99999A,
566 0xBF99999A, 0x00000000, 0x00000000,
567 0x40800000, 0x40800000 }
568 },
569 { .name = "Jazz",
570 .vals = { 0x00000000, 0x00000000, 0x00000000,
571 0x3F8CCCCD, 0x40800000, 0x40800000,
572 0x40800000, 0x00000000, 0x3F8CCCCD,
573 0x40466666, 0x40466666 }
574 },
575 { .name = "New Age",
576 .vals = { 0x00000000, 0x00000000, 0x40000000,
577 0x40000000, 0x00000000, 0x00000000,
578 0x00000000, 0x3F8CCCCD, 0x40000000,
579 0x40000000, 0x40000000 }
580 },
581 { .name = "Pop",
582 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
583 0x40000000, 0x40000000, 0x00000000,
584 0xBF99999A, 0xBF99999A, 0x00000000,
585 0x40466666, 0x40C00000 }
586 },
587 { .name = "Rock",
588 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
589 0x3F8CCCCD, 0x40000000, 0xBF99999A,
590 0xBF99999A, 0x00000000, 0x00000000,
591 0x40800000, 0x40800000 }
592 },
593 { .name = "Vocal",
594 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
595 0xBF99999A, 0x00000000, 0x40466666,
596 0x40800000, 0x40466666, 0x00000000,
597 0x00000000, 0x3F8CCCCD }
598 }
599};
600
7cb9d94c
CM		 601/* DSP command sequences for ca0132_alt_select_out */
602#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
603struct ca0132_alt_out_set {
604 char *name; /*preset name*/
605 unsigned char commands;
606 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
607 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
608 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
609};
610
611static const struct ca0132_alt_out_set alt_out_presets[] = {
612 { .name = "Line Out",
613 .commands = 7,
614 .mids = { 0x96, 0x96, 0x96, 0x8F,
615 0x96, 0x96, 0x96 },
616 .reqs = { 0x19, 0x17, 0x18, 0x01,
617 0x1F, 0x15, 0x3A },
618 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
619 0x00000000, 0x00000000, 0x00000000,
620 0x00000000 }
621 },
622 { .name = "Headphone",
623 .commands = 7,
624 .mids = { 0x96, 0x96, 0x96, 0x8F,
625 0x96, 0x96, 0x96 },
626 .reqs = { 0x19, 0x17, 0x18, 0x01,
627 0x1F, 0x15, 0x3A },
628 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
629 0x00000000, 0x00000000, 0x00000000,
630 0x00000000 }
631 },
632 { .name = "Surround",
633 .commands = 8,
634 .mids = { 0x96, 0x8F, 0x96, 0x96,
635 0x96, 0x96, 0x96, 0x96 },
636 .reqs = { 0x18, 0x01, 0x1F, 0x15,
637 0x3A, 0x1A, 0x1B, 0x1C },
638 .vals = { 0x00000000, 0x00000000, 0x00000000,
639 0x00000000, 0x00000000, 0x00000000,
640 0x00000000, 0x00000000 }
641 }
642};
643
017310fb
CM		 644/*
645 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
646 * and I don't know what the third req is, but it's always zero. I assume it's
647 * some sort of update or set command to tell the DSP there's new volume info.
648 */
649#define DSP_VOL_OUT 0
650#define DSP_VOL_IN 1
651
652struct ct_dsp_volume_ctl {
653 hda_nid_t vnid;
654 int mid; /* module ID*/
655 unsigned int reqs[3]; /* scp req ID */
656};
657
658static struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
659 { .vnid = VNID_SPK,
660 .mid = 0x32,
661 .reqs = {3, 4, 2}
662 },
663 { .vnid = VNID_MIC,
664 .mid = 0x37,
665 .reqs = {2, 3, 1}
666 }
667};
668
95c6e9cb
IM		 669enum hda_cmd_vendor_io {
670 /* for DspIO node */
671 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
672 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
673
674 VENDOR_DSPIO_STATUS = 0xF01,
675 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
676 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
677 VENDOR_DSPIO_DSP_INIT = 0x703,
678 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
679 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
680
681 /* for ChipIO node */
682 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
683 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
684 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
685 VENDOR_CHIPIO_DATA_LOW = 0x300,
686 VENDOR_CHIPIO_DATA_HIGH = 0x400,
687
688 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
689 VENDOR_CHIPIO_STATUS = 0xF01,
690 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
691 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
692
4aa3bb0c
IM		 693 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
694 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
695
95c6e9cb 696 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 697 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 698
699 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
700 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
701 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
702 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
703 VENDOR_CHIPIO_FLAG_SET = 0x70F,
704 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 705 VENDOR_CHIPIO_PARAM_SET = 0x710,
706 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 707
708 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
709 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
710 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
711 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
712
4aa3bb0c
IM		 713 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
714 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
715 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
716 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
717
718 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
719 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
720 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
721 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
722 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
723 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
724
725 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 726};
727
728/*
729 * Control flag IDs
730 */
731enum control_flag_id {
732 /* Connection manager stream setup is bypassed/enabled */
733 CONTROL_FLAG_C_MGR = 0,
734 /* DSP DMA is bypassed/enabled */
735 CONTROL_FLAG_DMA = 1,
736 /* 8051 'idle' mode is disabled/enabled */
737 CONTROL_FLAG_IDLE_ENABLE = 2,
738 /* Tracker for the SPDIF-in path is bypassed/enabled */
739 CONTROL_FLAG_TRACKER = 3,
740 /* DigitalOut to Spdif2Out connection is disabled/enabled */
741 CONTROL_FLAG_SPDIF2OUT = 4,
742 /* Digital Microphone is disabled/enabled */
743 CONTROL_FLAG_DMIC = 5,
744 /* ADC_B rate is 48 kHz/96 kHz */
745 CONTROL_FLAG_ADC_B_96KHZ = 6,
746 /* ADC_C rate is 48 kHz/96 kHz */
747 CONTROL_FLAG_ADC_C_96KHZ = 7,
748 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
749 CONTROL_FLAG_DAC_96KHZ = 8,
750 /* DSP rate is 48 kHz/96 kHz */
751 CONTROL_FLAG_DSP_96KHZ = 9,
752 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
753 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
754 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
755 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
756 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
757 CONTROL_FLAG_DECODE_LOOP = 12,
758 /* De-emphasis filter on DAC-1 disabled/enabled */
759 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
760 /* De-emphasis filter on DAC-2 disabled/enabled */
761 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
762 /* De-emphasis filter on DAC-3 disabled/enabled */
763 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
764 /* High-pass filter on ADC_B disabled/enabled */
765 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
766 /* High-pass filter on ADC_C disabled/enabled */
767 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
768 /* Common mode on Port_A disabled/enabled */
769 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
770 /* Common mode on Port_D disabled/enabled */
771 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
772 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
773 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
774 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 775 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 776 /* ASI rate is 48kHz/96kHz */
777 CONTROL_FLAG_ASI_96KHZ = 22,
778 /* DAC power settings able to control attached ports no/yes */
779 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
780 /* Clock Stop OK reporting is disabled/enabled */
781 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
782 /* Number of control flags */
783 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
784};
785
786/*
787 * Control parameter IDs
788 */
4aa3bb0c 789enum control_param_id {
ef6b2ead
IM		 790 /* 0: None, 1: Mic1In*/
791 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 792 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
793 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 794 /* Port A output stage gain setting to use when 16 Ohm output
795 * impedance is selected*/
796 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
797 /* Port D output stage gain setting to use when 16 Ohm output
798 * impedance is selected*/
799 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 800
801 /* Stream Control */
802
803 /* Select stream with the given ID */
804 CONTROL_PARAM_STREAM_ID = 24,
805 /* Source connection point for the selected stream */
806 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
807 /* Destination connection point for the selected stream */
808 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
809 /* Number of audio channels in the selected stream */
810 CONTROL_PARAM_STREAMS_CHANNELS = 27,
811 /*Enable control for the selected stream */
812 CONTROL_PARAM_STREAM_CONTROL = 28,
813
814 /* Connection Point Control */
815
816 /* Select connection point with the given ID */
817 CONTROL_PARAM_CONN_POINT_ID = 29,
818 /* Connection point sample rate */
819 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
820
821 /* Node Control */
822
823 /* Select HDA node with the given ID */
824 CONTROL_PARAM_NODE_ID = 31
825};
826
827/*
828 * Dsp Io Status codes
829 */
830enum hda_vendor_status_dspio {
831 /* Success */
832 VENDOR_STATUS_DSPIO_OK = 0x00,
833 /* Busy, unable to accept new command, the host must retry */
834 VENDOR_STATUS_DSPIO_BUSY = 0x01,
835 /* SCP command queue is full */
836 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
837 /* SCP response queue is empty */
838 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
839};
840
841/*
842 * Chip Io Status codes
843 */
844enum hda_vendor_status_chipio {
845 /* Success */
846 VENDOR_STATUS_CHIPIO_OK = 0x00,
847 /* Busy, unable to accept new command, the host must retry */
848 VENDOR_STATUS_CHIPIO_BUSY = 0x01
849};
850
851/*
852 * CA0132 sample rate
853 */
854enum ca0132_sample_rate {
855 SR_6_000 = 0x00,
856 SR_8_000 = 0x01,
857 SR_9_600 = 0x02,
858 SR_11_025 = 0x03,
859 SR_16_000 = 0x04,
860 SR_22_050 = 0x05,
861 SR_24_000 = 0x06,
862 SR_32_000 = 0x07,
863 SR_44_100 = 0x08,
864 SR_48_000 = 0x09,
865 SR_88_200 = 0x0A,
866 SR_96_000 = 0x0B,
867 SR_144_000 = 0x0C,
868 SR_176_400 = 0x0D,
869 SR_192_000 = 0x0E,
870 SR_384_000 = 0x0F,
871
872 SR_COUNT = 0x10,
873
874 SR_RATE_UNKNOWN = 0x1F
875};
876
01ef7dbf
IM		 877enum dsp_download_state {
878 DSP_DOWNLOAD_FAILED = -1,
879 DSP_DOWNLOAD_INIT = 0,
880 DSP_DOWNLOADING = 1,
881 DSP_DOWNLOADED = 2
882};
883
01ef7dbf
IM		 884/* retrieve parameters from hda format */
885#define get_hdafmt_chs(fmt) (fmt & 0xf)
886#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
887#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
888#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
889
890/*
891 * CA0132 specific
892 */
893
894struct ca0132_spec {
b0eaa072 895 const struct snd_kcontrol_new *mixers[5];
a7e76271 896 unsigned int num_mixers;
5aaca44d
IM		 897 const struct hda_verb *base_init_verbs;
898 const struct hda_verb *base_exit_verbs;
d5c016b5 899 const struct hda_verb *chip_init_verbs;
e93ac30a 900 const struct hda_verb *sbz_init_verbs;
d5c016b5 901 struct hda_verb *spec_init_verbs;
01ef7dbf 902 struct auto_pin_cfg autocfg;
5aaca44d
IM		 903
904 /* Nodes configurations */
01ef7dbf
IM		 905 struct hda_multi_out multiout;
906 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
907 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 908 unsigned int num_outputs;
01ef7dbf
IM		 909 hda_nid_t input_pins[AUTO_PIN_LAST];
910 hda_nid_t adcs[AUTO_PIN_LAST];
911 hda_nid_t dig_out;
912 hda_nid_t dig_in;
913 unsigned int num_inputs;
a7e76271
IM		 914 hda_nid_t shared_mic_nid;
915 hda_nid_t shared_out_nid;
d5c016b5 916 hda_nid_t unsol_tag_hp;
63177afc 917 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 918 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 919
920 /* chip access */
921 struct mutex chipio_mutex; /* chip access mutex */
922 u32 curr_chip_addx;
923
924 /* DSP download related */
925 enum dsp_download_state dsp_state;
926 unsigned int dsp_stream_id;
927 unsigned int wait_scp;
928 unsigned int wait_scp_header;
929 unsigned int wait_num_data;
930 unsigned int scp_resp_header;
931 unsigned int scp_resp_data[4];
932 unsigned int scp_resp_count;
8a19bcee 933 bool alt_firmware_present;
38ba69ff 934 bool startup_check_entered;
e93ac30a 935 bool dsp_reload;
5aaca44d
IM		 936
937 /* mixer and effects related */
938 unsigned char dmic_ctl;
939 int cur_out_type;
940 int cur_mic_type;
941 long vnode_lvol[VNODES_COUNT];
942 long vnode_rvol[VNODES_COUNT];
943 long vnode_lswitch[VNODES_COUNT];
944 long vnode_rswitch[VNODES_COUNT];
945 long effects_switch[EFFECTS_COUNT];
946 long voicefx_val;
947 long cur_mic_boost;
7cb9d94c
CM		 948 /* ca0132_alt control related values */
949 unsigned char in_enum_val;
950 unsigned char out_enum_val;
47cdf76e
CM		 951 unsigned char mic_boost_enum_val;
952 unsigned char smart_volume_setting;
953 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
954 long xbass_xover_freq;
955 long eq_preset_val;
956 unsigned int tlv[4];
957 struct hda_vmaster_mute_hook vmaster_mute;
958
44f0c978 959
993884f6
CCC		 960 struct hda_codec *codec;
961 struct delayed_work unsol_hp_work;
d5c016b5 962 int quirk;
993884f6 963
44f0c978
IM		 964#ifdef ENABLE_TUNING_CONTROLS
965 long cur_ctl_vals[TUNING_CTLS_COUNT];
966#endif
aa31704f
CM		 967 /*
968 * Sound Blaster Z PCI region 2 iomem, used for input and output
969 * switching, and other unknown commands.
970 */
971 void __iomem *mem_base;
009b8f97
CM		 972
973 /*
974 * Whether or not to use the alt functions like alt_select_out,
975 * alt_select_in, etc. Only used on desktop codecs for now, because of
976 * surround sound support.
977 */
978 bool use_alt_functions;
47cdf76e
CM		 979
980 /*
981 * Whether or not to use alt controls: volume effect sliders, EQ
982 * presets, smart volume presets, and new control names with FX prefix.
983 * Renames PlayEnhancement and CrystalVoice too.
984 */
985 bool use_alt_controls;
01ef7dbf
IM		 986};
987
d5c016b5
GM		 988/*
989 * CA0132 quirks table
990 */
991enum {
992 QUIRK_NONE,
993 QUIRK_ALIENWARE,
8a19bcee
CM		 994 QUIRK_SBZ,
995 QUIRK_R3DI,
d5c016b5
GM		 996};
997
fe14f39e
TI		 998static const struct hda_pintbl alienware_pincfgs[] = {
999 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1000 { 0x0c, 0x411111f0 }, /* N/A */
1001 { 0x0d, 0x411111f0 }, /* N/A */
1002 { 0x0e, 0x411111f0 }, /* N/A */
1003 { 0x0f, 0x0321101f }, /* HP */
1004 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1005 { 0x11, 0x03a11021 }, /* Mic */
1006 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1007 { 0x13, 0x411111f0 }, /* N/A */
1008 { 0x18, 0x411111f0 }, /* N/A */
1009 {}
1010};
1011
63177afc
CM		 1012/* Sound Blaster Z pin configs taken from Windows Driver */
1013static const struct hda_pintbl sbz_pincfgs[] = {
1014 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1015 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1016 { 0x0d, 0x014510f0 }, /* Digital Out */
1017 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1018 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1019 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1020 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1021 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1022 { 0x13, 0x908700f0 }, /* What U Hear In*/
1023 { 0x18, 0x50d000f0 }, /* N/A */
1024 {}
1025};
1026
1027/* Recon3D integrated pin configs taken from Windows Driver */
1028static const struct hda_pintbl r3di_pincfgs[] = {
1029 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1030 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1031 { 0x0d, 0x014510f0 }, /* Digital Out */
1032 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1033 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1034 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1035 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1036 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1037 { 0x13, 0x908700f0 }, /* What U Hear In*/
1038 { 0x18, 0x500000f0 }, /* N/A */
1039 {}
1040};
1041
d5c016b5 1042static const struct snd_pci_quirk ca0132_quirks[] = {
5328e1ea
GM		 1043 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1044 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1045 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1046 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1047 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1048 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1049 SND_PCI_QUIRK(0x1458, 0xA036, "Recon3Di", QUIRK_R3DI),
d5c016b5
GM		 1050 {}
1051};
1052
01ef7dbf
IM		 1053/*
1054 * CA0132 codec access
1055 */
399ae725 1056static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1057 unsigned int verb, unsigned int parm, unsigned int *res)
1058{
1059 unsigned int response;
1060 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1061 *res = response;
1062
1063 return ((response == -1) ? -1 : 0);
1064}
1065
1066static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1067 unsigned short converter_format, unsigned int *res)
1068{
1069 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1070 converter_format & 0xffff, res);
1071}
1072
1073static int codec_set_converter_stream_channel(struct hda_codec *codec,
1074 hda_nid_t nid, unsigned char stream,
1075 unsigned char channel, unsigned int *res)
1076{
1077 unsigned char converter_stream_channel = 0;
1078
1079 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1080 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1081 converter_stream_channel, res);
1082}
1083
1084/* Chip access helper function */
1085static int chipio_send(struct hda_codec *codec,
1086 unsigned int reg,
1087 unsigned int data)
1088{
1089 unsigned int res;
6d67530e 1090 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1091
1092 /* send bits of data specified by reg */
1093 do {
1094 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1095 reg, data);
1096 if (res == VENDOR_STATUS_CHIPIO_OK)
1097 return 0;
6d67530e
IM		 1098 msleep(20);
1099 } while (time_before(jiffies, timeout));
1100
01ef7dbf
IM		 1101 return -EIO;
1102}
1103
1104/*
1105 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1106 */
1107static int chipio_write_address(struct hda_codec *codec,
1108 unsigned int chip_addx)
1109{
4861af80 1110 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1111 int res;
1112
4861af80
IM		 1113 if (spec->curr_chip_addx == chip_addx)
1114 return 0;
1115
01ef7dbf
IM		 1116 /* send low 16 bits of the address */
1117 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1118 chip_addx & 0xffff);
1119
1120 if (res != -EIO) {
1121 /* send high 16 bits of the address */
1122 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1123 chip_addx >> 16);
1124 }
1125
d1600401 1126 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1127
4861af80 1128 return res;
01ef7dbf
IM		 1129}
1130
1131/*
1132 * Write data through the vendor widget -- NOT protected by the Mutex!
1133 */
01ef7dbf
IM		 1134static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1135{
5aaca44d 1136 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1137 int res;
1138
1139 /* send low 16 bits of the data */
1140 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1141
1142 if (res != -EIO) {
1143 /* send high 16 bits of the data */
1144 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1145 data >> 16);
1146 }
1147
5aaca44d
IM		 1148 /*If no error encountered, automatically increment the address
1149 as per chip behaviour*/
1150 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1151 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1152 return res;
1153}
1154
d5c21b88
IM		 1155/*
1156 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1157 */
01ef7dbf
IM		 1158static int chipio_write_data_multiple(struct hda_codec *codec,
1159 const u32 *data,
1160 unsigned int count)
1161{
1162 int status = 0;
1163
1164 if (data == NULL) {
4e76a883 1165 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1166 return -EINVAL;
1167 }
1168
1169 while ((count-- != 0) && (status == 0))
1170 status = chipio_write_data(codec, *data++);
1171
1172 return status;
1173}
1174
1175
1176/*
1177 * Read data through the vendor widget -- NOT protected by the Mutex!
1178 */
1179static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1180{
5aaca44d 1181 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1182 int res;
1183
1184 /* post read */
1185 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1186
1187 if (res != -EIO) {
1188 /* read status */
1189 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1190 }
1191
1192 if (res != -EIO) {
1193 /* read data */
1194 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1195 VENDOR_CHIPIO_HIC_READ_DATA,
1196 0);
1197 }
1198
5aaca44d
IM		 1199 /*If no error encountered, automatically increment the address
1200 as per chip behaviour*/
1201 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1202 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1203 return res;
1204}
1205
1206/*
1207 * Write given value to the given address through the chip I/O widget.
1208 * protected by the Mutex
1209 */
1210static int chipio_write(struct hda_codec *codec,
1211 unsigned int chip_addx, const unsigned int data)
1212{
1213 struct ca0132_spec *spec = codec->spec;
1214 int err;
1215
1216 mutex_lock(&spec->chipio_mutex);
1217
1218 /* write the address, and if successful proceed to write data */
1219 err = chipio_write_address(codec, chip_addx);
1220 if (err < 0)
1221 goto exit;
1222
1223 err = chipio_write_data(codec, data);
1224 if (err < 0)
1225 goto exit;
1226
1227exit:
1228 mutex_unlock(&spec->chipio_mutex);
1229 return err;
1230}
1231
38ba69ff
CM		 1232/*
1233 * Write given value to the given address through the chip I/O widget.
1234 * not protected by the Mutex
1235 */
1236static int chipio_write_no_mutex(struct hda_codec *codec,
1237 unsigned int chip_addx, const unsigned int data)
1238{
1239 int err;
1240
1241
1242 /* write the address, and if successful proceed to write data */
1243 err = chipio_write_address(codec, chip_addx);
1244 if (err < 0)
1245 goto exit;
1246
1247 err = chipio_write_data(codec, data);
1248 if (err < 0)
1249 goto exit;
1250
1251exit:
1252 return err;
1253}
1254
d5c21b88
IM		 1255/*
1256 * Write multiple values to the given address through the chip I/O widget.
1257 * protected by the Mutex
1258 */
01ef7dbf
IM		 1259static int chipio_write_multiple(struct hda_codec *codec,
1260 u32 chip_addx,
1261 const u32 *data,
1262 unsigned int count)
1263{
1264 struct ca0132_spec *spec = codec->spec;
1265 int status;
1266
1267 mutex_lock(&spec->chipio_mutex);
4861af80 1268 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1269 if (status < 0)
1270 goto error;
1271
1272 status = chipio_write_data_multiple(codec, data, count);
1273error:
1274 mutex_unlock(&spec->chipio_mutex);
1275
1276 return status;
1277}
1278
1279/*
1280 * Read the given address through the chip I/O widget
1281 * protected by the Mutex
1282 */
1283static int chipio_read(struct hda_codec *codec,
1284 unsigned int chip_addx, unsigned int *data)
1285{
1286 struct ca0132_spec *spec = codec->spec;
1287 int err;
1288
1289 mutex_lock(&spec->chipio_mutex);
1290
1291 /* write the address, and if successful proceed to write data */
1292 err = chipio_write_address(codec, chip_addx);
1293 if (err < 0)
1294 goto exit;
1295
1296 err = chipio_read_data(codec, data);
1297 if (err < 0)
1298 goto exit;
1299
1300exit:
1301 mutex_unlock(&spec->chipio_mutex);
1302 return err;
1303}
1304
d5c21b88
IM		 1305/*
1306 * Set chip control flags through the chip I/O widget.
1307 */
01ef7dbf
IM		 1308static void chipio_set_control_flag(struct hda_codec *codec,
1309 enum control_flag_id flag_id,
1310 bool flag_state)
1311{
1312 unsigned int val;
1313 unsigned int flag_bit;
1314
1315 flag_bit = (flag_state ? 1 : 0);
1316 val = (flag_bit << 7) | (flag_id);
1317 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1318 VENDOR_CHIPIO_FLAG_SET, val);
1319}
1320
d5c21b88
IM		 1321/*
1322 * Set chip parameters through the chip I/O widget.
1323 */
01ef7dbf
IM		 1324static void chipio_set_control_param(struct hda_codec *codec,
1325 enum control_param_id param_id, int param_val)
1326{
1327 struct ca0132_spec *spec = codec->spec;
1328 int val;
1329
1330 if ((param_id < 32) && (param_val < 8)) {
1331 val = (param_val << 5) | (param_id);
1332 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1333 VENDOR_CHIPIO_PARAM_SET, val);
1334 } else {
1335 mutex_lock(&spec->chipio_mutex);
1336 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1337 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1338 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1339 param_id);
1340 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1341 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1342 param_val);
1343 }
1344 mutex_unlock(&spec->chipio_mutex);
1345 }
1346}
1347
009b8f97
CM		 1348/*
1349 * Set chip parameters through the chip I/O widget. NO MUTEX.
1350 */
1351static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1352 enum control_param_id param_id, int param_val)
1353{
1354 int val;
1355
1356 if ((param_id < 32) && (param_val < 8)) {
1357 val = (param_val << 5) | (param_id);
1358 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1359 VENDOR_CHIPIO_PARAM_SET, val);
1360 } else {
1361 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1362 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1363 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1364 param_id);
1365 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1366 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1367 param_val);
1368 }
1369 }
1370}
38ba69ff
CM		 1371/*
1372 * Connect stream to a source point, and then connect
1373 * that source point to a destination point.
1374 */
1375static void chipio_set_stream_source_dest(struct hda_codec *codec,
1376 int streamid, int source_point, int dest_point)
1377{
1378 chipio_set_control_param_no_mutex(codec,
1379 CONTROL_PARAM_STREAM_ID, streamid);
1380 chipio_set_control_param_no_mutex(codec,
1381 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1382 chipio_set_control_param_no_mutex(codec,
1383 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1384}
1385
1386/*
1387 * Set number of channels in the selected stream.
1388 */
1389static void chipio_set_stream_channels(struct hda_codec *codec,
1390 int streamid, unsigned int channels)
1391{
1392 chipio_set_control_param_no_mutex(codec,
1393 CONTROL_PARAM_STREAM_ID, streamid);
1394 chipio_set_control_param_no_mutex(codec,
1395 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1396}
009b8f97
CM		 1397
1398/*
1399 * Enable/Disable audio stream.
1400 */
1401static void chipio_set_stream_control(struct hda_codec *codec,
1402 int streamid, int enable)
1403{
1404 chipio_set_control_param_no_mutex(codec,
1405 CONTROL_PARAM_STREAM_ID, streamid);
1406 chipio_set_control_param_no_mutex(codec,
1407 CONTROL_PARAM_STREAM_CONTROL, enable);
1408}
1409
38ba69ff
CM		 1410
1411/*
1412 * Set sampling rate of the connection point. NO MUTEX.
1413 */
1414static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1415 int connid, enum ca0132_sample_rate rate)
1416{
1417 chipio_set_control_param_no_mutex(codec,
1418 CONTROL_PARAM_CONN_POINT_ID, connid);
1419 chipio_set_control_param_no_mutex(codec,
1420 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1421}
1422
d5c21b88
IM		 1423/*
1424 * Set sampling rate of the connection point.
1425 */
01ef7dbf
IM		 1426static void chipio_set_conn_rate(struct hda_codec *codec,
1427 int connid, enum ca0132_sample_rate rate)
1428{
1429 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1430 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1431 rate);
1432}
1433
d5c21b88
IM		 1434/*
1435 * Enable clocks.
1436 */
01ef7dbf
IM		 1437static void chipio_enable_clocks(struct hda_codec *codec)
1438{
1439 struct ca0132_spec *spec = codec->spec;
1440
1441 mutex_lock(&spec->chipio_mutex);
1442 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1443 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1444 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1445 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1446 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1447 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1448 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1449 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1450 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1451 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1452 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1453 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1454 mutex_unlock(&spec->chipio_mutex);
1455}
1456
1457/*
1458 * CA0132 DSP IO stuffs
1459 */
1460static int dspio_send(struct hda_codec *codec, unsigned int reg,
1461 unsigned int data)
1462{
b645d796 1463 int res;
6d67530e 1464 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1465
1466 /* send bits of data specified by reg to dsp */
1467 do {
1468 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1469 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1470 return res;
6d67530e
IM		 1471 msleep(20);
1472 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1473
1474 return -EIO;
1475}
1476
d5c21b88
IM		 1477/*
1478 * Wait for DSP to be ready for commands
1479 */
01ef7dbf
IM		 1480static void dspio_write_wait(struct hda_codec *codec)
1481{
4861af80
IM		 1482 int status;
1483 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1484
01ef7dbf 1485 do {
4861af80
IM		 1486 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1487 VENDOR_DSPIO_STATUS, 0);
1488 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1489 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1490 break;
1491 msleep(1);
1492 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1493}
1494
d5c21b88
IM		 1495/*
1496 * Write SCP data to DSP
1497 */
01ef7dbf
IM		 1498static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1499{
1500 struct ca0132_spec *spec = codec->spec;
1501 int status;
1502
1503 dspio_write_wait(codec);
1504
1505 mutex_lock(&spec->chipio_mutex);
1506 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1507 scp_data & 0xffff);
1508 if (status < 0)
1509 goto error;
1510
1511 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1512 scp_data >> 16);
1513 if (status < 0)
1514 goto error;
1515
1516 /* OK, now check if the write itself has executed*/
1517 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1518 VENDOR_DSPIO_STATUS, 0);
1519error:
1520 mutex_unlock(&spec->chipio_mutex);
1521
1522 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1523 -EIO : 0;
1524}
1525
d5c21b88
IM		 1526/*
1527 * Write multiple SCP data to DSP
1528 */
01ef7dbf
IM		 1529static int dspio_write_multiple(struct hda_codec *codec,
1530 unsigned int *buffer, unsigned int size)
1531{
1532 int status = 0;
1533 unsigned int count;
1534
a16fbb85 1535 if (buffer == NULL)
01ef7dbf
IM		 1536 return -EINVAL;
1537
1538 count = 0;
1539 while (count < size) {
1540 status = dspio_write(codec, *buffer++);
1541 if (status != 0)
1542 break;
1543 count++;
1544 }
1545
1546 return status;
1547}
1548
a73d511c
IM		 1549static int dspio_read(struct hda_codec *codec, unsigned int *data)
1550{
1551 int status;
1552
1553 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1554 if (status == -EIO)
1555 return status;
1556
1557 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1558 if (status == -EIO ||
1559 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1560 return -EIO;
1561
1562 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1563 VENDOR_DSPIO_SCP_READ_DATA, 0);
1564
1565 return 0;
1566}
1567
1568static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1569 unsigned int *buf_size, unsigned int size_count)
1570{
1571 int status = 0;
1572 unsigned int size = *buf_size;
1573 unsigned int count;
1574 unsigned int skip_count;
1575 unsigned int dummy;
1576
a16fbb85 1577 if (buffer == NULL)
a73d511c
IM		 1578 return -1;
1579
1580 count = 0;
1581 while (count < size && count < size_count) {
1582 status = dspio_read(codec, buffer++);
1583 if (status != 0)
1584 break;
1585 count++;
1586 }
1587
1588 skip_count = count;
1589 if (status == 0) {
1590 while (skip_count < size) {
1591 status = dspio_read(codec, &dummy);
1592 if (status != 0)
1593 break;
1594 skip_count++;
1595 }
1596 }
1597 *buf_size = count;
1598
1599 return status;
1600}
1601
d5c21b88
IM		 1602/*
1603 * Construct the SCP header using corresponding fields
1604 */
01ef7dbf
IM		 1605static inline unsigned int
1606make_scp_header(unsigned int target_id, unsigned int source_id,
1607 unsigned int get_flag, unsigned int req,
1608 unsigned int device_flag, unsigned int resp_flag,
1609 unsigned int error_flag, unsigned int data_size)
1610{
1611 unsigned int header = 0;
1612
1613 header = (data_size & 0x1f) << 27;
1614 header |= (error_flag & 0x01) << 26;
1615 header |= (resp_flag & 0x01) << 25;
1616 header |= (device_flag & 0x01) << 24;
1617 header |= (req & 0x7f) << 17;
1618 header |= (get_flag & 0x01) << 16;
1619 header |= (source_id & 0xff) << 8;
1620 header |= target_id & 0xff;
1621
1622 return header;
1623}
1624
d5c21b88
IM		 1625/*
1626 * Extract corresponding fields from SCP header
1627 */
01ef7dbf
IM		 1628static inline void
1629extract_scp_header(unsigned int header,
1630 unsigned int *target_id, unsigned int *source_id,
1631 unsigned int *get_flag, unsigned int *req,
1632 unsigned int *device_flag, unsigned int *resp_flag,
1633 unsigned int *error_flag, unsigned int *data_size)
1634{
1635 if (data_size)
1636 *data_size = (header >> 27) & 0x1f;
1637 if (error_flag)
1638 *error_flag = (header >> 26) & 0x01;
1639 if (resp_flag)
1640 *resp_flag = (header >> 25) & 0x01;
1641 if (device_flag)
1642 *device_flag = (header >> 24) & 0x01;
1643 if (req)
1644 *req = (header >> 17) & 0x7f;
1645 if (get_flag)
1646 *get_flag = (header >> 16) & 0x01;
1647 if (source_id)
1648 *source_id = (header >> 8) & 0xff;
1649 if (target_id)
1650 *target_id = header & 0xff;
1651}
1652
1653#define SCP_MAX_DATA_WORDS (16)
1654
1655/* Structure to contain any SCP message */
1656struct scp_msg {
1657 unsigned int hdr;
1658 unsigned int data[SCP_MAX_DATA_WORDS];
1659};
1660
a73d511c
IM		 1661static void dspio_clear_response_queue(struct hda_codec *codec)
1662{
1663 unsigned int dummy = 0;
1664 int status = -1;
1665
1666 /* clear all from the response queue */
1667 do {
1668 status = dspio_read(codec, &dummy);
1669 } while (status == 0);
1670}
1671
1672static int dspio_get_response_data(struct hda_codec *codec)
1673{
1674 struct ca0132_spec *spec = codec->spec;
1675 unsigned int data = 0;
1676 unsigned int count;
1677
1678 if (dspio_read(codec, &data) < 0)
1679 return -EIO;
1680
1681 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1682 spec->scp_resp_header = data;
1683 spec->scp_resp_count = data >> 27;
1684 count = spec->wait_num_data;
1685 dspio_read_multiple(codec, spec->scp_resp_data,
1686 &spec->scp_resp_count, count);
1687 return 0;
1688 }
1689
1690 return -EIO;
1691}
1692
d5c21b88
IM		 1693/*
1694 * Send SCP message to DSP
1695 */
01ef7dbf
IM		 1696static int dspio_send_scp_message(struct hda_codec *codec,
1697 unsigned char *send_buf,
1698 unsigned int send_buf_size,
1699 unsigned char *return_buf,
1700 unsigned int return_buf_size,
1701 unsigned int *bytes_returned)
1702{
1703 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1704 int status = -1;
1705 unsigned int scp_send_size = 0;
1706 unsigned int total_size;
1707 bool waiting_for_resp = false;
1708 unsigned int header;
1709 struct scp_msg *ret_msg;
1710 unsigned int resp_src_id, resp_target_id;
1711 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1712
1713 if (bytes_returned)
1714 *bytes_returned = 0;
1715
1716 /* get scp header from buffer */
1717 header = *((unsigned int *)send_buf);
1718 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1719 &device_flag, NULL, NULL, &data_size);
1720 scp_send_size = data_size + 1;
1721 total_size = (scp_send_size * 4);
1722
1723 if (send_buf_size < total_size)
1724 return -EINVAL;
1725
1726 if (get_flag || device_flag) {
1727 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1728 return -EINVAL;
1729
1730 spec->wait_scp_header = *((unsigned int *)send_buf);
1731
1732 /* swap source id with target id */
1733 resp_target_id = src_id;
1734 resp_src_id = target_id;
1735 spec->wait_scp_header &= 0xffff0000;
1736 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1737 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1738 spec->wait_scp = 1;
1739 waiting_for_resp = true;
1740 }
1741
1742 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1743 scp_send_size);
1744 if (status < 0) {
1745 spec->wait_scp = 0;
1746 return status;
1747 }
1748
1749 if (waiting_for_resp) {
6d67530e 1750 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1751 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1752 do {
1753 msleep(20);
6d67530e 1754 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1755 waiting_for_resp = false;
6d67530e 1756 if (!spec->wait_scp) {
01ef7dbf
IM		 1757 ret_msg = (struct scp_msg *)return_buf;
1758 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1759 memcpy(&ret_msg->data, spec->scp_resp_data,
1760 spec->wait_num_data);
1761 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1762 status = 0;
1763 } else {
1764 status = -EIO;
1765 }
1766 spec->wait_scp = 0;
1767 }
1768
1769 return status;
1770}
1771
d5c21b88
IM		 1772/**
1773 * Prepare and send the SCP message to DSP
1774 * @codec: the HDA codec
1775 * @mod_id: ID of the DSP module to send the command
1776 * @req: ID of request to send to the DSP module
1777 * @dir: SET or GET
1778 * @data: pointer to the data to send with the request, request specific
1779 * @len: length of the data, in bytes
1780 * @reply: point to the buffer to hold data returned for a reply
1781 * @reply_len: length of the reply buffer returned from GET
1782 *
1783 * Returns zero or a negative error code.
1784 */
01ef7dbf 1785static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1786 int mod_id, int src_id, int req, int dir, const void *data,
1787 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1788{
1789 int status = 0;
1790 struct scp_msg scp_send, scp_reply;
1791 unsigned int ret_bytes, send_size, ret_size;
1792 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1793 unsigned int reply_data_size;
1794
1795 memset(&scp_send, 0, sizeof(scp_send));
1796 memset(&scp_reply, 0, sizeof(scp_reply));
1797
1798 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1799 return -EINVAL;
1800
1801 if (dir == SCP_GET && reply == NULL) {
4e76a883 1802 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1803 return -EINVAL;
1804 }
1805
1806 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1807 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1808 return -EINVAL;
1809 }
1810
447fd8e9 1811 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1812 0, 0, 0, len/sizeof(unsigned int));
1813 if (data != NULL && len > 0) {
1814 len = min((unsigned int)(sizeof(scp_send.data)), len);
1815 memcpy(scp_send.data, data, len);
1816 }
1817
1818 ret_bytes = 0;
1819 send_size = sizeof(unsigned int) + len;
1820 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1821 send_size, (unsigned char *)&scp_reply,
1822 sizeof(scp_reply), &ret_bytes);
1823
1824 if (status < 0) {
4e76a883 1825 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1826 return status;
1827 }
1828
1829 /* extract send and reply headers members */
1830 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1831 NULL, NULL, NULL, NULL, NULL);
1832 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1833 &reply_resp_flag, &reply_error_flag,
1834 &reply_data_size);
1835
1836 if (!send_get_flag)
1837 return 0;
1838
1839 if (reply_resp_flag && !reply_error_flag) {
1840 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1841 / sizeof(unsigned int);
1842
1843 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1844 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1845 return -EINVAL;
1846 } else if (ret_size != reply_data_size) {
4e76a883 1847 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1848 return -EINVAL;
46a049da
AB		 1849 } else if (!reply) {
1850 codec_dbg(codec, "NULL reply\n");
1851 return -EINVAL;
01ef7dbf
IM		 1852 } else {
1853 *reply_len = ret_size*sizeof(unsigned int);
1854 memcpy(reply, scp_reply.data, *reply_len);
1855 }
1856 } else {
4e76a883 1857 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1858 return -EIO;
1859 }
1860
1861 return status;
1862}
1863
5aaca44d
IM		 1864/*
1865 * Set DSP parameters
1866 */
1867static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 1868 int src_id, int req, const void *data, unsigned int len)
5aaca44d 1869{
447fd8e9
CM		 1870 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1871 NULL);
5aaca44d
IM		 1872}
1873
1874static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 1875 int req, const unsigned int data)
5aaca44d 1876{
447fd8e9
CM		 1877 return dspio_set_param(codec, mod_id, 0x20, req, &data,
1878 sizeof(unsigned int));
1879}
1880
1881static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1882 int req, const unsigned int data)
1883{
1884 return dspio_set_param(codec, mod_id, 0x00, req, &data,
1885 sizeof(unsigned int));
5aaca44d
IM		 1886}
1887
d5c21b88
IM		 1888/*
1889 * Allocate a DSP DMA channel via an SCP message
1890 */
01ef7dbf
IM		 1891static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1892{
1893 int status = 0;
1894 unsigned int size = sizeof(dma_chan);
1895
4e76a883 1896 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 1897 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1898 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1899 dma_chan, &size);
01ef7dbf
IM		 1900
1901 if (status < 0) {
4e76a883 1902 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1903 return status;
1904 }
1905
1906 if ((*dma_chan + 1) == 0) {
4e76a883 1907 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1908 return -EBUSY;
1909 }
1910
4e76a883
TI		 1911 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1912 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1913
1914 return status;
1915}
1916
d5c21b88
IM		 1917/*
1918 * Free a DSP DMA via an SCP message
1919 */
01ef7dbf
IM		 1920static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1921{
1922 int status = 0;
1923 unsigned int dummy = 0;
1924
4e76a883
TI		 1925 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1926 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 1927
447fd8e9
CM		 1928 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1929 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1930 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 1931
1932 if (status < 0) {
4e76a883 1933 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1934 return status;
1935 }
1936
4e76a883 1937 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1938
1939 return status;
1940}
1941
1942/*
d5c21b88 1943 * (Re)start the DSP
01ef7dbf
IM		 1944 */
1945static int dsp_set_run_state(struct hda_codec *codec)
1946{
1947 unsigned int dbg_ctrl_reg;
1948 unsigned int halt_state;
1949 int err;
1950
1951 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1952 if (err < 0)
1953 return err;
1954
1955 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1956 DSP_DBGCNTL_STATE_LOBIT;
1957
1958 if (halt_state != 0) {
1959 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1960 DSP_DBGCNTL_SS_MASK);
1961 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1962 dbg_ctrl_reg);
1963 if (err < 0)
1964 return err;
1965
1966 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1967 DSP_DBGCNTL_EXEC_MASK;
1968 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1969 dbg_ctrl_reg);
1970 if (err < 0)
1971 return err;
1972 }
1973
1974 return 0;
1975}
1976
d5c21b88
IM		 1977/*
1978 * Reset the DSP
1979 */
01ef7dbf
IM		 1980static int dsp_reset(struct hda_codec *codec)
1981{
1982 unsigned int res;
1983 int retry = 20;
1984
4e76a883 1985 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1986 do {
1987 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1988 retry--;
1989 } while (res == -EIO && retry);
1990
1991 if (!retry) {
4e76a883 1992 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1993 return -EIO;
1994 }
1995
1996 return 0;
1997}
1998
d5c21b88
IM		 1999/*
2000 * Convert chip address to DSP address
2001 */
01ef7dbf
IM		 2002static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2003 bool *code, bool *yram)
2004{
2005 *code = *yram = false;
2006
2007 if (UC_RANGE(chip_addx, 1)) {
2008 *code = true;
2009 return UC_OFF(chip_addx);
2010 } else if (X_RANGE_ALL(chip_addx, 1)) {
2011 return X_OFF(chip_addx);
2012 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2013 *yram = true;
2014 return Y_OFF(chip_addx);
2015 }
2016
4a8b89f9 2017 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2018}
2019
d5c21b88
IM		 2020/*
2021 * Check if the DSP DMA is active
2022 */
01ef7dbf
IM		 2023static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2024{
2025 unsigned int dma_chnlstart_reg;
2026
2027 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2028
2029 return ((dma_chnlstart_reg & (1 <<
2030 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2031}
2032
2033static int dsp_dma_setup_common(struct hda_codec *codec,
2034 unsigned int chip_addx,
2035 unsigned int dma_chan,
2036 unsigned int port_map_mask,
2037 bool ovly)
2038{
2039 int status = 0;
2040 unsigned int chnl_prop;
2041 unsigned int dsp_addx;
2042 unsigned int active;
2043 bool code, yram;
2044
4e76a883 2045 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2046
2047 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2048 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2049 return -EINVAL;
2050 }
2051
2052 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2053 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2054 return -EBUSY;
2055 }
2056
2057 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2058
2059 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2060 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2061 return -ENXIO;
2062 }
2063
2064 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2065 active = 0;
2066
4e76a883 2067 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2068
2069 if (ovly) {
2070 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2071 &chnl_prop);
2072
2073 if (status < 0) {
4e76a883 2074 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2075 return status;
2076 }
4e76a883 2077 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2078 }
2079
2080 if (!code)
2081 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2082 else
2083 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2084
2085 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2086
2087 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2088 if (status < 0) {
4e76a883 2089 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2090 return status;
2091 }
4e76a883 2092 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2093
2094 if (ovly) {
2095 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2096 &active);
2097
2098 if (status < 0) {
4e76a883 2099 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2100 return status;
2101 }
4e76a883 2102 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2103 }
2104
2105 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2106 DSPDMAC_ACTIVE_AAR_MASK;
2107
2108 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2109 if (status < 0) {
4e76a883 2110 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2111 return status;
2112 }
2113
4e76a883 2114 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2115
2116 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2117 port_map_mask);
2118 if (status < 0) {
4e76a883 2119 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2120 return status;
2121 }
4e76a883 2122 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2123
2124 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2125 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2126 if (status < 0) {
4e76a883 2127 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2128 return status;
2129 }
4e76a883 2130 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2131
4e76a883 2132 codec_dbg(codec,
01ef7dbf
IM		 2133 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2134 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2135 chip_addx, dsp_addx, dma_chan,
2136 port_map_mask, chnl_prop, active);
2137
4e76a883 2138 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2139
2140 return 0;
2141}
2142
d5c21b88
IM		 2143/*
2144 * Setup the DSP DMA per-transfer-specific registers
2145 */
01ef7dbf
IM		 2146static int dsp_dma_setup(struct hda_codec *codec,
2147 unsigned int chip_addx,
2148 unsigned int count,
2149 unsigned int dma_chan)
2150{
2151 int status = 0;
2152 bool code, yram;
2153 unsigned int dsp_addx;
2154 unsigned int addr_field;
2155 unsigned int incr_field;
2156 unsigned int base_cnt;
2157 unsigned int cur_cnt;
2158 unsigned int dma_cfg = 0;
2159 unsigned int adr_ofs = 0;
2160 unsigned int xfr_cnt = 0;
2161 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2162 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2163
4e76a883 2164 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2165
2166 if (count > max_dma_count) {
4e76a883 2167 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2168 return -EINVAL;
2169 }
2170
2171 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2172 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2173 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2174 return -ENXIO;
2175 }
2176
4e76a883 2177 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2178
2179 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2180 incr_field = 0;
2181
2182 if (!code) {
2183 addr_field <<= 1;
2184 if (yram)
2185 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2186
2187 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2188 }
2189
2190 dma_cfg = addr_field + incr_field;
2191 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2192 dma_cfg);
2193 if (status < 0) {
4e76a883 2194 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2195 return status;
2196 }
4e76a883 2197 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2198
2199 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2200 (code ? 0 : 1));
2201
2202 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2203 adr_ofs);
2204 if (status < 0) {
4e76a883 2205 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2206 return status;
2207 }
4e76a883 2208 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2209
2210 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2211
2212 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2213
2214 xfr_cnt = base_cnt | cur_cnt;
2215
2216 status = chipio_write(codec,
2217 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2218 if (status < 0) {
4e76a883 2219 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2220 return status;
2221 }
4e76a883 2222 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2223
4e76a883 2224 codec_dbg(codec,
01ef7dbf
IM		 2225 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2226 "ADROFS=0x%x, XFRCNT=0x%x\n",
2227 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2228
4e76a883 2229 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2230
2231 return 0;
2232}
2233
d5c21b88
IM		 2234/*
2235 * Start the DSP DMA
2236 */
01ef7dbf
IM		 2237static int dsp_dma_start(struct hda_codec *codec,
2238 unsigned int dma_chan, bool ovly)
2239{
2240 unsigned int reg = 0;
2241 int status = 0;
2242
4e76a883 2243 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2244
2245 if (ovly) {
2246 status = chipio_read(codec,
2247 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2248
2249 if (status < 0) {
4e76a883 2250 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2251 return status;
2252 }
4e76a883 2253 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2254
2255 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2256 DSPDMAC_CHNLSTART_DIS_MASK);
2257 }
2258
2259 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2260 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2261 if (status < 0) {
4e76a883 2262 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2263 return status;
2264 }
4e76a883 2265 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2266
2267 return status;
2268}
2269
d5c21b88
IM		 2270/*
2271 * Stop the DSP DMA
2272 */
01ef7dbf
IM		 2273static int dsp_dma_stop(struct hda_codec *codec,
2274 unsigned int dma_chan, bool ovly)
2275{
2276 unsigned int reg = 0;
2277 int status = 0;
2278
4e76a883 2279 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2280
2281 if (ovly) {
2282 status = chipio_read(codec,
2283 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2284
2285 if (status < 0) {
4e76a883 2286 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2287 return status;
2288 }
4e76a883 2289 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2290 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2291 DSPDMAC_CHNLSTART_DIS_MASK);
2292 }
2293
2294 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2295 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2296 if (status < 0) {
4e76a883 2297 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2298 return status;
2299 }
4e76a883 2300 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2301
2302 return status;
2303}
2304
d5c21b88
IM		 2305/**
2306 * Allocate router ports
2307 *
2308 * @codec: the HDA codec
2309 * @num_chans: number of channels in the stream
2310 * @ports_per_channel: number of ports per channel
2311 * @start_device: start device
2312 * @port_map: pointer to the port list to hold the allocated ports
2313 *
2314 * Returns zero or a negative error code.
2315 */
01ef7dbf
IM		 2316static int dsp_allocate_router_ports(struct hda_codec *codec,
2317 unsigned int num_chans,
2318 unsigned int ports_per_channel,
2319 unsigned int start_device,
2320 unsigned int *port_map)
2321{
2322 int status = 0;
2323 int res;
2324 u8 val;
2325
2326 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2327 if (status < 0)
2328 return status;
2329
2330 val = start_device << 6;
2331 val |= (ports_per_channel - 1) << 4;
2332 val |= num_chans - 1;
2333
2334 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2335 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2336 val);
2337
2338 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2339 VENDOR_CHIPIO_PORT_ALLOC_SET,
2340 MEM_CONNID_DSP);
2341
2342 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2343 if (status < 0)
2344 return status;
2345
2346 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2347 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2348
2349 *port_map = res;
2350
2351 return (res < 0) ? res : 0;
2352}
2353
d5c21b88
IM		 2354/*
2355 * Free router ports
2356 */
01ef7dbf
IM		 2357static int dsp_free_router_ports(struct hda_codec *codec)
2358{
2359 int status = 0;
2360
2361 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2362 if (status < 0)
2363 return status;
2364
2365 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2366 VENDOR_CHIPIO_PORT_FREE_SET,
2367 MEM_CONNID_DSP);
2368
2369 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2370
2371 return status;
2372}
2373
d5c21b88
IM		 2374/*
2375 * Allocate DSP ports for the download stream
2376 */
01ef7dbf
IM		 2377static int dsp_allocate_ports(struct hda_codec *codec,
2378 unsigned int num_chans,
2379 unsigned int rate_multi, unsigned int *port_map)
2380{
2381 int status;
2382
4e76a883 2383 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2384
2385 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2386 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2387 return -EINVAL;
2388 }
2389
2390 status = dsp_allocate_router_ports(codec, num_chans,
2391 rate_multi, 0, port_map);
2392
4e76a883 2393 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2394
2395 return status;
2396}
2397
01ef7dbf
IM		 2398static int dsp_allocate_ports_format(struct hda_codec *codec,
2399 const unsigned short fmt,
2400 unsigned int *port_map)
2401{
2402 int status;
2403 unsigned int num_chans;
2404
2405 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2406 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2407 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2408
2409 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2410 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2411 return -EINVAL;
2412 }
2413
2414 num_chans = get_hdafmt_chs(fmt) + 1;
2415
2416 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2417
2418 return status;
2419}
2420
d5c21b88
IM		 2421/*
2422 * free DSP ports
2423 */
2424static int dsp_free_ports(struct hda_codec *codec)
2425{
2426 int status;
2427
4e76a883 2428 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2429
2430 status = dsp_free_router_ports(codec);
2431 if (status < 0) {
4e76a883 2432 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2433 return status;
2434 }
4e76a883 2435 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2436
2437 return status;
2438}
2439
01ef7dbf
IM		 2440/*
2441 * HDA DMA engine stuffs for DSP code download
2442 */
2443struct dma_engine {
2444 struct hda_codec *codec;
2445 unsigned short m_converter_format;
2446 struct snd_dma_buffer *dmab;
2447 unsigned int buf_size;
2448};
2449
2450
2451enum dma_state {
2452 DMA_STATE_STOP = 0,
2453 DMA_STATE_RUN = 1
2454};
2455
6194b99d 2456static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2457 unsigned int sample_rate,
2458 unsigned short channels,
01ef7dbf
IM		 2459 unsigned short *hda_format)
2460{
2461 unsigned int format_val;
2462
b7d023e1
TI		 2463 format_val = snd_hdac_calc_stream_format(sample_rate,
2464 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2465
2466 if (hda_format)
2467 *hda_format = (unsigned short)format_val;
2468
2469 return 0;
2470}
2471
d5c21b88
IM		 2472/*
2473 * Reset DMA for DSP download
2474 */
01ef7dbf
IM		 2475static int dma_reset(struct dma_engine *dma)
2476{
2477 struct hda_codec *codec = dma->codec;
2478 struct ca0132_spec *spec = codec->spec;
2479 int status;
2480
b3667bd7 2481 if (dma->dmab->area)
01ef7dbf
IM		 2482 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2483
2484 status = snd_hda_codec_load_dsp_prepare(codec,
2485 dma->m_converter_format,
2486 dma->buf_size,
2487 dma->dmab);
2488 if (status < 0)
2489 return status;
2490 spec->dsp_stream_id = status;
2491 return 0;
2492}
2493
2494static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2495{
01ef7dbf
IM		 2496 bool cmd;
2497
01ef7dbf
IM		 2498 switch (state) {
2499 case DMA_STATE_STOP:
2500 cmd = false;
2501 break;
2502 case DMA_STATE_RUN:
2503 cmd = true;
2504 break;
2505 default:
c41999a2
DH		 2506 return 0;
2507 }
01ef7dbf
IM		 2508
2509 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2510 return 0;
95c6e9cb
IM		 2511}
2512
01ef7dbf
IM		 2513static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2514{
2515 return dma->dmab->bytes;
2516}
95c6e9cb 2517
01ef7dbf
IM		 2518static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2519{
2520 return dma->dmab->area;
2521}
95c6e9cb 2522
01ef7dbf
IM		 2523static int dma_xfer(struct dma_engine *dma,
2524 const unsigned int *data,
2525 unsigned int count)
2526{
2527 memcpy(dma->dmab->area, data, count);
2528 return 0;
2529}
95c6e9cb 2530
01ef7dbf
IM		 2531static void dma_get_converter_format(
2532 struct dma_engine *dma,
2533 unsigned short *format)
2534{
2535 if (format)
2536 *format = dma->m_converter_format;
2537}
95c6e9cb 2538
01ef7dbf 2539static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2540{
01ef7dbf 2541 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2542
01ef7dbf 2543 return spec->dsp_stream_id;
95c6e9cb
IM		 2544}
2545
01ef7dbf
IM		 2546struct dsp_image_seg {
2547 u32 magic;
2548 u32 chip_addr;
2549 u32 count;
2550 u32 data[0];
2551};
2552
2553static const u32 g_magic_value = 0x4c46584d;
2554static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2555
2556static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2557{
01ef7dbf
IM		 2558 return p->magic == g_magic_value;
2559}
95c6e9cb 2560
01ef7dbf
IM		 2561static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2562{
2563 return g_chip_addr_magic_value == p->chip_addr;
2564}
95c6e9cb 2565
01ef7dbf
IM		 2566static bool is_last(const struct dsp_image_seg *p)
2567{
2568 return p->count == 0;
2569}
95c6e9cb 2570
01ef7dbf
IM		 2571static size_t dsp_sizeof(const struct dsp_image_seg *p)
2572{
2573 return sizeof(*p) + p->count*sizeof(u32);
2574}
2575
2576static const struct dsp_image_seg *get_next_seg_ptr(
2577 const struct dsp_image_seg *p)
2578{
2579 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2580}
2581
2582/*
01ef7dbf 2583 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2584 */
8ae3124b 2585#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2586
d5c21b88
IM		 2587/*
2588 * Program a list of address/data pairs via the ChipIO widget.
2589 * The segment data is in the format of successive pairs of words.
2590 * These are repeated as indicated by the segment's count field.
2591 */
01ef7dbf
IM		 2592static int dspxfr_hci_write(struct hda_codec *codec,
2593 const struct dsp_image_seg *fls)
95c6e9cb 2594{
01ef7dbf
IM		 2595 int status;
2596 const u32 *data;
2597 unsigned int count;
95c6e9cb 2598
01ef7dbf 2599 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2600 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2601 return -EINVAL;
95c6e9cb
IM		 2602 }
2603
01ef7dbf
IM		 2604 count = fls->count;
2605 data = (u32 *)(fls->data);
2606 while (count >= 2) {
2607 status = chipio_write(codec, data[0], data[1]);
2608 if (status < 0) {
4e76a883 2609 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2610 return status;
2611 }
2612 count -= 2;
2613 data += 2;
2614 }
2615 return 0;
95c6e9cb
IM		 2616}
2617
d5c21b88
IM		 2618/**
2619 * Write a block of data into DSP code or data RAM using pre-allocated
2620 * DMA engine.
2621 *
2622 * @codec: the HDA codec
2623 * @fls: pointer to a fast load image
2624 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2625 * no relocation
2626 * @dma_engine: pointer to DMA engine to be used for DSP download
2627 * @dma_chan: The number of DMA channels used for DSP download
2628 * @port_map_mask: port mapping
2629 * @ovly: TRUE if overlay format is required
2630 *
2631 * Returns zero or a negative error code.
2632 */
01ef7dbf
IM		 2633static int dspxfr_one_seg(struct hda_codec *codec,
2634 const struct dsp_image_seg *fls,
2635 unsigned int reloc,
2636 struct dma_engine *dma_engine,
2637 unsigned int dma_chan,
2638 unsigned int port_map_mask,
2639 bool ovly)
95c6e9cb 2640{
406261ce 2641 int status = 0;
01ef7dbf
IM		 2642 bool comm_dma_setup_done = false;
2643 const unsigned int *data;
2644 unsigned int chip_addx;
2645 unsigned int words_to_write;
2646 unsigned int buffer_size_words;
2647 unsigned char *buffer_addx;
2648 unsigned short hda_format;
2649 unsigned int sample_rate_div;
2650 unsigned int sample_rate_mul;
2651 unsigned int num_chans;
2652 unsigned int hda_frame_size_words;
2653 unsigned int remainder_words;
2654 const u32 *data_remainder;
2655 u32 chip_addx_remainder;
2656 unsigned int run_size_words;
2657 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2658 unsigned long timeout;
2659 bool dma_active;
01ef7dbf
IM		 2660
2661 if (fls == NULL)
2662 return -EINVAL;
2663 if (is_hci_prog_list_seg(fls)) {
2664 hci_write = fls;
2665 fls = get_next_seg_ptr(fls);
2666 }
95c6e9cb 2667
01ef7dbf 2668 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2669 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2670 return dspxfr_hci_write(codec, hci_write);
2671 }
95c6e9cb 2672
01ef7dbf 2673 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2674 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2675 return -EINVAL;
95c6e9cb
IM		 2676 }
2677
01ef7dbf
IM		 2678 data = fls->data;
2679 chip_addx = fls->chip_addr,
2680 words_to_write = fls->count;
2681
2682 if (!words_to_write)
2683 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2684 if (reloc)
2685 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2686
2687 if (!UC_RANGE(chip_addx, words_to_write) &&
2688 !X_RANGE_ALL(chip_addx, words_to_write) &&
2689 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2690 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2691 return -EINVAL;
95c6e9cb
IM		 2692 }
2693
01ef7dbf
IM		 2694 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2695 sizeof(u32);
2696
2697 buffer_addx = dma_get_buffer_addr(dma_engine);
2698
2699 if (buffer_addx == NULL) {
4e76a883 2700 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2701 return -EINVAL;
2702 }
2703
2704 dma_get_converter_format(dma_engine, &hda_format);
2705 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2706 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2707 num_chans = get_hdafmt_chs(hda_format) + 1;
2708
2709 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2710 (num_chans * sample_rate_mul / sample_rate_div));
2711
3bc085a1 2712 if (hda_frame_size_words == 0) {
4e76a883 2713 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2714 return -EINVAL;
2715 }
2716
01ef7dbf
IM		 2717 buffer_size_words = min(buffer_size_words,
2718 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2719 65536 : 32768));
2720 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2721 codec_dbg(codec,
01ef7dbf
IM		 2722 "chpadr=0x%08x frmsz=%u nchan=%u "
2723 "rate_mul=%u div=%u bufsz=%u\n",
2724 chip_addx, hda_frame_size_words, num_chans,
2725 sample_rate_mul, sample_rate_div, buffer_size_words);
2726
3bc085a1 2727 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2728 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2729 return -EINVAL;
2730 }
2731
2732 remainder_words = words_to_write % hda_frame_size_words;
2733 data_remainder = data;
2734 chip_addx_remainder = chip_addx;
2735
2736 data += remainder_words;
2737 chip_addx += remainder_words*sizeof(u32);
2738 words_to_write -= remainder_words;
2739
2740 while (words_to_write != 0) {
2741 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2742 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2743 words_to_write, run_size_words, remainder_words);
2744 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2745 if (!comm_dma_setup_done) {
2746 status = dsp_dma_stop(codec, dma_chan, ovly);
2747 if (status < 0)
425a7880 2748 return status;
01ef7dbf
IM		 2749 status = dsp_dma_setup_common(codec, chip_addx,
2750 dma_chan, port_map_mask, ovly);
2751 if (status < 0)
2752 return status;
2753 comm_dma_setup_done = true;
2754 }
2755
2756 status = dsp_dma_setup(codec, chip_addx,
2757 run_size_words, dma_chan);
2758 if (status < 0)
2759 return status;
2760 status = dsp_dma_start(codec, dma_chan, ovly);
2761 if (status < 0)
2762 return status;
2763 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2764 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2765 return -EIO;
2766 }
2767 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2768 if (status < 0)
2769 return status;
2770 if (remainder_words != 0) {
2771 status = chipio_write_multiple(codec,
2772 chip_addx_remainder,
2773 data_remainder,
2774 remainder_words);
b3667bd7
TI		 2775 if (status < 0)
2776 return status;
01ef7dbf
IM		 2777 remainder_words = 0;
2778 }
2779 if (hci_write) {
2780 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2781 if (status < 0)
2782 return status;
01ef7dbf
IM		 2783 hci_write = NULL;
2784 }
6d67530e
IM		 2785
2786 timeout = jiffies + msecs_to_jiffies(2000);
2787 do {
2788 dma_active = dsp_is_dma_active(codec, dma_chan);
2789 if (!dma_active)
01ef7dbf 2790 break;
6d67530e
IM		 2791 msleep(20);
2792 } while (time_before(jiffies, timeout));
2793 if (dma_active)
2794 break;
2795
4e76a883 2796 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2797 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2798 status = dma_reset(dma_engine);
01ef7dbf
IM		 2799
2800 if (status < 0)
2801 return status;
2802
2803 data += run_size_words;
2804 chip_addx += run_size_words*sizeof(u32);
2805 words_to_write -= run_size_words;
2806 }
2807
2808 if (remainder_words != 0) {
2809 status = chipio_write_multiple(codec, chip_addx_remainder,
2810 data_remainder, remainder_words);
2811 }
2812
2813 return status;
95c6e9cb
IM		 2814}
2815
d5c21b88
IM		 2816/**
2817 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2818 *
2819 * @codec: the HDA codec
2820 * @fls_data: pointer to a fast load image
2821 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2822 * no relocation
e97249dd 2823 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2824 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2825 * @ovly: TRUE if overlay format is required
2826 *
2827 * Returns zero or a negative error code.
2828 */
01ef7dbf
IM		 2829static int dspxfr_image(struct hda_codec *codec,
2830 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2831 unsigned int reloc,
2832 unsigned int sample_rate,
2833 unsigned short channels,
01ef7dbf 2834 bool ovly)
95c6e9cb
IM		 2835{
2836 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2837 int status;
2838 unsigned short hda_format = 0;
2839 unsigned int response;
2840 unsigned char stream_id = 0;
2841 struct dma_engine *dma_engine;
2842 unsigned int dma_chan;
2843 unsigned int port_map_mask;
2844
2845 if (fls_data == NULL)
2846 return -EINVAL;
2847
2848 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2849 if (!dma_engine)
2850 return -ENOMEM;
95c6e9cb 2851
01ef7dbf
IM		 2852 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2853 if (!dma_engine->dmab) {
549e8292
TI		 2854 kfree(dma_engine);
2855 return -ENOMEM;
01ef7dbf 2856 }
95c6e9cb 2857
01ef7dbf 2858 dma_engine->codec = codec;
6194b99d 2859 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2860 dma_engine->m_converter_format = hda_format;
2861 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2862 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2863
8ae3124b 2864 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2865
2866 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2867 hda_format, &response);
2868
2869 if (status < 0) {
4e76a883 2870 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2871 goto exit;
2872 }
2873
2874 status = snd_hda_codec_load_dsp_prepare(codec,
2875 dma_engine->m_converter_format,
2876 dma_engine->buf_size,
2877 dma_engine->dmab);
2878 if (status < 0)
95c6e9cb 2879 goto exit;
01ef7dbf
IM		 2880 spec->dsp_stream_id = status;
2881
2882 if (ovly) {
2883 status = dspio_alloc_dma_chan(codec, &dma_chan);
2884 if (status < 0) {
4e76a883 2885 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2886 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2887 goto exit;
2888 }
2889 }
95c6e9cb 2890
01ef7dbf
IM		 2891 port_map_mask = 0;
2892 status = dsp_allocate_ports_format(codec, hda_format,
2893 &port_map_mask);
2894 if (status < 0) {
4e76a883 2895 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2896 goto exit;
2897 }
2898
2899 stream_id = dma_get_stream_id(dma_engine);
2900 status = codec_set_converter_stream_channel(codec,
2901 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2902 if (status < 0) {
4e76a883 2903 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2904 goto exit;
2905 }
2906
2907 while ((fls_data != NULL) && !is_last(fls_data)) {
2908 if (!is_valid(fls_data)) {
4e76a883 2909 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2910 status = -EINVAL;
2911 goto exit;
2912 }
2913 status = dspxfr_one_seg(codec, fls_data, reloc,
2914 dma_engine, dma_chan,
2915 port_map_mask, ovly);
2916 if (status < 0)
2917 break;
2918
2919 if (is_hci_prog_list_seg(fls_data))
2920 fls_data = get_next_seg_ptr(fls_data);
2921
2922 if ((fls_data != NULL) && !is_last(fls_data))
2923 fls_data = get_next_seg_ptr(fls_data);
2924 }
2925
2926 if (port_map_mask != 0)
2927 status = dsp_free_ports(codec);
2928
2929 if (status < 0)
95c6e9cb
IM		 2930 goto exit;
2931
01ef7dbf
IM		 2932 status = codec_set_converter_stream_channel(codec,
2933 WIDGET_CHIP_CTRL, 0, 0, &response);
2934
95c6e9cb 2935exit:
01ef7dbf
IM		 2936 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2937 dspio_free_dma_chan(codec, dma_chan);
2938
b3667bd7 2939 if (dma_engine->dmab->area)
01ef7dbf
IM		 2940 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2941 kfree(dma_engine->dmab);
2942 kfree(dma_engine);
2943
2944 return status;
95c6e9cb
IM		 2945}
2946
2947/*
01ef7dbf 2948 * CA0132 DSP download stuffs.
95c6e9cb 2949 */
01ef7dbf 2950static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2951{
009b8f97 2952 struct ca0132_spec *spec = codec->spec;
4e76a883 2953 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 2954 if (!spec->use_alt_functions) {
2955 /*set DSP speaker to 2.0 configuration*/
2956 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2957 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2958
009b8f97
CM		 2959 /*update write pointer*/
2960 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2961 }
01ef7dbf 2962}
95c6e9cb 2963
d5c21b88 2964/**
e60b2c7f 2965 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2966 *
2967 * @codec: the HDA codec
2968 * @fls: pointer to a fast load image
2969 * @ovly: TRUE if overlay format is required
2970 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2971 * no relocation
2972 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2973 * @router_chans: number of audio router channels to be allocated (0 means use
2974 * internal defaults; max is 32)
2975 *
e60b2c7f
TI		 2976 * Download DSP from a DSP Image Fast Load structure. This structure is a
2977 * linear, non-constant sized element array of structures, each of which
2978 * contain the count of the data to be loaded, the data itself, and the
2979 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2980 * Returns zero or a negative error code.
2981 */
01ef7dbf
IM		 2982static int dspload_image(struct hda_codec *codec,
2983 const struct dsp_image_seg *fls,
2984 bool ovly,
2985 unsigned int reloc,
2986 bool autostart,
2987 int router_chans)
2988{
2989 int status = 0;
e97249dd
IM		 2990 unsigned int sample_rate;
2991 unsigned short channels;
01ef7dbf 2992
4e76a883 2993 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2994 if (router_chans == 0) {
2995 if (!ovly)
2996 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2997 else
2998 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2999 }
95c6e9cb 3000
e97249dd
IM		 3001 sample_rate = 48000;
3002 channels = (unsigned short)router_chans;
01ef7dbf 3003
e97249dd
IM		 3004 while (channels > 16) {
3005 sample_rate *= 2;
3006 channels /= 2;
01ef7dbf
IM		 3007 }
3008
01ef7dbf 3009 do {
4e76a883 3010 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3011 if (!ovly)
3012 status = dsp_reset(codec);
3013
3014 if (status < 0)
3015 break;
3016
4e76a883 3017 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3018 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3019 ovly);
01ef7dbf
IM		 3020
3021 if (status < 0)
3022 break;
3023
4e76a883 3024 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3025 if (autostart && !ovly) {
3026 dspload_post_setup(codec);
3027 status = dsp_set_run_state(codec);
3028 }
3029
4e76a883 3030 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3031 } while (0);
3032
3033 return status;
3034}
3035
f664417e 3036#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3037static bool dspload_is_loaded(struct hda_codec *codec)
3038{
3039 unsigned int data = 0;
3040 int status = 0;
3041
3042 status = chipio_read(codec, 0x40004, &data);
3043 if ((status < 0) || (data != 1))
3044 return false;
3045
3046 return true;
3047}
f664417e
TI		 3048#else
3049#define dspload_is_loaded(codec) false
3050#endif
01ef7dbf
IM		 3051
3052static bool dspload_wait_loaded(struct hda_codec *codec)
3053{
6d67530e 3054 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3055
3056 do {
01ef7dbf 3057 if (dspload_is_loaded(codec)) {
d9684bb5 3058 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3059 return true;
3060 }
6d67530e
IM		 3061 msleep(20);
3062 } while (time_before(jiffies, timeout));
01ef7dbf 3063
d9684bb5 3064 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3065 return false;
95c6e9cb
IM		 3066}
3067
e93ac30a
CM		 3068/*
3069 * Setup GPIO for the other variants of Core3D.
3070 */
3071
3072/*
3073 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3074 * the card shows as having no GPIO pins.
3075 */
3076static void ca0132_gpio_init(struct hda_codec *codec)
3077{
3078 struct ca0132_spec *spec = codec->spec;
3079
3080 switch (spec->quirk) {
3081 case QUIRK_SBZ:
3082 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3083 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3084 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3085 break;
3086 case QUIRK_R3DI:
3087 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3088 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3089 break;
3090 }
3091
3092}
3093
3094/* Sets the GPIO for audio output. */
3095static void ca0132_gpio_setup(struct hda_codec *codec)
3096{
3097 struct ca0132_spec *spec = codec->spec;
3098
3099 switch (spec->quirk) {
3100 case QUIRK_SBZ:
3101 snd_hda_codec_write(codec, 0x01, 0,
3102 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3103 snd_hda_codec_write(codec, 0x01, 0,
3104 AC_VERB_SET_GPIO_MASK, 0x07);
3105 snd_hda_codec_write(codec, 0x01, 0,
3106 AC_VERB_SET_GPIO_DATA, 0x04);
3107 snd_hda_codec_write(codec, 0x01, 0,
3108 AC_VERB_SET_GPIO_DATA, 0x06);
3109 break;
3110 case QUIRK_R3DI:
3111 snd_hda_codec_write(codec, 0x01, 0,
3112 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3113 snd_hda_codec_write(codec, 0x01, 0,
3114 AC_VERB_SET_GPIO_MASK, 0x1F);
3115 snd_hda_codec_write(codec, 0x01, 0,
3116 AC_VERB_SET_GPIO_DATA, 0x0C);
3117 break;
3118 }
3119}
3120
7e6ed62e
CM		 3121/*
3122 * GPIO control functions for the Recon3D integrated.
3123 */
3124
3125enum r3di_gpio_bit {
3126 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3127 R3DI_MIC_SELECT_BIT = 1,
3128 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3129 R3DI_OUT_SELECT_BIT = 2,
3130 /*
3131 * I dunno what this actually does, but it stays on until the dsp
3132 * is downloaded.
3133 */
3134 R3DI_GPIO_DSP_DOWNLOADING = 3,
3135 /*
3136 * Same as above, no clue what it does, but it comes on after the dsp
3137 * is downloaded.
3138 */
3139 R3DI_GPIO_DSP_DOWNLOADED = 4
3140};
3141
3142enum r3di_mic_select {
3143 /* Set GPIO bit 1 to 0 for rear mic */
3144 R3DI_REAR_MIC = 0,
3145 /* Set GPIO bit 1 to 1 for front microphone*/
3146 R3DI_FRONT_MIC = 1
3147};
3148
3149enum r3di_out_select {
3150 /* Set GPIO bit 2 to 0 for headphone */
3151 R3DI_HEADPHONE_OUT = 0,
3152 /* Set GPIO bit 2 to 1 for speaker */
3153 R3DI_LINE_OUT = 1
3154};
3155enum r3di_dsp_status {
3156 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3157 R3DI_DSP_DOWNLOADING = 0,
3158 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3159 R3DI_DSP_DOWNLOADED = 1
3160};
3161
7cb9d94c
CM		 3162
3163static void r3di_gpio_mic_set(struct hda_codec *codec,
3164 enum r3di_mic_select cur_mic)
3165{
3166 unsigned int cur_gpio;
3167
3168 /* Get the current GPIO Data setup */
3169 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3170
3171 switch (cur_mic) {
3172 case R3DI_REAR_MIC:
3173 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3174 break;
3175 case R3DI_FRONT_MIC:
3176 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3177 break;
3178 }
3179 snd_hda_codec_write(codec, codec->core.afg, 0,
3180 AC_VERB_SET_GPIO_DATA, cur_gpio);
3181}
3182
3183static void r3di_gpio_out_set(struct hda_codec *codec,
3184 enum r3di_out_select cur_out)
3185{
3186 unsigned int cur_gpio;
3187
3188 /* Get the current GPIO Data setup */
3189 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3190
3191 switch (cur_out) {
3192 case R3DI_HEADPHONE_OUT:
3193 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3194 break;
3195 case R3DI_LINE_OUT:
3196 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3197 break;
3198 }
3199 snd_hda_codec_write(codec, codec->core.afg, 0,
3200 AC_VERB_SET_GPIO_DATA, cur_gpio);
3201}
3202
7e6ed62e
CM		 3203static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3204 enum r3di_dsp_status dsp_status)
3205{
3206 unsigned int cur_gpio;
3207
3208 /* Get the current GPIO Data setup */
3209 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3210
3211 switch (dsp_status) {
3212 case R3DI_DSP_DOWNLOADING:
3213 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3214 snd_hda_codec_write(codec, codec->core.afg, 0,
3215 AC_VERB_SET_GPIO_DATA, cur_gpio);
3216 break;
3217 case R3DI_DSP_DOWNLOADED:
3218 /* Set DOWNLOADING bit to 0. */
3219 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3220
3221 snd_hda_codec_write(codec, codec->core.afg, 0,
3222 AC_VERB_SET_GPIO_DATA, cur_gpio);
3223
3224 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3225 break;
3226 }
3227
3228 snd_hda_codec_write(codec, codec->core.afg, 0,
3229 AC_VERB_SET_GPIO_DATA, cur_gpio);
3230}
3231
825315bc
IM		 3232/*
3233 * PCM callbacks
3234 */
95c6e9cb
IM		 3235static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3236 struct hda_codec *codec,
3237 unsigned int stream_tag,
3238 unsigned int format,
3239 struct snd_pcm_substream *substream)
3240{
3241 struct ca0132_spec *spec = codec->spec;
825315bc 3242
28fba950 3243 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3244
3245 return 0;
95c6e9cb
IM		 3246}
3247
3248static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3249 struct hda_codec *codec,
3250 struct snd_pcm_substream *substream)
3251{
3252 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3253
3254 if (spec->dsp_state == DSP_DOWNLOADING)
3255 return 0;
3256
3257 /*If Playback effects are on, allow stream some time to flush
3258 *effects tail*/
3259 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3260 msleep(50);
3261
28fba950 3262 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3263
3264 return 0;
95c6e9cb
IM		 3265}
3266
e8412ca4
DR		 3267static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3268 struct hda_codec *codec,
3269 struct snd_pcm_substream *substream)
3270{
3271 struct ca0132_spec *spec = codec->spec;
3272 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3273 struct snd_pcm_runtime *runtime = substream->runtime;
3274
3275 if (spec->dsp_state != DSP_DOWNLOADED)
3276 return 0;
3277
3278 /* Add latency if playback enhancement and either effect is enabled. */
3279 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3280 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3281 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3282 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3283 }
3284
3285 /* Applying Speaker EQ adds latency as well. */
3286 if (spec->cur_out_type == SPEAKER_OUT)
3287 latency += DSP_SPEAKER_OUT_LATENCY;
3288
3289 return (latency * runtime->rate) / 1000;
3290}
3291
95c6e9cb
IM		 3292/*
3293 * Digital out
3294 */
27ebeb0b
TI		 3295static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3296 struct hda_codec *codec,
3297 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3298{
3299 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3300 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3301}
3302
27ebeb0b 3303static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3304 struct hda_codec *codec,
3305 unsigned int stream_tag,
3306 unsigned int format,
3307 struct snd_pcm_substream *substream)
3308{
3309 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3310 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3311 stream_tag, format, substream);
95c6e9cb
IM		 3312}
3313
27ebeb0b 3314static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3315 struct hda_codec *codec,
95c6e9cb
IM		 3316 struct snd_pcm_substream *substream)
3317{
3318 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3319 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3320}
3321
27ebeb0b
TI		 3322static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3323 struct hda_codec *codec,
3324 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3325{
3326 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3327 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3328}
3329
825315bc
IM		 3330/*
3331 * Analog capture
3332 */
3333static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3334 struct hda_codec *codec,
3335 unsigned int stream_tag,
3336 unsigned int format,
3337 struct snd_pcm_substream *substream)
3338{
13c12dbe 3339 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3340 stream_tag, 0, format);
825315bc
IM		 3341
3342 return 0;
3343}
3344
3345static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3346 struct hda_codec *codec,
3347 struct snd_pcm_substream *substream)
3348{
3349 struct ca0132_spec *spec = codec->spec;
3350
3351 if (spec->dsp_state == DSP_DOWNLOADING)
3352 return 0;
3353
28fba950 3354 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3355 return 0;
3356}
3357
e8412ca4
DR		 3358static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3359 struct hda_codec *codec,
3360 struct snd_pcm_substream *substream)
3361{
3362 struct ca0132_spec *spec = codec->spec;
3363 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3364 struct snd_pcm_runtime *runtime = substream->runtime;
3365
3366 if (spec->dsp_state != DSP_DOWNLOADED)
3367 return 0;
3368
3369 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3370 latency += DSP_CRYSTAL_VOICE_LATENCY;
3371
3372 return (latency * runtime->rate) / 1000;
3373}
3374
e90f29e4
IM		 3375/*
3376 * Controls stuffs.
3377 */
3378
3379/*
3380 * Mixer controls helpers.
3381 */
3382#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3383 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3384 .name = xname, \
3385 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3386 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3387 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3388 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3389 .info = ca0132_volume_info, \
3390 .get = ca0132_volume_get, \
3391 .put = ca0132_volume_put, \
3392 .tlv = { .c = ca0132_volume_tlv }, \
3393 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3394
017310fb
CM		 3395/*
3396 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3397 * volume put, which is used for setting the DSP volume. This was done because
3398 * the ca0132 functions were taking too much time and causing lag.
3399 */
3400#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3401 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3402 .name = xname, \
3403 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3404 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3405 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3406 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3407 .info = snd_hda_mixer_amp_volume_info, \
3408 .get = snd_hda_mixer_amp_volume_get, \
3409 .put = ca0132_alt_volume_put, \
3410 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3411 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3412
e90f29e4
IM		 3413#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3414 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3415 .name = xname, \
3416 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3417 .info = snd_hda_mixer_amp_switch_info, \
3418 .get = ca0132_switch_get, \
3419 .put = ca0132_switch_put, \
3420 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3421
3422/* stereo */
3423#define CA0132_CODEC_VOL(xname, nid, dir) \
3424 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3425#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3426 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3427#define CA0132_CODEC_MUTE(xname, nid, dir) \
3428 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3429
017310fb
CM		 3430/* lookup tables */
3431/*
3432 * Lookup table with decibel values for the DSP. When volume is changed in
3433 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3434 * these values have decimal points, probably because the Windows driver
3435 * actually uses floating point. We can't here, so I made a lookup table of
3436 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3437 * DAC's, and 9 is the maximum.
3438 */
3439static const unsigned int float_vol_db_lookup[] = {
34400xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
34410xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
34420xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
34430xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
34440xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
34450xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
34460xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
34470xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
34480xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
34490xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
34500xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
34510xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
34520xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
34530xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
34540xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
34550x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
34560x40C00000, 0x40E00000, 0x41000000, 0x41100000
3457};
3458
47cdf76e
CM		 3459/*
3460 * This table counts from float 0 to 1 in increments of .01, which is
3461 * useful for a few different sliders.
3462 */
3463static const unsigned int float_zero_to_one_lookup[] = {
34640x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
34650x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
34660x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
34670x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
34680x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
34690x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
34700x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
34710x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
34720x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
34730x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
34740x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
34750x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
34760x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
34770x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
34780x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
34790x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
34800x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3481};
3482
3483/*
3484 * This table counts from float 10 to 1000, which is the range of the x-bass
3485 * crossover slider in Windows.
3486 */
3487static const unsigned int float_xbass_xover_lookup[] = {
34880x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
34890x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
34900x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
34910x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
34920x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
34930x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
34940x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
34950x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
34960x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
34970x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
34980x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
34990x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
35000x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
35010x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
35020x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
35030x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
35040x44728000, 0x44750000, 0x44778000, 0x447A0000
3505};
3506
4091fb95 3507/* The following are for tuning of products */
44f0c978
IM		 3508#ifdef ENABLE_TUNING_CONTROLS
3509
3510static unsigned int voice_focus_vals_lookup[] = {
35110x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
35120x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
35130x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
35140x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
35150x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
35160x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
35170x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
35180x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
35190x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
35200x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
35210x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
35220x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
35230x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
35240x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
35250x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
35260x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
35270x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
35280x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
35290x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
35300x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
35310x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
35320x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
35330x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
35340x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
35350x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
35360x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
35370x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3538};
3539
3540static unsigned int mic_svm_vals_lookup[] = {
35410x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
35420x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
35430x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
35440x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
35450x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
35460x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
35470x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
35480x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
35490x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
35500x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
35510x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
35520x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
35530x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
35540x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
35550x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
35560x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
35570x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3558};
3559
3560static unsigned int equalizer_vals_lookup[] = {
35610xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
35620xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
35630xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
35640xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
35650x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
35660x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
35670x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
35680x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
35690x41C00000
3570};
3571
3572static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3573 unsigned int *lookup, int idx)
3574{
3575 int i = 0;
3576
3577 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3578 if (nid == ca0132_tuning_ctls[i].nid)
3579 break;
3580
3581 snd_hda_power_up(codec);
447fd8e9 3582 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3583 ca0132_tuning_ctls[i].req,
3584 &(lookup[idx]), sizeof(unsigned int));
3585 snd_hda_power_down(codec);
3586
3587 return 1;
3588}
3589
3590static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3591 struct snd_ctl_elem_value *ucontrol)
3592{
3593 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3594 struct ca0132_spec *spec = codec->spec;
3595 hda_nid_t nid = get_amp_nid(kcontrol);
3596 long *valp = ucontrol->value.integer.value;
3597 int idx = nid - TUNING_CTL_START_NID;
3598
3599 *valp = spec->cur_ctl_vals[idx];
3600 return 0;
3601}
3602
3603static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3604 struct snd_ctl_elem_info *uinfo)
3605{
3606 int chs = get_amp_channels(kcontrol);
3607 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3608 uinfo->count = chs == 3 ? 2 : 1;
3609 uinfo->value.integer.min = 20;
3610 uinfo->value.integer.max = 180;
3611 uinfo->value.integer.step = 1;
3612
3613 return 0;
3614}
3615
3616static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3617 struct snd_ctl_elem_value *ucontrol)
3618{
3619 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3620 struct ca0132_spec *spec = codec->spec;
3621 hda_nid_t nid = get_amp_nid(kcontrol);
3622 long *valp = ucontrol->value.integer.value;
3623 int idx;
3624
3625 idx = nid - TUNING_CTL_START_NID;
3626 /* any change? */
3627 if (spec->cur_ctl_vals[idx] == *valp)
3628 return 0;
3629
3630 spec->cur_ctl_vals[idx] = *valp;
3631
3632 idx = *valp - 20;
3633 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3634
3635 return 1;
3636}
3637
3638static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3639 struct snd_ctl_elem_info *uinfo)
3640{
3641 int chs = get_amp_channels(kcontrol);
3642 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3643 uinfo->count = chs == 3 ? 2 : 1;
3644 uinfo->value.integer.min = 0;
3645 uinfo->value.integer.max = 100;
3646 uinfo->value.integer.step = 1;
3647
3648 return 0;
3649}
3650
3651static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3652 struct snd_ctl_elem_value *ucontrol)
3653{
3654 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3655 struct ca0132_spec *spec = codec->spec;
3656 hda_nid_t nid = get_amp_nid(kcontrol);
3657 long *valp = ucontrol->value.integer.value;
3658 int idx;
3659
3660 idx = nid - TUNING_CTL_START_NID;
3661 /* any change? */
3662 if (spec->cur_ctl_vals[idx] == *valp)
3663 return 0;
3664
3665 spec->cur_ctl_vals[idx] = *valp;
3666
3667 idx = *valp;
3668 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3669
3670 return 0;
3671}
3672
3673static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3674 struct snd_ctl_elem_info *uinfo)
3675{
3676 int chs = get_amp_channels(kcontrol);
3677 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3678 uinfo->count = chs == 3 ? 2 : 1;
3679 uinfo->value.integer.min = 0;
3680 uinfo->value.integer.max = 48;
3681 uinfo->value.integer.step = 1;
3682
3683 return 0;
3684}
3685
3686static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3687 struct snd_ctl_elem_value *ucontrol)
3688{
3689 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3690 struct ca0132_spec *spec = codec->spec;
3691 hda_nid_t nid = get_amp_nid(kcontrol);
3692 long *valp = ucontrol->value.integer.value;
3693 int idx;
3694
3695 idx = nid - TUNING_CTL_START_NID;
3696 /* any change? */
3697 if (spec->cur_ctl_vals[idx] == *valp)
3698 return 0;
3699
3700 spec->cur_ctl_vals[idx] = *valp;
3701
3702 idx = *valp;
3703 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3704
3705 return 1;
3706}
3707
8e142e9e
TS		 3708static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3709static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3710
3711static int add_tuning_control(struct hda_codec *codec,
3712 hda_nid_t pnid, hda_nid_t nid,
3713 const char *name, int dir)
3714{
975cc02a 3715 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3716 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3717 struct snd_kcontrol_new knew =
3718 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3719
3720 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3721 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3722 knew.tlv.c = 0;
3723 knew.tlv.p = 0;
3724 switch (pnid) {
3725 case VOICE_FOCUS:
3726 knew.info = voice_focus_ctl_info;
3727 knew.get = tuning_ctl_get;
3728 knew.put = voice_focus_ctl_put;
3729 knew.tlv.p = voice_focus_db_scale;
3730 break;
3731 case MIC_SVM:
3732 knew.info = mic_svm_ctl_info;
3733 knew.get = tuning_ctl_get;
3734 knew.put = mic_svm_ctl_put;
3735 break;
3736 case EQUALIZER:
3737 knew.info = equalizer_ctl_info;
3738 knew.get = tuning_ctl_get;
3739 knew.put = equalizer_ctl_put;
3740 knew.tlv.p = eq_db_scale;
3741 break;
3742 default:
3743 return 0;
3744 }
3745 knew.private_value =
3746 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3747 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3748 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3749}
3750
3751static int add_tuning_ctls(struct hda_codec *codec)
3752{
3753 int i;
3754 int err;
3755
3756 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3757 err = add_tuning_control(codec,
3758 ca0132_tuning_ctls[i].parent_nid,
3759 ca0132_tuning_ctls[i].nid,
3760 ca0132_tuning_ctls[i].name,
3761 ca0132_tuning_ctls[i].direct);
3762 if (err < 0)
3763 return err;
3764 }
3765
3766 return 0;
3767}
3768
3769static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3770{
3771 struct ca0132_spec *spec = codec->spec;
3772 int i;
3773
3774 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3775 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3776 /* SVM level defaults to 0.74. */
3777 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3778
3779 /* EQ defaults to 0dB. */
3780 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3781 spec->cur_ctl_vals[i] = 24;
3782}
3783#endif /*ENABLE_TUNING_CONTROLS*/
3784
5aaca44d
IM		 3785/*
3786 * Select the active output.
3787 * If autodetect is enabled, output will be selected based on jack detection.
3788 * If jack inserted, headphone will be selected, else built-in speakers
3789 * If autodetect is disabled, output will be selected based on selection.
3790 */
3791static int ca0132_select_out(struct hda_codec *codec)
3792{
3793 struct ca0132_spec *spec = codec->spec;
3794 unsigned int pin_ctl;
3795 int jack_present;
3796 int auto_jack;
3797 unsigned int tmp;
3798 int err;
3799
4e76a883 3800 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3801
664c7155 3802 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3803
3804 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3805
3806 if (auto_jack)
fe14f39e 3807 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3808 else
3809 jack_present =
3810 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3811
3812 if (jack_present)
3813 spec->cur_out_type = HEADPHONE_OUT;
3814 else
3815 spec->cur_out_type = SPEAKER_OUT;
3816
3817 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3818 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3819 /*speaker out config*/
3820 tmp = FLOAT_ONE;
3821 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3822 if (err < 0)
3823 goto exit;
3824 /*enable speaker EQ*/
3825 tmp = FLOAT_ONE;
3826 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3827 if (err < 0)
3828 goto exit;
3829
3830 /* Setup EAPD */
3831 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3832 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3833 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3834 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3835 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3836 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3837 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3838 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3839
3840 /* disable headphone node */
3841 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3842 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3843 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3844 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3845 /* enable speaker node */
3846 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 3847 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3848 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3849 pin_ctl | PIN_OUT);
5aaca44d 3850 } else {
4e76a883 3851 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3852 /*headphone out config*/
3853 tmp = FLOAT_ZERO;
3854 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3855 if (err < 0)
3856 goto exit;
3857 /*disable speaker EQ*/
3858 tmp = FLOAT_ZERO;
3859 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3860 if (err < 0)
3861 goto exit;
3862
3863 /* Setup EAPD */
3864 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3865 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3866 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3867 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3868 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3869 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3870 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3871 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3872
3873 /* disable speaker*/
3874 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3875 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3876 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3877 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3878 /* enable headphone*/
3879 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3880 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3881 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3882 pin_ctl | PIN_HP);
5aaca44d
IM		 3883 }
3884
3885exit:
664c7155 3886 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3887
3888 return err < 0 ? err : 0;
3889}
3890
7cb9d94c
CM		 3891/*
3892 * This function behaves similarly to the ca0132_select_out funciton above,
3893 * except with a few differences. It adds the ability to select the current
3894 * output with an enumerated control "output source" if the auto detect
3895 * mute switch is set to off. If the auto detect mute switch is enabled, it
3896 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3897 * It also adds the ability to auto-detect the front headphone port. The only
3898 * way to select surround is to disable auto detect, and set Surround with the
3899 * enumerated control.
3900 */
3901static int ca0132_alt_select_out(struct hda_codec *codec)
3902{
3903 struct ca0132_spec *spec = codec->spec;
3904 unsigned int pin_ctl;
3905 int jack_present;
3906 int auto_jack;
3907 unsigned int i;
3908 unsigned int tmp;
3909 int err;
3910 /* Default Headphone is rear headphone */
3911 hda_nid_t headphone_nid = spec->out_pins[1];
3912
3913 codec_dbg(codec, "%s\n", __func__);
3914
3915 snd_hda_power_up_pm(codec);
3916
3917 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3918
3919 /*
3920 * If headphone rear or front is plugged in, set to headphone.
3921 * If neither is plugged in, set to rear line out. Only if
3922 * hp/speaker auto detect is enabled.
3923 */
3924 if (auto_jack) {
3925 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3926 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3927
3928 if (jack_present)
3929 spec->cur_out_type = HEADPHONE_OUT;
3930 else
3931 spec->cur_out_type = SPEAKER_OUT;
3932 } else
3933 spec->cur_out_type = spec->out_enum_val;
3934
3935 /* Begin DSP output switch */
3936 tmp = FLOAT_ONE;
3937 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3938 if (err < 0)
3939 goto exit;
3940
3941 switch (spec->cur_out_type) {
3942 case SPEAKER_OUT:
3943 codec_dbg(codec, "%s speaker\n", __func__);
3944 /*speaker out config*/
3945 switch (spec->quirk) {
3946 case QUIRK_SBZ:
3947 writew(0x0007, spec->mem_base + 0x320);
3948 writew(0x0104, spec->mem_base + 0x320);
3949 writew(0x0101, spec->mem_base + 0x320);
3950 chipio_set_control_param(codec, 0x0D, 0x18);
3951 break;
3952 case QUIRK_R3DI:
3953 chipio_set_control_param(codec, 0x0D, 0x24);
3954 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3955 break;
3956 }
3957
3958 /* disable headphone node */
3959 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3960 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3961 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3962 pin_ctl & ~PIN_HP);
3963 /* enable line-out node */
3964 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3965 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3966 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3967 pin_ctl | PIN_OUT);
3968 /* Enable EAPD */
3969 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3970 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
3971
3972 /* If PlayEnhancement is enabled, set different source */
3973 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3974 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
3975 else
3976 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
3977 break;
3978 case HEADPHONE_OUT:
3979 codec_dbg(codec, "%s hp\n", __func__);
3980 /* Headphone out config*/
3981 switch (spec->quirk) {
3982 case QUIRK_SBZ:
3983 writew(0x0107, spec->mem_base + 0x320);
3984 writew(0x0104, spec->mem_base + 0x320);
3985 writew(0x0001, spec->mem_base + 0x320);
3986 chipio_set_control_param(codec, 0x0D, 0x12);
3987 break;
3988 case QUIRK_R3DI:
3989 chipio_set_control_param(codec, 0x0D, 0x21);
3990 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
3991 break;
3992 }
3993
3994 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3995 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3996
3997 /* disable speaker*/
3998 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3999 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4000 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4001 pin_ctl & ~PIN_HP);
4002
4003 /* enable headphone, either front or rear */
4004
4005 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4006 headphone_nid = spec->out_pins[2];
4007 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4008 headphone_nid = spec->out_pins[1];
4009
4010 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4011 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4012 snd_hda_set_pin_ctl(codec, headphone_nid,
4013 pin_ctl | PIN_HP);
4014
4015 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4016 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4017 else
4018 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4019 break;
4020 case SURROUND_OUT:
4021 codec_dbg(codec, "%s surround\n", __func__);
4022 /* Surround out config*/
4023 switch (spec->quirk) {
4024 case QUIRK_SBZ:
4025 writew(0x0007, spec->mem_base + 0x320);
4026 writew(0x0104, spec->mem_base + 0x320);
4027 writew(0x0101, spec->mem_base + 0x320);
4028 chipio_set_control_param(codec, 0x0D, 0x18);
4029 break;
4030 case QUIRK_R3DI:
4031 chipio_set_control_param(codec, 0x0D, 0x24);
4032 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4033 break;
4034 }
4035 /* enable line out node */
4036 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4037 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4038 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4039 pin_ctl | PIN_OUT);
4040 /* Disable headphone out */
4041 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4042 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4043 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4044 pin_ctl & ~PIN_HP);
4045 /* Enable EAPD on line out */
4046 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4047 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4048 /* enable center/lfe out node */
4049 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4050 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4051 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4052 pin_ctl | PIN_OUT);
4053 /* Now set rear surround node as out. */
4054 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4055 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4056 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4057 pin_ctl | PIN_OUT);
4058
4059 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4060 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4061 else
4062 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4063 break;
4064 }
4065
4066 /* run through the output dsp commands for line-out */
4067 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4068 err = dspio_set_uint_param(codec,
4069 alt_out_presets[spec->cur_out_type].mids[i],
4070 alt_out_presets[spec->cur_out_type].reqs[i],
4071 alt_out_presets[spec->cur_out_type].vals[i]);
4072
4073 if (err < 0)
4074 goto exit;
4075 }
4076
4077exit:
4078 snd_hda_power_down_pm(codec);
4079
4080 return err < 0 ? err : 0;
4081}
4082
993884f6
CCC		 4083static void ca0132_unsol_hp_delayed(struct work_struct *work)
4084{
4085 struct ca0132_spec *spec = container_of(
4086 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4087 struct hda_jack_tbl *jack;
4088
7cb9d94c
CM		 4089 if (spec->use_alt_functions)
4090 ca0132_alt_select_out(spec->codec);
4091 else
4092 ca0132_select_out(spec->codec);
4093
d5c016b5 4094 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4095 if (jack) {
4096 jack->block_report = 0;
4097 snd_hda_jack_report_sync(spec->codec);
4098 }
993884f6
CCC		 4099}
4100
5aaca44d
IM		 4101static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4102static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4103static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
e0026d03
CM		 4104static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4105static int stop_mic1(struct hda_codec *codec);
4106static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4107static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4108
4109/*
4110 * Select the active VIP source
4111 */
4112static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4113{
4114 struct ca0132_spec *spec = codec->spec;
4115 unsigned int tmp;
4116
e8f1bd5d 4117 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4118 return 0;
4119
4120 /* if CrystalVoice if off, vipsource should be 0 */
4121 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4122 (val == 0)) {
4123 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4124 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4125 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4126 if (spec->cur_mic_type == DIGITAL_MIC)
4127 tmp = FLOAT_TWO;
4128 else
4129 tmp = FLOAT_ONE;
4130 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4131 tmp = FLOAT_ZERO;
4132 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4133 } else {
4134 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4135 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4136 if (spec->cur_mic_type == DIGITAL_MIC)
4137 tmp = FLOAT_TWO;
4138 else
4139 tmp = FLOAT_ONE;
4140 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4141 tmp = FLOAT_ONE;
4142 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4143 msleep(20);
4144 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4145 }
4146
4147 return 1;
4148}
4149
e0026d03
CM		 4150static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4151{
4152 struct ca0132_spec *spec = codec->spec;
4153 unsigned int tmp;
4154
4155 if (spec->dsp_state != DSP_DOWNLOADED)
4156 return 0;
4157
4158 codec_dbg(codec, "%s\n", __func__);
4159
4160 chipio_set_stream_control(codec, 0x03, 0);
4161 chipio_set_stream_control(codec, 0x04, 0);
4162
4163 /* if CrystalVoice is off, vipsource should be 0 */
4164 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4165 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4166 codec_dbg(codec, "%s: off.", __func__);
4167 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4168
4169 tmp = FLOAT_ZERO;
4170 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4171
4172 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4173 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4174 if (spec->quirk == QUIRK_R3DI)
4175 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4176
4177
4178 if (spec->in_enum_val == REAR_LINE_IN)
4179 tmp = FLOAT_ZERO;
4180 else {
4181 if (spec->quirk == QUIRK_SBZ)
4182 tmp = FLOAT_THREE;
4183 else
4184 tmp = FLOAT_ONE;
4185 }
4186
4187 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4188
4189 } else {
4190 codec_dbg(codec, "%s: on.", __func__);
4191 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4192 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4193 if (spec->quirk == QUIRK_R3DI)
4194 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4195
4196 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4197 tmp = FLOAT_TWO;
4198 else
4199 tmp = FLOAT_ONE;
4200 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4201
4202 tmp = FLOAT_ONE;
4203 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4204
4205 msleep(20);
4206 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4207 }
4208
4209 chipio_set_stream_control(codec, 0x03, 1);
4210 chipio_set_stream_control(codec, 0x04, 1);
4211
4212 return 1;
4213}
4214
5aaca44d
IM		 4215/*
4216 * Select the active microphone.
4217 * If autodetect is enabled, mic will be selected based on jack detection.
4218 * If jack inserted, ext.mic will be selected, else built-in mic
4219 * If autodetect is disabled, mic will be selected based on selection.
4220 */
4221static int ca0132_select_mic(struct hda_codec *codec)
4222{
4223 struct ca0132_spec *spec = codec->spec;
4224 int jack_present;
4225 int auto_jack;
4226
4e76a883 4227 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4228
664c7155 4229 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4230
4231 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4232
4233 if (auto_jack)
fe14f39e 4234 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4235 else
4236 jack_present =
4237 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4238
4239 if (jack_present)
4240 spec->cur_mic_type = LINE_MIC_IN;
4241 else
4242 spec->cur_mic_type = DIGITAL_MIC;
4243
4244 if (spec->cur_mic_type == DIGITAL_MIC) {
4245 /* enable digital Mic */
4246 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4247 ca0132_set_dmic(codec, 1);
4248 ca0132_mic_boost_set(codec, 0);
4249 /* set voice focus */
4250 ca0132_effects_set(codec, VOICE_FOCUS,
4251 spec->effects_switch
4252 [VOICE_FOCUS - EFFECT_START_NID]);
4253 } else {
4254 /* disable digital Mic */
4255 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4256 ca0132_set_dmic(codec, 0);
4257 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4258 /* disable voice focus */
4259 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4260 }
4261
664c7155 4262 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4263
4264 return 0;
4265}
4266
7cb9d94c
CM		 4267/*
4268 * Select the active input.
4269 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4270 * The front mic has no jack-detection, so the only way to switch to it
4271 * is to do it manually in alsamixer.
4272 */
4273static int ca0132_alt_select_in(struct hda_codec *codec)
4274{
4275 struct ca0132_spec *spec = codec->spec;
4276 unsigned int tmp;
4277
4278 codec_dbg(codec, "%s\n", __func__);
4279
4280 snd_hda_power_up_pm(codec);
4281
4282 chipio_set_stream_control(codec, 0x03, 0);
4283 chipio_set_stream_control(codec, 0x04, 0);
4284
4285 spec->cur_mic_type = spec->in_enum_val;
4286
4287 switch (spec->cur_mic_type) {
4288 case REAR_MIC:
4289 switch (spec->quirk) {
4290 case QUIRK_SBZ:
4291 writew(0x0000, spec->mem_base + 0x320);
4292 tmp = FLOAT_THREE;
4293 break;
4294 case QUIRK_R3DI:
4295 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4296 tmp = FLOAT_ONE;
4297 break;
4298 default:
4299 tmp = FLOAT_ONE;
4300 break;
4301 }
4302
4303 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4304 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4305 if (spec->quirk == QUIRK_R3DI)
4306 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4307
4308 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4309
4310 chipio_set_stream_control(codec, 0x03, 1);
4311 chipio_set_stream_control(codec, 0x04, 1);
4312
4313 if (spec->quirk == QUIRK_SBZ) {
4314 chipio_write(codec, 0x18B098, 0x0000000C);
4315 chipio_write(codec, 0x18B09C, 0x0000000C);
4316 }
47cdf76e 4317 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4318 break;
4319 case REAR_LINE_IN:
4320 ca0132_mic_boost_set(codec, 0);
4321 switch (spec->quirk) {
4322 case QUIRK_SBZ:
4323 writew(0x0000, spec->mem_base + 0x320);
4324 break;
4325 case QUIRK_R3DI:
4326 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4327 break;
4328 }
4329
4330 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4331 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4332 if (spec->quirk == QUIRK_R3DI)
4333 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4334
4335 tmp = FLOAT_ZERO;
4336 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4337
4338 if (spec->quirk == QUIRK_SBZ) {
4339 chipio_write(codec, 0x18B098, 0x00000000);
4340 chipio_write(codec, 0x18B09C, 0x00000000);
4341 }
4342
4343 chipio_set_stream_control(codec, 0x03, 1);
4344 chipio_set_stream_control(codec, 0x04, 1);
4345 break;
4346 case FRONT_MIC:
4347 switch (spec->quirk) {
4348 case QUIRK_SBZ:
4349 writew(0x0100, spec->mem_base + 0x320);
4350 writew(0x0005, spec->mem_base + 0x320);
4351 tmp = FLOAT_THREE;
4352 break;
4353 case QUIRK_R3DI:
4354 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4355 tmp = FLOAT_ONE;
4356 break;
4357 default:
4358 tmp = FLOAT_ONE;
4359 break;
4360 }
4361
4362 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4363 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4364 if (spec->quirk == QUIRK_R3DI)
4365 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4366
4367 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4368
4369 chipio_set_stream_control(codec, 0x03, 1);
4370 chipio_set_stream_control(codec, 0x04, 1);
4371
4372 if (spec->quirk == QUIRK_SBZ) {
4373 chipio_write(codec, 0x18B098, 0x0000000C);
4374 chipio_write(codec, 0x18B09C, 0x000000CC);
4375 }
47cdf76e 4376 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4377 break;
4378 }
e0026d03 4379 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4380
4381 snd_hda_power_down_pm(codec);
4382 return 0;
4383
4384}
4385
a7e76271
IM		 4386/*
4387 * Check if VNODE settings take effect immediately.
4388 */
4389static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4390 hda_nid_t vnid,
4391 hda_nid_t *shared_nid)
4392{
4393 struct ca0132_spec *spec = codec->spec;
4394 hda_nid_t nid;
a7e76271
IM		 4395
4396 switch (vnid) {
4397 case VNID_SPK:
4398 nid = spec->shared_out_nid;
a7e76271
IM		 4399 break;
4400 case VNID_MIC:
4401 nid = spec->shared_mic_nid;
a7e76271
IM		 4402 break;
4403 default:
9a0869f4 4404 return false;
a7e76271
IM		 4405 }
4406
9a0869f4 4407 if (shared_nid)
a7e76271
IM		 4408 *shared_nid = nid;
4409
9a0869f4 4410 return true;
a7e76271
IM		 4411}
4412
4413/*
4414* The following functions are control change helpers.
4415* They return 0 if no changed. Return 1 if changed.
4416*/
4417static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4418{
4419 struct ca0132_spec *spec = codec->spec;
4420 unsigned int tmp;
4421
4422 /* based on CrystalVoice state to enable VoiceFX. */
4423 if (enable) {
4424 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4425 FLOAT_ONE : FLOAT_ZERO;
4426 } else {
4427 tmp = FLOAT_ZERO;
4428 }
4429
4430 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4431 ca0132_voicefx.reqs[0], tmp);
4432
4433 return 1;
4434}
4435
5aaca44d
IM		 4436/*
4437 * Set the effects parameters
4438 */
4439static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4440{
4441 struct ca0132_spec *spec = codec->spec;
009b8f97 4442 unsigned int on, tmp;
5aaca44d
IM		 4443 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4444 int err = 0;
4445 int idx = nid - EFFECT_START_NID;
4446
4447 if ((idx < 0) || (idx >= num_fx))
4448 return 0; /* no changed */
4449
4450 /* for out effect, qualify with PE */
4451 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4452 /* if PE if off, turn off out effects. */
4453 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4454 val = 0;
4455 }
4456
4457 /* for in effect, qualify with CrystalVoice */
4458 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4459 /* if CrystalVoice if off, turn off in effects. */
4460 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4461 val = 0;
4462
4463 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4464 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4465 val = 0;
009b8f97
CM		 4466
4467 /* If Voice Focus on SBZ, set to two channel. */
7cb9d94c
CM		 4468 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4469 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4470 if (spec->effects_switch[CRYSTAL_VOICE -
4471 EFFECT_START_NID]) {
4472
4473 if (spec->effects_switch[VOICE_FOCUS -
4474 EFFECT_START_NID]) {
4475 tmp = FLOAT_TWO;
4476 val = 1;
4477 } else
4478 tmp = FLOAT_ONE;
4479
4480 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4481 }
4482 }
4483 /*
4484 * For SBZ noise reduction, there's an extra command
4485 * to module ID 0x47. No clue why.
4486 */
7cb9d94c
CM		 4487 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4488 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4489 if (spec->effects_switch[CRYSTAL_VOICE -
4490 EFFECT_START_NID]) {
4491 if (spec->effects_switch[NOISE_REDUCTION -
4492 EFFECT_START_NID])
4493 tmp = FLOAT_ONE;
4494 else
4495 tmp = FLOAT_ZERO;
4496 } else
4497 tmp = FLOAT_ZERO;
4498
4499 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4500 }
7cb9d94c
CM		 4501
4502 /* If rear line in disable effects. */
4503 if (spec->use_alt_functions &&
4504 spec->in_enum_val == REAR_LINE_IN)
4505 val = 0;
5aaca44d
IM		 4506 }
4507
4e76a883 4508 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4509 nid, val);
4510
4511 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4512 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4513 ca0132_effects[idx].reqs[0], on);
4514
4515 if (err < 0)
4516 return 0; /* no changed */
4517
4518 return 1;
4519}
4520
a7e76271
IM		 4521/*
4522 * Turn on/off Playback Enhancements
4523 */
4524static int ca0132_pe_switch_set(struct hda_codec *codec)
4525{
4526 struct ca0132_spec *spec = codec->spec;
4527 hda_nid_t nid;
4528 int i, ret = 0;
4529
4e76a883 4530 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4531 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4532
7cb9d94c
CM		 4533 if (spec->use_alt_functions)
4534 ca0132_alt_select_out(codec);
4535
a7e76271
IM		 4536 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4537 nid = OUT_EFFECT_START_NID;
4538 /* PE affects all out effects */
4539 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4540 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4541
4542 return ret;
4543}
4544
5aaca44d
IM		 4545/* Check if Mic1 is streaming, if so, stop streaming */
4546static int stop_mic1(struct hda_codec *codec)
4547{
4548 struct ca0132_spec *spec = codec->spec;
4549 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4550 AC_VERB_GET_CONV, 0);
4551 if (oldval != 0)
4552 snd_hda_codec_write(codec, spec->adcs[0], 0,
4553 AC_VERB_SET_CHANNEL_STREAMID,
4554 0);
4555 return oldval;
4556}
4557
4558/* Resume Mic1 streaming if it was stopped. */
4559static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4560{
4561 struct ca0132_spec *spec = codec->spec;
4562 /* Restore the previous stream and channel */
4563 if (oldval != 0)
4564 snd_hda_codec_write(codec, spec->adcs[0], 0,
4565 AC_VERB_SET_CHANNEL_STREAMID,
4566 oldval);
4567}
4568
4569/*
a7e76271 4570 * Turn on/off CrystalVoice
5aaca44d 4571 */
a7e76271
IM		 4572static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4573{
4574 struct ca0132_spec *spec = codec->spec;
4575 hda_nid_t nid;
4576 int i, ret = 0;
4577 unsigned int oldval;
4578
4e76a883 4579 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4580 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4581
4582 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4583 nid = IN_EFFECT_START_NID;
4584 /* CrystalVoice affects all in effects */
4585 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4586 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4587
4588 /* including VoiceFX */
4589 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4590
4591 /* set correct vipsource */
4592 oldval = stop_mic1(codec);
e0026d03
CM		 4593 if (spec->use_alt_functions)
4594 ret |= ca0132_alt_set_vipsource(codec, 1);
4595 else
4596 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 4597 resume_mic1(codec, oldval);
4598 return ret;
4599}
4600
5aaca44d
IM		 4601static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4602{
4603 struct ca0132_spec *spec = codec->spec;
4604 int ret = 0;
4605
4606 if (val) /* on */
4607 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4608 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4609 else /* off */
4610 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4611 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4612
4613 return ret;
4614}
4615
47cdf76e
CM		 4616static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4617{
4618 struct ca0132_spec *spec = codec->spec;
4619 int ret = 0;
4620
4621 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4622 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4623 return ret;
4624}
4625
a7e76271
IM		 4626static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4627 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 4628{
a7e76271
IM		 4629 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4630 hda_nid_t nid = get_amp_nid(kcontrol);
4631 hda_nid_t shared_nid = 0;
4632 bool effective;
4633 int ret = 0;
95c6e9cb 4634 struct ca0132_spec *spec = codec->spec;
a7e76271 4635 int auto_jack;
95c6e9cb 4636
a7e76271
IM		 4637 if (nid == VNID_HP_SEL) {
4638 auto_jack =
4639 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 4640 if (!auto_jack) {
4641 if (spec->use_alt_functions)
4642 ca0132_alt_select_out(codec);
4643 else
4644 ca0132_select_out(codec);
4645 }
a7e76271
IM		 4646 return 1;
4647 }
95c6e9cb 4648
a7e76271
IM		 4649 if (nid == VNID_AMIC1_SEL) {
4650 auto_jack =
4651 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4652 if (!auto_jack)
4653 ca0132_select_mic(codec);
4654 return 1;
4655 }
95c6e9cb 4656
a7e76271 4657 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 4658 if (spec->use_alt_functions)
4659 ca0132_alt_select_out(codec);
4660 else
4661 ca0132_select_out(codec);
a7e76271
IM		 4662 return 1;
4663 }
95c6e9cb 4664
a7e76271
IM		 4665 if (nid == VNID_AMIC1_ASEL) {
4666 ca0132_select_mic(codec);
4667 return 1;
95c6e9cb 4668 }
a7e76271
IM		 4669
4670 /* if effective conditions, then update hw immediately. */
4671 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4672 if (effective) {
4673 int dir = get_amp_direction(kcontrol);
4674 int ch = get_amp_channels(kcontrol);
4675 unsigned long pval;
4676
4677 mutex_lock(&codec->control_mutex);
4678 pval = kcontrol->private_value;
4679 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4680 0, dir);
4681 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4682 kcontrol->private_value = pval;
4683 mutex_unlock(&codec->control_mutex);
95c6e9cb 4684 }
95c6e9cb 4685
a7e76271 4686 return ret;
95c6e9cb 4687}
a7e76271 4688/* End of control change helpers. */
47cdf76e
CM		 4689/*
4690 * Below I've added controls to mess with the effect levels, I've only enabled
4691 * them on the Sound Blaster Z, but they would probably also work on the
4692 * Chromebook. I figured they were probably tuned specifically for it, and left
4693 * out for a reason.
4694 */
4695
4696/* Sets DSP effect level from the sliders above the controls */
4697static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4698 const unsigned int *lookup, int idx)
4699{
4700 int i = 0;
4701 unsigned int y;
4702 /*
4703 * For X_BASS, req 2 is actually crossover freq instead of
4704 * effect level
4705 */
4706 if (nid == X_BASS)
4707 y = 2;
4708 else
4709 y = 1;
4710
4711 snd_hda_power_up(codec);
4712 if (nid == XBASS_XOVER) {
4713 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4714 if (ca0132_effects[i].nid == X_BASS)
4715 break;
4716
4717 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4718 ca0132_effects[i].reqs[1],
4719 &(lookup[idx - 1]), sizeof(unsigned int));
4720 } else {
4721 /* Find the actual effect structure */
4722 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4723 if (nid == ca0132_effects[i].nid)
4724 break;
4725
4726 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4727 ca0132_effects[i].reqs[y],
4728 &(lookup[idx]), sizeof(unsigned int));
4729 }
4730
4731 snd_hda_power_down(codec);
4732
4733 return 0;
4734}
4735
4736static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4737 struct snd_ctl_elem_value *ucontrol)
4738{
4739 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4740 struct ca0132_spec *spec = codec->spec;
4741 long *valp = ucontrol->value.integer.value;
4742
4743 *valp = spec->xbass_xover_freq;
4744 return 0;
4745}
4746
4747static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4748 struct snd_ctl_elem_value *ucontrol)
4749{
4750 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4751 struct ca0132_spec *spec = codec->spec;
4752 hda_nid_t nid = get_amp_nid(kcontrol);
4753 long *valp = ucontrol->value.integer.value;
4754 int idx = nid - OUT_EFFECT_START_NID;
4755
4756 *valp = spec->fx_ctl_val[idx];
4757 return 0;
4758}
4759
4760/*
4761 * The X-bass crossover starts at 10hz, so the min is 1. The
4762 * frequency is set in multiples of 10.
4763 */
4764static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4765 struct snd_ctl_elem_info *uinfo)
4766{
4767 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4768 uinfo->count = 1;
4769 uinfo->value.integer.min = 1;
4770 uinfo->value.integer.max = 100;
4771 uinfo->value.integer.step = 1;
4772
4773 return 0;
4774}
4775
4776static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4777 struct snd_ctl_elem_info *uinfo)
4778{
4779 int chs = get_amp_channels(kcontrol);
4780
4781 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4782 uinfo->count = chs == 3 ? 2 : 1;
4783 uinfo->value.integer.min = 0;
4784 uinfo->value.integer.max = 100;
4785 uinfo->value.integer.step = 1;
4786
4787 return 0;
4788}
4789
4790static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4791 struct snd_ctl_elem_value *ucontrol)
4792{
4793 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4794 struct ca0132_spec *spec = codec->spec;
4795 hda_nid_t nid = get_amp_nid(kcontrol);
4796 long *valp = ucontrol->value.integer.value;
4797 int idx;
4798
4799 /* any change? */
4800 if (spec->xbass_xover_freq == *valp)
4801 return 0;
4802
4803 spec->xbass_xover_freq = *valp;
4804
4805 idx = *valp;
4806 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4807
4808 return 0;
4809}
4810
4811static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4812 struct snd_ctl_elem_value *ucontrol)
4813{
4814 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4815 struct ca0132_spec *spec = codec->spec;
4816 hda_nid_t nid = get_amp_nid(kcontrol);
4817 long *valp = ucontrol->value.integer.value;
4818 int idx;
4819
4820 idx = nid - EFFECT_START_NID;
4821 /* any change? */
4822 if (spec->fx_ctl_val[idx] == *valp)
4823 return 0;
4824
4825 spec->fx_ctl_val[idx] = *valp;
4826
4827 idx = *valp;
4828 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4829
4830 return 0;
4831}
4832
4833
4834/*
4835 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4836 * only has off or full 30 dB, and didn't like making a volume slider that has
4837 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4838 */
4839#define MIC_BOOST_NUM_OF_STEPS 4
4840#define MIC_BOOST_ENUM_MAX_STRLEN 10
4841
4842static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4843 struct snd_ctl_elem_info *uinfo)
4844{
4845 char *sfx = "dB";
4846 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4847
4848 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4849 uinfo->count = 1;
4850 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
4851 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
4852 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
4853 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
4854 strcpy(uinfo->value.enumerated.name, namestr);
4855 return 0;
4856}
4857
4858static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
4859 struct snd_ctl_elem_value *ucontrol)
4860{
4861 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4862 struct ca0132_spec *spec = codec->spec;
4863
4864 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
4865 return 0;
4866}
4867
4868static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
4869 struct snd_ctl_elem_value *ucontrol)
4870{
4871 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4872 struct ca0132_spec *spec = codec->spec;
4873 int sel = ucontrol->value.enumerated.item[0];
4874 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
4875
4876 if (sel >= items)
4877 return 0;
4878
4879 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
4880 sel);
4881
4882 spec->mic_boost_enum_val = sel;
4883
4884 if (spec->in_enum_val != REAR_LINE_IN)
4885 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4886
4887 return 1;
4888}
4889
95c6e9cb 4890
7cb9d94c
CM		 4891/*
4892 * Input Select Control for alternative ca0132 codecs. This exists because
4893 * front microphone has no auto-detect, and we need a way to set the rear
4894 * as line-in
4895 */
4896static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4897 struct snd_ctl_elem_info *uinfo)
4898{
4899 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4900 uinfo->count = 1;
4901 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4902 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4903 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4904 strcpy(uinfo->value.enumerated.name,
4905 in_src_str[uinfo->value.enumerated.item]);
4906 return 0;
4907}
4908
4909static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4910 struct snd_ctl_elem_value *ucontrol)
4911{
4912 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4913 struct ca0132_spec *spec = codec->spec;
4914
4915 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4916 return 0;
4917}
4918
4919static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4920 struct snd_ctl_elem_value *ucontrol)
4921{
4922 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4923 struct ca0132_spec *spec = codec->spec;
4924 int sel = ucontrol->value.enumerated.item[0];
4925 unsigned int items = IN_SRC_NUM_OF_INPUTS;
4926
4927 if (sel >= items)
4928 return 0;
4929
4930 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4931 sel, in_src_str[sel]);
4932
4933 spec->in_enum_val = sel;
4934
4935 ca0132_alt_select_in(codec);
4936
4937 return 1;
4938}
4939
4940/* Sound Blaster Z Output Select Control */
4941static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
4942 struct snd_ctl_elem_info *uinfo)
4943{
4944 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4945 uinfo->count = 1;
4946 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
4947 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
4948 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
4949 strcpy(uinfo->value.enumerated.name,
4950 alt_out_presets[uinfo->value.enumerated.item].name);
4951 return 0;
4952}
4953
4954static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
4955 struct snd_ctl_elem_value *ucontrol)
4956{
4957 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4958 struct ca0132_spec *spec = codec->spec;
4959
4960 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
4961 return 0;
4962}
4963
4964static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
4965 struct snd_ctl_elem_value *ucontrol)
4966{
4967 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4968 struct ca0132_spec *spec = codec->spec;
4969 int sel = ucontrol->value.enumerated.item[0];
4970 unsigned int items = NUM_OF_OUTPUTS;
4971 unsigned int auto_jack;
4972
4973 if (sel >= items)
4974 return 0;
4975
4976 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
4977 sel, alt_out_presets[sel].name);
4978
4979 spec->out_enum_val = sel;
4980
4981 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4982
4983 if (!auto_jack)
4984 ca0132_alt_select_out(codec);
4985
4986 return 1;
4987}
4988
47cdf76e
CM		 4989/*
4990 * Smart Volume output setting control. Three different settings, Normal,
4991 * which takes the value from the smart volume slider. The two others, loud
4992 * and night, disregard the slider value and have uneditable values.
4993 */
4994#define NUM_OF_SVM_SETTINGS 3
4995static const char *out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
4996
4997static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
4998 struct snd_ctl_elem_info *uinfo)
4999{
5000 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5001 uinfo->count = 1;
5002 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5003 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5004 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5005 strcpy(uinfo->value.enumerated.name,
5006 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5007 return 0;
5008}
5009
5010static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5011 struct snd_ctl_elem_value *ucontrol)
5012{
5013 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5014 struct ca0132_spec *spec = codec->spec;
5015
5016 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5017 return 0;
5018}
5019
5020static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5021 struct snd_ctl_elem_value *ucontrol)
5022{
5023 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5024 struct ca0132_spec *spec = codec->spec;
5025 int sel = ucontrol->value.enumerated.item[0];
5026 unsigned int items = NUM_OF_SVM_SETTINGS;
5027 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5028 unsigned int tmp;
5029
5030 if (sel >= items)
5031 return 0;
5032
5033 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5034 sel, out_svm_set_enum_str[sel]);
5035
5036 spec->smart_volume_setting = sel;
5037
5038 switch (sel) {
5039 case 0:
5040 tmp = FLOAT_ZERO;
5041 break;
5042 case 1:
5043 tmp = FLOAT_ONE;
5044 break;
5045 case 2:
5046 tmp = FLOAT_TWO;
5047 break;
5048 default:
5049 tmp = FLOAT_ZERO;
5050 break;
5051 }
5052 /* Req 2 is the Smart Volume Setting req. */
5053 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5054 ca0132_effects[idx].reqs[2], tmp);
5055 return 1;
5056}
5057
5058/* Sound Blaster Z EQ preset controls */
5059static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5060 struct snd_ctl_elem_info *uinfo)
5061{
c5f13d75 5062 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5063
5064 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5065 uinfo->count = 1;
5066 uinfo->value.enumerated.items = items;
5067 if (uinfo->value.enumerated.item >= items)
5068 uinfo->value.enumerated.item = items - 1;
5069 strcpy(uinfo->value.enumerated.name,
5070 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5071 return 0;
5072}
5073
5074static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5075 struct snd_ctl_elem_value *ucontrol)
5076{
5077 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5078 struct ca0132_spec *spec = codec->spec;
5079
5080 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5081 return 0;
5082}
5083
5084static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5085 struct snd_ctl_elem_value *ucontrol)
5086{
5087 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5088 struct ca0132_spec *spec = codec->spec;
5089 int i, err = 0;
5090 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5091 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5092
5093 if (sel >= items)
5094 return 0;
5095
5096 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5097 ca0132_alt_eq_presets[sel].name);
5098 /*
5099 * Idx 0 is default.
5100 * Default needs to qualify with CrystalVoice state.
5101 */
5102 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5103 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5104 ca0132_alt_eq_enum.reqs[i],
5105 ca0132_alt_eq_presets[sel].vals[i]);
5106 if (err < 0)
5107 break;
5108 }
5109
5110 if (err >= 0)
5111 spec->eq_preset_val = sel;
5112
5113 return 1;
5114}
5115
a7e76271
IM		 5116static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5117 struct snd_ctl_elem_info *uinfo)
5118{
a9291f46 5119 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5120
5121 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5122 uinfo->count = 1;
5123 uinfo->value.enumerated.items = items;
5124 if (uinfo->value.enumerated.item >= items)
5125 uinfo->value.enumerated.item = items - 1;
5126 strcpy(uinfo->value.enumerated.name,
5127 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5128 return 0;
5129}
95c6e9cb 5130
a7e76271 5131static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5132 struct snd_ctl_elem_value *ucontrol)
5133{
5134 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5135 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5136
a7e76271 5137 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5138 return 0;
5139}
5140
a7e76271 5141static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5142 struct snd_ctl_elem_value *ucontrol)
5143{
5144 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5145 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5146 int i, err = 0;
5147 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5148
a9291f46 5149 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5150 return 0;
5151
4e76a883 5152 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5153 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5154
a7e76271
IM		 5155 /*
5156 * Idx 0 is default.
5157 * Default needs to qualify with CrystalVoice state.
5158 */
5159 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5160 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5161 ca0132_voicefx.reqs[i],
5162 ca0132_voicefx_presets[sel].vals[i]);
5163 if (err < 0)
5164 break;
5165 }
95c6e9cb 5166
a7e76271
IM		 5167 if (err >= 0) {
5168 spec->voicefx_val = sel;
5169 /* enable voice fx */
5170 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5171 }
95c6e9cb 5172
a7e76271 5173 return 1;
95c6e9cb
IM		 5174}
5175
a7e76271
IM		 5176static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5177 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5178{
5179 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5180 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5181 hda_nid_t nid = get_amp_nid(kcontrol);
5182 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5183 long *valp = ucontrol->value.integer.value;
5184
a7e76271
IM		 5185 /* vnode */
5186 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5187 if (ch & 1) {
5188 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5189 valp++;
5190 }
5191 if (ch & 2) {
5192 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5193 valp++;
5194 }
5195 return 0;
5196 }
5197
5198 /* effects, include PE and CrystalVoice */
5199 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5200 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5201 return 0;
5202 }
5203
5204 /* mic boost */
5205 if (nid == spec->input_pins[0]) {
5206 *valp = spec->cur_mic_boost;
5207 return 0;
5208 }
5209
95c6e9cb
IM		 5210 return 0;
5211}
5212
a7e76271
IM		 5213static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5214 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5215{
5216 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5217 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5218 hda_nid_t nid = get_amp_nid(kcontrol);
5219 int ch = get_amp_channels(kcontrol);
95c6e9cb 5220 long *valp = ucontrol->value.integer.value;
a7e76271 5221 int changed = 1;
95c6e9cb 5222
4e76a883 5223 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5224 nid, *valp);
95c6e9cb
IM		 5225
5226 snd_hda_power_up(codec);
a7e76271
IM		 5227 /* vnode */
5228 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5229 if (ch & 1) {
5230 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5231 valp++;
5232 }
5233 if (ch & 2) {
5234 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5235 valp++;
5236 }
5237 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5238 goto exit;
5239 }
95c6e9cb 5240
a7e76271
IM		 5241 /* PE */
5242 if (nid == PLAY_ENHANCEMENT) {
5243 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5244 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5245 goto exit;
a7e76271 5246 }
95c6e9cb 5247
a7e76271
IM		 5248 /* CrystalVoice */
5249 if (nid == CRYSTAL_VOICE) {
5250 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5251 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5252 goto exit;
a7e76271 5253 }
95c6e9cb 5254
a7e76271
IM		 5255 /* out and in effects */
5256 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5257 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5258 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5259 changed = ca0132_effects_set(codec, nid, *valp);
5260 goto exit;
5261 }
5262
5263 /* mic boost */
5264 if (nid == spec->input_pins[0]) {
5265 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 5266 if (spec->use_alt_functions) {
5267 if (spec->in_enum_val != REAR_LINE_IN)
5268 changed = ca0132_mic_boost_set(codec, *valp);
5269 } else {
5270 /* Mic boost does not apply to Digital Mic */
5271 if (spec->cur_mic_type != DIGITAL_MIC)
5272 changed = ca0132_mic_boost_set(codec, *valp);
5273 }
a7e76271 5274
a7e76271
IM		 5275 goto exit;
5276 }
95c6e9cb 5277
a7e76271 5278exit:
95c6e9cb 5279 snd_hda_power_down(codec);
a7e76271 5280 return changed;
95c6e9cb
IM		 5281}
5282
a7e76271
IM		 5283/*
5284 * Volume related
5285 */
017310fb
CM		 5286/*
5287 * Sets the internal DSP decibel level to match the DAC for output, and the
5288 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5289 * all alternative codecs set DSP playback volume.
5290 */
5291static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5292{
5293 struct ca0132_spec *spec = codec->spec;
5294 unsigned int dsp_dir;
5295 unsigned int lookup_val;
5296
5297 if (nid == VNID_SPK)
5298 dsp_dir = DSP_VOL_OUT;
5299 else
5300 dsp_dir = DSP_VOL_IN;
5301
5302 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5303
5304 dspio_set_uint_param(codec,
5305 ca0132_alt_vol_ctls[dsp_dir].mid,
5306 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5307 float_vol_db_lookup[lookup_val]);
5308
5309 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5310
5311 dspio_set_uint_param(codec,
5312 ca0132_alt_vol_ctls[dsp_dir].mid,
5313 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5314 float_vol_db_lookup[lookup_val]);
5315
5316 dspio_set_uint_param(codec,
5317 ca0132_alt_vol_ctls[dsp_dir].mid,
5318 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5319}
5320
a7e76271
IM		 5321static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5322 struct snd_ctl_elem_info *uinfo)
5323{
5324 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5325 struct ca0132_spec *spec = codec->spec;
5326 hda_nid_t nid = get_amp_nid(kcontrol);
5327 int ch = get_amp_channels(kcontrol);
5328 int dir = get_amp_direction(kcontrol);
5329 unsigned long pval;
5330 int err;
5331
5332 switch (nid) {
5333 case VNID_SPK:
5334 /* follow shared_out info */
5335 nid = spec->shared_out_nid;
5336 mutex_lock(&codec->control_mutex);
5337 pval = kcontrol->private_value;
5338 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5339 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5340 kcontrol->private_value = pval;
5341 mutex_unlock(&codec->control_mutex);
5342 break;
5343 case VNID_MIC:
5344 /* follow shared_mic info */
5345 nid = spec->shared_mic_nid;
5346 mutex_lock(&codec->control_mutex);
5347 pval = kcontrol->private_value;
5348 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5349 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5350 kcontrol->private_value = pval;
5351 mutex_unlock(&codec->control_mutex);
5352 break;
5353 default:
5354 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5355 }
5356 return err;
5357}
5358
5359static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5360 struct snd_ctl_elem_value *ucontrol)
5361{
5362 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5363 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5364 hda_nid_t nid = get_amp_nid(kcontrol);
5365 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5366 long *valp = ucontrol->value.integer.value;
5367
a7e76271
IM		 5368 /* store the left and right volume */
5369 if (ch & 1) {
5370 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5371 valp++;
5372 }
5373 if (ch & 2) {
5374 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5375 valp++;
5376 }
95c6e9cb
IM		 5377 return 0;
5378}
5379
a7e76271 5380static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5381 struct snd_ctl_elem_value *ucontrol)
5382{
5383 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5384 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5385 hda_nid_t nid = get_amp_nid(kcontrol);
5386 int ch = get_amp_channels(kcontrol);
95c6e9cb 5387 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5388 hda_nid_t shared_nid = 0;
5389 bool effective;
5390 int changed = 1;
5391
5392 /* store the left and right volume */
5393 if (ch & 1) {
5394 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5395 valp++;
5396 }
5397 if (ch & 2) {
5398 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5399 valp++;
5400 }
95c6e9cb 5401
a7e76271
IM		 5402 /* if effective conditions, then update hw immediately. */
5403 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5404 if (effective) {
5405 int dir = get_amp_direction(kcontrol);
5406 unsigned long pval;
5407
5408 snd_hda_power_up(codec);
5409 mutex_lock(&codec->control_mutex);
5410 pval = kcontrol->private_value;
5411 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5412 0, dir);
5413 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5414 kcontrol->private_value = pval;
5415 mutex_unlock(&codec->control_mutex);
5416 snd_hda_power_down(codec);
5417 }
95c6e9cb 5418
a7e76271 5419 return changed;
95c6e9cb
IM		 5420}
5421
017310fb
CM		 5422/*
5423 * This function is the same as the one above, because using an if statement
5424 * inside of the above volume control for the DSP volume would cause too much
5425 * lag. This is a lot more smooth.
5426 */
5427static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5428 struct snd_ctl_elem_value *ucontrol)
5429{
5430 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5431 struct ca0132_spec *spec = codec->spec;
5432 hda_nid_t nid = get_amp_nid(kcontrol);
5433 int ch = get_amp_channels(kcontrol);
5434 long *valp = ucontrol->value.integer.value;
5435 hda_nid_t vnid = 0;
5436 int changed = 1;
5437
5438 switch (nid) {
5439 case 0x02:
5440 vnid = VNID_SPK;
5441 break;
5442 case 0x07:
5443 vnid = VNID_MIC;
5444 break;
5445 }
5446
5447 /* store the left and right volume */
5448 if (ch & 1) {
5449 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5450 valp++;
5451 }
5452 if (ch & 2) {
5453 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5454 valp++;
5455 }
5456
5457 snd_hda_power_up(codec);
5458 ca0132_alt_dsp_volume_put(codec, vnid);
5459 mutex_lock(&codec->control_mutex);
5460 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5461 mutex_unlock(&codec->control_mutex);
5462 snd_hda_power_down(codec);
5463
5464 return changed;
5465}
5466
a7e76271
IM		 5467static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5468 unsigned int size, unsigned int __user *tlv)
95c6e9cb 5469{
a7e76271
IM		 5470 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5471 struct ca0132_spec *spec = codec->spec;
5472 hda_nid_t nid = get_amp_nid(kcontrol);
5473 int ch = get_amp_channels(kcontrol);
5474 int dir = get_amp_direction(kcontrol);
5475 unsigned long pval;
5476 int err;
5477
5478 switch (nid) {
5479 case VNID_SPK:
5480 /* follow shared_out tlv */
5481 nid = spec->shared_out_nid;
5482 mutex_lock(&codec->control_mutex);
5483 pval = kcontrol->private_value;
5484 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5485 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5486 kcontrol->private_value = pval;
5487 mutex_unlock(&codec->control_mutex);
5488 break;
5489 case VNID_MIC:
5490 /* follow shared_mic tlv */
5491 nid = spec->shared_mic_nid;
5492 mutex_lock(&codec->control_mutex);
5493 pval = kcontrol->private_value;
5494 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5495 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5496 kcontrol->private_value = pval;
5497 mutex_unlock(&codec->control_mutex);
5498 break;
5499 default:
5500 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5501 }
5502 return err;
95c6e9cb
IM		 5503}
5504
47cdf76e
CM		 5505/* Add volume slider control for effect level */
5506static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5507 const char *pfx, int dir)
5508{
5509 char *fx = "FX:";
5510 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5511 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5512 struct snd_kcontrol_new knew =
5513 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5514
5515 sprintf(namestr, "%s %s %s Volume", fx, pfx, dirstr[dir]);
5516
5517 knew.tlv.c = 0;
5518 knew.tlv.p = 0;
5519
5520 switch (nid) {
5521 case XBASS_XOVER:
5522 knew.info = ca0132_alt_xbass_xover_slider_info;
5523 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5524 knew.put = ca0132_alt_xbass_xover_slider_put;
5525 break;
5526 default:
5527 knew.info = ca0132_alt_effect_slider_info;
5528 knew.get = ca0132_alt_slider_ctl_get;
5529 knew.put = ca0132_alt_effect_slider_put;
5530 knew.private_value =
5531 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5532 break;
5533 }
5534
5535 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5536}
5537
5538/*
5539 * Added FX: prefix for the alternative codecs, because otherwise the surround
5540 * effect would conflict with the Surround sound volume control. Also seems more
5541 * clear as to what the switches do. Left alone for others.
5542 */
a7e76271
IM		 5543static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5544 const char *pfx, int dir)
95c6e9cb 5545{
47cdf76e
CM		 5546 struct ca0132_spec *spec = codec->spec;
5547 char *fx = "FX:";
975cc02a 5548 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 5549 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 5550 struct snd_kcontrol_new knew =
a7e76271 5551 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 5552 /* If using alt_controls, add FX: prefix. But, don't add FX:
5553 * prefix to OutFX or InFX enable controls.
5554 */
5555 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
5556 sprintf(namestr, "%s %s %s Switch", fx, pfx, dirstr[dir]);
5557 else
5558 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5559
95c6e9cb
IM		 5560 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5561}
5562
a7e76271 5563static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 5564{
5565 struct snd_kcontrol_new knew =
a7e76271
IM		 5566 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5567 VOICEFX, 1, 0, HDA_INPUT);
5568 knew.info = ca0132_voicefx_info;
5569 knew.get = ca0132_voicefx_get;
5570 knew.put = ca0132_voicefx_put;
5571 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 5572}
5573
47cdf76e
CM		 5574/* Create the EQ Preset control */
5575static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5576{
5577 struct snd_kcontrol_new knew =
5578 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5579 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5580 knew.info = ca0132_alt_eq_preset_info;
5581 knew.get = ca0132_alt_eq_preset_get;
5582 knew.put = ca0132_alt_eq_preset_put;
5583 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5584 snd_ctl_new1(&knew, codec));
5585}
5586
5587/*
5588 * Add enumerated control for the three different settings of the smart volume
5589 * output effect. Normal just uses the slider value, and loud and night are
5590 * their own things that ignore that value.
5591 */
5592static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5593{
5594 struct snd_kcontrol_new knew =
5595 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5596 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5597 knew.info = ca0132_alt_svm_setting_info;
5598 knew.get = ca0132_alt_svm_setting_get;
5599 knew.put = ca0132_alt_svm_setting_put;
5600 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5601 snd_ctl_new1(&knew, codec));
5602
5603}
5604
7cb9d94c
CM		 5605/*
5606 * Create an Output Select enumerated control for codecs with surround
5607 * out capabilities.
5608 */
5609static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5610{
5611 struct snd_kcontrol_new knew =
5612 HDA_CODEC_MUTE_MONO("Output Select",
5613 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5614 knew.info = ca0132_alt_output_select_get_info;
5615 knew.get = ca0132_alt_output_select_get;
5616 knew.put = ca0132_alt_output_select_put;
5617 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5618 snd_ctl_new1(&knew, codec));
5619}
5620
5621/*
5622 * Create an Input Source enumerated control for the alternate ca0132 codecs
5623 * because the front microphone has no auto-detect, and Line-in has to be set
5624 * somehow.
5625 */
5626static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5627{
5628 struct snd_kcontrol_new knew =
5629 HDA_CODEC_MUTE_MONO("Input Source",
5630 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5631 knew.info = ca0132_alt_input_source_info;
5632 knew.get = ca0132_alt_input_source_get;
5633 knew.put = ca0132_alt_input_source_put;
5634 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5635 snd_ctl_new1(&knew, codec));
5636}
5637
47cdf76e
CM		 5638/*
5639 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5640 * more control than the original mic boost, which is either full 30dB or off.
5641 */
5642static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5643{
5644 struct snd_kcontrol_new knew =
5645 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5646 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5647 knew.info = ca0132_alt_mic_boost_info;
5648 knew.get = ca0132_alt_mic_boost_get;
5649 knew.put = ca0132_alt_mic_boost_put;
5650 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5651 snd_ctl_new1(&knew, codec));
5652
5653}
5654
5655/*
5656 * Need to create slave controls for the alternate codecs that have surround
5657 * capabilities.
5658 */
5659static const char * const ca0132_alt_slave_pfxs[] = {
5660 "Front", "Surround", "Center", "LFE", NULL,
5661};
5662
5663/*
5664 * Also need special channel map, because the default one is incorrect.
5665 * I think this has to do with the pin for rear surround being 0x11,
5666 * and the center/lfe being 0x10. Usually the pin order is the opposite.
5667 */
5668const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
5669 { .channels = 2,
5670 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5671 { .channels = 4,
5672 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5673 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5674 { .channels = 6,
5675 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5676 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5677 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5678 { }
5679};
5680
5681/* Add the correct chmap for streams with 6 channels. */
5682static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5683{
5684 int err = 0;
5685 struct hda_pcm *pcm;
5686
5687 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5688 struct hda_pcm_stream *hinfo =
5689 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5690 struct snd_pcm_chmap *chmap;
5691 const struct snd_pcm_chmap_elem *elem;
5692
5693 elem = ca0132_alt_chmaps;
5694 if (hinfo->channels_max == 6) {
5695 err = snd_pcm_add_chmap_ctls(pcm->pcm,
5696 SNDRV_PCM_STREAM_PLAYBACK,
5697 elem, hinfo->channels_max, 0, &chmap);
5698 if (err < 0)
5699 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5700 }
5701 }
5702}
5703
a7e76271
IM		 5704/*
5705 * When changing Node IDs for Mixer Controls below, make sure to update
5706 * Node IDs in ca0132_config() as well.
5707 */
b0eaa072 5708static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 5709 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5710 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5711 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5712 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5713 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5714 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5715 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5716 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5717 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5718 0x12, 1, HDA_INPUT),
5719 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5720 VNID_HP_SEL, 1, HDA_OUTPUT),
5721 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5722 VNID_AMIC1_SEL, 1, HDA_INPUT),
5723 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5724 VNID_HP_ASEL, 1, HDA_OUTPUT),
5725 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5726 VNID_AMIC1_ASEL, 1, HDA_INPUT),
5727 { } /* end */
5728};
5729
017310fb
CM		 5730/*
5731 * SBZ specific control mixer. Removes auto-detect for mic, and adds surround
5732 * controls. Also sets both the Front Playback and Capture Volume controls to
5733 * alt so they set the DSP's decibel level.
5734 */
b0eaa072 5735static const struct snd_kcontrol_new sbz_mixer[] = {
017310fb
CM		 5736 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5737 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5738 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5739 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5740 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5741 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5742 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5743 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5744 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5745 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5746 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5747 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5748 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5749 VNID_HP_ASEL, 1, HDA_OUTPUT),
5750 { } /* end */
5751};
5752
5753/*
5754 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5755 * because it doesn't set decibel levels for the DSP for capture.
5756 */
b0eaa072 5757static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 5758 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5759 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5760 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5761 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5762 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5763 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5764 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5765 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5766 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5767 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5768 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5769 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5770 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5771 VNID_HP_ASEL, 1, HDA_OUTPUT),
5772 { } /* end */
5773};
5774
e90f29e4
IM		 5775static int ca0132_build_controls(struct hda_codec *codec)
5776{
5777 struct ca0132_spec *spec = codec->spec;
47cdf76e 5778 int i, num_fx, num_sliders;
e90f29e4
IM		 5779 int err = 0;
5780
5781 /* Add Mixer controls */
5782 for (i = 0; i < spec->num_mixers; i++) {
5783 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5784 if (err < 0)
5785 return err;
5786 }
47cdf76e
CM		 5787 /* Setup vmaster with surround slaves for desktop ca0132 devices */
5788 if (spec->use_alt_functions) {
5789 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5790 spec->tlv);
5791 snd_hda_add_vmaster(codec, "Master Playback Volume",
5792 spec->tlv, ca0132_alt_slave_pfxs,
5793 "Playback Volume");
5794 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5795 NULL, ca0132_alt_slave_pfxs,
5796 "Playback Switch",
5797 true, &spec->vmaster_mute.sw_kctl);
5798
5799 }
e90f29e4
IM		 5800
5801 /* Add in and out effects controls.
5802 * VoiceFX, PE and CrystalVoice are added separately.
5803 */
5804 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5805 for (i = 0; i < num_fx; i++) {
47cdf76e
CM		 5806 /* SBZ breaks if Echo Cancellation is used */
5807 if (spec->quirk == QUIRK_SBZ) {
5808 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5809 OUT_EFFECTS_COUNT))
5810 continue;
5811 }
5812
e90f29e4
IM		 5813 err = add_fx_switch(codec, ca0132_effects[i].nid,
5814 ca0132_effects[i].name,
5815 ca0132_effects[i].direct);
5816 if (err < 0)
5817 return err;
5818 }
47cdf76e
CM		 5819 /*
5820 * If codec has use_alt_controls set to true, add effect level sliders,
5821 * EQ presets, and Smart Volume presets. Also, change names to add FX
5822 * prefix, and change PlayEnhancement and CrystalVoice to match.
5823 */
5824 if (spec->use_alt_controls) {
5825 ca0132_alt_add_svm_enum(codec);
5826 add_ca0132_alt_eq_presets(codec);
5827 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5828 "Enable OutFX", 0);
5829 if (err < 0)
5830 return err;
e90f29e4 5831
47cdf76e
CM		 5832 err = add_fx_switch(codec, CRYSTAL_VOICE,
5833 "Enable InFX", 1);
5834 if (err < 0)
5835 return err;
e90f29e4 5836
47cdf76e
CM		 5837 num_sliders = OUT_EFFECTS_COUNT - 1;
5838 for (i = 0; i < num_sliders; i++) {
5839 err = ca0132_alt_add_effect_slider(codec,
5840 ca0132_effects[i].nid,
5841 ca0132_effects[i].name,
5842 ca0132_effects[i].direct);
5843 if (err < 0)
5844 return err;
5845 }
5846
5847 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5848 "X-Bass Crossover", EFX_DIR_OUT);
5849
5850 if (err < 0)
5851 return err;
5852 } else {
5853 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5854 "PlayEnhancement", 0);
5855 if (err < 0)
5856 return err;
e90f29e4 5857
47cdf76e
CM		 5858 err = add_fx_switch(codec, CRYSTAL_VOICE,
5859 "CrystalVoice", 1);
5860 if (err < 0)
5861 return err;
5862 }
e90f29e4
IM		 5863 add_voicefx(codec);
5864
7cb9d94c
CM		 5865 /*
5866 * If the codec uses alt_functions, you need the enumerated controls
5867 * to select the new outputs and inputs, plus add the new mic boost
5868 * setting control.
5869 */
5870 if (spec->use_alt_functions) {
5871 ca0132_alt_add_output_enum(codec);
5872 ca0132_alt_add_input_enum(codec);
47cdf76e 5873 ca0132_alt_add_mic_boost_enum(codec);
7cb9d94c 5874 }
e90f29e4
IM		 5875#ifdef ENABLE_TUNING_CONTROLS
5876 add_tuning_ctls(codec);
5877#endif
5878
5879 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
5880 if (err < 0)
5881 return err;
5882
5883 if (spec->dig_out) {
5884 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
5885 spec->dig_out);
5886 if (err < 0)
5887 return err;
5888 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
5889 if (err < 0)
5890 return err;
5891 /* spec->multiout.share_spdif = 1; */
5892 }
5893
5894 if (spec->dig_in) {
5895 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
5896 if (err < 0)
5897 return err;
5898 }
47cdf76e
CM		 5899
5900 if (spec->use_alt_functions)
5901 ca0132_alt_add_chmap_ctls(codec);
5902
e90f29e4
IM		 5903 return 0;
5904}
5905
a7e76271 5906/*
e90f29e4 5907 * PCM
a7e76271 5908 */
071f1344 5909static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 5910 .substreams = 1,
5911 .channels_min = 2,
825315bc 5912 .channels_max = 6,
a7e76271 5913 .ops = {
a7e76271 5914 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 5915 .cleanup = ca0132_playback_pcm_cleanup,
5916 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 5917 },
5918};
5919
071f1344 5920static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 5921 .substreams = 1,
5922 .channels_min = 2,
5923 .channels_max = 2,
825315bc
IM		 5924 .ops = {
5925 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 5926 .cleanup = ca0132_capture_pcm_cleanup,
5927 .get_delay = ca0132_capture_pcm_delay,
825315bc 5928 },
a7e76271
IM		 5929};
5930
071f1344 5931static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 5932 .substreams = 1,
5933 .channels_min = 2,
5934 .channels_max = 2,
5935 .ops = {
5936 .open = ca0132_dig_playback_pcm_open,
5937 .close = ca0132_dig_playback_pcm_close,
5938 .prepare = ca0132_dig_playback_pcm_prepare,
5939 .cleanup = ca0132_dig_playback_pcm_cleanup
5940 },
5941};
5942
071f1344 5943static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 5944 .substreams = 1,
5945 .channels_min = 2,
5946 .channels_max = 2,
5947};
5948
5949static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 5950{
5951 struct ca0132_spec *spec = codec->spec;
bbbc7e85 5952 struct hda_pcm *info;
a7e76271 5953
bbbc7e85
TI		 5954 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
5955 if (!info)
5956 return -ENOMEM;
47cdf76e
CM		 5957 if (spec->use_alt_functions) {
5958 info->own_chmap = true;
5959 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
5960 = ca0132_alt_chmaps;
5961 }
a7e76271
IM		 5962 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
5963 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
5964 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
5965 spec->multiout.max_channels;
5966 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 5967 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 5968 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 5969
009b8f97
CM		 5970 /* With the DSP enabled, desktops don't use this ADC. */
5971 if (spec->use_alt_functions) {
5972 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
5973 if (!info)
5974 return -ENOMEM;
5975 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
5976 ca0132_pcm_analog_capture;
5977 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
5978 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
5979 }
825315bc 5980
bbbc7e85
TI		 5981 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
5982 if (!info)
5983 return -ENOMEM;
825315bc
IM		 5984 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
5985 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
5986 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 5987
a7e76271
IM		 5988 if (!spec->dig_out && !spec->dig_in)
5989 return 0;
5990
bbbc7e85
TI		 5991 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
5992 if (!info)
5993 return -ENOMEM;
a7e76271
IM		 5994 info->pcm_type = HDA_PCM_TYPE_SPDIF;
5995 if (spec->dig_out) {
5996 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
5997 ca0132_pcm_digital_playback;
5998 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
5999 }
6000 if (spec->dig_in) {
6001 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6002 ca0132_pcm_digital_capture;
6003 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6004 }
95c6e9cb 6005
a7e76271 6006 return 0;
95c6e9cb
IM		 6007}
6008
441aa6a0
IM		 6009static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6010{
6011 if (pin) {
a0c041cb 6012 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6013 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6014 snd_hda_codec_write(codec, pin, 0,
6015 AC_VERB_SET_AMP_GAIN_MUTE,
6016 AMP_OUT_UNMUTE);
6017 }
6018 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6019 snd_hda_codec_write(codec, dac, 0,
6020 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6021}
6022
6023static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6024{
6025 if (pin) {
a0c041cb 6026 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6027 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6028 snd_hda_codec_write(codec, pin, 0,
6029 AC_VERB_SET_AMP_GAIN_MUTE,
6030 AMP_IN_UNMUTE(0));
6031 }
6032 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6033 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6034 AMP_IN_UNMUTE(0));
6035
6036 /* init to 0 dB and unmute. */
6037 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6038 HDA_AMP_VOLMASK, 0x5a);
6039 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6040 HDA_AMP_MUTE, 0);
6041 }
6042}
6043
5aaca44d
IM		 6044static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6045{
6046 unsigned int caps;
6047
6048 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6049 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6050 snd_hda_override_amp_caps(codec, nid, dir, caps);
6051}
6052
6053/*
6054 * Switch between Digital built-in mic and analog mic.
6055 */
6056static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6057{
6058 struct ca0132_spec *spec = codec->spec;
6059 unsigned int tmp;
6060 u8 val;
6061 unsigned int oldval;
6062
4e76a883 6063 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6064
6065 oldval = stop_mic1(codec);
6066 ca0132_set_vipsource(codec, 0);
6067 if (enable) {
6068 /* set DMic input as 2-ch */
6069 tmp = FLOAT_TWO;
6070 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6071
6072 val = spec->dmic_ctl;
6073 val |= 0x80;
6074 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6075 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6076
6077 if (!(spec->dmic_ctl & 0x20))
6078 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6079 } else {
6080 /* set AMic input as mono */
6081 tmp = FLOAT_ONE;
6082 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6083
6084 val = spec->dmic_ctl;
6085 /* clear bit7 and bit5 to disable dmic */
6086 val &= 0x5f;
6087 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6088 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6089
6090 if (!(spec->dmic_ctl & 0x20))
6091 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6092 }
6093 ca0132_set_vipsource(codec, 1);
6094 resume_mic1(codec, oldval);
6095}
6096
6097/*
6098 * Initialization for Digital Mic.
6099 */
6100static void ca0132_init_dmic(struct hda_codec *codec)
6101{
6102 struct ca0132_spec *spec = codec->spec;
6103 u8 val;
6104
6105 /* Setup Digital Mic here, but don't enable.
6106 * Enable based on jack detect.
6107 */
6108
6109 /* MCLK uses MPIO1, set to enable.
6110 * Bit 2-0: MPIO select
6111 * Bit 3: set to disable
6112 * Bit 7-4: reserved
6113 */
6114 val = 0x01;
6115 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6116 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6117
6118 /* Data1 uses MPIO3. Data2 not use
6119 * Bit 2-0: Data1 MPIO select
6120 * Bit 3: set disable Data1
6121 * Bit 6-4: Data2 MPIO select
6122 * Bit 7: set disable Data2
6123 */
6124 val = 0x83;
6125 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6126 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6127
6128 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6129 * Bit 3-0: Channel mask
6130 * Bit 4: set for 48KHz, clear for 32KHz
6131 * Bit 5: mode
6132 * Bit 6: set to select Data2, clear for Data1
6133 * Bit 7: set to enable DMic, clear for AMic
6134 */
6135 val = 0x23;
6136 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6137 spec->dmic_ctl = val;
6138 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6139 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6140}
6141
6142/*
6143 * Initialization for Analog Mic 2
6144 */
6145static void ca0132_init_analog_mic2(struct hda_codec *codec)
6146{
6147 struct ca0132_spec *spec = codec->spec;
6148
6149 mutex_lock(&spec->chipio_mutex);
6150 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6151 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6152 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6153 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6154 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6155 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6156 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6157 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6158 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6159 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6160 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6161 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6162 mutex_unlock(&spec->chipio_mutex);
6163}
6164
6165static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6166{
6167 struct ca0132_spec *spec = codec->spec;
6168 int i;
5aaca44d 6169
4e76a883 6170 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6171 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6172
6173 for (i = 0; i < spec->multiout.num_dacs; i++)
6174 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6175
6176 for (i = 0; i < spec->num_outputs; i++)
6177 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6178
6179 for (i = 0; i < spec->num_inputs; i++) {
6180 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6181 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6182 }
6183}
6184
7e6ed62e
CM		 6185/*
6186 * Recon3Di r3di_setup_defaults sub functions.
6187 */
6188
447fd8e9
CM		 6189static void r3di_dsp_scp_startup(struct hda_codec *codec)
6190{
6191 unsigned int tmp;
6192
6193 tmp = 0x00000000;
6194 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6195
6196 tmp = 0x00000001;
6197 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6198
6199 tmp = 0x00000004;
6200 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6201
6202 tmp = 0x00000005;
6203 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6204
6205 tmp = 0x00000000;
6206 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6207
6208}
6209
7e6ed62e
CM		 6210static void r3di_dsp_initial_mic_setup(struct hda_codec *codec)
6211{
6212 unsigned int tmp;
6213
6214 /* Mic 1 Setup */
6215 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6216 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6217 /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6218 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6219 tmp = FLOAT_ONE;
6220 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6221
6222 /* Mic 2 Setup, even though it isn't connected on SBZ */
6223 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6224 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6225 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6226 tmp = FLOAT_ZERO;
6227 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6228}
6229
38ba69ff
CM		 6230/*
6231 * Initialize Sound Blaster Z analog microphones.
6232 */
6233static void sbz_init_analog_mics(struct hda_codec *codec)
6234{
6235 unsigned int tmp;
6236
6237 /* Mic 1 Setup */
6238 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6239 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6240 tmp = FLOAT_THREE;
6241 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6242
6243 /* Mic 2 Setup, even though it isn't connected on SBZ */
6244 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6245 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6246 tmp = FLOAT_ZERO;
6247 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6248
6249}
6250
6251/*
6252 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6253 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6254 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6255 * having an updated DAC, which changes the destination to that DAC.
6256 */
6257static void sbz_connect_streams(struct hda_codec *codec)
6258{
6259 struct ca0132_spec *spec = codec->spec;
6260
6261 mutex_lock(&spec->chipio_mutex);
6262
6263 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6264
6265 chipio_set_stream_channels(codec, 0x0C, 6);
6266 chipio_set_stream_control(codec, 0x0C, 1);
6267
6268 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6269 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6270
6271 /* Setup stream 0x14 with it's source and destination points */
6272 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6273 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6274 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6275 chipio_set_stream_channels(codec, 0x14, 2);
6276 chipio_set_stream_control(codec, 0x14, 1);
6277
6278 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6279
6280 mutex_unlock(&spec->chipio_mutex);
6281
6282}
6283
6284/*
6285 * Write data through ChipIO to setup proper stream destinations.
6286 * Not sure how it exactly works, but it seems to direct data
6287 * to different destinations. Example is f8 to c0, e0 to c0.
6288 * All I know is, if you don't set these, you get no sound.
6289 */
6290static void sbz_chipio_startup_data(struct hda_codec *codec)
6291{
6292 struct ca0132_spec *spec = codec->spec;
6293
6294 mutex_lock(&spec->chipio_mutex);
6295 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6296
6297 /* These control audio output */
6298 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6299 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6300 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6301 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6302 /* Signal to update I think */
6303 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6304
6305 chipio_set_stream_channels(codec, 0x0C, 6);
6306 chipio_set_stream_control(codec, 0x0C, 1);
6307 /* No clue what these control */
6308 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6309 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6310 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6311 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6312 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6313 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6314 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6315 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6316 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6317 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6318 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6319 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6320
6321 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6322
6323 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6324 mutex_unlock(&spec->chipio_mutex);
6325}
6326
447fd8e9
CM		 6327/*
6328 * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6329 * without a 0x20 source like normal.
6330 */
6331static void sbz_dsp_scp_startup(struct hda_codec *codec)
6332{
6333 unsigned int tmp;
6334
6335 tmp = 0x00000003;
6336 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6337
6338 tmp = 0x00000000;
6339 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6340
6341 tmp = 0x00000001;
6342 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6343
6344 tmp = 0x00000004;
6345 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6346
6347 tmp = 0x00000005;
6348 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6349
6350 tmp = 0x00000000;
6351 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6352
6353}
6354
38ba69ff
CM		 6355static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
6356{
6357 unsigned int tmp;
6358
6359 chipio_set_stream_control(codec, 0x03, 0);
6360 chipio_set_stream_control(codec, 0x04, 0);
6361
6362 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6363 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6364
6365 tmp = FLOAT_THREE;
6366 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6367
6368 chipio_set_stream_control(codec, 0x03, 1);
6369 chipio_set_stream_control(codec, 0x04, 1);
6370
6371 chipio_write(codec, 0x18b098, 0x0000000c);
6372 chipio_write(codec, 0x18b09C, 0x0000000c);
6373}
6374
5aaca44d
IM		 6375/*
6376 * Setup default parameters for DSP
6377 */
6378static void ca0132_setup_defaults(struct hda_codec *codec)
6379{
e8f1bd5d 6380 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 6381 unsigned int tmp;
6382 int num_fx;
6383 int idx, i;
6384
e8f1bd5d 6385 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 6386 return;
6387
6388 /* out, in effects + voicefx */
6389 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6390 for (idx = 0; idx < num_fx; idx++) {
6391 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6392 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6393 ca0132_effects[idx].reqs[i],
6394 ca0132_effects[idx].def_vals[i]);
6395 }
6396 }
6397
6398 /*remove DSP headroom*/
6399 tmp = FLOAT_ZERO;
6400 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6401
6402 /*set speaker EQ bypass attenuation*/
6403 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6404
6405 /* set AMic1 and AMic2 as mono mic */
6406 tmp = FLOAT_ONE;
6407 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6408 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6409
6410 /* set AMic1 as CrystalVoice input */
6411 tmp = FLOAT_ONE;
6412 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6413
6414 /* set WUH source */
6415 tmp = FLOAT_TWO;
6416 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6417}
6418
7e6ed62e
CM		 6419/*
6420 * Setup default parameters for Recon3Di DSP.
6421 */
6422
6423static void r3di_setup_defaults(struct hda_codec *codec)
6424{
6425 struct ca0132_spec *spec = codec->spec;
6426 unsigned int tmp;
6427 int num_fx;
6428 int idx, i;
6429
6430 if (spec->dsp_state != DSP_DOWNLOADED)
6431 return;
6432
447fd8e9 6433 r3di_dsp_scp_startup(codec);
7e6ed62e
CM		 6434
6435 r3di_dsp_initial_mic_setup(codec);
6436
6437 /*remove DSP headroom*/
6438 tmp = FLOAT_ZERO;
6439 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6440
6441 /* set WUH source */
6442 tmp = FLOAT_TWO;
6443 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6444 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6445
6446 /* Set speaker source? */
6447 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6448
6449 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6450
6451 /* Setup effect defaults */
6452 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6453 for (idx = 0; idx < num_fx; idx++) {
6454 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6455 dspio_set_uint_param(codec,
6456 ca0132_effects[idx].mid,
6457 ca0132_effects[idx].reqs[i],
6458 ca0132_effects[idx].def_vals[i]);
6459 }
6460 }
6461
6462}
6463
38ba69ff
CM		 6464/*
6465 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6466 * than the Chromebook setup.
6467 */
6468static void sbz_setup_defaults(struct hda_codec *codec)
6469{
6470 struct ca0132_spec *spec = codec->spec;
6471 unsigned int tmp, stream_format;
6472 int num_fx;
6473 int idx, i;
6474
6475 if (spec->dsp_state != DSP_DOWNLOADED)
6476 return;
6477
447fd8e9 6478 sbz_dsp_scp_startup(codec);
38ba69ff
CM		 6479
6480 sbz_init_analog_mics(codec);
6481
6482 sbz_connect_streams(codec);
6483
6484 sbz_chipio_startup_data(codec);
6485
6486 chipio_set_stream_control(codec, 0x03, 1);
6487 chipio_set_stream_control(codec, 0x04, 1);
6488
6489 /*
6490 * Sets internal input loopback to off, used to have a switch to
6491 * enable input loopback, but turned out to be way too buggy.
6492 */
6493 tmp = FLOAT_ONE;
6494 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6495 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6496
6497 /*remove DSP headroom*/
6498 tmp = FLOAT_ZERO;
6499 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6500
6501 /* set WUH source */
6502 tmp = FLOAT_TWO;
6503 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6504 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6505
6506 /* Set speaker source? */
6507 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6508
6509 sbz_dsp_initial_mic_setup(codec);
6510
6511
6512 /* out, in effects + voicefx */
6513 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6514 for (idx = 0; idx < num_fx; idx++) {
6515 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6516 dspio_set_uint_param(codec,
6517 ca0132_effects[idx].mid,
6518 ca0132_effects[idx].reqs[i],
6519 ca0132_effects[idx].def_vals[i]);
6520 }
6521 }
6522
6523 /*
6524 * Have to make a stream to bind the sound output to, otherwise
6525 * you'll get dead audio. Before I did this, it would bind to an
6526 * audio input, and would never work
6527 */
6528 stream_format = snd_hdac_calc_stream_format(48000, 2,
6529 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6530
6531 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6532 0, stream_format);
6533
6534 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6535
6536 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6537 0, stream_format);
6538
6539 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6540}
6541
5aaca44d
IM		 6542/*
6543 * Initialization of flags in chip
6544 */
6545static void ca0132_init_flags(struct hda_codec *codec)
6546{
009b8f97
CM		 6547 struct ca0132_spec *spec = codec->spec;
6548
6549 if (spec->use_alt_functions) {
6550 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6551 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6552 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6553 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6554 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6555 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6556 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6557 chipio_set_control_flag(codec,
6558 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6559 chipio_set_control_flag(codec,
6560 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6561 } else {
6562 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6563 chipio_set_control_flag(codec,
6564 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6565 chipio_set_control_flag(codec,
6566 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6567 chipio_set_control_flag(codec,
6568 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6569 chipio_set_control_flag(codec,
6570 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6571 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6572 }
5aaca44d
IM		 6573}
6574
6575/*
6576 * Initialization of parameters in chip
6577 */
6578static void ca0132_init_params(struct hda_codec *codec)
6579{
009b8f97
CM		 6580 struct ca0132_spec *spec = codec->spec;
6581
6582 if (spec->use_alt_functions) {
6583 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6584 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6585 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6586 chipio_set_control_param(codec, 0, 0);
6587 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6588 }
6589
5aaca44d
IM		 6590 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6591 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6592}
95c6e9cb 6593
e90f29e4
IM		 6594static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6595{
6596 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6597 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6598 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6599 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6600 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6601 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6602
406261ce
IM		 6603 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6604 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 6605 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6606}
6607
6608static bool ca0132_download_dsp_images(struct hda_codec *codec)
6609{
6610 bool dsp_loaded = false;
8a19bcee 6611 struct ca0132_spec *spec = codec->spec;
e90f29e4 6612 const struct dsp_image_seg *dsp_os_image;
15e4ba66 6613 const struct firmware *fw_entry;
8a19bcee
CM		 6614 /*
6615 * Alternate firmwares for different variants. The Recon3Di apparently
6616 * can use the default firmware, but I'll leave the option in case
6617 * it needs it again.
6618 */
6619 switch (spec->quirk) {
6620 case QUIRK_SBZ:
6621 if (request_firmware(&fw_entry, SBZ_EFX_FILE,
6622 codec->card->dev) != 0) {
6623 codec_dbg(codec, "SBZ alt firmware not detected. ");
6624 spec->alt_firmware_present = false;
6625 } else {
6626 codec_dbg(codec, "Sound Blaster Z firmware selected.");
6627 spec->alt_firmware_present = true;
6628 }
6629 break;
6630 case QUIRK_R3DI:
6631 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6632 codec->card->dev) != 0) {
6633 codec_dbg(codec, "Recon3Di alt firmware not detected.");
6634 spec->alt_firmware_present = false;
6635 } else {
6636 codec_dbg(codec, "Recon3Di firmware selected.");
6637 spec->alt_firmware_present = true;
6638 }
6639 break;
6640 default:
6641 spec->alt_firmware_present = false;
6642 break;
6643 }
6644 /*
6645 * Use default ctefx.bin if no alt firmware is detected, or if none
6646 * exists for your particular codec.
6647 */
6648 if (!spec->alt_firmware_present) {
6649 codec_dbg(codec, "Default firmware selected.");
6650 if (request_firmware(&fw_entry, EFX_FILE,
6651 codec->card->dev) != 0)
6652 return false;
6653 }
e90f29e4 6654
15e4ba66 6655 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 6656 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 6657 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 6658 goto exit_download;
6659 }
6660
e90f29e4
IM		 6661 dsp_loaded = dspload_wait_loaded(codec);
6662
d1d28500 6663exit_download:
15e4ba66
TI		 6664 release_firmware(fw_entry);
6665
e90f29e4
IM		 6666 return dsp_loaded;
6667}
6668
6669static void ca0132_download_dsp(struct hda_codec *codec)
6670{
6671 struct ca0132_spec *spec = codec->spec;
6672
9a0869f4
TI		 6673#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6674 return; /* NOP */
6675#endif
e90f29e4 6676
e24aa0a4
TI		 6677 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6678 return; /* don't retry failures */
6679
b714a710 6680 chipio_enable_clocks(codec);
e93ac30a
CM		 6681 if (spec->dsp_state != DSP_DOWNLOADED) {
6682 spec->dsp_state = DSP_DOWNLOADING;
6683
6684 if (!ca0132_download_dsp_images(codec))
6685 spec->dsp_state = DSP_DOWNLOAD_FAILED;
6686 else
6687 spec->dsp_state = DSP_DOWNLOADED;
6688 }
e90f29e4 6689
009b8f97
CM		 6690 /* For codecs using alt functions, this is already done earlier */
6691 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 6692 ca0132_set_dsp_msr(codec, true);
6693}
6694
f8fb1170
TI		 6695static void ca0132_process_dsp_response(struct hda_codec *codec,
6696 struct hda_jack_callback *callback)
e90f29e4
IM		 6697{
6698 struct ca0132_spec *spec = codec->spec;
6699
4e76a883 6700 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 6701 if (spec->wait_scp) {
6702 if (dspio_get_response_data(codec) >= 0)
6703 spec->wait_scp = 0;
6704 }
6705
6706 dspio_clear_response_queue(codec);
6707}
6708
f8fb1170 6709static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 6710{
993884f6 6711 struct ca0132_spec *spec = codec->spec;
2ebab40e 6712 struct hda_jack_tbl *tbl;
e90f29e4 6713
f8fb1170
TI		 6714 /* Delay enabling the HP amp, to let the mic-detection
6715 * state machine run.
6716 */
6717 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 6718 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 6719 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6720 if (tbl)
6721 tbl->block_report = 1;
f8fb1170
TI		 6722}
6723
6724static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6725{
6726 ca0132_select_mic(codec);
6727}
6728
6729static void ca0132_init_unsol(struct hda_codec *codec)
6730{
d5c016b5
GM		 6731 struct ca0132_spec *spec = codec->spec;
6732 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6733 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 6734 amic_callback);
6735 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6736 ca0132_process_dsp_response);
63177afc 6737 /* Front headphone jack detection */
009b8f97 6738 if (spec->use_alt_functions)
63177afc
CM		 6739 snd_hda_jack_detect_enable_callback(codec,
6740 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 6741}
6742
5aaca44d
IM		 6743/*
6744 * Verbs tables.
6745 */
6746
6747/* Sends before DSP download. */
6748static struct hda_verb ca0132_base_init_verbs[] = {
6749 /*enable ct extension*/
6750 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 6751 {}
6752};
6753
6754/* Send at exit. */
6755static struct hda_verb ca0132_base_exit_verbs[] = {
6756 /*set afg to D3*/
6757 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
6758 /*disable ct extension*/
6759 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6760 {}
6761};
6762
8a19bcee 6763/* Other verbs tables. Sends after DSP download. */
e93ac30a 6764
5aaca44d
IM		 6765static struct hda_verb ca0132_init_verbs0[] = {
6766 /* chip init verbs */
6767 {0x15, 0x70D, 0xF0},
6768 {0x15, 0x70E, 0xFE},
6769 {0x15, 0x707, 0x75},
6770 {0x15, 0x707, 0xD3},
6771 {0x15, 0x707, 0x09},
6772 {0x15, 0x707, 0x53},
6773 {0x15, 0x707, 0xD4},
6774 {0x15, 0x707, 0xEF},
6775 {0x15, 0x707, 0x75},
6776 {0x15, 0x707, 0xD3},
6777 {0x15, 0x707, 0x09},
6778 {0x15, 0x707, 0x02},
6779 {0x15, 0x707, 0x37},
6780 {0x15, 0x707, 0x78},
6781 {0x15, 0x53C, 0xCE},
6782 {0x15, 0x575, 0xC9},
6783 {0x15, 0x53D, 0xCE},
6784 {0x15, 0x5B7, 0xC9},
6785 {0x15, 0x70D, 0xE8},
6786 {0x15, 0x70E, 0xFE},
6787 {0x15, 0x707, 0x02},
6788 {0x15, 0x707, 0x68},
6789 {0x15, 0x707, 0x62},
6790 {0x15, 0x53A, 0xCE},
6791 {0x15, 0x546, 0xC9},
6792 {0x15, 0x53B, 0xCE},
6793 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 6794 {}
6795};
6796
6797/* Extra init verbs for SBZ */
6798static struct hda_verb sbz_init_verbs[] = {
6799 {0x15, 0x70D, 0x20},
6800 {0x15, 0x70E, 0x19},
6801 {0x15, 0x707, 0x00},
6802 {0x15, 0x539, 0xCE},
6803 {0x15, 0x546, 0xC9},
6804 {0x15, 0x70D, 0xB7},
6805 {0x15, 0x70E, 0x09},
6806 {0x15, 0x707, 0x10},
6807 {0x15, 0x70D, 0xAF},
6808 {0x15, 0x70E, 0x09},
6809 {0x15, 0x707, 0x01},
6810 {0x15, 0x707, 0x05},
6811 {0x15, 0x70D, 0x73},
6812 {0x15, 0x70E, 0x09},
6813 {0x15, 0x707, 0x14},
6814 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 6815 {}
6816};
6817
95c6e9cb
IM		 6818static void ca0132_init_chip(struct hda_codec *codec)
6819{
6820 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 6821 int num_fx;
6822 int i;
6823 unsigned int on;
95c6e9cb
IM		 6824
6825 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 6826
6827 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 6828 if (!spec->use_alt_functions)
6829 spec->cur_mic_type = DIGITAL_MIC;
6830 else
6831 spec->cur_mic_type = REAR_MIC;
6832
5aaca44d
IM		 6833 spec->cur_mic_boost = 0;
6834
6835 for (i = 0; i < VNODES_COUNT; i++) {
6836 spec->vnode_lvol[i] = 0x5a;
6837 spec->vnode_rvol[i] = 0x5a;
6838 spec->vnode_lswitch[i] = 0;
6839 spec->vnode_rswitch[i] = 0;
6840 }
6841
6842 /*
6843 * Default states for effects are in ca0132_effects[].
6844 */
6845 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6846 for (i = 0; i < num_fx; i++) {
6847 on = (unsigned int)ca0132_effects[i].reqs[0];
6848 spec->effects_switch[i] = on ? 1 : 0;
6849 }
47cdf76e
CM		 6850 /*
6851 * Sets defaults for the effect slider controls, only for alternative
6852 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6853 */
6854 if (spec->use_alt_controls) {
6855 spec->xbass_xover_freq = 8;
6856 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6857 spec->fx_ctl_val[i] = effect_slider_defaults[i];
6858 }
5aaca44d
IM		 6859
6860 spec->voicefx_val = 0;
6861 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6862 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
6863
44f0c978
IM		 6864#ifdef ENABLE_TUNING_CONTROLS
6865 ca0132_init_tuning_defaults(codec);
6866#endif
95c6e9cb
IM		 6867}
6868
2e48b2b7
CM		 6869/*
6870 * Recon3Di exit specific commands.
6871 */
6872/* prevents popping noise on shutdown */
6873static void r3di_gpio_shutdown(struct hda_codec *codec)
6874{
6875 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
6876}
6877
6878/*
6879 * Sound Blaster Z exit specific commands.
6880 */
6881static void sbz_region2_exit(struct hda_codec *codec)
6882{
6883 struct ca0132_spec *spec = codec->spec;
6884 unsigned int i;
6885
6886 for (i = 0; i < 4; i++)
6887 writeb(0x0, spec->mem_base + 0x100);
6888 for (i = 0; i < 8; i++)
6889 writeb(0xb3, spec->mem_base + 0x304);
6890 /*
6891 * I believe these are GPIO, with the right most hex digit being the
6892 * gpio pin, and the second digit being on or off. We see this more in
6893 * the input/output select functions.
6894 */
6895 writew(0x0000, spec->mem_base + 0x320);
6896 writew(0x0001, spec->mem_base + 0x320);
6897 writew(0x0104, spec->mem_base + 0x320);
6898 writew(0x0005, spec->mem_base + 0x320);
6899 writew(0x0007, spec->mem_base + 0x320);
6900}
6901
6902static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6903{
6904 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6905 unsigned int i;
6906
6907 snd_hda_codec_write(codec, 0x11, 0,
6908 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6909
6910 for (i = 0; i < 5; i++)
6911 snd_hda_codec_write(codec, pins[i], 0,
6912 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6913}
6914
6915static void sbz_clear_unsolicited(struct hda_codec *codec)
6916{
6917 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6918 unsigned int i;
6919
6920 for (i = 0; i < 7; i++) {
6921 snd_hda_codec_write(codec, pins[i], 0,
6922 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6923 }
6924}
6925
6926/* On shutdown, sends commands in sets of three */
6927static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
6928 int mask, int data)
6929{
6930 if (dir >= 0)
6931 snd_hda_codec_write(codec, 0x01, 0,
6932 AC_VERB_SET_GPIO_DIRECTION, dir);
6933 if (mask >= 0)
6934 snd_hda_codec_write(codec, 0x01, 0,
6935 AC_VERB_SET_GPIO_MASK, mask);
6936
6937 if (data >= 0)
6938 snd_hda_codec_write(codec, 0x01, 0,
6939 AC_VERB_SET_GPIO_DATA, data);
6940}
6941
6942static void sbz_exit_chip(struct hda_codec *codec)
6943{
009b8f97
CM		 6944 chipio_set_stream_control(codec, 0x03, 0);
6945 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 6946
6947 /* Mess with GPIO */
6948 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
6949 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
6950 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
6951
009b8f97
CM		 6952 chipio_set_stream_control(codec, 0x14, 0);
6953 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 6954
6955 chipio_set_conn_rate(codec, 0x41, SR_192_000);
6956 chipio_set_conn_rate(codec, 0x91, SR_192_000);
6957
6958 chipio_write(codec, 0x18a020, 0x00000083);
6959
6960 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
6961 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
6962 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
6963
009b8f97 6964 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 6965
6966 chipio_set_control_param(codec, 0x0D, 0x24);
6967
6968 sbz_clear_unsolicited(codec);
6969 sbz_set_pin_ctl_default(codec);
6970
6971 snd_hda_codec_write(codec, 0x0B, 0,
6972 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
6973
6974 if (dspload_is_loaded(codec))
6975 dsp_reset(codec);
6976
6977 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6978 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x00);
6979
6980 sbz_region2_exit(codec);
6981}
6982
95c6e9cb
IM		 6983static void ca0132_exit_chip(struct hda_codec *codec)
6984{
6985 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 6986
6987 if (dspload_is_loaded(codec))
6988 dsp_reset(codec);
95c6e9cb
IM		 6989}
6990
38ba69ff
CM		 6991/*
6992 * This fixes a problem that was hard to reproduce. Very rarely, I would
6993 * boot up, and there would be no sound, but the DSP indicated it had loaded
6994 * properly. I did a few memory dumps to see if anything was different, and
6995 * there were a few areas of memory uninitialized with a1a2a3a4. This function
6996 * checks if those areas are uninitialized, and if they are, it'll attempt to
6997 * reload the card 3 times. Usually it fixes by the second.
6998 */
6999static void sbz_dsp_startup_check(struct hda_codec *codec)
7000{
7001 struct ca0132_spec *spec = codec->spec;
7002 unsigned int dsp_data_check[4];
7003 unsigned int cur_address = 0x390;
7004 unsigned int i;
7005 unsigned int failure = 0;
7006 unsigned int reload = 3;
7007
7008 if (spec->startup_check_entered)
7009 return;
7010
7011 spec->startup_check_entered = true;
7012
7013 for (i = 0; i < 4; i++) {
7014 chipio_read(codec, cur_address, &dsp_data_check[i]);
7015 cur_address += 0x4;
7016 }
7017 for (i = 0; i < 4; i++) {
7018 if (dsp_data_check[i] == 0xa1a2a3a4)
7019 failure = 1;
7020 }
7021
7022 codec_dbg(codec, "Startup Check: %d ", failure);
7023 if (failure)
7024 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7025 /*
7026 * While the failure condition is true, and we haven't reached our
7027 * three reload limit, continue trying to reload the driver and
7028 * fix the issue.
7029 */
7030 while (failure && (reload != 0)) {
7031 codec_info(codec, "Reloading... Tries left: %d", reload);
7032 sbz_exit_chip(codec);
7033 spec->dsp_state = DSP_DOWNLOAD_INIT;
7034 codec->patch_ops.init(codec);
7035 failure = 0;
7036 for (i = 0; i < 4; i++) {
7037 chipio_read(codec, cur_address, &dsp_data_check[i]);
7038 cur_address += 0x4;
7039 }
7040 for (i = 0; i < 4; i++) {
7041 if (dsp_data_check[i] == 0xa1a2a3a4)
7042 failure = 1;
7043 }
7044 reload--;
7045 }
7046
7047 if (!failure && reload < 3)
7048 codec_info(codec, "DSP fixed.");
7049
7050 if (!failure)
7051 return;
7052
7053 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7054}
7055
e93ac30a
CM		 7056/*
7057 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7058 * extra precision for decibel values. If you had the dB value in floating point
7059 * you would take the value after the decimal point, multiply by 64, and divide
7060 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7061 * implement fixed point or floating point dB volumes. For now, I'll set them
7062 * to 0 just incase a value has lingered from a boot into Windows.
7063 */
7064static void ca0132_alt_vol_setup(struct hda_codec *codec)
7065{
7066 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7067 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7068 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7069 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7070 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7071 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7072 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7073 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7074}
7075
7076/*
7077 * Extra commands that don't really fit anywhere else.
7078 */
7079static void sbz_pre_dsp_setup(struct hda_codec *codec)
7080{
7081 struct ca0132_spec *spec = codec->spec;
7082
7083 writel(0x00820680, spec->mem_base + 0x01C);
7084 writel(0x00820680, spec->mem_base + 0x01C);
7085
7086 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7087 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7088 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7089 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7090
7091 chipio_write(codec, 0x18b0a4, 0x000000c2);
7092
7093 snd_hda_codec_write(codec, 0x11, 0,
7094 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7095}
7096
7097/*
7098 * Extra commands that don't really fit anywhere else.
7099 */
7100static void r3di_pre_dsp_setup(struct hda_codec *codec)
7101{
7102 chipio_write(codec, 0x18b0a4, 0x000000c2);
7103
7104 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7105 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7106 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7107 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7108 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7109 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7110
7111 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7112 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7113 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7114 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7115 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7116 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7117 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7118 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7119
7120 snd_hda_codec_write(codec, 0x11, 0,
7121 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7122}
7123
7124
7125/*
7126 * These are sent before the DSP is downloaded. Not sure
7127 * what they do, or if they're necessary. Could possibly
7128 * be removed. Figure they're better to leave in.
7129 */
7130static void sbz_region2_startup(struct hda_codec *codec)
7131{
7132 struct ca0132_spec *spec = codec->spec;
7133
7134 writel(0x00000000, spec->mem_base + 0x400);
7135 writel(0x00000000, spec->mem_base + 0x408);
7136 writel(0x00000000, spec->mem_base + 0x40C);
7137 writel(0x00880680, spec->mem_base + 0x01C);
7138 writel(0x00000083, spec->mem_base + 0xC0C);
7139 writel(0x00000030, spec->mem_base + 0xC00);
7140 writel(0x00000000, spec->mem_base + 0xC04);
7141 writel(0x00000003, spec->mem_base + 0xC0C);
7142 writel(0x00000003, spec->mem_base + 0xC0C);
7143 writel(0x00000003, spec->mem_base + 0xC0C);
7144 writel(0x00000003, spec->mem_base + 0xC0C);
7145 writel(0x000000C1, spec->mem_base + 0xC08);
7146 writel(0x000000F1, spec->mem_base + 0xC08);
7147 writel(0x00000001, spec->mem_base + 0xC08);
7148 writel(0x000000C7, spec->mem_base + 0xC08);
7149 writel(0x000000C1, spec->mem_base + 0xC08);
7150 writel(0x00000080, spec->mem_base + 0xC04);
7151}
7152
7153/*
7154 * Extra init functions for alternative ca0132 codecs. Done
7155 * here so they don't clutter up the main ca0132_init function
7156 * anymore than they have to.
7157 */
7158static void ca0132_alt_init(struct hda_codec *codec)
7159{
7160 struct ca0132_spec *spec = codec->spec;
7161
7162 ca0132_alt_vol_setup(codec);
7163
7164 switch (spec->quirk) {
7165 case QUIRK_SBZ:
7166 codec_dbg(codec, "SBZ alt_init");
7167 ca0132_gpio_init(codec);
7168 sbz_pre_dsp_setup(codec);
7169 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7170 snd_hda_sequence_write(codec, spec->sbz_init_verbs);
7171 break;
7172 case QUIRK_R3DI:
7173 codec_dbg(codec, "R3DI alt_init");
7174 ca0132_gpio_init(codec);
7175 ca0132_gpio_setup(codec);
7e6ed62e 7176 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 7177 r3di_pre_dsp_setup(codec);
7178 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7179 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7180 break;
7181 }
7182}
7183
95c6e9cb
IM		 7184static int ca0132_init(struct hda_codec *codec)
7185{
7186 struct ca0132_spec *spec = codec->spec;
7187 struct auto_pin_cfg *cfg = &spec->autocfg;
7188 int i;
e93ac30a
CM		 7189 bool dsp_loaded;
7190
7191 /*
7192 * If the DSP is already downloaded, and init has been entered again,
7193 * there's only two reasons for it. One, the codec has awaken from a
7194 * suspended state, and in that case dspload_is_loaded will return
7195 * false, and the init will be ran again. The other reason it gets
7196 * re entered is on startup for some reason it triggers a suspend and
7197 * resume state. In this case, it will check if the DSP is downloaded,
7198 * and not run the init function again. For codecs using alt_functions,
7199 * it will check if the DSP is loaded properly.
7200 */
7201 if (spec->dsp_state == DSP_DOWNLOADED) {
7202 dsp_loaded = dspload_is_loaded(codec);
7203 if (!dsp_loaded) {
7204 spec->dsp_reload = true;
7205 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 7206 } else {
7207 if (spec->quirk == QUIRK_SBZ)
7208 sbz_dsp_startup_check(codec);
e93ac30a 7209 return 0;
38ba69ff 7210 }
e93ac30a 7211 }
95c6e9cb 7212
e24aa0a4
TI		 7213 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7214 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 7215 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 7216
e93ac30a
CM		 7217 if (spec->quirk == QUIRK_SBZ)
7218 sbz_region2_startup(codec);
7219
664c7155 7220 snd_hda_power_up_pm(codec);
5aaca44d 7221
f8fb1170 7222 ca0132_init_unsol(codec);
5aaca44d
IM		 7223 ca0132_init_params(codec);
7224 ca0132_init_flags(codec);
7e6ed62e 7225
5aaca44d 7226 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a
CM		 7227
7228 if (spec->quirk != QUIRK_NONE)
7229 ca0132_alt_init(codec);
7230
01ef7dbf 7231 ca0132_download_dsp(codec);
7e6ed62e 7232
5aaca44d 7233 ca0132_refresh_widget_caps(codec);
e93ac30a
CM		 7234
7235 if (spec->quirk == QUIRK_SBZ)
7236 writew(0x0107, spec->mem_base + 0x320);
7237
7e6ed62e
CM		 7238 switch (spec->quirk) {
7239 case QUIRK_R3DI:
7240 r3di_setup_defaults(codec);
7241 break;
7242 case QUIRK_NONE:
7243 case QUIRK_ALIENWARE:
38ba69ff
CM		 7244 ca0132_setup_defaults(codec);
7245 ca0132_init_analog_mic2(codec);
7246 ca0132_init_dmic(codec);
7e6ed62e 7247 break;
38ba69ff 7248 }
5aaca44d
IM		 7249
7250 for (i = 0; i < spec->num_outputs; i++)
7251 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 7252
95c6e9cb
IM		 7253 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7254
7255 for (i = 0; i < spec->num_inputs; i++)
7256 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7257
7258 init_input(codec, cfg->dig_in_pin, spec->dig_in);
7259
009b8f97 7260 if (!spec->use_alt_functions) {
e93ac30a
CM		 7261 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7262 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7263 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7264 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7265 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7266 }
7267
7cb9d94c 7268 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 7269 ca0132_gpio_setup(codec);
7270
d5c016b5 7271 snd_hda_sequence_write(codec, spec->spec_init_verbs);
7cb9d94c
CM		 7272 switch (spec->quirk) {
7273 case QUIRK_SBZ:
7274 sbz_setup_defaults(codec);
7275 ca0132_alt_select_out(codec);
7276 ca0132_alt_select_in(codec);
7277 break;
7278 case QUIRK_R3DI:
7279 ca0132_alt_select_out(codec);
7280 ca0132_alt_select_in(codec);
7281 break;
7282 default:
7283 ca0132_select_out(codec);
7284 ca0132_select_mic(codec);
7285 break;
7286 }
5aaca44d 7287
a73d511c
IM		 7288 snd_hda_jack_report_sync(codec);
7289
e93ac30a
CM		 7290 /*
7291 * Re set the PlayEnhancement switch on a resume event, because the
7292 * controls will not be reloaded.
7293 */
7294 if (spec->dsp_reload) {
7295 spec->dsp_reload = false;
7296 ca0132_pe_switch_set(codec);
7297 }
7298
664c7155 7299 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 7300
7301 return 0;
7302}
7303
95c6e9cb
IM		 7304static void ca0132_free(struct hda_codec *codec)
7305{
5aaca44d
IM		 7306 struct ca0132_spec *spec = codec->spec;
7307
993884f6 7308 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 7309 snd_hda_power_up(codec);
2e48b2b7
CM		 7310 switch (spec->quirk) {
7311 case QUIRK_SBZ:
7312 sbz_exit_chip(codec);
7313 break;
7314 case QUIRK_R3DI:
7315 r3di_gpio_shutdown(codec);
7316 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7317 ca0132_exit_chip(codec);
7318 break;
7319 default:
7320 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7321 ca0132_exit_chip(codec);
7322 break;
7323 }
5aaca44d 7324 snd_hda_power_down(codec);
aa31704f
CM		 7325 if (spec->mem_base)
7326 iounmap(spec->mem_base);
d5c016b5 7327 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 7328 kfree(codec->spec);
7329}
7330
2e48b2b7
CM		 7331static void ca0132_reboot_notify(struct hda_codec *codec)
7332{
7333 codec->patch_ops.free(codec);
7334}
7335
071f1344 7336static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 7337 .build_controls = ca0132_build_controls,
7338 .build_pcms = ca0132_build_pcms,
7339 .init = ca0132_init,
7340 .free = ca0132_free,
f8fb1170 7341 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 7342 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 7343};
7344
441aa6a0
IM		 7345static void ca0132_config(struct hda_codec *codec)
7346{
7347 struct ca0132_spec *spec = codec->spec;
7348 struct auto_pin_cfg *cfg = &spec->autocfg;
7349
7350 spec->dacs[0] = 0x2;
7351 spec->dacs[1] = 0x3;
7352 spec->dacs[2] = 0x4;
7353
7354 spec->multiout.dac_nids = spec->dacs;
7355 spec->multiout.num_dacs = 3;
441aa6a0 7356
009b8f97 7357 if (!spec->use_alt_functions)
63177afc
CM		 7358 spec->multiout.max_channels = 2;
7359 else
7360 spec->multiout.max_channels = 6;
7361
7362 switch (spec->quirk) {
7363 case QUIRK_ALIENWARE:
d5c016b5 7364 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 7365 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7366
7367 spec->num_outputs = 2;
7368 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 7369 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 7370 spec->shared_out_nid = 0x2;
7371 spec->unsol_tag_hp = 0x0f;
7372
7373 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7374 spec->adcs[1] = 0x8; /* analog mic2 */
7375 spec->adcs[2] = 0xa; /* what u hear */
7376
7377 spec->num_inputs = 3;
7378 spec->input_pins[0] = 0x12;
7379 spec->input_pins[1] = 0x11;
7380 spec->input_pins[2] = 0x13;
7381 spec->shared_mic_nid = 0x7;
7382 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 7383 break;
7384 case QUIRK_SBZ:
7385 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7386 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7387
7388 spec->num_outputs = 2;
7389 spec->out_pins[0] = 0x0B; /* Line out */
7390 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7391 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7392 spec->out_pins[3] = 0x11; /* Rear surround */
7393 spec->shared_out_nid = 0x2;
7394 spec->unsol_tag_hp = spec->out_pins[1];
7395 spec->unsol_tag_front_hp = spec->out_pins[2];
7396
7397 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7398 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7399 spec->adcs[2] = 0xa; /* what u hear */
7400
7401 spec->num_inputs = 2;
7402 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7403 spec->input_pins[1] = 0x13; /* What U Hear */
7404 spec->shared_mic_nid = 0x7;
7405 spec->unsol_tag_amic1 = spec->input_pins[0];
7406
7407 /* SPDIF I/O */
7408 spec->dig_out = 0x05;
7409 spec->multiout.dig_out_nid = spec->dig_out;
7410 cfg->dig_out_pins[0] = 0x0c;
7411 cfg->dig_outs = 1;
7412 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
7413 spec->dig_in = 0x09;
7414 cfg->dig_in_pin = 0x0e;
7415 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
7416 break;
7417 case QUIRK_R3DI:
7418 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7419 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7420
7421 spec->num_outputs = 2;
7422 spec->out_pins[0] = 0x0B; /* Line out */
7423 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7424 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7425 spec->out_pins[3] = 0x11; /* Rear surround */
7426 spec->shared_out_nid = 0x2;
7427 spec->unsol_tag_hp = spec->out_pins[1];
7428 spec->unsol_tag_front_hp = spec->out_pins[2];
7429
7430 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7431 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7432 spec->adcs[2] = 0x0a; /* what u hear */
7433
7434 spec->num_inputs = 2;
7435 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7436 spec->input_pins[1] = 0x13; /* What U Hear */
7437 spec->shared_mic_nid = 0x7;
7438 spec->unsol_tag_amic1 = spec->input_pins[0];
7439
7440 /* SPDIF I/O */
7441 spec->dig_out = 0x05;
7442 spec->multiout.dig_out_nid = spec->dig_out;
7443 cfg->dig_out_pins[0] = 0x0c;
7444 cfg->dig_outs = 1;
7445 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
7446 break;
7447 default:
fe14f39e
TI		 7448 spec->num_outputs = 2;
7449 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 7450 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 7451 spec->shared_out_nid = 0x2;
7452 spec->unsol_tag_hp = spec->out_pins[1];
7453
7454 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7455 spec->adcs[1] = 0x8; /* analog mic2 */
7456 spec->adcs[2] = 0xa; /* what u hear */
7457
7458 spec->num_inputs = 3;
7459 spec->input_pins[0] = 0x12;
7460 spec->input_pins[1] = 0x11;
7461 spec->input_pins[2] = 0x13;
7462 spec->shared_mic_nid = 0x7;
7463 spec->unsol_tag_amic1 = spec->input_pins[0];
7464
7465 /* SPDIF I/O */
7466 spec->dig_out = 0x05;
7467 spec->multiout.dig_out_nid = spec->dig_out;
7468 cfg->dig_out_pins[0] = 0x0c;
7469 cfg->dig_outs = 1;
7470 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
7471 spec->dig_in = 0x09;
7472 cfg->dig_in_pin = 0x0e;
7473 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
63177afc 7474 break;
d5c016b5 7475 }
441aa6a0
IM		 7476}
7477
d5c016b5
GM		 7478static int ca0132_prepare_verbs(struct hda_codec *codec)
7479{
7480/* Verbs + terminator (an empty element) */
7481#define NUM_SPEC_VERBS 4
7482 struct ca0132_spec *spec = codec->spec;
7483
7484 spec->chip_init_verbs = ca0132_init_verbs0;
e93ac30a
CM		 7485 if (spec->quirk == QUIRK_SBZ)
7486 spec->sbz_init_verbs = sbz_init_verbs;
d5c016b5
GM		 7487 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
7488 if (!spec->spec_init_verbs)
7489 return -ENOMEM;
7490
7491 /* HP jack autodetection */
7492 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
7493 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
7494 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
7495
7496 /* MIC1 jack autodetection */
7497 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
7498 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
7499 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
7500
7501 /* config EAPD */
7502 spec->spec_init_verbs[2].nid = 0x0b;
7503 spec->spec_init_verbs[2].param = 0x78D;
7504 spec->spec_init_verbs[2].verb = 0x00;
7505
7506 /* Previously commented configuration */
7507 /*
7508 spec->spec_init_verbs[3].nid = 0x0b;
7509 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
7510 spec->spec_init_verbs[3].verb = 0x02;
7511
7512 spec->spec_init_verbs[4].nid = 0x10;
7513 spec->spec_init_verbs[4].param = 0x78D;
7514 spec->spec_init_verbs[4].verb = 0x02;
7515
7516 spec->spec_init_verbs[5].nid = 0x10;
7517 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
7518 spec->spec_init_verbs[5].verb = 0x02;
7519 */
7520
7521 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7522 return 0;
7523}
7524
95c6e9cb
IM		 7525static int patch_ca0132(struct hda_codec *codec)
7526{
7527 struct ca0132_spec *spec;
a73d511c 7528 int err;
d5c016b5 7529 const struct snd_pci_quirk *quirk;
95c6e9cb 7530
4e76a883 7531 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 7532
7533 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7534 if (!spec)
7535 return -ENOMEM;
7536 codec->spec = spec;
993884f6 7537 spec->codec = codec;
95c6e9cb 7538
225068ab
TI		 7539 codec->patch_ops = ca0132_patch_ops;
7540 codec->pcm_format_first = 1;
7541 codec->no_sticky_stream = 1;
7542
d5c016b5
GM		 7543 /* Detect codec quirk */
7544 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7545 if (quirk)
7546 spec->quirk = quirk->value;
7547 else
7548 spec->quirk = QUIRK_NONE;
7549
aa31704f
CM		 7550 /* Setup BAR Region 2 for Sound Blaster Z */
7551 if (spec->quirk == QUIRK_SBZ) {
7552 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7553 if (spec->mem_base == NULL) {
7554 codec_warn(codec, "pci_iomap failed!");
7555 codec_info(codec, "perhaps this is not an SBZ?");
7556 spec->quirk = QUIRK_NONE;
7557 }
7558 }
009b8f97 7559
e24aa0a4 7560 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 7561 spec->num_mixers = 1;
017310fb
CM		 7562
7563 /* Set which mixers each quirk uses. */
7564 switch (spec->quirk) {
7565 case QUIRK_SBZ:
7566 spec->mixers[0] = sbz_mixer;
7567 snd_hda_codec_set_name(codec, "Sound Blaster Z");
7568 break;
7569 case QUIRK_R3DI:
7570 spec->mixers[0] = r3di_mixer;
7571 snd_hda_codec_set_name(codec, "Recon3Di");
7572 break;
7573 default:
7574 spec->mixers[0] = ca0132_mixer;
7575 break;
7576 }
a7e76271 7577
47cdf76e 7578 /* Setup whether or not to use alt functions/controls */
009b8f97
CM		 7579 switch (spec->quirk) {
7580 case QUIRK_SBZ:
7581 case QUIRK_R3DI:
47cdf76e 7582 spec->use_alt_controls = true;
009b8f97
CM		 7583 spec->use_alt_functions = true;
7584 break;
7585 default:
47cdf76e 7586 spec->use_alt_controls = false;
009b8f97
CM		 7587 spec->use_alt_functions = false;
7588 break;
7589 }
7590
5aaca44d
IM		 7591 spec->base_init_verbs = ca0132_base_init_verbs;
7592 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 7593
993884f6
CCC		 7594 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7595
95c6e9cb
IM		 7596 ca0132_init_chip(codec);
7597
7598 ca0132_config(codec);
7599
d5c016b5
GM		 7600 err = ca0132_prepare_verbs(codec);
7601 if (err < 0)
cc91ceaf 7602 goto error;
d5c016b5 7603
a73d511c
IM		 7604 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7605 if (err < 0)
cc91ceaf 7606 goto error;
a73d511c 7607
95c6e9cb 7608 return 0;
cc91ceaf
TI		 7609
7610 error:
7611 ca0132_free(codec);
7612 return err;
95c6e9cb
IM		 7613}
7614
7615/*
7616 * patch entries
7617 */
b9a94a9c
TI		 7618static struct hda_device_id snd_hda_id_ca0132[] = {
7619 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 7620 {} /* terminator */
7621};
b9a94a9c 7622MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 7623
7624MODULE_LICENSE("GPL");
406261ce 7625MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 7626
d8a766a1 7627static struct hda_codec_driver ca0132_driver = {
b9a94a9c 7628 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 7629};
7630
d8a766a1 7631module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)