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ALSA: hda/ca0132: Add PCI region2 iomap for SBZ
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb
IM		 34#include <sound/core.h>
35#include "hda_codec.h"
36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
52#define FLOAT_MINUS_5 0xc0a00000
53
ef6b2ead
IM		 54#define UNSOL_TAG_DSP 0x16
55
4aa3bb0c
IM		 56#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
57#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
58
59#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
60#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
61#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
62
63#define MASTERCONTROL 0x80
ef6b2ead
IM		 64#define MASTERCONTROL_ALLOC_DMA_CHAN 10
65#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 66
95c6e9cb
IM		 67#define WIDGET_CHIP_CTRL 0x15
68#define WIDGET_DSP_CTRL 0x16
69
4aa3bb0c
IM		 70#define MEM_CONNID_MICIN1 3
71#define MEM_CONNID_MICIN2 5
72#define MEM_CONNID_MICOUT1 12
73#define MEM_CONNID_MICOUT2 14
74#define MEM_CONNID_WUH 10
75#define MEM_CONNID_DSP 16
76#define MEM_CONNID_DMIC 100
77
78#define SCP_SET 0
79#define SCP_GET 1
80
01ef7dbf 81#define EFX_FILE "ctefx.bin"
8a19bcee
CM		 82#define SBZ_EFX_FILE "ctefx-sbz.bin"
83#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 84
24f3cede 85#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 86MODULE_FIRMWARE(EFX_FILE);
8a19bcee
CM		 87MODULE_FIRMWARE(SBZ_EFX_FILE);
88MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 89#endif
01ef7dbf 90
8a19bcee 91static const char *dirstr[2] = { "Playback", "Capture" };
ef6b2ead
IM		 92
93enum {
94 SPEAKER_OUT,
95 HEADPHONE_OUT
96};
97
98enum {
99 DIGITAL_MIC,
100 LINE_MIC_IN
101};
102
103enum {
104#define VNODE_START_NID 0x80
105 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
106 VNID_MIC,
107 VNID_HP_SEL,
108 VNID_AMIC1_SEL,
109 VNID_HP_ASEL,
110 VNID_AMIC1_ASEL,
111 VNODE_END_NID,
112#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
113
114#define EFFECT_START_NID 0x90
115#define OUT_EFFECT_START_NID EFFECT_START_NID
116 SURROUND = OUT_EFFECT_START_NID,
117 CRYSTALIZER,
118 DIALOG_PLUS,
119 SMART_VOLUME,
120 X_BASS,
121 EQUALIZER,
122 OUT_EFFECT_END_NID,
123#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
124
125#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
126 ECHO_CANCELLATION = IN_EFFECT_START_NID,
127 VOICE_FOCUS,
128 MIC_SVM,
129 NOISE_REDUCTION,
130 IN_EFFECT_END_NID,
131#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
132
133 VOICEFX = IN_EFFECT_END_NID,
134 PLAY_ENHANCEMENT,
135 CRYSTAL_VOICE,
136 EFFECT_END_NID
137#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
138};
139
140/* Effects values size*/
141#define EFFECT_VALS_MAX_COUNT 12
142
e8412ca4
DR		 143/* Latency introduced by DSP blocks in milliseconds. */
144#define DSP_CAPTURE_INIT_LATENCY 0
145#define DSP_CRYSTAL_VOICE_LATENCY 124
146#define DSP_PLAYBACK_INIT_LATENCY 13
147#define DSP_PLAY_ENHANCEMENT_LATENCY 30
148#define DSP_SPEAKER_OUT_LATENCY 7
149
ef6b2ead 150struct ct_effect {
975cc02a 151 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 152 hda_nid_t nid;
153 int mid; /*effect module ID*/
154 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
155 int direct; /* 0:output; 1:input*/
156 int params; /* number of default non-on/off params */
157 /*effect default values, 1st is on/off. */
158 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
159};
160
161#define EFX_DIR_OUT 0
162#define EFX_DIR_IN 1
163
164static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
165 { .name = "Surround",
166 .nid = SURROUND,
167 .mid = 0x96,
168 .reqs = {0, 1},
169 .direct = EFX_DIR_OUT,
170 .params = 1,
171 .def_vals = {0x3F800000, 0x3F2B851F}
172 },
173 { .name = "Crystalizer",
174 .nid = CRYSTALIZER,
175 .mid = 0x96,
176 .reqs = {7, 8},
177 .direct = EFX_DIR_OUT,
178 .params = 1,
179 .def_vals = {0x3F800000, 0x3F266666}
180 },
181 { .name = "Dialog Plus",
182 .nid = DIALOG_PLUS,
183 .mid = 0x96,
184 .reqs = {2, 3},
185 .direct = EFX_DIR_OUT,
186 .params = 1,
187 .def_vals = {0x00000000, 0x3F000000}
188 },
189 { .name = "Smart Volume",
190 .nid = SMART_VOLUME,
191 .mid = 0x96,
192 .reqs = {4, 5, 6},
193 .direct = EFX_DIR_OUT,
194 .params = 2,
195 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
196 },
197 { .name = "X-Bass",
198 .nid = X_BASS,
199 .mid = 0x96,
200 .reqs = {24, 23, 25},
201 .direct = EFX_DIR_OUT,
202 .params = 2,
203 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
204 },
205 { .name = "Equalizer",
206 .nid = EQUALIZER,
207 .mid = 0x96,
208 .reqs = {9, 10, 11, 12, 13, 14,
209 15, 16, 17, 18, 19, 20},
210 .direct = EFX_DIR_OUT,
211 .params = 11,
212 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
213 0x00000000, 0x00000000, 0x00000000, 0x00000000,
214 0x00000000, 0x00000000, 0x00000000, 0x00000000}
215 },
216 { .name = "Echo Cancellation",
217 .nid = ECHO_CANCELLATION,
218 .mid = 0x95,
219 .reqs = {0, 1, 2, 3},
220 .direct = EFX_DIR_IN,
221 .params = 3,
222 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
223 },
224 { .name = "Voice Focus",
225 .nid = VOICE_FOCUS,
226 .mid = 0x95,
227 .reqs = {6, 7, 8, 9},
228 .direct = EFX_DIR_IN,
229 .params = 3,
230 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
231 },
232 { .name = "Mic SVM",
233 .nid = MIC_SVM,
234 .mid = 0x95,
235 .reqs = {44, 45},
236 .direct = EFX_DIR_IN,
237 .params = 1,
238 .def_vals = {0x00000000, 0x3F3D70A4}
239 },
240 { .name = "Noise Reduction",
241 .nid = NOISE_REDUCTION,
242 .mid = 0x95,
243 .reqs = {4, 5},
244 .direct = EFX_DIR_IN,
245 .params = 1,
246 .def_vals = {0x3F800000, 0x3F000000}
247 },
248 { .name = "VoiceFX",
249 .nid = VOICEFX,
250 .mid = 0x95,
251 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
252 .direct = EFX_DIR_IN,
253 .params = 8,
254 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
255 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
256 0x00000000}
257 }
258};
259
260/* Tuning controls */
261#ifdef ENABLE_TUNING_CONTROLS
262
263enum {
264#define TUNING_CTL_START_NID 0xC0
265 WEDGE_ANGLE = TUNING_CTL_START_NID,
266 SVM_LEVEL,
267 EQUALIZER_BAND_0,
268 EQUALIZER_BAND_1,
269 EQUALIZER_BAND_2,
270 EQUALIZER_BAND_3,
271 EQUALIZER_BAND_4,
272 EQUALIZER_BAND_5,
273 EQUALIZER_BAND_6,
274 EQUALIZER_BAND_7,
275 EQUALIZER_BAND_8,
276 EQUALIZER_BAND_9,
277 TUNING_CTL_END_NID
278#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
279};
280
281struct ct_tuning_ctl {
975cc02a 282 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 283 hda_nid_t parent_nid;
284 hda_nid_t nid;
285 int mid; /*effect module ID*/
286 int req; /*effect module request*/
287 int direct; /* 0:output; 1:input*/
288 unsigned int def_val;/*effect default values*/
289};
290
291static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
292 { .name = "Wedge Angle",
293 .parent_nid = VOICE_FOCUS,
294 .nid = WEDGE_ANGLE,
295 .mid = 0x95,
296 .req = 8,
297 .direct = EFX_DIR_IN,
298 .def_val = 0x41F00000
299 },
300 { .name = "SVM Level",
301 .parent_nid = MIC_SVM,
302 .nid = SVM_LEVEL,
303 .mid = 0x95,
304 .req = 45,
305 .direct = EFX_DIR_IN,
306 .def_val = 0x3F3D70A4
307 },
308 { .name = "EQ Band0",
309 .parent_nid = EQUALIZER,
310 .nid = EQUALIZER_BAND_0,
311 .mid = 0x96,
312 .req = 11,
313 .direct = EFX_DIR_OUT,
314 .def_val = 0x00000000
315 },
316 { .name = "EQ Band1",
317 .parent_nid = EQUALIZER,
318 .nid = EQUALIZER_BAND_1,
319 .mid = 0x96,
320 .req = 12,
321 .direct = EFX_DIR_OUT,
322 .def_val = 0x00000000
323 },
324 { .name = "EQ Band2",
325 .parent_nid = EQUALIZER,
326 .nid = EQUALIZER_BAND_2,
327 .mid = 0x96,
328 .req = 13,
329 .direct = EFX_DIR_OUT,
330 .def_val = 0x00000000
331 },
332 { .name = "EQ Band3",
333 .parent_nid = EQUALIZER,
334 .nid = EQUALIZER_BAND_3,
335 .mid = 0x96,
336 .req = 14,
337 .direct = EFX_DIR_OUT,
338 .def_val = 0x00000000
339 },
340 { .name = "EQ Band4",
341 .parent_nid = EQUALIZER,
342 .nid = EQUALIZER_BAND_4,
343 .mid = 0x96,
344 .req = 15,
345 .direct = EFX_DIR_OUT,
346 .def_val = 0x00000000
347 },
348 { .name = "EQ Band5",
349 .parent_nid = EQUALIZER,
350 .nid = EQUALIZER_BAND_5,
351 .mid = 0x96,
352 .req = 16,
353 .direct = EFX_DIR_OUT,
354 .def_val = 0x00000000
355 },
356 { .name = "EQ Band6",
357 .parent_nid = EQUALIZER,
358 .nid = EQUALIZER_BAND_6,
359 .mid = 0x96,
360 .req = 17,
361 .direct = EFX_DIR_OUT,
362 .def_val = 0x00000000
363 },
364 { .name = "EQ Band7",
365 .parent_nid = EQUALIZER,
366 .nid = EQUALIZER_BAND_7,
367 .mid = 0x96,
368 .req = 18,
369 .direct = EFX_DIR_OUT,
370 .def_val = 0x00000000
371 },
372 { .name = "EQ Band8",
373 .parent_nid = EQUALIZER,
374 .nid = EQUALIZER_BAND_8,
375 .mid = 0x96,
376 .req = 19,
377 .direct = EFX_DIR_OUT,
378 .def_val = 0x00000000
379 },
380 { .name = "EQ Band9",
381 .parent_nid = EQUALIZER,
382 .nid = EQUALIZER_BAND_9,
383 .mid = 0x96,
384 .req = 20,
385 .direct = EFX_DIR_OUT,
386 .def_val = 0x00000000
387 }
388};
389#endif
390
391/* Voice FX Presets */
392#define VOICEFX_MAX_PARAM_COUNT 9
393
394struct ct_voicefx {
395 char *name;
396 hda_nid_t nid;
397 int mid;
398 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
399};
400
401struct ct_voicefx_preset {
402 char *name; /*preset name*/
403 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
404};
405
ccd7bd3d 406static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 407 .name = "VoiceFX Capture Switch",
408 .nid = VOICEFX,
409 .mid = 0x95,
410 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
411};
412
ccd7bd3d 413static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 414 { .name = "Neutral",
415 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
416 0x44FA0000, 0x3F800000, 0x3F800000,
417 0x3F800000, 0x00000000, 0x00000000 }
418 },
419 { .name = "Female2Male",
420 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
421 0x44FA0000, 0x3F19999A, 0x3F866666,
422 0x3F800000, 0x00000000, 0x00000000 }
423 },
424 { .name = "Male2Female",
425 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
426 0x450AC000, 0x4017AE14, 0x3F6B851F,
427 0x3F800000, 0x00000000, 0x00000000 }
428 },
429 { .name = "ScrappyKid",
430 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
431 0x44FA0000, 0x40400000, 0x3F28F5C3,
432 0x3F800000, 0x00000000, 0x00000000 }
433 },
434 { .name = "Elderly",
435 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
436 0x44E10000, 0x3FB33333, 0x3FB9999A,
437 0x3F800000, 0x3E3A2E43, 0x00000000 }
438 },
439 { .name = "Orc",
440 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
441 0x45098000, 0x3F266666, 0x3FC00000,
442 0x3F800000, 0x00000000, 0x00000000 }
443 },
444 { .name = "Elf",
445 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
446 0x45193000, 0x3F8E147B, 0x3F75C28F,
447 0x3F800000, 0x00000000, 0x00000000 }
448 },
449 { .name = "Dwarf",
450 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
451 0x45007000, 0x3F451EB8, 0x3F7851EC,
452 0x3F800000, 0x00000000, 0x00000000 }
453 },
454 { .name = "AlienBrute",
455 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
456 0x451F6000, 0x3F266666, 0x3FA7D945,
457 0x3F800000, 0x3CF5C28F, 0x00000000 }
458 },
459 { .name = "Robot",
460 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
461 0x44FA0000, 0x3FB2718B, 0x3F800000,
462 0xBC07010E, 0x00000000, 0x00000000 }
463 },
464 { .name = "Marine",
465 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
466 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
467 0x3F0A3D71, 0x00000000, 0x00000000 }
468 },
469 { .name = "Emo",
470 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
471 0x44FA0000, 0x3F800000, 0x3F800000,
472 0x3E4CCCCD, 0x00000000, 0x00000000 }
473 },
474 { .name = "DeepVoice",
475 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
476 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
477 0x3F800000, 0x00000000, 0x00000000 }
478 },
479 { .name = "Munchkin",
480 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
481 0x44FA0000, 0x3F800000, 0x3F1A043C,
482 0x3F800000, 0x00000000, 0x00000000 }
483 }
484};
485
95c6e9cb
IM		 486enum hda_cmd_vendor_io {
487 /* for DspIO node */
488 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
489 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
490
491 VENDOR_DSPIO_STATUS = 0xF01,
492 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
493 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
494 VENDOR_DSPIO_DSP_INIT = 0x703,
495 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
496 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
497
498 /* for ChipIO node */
499 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
500 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
501 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
502 VENDOR_CHIPIO_DATA_LOW = 0x300,
503 VENDOR_CHIPIO_DATA_HIGH = 0x400,
504
505 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
506 VENDOR_CHIPIO_STATUS = 0xF01,
507 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
508 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
509
4aa3bb0c
IM		 510 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
511 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
512
95c6e9cb 513 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 514 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 515
516 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
517 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
518 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
519 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
520 VENDOR_CHIPIO_FLAG_SET = 0x70F,
521 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 522 VENDOR_CHIPIO_PARAM_SET = 0x710,
523 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 524
525 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
526 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
527 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
528 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
529
4aa3bb0c
IM		 530 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
531 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
532 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
533 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
534
535 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
536 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
537 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
538 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
539 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
540 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
541
542 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 543};
544
545/*
546 * Control flag IDs
547 */
548enum control_flag_id {
549 /* Connection manager stream setup is bypassed/enabled */
550 CONTROL_FLAG_C_MGR = 0,
551 /* DSP DMA is bypassed/enabled */
552 CONTROL_FLAG_DMA = 1,
553 /* 8051 'idle' mode is disabled/enabled */
554 CONTROL_FLAG_IDLE_ENABLE = 2,
555 /* Tracker for the SPDIF-in path is bypassed/enabled */
556 CONTROL_FLAG_TRACKER = 3,
557 /* DigitalOut to Spdif2Out connection is disabled/enabled */
558 CONTROL_FLAG_SPDIF2OUT = 4,
559 /* Digital Microphone is disabled/enabled */
560 CONTROL_FLAG_DMIC = 5,
561 /* ADC_B rate is 48 kHz/96 kHz */
562 CONTROL_FLAG_ADC_B_96KHZ = 6,
563 /* ADC_C rate is 48 kHz/96 kHz */
564 CONTROL_FLAG_ADC_C_96KHZ = 7,
565 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
566 CONTROL_FLAG_DAC_96KHZ = 8,
567 /* DSP rate is 48 kHz/96 kHz */
568 CONTROL_FLAG_DSP_96KHZ = 9,
569 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
570 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
571 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
572 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
573 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
574 CONTROL_FLAG_DECODE_LOOP = 12,
575 /* De-emphasis filter on DAC-1 disabled/enabled */
576 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
577 /* De-emphasis filter on DAC-2 disabled/enabled */
578 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
579 /* De-emphasis filter on DAC-3 disabled/enabled */
580 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
581 /* High-pass filter on ADC_B disabled/enabled */
582 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
583 /* High-pass filter on ADC_C disabled/enabled */
584 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
585 /* Common mode on Port_A disabled/enabled */
586 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
587 /* Common mode on Port_D disabled/enabled */
588 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
589 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
590 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
591 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 592 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 593 /* ASI rate is 48kHz/96kHz */
594 CONTROL_FLAG_ASI_96KHZ = 22,
595 /* DAC power settings able to control attached ports no/yes */
596 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
597 /* Clock Stop OK reporting is disabled/enabled */
598 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
599 /* Number of control flags */
600 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
601};
602
603/*
604 * Control parameter IDs
605 */
4aa3bb0c 606enum control_param_id {
ef6b2ead
IM		 607 /* 0: None, 1: Mic1In*/
608 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 609 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
610 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 611 /* Port A output stage gain setting to use when 16 Ohm output
612 * impedance is selected*/
613 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
614 /* Port D output stage gain setting to use when 16 Ohm output
615 * impedance is selected*/
616 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 617
618 /* Stream Control */
619
620 /* Select stream with the given ID */
621 CONTROL_PARAM_STREAM_ID = 24,
622 /* Source connection point for the selected stream */
623 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
624 /* Destination connection point for the selected stream */
625 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
626 /* Number of audio channels in the selected stream */
627 CONTROL_PARAM_STREAMS_CHANNELS = 27,
628 /*Enable control for the selected stream */
629 CONTROL_PARAM_STREAM_CONTROL = 28,
630
631 /* Connection Point Control */
632
633 /* Select connection point with the given ID */
634 CONTROL_PARAM_CONN_POINT_ID = 29,
635 /* Connection point sample rate */
636 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
637
638 /* Node Control */
639
640 /* Select HDA node with the given ID */
641 CONTROL_PARAM_NODE_ID = 31
642};
643
644/*
645 * Dsp Io Status codes
646 */
647enum hda_vendor_status_dspio {
648 /* Success */
649 VENDOR_STATUS_DSPIO_OK = 0x00,
650 /* Busy, unable to accept new command, the host must retry */
651 VENDOR_STATUS_DSPIO_BUSY = 0x01,
652 /* SCP command queue is full */
653 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
654 /* SCP response queue is empty */
655 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
656};
657
658/*
659 * Chip Io Status codes
660 */
661enum hda_vendor_status_chipio {
662 /* Success */
663 VENDOR_STATUS_CHIPIO_OK = 0x00,
664 /* Busy, unable to accept new command, the host must retry */
665 VENDOR_STATUS_CHIPIO_BUSY = 0x01
666};
667
668/*
669 * CA0132 sample rate
670 */
671enum ca0132_sample_rate {
672 SR_6_000 = 0x00,
673 SR_8_000 = 0x01,
674 SR_9_600 = 0x02,
675 SR_11_025 = 0x03,
676 SR_16_000 = 0x04,
677 SR_22_050 = 0x05,
678 SR_24_000 = 0x06,
679 SR_32_000 = 0x07,
680 SR_44_100 = 0x08,
681 SR_48_000 = 0x09,
682 SR_88_200 = 0x0A,
683 SR_96_000 = 0x0B,
684 SR_144_000 = 0x0C,
685 SR_176_400 = 0x0D,
686 SR_192_000 = 0x0E,
687 SR_384_000 = 0x0F,
688
689 SR_COUNT = 0x10,
690
691 SR_RATE_UNKNOWN = 0x1F
692};
693
01ef7dbf
IM		 694enum dsp_download_state {
695 DSP_DOWNLOAD_FAILED = -1,
696 DSP_DOWNLOAD_INIT = 0,
697 DSP_DOWNLOADING = 1,
698 DSP_DOWNLOADED = 2
699};
700
01ef7dbf
IM		 701/* retrieve parameters from hda format */
702#define get_hdafmt_chs(fmt) (fmt & 0xf)
703#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
704#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
705#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
706
707/*
708 * CA0132 specific
709 */
710
711struct ca0132_spec {
a7e76271
IM		 712 struct snd_kcontrol_new *mixers[5];
713 unsigned int num_mixers;
5aaca44d
IM		 714 const struct hda_verb *base_init_verbs;
715 const struct hda_verb *base_exit_verbs;
d5c016b5
GM		 716 const struct hda_verb *chip_init_verbs;
717 struct hda_verb *spec_init_verbs;
01ef7dbf 718 struct auto_pin_cfg autocfg;
5aaca44d
IM		 719
720 /* Nodes configurations */
01ef7dbf
IM		 721 struct hda_multi_out multiout;
722 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
723 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 724 unsigned int num_outputs;
01ef7dbf
IM		 725 hda_nid_t input_pins[AUTO_PIN_LAST];
726 hda_nid_t adcs[AUTO_PIN_LAST];
727 hda_nid_t dig_out;
728 hda_nid_t dig_in;
729 unsigned int num_inputs;
a7e76271
IM		 730 hda_nid_t shared_mic_nid;
731 hda_nid_t shared_out_nid;
d5c016b5 732 hda_nid_t unsol_tag_hp;
63177afc 733 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 734 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 735
736 /* chip access */
737 struct mutex chipio_mutex; /* chip access mutex */
738 u32 curr_chip_addx;
739
740 /* DSP download related */
741 enum dsp_download_state dsp_state;
742 unsigned int dsp_stream_id;
743 unsigned int wait_scp;
744 unsigned int wait_scp_header;
745 unsigned int wait_num_data;
746 unsigned int scp_resp_header;
747 unsigned int scp_resp_data[4];
748 unsigned int scp_resp_count;
8a19bcee 749 bool alt_firmware_present;
5aaca44d
IM		 750
751 /* mixer and effects related */
752 unsigned char dmic_ctl;
753 int cur_out_type;
754 int cur_mic_type;
755 long vnode_lvol[VNODES_COUNT];
756 long vnode_rvol[VNODES_COUNT];
757 long vnode_lswitch[VNODES_COUNT];
758 long vnode_rswitch[VNODES_COUNT];
759 long effects_switch[EFFECTS_COUNT];
760 long voicefx_val;
761 long cur_mic_boost;
44f0c978 762
993884f6
CCC		 763 struct hda_codec *codec;
764 struct delayed_work unsol_hp_work;
d5c016b5 765 int quirk;
993884f6 766
44f0c978
IM		 767#ifdef ENABLE_TUNING_CONTROLS
768 long cur_ctl_vals[TUNING_CTLS_COUNT];
769#endif
aa31704f
CM		 770 /*
771 * Sound Blaster Z PCI region 2 iomem, used for input and output
772 * switching, and other unknown commands.
773 */
774 void __iomem *mem_base;
01ef7dbf
IM		 775};
776
d5c016b5
GM		 777/*
778 * CA0132 quirks table
779 */
780enum {
781 QUIRK_NONE,
782 QUIRK_ALIENWARE,
8a19bcee
CM		 783 QUIRK_SBZ,
784 QUIRK_R3DI,
d5c016b5
GM		 785};
786
fe14f39e
TI		 787static const struct hda_pintbl alienware_pincfgs[] = {
788 { 0x0b, 0x90170110 }, /* Builtin Speaker */
789 { 0x0c, 0x411111f0 }, /* N/A */
790 { 0x0d, 0x411111f0 }, /* N/A */
791 { 0x0e, 0x411111f0 }, /* N/A */
792 { 0x0f, 0x0321101f }, /* HP */
793 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
794 { 0x11, 0x03a11021 }, /* Mic */
795 { 0x12, 0xd5a30140 }, /* Builtin Mic */
796 { 0x13, 0x411111f0 }, /* N/A */
797 { 0x18, 0x411111f0 }, /* N/A */
798 {}
799};
800
63177afc
CM		 801/* Sound Blaster Z pin configs taken from Windows Driver */
802static const struct hda_pintbl sbz_pincfgs[] = {
803 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
804 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
805 { 0x0d, 0x014510f0 }, /* Digital Out */
806 { 0x0e, 0x01c510f0 }, /* SPDIF In */
807 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
808 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
809 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
810 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
811 { 0x13, 0x908700f0 }, /* What U Hear In*/
812 { 0x18, 0x50d000f0 }, /* N/A */
813 {}
814};
815
816/* Recon3D integrated pin configs taken from Windows Driver */
817static const struct hda_pintbl r3di_pincfgs[] = {
818 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
819 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
820 { 0x0d, 0x014510f0 }, /* Digital Out */
821 { 0x0e, 0x41c520f0 }, /* SPDIF In */
822 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
823 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
824 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
825 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
826 { 0x13, 0x908700f0 }, /* What U Hear In*/
827 { 0x18, 0x500000f0 }, /* N/A */
828 {}
829};
830
d5c016b5 831static const struct snd_pci_quirk ca0132_quirks[] = {
5328e1ea
GM		 832 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
833 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 834 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 835 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
836 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
837 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
838 SND_PCI_QUIRK(0x1458, 0xA036, "Recon3Di", QUIRK_R3DI),
d5c016b5
GM		 839 {}
840};
841
01ef7dbf
IM		 842/*
843 * CA0132 codec access
844 */
399ae725 845static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 846 unsigned int verb, unsigned int parm, unsigned int *res)
847{
848 unsigned int response;
849 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
850 *res = response;
851
852 return ((response == -1) ? -1 : 0);
853}
854
855static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
856 unsigned short converter_format, unsigned int *res)
857{
858 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
859 converter_format & 0xffff, res);
860}
861
862static int codec_set_converter_stream_channel(struct hda_codec *codec,
863 hda_nid_t nid, unsigned char stream,
864 unsigned char channel, unsigned int *res)
865{
866 unsigned char converter_stream_channel = 0;
867
868 converter_stream_channel = (stream << 4) | (channel & 0x0f);
869 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
870 converter_stream_channel, res);
871}
872
873/* Chip access helper function */
874static int chipio_send(struct hda_codec *codec,
875 unsigned int reg,
876 unsigned int data)
877{
878 unsigned int res;
6d67530e 879 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 880
881 /* send bits of data specified by reg */
882 do {
883 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
884 reg, data);
885 if (res == VENDOR_STATUS_CHIPIO_OK)
886 return 0;
6d67530e
IM		 887 msleep(20);
888 } while (time_before(jiffies, timeout));
889
01ef7dbf
IM		 890 return -EIO;
891}
892
893/*
894 * Write chip address through the vendor widget -- NOT protected by the Mutex!
895 */
896static int chipio_write_address(struct hda_codec *codec,
897 unsigned int chip_addx)
898{
4861af80 899 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 900 int res;
901
4861af80
IM		 902 if (spec->curr_chip_addx == chip_addx)
903 return 0;
904
01ef7dbf
IM		 905 /* send low 16 bits of the address */
906 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
907 chip_addx & 0xffff);
908
909 if (res != -EIO) {
910 /* send high 16 bits of the address */
911 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
912 chip_addx >> 16);
913 }
914
d1600401 915 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 916
4861af80 917 return res;
01ef7dbf
IM		 918}
919
920/*
921 * Write data through the vendor widget -- NOT protected by the Mutex!
922 */
01ef7dbf
IM		 923static int chipio_write_data(struct hda_codec *codec, unsigned int data)
924{
5aaca44d 925 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 926 int res;
927
928 /* send low 16 bits of the data */
929 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
930
931 if (res != -EIO) {
932 /* send high 16 bits of the data */
933 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
934 data >> 16);
935 }
936
5aaca44d
IM		 937 /*If no error encountered, automatically increment the address
938 as per chip behaviour*/
939 spec->curr_chip_addx = (res != -EIO) ?
d1600401 940 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 941 return res;
942}
943
d5c21b88
IM		 944/*
945 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
946 */
01ef7dbf
IM		 947static int chipio_write_data_multiple(struct hda_codec *codec,
948 const u32 *data,
949 unsigned int count)
950{
951 int status = 0;
952
953 if (data == NULL) {
4e76a883 954 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 955 return -EINVAL;
956 }
957
958 while ((count-- != 0) && (status == 0))
959 status = chipio_write_data(codec, *data++);
960
961 return status;
962}
963
964
965/*
966 * Read data through the vendor widget -- NOT protected by the Mutex!
967 */
968static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
969{
5aaca44d 970 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 971 int res;
972
973 /* post read */
974 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
975
976 if (res != -EIO) {
977 /* read status */
978 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
979 }
980
981 if (res != -EIO) {
982 /* read data */
983 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
984 VENDOR_CHIPIO_HIC_READ_DATA,
985 0);
986 }
987
5aaca44d
IM		 988 /*If no error encountered, automatically increment the address
989 as per chip behaviour*/
990 spec->curr_chip_addx = (res != -EIO) ?
d1600401 991 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 992 return res;
993}
994
995/*
996 * Write given value to the given address through the chip I/O widget.
997 * protected by the Mutex
998 */
999static int chipio_write(struct hda_codec *codec,
1000 unsigned int chip_addx, const unsigned int data)
1001{
1002 struct ca0132_spec *spec = codec->spec;
1003 int err;
1004
1005 mutex_lock(&spec->chipio_mutex);
1006
1007 /* write the address, and if successful proceed to write data */
1008 err = chipio_write_address(codec, chip_addx);
1009 if (err < 0)
1010 goto exit;
1011
1012 err = chipio_write_data(codec, data);
1013 if (err < 0)
1014 goto exit;
1015
1016exit:
1017 mutex_unlock(&spec->chipio_mutex);
1018 return err;
1019}
1020
d5c21b88
IM		 1021/*
1022 * Write multiple values to the given address through the chip I/O widget.
1023 * protected by the Mutex
1024 */
01ef7dbf
IM		 1025static int chipio_write_multiple(struct hda_codec *codec,
1026 u32 chip_addx,
1027 const u32 *data,
1028 unsigned int count)
1029{
1030 struct ca0132_spec *spec = codec->spec;
1031 int status;
1032
1033 mutex_lock(&spec->chipio_mutex);
4861af80 1034 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1035 if (status < 0)
1036 goto error;
1037
1038 status = chipio_write_data_multiple(codec, data, count);
1039error:
1040 mutex_unlock(&spec->chipio_mutex);
1041
1042 return status;
1043}
1044
1045/*
1046 * Read the given address through the chip I/O widget
1047 * protected by the Mutex
1048 */
1049static int chipio_read(struct hda_codec *codec,
1050 unsigned int chip_addx, unsigned int *data)
1051{
1052 struct ca0132_spec *spec = codec->spec;
1053 int err;
1054
1055 mutex_lock(&spec->chipio_mutex);
1056
1057 /* write the address, and if successful proceed to write data */
1058 err = chipio_write_address(codec, chip_addx);
1059 if (err < 0)
1060 goto exit;
1061
1062 err = chipio_read_data(codec, data);
1063 if (err < 0)
1064 goto exit;
1065
1066exit:
1067 mutex_unlock(&spec->chipio_mutex);
1068 return err;
1069}
1070
d5c21b88
IM		 1071/*
1072 * Set chip control flags through the chip I/O widget.
1073 */
01ef7dbf
IM		 1074static void chipio_set_control_flag(struct hda_codec *codec,
1075 enum control_flag_id flag_id,
1076 bool flag_state)
1077{
1078 unsigned int val;
1079 unsigned int flag_bit;
1080
1081 flag_bit = (flag_state ? 1 : 0);
1082 val = (flag_bit << 7) | (flag_id);
1083 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1084 VENDOR_CHIPIO_FLAG_SET, val);
1085}
1086
d5c21b88
IM		 1087/*
1088 * Set chip parameters through the chip I/O widget.
1089 */
01ef7dbf
IM		 1090static void chipio_set_control_param(struct hda_codec *codec,
1091 enum control_param_id param_id, int param_val)
1092{
1093 struct ca0132_spec *spec = codec->spec;
1094 int val;
1095
1096 if ((param_id < 32) && (param_val < 8)) {
1097 val = (param_val << 5) | (param_id);
1098 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1099 VENDOR_CHIPIO_PARAM_SET, val);
1100 } else {
1101 mutex_lock(&spec->chipio_mutex);
1102 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1103 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1104 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1105 param_id);
1106 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1107 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1108 param_val);
1109 }
1110 mutex_unlock(&spec->chipio_mutex);
1111 }
1112}
1113
d5c21b88
IM		 1114/*
1115 * Set sampling rate of the connection point.
1116 */
01ef7dbf
IM		 1117static void chipio_set_conn_rate(struct hda_codec *codec,
1118 int connid, enum ca0132_sample_rate rate)
1119{
1120 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1121 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1122 rate);
1123}
1124
d5c21b88
IM		 1125/*
1126 * Enable clocks.
1127 */
01ef7dbf
IM		 1128static void chipio_enable_clocks(struct hda_codec *codec)
1129{
1130 struct ca0132_spec *spec = codec->spec;
1131
1132 mutex_lock(&spec->chipio_mutex);
1133 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1134 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1135 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1136 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1137 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1138 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1139 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1140 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1141 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1142 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1143 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1144 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1145 mutex_unlock(&spec->chipio_mutex);
1146}
1147
1148/*
1149 * CA0132 DSP IO stuffs
1150 */
1151static int dspio_send(struct hda_codec *codec, unsigned int reg,
1152 unsigned int data)
1153{
b645d796 1154 int res;
6d67530e 1155 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1156
1157 /* send bits of data specified by reg to dsp */
1158 do {
1159 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1160 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1161 return res;
6d67530e
IM		 1162 msleep(20);
1163 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1164
1165 return -EIO;
1166}
1167
d5c21b88
IM		 1168/*
1169 * Wait for DSP to be ready for commands
1170 */
01ef7dbf
IM		 1171static void dspio_write_wait(struct hda_codec *codec)
1172{
4861af80
IM		 1173 int status;
1174 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1175
01ef7dbf 1176 do {
4861af80
IM		 1177 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1178 VENDOR_DSPIO_STATUS, 0);
1179 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1180 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1181 break;
1182 msleep(1);
1183 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1184}
1185
d5c21b88
IM		 1186/*
1187 * Write SCP data to DSP
1188 */
01ef7dbf
IM		 1189static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1190{
1191 struct ca0132_spec *spec = codec->spec;
1192 int status;
1193
1194 dspio_write_wait(codec);
1195
1196 mutex_lock(&spec->chipio_mutex);
1197 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1198 scp_data & 0xffff);
1199 if (status < 0)
1200 goto error;
1201
1202 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1203 scp_data >> 16);
1204 if (status < 0)
1205 goto error;
1206
1207 /* OK, now check if the write itself has executed*/
1208 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1209 VENDOR_DSPIO_STATUS, 0);
1210error:
1211 mutex_unlock(&spec->chipio_mutex);
1212
1213 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1214 -EIO : 0;
1215}
1216
d5c21b88
IM		 1217/*
1218 * Write multiple SCP data to DSP
1219 */
01ef7dbf
IM		 1220static int dspio_write_multiple(struct hda_codec *codec,
1221 unsigned int *buffer, unsigned int size)
1222{
1223 int status = 0;
1224 unsigned int count;
1225
a16fbb85 1226 if (buffer == NULL)
01ef7dbf
IM		 1227 return -EINVAL;
1228
1229 count = 0;
1230 while (count < size) {
1231 status = dspio_write(codec, *buffer++);
1232 if (status != 0)
1233 break;
1234 count++;
1235 }
1236
1237 return status;
1238}
1239
a73d511c
IM		 1240static int dspio_read(struct hda_codec *codec, unsigned int *data)
1241{
1242 int status;
1243
1244 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1245 if (status == -EIO)
1246 return status;
1247
1248 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1249 if (status == -EIO ||
1250 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1251 return -EIO;
1252
1253 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1254 VENDOR_DSPIO_SCP_READ_DATA, 0);
1255
1256 return 0;
1257}
1258
1259static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1260 unsigned int *buf_size, unsigned int size_count)
1261{
1262 int status = 0;
1263 unsigned int size = *buf_size;
1264 unsigned int count;
1265 unsigned int skip_count;
1266 unsigned int dummy;
1267
a16fbb85 1268 if (buffer == NULL)
a73d511c
IM		 1269 return -1;
1270
1271 count = 0;
1272 while (count < size && count < size_count) {
1273 status = dspio_read(codec, buffer++);
1274 if (status != 0)
1275 break;
1276 count++;
1277 }
1278
1279 skip_count = count;
1280 if (status == 0) {
1281 while (skip_count < size) {
1282 status = dspio_read(codec, &dummy);
1283 if (status != 0)
1284 break;
1285 skip_count++;
1286 }
1287 }
1288 *buf_size = count;
1289
1290 return status;
1291}
1292
d5c21b88
IM		 1293/*
1294 * Construct the SCP header using corresponding fields
1295 */
01ef7dbf
IM		 1296static inline unsigned int
1297make_scp_header(unsigned int target_id, unsigned int source_id,
1298 unsigned int get_flag, unsigned int req,
1299 unsigned int device_flag, unsigned int resp_flag,
1300 unsigned int error_flag, unsigned int data_size)
1301{
1302 unsigned int header = 0;
1303
1304 header = (data_size & 0x1f) << 27;
1305 header |= (error_flag & 0x01) << 26;
1306 header |= (resp_flag & 0x01) << 25;
1307 header |= (device_flag & 0x01) << 24;
1308 header |= (req & 0x7f) << 17;
1309 header |= (get_flag & 0x01) << 16;
1310 header |= (source_id & 0xff) << 8;
1311 header |= target_id & 0xff;
1312
1313 return header;
1314}
1315
d5c21b88
IM		 1316/*
1317 * Extract corresponding fields from SCP header
1318 */
01ef7dbf
IM		 1319static inline void
1320extract_scp_header(unsigned int header,
1321 unsigned int *target_id, unsigned int *source_id,
1322 unsigned int *get_flag, unsigned int *req,
1323 unsigned int *device_flag, unsigned int *resp_flag,
1324 unsigned int *error_flag, unsigned int *data_size)
1325{
1326 if (data_size)
1327 *data_size = (header >> 27) & 0x1f;
1328 if (error_flag)
1329 *error_flag = (header >> 26) & 0x01;
1330 if (resp_flag)
1331 *resp_flag = (header >> 25) & 0x01;
1332 if (device_flag)
1333 *device_flag = (header >> 24) & 0x01;
1334 if (req)
1335 *req = (header >> 17) & 0x7f;
1336 if (get_flag)
1337 *get_flag = (header >> 16) & 0x01;
1338 if (source_id)
1339 *source_id = (header >> 8) & 0xff;
1340 if (target_id)
1341 *target_id = header & 0xff;
1342}
1343
1344#define SCP_MAX_DATA_WORDS (16)
1345
1346/* Structure to contain any SCP message */
1347struct scp_msg {
1348 unsigned int hdr;
1349 unsigned int data[SCP_MAX_DATA_WORDS];
1350};
1351
a73d511c
IM		 1352static void dspio_clear_response_queue(struct hda_codec *codec)
1353{
1354 unsigned int dummy = 0;
1355 int status = -1;
1356
1357 /* clear all from the response queue */
1358 do {
1359 status = dspio_read(codec, &dummy);
1360 } while (status == 0);
1361}
1362
1363static int dspio_get_response_data(struct hda_codec *codec)
1364{
1365 struct ca0132_spec *spec = codec->spec;
1366 unsigned int data = 0;
1367 unsigned int count;
1368
1369 if (dspio_read(codec, &data) < 0)
1370 return -EIO;
1371
1372 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1373 spec->scp_resp_header = data;
1374 spec->scp_resp_count = data >> 27;
1375 count = spec->wait_num_data;
1376 dspio_read_multiple(codec, spec->scp_resp_data,
1377 &spec->scp_resp_count, count);
1378 return 0;
1379 }
1380
1381 return -EIO;
1382}
1383
d5c21b88
IM		 1384/*
1385 * Send SCP message to DSP
1386 */
01ef7dbf
IM		 1387static int dspio_send_scp_message(struct hda_codec *codec,
1388 unsigned char *send_buf,
1389 unsigned int send_buf_size,
1390 unsigned char *return_buf,
1391 unsigned int return_buf_size,
1392 unsigned int *bytes_returned)
1393{
1394 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1395 int status = -1;
1396 unsigned int scp_send_size = 0;
1397 unsigned int total_size;
1398 bool waiting_for_resp = false;
1399 unsigned int header;
1400 struct scp_msg *ret_msg;
1401 unsigned int resp_src_id, resp_target_id;
1402 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1403
1404 if (bytes_returned)
1405 *bytes_returned = 0;
1406
1407 /* get scp header from buffer */
1408 header = *((unsigned int *)send_buf);
1409 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1410 &device_flag, NULL, NULL, &data_size);
1411 scp_send_size = data_size + 1;
1412 total_size = (scp_send_size * 4);
1413
1414 if (send_buf_size < total_size)
1415 return -EINVAL;
1416
1417 if (get_flag || device_flag) {
1418 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1419 return -EINVAL;
1420
1421 spec->wait_scp_header = *((unsigned int *)send_buf);
1422
1423 /* swap source id with target id */
1424 resp_target_id = src_id;
1425 resp_src_id = target_id;
1426 spec->wait_scp_header &= 0xffff0000;
1427 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1428 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1429 spec->wait_scp = 1;
1430 waiting_for_resp = true;
1431 }
1432
1433 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1434 scp_send_size);
1435 if (status < 0) {
1436 spec->wait_scp = 0;
1437 return status;
1438 }
1439
1440 if (waiting_for_resp) {
6d67530e 1441 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1442 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1443 do {
1444 msleep(20);
6d67530e 1445 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1446 waiting_for_resp = false;
6d67530e 1447 if (!spec->wait_scp) {
01ef7dbf
IM		 1448 ret_msg = (struct scp_msg *)return_buf;
1449 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1450 memcpy(&ret_msg->data, spec->scp_resp_data,
1451 spec->wait_num_data);
1452 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1453 status = 0;
1454 } else {
1455 status = -EIO;
1456 }
1457 spec->wait_scp = 0;
1458 }
1459
1460 return status;
1461}
1462
d5c21b88
IM		 1463/**
1464 * Prepare and send the SCP message to DSP
1465 * @codec: the HDA codec
1466 * @mod_id: ID of the DSP module to send the command
1467 * @req: ID of request to send to the DSP module
1468 * @dir: SET or GET
1469 * @data: pointer to the data to send with the request, request specific
1470 * @len: length of the data, in bytes
1471 * @reply: point to the buffer to hold data returned for a reply
1472 * @reply_len: length of the reply buffer returned from GET
1473 *
1474 * Returns zero or a negative error code.
1475 */
01ef7dbf
IM		 1476static int dspio_scp(struct hda_codec *codec,
1477 int mod_id, int req, int dir, void *data, unsigned int len,
1478 void *reply, unsigned int *reply_len)
1479{
1480 int status = 0;
1481 struct scp_msg scp_send, scp_reply;
1482 unsigned int ret_bytes, send_size, ret_size;
1483 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1484 unsigned int reply_data_size;
1485
1486 memset(&scp_send, 0, sizeof(scp_send));
1487 memset(&scp_reply, 0, sizeof(scp_reply));
1488
1489 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1490 return -EINVAL;
1491
1492 if (dir == SCP_GET && reply == NULL) {
4e76a883 1493 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1494 return -EINVAL;
1495 }
1496
1497 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1498 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1499 return -EINVAL;
1500 }
1501
1502 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1503 0, 0, 0, len/sizeof(unsigned int));
1504 if (data != NULL && len > 0) {
1505 len = min((unsigned int)(sizeof(scp_send.data)), len);
1506 memcpy(scp_send.data, data, len);
1507 }
1508
1509 ret_bytes = 0;
1510 send_size = sizeof(unsigned int) + len;
1511 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1512 send_size, (unsigned char *)&scp_reply,
1513 sizeof(scp_reply), &ret_bytes);
1514
1515 if (status < 0) {
4e76a883 1516 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1517 return status;
1518 }
1519
1520 /* extract send and reply headers members */
1521 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1522 NULL, NULL, NULL, NULL, NULL);
1523 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1524 &reply_resp_flag, &reply_error_flag,
1525 &reply_data_size);
1526
1527 if (!send_get_flag)
1528 return 0;
1529
1530 if (reply_resp_flag && !reply_error_flag) {
1531 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1532 / sizeof(unsigned int);
1533
1534 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1535 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1536 return -EINVAL;
1537 } else if (ret_size != reply_data_size) {
4e76a883 1538 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1539 return -EINVAL;
46a049da
AB		 1540 } else if (!reply) {
1541 codec_dbg(codec, "NULL reply\n");
1542 return -EINVAL;
01ef7dbf
IM		 1543 } else {
1544 *reply_len = ret_size*sizeof(unsigned int);
1545 memcpy(reply, scp_reply.data, *reply_len);
1546 }
1547 } else {
4e76a883 1548 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1549 return -EIO;
1550 }
1551
1552 return status;
1553}
1554
5aaca44d
IM		 1555/*
1556 * Set DSP parameters
1557 */
1558static int dspio_set_param(struct hda_codec *codec, int mod_id,
1559 int req, void *data, unsigned int len)
1560{
1561 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1562}
1563
1564static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1565 int req, unsigned int data)
1566{
1567 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1568}
1569
d5c21b88
IM		 1570/*
1571 * Allocate a DSP DMA channel via an SCP message
1572 */
01ef7dbf
IM		 1573static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1574{
1575 int status = 0;
1576 unsigned int size = sizeof(dma_chan);
1577
4e76a883 1578 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
01ef7dbf
IM		 1579 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1580 SCP_GET, NULL, 0, dma_chan, &size);
1581
1582 if (status < 0) {
4e76a883 1583 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1584 return status;
1585 }
1586
1587 if ((*dma_chan + 1) == 0) {
4e76a883 1588 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1589 return -EBUSY;
1590 }
1591
4e76a883
TI		 1592 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1593 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1594
1595 return status;
1596}
1597
d5c21b88
IM		 1598/*
1599 * Free a DSP DMA via an SCP message
1600 */
01ef7dbf
IM		 1601static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1602{
1603 int status = 0;
1604 unsigned int dummy = 0;
1605
4e76a883
TI		 1606 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1607 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf
IM		 1608
1609 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1610 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1611
1612 if (status < 0) {
4e76a883 1613 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1614 return status;
1615 }
1616
4e76a883 1617 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1618
1619 return status;
1620}
1621
1622/*
d5c21b88 1623 * (Re)start the DSP
01ef7dbf
IM		 1624 */
1625static int dsp_set_run_state(struct hda_codec *codec)
1626{
1627 unsigned int dbg_ctrl_reg;
1628 unsigned int halt_state;
1629 int err;
1630
1631 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1632 if (err < 0)
1633 return err;
1634
1635 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1636 DSP_DBGCNTL_STATE_LOBIT;
1637
1638 if (halt_state != 0) {
1639 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1640 DSP_DBGCNTL_SS_MASK);
1641 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1642 dbg_ctrl_reg);
1643 if (err < 0)
1644 return err;
1645
1646 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1647 DSP_DBGCNTL_EXEC_MASK;
1648 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1649 dbg_ctrl_reg);
1650 if (err < 0)
1651 return err;
1652 }
1653
1654 return 0;
1655}
1656
d5c21b88
IM		 1657/*
1658 * Reset the DSP
1659 */
01ef7dbf
IM		 1660static int dsp_reset(struct hda_codec *codec)
1661{
1662 unsigned int res;
1663 int retry = 20;
1664
4e76a883 1665 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1666 do {
1667 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1668 retry--;
1669 } while (res == -EIO && retry);
1670
1671 if (!retry) {
4e76a883 1672 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1673 return -EIO;
1674 }
1675
1676 return 0;
1677}
1678
d5c21b88
IM		 1679/*
1680 * Convert chip address to DSP address
1681 */
01ef7dbf
IM		 1682static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1683 bool *code, bool *yram)
1684{
1685 *code = *yram = false;
1686
1687 if (UC_RANGE(chip_addx, 1)) {
1688 *code = true;
1689 return UC_OFF(chip_addx);
1690 } else if (X_RANGE_ALL(chip_addx, 1)) {
1691 return X_OFF(chip_addx);
1692 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1693 *yram = true;
1694 return Y_OFF(chip_addx);
1695 }
1696
4a8b89f9 1697 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 1698}
1699
d5c21b88
IM		 1700/*
1701 * Check if the DSP DMA is active
1702 */
01ef7dbf
IM		 1703static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1704{
1705 unsigned int dma_chnlstart_reg;
1706
1707 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1708
1709 return ((dma_chnlstart_reg & (1 <<
1710 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1711}
1712
1713static int dsp_dma_setup_common(struct hda_codec *codec,
1714 unsigned int chip_addx,
1715 unsigned int dma_chan,
1716 unsigned int port_map_mask,
1717 bool ovly)
1718{
1719 int status = 0;
1720 unsigned int chnl_prop;
1721 unsigned int dsp_addx;
1722 unsigned int active;
1723 bool code, yram;
1724
4e76a883 1725 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 1726
1727 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 1728 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 1729 return -EINVAL;
1730 }
1731
1732 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 1733 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 1734 return -EBUSY;
1735 }
1736
1737 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1738
1739 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1740 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1741 return -ENXIO;
1742 }
1743
1744 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1745 active = 0;
1746
4e76a883 1747 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 1748
1749 if (ovly) {
1750 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1751 &chnl_prop);
1752
1753 if (status < 0) {
4e76a883 1754 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 1755 return status;
1756 }
4e76a883 1757 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 1758 }
1759
1760 if (!code)
1761 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1762 else
1763 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1764
1765 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1766
1767 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1768 if (status < 0) {
4e76a883 1769 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 1770 return status;
1771 }
4e76a883 1772 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 1773
1774 if (ovly) {
1775 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1776 &active);
1777
1778 if (status < 0) {
4e76a883 1779 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 1780 return status;
1781 }
4e76a883 1782 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 1783 }
1784
1785 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1786 DSPDMAC_ACTIVE_AAR_MASK;
1787
1788 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1789 if (status < 0) {
4e76a883 1790 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 1791 return status;
1792 }
1793
4e76a883 1794 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 1795
1796 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1797 port_map_mask);
1798 if (status < 0) {
4e76a883 1799 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 1800 return status;
1801 }
4e76a883 1802 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 1803
1804 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1805 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1806 if (status < 0) {
4e76a883 1807 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 1808 return status;
1809 }
4e76a883 1810 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 1811
4e76a883 1812 codec_dbg(codec,
01ef7dbf
IM		 1813 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1814 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1815 chip_addx, dsp_addx, dma_chan,
1816 port_map_mask, chnl_prop, active);
1817
4e76a883 1818 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 1819
1820 return 0;
1821}
1822
d5c21b88
IM		 1823/*
1824 * Setup the DSP DMA per-transfer-specific registers
1825 */
01ef7dbf
IM		 1826static int dsp_dma_setup(struct hda_codec *codec,
1827 unsigned int chip_addx,
1828 unsigned int count,
1829 unsigned int dma_chan)
1830{
1831 int status = 0;
1832 bool code, yram;
1833 unsigned int dsp_addx;
1834 unsigned int addr_field;
1835 unsigned int incr_field;
1836 unsigned int base_cnt;
1837 unsigned int cur_cnt;
1838 unsigned int dma_cfg = 0;
1839 unsigned int adr_ofs = 0;
1840 unsigned int xfr_cnt = 0;
1841 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1842 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1843
4e76a883 1844 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 1845
1846 if (count > max_dma_count) {
4e76a883 1847 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 1848 return -EINVAL;
1849 }
1850
1851 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1852 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1853 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1854 return -ENXIO;
1855 }
1856
4e76a883 1857 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 1858
1859 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1860 incr_field = 0;
1861
1862 if (!code) {
1863 addr_field <<= 1;
1864 if (yram)
1865 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1866
1867 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1868 }
1869
1870 dma_cfg = addr_field + incr_field;
1871 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1872 dma_cfg);
1873 if (status < 0) {
4e76a883 1874 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 1875 return status;
1876 }
4e76a883 1877 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 1878
1879 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1880 (code ? 0 : 1));
1881
1882 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1883 adr_ofs);
1884 if (status < 0) {
4e76a883 1885 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 1886 return status;
1887 }
4e76a883 1888 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 1889
1890 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1891
1892 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1893
1894 xfr_cnt = base_cnt | cur_cnt;
1895
1896 status = chipio_write(codec,
1897 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1898 if (status < 0) {
4e76a883 1899 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 1900 return status;
1901 }
4e76a883 1902 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 1903
4e76a883 1904 codec_dbg(codec,
01ef7dbf
IM		 1905 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1906 "ADROFS=0x%x, XFRCNT=0x%x\n",
1907 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1908
4e76a883 1909 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 1910
1911 return 0;
1912}
1913
d5c21b88
IM		 1914/*
1915 * Start the DSP DMA
1916 */
01ef7dbf
IM		 1917static int dsp_dma_start(struct hda_codec *codec,
1918 unsigned int dma_chan, bool ovly)
1919{
1920 unsigned int reg = 0;
1921 int status = 0;
1922
4e76a883 1923 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 1924
1925 if (ovly) {
1926 status = chipio_read(codec,
1927 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1928
1929 if (status < 0) {
4e76a883 1930 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1931 return status;
1932 }
4e76a883 1933 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 1934
1935 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1936 DSPDMAC_CHNLSTART_DIS_MASK);
1937 }
1938
1939 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1940 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1941 if (status < 0) {
4e76a883 1942 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1943 return status;
1944 }
4e76a883 1945 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 1946
1947 return status;
1948}
1949
d5c21b88
IM		 1950/*
1951 * Stop the DSP DMA
1952 */
01ef7dbf
IM		 1953static int dsp_dma_stop(struct hda_codec *codec,
1954 unsigned int dma_chan, bool ovly)
1955{
1956 unsigned int reg = 0;
1957 int status = 0;
1958
4e76a883 1959 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 1960
1961 if (ovly) {
1962 status = chipio_read(codec,
1963 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1964
1965 if (status < 0) {
4e76a883 1966 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1967 return status;
1968 }
4e76a883 1969 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 1970 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1971 DSPDMAC_CHNLSTART_DIS_MASK);
1972 }
1973
1974 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1975 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1976 if (status < 0) {
4e76a883 1977 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1978 return status;
1979 }
4e76a883 1980 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 1981
1982 return status;
1983}
1984
d5c21b88
IM		 1985/**
1986 * Allocate router ports
1987 *
1988 * @codec: the HDA codec
1989 * @num_chans: number of channels in the stream
1990 * @ports_per_channel: number of ports per channel
1991 * @start_device: start device
1992 * @port_map: pointer to the port list to hold the allocated ports
1993 *
1994 * Returns zero or a negative error code.
1995 */
01ef7dbf
IM		 1996static int dsp_allocate_router_ports(struct hda_codec *codec,
1997 unsigned int num_chans,
1998 unsigned int ports_per_channel,
1999 unsigned int start_device,
2000 unsigned int *port_map)
2001{
2002 int status = 0;
2003 int res;
2004 u8 val;
2005
2006 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2007 if (status < 0)
2008 return status;
2009
2010 val = start_device << 6;
2011 val |= (ports_per_channel - 1) << 4;
2012 val |= num_chans - 1;
2013
2014 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2015 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2016 val);
2017
2018 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2019 VENDOR_CHIPIO_PORT_ALLOC_SET,
2020 MEM_CONNID_DSP);
2021
2022 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2023 if (status < 0)
2024 return status;
2025
2026 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2027 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2028
2029 *port_map = res;
2030
2031 return (res < 0) ? res : 0;
2032}
2033
d5c21b88
IM		 2034/*
2035 * Free router ports
2036 */
01ef7dbf
IM		 2037static int dsp_free_router_ports(struct hda_codec *codec)
2038{
2039 int status = 0;
2040
2041 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2042 if (status < 0)
2043 return status;
2044
2045 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2046 VENDOR_CHIPIO_PORT_FREE_SET,
2047 MEM_CONNID_DSP);
2048
2049 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2050
2051 return status;
2052}
2053
d5c21b88
IM		 2054/*
2055 * Allocate DSP ports for the download stream
2056 */
01ef7dbf
IM		 2057static int dsp_allocate_ports(struct hda_codec *codec,
2058 unsigned int num_chans,
2059 unsigned int rate_multi, unsigned int *port_map)
2060{
2061 int status;
2062
4e76a883 2063 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2064
2065 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2066 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2067 return -EINVAL;
2068 }
2069
2070 status = dsp_allocate_router_ports(codec, num_chans,
2071 rate_multi, 0, port_map);
2072
4e76a883 2073 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2074
2075 return status;
2076}
2077
01ef7dbf
IM		 2078static int dsp_allocate_ports_format(struct hda_codec *codec,
2079 const unsigned short fmt,
2080 unsigned int *port_map)
2081{
2082 int status;
2083 unsigned int num_chans;
2084
2085 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2086 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2087 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2088
2089 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2090 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2091 return -EINVAL;
2092 }
2093
2094 num_chans = get_hdafmt_chs(fmt) + 1;
2095
2096 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2097
2098 return status;
2099}
2100
d5c21b88
IM		 2101/*
2102 * free DSP ports
2103 */
2104static int dsp_free_ports(struct hda_codec *codec)
2105{
2106 int status;
2107
4e76a883 2108 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2109
2110 status = dsp_free_router_ports(codec);
2111 if (status < 0) {
4e76a883 2112 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2113 return status;
2114 }
4e76a883 2115 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2116
2117 return status;
2118}
2119
01ef7dbf
IM		 2120/*
2121 * HDA DMA engine stuffs for DSP code download
2122 */
2123struct dma_engine {
2124 struct hda_codec *codec;
2125 unsigned short m_converter_format;
2126 struct snd_dma_buffer *dmab;
2127 unsigned int buf_size;
2128};
2129
2130
2131enum dma_state {
2132 DMA_STATE_STOP = 0,
2133 DMA_STATE_RUN = 1
2134};
2135
6194b99d 2136static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2137 unsigned int sample_rate,
2138 unsigned short channels,
01ef7dbf
IM		 2139 unsigned short *hda_format)
2140{
2141 unsigned int format_val;
2142
b7d023e1
TI		 2143 format_val = snd_hdac_calc_stream_format(sample_rate,
2144 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2145
2146 if (hda_format)
2147 *hda_format = (unsigned short)format_val;
2148
2149 return 0;
2150}
2151
d5c21b88
IM		 2152/*
2153 * Reset DMA for DSP download
2154 */
01ef7dbf
IM		 2155static int dma_reset(struct dma_engine *dma)
2156{
2157 struct hda_codec *codec = dma->codec;
2158 struct ca0132_spec *spec = codec->spec;
2159 int status;
2160
b3667bd7 2161 if (dma->dmab->area)
01ef7dbf
IM		 2162 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2163
2164 status = snd_hda_codec_load_dsp_prepare(codec,
2165 dma->m_converter_format,
2166 dma->buf_size,
2167 dma->dmab);
2168 if (status < 0)
2169 return status;
2170 spec->dsp_stream_id = status;
2171 return 0;
2172}
2173
2174static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2175{
01ef7dbf
IM		 2176 bool cmd;
2177
01ef7dbf
IM		 2178 switch (state) {
2179 case DMA_STATE_STOP:
2180 cmd = false;
2181 break;
2182 case DMA_STATE_RUN:
2183 cmd = true;
2184 break;
2185 default:
c41999a2
DH		 2186 return 0;
2187 }
01ef7dbf
IM		 2188
2189 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2190 return 0;
95c6e9cb
IM		 2191}
2192
01ef7dbf
IM		 2193static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2194{
2195 return dma->dmab->bytes;
2196}
95c6e9cb 2197
01ef7dbf
IM		 2198static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2199{
2200 return dma->dmab->area;
2201}
95c6e9cb 2202
01ef7dbf
IM		 2203static int dma_xfer(struct dma_engine *dma,
2204 const unsigned int *data,
2205 unsigned int count)
2206{
2207 memcpy(dma->dmab->area, data, count);
2208 return 0;
2209}
95c6e9cb 2210
01ef7dbf
IM		 2211static void dma_get_converter_format(
2212 struct dma_engine *dma,
2213 unsigned short *format)
2214{
2215 if (format)
2216 *format = dma->m_converter_format;
2217}
95c6e9cb 2218
01ef7dbf 2219static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2220{
01ef7dbf 2221 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2222
01ef7dbf 2223 return spec->dsp_stream_id;
95c6e9cb
IM		 2224}
2225
01ef7dbf
IM		 2226struct dsp_image_seg {
2227 u32 magic;
2228 u32 chip_addr;
2229 u32 count;
2230 u32 data[0];
2231};
2232
2233static const u32 g_magic_value = 0x4c46584d;
2234static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2235
2236static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2237{
01ef7dbf
IM		 2238 return p->magic == g_magic_value;
2239}
95c6e9cb 2240
01ef7dbf
IM		 2241static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2242{
2243 return g_chip_addr_magic_value == p->chip_addr;
2244}
95c6e9cb 2245
01ef7dbf
IM		 2246static bool is_last(const struct dsp_image_seg *p)
2247{
2248 return p->count == 0;
2249}
95c6e9cb 2250
01ef7dbf
IM		 2251static size_t dsp_sizeof(const struct dsp_image_seg *p)
2252{
2253 return sizeof(*p) + p->count*sizeof(u32);
2254}
2255
2256static const struct dsp_image_seg *get_next_seg_ptr(
2257 const struct dsp_image_seg *p)
2258{
2259 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2260}
2261
2262/*
01ef7dbf 2263 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2264 */
8ae3124b 2265#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2266
d5c21b88
IM		 2267/*
2268 * Program a list of address/data pairs via the ChipIO widget.
2269 * The segment data is in the format of successive pairs of words.
2270 * These are repeated as indicated by the segment's count field.
2271 */
01ef7dbf
IM		 2272static int dspxfr_hci_write(struct hda_codec *codec,
2273 const struct dsp_image_seg *fls)
95c6e9cb 2274{
01ef7dbf
IM		 2275 int status;
2276 const u32 *data;
2277 unsigned int count;
95c6e9cb 2278
01ef7dbf 2279 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2280 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2281 return -EINVAL;
95c6e9cb
IM		 2282 }
2283
01ef7dbf
IM		 2284 count = fls->count;
2285 data = (u32 *)(fls->data);
2286 while (count >= 2) {
2287 status = chipio_write(codec, data[0], data[1]);
2288 if (status < 0) {
4e76a883 2289 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2290 return status;
2291 }
2292 count -= 2;
2293 data += 2;
2294 }
2295 return 0;
95c6e9cb
IM		 2296}
2297
d5c21b88
IM		 2298/**
2299 * Write a block of data into DSP code or data RAM using pre-allocated
2300 * DMA engine.
2301 *
2302 * @codec: the HDA codec
2303 * @fls: pointer to a fast load image
2304 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2305 * no relocation
2306 * @dma_engine: pointer to DMA engine to be used for DSP download
2307 * @dma_chan: The number of DMA channels used for DSP download
2308 * @port_map_mask: port mapping
2309 * @ovly: TRUE if overlay format is required
2310 *
2311 * Returns zero or a negative error code.
2312 */
01ef7dbf
IM		 2313static int dspxfr_one_seg(struct hda_codec *codec,
2314 const struct dsp_image_seg *fls,
2315 unsigned int reloc,
2316 struct dma_engine *dma_engine,
2317 unsigned int dma_chan,
2318 unsigned int port_map_mask,
2319 bool ovly)
95c6e9cb 2320{
406261ce 2321 int status = 0;
01ef7dbf
IM		 2322 bool comm_dma_setup_done = false;
2323 const unsigned int *data;
2324 unsigned int chip_addx;
2325 unsigned int words_to_write;
2326 unsigned int buffer_size_words;
2327 unsigned char *buffer_addx;
2328 unsigned short hda_format;
2329 unsigned int sample_rate_div;
2330 unsigned int sample_rate_mul;
2331 unsigned int num_chans;
2332 unsigned int hda_frame_size_words;
2333 unsigned int remainder_words;
2334 const u32 *data_remainder;
2335 u32 chip_addx_remainder;
2336 unsigned int run_size_words;
2337 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2338 unsigned long timeout;
2339 bool dma_active;
01ef7dbf
IM		 2340
2341 if (fls == NULL)
2342 return -EINVAL;
2343 if (is_hci_prog_list_seg(fls)) {
2344 hci_write = fls;
2345 fls = get_next_seg_ptr(fls);
2346 }
95c6e9cb 2347
01ef7dbf 2348 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2349 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2350 return dspxfr_hci_write(codec, hci_write);
2351 }
95c6e9cb 2352
01ef7dbf 2353 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2354 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2355 return -EINVAL;
95c6e9cb
IM		 2356 }
2357
01ef7dbf
IM		 2358 data = fls->data;
2359 chip_addx = fls->chip_addr,
2360 words_to_write = fls->count;
2361
2362 if (!words_to_write)
2363 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2364 if (reloc)
2365 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2366
2367 if (!UC_RANGE(chip_addx, words_to_write) &&
2368 !X_RANGE_ALL(chip_addx, words_to_write) &&
2369 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2370 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2371 return -EINVAL;
95c6e9cb
IM		 2372 }
2373
01ef7dbf
IM		 2374 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2375 sizeof(u32);
2376
2377 buffer_addx = dma_get_buffer_addr(dma_engine);
2378
2379 if (buffer_addx == NULL) {
4e76a883 2380 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2381 return -EINVAL;
2382 }
2383
2384 dma_get_converter_format(dma_engine, &hda_format);
2385 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2386 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2387 num_chans = get_hdafmt_chs(hda_format) + 1;
2388
2389 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2390 (num_chans * sample_rate_mul / sample_rate_div));
2391
3bc085a1 2392 if (hda_frame_size_words == 0) {
4e76a883 2393 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2394 return -EINVAL;
2395 }
2396
01ef7dbf
IM		 2397 buffer_size_words = min(buffer_size_words,
2398 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2399 65536 : 32768));
2400 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2401 codec_dbg(codec,
01ef7dbf
IM		 2402 "chpadr=0x%08x frmsz=%u nchan=%u "
2403 "rate_mul=%u div=%u bufsz=%u\n",
2404 chip_addx, hda_frame_size_words, num_chans,
2405 sample_rate_mul, sample_rate_div, buffer_size_words);
2406
3bc085a1 2407 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2408 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2409 return -EINVAL;
2410 }
2411
2412 remainder_words = words_to_write % hda_frame_size_words;
2413 data_remainder = data;
2414 chip_addx_remainder = chip_addx;
2415
2416 data += remainder_words;
2417 chip_addx += remainder_words*sizeof(u32);
2418 words_to_write -= remainder_words;
2419
2420 while (words_to_write != 0) {
2421 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2422 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2423 words_to_write, run_size_words, remainder_words);
2424 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2425 if (!comm_dma_setup_done) {
2426 status = dsp_dma_stop(codec, dma_chan, ovly);
2427 if (status < 0)
425a7880 2428 return status;
01ef7dbf
IM		 2429 status = dsp_dma_setup_common(codec, chip_addx,
2430 dma_chan, port_map_mask, ovly);
2431 if (status < 0)
2432 return status;
2433 comm_dma_setup_done = true;
2434 }
2435
2436 status = dsp_dma_setup(codec, chip_addx,
2437 run_size_words, dma_chan);
2438 if (status < 0)
2439 return status;
2440 status = dsp_dma_start(codec, dma_chan, ovly);
2441 if (status < 0)
2442 return status;
2443 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2444 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2445 return -EIO;
2446 }
2447 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2448 if (status < 0)
2449 return status;
2450 if (remainder_words != 0) {
2451 status = chipio_write_multiple(codec,
2452 chip_addx_remainder,
2453 data_remainder,
2454 remainder_words);
b3667bd7
TI		 2455 if (status < 0)
2456 return status;
01ef7dbf
IM		 2457 remainder_words = 0;
2458 }
2459 if (hci_write) {
2460 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2461 if (status < 0)
2462 return status;
01ef7dbf
IM		 2463 hci_write = NULL;
2464 }
6d67530e
IM		 2465
2466 timeout = jiffies + msecs_to_jiffies(2000);
2467 do {
2468 dma_active = dsp_is_dma_active(codec, dma_chan);
2469 if (!dma_active)
01ef7dbf 2470 break;
6d67530e
IM		 2471 msleep(20);
2472 } while (time_before(jiffies, timeout));
2473 if (dma_active)
2474 break;
2475
4e76a883 2476 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2477 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2478 status = dma_reset(dma_engine);
01ef7dbf
IM		 2479
2480 if (status < 0)
2481 return status;
2482
2483 data += run_size_words;
2484 chip_addx += run_size_words*sizeof(u32);
2485 words_to_write -= run_size_words;
2486 }
2487
2488 if (remainder_words != 0) {
2489 status = chipio_write_multiple(codec, chip_addx_remainder,
2490 data_remainder, remainder_words);
2491 }
2492
2493 return status;
95c6e9cb
IM		 2494}
2495
d5c21b88
IM		 2496/**
2497 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2498 *
2499 * @codec: the HDA codec
2500 * @fls_data: pointer to a fast load image
2501 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2502 * no relocation
e97249dd 2503 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2504 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2505 * @ovly: TRUE if overlay format is required
2506 *
2507 * Returns zero or a negative error code.
2508 */
01ef7dbf
IM		 2509static int dspxfr_image(struct hda_codec *codec,
2510 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2511 unsigned int reloc,
2512 unsigned int sample_rate,
2513 unsigned short channels,
01ef7dbf 2514 bool ovly)
95c6e9cb
IM		 2515{
2516 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2517 int status;
2518 unsigned short hda_format = 0;
2519 unsigned int response;
2520 unsigned char stream_id = 0;
2521 struct dma_engine *dma_engine;
2522 unsigned int dma_chan;
2523 unsigned int port_map_mask;
2524
2525 if (fls_data == NULL)
2526 return -EINVAL;
2527
2528 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2529 if (!dma_engine)
2530 return -ENOMEM;
95c6e9cb 2531
01ef7dbf
IM		 2532 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2533 if (!dma_engine->dmab) {
549e8292
TI		 2534 kfree(dma_engine);
2535 return -ENOMEM;
01ef7dbf 2536 }
95c6e9cb 2537
01ef7dbf 2538 dma_engine->codec = codec;
6194b99d 2539 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2540 dma_engine->m_converter_format = hda_format;
2541 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2542 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2543
8ae3124b 2544 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2545
2546 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2547 hda_format, &response);
2548
2549 if (status < 0) {
4e76a883 2550 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2551 goto exit;
2552 }
2553
2554 status = snd_hda_codec_load_dsp_prepare(codec,
2555 dma_engine->m_converter_format,
2556 dma_engine->buf_size,
2557 dma_engine->dmab);
2558 if (status < 0)
95c6e9cb 2559 goto exit;
01ef7dbf
IM		 2560 spec->dsp_stream_id = status;
2561
2562 if (ovly) {
2563 status = dspio_alloc_dma_chan(codec, &dma_chan);
2564 if (status < 0) {
4e76a883 2565 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2566 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2567 goto exit;
2568 }
2569 }
95c6e9cb 2570
01ef7dbf
IM		 2571 port_map_mask = 0;
2572 status = dsp_allocate_ports_format(codec, hda_format,
2573 &port_map_mask);
2574 if (status < 0) {
4e76a883 2575 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2576 goto exit;
2577 }
2578
2579 stream_id = dma_get_stream_id(dma_engine);
2580 status = codec_set_converter_stream_channel(codec,
2581 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2582 if (status < 0) {
4e76a883 2583 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2584 goto exit;
2585 }
2586
2587 while ((fls_data != NULL) && !is_last(fls_data)) {
2588 if (!is_valid(fls_data)) {
4e76a883 2589 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2590 status = -EINVAL;
2591 goto exit;
2592 }
2593 status = dspxfr_one_seg(codec, fls_data, reloc,
2594 dma_engine, dma_chan,
2595 port_map_mask, ovly);
2596 if (status < 0)
2597 break;
2598
2599 if (is_hci_prog_list_seg(fls_data))
2600 fls_data = get_next_seg_ptr(fls_data);
2601
2602 if ((fls_data != NULL) && !is_last(fls_data))
2603 fls_data = get_next_seg_ptr(fls_data);
2604 }
2605
2606 if (port_map_mask != 0)
2607 status = dsp_free_ports(codec);
2608
2609 if (status < 0)
95c6e9cb
IM		 2610 goto exit;
2611
01ef7dbf
IM		 2612 status = codec_set_converter_stream_channel(codec,
2613 WIDGET_CHIP_CTRL, 0, 0, &response);
2614
95c6e9cb 2615exit:
01ef7dbf
IM		 2616 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2617 dspio_free_dma_chan(codec, dma_chan);
2618
b3667bd7 2619 if (dma_engine->dmab->area)
01ef7dbf
IM		 2620 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2621 kfree(dma_engine->dmab);
2622 kfree(dma_engine);
2623
2624 return status;
95c6e9cb
IM		 2625}
2626
2627/*
01ef7dbf 2628 * CA0132 DSP download stuffs.
95c6e9cb 2629 */
01ef7dbf 2630static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2631{
4e76a883 2632 codec_dbg(codec, "---- dspload_post_setup ------\n");
95c6e9cb 2633
01ef7dbf
IM		 2634 /*set DSP speaker to 2.0 configuration*/
2635 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2636 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2637
01ef7dbf
IM		 2638 /*update write pointer*/
2639 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2640}
95c6e9cb 2641
d5c21b88 2642/**
e60b2c7f 2643 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2644 *
2645 * @codec: the HDA codec
2646 * @fls: pointer to a fast load image
2647 * @ovly: TRUE if overlay format is required
2648 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2649 * no relocation
2650 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2651 * @router_chans: number of audio router channels to be allocated (0 means use
2652 * internal defaults; max is 32)
2653 *
e60b2c7f
TI		 2654 * Download DSP from a DSP Image Fast Load structure. This structure is a
2655 * linear, non-constant sized element array of structures, each of which
2656 * contain the count of the data to be loaded, the data itself, and the
2657 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2658 * Returns zero or a negative error code.
2659 */
01ef7dbf
IM		 2660static int dspload_image(struct hda_codec *codec,
2661 const struct dsp_image_seg *fls,
2662 bool ovly,
2663 unsigned int reloc,
2664 bool autostart,
2665 int router_chans)
2666{
2667 int status = 0;
e97249dd
IM		 2668 unsigned int sample_rate;
2669 unsigned short channels;
01ef7dbf 2670
4e76a883 2671 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2672 if (router_chans == 0) {
2673 if (!ovly)
2674 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2675 else
2676 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2677 }
95c6e9cb 2678
e97249dd
IM		 2679 sample_rate = 48000;
2680 channels = (unsigned short)router_chans;
01ef7dbf 2681
e97249dd
IM		 2682 while (channels > 16) {
2683 sample_rate *= 2;
2684 channels /= 2;
01ef7dbf
IM		 2685 }
2686
01ef7dbf 2687 do {
4e76a883 2688 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 2689 if (!ovly)
2690 status = dsp_reset(codec);
2691
2692 if (status < 0)
2693 break;
2694
4e76a883 2695 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 2696 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2697 ovly);
01ef7dbf
IM		 2698
2699 if (status < 0)
2700 break;
2701
4e76a883 2702 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 2703 if (autostart && !ovly) {
2704 dspload_post_setup(codec);
2705 status = dsp_set_run_state(codec);
2706 }
2707
4e76a883 2708 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 2709 } while (0);
2710
2711 return status;
2712}
2713
f664417e 2714#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 2715static bool dspload_is_loaded(struct hda_codec *codec)
2716{
2717 unsigned int data = 0;
2718 int status = 0;
2719
2720 status = chipio_read(codec, 0x40004, &data);
2721 if ((status < 0) || (data != 1))
2722 return false;
2723
2724 return true;
2725}
f664417e
TI		 2726#else
2727#define dspload_is_loaded(codec) false
2728#endif
01ef7dbf
IM		 2729
2730static bool dspload_wait_loaded(struct hda_codec *codec)
2731{
6d67530e 2732 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 2733
2734 do {
01ef7dbf 2735 if (dspload_is_loaded(codec)) {
d9684bb5 2736 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 2737 return true;
2738 }
6d67530e
IM		 2739 msleep(20);
2740 } while (time_before(jiffies, timeout));
01ef7dbf 2741
d9684bb5 2742 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 2743 return false;
95c6e9cb
IM		 2744}
2745
825315bc
IM		 2746/*
2747 * PCM callbacks
2748 */
95c6e9cb
IM		 2749static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2750 struct hda_codec *codec,
2751 unsigned int stream_tag,
2752 unsigned int format,
2753 struct snd_pcm_substream *substream)
2754{
2755 struct ca0132_spec *spec = codec->spec;
825315bc 2756
28fba950 2757 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 2758
2759 return 0;
95c6e9cb
IM		 2760}
2761
2762static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2763 struct hda_codec *codec,
2764 struct snd_pcm_substream *substream)
2765{
2766 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2767
2768 if (spec->dsp_state == DSP_DOWNLOADING)
2769 return 0;
2770
2771 /*If Playback effects are on, allow stream some time to flush
2772 *effects tail*/
2773 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2774 msleep(50);
2775
28fba950 2776 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 2777
2778 return 0;
95c6e9cb
IM		 2779}
2780
e8412ca4
DR		 2781static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2782 struct hda_codec *codec,
2783 struct snd_pcm_substream *substream)
2784{
2785 struct ca0132_spec *spec = codec->spec;
2786 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2787 struct snd_pcm_runtime *runtime = substream->runtime;
2788
2789 if (spec->dsp_state != DSP_DOWNLOADED)
2790 return 0;
2791
2792 /* Add latency if playback enhancement and either effect is enabled. */
2793 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2794 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2795 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2796 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2797 }
2798
2799 /* Applying Speaker EQ adds latency as well. */
2800 if (spec->cur_out_type == SPEAKER_OUT)
2801 latency += DSP_SPEAKER_OUT_LATENCY;
2802
2803 return (latency * runtime->rate) / 1000;
2804}
2805
95c6e9cb
IM		 2806/*
2807 * Digital out
2808 */
27ebeb0b
TI		 2809static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2810 struct hda_codec *codec,
2811 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2812{
2813 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2814 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2815}
2816
27ebeb0b 2817static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2818 struct hda_codec *codec,
2819 unsigned int stream_tag,
2820 unsigned int format,
2821 struct snd_pcm_substream *substream)
2822{
2823 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2824 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2825 stream_tag, format, substream);
95c6e9cb
IM		 2826}
2827
27ebeb0b 2828static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2829 struct hda_codec *codec,
95c6e9cb
IM		 2830 struct snd_pcm_substream *substream)
2831{
2832 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2833 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2834}
2835
27ebeb0b
TI		 2836static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2837 struct hda_codec *codec,
2838 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2839{
2840 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2841 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2842}
2843
825315bc
IM		 2844/*
2845 * Analog capture
2846 */
2847static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2848 struct hda_codec *codec,
2849 unsigned int stream_tag,
2850 unsigned int format,
2851 struct snd_pcm_substream *substream)
2852{
13c12dbe 2853 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 2854 stream_tag, 0, format);
825315bc
IM		 2855
2856 return 0;
2857}
2858
2859static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2860 struct hda_codec *codec,
2861 struct snd_pcm_substream *substream)
2862{
2863 struct ca0132_spec *spec = codec->spec;
2864
2865 if (spec->dsp_state == DSP_DOWNLOADING)
2866 return 0;
2867
28fba950 2868 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 2869 return 0;
2870}
2871
e8412ca4
DR		 2872static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2873 struct hda_codec *codec,
2874 struct snd_pcm_substream *substream)
2875{
2876 struct ca0132_spec *spec = codec->spec;
2877 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2878 struct snd_pcm_runtime *runtime = substream->runtime;
2879
2880 if (spec->dsp_state != DSP_DOWNLOADED)
2881 return 0;
2882
2883 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2884 latency += DSP_CRYSTAL_VOICE_LATENCY;
2885
2886 return (latency * runtime->rate) / 1000;
2887}
2888
e90f29e4
IM		 2889/*
2890 * Controls stuffs.
2891 */
2892
2893/*
2894 * Mixer controls helpers.
2895 */
2896#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2897 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2898 .name = xname, \
2899 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2900 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2901 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2902 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2903 .info = ca0132_volume_info, \
2904 .get = ca0132_volume_get, \
2905 .put = ca0132_volume_put, \
2906 .tlv = { .c = ca0132_volume_tlv }, \
2907 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2908
2909#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2910 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2911 .name = xname, \
2912 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2913 .info = snd_hda_mixer_amp_switch_info, \
2914 .get = ca0132_switch_get, \
2915 .put = ca0132_switch_put, \
2916 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2917
2918/* stereo */
2919#define CA0132_CODEC_VOL(xname, nid, dir) \
2920 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2921#define CA0132_CODEC_MUTE(xname, nid, dir) \
2922 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2923
4091fb95 2924/* The following are for tuning of products */
44f0c978
IM		 2925#ifdef ENABLE_TUNING_CONTROLS
2926
2927static unsigned int voice_focus_vals_lookup[] = {
29280x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
29290x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
29300x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
29310x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
29320x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
29330x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
29340x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
29350x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
29360x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
29370x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
29380x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
29390x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
29400x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
29410x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
29420x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
29430x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
29440x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
29450x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
29460x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
29470x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
29480x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
29490x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
29500x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
29510x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
29520x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
29530x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
29540x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2955};
2956
2957static unsigned int mic_svm_vals_lookup[] = {
29580x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
29590x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
29600x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
29610x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
29620x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
29630x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
29640x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
29650x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
29660x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
29670x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
29680x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
29690x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
29700x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
29710x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
29720x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
29730x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
29740x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2975};
2976
2977static unsigned int equalizer_vals_lookup[] = {
29780xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
29790xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
29800xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
29810xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
29820x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
29830x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
29840x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
29850x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
29860x41C00000
2987};
2988
2989static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2990 unsigned int *lookup, int idx)
2991{
2992 int i = 0;
2993
2994 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2995 if (nid == ca0132_tuning_ctls[i].nid)
2996 break;
2997
2998 snd_hda_power_up(codec);
2999 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
3000 ca0132_tuning_ctls[i].req,
3001 &(lookup[idx]), sizeof(unsigned int));
3002 snd_hda_power_down(codec);
3003
3004 return 1;
3005}
3006
3007static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3008 struct snd_ctl_elem_value *ucontrol)
3009{
3010 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3011 struct ca0132_spec *spec = codec->spec;
3012 hda_nid_t nid = get_amp_nid(kcontrol);
3013 long *valp = ucontrol->value.integer.value;
3014 int idx = nid - TUNING_CTL_START_NID;
3015
3016 *valp = spec->cur_ctl_vals[idx];
3017 return 0;
3018}
3019
3020static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3021 struct snd_ctl_elem_info *uinfo)
3022{
3023 int chs = get_amp_channels(kcontrol);
3024 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3025 uinfo->count = chs == 3 ? 2 : 1;
3026 uinfo->value.integer.min = 20;
3027 uinfo->value.integer.max = 180;
3028 uinfo->value.integer.step = 1;
3029
3030 return 0;
3031}
3032
3033static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3034 struct snd_ctl_elem_value *ucontrol)
3035{
3036 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3037 struct ca0132_spec *spec = codec->spec;
3038 hda_nid_t nid = get_amp_nid(kcontrol);
3039 long *valp = ucontrol->value.integer.value;
3040 int idx;
3041
3042 idx = nid - TUNING_CTL_START_NID;
3043 /* any change? */
3044 if (spec->cur_ctl_vals[idx] == *valp)
3045 return 0;
3046
3047 spec->cur_ctl_vals[idx] = *valp;
3048
3049 idx = *valp - 20;
3050 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3051
3052 return 1;
3053}
3054
3055static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3056 struct snd_ctl_elem_info *uinfo)
3057{
3058 int chs = get_amp_channels(kcontrol);
3059 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3060 uinfo->count = chs == 3 ? 2 : 1;
3061 uinfo->value.integer.min = 0;
3062 uinfo->value.integer.max = 100;
3063 uinfo->value.integer.step = 1;
3064
3065 return 0;
3066}
3067
3068static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3069 struct snd_ctl_elem_value *ucontrol)
3070{
3071 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3072 struct ca0132_spec *spec = codec->spec;
3073 hda_nid_t nid = get_amp_nid(kcontrol);
3074 long *valp = ucontrol->value.integer.value;
3075 int idx;
3076
3077 idx = nid - TUNING_CTL_START_NID;
3078 /* any change? */
3079 if (spec->cur_ctl_vals[idx] == *valp)
3080 return 0;
3081
3082 spec->cur_ctl_vals[idx] = *valp;
3083
3084 idx = *valp;
3085 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3086
3087 return 0;
3088}
3089
3090static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3091 struct snd_ctl_elem_info *uinfo)
3092{
3093 int chs = get_amp_channels(kcontrol);
3094 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3095 uinfo->count = chs == 3 ? 2 : 1;
3096 uinfo->value.integer.min = 0;
3097 uinfo->value.integer.max = 48;
3098 uinfo->value.integer.step = 1;
3099
3100 return 0;
3101}
3102
3103static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3104 struct snd_ctl_elem_value *ucontrol)
3105{
3106 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3107 struct ca0132_spec *spec = codec->spec;
3108 hda_nid_t nid = get_amp_nid(kcontrol);
3109 long *valp = ucontrol->value.integer.value;
3110 int idx;
3111
3112 idx = nid - TUNING_CTL_START_NID;
3113 /* any change? */
3114 if (spec->cur_ctl_vals[idx] == *valp)
3115 return 0;
3116
3117 spec->cur_ctl_vals[idx] = *valp;
3118
3119 idx = *valp;
3120 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3121
3122 return 1;
3123}
3124
8e142e9e
TS		 3125static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3126static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3127
3128static int add_tuning_control(struct hda_codec *codec,
3129 hda_nid_t pnid, hda_nid_t nid,
3130 const char *name, int dir)
3131{
975cc02a 3132 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3133 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3134 struct snd_kcontrol_new knew =
3135 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3136
3137 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3138 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3139 knew.tlv.c = 0;
3140 knew.tlv.p = 0;
3141 switch (pnid) {
3142 case VOICE_FOCUS:
3143 knew.info = voice_focus_ctl_info;
3144 knew.get = tuning_ctl_get;
3145 knew.put = voice_focus_ctl_put;
3146 knew.tlv.p = voice_focus_db_scale;
3147 break;
3148 case MIC_SVM:
3149 knew.info = mic_svm_ctl_info;
3150 knew.get = tuning_ctl_get;
3151 knew.put = mic_svm_ctl_put;
3152 break;
3153 case EQUALIZER:
3154 knew.info = equalizer_ctl_info;
3155 knew.get = tuning_ctl_get;
3156 knew.put = equalizer_ctl_put;
3157 knew.tlv.p = eq_db_scale;
3158 break;
3159 default:
3160 return 0;
3161 }
3162 knew.private_value =
3163 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3164 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3165 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3166}
3167
3168static int add_tuning_ctls(struct hda_codec *codec)
3169{
3170 int i;
3171 int err;
3172
3173 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3174 err = add_tuning_control(codec,
3175 ca0132_tuning_ctls[i].parent_nid,
3176 ca0132_tuning_ctls[i].nid,
3177 ca0132_tuning_ctls[i].name,
3178 ca0132_tuning_ctls[i].direct);
3179 if (err < 0)
3180 return err;
3181 }
3182
3183 return 0;
3184}
3185
3186static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3187{
3188 struct ca0132_spec *spec = codec->spec;
3189 int i;
3190
3191 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3192 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3193 /* SVM level defaults to 0.74. */
3194 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3195
3196 /* EQ defaults to 0dB. */
3197 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3198 spec->cur_ctl_vals[i] = 24;
3199}
3200#endif /*ENABLE_TUNING_CONTROLS*/
3201
5aaca44d
IM		 3202/*
3203 * Select the active output.
3204 * If autodetect is enabled, output will be selected based on jack detection.
3205 * If jack inserted, headphone will be selected, else built-in speakers
3206 * If autodetect is disabled, output will be selected based on selection.
3207 */
3208static int ca0132_select_out(struct hda_codec *codec)
3209{
3210 struct ca0132_spec *spec = codec->spec;
3211 unsigned int pin_ctl;
3212 int jack_present;
3213 int auto_jack;
3214 unsigned int tmp;
3215 int err;
3216
4e76a883 3217 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3218
664c7155 3219 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3220
3221 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3222
3223 if (auto_jack)
fe14f39e 3224 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3225 else
3226 jack_present =
3227 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3228
3229 if (jack_present)
3230 spec->cur_out_type = HEADPHONE_OUT;
3231 else
3232 spec->cur_out_type = SPEAKER_OUT;
3233
3234 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3235 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3236 /*speaker out config*/
3237 tmp = FLOAT_ONE;
3238 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3239 if (err < 0)
3240 goto exit;
3241 /*enable speaker EQ*/
3242 tmp = FLOAT_ONE;
3243 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3244 if (err < 0)
3245 goto exit;
3246
3247 /* Setup EAPD */
3248 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3249 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3250 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3251 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3252 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3253 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3254 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3255 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3256
3257 /* disable headphone node */
3258 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3259 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3260 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3261 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3262 /* enable speaker node */
3263 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 3264 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3265 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3266 pin_ctl | PIN_OUT);
5aaca44d 3267 } else {
4e76a883 3268 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3269 /*headphone out config*/
3270 tmp = FLOAT_ZERO;
3271 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3272 if (err < 0)
3273 goto exit;
3274 /*disable speaker EQ*/
3275 tmp = FLOAT_ZERO;
3276 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3277 if (err < 0)
3278 goto exit;
3279
3280 /* Setup EAPD */
3281 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3282 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3283 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3284 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3285 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3286 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3287 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3288 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3289
3290 /* disable speaker*/
3291 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3292 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3293 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3294 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3295 /* enable headphone*/
3296 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3297 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3298 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3299 pin_ctl | PIN_HP);
5aaca44d
IM		 3300 }
3301
3302exit:
664c7155 3303 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3304
3305 return err < 0 ? err : 0;
3306}
3307
993884f6
CCC		 3308static void ca0132_unsol_hp_delayed(struct work_struct *work)
3309{
3310 struct ca0132_spec *spec = container_of(
3311 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 3312 struct hda_jack_tbl *jack;
3313
993884f6 3314 ca0132_select_out(spec->codec);
d5c016b5 3315 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 3316 if (jack) {
3317 jack->block_report = 0;
3318 snd_hda_jack_report_sync(spec->codec);
3319 }
993884f6
CCC		 3320}
3321
5aaca44d
IM		 3322static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3323static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3324static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3325
3326/*
3327 * Select the active VIP source
3328 */
3329static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3330{
3331 struct ca0132_spec *spec = codec->spec;
3332 unsigned int tmp;
3333
e8f1bd5d 3334 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 3335 return 0;
3336
3337 /* if CrystalVoice if off, vipsource should be 0 */
3338 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3339 (val == 0)) {
3340 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3341 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3342 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3343 if (spec->cur_mic_type == DIGITAL_MIC)
3344 tmp = FLOAT_TWO;
3345 else
3346 tmp = FLOAT_ONE;
3347 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3348 tmp = FLOAT_ZERO;
3349 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3350 } else {
3351 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3352 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3353 if (spec->cur_mic_type == DIGITAL_MIC)
3354 tmp = FLOAT_TWO;
3355 else
3356 tmp = FLOAT_ONE;
3357 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3358 tmp = FLOAT_ONE;
3359 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3360 msleep(20);
3361 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3362 }
3363
3364 return 1;
3365}
3366
3367/*
3368 * Select the active microphone.
3369 * If autodetect is enabled, mic will be selected based on jack detection.
3370 * If jack inserted, ext.mic will be selected, else built-in mic
3371 * If autodetect is disabled, mic will be selected based on selection.
3372 */
3373static int ca0132_select_mic(struct hda_codec *codec)
3374{
3375 struct ca0132_spec *spec = codec->spec;
3376 int jack_present;
3377 int auto_jack;
3378
4e76a883 3379 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 3380
664c7155 3381 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3382
3383 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3384
3385 if (auto_jack)
fe14f39e 3386 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 3387 else
3388 jack_present =
3389 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3390
3391 if (jack_present)
3392 spec->cur_mic_type = LINE_MIC_IN;
3393 else
3394 spec->cur_mic_type = DIGITAL_MIC;
3395
3396 if (spec->cur_mic_type == DIGITAL_MIC) {
3397 /* enable digital Mic */
3398 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3399 ca0132_set_dmic(codec, 1);
3400 ca0132_mic_boost_set(codec, 0);
3401 /* set voice focus */
3402 ca0132_effects_set(codec, VOICE_FOCUS,
3403 spec->effects_switch
3404 [VOICE_FOCUS - EFFECT_START_NID]);
3405 } else {
3406 /* disable digital Mic */
3407 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3408 ca0132_set_dmic(codec, 0);
3409 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3410 /* disable voice focus */
3411 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3412 }
3413
664c7155 3414 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3415
3416 return 0;
3417}
3418
a7e76271
IM		 3419/*
3420 * Check if VNODE settings take effect immediately.
3421 */
3422static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3423 hda_nid_t vnid,
3424 hda_nid_t *shared_nid)
3425{
3426 struct ca0132_spec *spec = codec->spec;
3427 hda_nid_t nid;
a7e76271
IM		 3428
3429 switch (vnid) {
3430 case VNID_SPK:
3431 nid = spec->shared_out_nid;
a7e76271
IM		 3432 break;
3433 case VNID_MIC:
3434 nid = spec->shared_mic_nid;
a7e76271
IM		 3435 break;
3436 default:
9a0869f4 3437 return false;
a7e76271
IM		 3438 }
3439
9a0869f4 3440 if (shared_nid)
a7e76271
IM		 3441 *shared_nid = nid;
3442
9a0869f4 3443 return true;
a7e76271
IM		 3444}
3445
3446/*
3447* The following functions are control change helpers.
3448* They return 0 if no changed. Return 1 if changed.
3449*/
3450static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3451{
3452 struct ca0132_spec *spec = codec->spec;
3453 unsigned int tmp;
3454
3455 /* based on CrystalVoice state to enable VoiceFX. */
3456 if (enable) {
3457 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3458 FLOAT_ONE : FLOAT_ZERO;
3459 } else {
3460 tmp = FLOAT_ZERO;
3461 }
3462
3463 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3464 ca0132_voicefx.reqs[0], tmp);
3465
3466 return 1;
3467}
3468
5aaca44d
IM		 3469/*
3470 * Set the effects parameters
3471 */
3472static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3473{
3474 struct ca0132_spec *spec = codec->spec;
3475 unsigned int on;
3476 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3477 int err = 0;
3478 int idx = nid - EFFECT_START_NID;
3479
3480 if ((idx < 0) || (idx >= num_fx))
3481 return 0; /* no changed */
3482
3483 /* for out effect, qualify with PE */
3484 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3485 /* if PE if off, turn off out effects. */
3486 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3487 val = 0;
3488 }
3489
3490 /* for in effect, qualify with CrystalVoice */
3491 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3492 /* if CrystalVoice if off, turn off in effects. */
3493 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3494 val = 0;
3495
3496 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3497 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3498 val = 0;
3499 }
3500
4e76a883 3501 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 3502 nid, val);
3503
3504 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3505 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3506 ca0132_effects[idx].reqs[0], on);
3507
3508 if (err < 0)
3509 return 0; /* no changed */
3510
3511 return 1;
3512}
3513
a7e76271
IM		 3514/*
3515 * Turn on/off Playback Enhancements
3516 */
3517static int ca0132_pe_switch_set(struct hda_codec *codec)
3518{
3519 struct ca0132_spec *spec = codec->spec;
3520 hda_nid_t nid;
3521 int i, ret = 0;
3522
4e76a883 3523 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 3524 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3525
3526 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3527 nid = OUT_EFFECT_START_NID;
3528 /* PE affects all out effects */
3529 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3530 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3531
3532 return ret;
3533}
3534
5aaca44d
IM		 3535/* Check if Mic1 is streaming, if so, stop streaming */
3536static int stop_mic1(struct hda_codec *codec)
3537{
3538 struct ca0132_spec *spec = codec->spec;
3539 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3540 AC_VERB_GET_CONV, 0);
3541 if (oldval != 0)
3542 snd_hda_codec_write(codec, spec->adcs[0], 0,
3543 AC_VERB_SET_CHANNEL_STREAMID,
3544 0);
3545 return oldval;
3546}
3547
3548/* Resume Mic1 streaming if it was stopped. */
3549static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3550{
3551 struct ca0132_spec *spec = codec->spec;
3552 /* Restore the previous stream and channel */
3553 if (oldval != 0)
3554 snd_hda_codec_write(codec, spec->adcs[0], 0,
3555 AC_VERB_SET_CHANNEL_STREAMID,
3556 oldval);
3557}
3558
3559/*
a7e76271 3560 * Turn on/off CrystalVoice
5aaca44d 3561 */
a7e76271
IM		 3562static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3563{
3564 struct ca0132_spec *spec = codec->spec;
3565 hda_nid_t nid;
3566 int i, ret = 0;
3567 unsigned int oldval;
3568
4e76a883 3569 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 3570 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3571
3572 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3573 nid = IN_EFFECT_START_NID;
3574 /* CrystalVoice affects all in effects */
3575 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3576 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3577
3578 /* including VoiceFX */
3579 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3580
3581 /* set correct vipsource */
3582 oldval = stop_mic1(codec);
3583 ret |= ca0132_set_vipsource(codec, 1);
3584 resume_mic1(codec, oldval);
3585 return ret;
3586}
3587
5aaca44d
IM		 3588static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3589{
3590 struct ca0132_spec *spec = codec->spec;
3591 int ret = 0;
3592
3593 if (val) /* on */
3594 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3595 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3596 else /* off */
3597 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3598 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3599
3600 return ret;
3601}
3602
a7e76271
IM		 3603static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3604 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3605{
a7e76271
IM		 3606 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3607 hda_nid_t nid = get_amp_nid(kcontrol);
3608 hda_nid_t shared_nid = 0;
3609 bool effective;
3610 int ret = 0;
95c6e9cb 3611 struct ca0132_spec *spec = codec->spec;
a7e76271 3612 int auto_jack;
95c6e9cb 3613
a7e76271
IM		 3614 if (nid == VNID_HP_SEL) {
3615 auto_jack =
3616 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3617 if (!auto_jack)
3618 ca0132_select_out(codec);
3619 return 1;
3620 }
95c6e9cb 3621
a7e76271
IM		 3622 if (nid == VNID_AMIC1_SEL) {
3623 auto_jack =
3624 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3625 if (!auto_jack)
3626 ca0132_select_mic(codec);
3627 return 1;
3628 }
95c6e9cb 3629
a7e76271
IM		 3630 if (nid == VNID_HP_ASEL) {
3631 ca0132_select_out(codec);
3632 return 1;
3633 }
95c6e9cb 3634
a7e76271
IM		 3635 if (nid == VNID_AMIC1_ASEL) {
3636 ca0132_select_mic(codec);
3637 return 1;
95c6e9cb 3638 }
a7e76271
IM		 3639
3640 /* if effective conditions, then update hw immediately. */
3641 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3642 if (effective) {
3643 int dir = get_amp_direction(kcontrol);
3644 int ch = get_amp_channels(kcontrol);
3645 unsigned long pval;
3646
3647 mutex_lock(&codec->control_mutex);
3648 pval = kcontrol->private_value;
3649 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3650 0, dir);
3651 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3652 kcontrol->private_value = pval;
3653 mutex_unlock(&codec->control_mutex);
95c6e9cb 3654 }
95c6e9cb 3655
a7e76271 3656 return ret;
95c6e9cb 3657}
a7e76271 3658/* End of control change helpers. */
95c6e9cb 3659
a7e76271
IM		 3660static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3661 struct snd_ctl_elem_info *uinfo)
3662{
a9291f46 3663 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 3664
3665 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3666 uinfo->count = 1;
3667 uinfo->value.enumerated.items = items;
3668 if (uinfo->value.enumerated.item >= items)
3669 uinfo->value.enumerated.item = items - 1;
3670 strcpy(uinfo->value.enumerated.name,
3671 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3672 return 0;
3673}
95c6e9cb 3674
a7e76271 3675static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3676 struct snd_ctl_elem_value *ucontrol)
3677{
3678 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3679 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3680
a7e76271 3681 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3682 return 0;
3683}
3684
a7e76271 3685static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3686 struct snd_ctl_elem_value *ucontrol)
3687{
3688 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3689 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3690 int i, err = 0;
3691 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 3692
a9291f46 3693 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 3694 return 0;
3695
4e76a883 3696 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 3697 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3698
a7e76271
IM		 3699 /*
3700 * Idx 0 is default.
3701 * Default needs to qualify with CrystalVoice state.
3702 */
3703 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3704 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3705 ca0132_voicefx.reqs[i],
3706 ca0132_voicefx_presets[sel].vals[i]);
3707 if (err < 0)
3708 break;
3709 }
95c6e9cb 3710
a7e76271
IM		 3711 if (err >= 0) {
3712 spec->voicefx_val = sel;
3713 /* enable voice fx */
3714 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3715 }
95c6e9cb 3716
a7e76271 3717 return 1;
95c6e9cb
IM		 3718}
3719
a7e76271
IM		 3720static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3721 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3722{
3723 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3724 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3725 hda_nid_t nid = get_amp_nid(kcontrol);
3726 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3727 long *valp = ucontrol->value.integer.value;
3728
a7e76271
IM		 3729 /* vnode */
3730 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3731 if (ch & 1) {
3732 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3733 valp++;
3734 }
3735 if (ch & 2) {
3736 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3737 valp++;
3738 }
3739 return 0;
3740 }
3741
3742 /* effects, include PE and CrystalVoice */
3743 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3744 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3745 return 0;
3746 }
3747
3748 /* mic boost */
3749 if (nid == spec->input_pins[0]) {
3750 *valp = spec->cur_mic_boost;
3751 return 0;
3752 }
3753
95c6e9cb
IM		 3754 return 0;
3755}
3756
a7e76271
IM		 3757static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3758 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3759{
3760 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3761 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3762 hda_nid_t nid = get_amp_nid(kcontrol);
3763 int ch = get_amp_channels(kcontrol);
95c6e9cb 3764 long *valp = ucontrol->value.integer.value;
a7e76271 3765 int changed = 1;
95c6e9cb 3766
4e76a883 3767 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 3768 nid, *valp);
95c6e9cb
IM		 3769
3770 snd_hda_power_up(codec);
a7e76271
IM		 3771 /* vnode */
3772 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3773 if (ch & 1) {
3774 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3775 valp++;
3776 }
3777 if (ch & 2) {
3778 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3779 valp++;
3780 }
3781 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3782 goto exit;
3783 }
95c6e9cb 3784
a7e76271
IM		 3785 /* PE */
3786 if (nid == PLAY_ENHANCEMENT) {
3787 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3788 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3789 goto exit;
a7e76271 3790 }
95c6e9cb 3791
a7e76271
IM		 3792 /* CrystalVoice */
3793 if (nid == CRYSTAL_VOICE) {
3794 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3795 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3796 goto exit;
a7e76271 3797 }
95c6e9cb 3798
a7e76271
IM		 3799 /* out and in effects */
3800 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3801 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3802 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3803 changed = ca0132_effects_set(codec, nid, *valp);
3804 goto exit;
3805 }
3806
3807 /* mic boost */
3808 if (nid == spec->input_pins[0]) {
3809 spec->cur_mic_boost = *valp;
3810
3811 /* Mic boost does not apply to Digital Mic */
3812 if (spec->cur_mic_type != DIGITAL_MIC)
3813 changed = ca0132_mic_boost_set(codec, *valp);
3814 goto exit;
3815 }
95c6e9cb 3816
a7e76271 3817exit:
95c6e9cb 3818 snd_hda_power_down(codec);
a7e76271 3819 return changed;
95c6e9cb
IM		 3820}
3821
a7e76271
IM		 3822/*
3823 * Volume related
3824 */
3825static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3826 struct snd_ctl_elem_info *uinfo)
3827{
3828 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3829 struct ca0132_spec *spec = codec->spec;
3830 hda_nid_t nid = get_amp_nid(kcontrol);
3831 int ch = get_amp_channels(kcontrol);
3832 int dir = get_amp_direction(kcontrol);
3833 unsigned long pval;
3834 int err;
3835
3836 switch (nid) {
3837 case VNID_SPK:
3838 /* follow shared_out info */
3839 nid = spec->shared_out_nid;
3840 mutex_lock(&codec->control_mutex);
3841 pval = kcontrol->private_value;
3842 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3843 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3844 kcontrol->private_value = pval;
3845 mutex_unlock(&codec->control_mutex);
3846 break;
3847 case VNID_MIC:
3848 /* follow shared_mic info */
3849 nid = spec->shared_mic_nid;
3850 mutex_lock(&codec->control_mutex);
3851 pval = kcontrol->private_value;
3852 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3853 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3854 kcontrol->private_value = pval;
3855 mutex_unlock(&codec->control_mutex);
3856 break;
3857 default:
3858 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3859 }
3860 return err;
3861}
3862
3863static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3864 struct snd_ctl_elem_value *ucontrol)
3865{
3866 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3867 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3868 hda_nid_t nid = get_amp_nid(kcontrol);
3869 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3870 long *valp = ucontrol->value.integer.value;
3871
a7e76271
IM		 3872 /* store the left and right volume */
3873 if (ch & 1) {
3874 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3875 valp++;
3876 }
3877 if (ch & 2) {
3878 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3879 valp++;
3880 }
95c6e9cb
IM		 3881 return 0;
3882}
3883
a7e76271 3884static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3885 struct snd_ctl_elem_value *ucontrol)
3886{
3887 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3888 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3889 hda_nid_t nid = get_amp_nid(kcontrol);
3890 int ch = get_amp_channels(kcontrol);
95c6e9cb 3891 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3892 hda_nid_t shared_nid = 0;
3893 bool effective;
3894 int changed = 1;
3895
3896 /* store the left and right volume */
3897 if (ch & 1) {
3898 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3899 valp++;
3900 }
3901 if (ch & 2) {
3902 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3903 valp++;
3904 }
95c6e9cb 3905
a7e76271
IM		 3906 /* if effective conditions, then update hw immediately. */
3907 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3908 if (effective) {
3909 int dir = get_amp_direction(kcontrol);
3910 unsigned long pval;
3911
3912 snd_hda_power_up(codec);
3913 mutex_lock(&codec->control_mutex);
3914 pval = kcontrol->private_value;
3915 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3916 0, dir);
3917 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3918 kcontrol->private_value = pval;
3919 mutex_unlock(&codec->control_mutex);
3920 snd_hda_power_down(codec);
3921 }
95c6e9cb 3922
a7e76271 3923 return changed;
95c6e9cb
IM		 3924}
3925
a7e76271
IM		 3926static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3927 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3928{
a7e76271
IM		 3929 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3930 struct ca0132_spec *spec = codec->spec;
3931 hda_nid_t nid = get_amp_nid(kcontrol);
3932 int ch = get_amp_channels(kcontrol);
3933 int dir = get_amp_direction(kcontrol);
3934 unsigned long pval;
3935 int err;
3936
3937 switch (nid) {
3938 case VNID_SPK:
3939 /* follow shared_out tlv */
3940 nid = spec->shared_out_nid;
3941 mutex_lock(&codec->control_mutex);
3942 pval = kcontrol->private_value;
3943 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3944 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3945 kcontrol->private_value = pval;
3946 mutex_unlock(&codec->control_mutex);
3947 break;
3948 case VNID_MIC:
3949 /* follow shared_mic tlv */
3950 nid = spec->shared_mic_nid;
3951 mutex_lock(&codec->control_mutex);
3952 pval = kcontrol->private_value;
3953 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3954 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3955 kcontrol->private_value = pval;
3956 mutex_unlock(&codec->control_mutex);
3957 break;
3958 default:
3959 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3960 }
3961 return err;
95c6e9cb
IM		 3962}
3963
a7e76271
IM		 3964static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3965 const char *pfx, int dir)
95c6e9cb 3966{
975cc02a 3967 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 3968 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3969 struct snd_kcontrol_new knew =
a7e76271
IM		 3970 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3971 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3972 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3973}
3974
a7e76271 3975static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3976{
3977 struct snd_kcontrol_new knew =
a7e76271
IM		 3978 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3979 VOICEFX, 1, 0, HDA_INPUT);
3980 knew.info = ca0132_voicefx_info;
3981 knew.get = ca0132_voicefx_get;
3982 knew.put = ca0132_voicefx_put;
3983 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3984}
3985
a7e76271
IM		 3986/*
3987 * When changing Node IDs for Mixer Controls below, make sure to update
3988 * Node IDs in ca0132_config() as well.
3989 */
3990static struct snd_kcontrol_new ca0132_mixer[] = {
3991 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3992 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3993 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3994 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3995 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3996 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3997 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3998 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3999 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
4000 0x12, 1, HDA_INPUT),
4001 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
4002 VNID_HP_SEL, 1, HDA_OUTPUT),
4003 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
4004 VNID_AMIC1_SEL, 1, HDA_INPUT),
4005 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
4006 VNID_HP_ASEL, 1, HDA_OUTPUT),
4007 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
4008 VNID_AMIC1_ASEL, 1, HDA_INPUT),
4009 { } /* end */
4010};
4011
e90f29e4
IM		 4012static int ca0132_build_controls(struct hda_codec *codec)
4013{
4014 struct ca0132_spec *spec = codec->spec;
4015 int i, num_fx;
4016 int err = 0;
4017
4018 /* Add Mixer controls */
4019 for (i = 0; i < spec->num_mixers; i++) {
4020 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
4021 if (err < 0)
4022 return err;
4023 }
4024
4025 /* Add in and out effects controls.
4026 * VoiceFX, PE and CrystalVoice are added separately.
4027 */
4028 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4029 for (i = 0; i < num_fx; i++) {
4030 err = add_fx_switch(codec, ca0132_effects[i].nid,
4031 ca0132_effects[i].name,
4032 ca0132_effects[i].direct);
4033 if (err < 0)
4034 return err;
4035 }
4036
4037 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
4038 if (err < 0)
4039 return err;
4040
4041 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
4042 if (err < 0)
4043 return err;
4044
4045 add_voicefx(codec);
4046
4047#ifdef ENABLE_TUNING_CONTROLS
4048 add_tuning_ctls(codec);
4049#endif
4050
4051 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
4052 if (err < 0)
4053 return err;
4054
4055 if (spec->dig_out) {
4056 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4057 spec->dig_out);
4058 if (err < 0)
4059 return err;
4060 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4061 if (err < 0)
4062 return err;
4063 /* spec->multiout.share_spdif = 1; */
4064 }
4065
4066 if (spec->dig_in) {
4067 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4068 if (err < 0)
4069 return err;
4070 }
4071 return 0;
4072}
4073
a7e76271 4074/*
e90f29e4 4075 * PCM
a7e76271 4076 */
071f1344 4077static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 4078 .substreams = 1,
4079 .channels_min = 2,
825315bc 4080 .channels_max = 6,
a7e76271 4081 .ops = {
a7e76271 4082 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 4083 .cleanup = ca0132_playback_pcm_cleanup,
4084 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 4085 },
4086};
4087
071f1344 4088static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 4089 .substreams = 1,
4090 .channels_min = 2,
4091 .channels_max = 2,
825315bc
IM		 4092 .ops = {
4093 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 4094 .cleanup = ca0132_capture_pcm_cleanup,
4095 .get_delay = ca0132_capture_pcm_delay,
825315bc 4096 },
a7e76271
IM		 4097};
4098
071f1344 4099static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 4100 .substreams = 1,
4101 .channels_min = 2,
4102 .channels_max = 2,
4103 .ops = {
4104 .open = ca0132_dig_playback_pcm_open,
4105 .close = ca0132_dig_playback_pcm_close,
4106 .prepare = ca0132_dig_playback_pcm_prepare,
4107 .cleanup = ca0132_dig_playback_pcm_cleanup
4108 },
4109};
4110
071f1344 4111static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 4112 .substreams = 1,
4113 .channels_min = 2,
4114 .channels_max = 2,
4115};
4116
4117static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4118{
4119 struct ca0132_spec *spec = codec->spec;
bbbc7e85 4120 struct hda_pcm *info;
a7e76271 4121
bbbc7e85
TI		 4122 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4123 if (!info)
4124 return -ENOMEM;
a7e76271
IM		 4125 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4126 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4127 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4128 spec->multiout.max_channels;
4129 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4130 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 4131 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 4132
bbbc7e85
TI		 4133 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4134 if (!info)
4135 return -ENOMEM;
825315bc
IM		 4136 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4137 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4138 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
825315bc 4139
bbbc7e85
TI		 4140 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4141 if (!info)
4142 return -ENOMEM;
825315bc
IM		 4143 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4144 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4145 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 4146
a7e76271
IM		 4147 if (!spec->dig_out && !spec->dig_in)
4148 return 0;
4149
bbbc7e85
TI		 4150 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4151 if (!info)
4152 return -ENOMEM;
a7e76271
IM		 4153 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4154 if (spec->dig_out) {
4155 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4156 ca0132_pcm_digital_playback;
4157 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4158 }
4159 if (spec->dig_in) {
4160 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4161 ca0132_pcm_digital_capture;
4162 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4163 }
95c6e9cb 4164
a7e76271 4165 return 0;
95c6e9cb
IM		 4166}
4167
441aa6a0
IM		 4168static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4169{
4170 if (pin) {
a0c041cb 4171 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 4172 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4173 snd_hda_codec_write(codec, pin, 0,
4174 AC_VERB_SET_AMP_GAIN_MUTE,
4175 AMP_OUT_UNMUTE);
4176 }
4177 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4178 snd_hda_codec_write(codec, dac, 0,
4179 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4180}
4181
4182static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4183{
4184 if (pin) {
a0c041cb 4185 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 4186 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4187 snd_hda_codec_write(codec, pin, 0,
4188 AC_VERB_SET_AMP_GAIN_MUTE,
4189 AMP_IN_UNMUTE(0));
4190 }
4191 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4192 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4193 AMP_IN_UNMUTE(0));
4194
4195 /* init to 0 dB and unmute. */
4196 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4197 HDA_AMP_VOLMASK, 0x5a);
4198 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4199 HDA_AMP_MUTE, 0);
4200 }
4201}
4202
5aaca44d
IM		 4203static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4204{
4205 unsigned int caps;
4206
4207 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4208 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4209 snd_hda_override_amp_caps(codec, nid, dir, caps);
4210}
4211
4212/*
4213 * Switch between Digital built-in mic and analog mic.
4214 */
4215static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4216{
4217 struct ca0132_spec *spec = codec->spec;
4218 unsigned int tmp;
4219 u8 val;
4220 unsigned int oldval;
4221
4e76a883 4222 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 4223
4224 oldval = stop_mic1(codec);
4225 ca0132_set_vipsource(codec, 0);
4226 if (enable) {
4227 /* set DMic input as 2-ch */
4228 tmp = FLOAT_TWO;
4229 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4230
4231 val = spec->dmic_ctl;
4232 val |= 0x80;
4233 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4234 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4235
4236 if (!(spec->dmic_ctl & 0x20))
4237 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4238 } else {
4239 /* set AMic input as mono */
4240 tmp = FLOAT_ONE;
4241 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4242
4243 val = spec->dmic_ctl;
4244 /* clear bit7 and bit5 to disable dmic */
4245 val &= 0x5f;
4246 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4247 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4248
4249 if (!(spec->dmic_ctl & 0x20))
4250 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4251 }
4252 ca0132_set_vipsource(codec, 1);
4253 resume_mic1(codec, oldval);
4254}
4255
4256/*
4257 * Initialization for Digital Mic.
4258 */
4259static void ca0132_init_dmic(struct hda_codec *codec)
4260{
4261 struct ca0132_spec *spec = codec->spec;
4262 u8 val;
4263
4264 /* Setup Digital Mic here, but don't enable.
4265 * Enable based on jack detect.
4266 */
4267
4268 /* MCLK uses MPIO1, set to enable.
4269 * Bit 2-0: MPIO select
4270 * Bit 3: set to disable
4271 * Bit 7-4: reserved
4272 */
4273 val = 0x01;
4274 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4275 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4276
4277 /* Data1 uses MPIO3. Data2 not use
4278 * Bit 2-0: Data1 MPIO select
4279 * Bit 3: set disable Data1
4280 * Bit 6-4: Data2 MPIO select
4281 * Bit 7: set disable Data2
4282 */
4283 val = 0x83;
4284 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4285 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4286
4287 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4288 * Bit 3-0: Channel mask
4289 * Bit 4: set for 48KHz, clear for 32KHz
4290 * Bit 5: mode
4291 * Bit 6: set to select Data2, clear for Data1
4292 * Bit 7: set to enable DMic, clear for AMic
4293 */
4294 val = 0x23;
4295 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4296 spec->dmic_ctl = val;
4297 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4298 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4299}
4300
4301/*
4302 * Initialization for Analog Mic 2
4303 */
4304static void ca0132_init_analog_mic2(struct hda_codec *codec)
4305{
4306 struct ca0132_spec *spec = codec->spec;
4307
4308 mutex_lock(&spec->chipio_mutex);
4309 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4310 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4311 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4312 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4313 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4314 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4315 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4316 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4317 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4318 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4319 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4320 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4321 mutex_unlock(&spec->chipio_mutex);
4322}
4323
4324static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4325{
4326 struct ca0132_spec *spec = codec->spec;
4327 int i;
5aaca44d 4328
4e76a883 4329 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 4330 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 4331
4332 for (i = 0; i < spec->multiout.num_dacs; i++)
4333 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4334
4335 for (i = 0; i < spec->num_outputs; i++)
4336 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4337
4338 for (i = 0; i < spec->num_inputs; i++) {
4339 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4340 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4341 }
4342}
4343
4344/*
4345 * Setup default parameters for DSP
4346 */
4347static void ca0132_setup_defaults(struct hda_codec *codec)
4348{
e8f1bd5d 4349 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4350 unsigned int tmp;
4351 int num_fx;
4352 int idx, i;
4353
e8f1bd5d 4354 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4355 return;
4356
4357 /* out, in effects + voicefx */
4358 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4359 for (idx = 0; idx < num_fx; idx++) {
4360 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4361 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4362 ca0132_effects[idx].reqs[i],
4363 ca0132_effects[idx].def_vals[i]);
4364 }
4365 }
4366
4367 /*remove DSP headroom*/
4368 tmp = FLOAT_ZERO;
4369 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4370
4371 /*set speaker EQ bypass attenuation*/
4372 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4373
4374 /* set AMic1 and AMic2 as mono mic */
4375 tmp = FLOAT_ONE;
4376 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4377 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4378
4379 /* set AMic1 as CrystalVoice input */
4380 tmp = FLOAT_ONE;
4381 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4382
4383 /* set WUH source */
4384 tmp = FLOAT_TWO;
4385 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4386}
4387
4388/*
4389 * Initialization of flags in chip
4390 */
4391static void ca0132_init_flags(struct hda_codec *codec)
4392{
4393 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4394 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4395 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4396 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4397 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4398 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4399}
4400
4401/*
4402 * Initialization of parameters in chip
4403 */
4404static void ca0132_init_params(struct hda_codec *codec)
4405{
4406 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4407 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4408}
95c6e9cb 4409
e90f29e4
IM		 4410static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4411{
4412 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4413 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4414 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4415 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4416 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4417 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4418
406261ce
IM		 4419 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4420 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 4421 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4422}
4423
4424static bool ca0132_download_dsp_images(struct hda_codec *codec)
4425{
4426 bool dsp_loaded = false;
8a19bcee 4427 struct ca0132_spec *spec = codec->spec;
e90f29e4 4428 const struct dsp_image_seg *dsp_os_image;
15e4ba66 4429 const struct firmware *fw_entry;
8a19bcee
CM		 4430 /*
4431 * Alternate firmwares for different variants. The Recon3Di apparently
4432 * can use the default firmware, but I'll leave the option in case
4433 * it needs it again.
4434 */
4435 switch (spec->quirk) {
4436 case QUIRK_SBZ:
4437 if (request_firmware(&fw_entry, SBZ_EFX_FILE,
4438 codec->card->dev) != 0) {
4439 codec_dbg(codec, "SBZ alt firmware not detected. ");
4440 spec->alt_firmware_present = false;
4441 } else {
4442 codec_dbg(codec, "Sound Blaster Z firmware selected.");
4443 spec->alt_firmware_present = true;
4444 }
4445 break;
4446 case QUIRK_R3DI:
4447 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
4448 codec->card->dev) != 0) {
4449 codec_dbg(codec, "Recon3Di alt firmware not detected.");
4450 spec->alt_firmware_present = false;
4451 } else {
4452 codec_dbg(codec, "Recon3Di firmware selected.");
4453 spec->alt_firmware_present = true;
4454 }
4455 break;
4456 default:
4457 spec->alt_firmware_present = false;
4458 break;
4459 }
4460 /*
4461 * Use default ctefx.bin if no alt firmware is detected, or if none
4462 * exists for your particular codec.
4463 */
4464 if (!spec->alt_firmware_present) {
4465 codec_dbg(codec, "Default firmware selected.");
4466 if (request_firmware(&fw_entry, EFX_FILE,
4467 codec->card->dev) != 0)
4468 return false;
4469 }
e90f29e4 4470
15e4ba66 4471 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 4472 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 4473 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 4474 goto exit_download;
4475 }
4476
e90f29e4
IM		 4477 dsp_loaded = dspload_wait_loaded(codec);
4478
d1d28500 4479exit_download:
15e4ba66
TI		 4480 release_firmware(fw_entry);
4481
e90f29e4
IM		 4482 return dsp_loaded;
4483}
4484
4485static void ca0132_download_dsp(struct hda_codec *codec)
4486{
4487 struct ca0132_spec *spec = codec->spec;
4488
9a0869f4
TI		 4489#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4490 return; /* NOP */
4491#endif
e90f29e4 4492
e24aa0a4
TI		 4493 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4494 return; /* don't retry failures */
4495
b714a710
DR		 4496 chipio_enable_clocks(codec);
4497 spec->dsp_state = DSP_DOWNLOADING;
4498 if (!ca0132_download_dsp_images(codec))
4499 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4500 else
4501 spec->dsp_state = DSP_DOWNLOADED;
e90f29e4
IM		 4502
4503 if (spec->dsp_state == DSP_DOWNLOADED)
4504 ca0132_set_dsp_msr(codec, true);
4505}
4506
f8fb1170
TI		 4507static void ca0132_process_dsp_response(struct hda_codec *codec,
4508 struct hda_jack_callback *callback)
e90f29e4
IM		 4509{
4510 struct ca0132_spec *spec = codec->spec;
4511
4e76a883 4512 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 4513 if (spec->wait_scp) {
4514 if (dspio_get_response_data(codec) >= 0)
4515 spec->wait_scp = 0;
4516 }
4517
4518 dspio_clear_response_queue(codec);
4519}
4520
f8fb1170 4521static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 4522{
993884f6 4523 struct ca0132_spec *spec = codec->spec;
2ebab40e 4524 struct hda_jack_tbl *tbl;
e90f29e4 4525
f8fb1170
TI		 4526 /* Delay enabling the HP amp, to let the mic-detection
4527 * state machine run.
4528 */
4529 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 4530 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 4531 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4532 if (tbl)
4533 tbl->block_report = 1;
f8fb1170
TI		 4534}
4535
4536static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4537{
4538 ca0132_select_mic(codec);
4539}
4540
4541static void ca0132_init_unsol(struct hda_codec *codec)
4542{
d5c016b5
GM		 4543 struct ca0132_spec *spec = codec->spec;
4544 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4545 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 4546 amic_callback);
4547 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4548 ca0132_process_dsp_response);
63177afc
CM		 4549 /* Front headphone jack detection */
4550 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3DI)
4551 snd_hda_jack_detect_enable_callback(codec,
4552 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 4553}
4554
5aaca44d
IM		 4555/*
4556 * Verbs tables.
4557 */
4558
4559/* Sends before DSP download. */
4560static struct hda_verb ca0132_base_init_verbs[] = {
4561 /*enable ct extension*/
4562 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 4563 {}
4564};
4565
4566/* Send at exit. */
4567static struct hda_verb ca0132_base_exit_verbs[] = {
4568 /*set afg to D3*/
4569 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4570 /*disable ct extension*/
4571 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4572 {}
4573};
4574
8a19bcee 4575/* Other verbs tables. Sends after DSP download. */
5aaca44d
IM		 4576static struct hda_verb ca0132_init_verbs0[] = {
4577 /* chip init verbs */
4578 {0x15, 0x70D, 0xF0},
4579 {0x15, 0x70E, 0xFE},
4580 {0x15, 0x707, 0x75},
4581 {0x15, 0x707, 0xD3},
4582 {0x15, 0x707, 0x09},
4583 {0x15, 0x707, 0x53},
4584 {0x15, 0x707, 0xD4},
4585 {0x15, 0x707, 0xEF},
4586 {0x15, 0x707, 0x75},
4587 {0x15, 0x707, 0xD3},
4588 {0x15, 0x707, 0x09},
4589 {0x15, 0x707, 0x02},
4590 {0x15, 0x707, 0x37},
4591 {0x15, 0x707, 0x78},
4592 {0x15, 0x53C, 0xCE},
4593 {0x15, 0x575, 0xC9},
4594 {0x15, 0x53D, 0xCE},
4595 {0x15, 0x5B7, 0xC9},
4596 {0x15, 0x70D, 0xE8},
4597 {0x15, 0x70E, 0xFE},
4598 {0x15, 0x707, 0x02},
4599 {0x15, 0x707, 0x68},
4600 {0x15, 0x707, 0x62},
4601 {0x15, 0x53A, 0xCE},
4602 {0x15, 0x546, 0xC9},
4603 {0x15, 0x53B, 0xCE},
4604 {0x15, 0x5E8, 0xC9},
4605 {0x15, 0x717, 0x0D},
4606 {0x15, 0x718, 0x20},
4607 {}
4608};
4609
95c6e9cb
IM		 4610static void ca0132_init_chip(struct hda_codec *codec)
4611{
4612 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4613 int num_fx;
4614 int i;
4615 unsigned int on;
95c6e9cb
IM		 4616
4617 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 4618
4619 spec->cur_out_type = SPEAKER_OUT;
4620 spec->cur_mic_type = DIGITAL_MIC;
4621 spec->cur_mic_boost = 0;
4622
4623 for (i = 0; i < VNODES_COUNT; i++) {
4624 spec->vnode_lvol[i] = 0x5a;
4625 spec->vnode_rvol[i] = 0x5a;
4626 spec->vnode_lswitch[i] = 0;
4627 spec->vnode_rswitch[i] = 0;
4628 }
4629
4630 /*
4631 * Default states for effects are in ca0132_effects[].
4632 */
4633 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4634 for (i = 0; i < num_fx; i++) {
4635 on = (unsigned int)ca0132_effects[i].reqs[0];
4636 spec->effects_switch[i] = on ? 1 : 0;
4637 }
4638
4639 spec->voicefx_val = 0;
4640 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4641 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4642
44f0c978
IM		 4643#ifdef ENABLE_TUNING_CONTROLS
4644 ca0132_init_tuning_defaults(codec);
4645#endif
95c6e9cb
IM		 4646}
4647
4648static void ca0132_exit_chip(struct hda_codec *codec)
4649{
4650 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 4651
4652 if (dspload_is_loaded(codec))
4653 dsp_reset(codec);
95c6e9cb
IM		 4654}
4655
4656static int ca0132_init(struct hda_codec *codec)
4657{
4658 struct ca0132_spec *spec = codec->spec;
4659 struct auto_pin_cfg *cfg = &spec->autocfg;
4660 int i;
4661
e24aa0a4
TI		 4662 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4663 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 4664 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 4665
664c7155 4666 snd_hda_power_up_pm(codec);
5aaca44d 4667
f8fb1170
TI		 4668 ca0132_init_unsol(codec);
4669
5aaca44d
IM		 4670 ca0132_init_params(codec);
4671 ca0132_init_flags(codec);
4672 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf 4673 ca0132_download_dsp(codec);
5aaca44d
IM		 4674 ca0132_refresh_widget_caps(codec);
4675 ca0132_setup_defaults(codec);
4676 ca0132_init_analog_mic2(codec);
4677 ca0132_init_dmic(codec);
4678
4679 for (i = 0; i < spec->num_outputs; i++)
4680 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4681
95c6e9cb
IM		 4682 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4683
4684 for (i = 0; i < spec->num_inputs; i++)
4685 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4686
4687 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4688
d5c016b5
GM		 4689 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4690 snd_hda_sequence_write(codec, spec->spec_init_verbs);
5aaca44d
IM		 4691
4692 ca0132_select_out(codec);
4693 ca0132_select_mic(codec);
4694
a73d511c
IM		 4695 snd_hda_jack_report_sync(codec);
4696
664c7155 4697 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 4698
4699 return 0;
4700}
4701
95c6e9cb
IM		 4702static void ca0132_free(struct hda_codec *codec)
4703{
5aaca44d
IM		 4704 struct ca0132_spec *spec = codec->spec;
4705
993884f6 4706 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d
IM		 4707 snd_hda_power_up(codec);
4708 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4709 ca0132_exit_chip(codec);
5aaca44d 4710 snd_hda_power_down(codec);
aa31704f
CM		 4711 if (spec->mem_base)
4712 iounmap(spec->mem_base);
d5c016b5 4713 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 4714 kfree(codec->spec);
4715}
4716
071f1344 4717static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 4718 .build_controls = ca0132_build_controls,
4719 .build_pcms = ca0132_build_pcms,
4720 .init = ca0132_init,
4721 .free = ca0132_free,
f8fb1170 4722 .unsol_event = snd_hda_jack_unsol_event,
95c6e9cb
IM		 4723};
4724
441aa6a0
IM		 4725static void ca0132_config(struct hda_codec *codec)
4726{
4727 struct ca0132_spec *spec = codec->spec;
4728 struct auto_pin_cfg *cfg = &spec->autocfg;
4729
4730 spec->dacs[0] = 0x2;
4731 spec->dacs[1] = 0x3;
4732 spec->dacs[2] = 0x4;
4733
4734 spec->multiout.dac_nids = spec->dacs;
4735 spec->multiout.num_dacs = 3;
441aa6a0 4736
63177afc
CM		 4737 if (spec->quirk == QUIRK_NONE || spec->quirk == QUIRK_ALIENWARE)
4738 spec->multiout.max_channels = 2;
4739 else
4740 spec->multiout.max_channels = 6;
4741
4742 switch (spec->quirk) {
4743 case QUIRK_ALIENWARE:
d5c016b5 4744 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 4745 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4746
4747 spec->num_outputs = 2;
4748 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4749 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 4750 spec->shared_out_nid = 0x2;
4751 spec->unsol_tag_hp = 0x0f;
4752
4753 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4754 spec->adcs[1] = 0x8; /* analog mic2 */
4755 spec->adcs[2] = 0xa; /* what u hear */
4756
4757 spec->num_inputs = 3;
4758 spec->input_pins[0] = 0x12;
4759 spec->input_pins[1] = 0x11;
4760 spec->input_pins[2] = 0x13;
4761 spec->shared_mic_nid = 0x7;
4762 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 4763 break;
4764 case QUIRK_SBZ:
4765 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
4766 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
4767
4768 spec->num_outputs = 2;
4769 spec->out_pins[0] = 0x0B; /* Line out */
4770 spec->out_pins[1] = 0x0F; /* Rear headphone out */
4771 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
4772 spec->out_pins[3] = 0x11; /* Rear surround */
4773 spec->shared_out_nid = 0x2;
4774 spec->unsol_tag_hp = spec->out_pins[1];
4775 spec->unsol_tag_front_hp = spec->out_pins[2];
4776
4777 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
4778 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
4779 spec->adcs[2] = 0xa; /* what u hear */
4780
4781 spec->num_inputs = 2;
4782 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
4783 spec->input_pins[1] = 0x13; /* What U Hear */
4784 spec->shared_mic_nid = 0x7;
4785 spec->unsol_tag_amic1 = spec->input_pins[0];
4786
4787 /* SPDIF I/O */
4788 spec->dig_out = 0x05;
4789 spec->multiout.dig_out_nid = spec->dig_out;
4790 cfg->dig_out_pins[0] = 0x0c;
4791 cfg->dig_outs = 1;
4792 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4793 spec->dig_in = 0x09;
4794 cfg->dig_in_pin = 0x0e;
4795 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4796 break;
4797 case QUIRK_R3DI:
4798 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
4799 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
4800
4801 spec->num_outputs = 2;
4802 spec->out_pins[0] = 0x0B; /* Line out */
4803 spec->out_pins[1] = 0x0F; /* Rear headphone out */
4804 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
4805 spec->out_pins[3] = 0x11; /* Rear surround */
4806 spec->shared_out_nid = 0x2;
4807 spec->unsol_tag_hp = spec->out_pins[1];
4808 spec->unsol_tag_front_hp = spec->out_pins[2];
4809
4810 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
4811 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
4812 spec->adcs[2] = 0x0a; /* what u hear */
4813
4814 spec->num_inputs = 2;
4815 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
4816 spec->input_pins[1] = 0x13; /* What U Hear */
4817 spec->shared_mic_nid = 0x7;
4818 spec->unsol_tag_amic1 = spec->input_pins[0];
4819
4820 /* SPDIF I/O */
4821 spec->dig_out = 0x05;
4822 spec->multiout.dig_out_nid = spec->dig_out;
4823 cfg->dig_out_pins[0] = 0x0c;
4824 cfg->dig_outs = 1;
4825 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4826 break;
4827 default:
fe14f39e
TI		 4828 spec->num_outputs = 2;
4829 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4830 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 4831 spec->shared_out_nid = 0x2;
4832 spec->unsol_tag_hp = spec->out_pins[1];
4833
4834 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4835 spec->adcs[1] = 0x8; /* analog mic2 */
4836 spec->adcs[2] = 0xa; /* what u hear */
4837
4838 spec->num_inputs = 3;
4839 spec->input_pins[0] = 0x12;
4840 spec->input_pins[1] = 0x11;
4841 spec->input_pins[2] = 0x13;
4842 spec->shared_mic_nid = 0x7;
4843 spec->unsol_tag_amic1 = spec->input_pins[0];
4844
4845 /* SPDIF I/O */
4846 spec->dig_out = 0x05;
4847 spec->multiout.dig_out_nid = spec->dig_out;
4848 cfg->dig_out_pins[0] = 0x0c;
4849 cfg->dig_outs = 1;
4850 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4851 spec->dig_in = 0x09;
4852 cfg->dig_in_pin = 0x0e;
4853 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
63177afc 4854 break;
d5c016b5 4855 }
441aa6a0
IM		 4856}
4857
d5c016b5
GM		 4858static int ca0132_prepare_verbs(struct hda_codec *codec)
4859{
4860/* Verbs + terminator (an empty element) */
4861#define NUM_SPEC_VERBS 4
4862 struct ca0132_spec *spec = codec->spec;
4863
4864 spec->chip_init_verbs = ca0132_init_verbs0;
4865 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4866 if (!spec->spec_init_verbs)
4867 return -ENOMEM;
4868
4869 /* HP jack autodetection */
4870 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4871 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4872 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4873
4874 /* MIC1 jack autodetection */
4875 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4876 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4877 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4878
4879 /* config EAPD */
4880 spec->spec_init_verbs[2].nid = 0x0b;
4881 spec->spec_init_verbs[2].param = 0x78D;
4882 spec->spec_init_verbs[2].verb = 0x00;
4883
4884 /* Previously commented configuration */
4885 /*
4886 spec->spec_init_verbs[3].nid = 0x0b;
4887 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4888 spec->spec_init_verbs[3].verb = 0x02;
4889
4890 spec->spec_init_verbs[4].nid = 0x10;
4891 spec->spec_init_verbs[4].param = 0x78D;
4892 spec->spec_init_verbs[4].verb = 0x02;
4893
4894 spec->spec_init_verbs[5].nid = 0x10;
4895 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4896 spec->spec_init_verbs[5].verb = 0x02;
4897 */
4898
4899 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4900 return 0;
4901}
4902
95c6e9cb
IM		 4903static int patch_ca0132(struct hda_codec *codec)
4904{
4905 struct ca0132_spec *spec;
a73d511c 4906 int err;
d5c016b5 4907 const struct snd_pci_quirk *quirk;
95c6e9cb 4908
4e76a883 4909 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 4910
4911 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4912 if (!spec)
4913 return -ENOMEM;
4914 codec->spec = spec;
993884f6 4915 spec->codec = codec;
95c6e9cb 4916
225068ab
TI		 4917 codec->patch_ops = ca0132_patch_ops;
4918 codec->pcm_format_first = 1;
4919 codec->no_sticky_stream = 1;
4920
d5c016b5
GM		 4921 /* Detect codec quirk */
4922 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4923 if (quirk)
4924 spec->quirk = quirk->value;
4925 else
4926 spec->quirk = QUIRK_NONE;
4927
aa31704f
CM		 4928 /* Setup BAR Region 2 for Sound Blaster Z */
4929 if (spec->quirk == QUIRK_SBZ) {
4930 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
4931 if (spec->mem_base == NULL) {
4932 codec_warn(codec, "pci_iomap failed!");
4933 codec_info(codec, "perhaps this is not an SBZ?");
4934 spec->quirk = QUIRK_NONE;
4935 }
4936 }
e24aa0a4 4937 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271
IM		 4938 spec->num_mixers = 1;
4939 spec->mixers[0] = ca0132_mixer;
4940
5aaca44d
IM		 4941 spec->base_init_verbs = ca0132_base_init_verbs;
4942 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 4943
993884f6
CCC		 4944 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4945
95c6e9cb
IM		 4946 ca0132_init_chip(codec);
4947
4948 ca0132_config(codec);
4949
d5c016b5
GM		 4950 err = ca0132_prepare_verbs(codec);
4951 if (err < 0)
cc91ceaf 4952 goto error;
d5c016b5 4953
a73d511c
IM		 4954 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4955 if (err < 0)
cc91ceaf 4956 goto error;
a73d511c 4957
95c6e9cb 4958 return 0;
cc91ceaf
TI		 4959
4960 error:
4961 ca0132_free(codec);
4962 return err;
95c6e9cb
IM		 4963}
4964
4965/*
4966 * patch entries
4967 */
b9a94a9c
TI		 4968static struct hda_device_id snd_hda_id_ca0132[] = {
4969 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 4970 {} /* terminator */
4971};
b9a94a9c 4972MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 4973
4974MODULE_LICENSE("GPL");
406261ce 4975MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 4976
d8a766a1 4977static struct hda_codec_driver ca0132_driver = {
b9a94a9c 4978 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 4979};
4980
d8a766a1 4981module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)