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ALSA: hda/ca0132: Add DSP mixer controls and helpers
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/pci.h>
28#include <linux/mutex.h>
da155d5b 29#include <linux/module.h>
4aa3bb0c 30#include <linux/firmware.h>
95c6e9cb
IM		 31#include <sound/core.h>
32#include "hda_codec.h"
33#include "hda_local.h"
128bc4ba 34#include "hda_auto_parser.h"
5aaca44d 35#include "hda_jack.h"
95c6e9cb 36
bcd109c0
IM		 37#include "ca0132_regs.h"
38
ef6b2ead
IM		 39/* Enable this to see controls for tuning purpose. */
40/*#define ENABLE_TUNING_CONTROLS*/
41
42#define FLOAT_ZERO 0x00000000
43#define FLOAT_ONE 0x3f800000
44#define FLOAT_TWO 0x40000000
45#define FLOAT_MINUS_5 0xc0a00000
46
47#define UNSOL_TAG_HP 0x10
48#define UNSOL_TAG_AMIC1 0x12
49#define UNSOL_TAG_DSP 0x16
50
4aa3bb0c
IM		 51#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
52#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
53
54#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
55#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
56#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
57
58#define MASTERCONTROL 0x80
ef6b2ead
IM		 59#define MASTERCONTROL_ALLOC_DMA_CHAN 10
60#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 61
95c6e9cb
IM		 62#define WIDGET_CHIP_CTRL 0x15
63#define WIDGET_DSP_CTRL 0x16
64
4aa3bb0c
IM		 65#define MEM_CONNID_MICIN1 3
66#define MEM_CONNID_MICIN2 5
67#define MEM_CONNID_MICOUT1 12
68#define MEM_CONNID_MICOUT2 14
69#define MEM_CONNID_WUH 10
70#define MEM_CONNID_DSP 16
71#define MEM_CONNID_DMIC 100
72
73#define SCP_SET 0
74#define SCP_GET 1
75
01ef7dbf
IM		 76#define EFX_FILE "ctefx.bin"
77
78MODULE_FIRMWARE(EFX_FILE);
79
ef6b2ead
IM		 80static char *dirstr[2] = { "Playback", "Capture" };
81
82enum {
83 SPEAKER_OUT,
84 HEADPHONE_OUT
85};
86
87enum {
88 DIGITAL_MIC,
89 LINE_MIC_IN
90};
91
92enum {
93#define VNODE_START_NID 0x80
94 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
95 VNID_MIC,
96 VNID_HP_SEL,
97 VNID_AMIC1_SEL,
98 VNID_HP_ASEL,
99 VNID_AMIC1_ASEL,
100 VNODE_END_NID,
101#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
102
103#define EFFECT_START_NID 0x90
104#define OUT_EFFECT_START_NID EFFECT_START_NID
105 SURROUND = OUT_EFFECT_START_NID,
106 CRYSTALIZER,
107 DIALOG_PLUS,
108 SMART_VOLUME,
109 X_BASS,
110 EQUALIZER,
111 OUT_EFFECT_END_NID,
112#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
113
114#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
115 ECHO_CANCELLATION = IN_EFFECT_START_NID,
116 VOICE_FOCUS,
117 MIC_SVM,
118 NOISE_REDUCTION,
119 IN_EFFECT_END_NID,
120#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
121
122 VOICEFX = IN_EFFECT_END_NID,
123 PLAY_ENHANCEMENT,
124 CRYSTAL_VOICE,
125 EFFECT_END_NID
126#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
127};
128
129/* Effects values size*/
130#define EFFECT_VALS_MAX_COUNT 12
131
132struct ct_effect {
133 char name[44];
134 hda_nid_t nid;
135 int mid; /*effect module ID*/
136 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
137 int direct; /* 0:output; 1:input*/
138 int params; /* number of default non-on/off params */
139 /*effect default values, 1st is on/off. */
140 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
141};
142
143#define EFX_DIR_OUT 0
144#define EFX_DIR_IN 1
145
146static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
147 { .name = "Surround",
148 .nid = SURROUND,
149 .mid = 0x96,
150 .reqs = {0, 1},
151 .direct = EFX_DIR_OUT,
152 .params = 1,
153 .def_vals = {0x3F800000, 0x3F2B851F}
154 },
155 { .name = "Crystalizer",
156 .nid = CRYSTALIZER,
157 .mid = 0x96,
158 .reqs = {7, 8},
159 .direct = EFX_DIR_OUT,
160 .params = 1,
161 .def_vals = {0x3F800000, 0x3F266666}
162 },
163 { .name = "Dialog Plus",
164 .nid = DIALOG_PLUS,
165 .mid = 0x96,
166 .reqs = {2, 3},
167 .direct = EFX_DIR_OUT,
168 .params = 1,
169 .def_vals = {0x00000000, 0x3F000000}
170 },
171 { .name = "Smart Volume",
172 .nid = SMART_VOLUME,
173 .mid = 0x96,
174 .reqs = {4, 5, 6},
175 .direct = EFX_DIR_OUT,
176 .params = 2,
177 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
178 },
179 { .name = "X-Bass",
180 .nid = X_BASS,
181 .mid = 0x96,
182 .reqs = {24, 23, 25},
183 .direct = EFX_DIR_OUT,
184 .params = 2,
185 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
186 },
187 { .name = "Equalizer",
188 .nid = EQUALIZER,
189 .mid = 0x96,
190 .reqs = {9, 10, 11, 12, 13, 14,
191 15, 16, 17, 18, 19, 20},
192 .direct = EFX_DIR_OUT,
193 .params = 11,
194 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
195 0x00000000, 0x00000000, 0x00000000, 0x00000000,
196 0x00000000, 0x00000000, 0x00000000, 0x00000000}
197 },
198 { .name = "Echo Cancellation",
199 .nid = ECHO_CANCELLATION,
200 .mid = 0x95,
201 .reqs = {0, 1, 2, 3},
202 .direct = EFX_DIR_IN,
203 .params = 3,
204 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
205 },
206 { .name = "Voice Focus",
207 .nid = VOICE_FOCUS,
208 .mid = 0x95,
209 .reqs = {6, 7, 8, 9},
210 .direct = EFX_DIR_IN,
211 .params = 3,
212 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
213 },
214 { .name = "Mic SVM",
215 .nid = MIC_SVM,
216 .mid = 0x95,
217 .reqs = {44, 45},
218 .direct = EFX_DIR_IN,
219 .params = 1,
220 .def_vals = {0x00000000, 0x3F3D70A4}
221 },
222 { .name = "Noise Reduction",
223 .nid = NOISE_REDUCTION,
224 .mid = 0x95,
225 .reqs = {4, 5},
226 .direct = EFX_DIR_IN,
227 .params = 1,
228 .def_vals = {0x3F800000, 0x3F000000}
229 },
230 { .name = "VoiceFX",
231 .nid = VOICEFX,
232 .mid = 0x95,
233 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
234 .direct = EFX_DIR_IN,
235 .params = 8,
236 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
237 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
238 0x00000000}
239 }
240};
241
242/* Tuning controls */
243#ifdef ENABLE_TUNING_CONTROLS
244
245enum {
246#define TUNING_CTL_START_NID 0xC0
247 WEDGE_ANGLE = TUNING_CTL_START_NID,
248 SVM_LEVEL,
249 EQUALIZER_BAND_0,
250 EQUALIZER_BAND_1,
251 EQUALIZER_BAND_2,
252 EQUALIZER_BAND_3,
253 EQUALIZER_BAND_4,
254 EQUALIZER_BAND_5,
255 EQUALIZER_BAND_6,
256 EQUALIZER_BAND_7,
257 EQUALIZER_BAND_8,
258 EQUALIZER_BAND_9,
259 TUNING_CTL_END_NID
260#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
261};
262
263struct ct_tuning_ctl {
264 char name[44];
265 hda_nid_t parent_nid;
266 hda_nid_t nid;
267 int mid; /*effect module ID*/
268 int req; /*effect module request*/
269 int direct; /* 0:output; 1:input*/
270 unsigned int def_val;/*effect default values*/
271};
272
273static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
274 { .name = "Wedge Angle",
275 .parent_nid = VOICE_FOCUS,
276 .nid = WEDGE_ANGLE,
277 .mid = 0x95,
278 .req = 8,
279 .direct = EFX_DIR_IN,
280 .def_val = 0x41F00000
281 },
282 { .name = "SVM Level",
283 .parent_nid = MIC_SVM,
284 .nid = SVM_LEVEL,
285 .mid = 0x95,
286 .req = 45,
287 .direct = EFX_DIR_IN,
288 .def_val = 0x3F3D70A4
289 },
290 { .name = "EQ Band0",
291 .parent_nid = EQUALIZER,
292 .nid = EQUALIZER_BAND_0,
293 .mid = 0x96,
294 .req = 11,
295 .direct = EFX_DIR_OUT,
296 .def_val = 0x00000000
297 },
298 { .name = "EQ Band1",
299 .parent_nid = EQUALIZER,
300 .nid = EQUALIZER_BAND_1,
301 .mid = 0x96,
302 .req = 12,
303 .direct = EFX_DIR_OUT,
304 .def_val = 0x00000000
305 },
306 { .name = "EQ Band2",
307 .parent_nid = EQUALIZER,
308 .nid = EQUALIZER_BAND_2,
309 .mid = 0x96,
310 .req = 13,
311 .direct = EFX_DIR_OUT,
312 .def_val = 0x00000000
313 },
314 { .name = "EQ Band3",
315 .parent_nid = EQUALIZER,
316 .nid = EQUALIZER_BAND_3,
317 .mid = 0x96,
318 .req = 14,
319 .direct = EFX_DIR_OUT,
320 .def_val = 0x00000000
321 },
322 { .name = "EQ Band4",
323 .parent_nid = EQUALIZER,
324 .nid = EQUALIZER_BAND_4,
325 .mid = 0x96,
326 .req = 15,
327 .direct = EFX_DIR_OUT,
328 .def_val = 0x00000000
329 },
330 { .name = "EQ Band5",
331 .parent_nid = EQUALIZER,
332 .nid = EQUALIZER_BAND_5,
333 .mid = 0x96,
334 .req = 16,
335 .direct = EFX_DIR_OUT,
336 .def_val = 0x00000000
337 },
338 { .name = "EQ Band6",
339 .parent_nid = EQUALIZER,
340 .nid = EQUALIZER_BAND_6,
341 .mid = 0x96,
342 .req = 17,
343 .direct = EFX_DIR_OUT,
344 .def_val = 0x00000000
345 },
346 { .name = "EQ Band7",
347 .parent_nid = EQUALIZER,
348 .nid = EQUALIZER_BAND_7,
349 .mid = 0x96,
350 .req = 18,
351 .direct = EFX_DIR_OUT,
352 .def_val = 0x00000000
353 },
354 { .name = "EQ Band8",
355 .parent_nid = EQUALIZER,
356 .nid = EQUALIZER_BAND_8,
357 .mid = 0x96,
358 .req = 19,
359 .direct = EFX_DIR_OUT,
360 .def_val = 0x00000000
361 },
362 { .name = "EQ Band9",
363 .parent_nid = EQUALIZER,
364 .nid = EQUALIZER_BAND_9,
365 .mid = 0x96,
366 .req = 20,
367 .direct = EFX_DIR_OUT,
368 .def_val = 0x00000000
369 }
370};
371#endif
372
373/* Voice FX Presets */
374#define VOICEFX_MAX_PARAM_COUNT 9
375
376struct ct_voicefx {
377 char *name;
378 hda_nid_t nid;
379 int mid;
380 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
381};
382
383struct ct_voicefx_preset {
384 char *name; /*preset name*/
385 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
386};
387
388struct ct_voicefx ca0132_voicefx = {
389 .name = "VoiceFX Capture Switch",
390 .nid = VOICEFX,
391 .mid = 0x95,
392 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
393};
394
395struct ct_voicefx_preset ca0132_voicefx_presets[] = {
396 { .name = "Neutral",
397 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
398 0x44FA0000, 0x3F800000, 0x3F800000,
399 0x3F800000, 0x00000000, 0x00000000 }
400 },
401 { .name = "Female2Male",
402 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
403 0x44FA0000, 0x3F19999A, 0x3F866666,
404 0x3F800000, 0x00000000, 0x00000000 }
405 },
406 { .name = "Male2Female",
407 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
408 0x450AC000, 0x4017AE14, 0x3F6B851F,
409 0x3F800000, 0x00000000, 0x00000000 }
410 },
411 { .name = "ScrappyKid",
412 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
413 0x44FA0000, 0x40400000, 0x3F28F5C3,
414 0x3F800000, 0x00000000, 0x00000000 }
415 },
416 { .name = "Elderly",
417 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
418 0x44E10000, 0x3FB33333, 0x3FB9999A,
419 0x3F800000, 0x3E3A2E43, 0x00000000 }
420 },
421 { .name = "Orc",
422 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
423 0x45098000, 0x3F266666, 0x3FC00000,
424 0x3F800000, 0x00000000, 0x00000000 }
425 },
426 { .name = "Elf",
427 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
428 0x45193000, 0x3F8E147B, 0x3F75C28F,
429 0x3F800000, 0x00000000, 0x00000000 }
430 },
431 { .name = "Dwarf",
432 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
433 0x45007000, 0x3F451EB8, 0x3F7851EC,
434 0x3F800000, 0x00000000, 0x00000000 }
435 },
436 { .name = "AlienBrute",
437 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
438 0x451F6000, 0x3F266666, 0x3FA7D945,
439 0x3F800000, 0x3CF5C28F, 0x00000000 }
440 },
441 { .name = "Robot",
442 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
443 0x44FA0000, 0x3FB2718B, 0x3F800000,
444 0xBC07010E, 0x00000000, 0x00000000 }
445 },
446 { .name = "Marine",
447 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
448 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
449 0x3F0A3D71, 0x00000000, 0x00000000 }
450 },
451 { .name = "Emo",
452 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
453 0x44FA0000, 0x3F800000, 0x3F800000,
454 0x3E4CCCCD, 0x00000000, 0x00000000 }
455 },
456 { .name = "DeepVoice",
457 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
458 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
459 0x3F800000, 0x00000000, 0x00000000 }
460 },
461 { .name = "Munchkin",
462 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
463 0x44FA0000, 0x3F800000, 0x3F1A043C,
464 0x3F800000, 0x00000000, 0x00000000 }
465 }
466};
467
95c6e9cb
IM		 468enum hda_cmd_vendor_io {
469 /* for DspIO node */
470 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
471 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
472
473 VENDOR_DSPIO_STATUS = 0xF01,
474 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
475 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
476 VENDOR_DSPIO_DSP_INIT = 0x703,
477 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
478 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
479
480 /* for ChipIO node */
481 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
482 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
483 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
484 VENDOR_CHIPIO_DATA_LOW = 0x300,
485 VENDOR_CHIPIO_DATA_HIGH = 0x400,
486
487 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
488 VENDOR_CHIPIO_STATUS = 0xF01,
489 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
490 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
491
4aa3bb0c
IM		 492 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
493 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
494
95c6e9cb 495 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 496 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 497
498 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
499 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
500 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
501 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
502 VENDOR_CHIPIO_FLAG_SET = 0x70F,
503 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 504 VENDOR_CHIPIO_PARAM_SET = 0x710,
505 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 506
507 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
508 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
509 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
510 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
511
4aa3bb0c
IM		 512 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
513 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
514 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
515 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
516
517 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
518 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
519 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
520 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
521 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
522 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
523
524 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 525};
526
527/*
528 * Control flag IDs
529 */
530enum control_flag_id {
531 /* Connection manager stream setup is bypassed/enabled */
532 CONTROL_FLAG_C_MGR = 0,
533 /* DSP DMA is bypassed/enabled */
534 CONTROL_FLAG_DMA = 1,
535 /* 8051 'idle' mode is disabled/enabled */
536 CONTROL_FLAG_IDLE_ENABLE = 2,
537 /* Tracker for the SPDIF-in path is bypassed/enabled */
538 CONTROL_FLAG_TRACKER = 3,
539 /* DigitalOut to Spdif2Out connection is disabled/enabled */
540 CONTROL_FLAG_SPDIF2OUT = 4,
541 /* Digital Microphone is disabled/enabled */
542 CONTROL_FLAG_DMIC = 5,
543 /* ADC_B rate is 48 kHz/96 kHz */
544 CONTROL_FLAG_ADC_B_96KHZ = 6,
545 /* ADC_C rate is 48 kHz/96 kHz */
546 CONTROL_FLAG_ADC_C_96KHZ = 7,
547 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
548 CONTROL_FLAG_DAC_96KHZ = 8,
549 /* DSP rate is 48 kHz/96 kHz */
550 CONTROL_FLAG_DSP_96KHZ = 9,
551 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
552 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
553 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
554 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
555 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
556 CONTROL_FLAG_DECODE_LOOP = 12,
557 /* De-emphasis filter on DAC-1 disabled/enabled */
558 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
559 /* De-emphasis filter on DAC-2 disabled/enabled */
560 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
561 /* De-emphasis filter on DAC-3 disabled/enabled */
562 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
563 /* High-pass filter on ADC_B disabled/enabled */
564 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
565 /* High-pass filter on ADC_C disabled/enabled */
566 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
567 /* Common mode on Port_A disabled/enabled */
568 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
569 /* Common mode on Port_D disabled/enabled */
570 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
571 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
572 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
573 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 574 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 575 /* ASI rate is 48kHz/96kHz */
576 CONTROL_FLAG_ASI_96KHZ = 22,
577 /* DAC power settings able to control attached ports no/yes */
578 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
579 /* Clock Stop OK reporting is disabled/enabled */
580 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
581 /* Number of control flags */
582 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
583};
584
585/*
586 * Control parameter IDs
587 */
4aa3bb0c 588enum control_param_id {
ef6b2ead
IM		 589 /* 0: None, 1: Mic1In*/
590 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 591 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
592 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 593 /* Port A output stage gain setting to use when 16 Ohm output
594 * impedance is selected*/
595 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
596 /* Port D output stage gain setting to use when 16 Ohm output
597 * impedance is selected*/
598 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 599
600 /* Stream Control */
601
602 /* Select stream with the given ID */
603 CONTROL_PARAM_STREAM_ID = 24,
604 /* Source connection point for the selected stream */
605 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
606 /* Destination connection point for the selected stream */
607 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
608 /* Number of audio channels in the selected stream */
609 CONTROL_PARAM_STREAMS_CHANNELS = 27,
610 /*Enable control for the selected stream */
611 CONTROL_PARAM_STREAM_CONTROL = 28,
612
613 /* Connection Point Control */
614
615 /* Select connection point with the given ID */
616 CONTROL_PARAM_CONN_POINT_ID = 29,
617 /* Connection point sample rate */
618 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
619
620 /* Node Control */
621
622 /* Select HDA node with the given ID */
623 CONTROL_PARAM_NODE_ID = 31
624};
625
626/*
627 * Dsp Io Status codes
628 */
629enum hda_vendor_status_dspio {
630 /* Success */
631 VENDOR_STATUS_DSPIO_OK = 0x00,
632 /* Busy, unable to accept new command, the host must retry */
633 VENDOR_STATUS_DSPIO_BUSY = 0x01,
634 /* SCP command queue is full */
635 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
636 /* SCP response queue is empty */
637 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
638};
639
640/*
641 * Chip Io Status codes
642 */
643enum hda_vendor_status_chipio {
644 /* Success */
645 VENDOR_STATUS_CHIPIO_OK = 0x00,
646 /* Busy, unable to accept new command, the host must retry */
647 VENDOR_STATUS_CHIPIO_BUSY = 0x01
648};
649
650/*
651 * CA0132 sample rate
652 */
653enum ca0132_sample_rate {
654 SR_6_000 = 0x00,
655 SR_8_000 = 0x01,
656 SR_9_600 = 0x02,
657 SR_11_025 = 0x03,
658 SR_16_000 = 0x04,
659 SR_22_050 = 0x05,
660 SR_24_000 = 0x06,
661 SR_32_000 = 0x07,
662 SR_44_100 = 0x08,
663 SR_48_000 = 0x09,
664 SR_88_200 = 0x0A,
665 SR_96_000 = 0x0B,
666 SR_144_000 = 0x0C,
667 SR_176_400 = 0x0D,
668 SR_192_000 = 0x0E,
669 SR_384_000 = 0x0F,
670
671 SR_COUNT = 0x10,
672
673 SR_RATE_UNKNOWN = 0x1F
674};
675
95c6e9cb
IM		 676static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
677{
678 if (pin) {
5aaca44d
IM		 679 snd_hda_codec_write(codec, pin, 0,
680 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP);
95c6e9cb
IM		 681 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
682 snd_hda_codec_write(codec, pin, 0,
683 AC_VERB_SET_AMP_GAIN_MUTE,
684 AMP_OUT_UNMUTE);
685 }
8e13fc1c 686 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
95c6e9cb
IM		 687 snd_hda_codec_write(codec, dac, 0,
688 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
689}
690
691static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
692{
693 if (pin) {
5aaca44d
IM		 694 snd_hda_codec_write(codec, pin, 0,
695 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80);
95c6e9cb
IM		 696 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
697 snd_hda_codec_write(codec, pin, 0,
698 AC_VERB_SET_AMP_GAIN_MUTE,
699 AMP_IN_UNMUTE(0));
700 }
5aaca44d 701 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
95c6e9cb
IM		 702 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
703 AMP_IN_UNMUTE(0));
5aaca44d
IM		 704
705 /* init to 0 dB and unmute. */
706 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
707 HDA_AMP_VOLMASK, 0x5a);
708 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
709 HDA_AMP_MUTE, 0);
710 }
95c6e9cb
IM		 711}
712
01ef7dbf
IM		 713enum dsp_download_state {
714 DSP_DOWNLOAD_FAILED = -1,
715 DSP_DOWNLOAD_INIT = 0,
716 DSP_DOWNLOADING = 1,
717 DSP_DOWNLOADED = 2
718};
719
01ef7dbf
IM		 720/* retrieve parameters from hda format */
721#define get_hdafmt_chs(fmt) (fmt & 0xf)
722#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
723#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
724#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
725
726/*
727 * CA0132 specific
728 */
729
730struct ca0132_spec {
a7e76271
IM		 731 struct snd_kcontrol_new *mixers[5];
732 unsigned int num_mixers;
5aaca44d
IM		 733 const struct hda_verb *base_init_verbs;
734 const struct hda_verb *base_exit_verbs;
735 const struct hda_verb *init_verbs[5];
736 unsigned int num_init_verbs; /* exclude base init verbs */
01ef7dbf 737 struct auto_pin_cfg autocfg;
5aaca44d
IM		 738
739 /* Nodes configurations */
01ef7dbf
IM		 740 struct hda_multi_out multiout;
741 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
742 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 743 unsigned int num_outputs;
01ef7dbf
IM		 744 hda_nid_t input_pins[AUTO_PIN_LAST];
745 hda_nid_t adcs[AUTO_PIN_LAST];
746 hda_nid_t dig_out;
747 hda_nid_t dig_in;
748 unsigned int num_inputs;
a7e76271
IM		 749 hda_nid_t shared_mic_nid;
750 hda_nid_t shared_out_nid;
5aaca44d 751 struct hda_pcm pcm_rec[5]; /* PCM information */
01ef7dbf
IM		 752
753 /* chip access */
754 struct mutex chipio_mutex; /* chip access mutex */
755 u32 curr_chip_addx;
756
757 /* DSP download related */
758 enum dsp_download_state dsp_state;
759 unsigned int dsp_stream_id;
760 unsigned int wait_scp;
761 unsigned int wait_scp_header;
762 unsigned int wait_num_data;
763 unsigned int scp_resp_header;
764 unsigned int scp_resp_data[4];
765 unsigned int scp_resp_count;
5aaca44d
IM		 766
767 /* mixer and effects related */
768 unsigned char dmic_ctl;
769 int cur_out_type;
770 int cur_mic_type;
771 long vnode_lvol[VNODES_COUNT];
772 long vnode_rvol[VNODES_COUNT];
773 long vnode_lswitch[VNODES_COUNT];
774 long vnode_rswitch[VNODES_COUNT];
775 long effects_switch[EFFECTS_COUNT];
776 long voicefx_val;
777 long cur_mic_boost;
01ef7dbf
IM		 778};
779
780/*
781 * CA0132 codec access
782 */
783unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
784 unsigned int verb, unsigned int parm, unsigned int *res)
785{
786 unsigned int response;
787 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
788 *res = response;
789
790 return ((response == -1) ? -1 : 0);
791}
792
793static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
794 unsigned short converter_format, unsigned int *res)
795{
796 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
797 converter_format & 0xffff, res);
798}
799
800static int codec_set_converter_stream_channel(struct hda_codec *codec,
801 hda_nid_t nid, unsigned char stream,
802 unsigned char channel, unsigned int *res)
803{
804 unsigned char converter_stream_channel = 0;
805
806 converter_stream_channel = (stream << 4) | (channel & 0x0f);
807 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
808 converter_stream_channel, res);
809}
810
811/* Chip access helper function */
812static int chipio_send(struct hda_codec *codec,
813 unsigned int reg,
814 unsigned int data)
815{
816 unsigned int res;
817 int retry = 50;
818
819 /* send bits of data specified by reg */
820 do {
821 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
822 reg, data);
823 if (res == VENDOR_STATUS_CHIPIO_OK)
824 return 0;
825 } while (--retry);
826 return -EIO;
827}
828
829/*
830 * Write chip address through the vendor widget -- NOT protected by the Mutex!
831 */
832static int chipio_write_address(struct hda_codec *codec,
833 unsigned int chip_addx)
834{
4861af80 835 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 836 int res;
837
4861af80
IM		 838 if (spec->curr_chip_addx == chip_addx)
839 return 0;
840
01ef7dbf
IM		 841 /* send low 16 bits of the address */
842 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
843 chip_addx & 0xffff);
844
845 if (res != -EIO) {
846 /* send high 16 bits of the address */
847 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
848 chip_addx >> 16);
849 }
850
4861af80 851 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
01ef7dbf 852
4861af80 853 return res;
01ef7dbf
IM		 854}
855
856/*
857 * Write data through the vendor widget -- NOT protected by the Mutex!
858 */
01ef7dbf
IM		 859static int chipio_write_data(struct hda_codec *codec, unsigned int data)
860{
5aaca44d 861 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 862 int res;
863
864 /* send low 16 bits of the data */
865 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
866
867 if (res != -EIO) {
868 /* send high 16 bits of the data */
869 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
870 data >> 16);
871 }
872
5aaca44d
IM		 873 /*If no error encountered, automatically increment the address
874 as per chip behaviour*/
875 spec->curr_chip_addx = (res != -EIO) ?
876 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 877 return res;
878}
879
d5c21b88
IM		 880/*
881 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
882 */
01ef7dbf
IM		 883static int chipio_write_data_multiple(struct hda_codec *codec,
884 const u32 *data,
885 unsigned int count)
886{
887 int status = 0;
888
889 if (data == NULL) {
890 snd_printdd(KERN_ERR "chipio_write_data null ptr");
891 return -EINVAL;
892 }
893
894 while ((count-- != 0) && (status == 0))
895 status = chipio_write_data(codec, *data++);
896
897 return status;
898}
899
900
901/*
902 * Read data through the vendor widget -- NOT protected by the Mutex!
903 */
904static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
905{
5aaca44d 906 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 907 int res;
908
909 /* post read */
910 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
911
912 if (res != -EIO) {
913 /* read status */
914 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
915 }
916
917 if (res != -EIO) {
918 /* read data */
919 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
920 VENDOR_CHIPIO_HIC_READ_DATA,
921 0);
922 }
923
5aaca44d
IM		 924 /*If no error encountered, automatically increment the address
925 as per chip behaviour*/
926 spec->curr_chip_addx = (res != -EIO) ?
927 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 928 return res;
929}
930
931/*
932 * Write given value to the given address through the chip I/O widget.
933 * protected by the Mutex
934 */
935static int chipio_write(struct hda_codec *codec,
936 unsigned int chip_addx, const unsigned int data)
937{
938 struct ca0132_spec *spec = codec->spec;
939 int err;
940
941 mutex_lock(&spec->chipio_mutex);
942
943 /* write the address, and if successful proceed to write data */
944 err = chipio_write_address(codec, chip_addx);
945 if (err < 0)
946 goto exit;
947
948 err = chipio_write_data(codec, data);
949 if (err < 0)
950 goto exit;
951
952exit:
953 mutex_unlock(&spec->chipio_mutex);
954 return err;
955}
956
d5c21b88
IM		 957/*
958 * Write multiple values to the given address through the chip I/O widget.
959 * protected by the Mutex
960 */
01ef7dbf
IM		 961static int chipio_write_multiple(struct hda_codec *codec,
962 u32 chip_addx,
963 const u32 *data,
964 unsigned int count)
965{
966 struct ca0132_spec *spec = codec->spec;
967 int status;
968
969 mutex_lock(&spec->chipio_mutex);
4861af80 970 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 971 if (status < 0)
972 goto error;
973
974 status = chipio_write_data_multiple(codec, data, count);
975error:
976 mutex_unlock(&spec->chipio_mutex);
977
978 return status;
979}
980
981/*
982 * Read the given address through the chip I/O widget
983 * protected by the Mutex
984 */
985static int chipio_read(struct hda_codec *codec,
986 unsigned int chip_addx, unsigned int *data)
987{
988 struct ca0132_spec *spec = codec->spec;
989 int err;
990
991 mutex_lock(&spec->chipio_mutex);
992
993 /* write the address, and if successful proceed to write data */
994 err = chipio_write_address(codec, chip_addx);
995 if (err < 0)
996 goto exit;
997
998 err = chipio_read_data(codec, data);
999 if (err < 0)
1000 goto exit;
1001
1002exit:
1003 mutex_unlock(&spec->chipio_mutex);
1004 return err;
1005}
1006
d5c21b88
IM		 1007/*
1008 * Set chip control flags through the chip I/O widget.
1009 */
01ef7dbf
IM		 1010static void chipio_set_control_flag(struct hda_codec *codec,
1011 enum control_flag_id flag_id,
1012 bool flag_state)
1013{
1014 unsigned int val;
1015 unsigned int flag_bit;
1016
1017 flag_bit = (flag_state ? 1 : 0);
1018 val = (flag_bit << 7) | (flag_id);
1019 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1020 VENDOR_CHIPIO_FLAG_SET, val);
1021}
1022
d5c21b88
IM		 1023/*
1024 * Set chip parameters through the chip I/O widget.
1025 */
01ef7dbf
IM		 1026static void chipio_set_control_param(struct hda_codec *codec,
1027 enum control_param_id param_id, int param_val)
1028{
1029 struct ca0132_spec *spec = codec->spec;
1030 int val;
1031
1032 if ((param_id < 32) && (param_val < 8)) {
1033 val = (param_val << 5) | (param_id);
1034 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1035 VENDOR_CHIPIO_PARAM_SET, val);
1036 } else {
1037 mutex_lock(&spec->chipio_mutex);
1038 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1039 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1040 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1041 param_id);
1042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1043 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1044 param_val);
1045 }
1046 mutex_unlock(&spec->chipio_mutex);
1047 }
1048}
1049
d5c21b88
IM		 1050/*
1051 * Set sampling rate of the connection point.
1052 */
01ef7dbf
IM		 1053static void chipio_set_conn_rate(struct hda_codec *codec,
1054 int connid, enum ca0132_sample_rate rate)
1055{
1056 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1057 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1058 rate);
1059}
1060
d5c21b88
IM		 1061/*
1062 * Enable clocks.
1063 */
01ef7dbf
IM		 1064static void chipio_enable_clocks(struct hda_codec *codec)
1065{
1066 struct ca0132_spec *spec = codec->spec;
1067
1068 mutex_lock(&spec->chipio_mutex);
1069 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1070 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1071 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1072 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1073 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1074 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1075 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1076 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1077 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1078 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1079 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1080 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1081 mutex_unlock(&spec->chipio_mutex);
1082}
1083
1084/*
1085 * CA0132 DSP IO stuffs
1086 */
1087static int dspio_send(struct hda_codec *codec, unsigned int reg,
1088 unsigned int data)
1089{
1090 unsigned int res;
1091 int retry = 50;
1092
1093 /* send bits of data specified by reg to dsp */
1094 do {
1095 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1096 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1097 return res;
1098 } while (--retry);
1099
1100 return -EIO;
1101}
1102
d5c21b88
IM		 1103/*
1104 * Wait for DSP to be ready for commands
1105 */
01ef7dbf
IM		 1106static void dspio_write_wait(struct hda_codec *codec)
1107{
4861af80
IM		 1108 int status;
1109 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1110
01ef7dbf 1111 do {
4861af80
IM		 1112 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1113 VENDOR_DSPIO_STATUS, 0);
1114 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1115 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1116 break;
1117 msleep(1);
1118 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1119}
1120
d5c21b88
IM		 1121/*
1122 * Write SCP data to DSP
1123 */
01ef7dbf
IM		 1124static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1125{
1126 struct ca0132_spec *spec = codec->spec;
1127 int status;
1128
1129 dspio_write_wait(codec);
1130
1131 mutex_lock(&spec->chipio_mutex);
1132 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1133 scp_data & 0xffff);
1134 if (status < 0)
1135 goto error;
1136
1137 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1138 scp_data >> 16);
1139 if (status < 0)
1140 goto error;
1141
1142 /* OK, now check if the write itself has executed*/
1143 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1144 VENDOR_DSPIO_STATUS, 0);
1145error:
1146 mutex_unlock(&spec->chipio_mutex);
1147
1148 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1149 -EIO : 0;
1150}
1151
d5c21b88
IM		 1152/*
1153 * Write multiple SCP data to DSP
1154 */
01ef7dbf
IM		 1155static int dspio_write_multiple(struct hda_codec *codec,
1156 unsigned int *buffer, unsigned int size)
1157{
1158 int status = 0;
1159 unsigned int count;
1160
1161 if ((buffer == NULL))
1162 return -EINVAL;
1163
1164 count = 0;
1165 while (count < size) {
1166 status = dspio_write(codec, *buffer++);
1167 if (status != 0)
1168 break;
1169 count++;
1170 }
1171
1172 return status;
1173}
1174
d5c21b88
IM		 1175/*
1176 * Construct the SCP header using corresponding fields
1177 */
01ef7dbf
IM		 1178static inline unsigned int
1179make_scp_header(unsigned int target_id, unsigned int source_id,
1180 unsigned int get_flag, unsigned int req,
1181 unsigned int device_flag, unsigned int resp_flag,
1182 unsigned int error_flag, unsigned int data_size)
1183{
1184 unsigned int header = 0;
1185
1186 header = (data_size & 0x1f) << 27;
1187 header |= (error_flag & 0x01) << 26;
1188 header |= (resp_flag & 0x01) << 25;
1189 header |= (device_flag & 0x01) << 24;
1190 header |= (req & 0x7f) << 17;
1191 header |= (get_flag & 0x01) << 16;
1192 header |= (source_id & 0xff) << 8;
1193 header |= target_id & 0xff;
1194
1195 return header;
1196}
1197
d5c21b88
IM		 1198/*
1199 * Extract corresponding fields from SCP header
1200 */
01ef7dbf
IM		 1201static inline void
1202extract_scp_header(unsigned int header,
1203 unsigned int *target_id, unsigned int *source_id,
1204 unsigned int *get_flag, unsigned int *req,
1205 unsigned int *device_flag, unsigned int *resp_flag,
1206 unsigned int *error_flag, unsigned int *data_size)
1207{
1208 if (data_size)
1209 *data_size = (header >> 27) & 0x1f;
1210 if (error_flag)
1211 *error_flag = (header >> 26) & 0x01;
1212 if (resp_flag)
1213 *resp_flag = (header >> 25) & 0x01;
1214 if (device_flag)
1215 *device_flag = (header >> 24) & 0x01;
1216 if (req)
1217 *req = (header >> 17) & 0x7f;
1218 if (get_flag)
1219 *get_flag = (header >> 16) & 0x01;
1220 if (source_id)
1221 *source_id = (header >> 8) & 0xff;
1222 if (target_id)
1223 *target_id = header & 0xff;
1224}
1225
1226#define SCP_MAX_DATA_WORDS (16)
1227
1228/* Structure to contain any SCP message */
1229struct scp_msg {
1230 unsigned int hdr;
1231 unsigned int data[SCP_MAX_DATA_WORDS];
1232};
1233
d5c21b88
IM		 1234/*
1235 * Send SCP message to DSP
1236 */
01ef7dbf
IM		 1237static int dspio_send_scp_message(struct hda_codec *codec,
1238 unsigned char *send_buf,
1239 unsigned int send_buf_size,
1240 unsigned char *return_buf,
1241 unsigned int return_buf_size,
1242 unsigned int *bytes_returned)
1243{
1244 struct ca0132_spec *spec = codec->spec;
1245 int retry;
1246 int status = -1;
1247 unsigned int scp_send_size = 0;
1248 unsigned int total_size;
1249 bool waiting_for_resp = false;
1250 unsigned int header;
1251 struct scp_msg *ret_msg;
1252 unsigned int resp_src_id, resp_target_id;
1253 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1254
1255 if (bytes_returned)
1256 *bytes_returned = 0;
1257
1258 /* get scp header from buffer */
1259 header = *((unsigned int *)send_buf);
1260 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1261 &device_flag, NULL, NULL, &data_size);
1262 scp_send_size = data_size + 1;
1263 total_size = (scp_send_size * 4);
1264
1265 if (send_buf_size < total_size)
1266 return -EINVAL;
1267
1268 if (get_flag || device_flag) {
1269 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1270 return -EINVAL;
1271
1272 spec->wait_scp_header = *((unsigned int *)send_buf);
1273
1274 /* swap source id with target id */
1275 resp_target_id = src_id;
1276 resp_src_id = target_id;
1277 spec->wait_scp_header &= 0xffff0000;
1278 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1279 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1280 spec->wait_scp = 1;
1281 waiting_for_resp = true;
1282 }
1283
1284 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1285 scp_send_size);
1286 if (status < 0) {
1287 spec->wait_scp = 0;
1288 return status;
1289 }
1290
1291 if (waiting_for_resp) {
1292 memset(return_buf, 0, return_buf_size);
1293 retry = 50;
1294 do {
1295 msleep(20);
1296 } while (spec->wait_scp && (--retry != 0));
1297 waiting_for_resp = false;
1298 if (retry != 0) {
1299 ret_msg = (struct scp_msg *)return_buf;
1300 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1301 memcpy(&ret_msg->data, spec->scp_resp_data,
1302 spec->wait_num_data);
1303 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1304 status = 0;
1305 } else {
1306 status = -EIO;
1307 }
1308 spec->wait_scp = 0;
1309 }
1310
1311 return status;
1312}
1313
d5c21b88
IM		 1314/**
1315 * Prepare and send the SCP message to DSP
1316 * @codec: the HDA codec
1317 * @mod_id: ID of the DSP module to send the command
1318 * @req: ID of request to send to the DSP module
1319 * @dir: SET or GET
1320 * @data: pointer to the data to send with the request, request specific
1321 * @len: length of the data, in bytes
1322 * @reply: point to the buffer to hold data returned for a reply
1323 * @reply_len: length of the reply buffer returned from GET
1324 *
1325 * Returns zero or a negative error code.
1326 */
01ef7dbf
IM		 1327static int dspio_scp(struct hda_codec *codec,
1328 int mod_id, int req, int dir, void *data, unsigned int len,
1329 void *reply, unsigned int *reply_len)
1330{
1331 int status = 0;
1332 struct scp_msg scp_send, scp_reply;
1333 unsigned int ret_bytes, send_size, ret_size;
1334 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1335 unsigned int reply_data_size;
1336
1337 memset(&scp_send, 0, sizeof(scp_send));
1338 memset(&scp_reply, 0, sizeof(scp_reply));
1339
1340 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1341 return -EINVAL;
1342
1343 if (dir == SCP_GET && reply == NULL) {
1344 snd_printdd(KERN_ERR "dspio_scp get but has no buffer");
1345 return -EINVAL;
1346 }
1347
1348 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1349 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms");
1350 return -EINVAL;
1351 }
1352
1353 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1354 0, 0, 0, len/sizeof(unsigned int));
1355 if (data != NULL && len > 0) {
1356 len = min((unsigned int)(sizeof(scp_send.data)), len);
1357 memcpy(scp_send.data, data, len);
1358 }
1359
1360 ret_bytes = 0;
1361 send_size = sizeof(unsigned int) + len;
1362 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1363 send_size, (unsigned char *)&scp_reply,
1364 sizeof(scp_reply), &ret_bytes);
1365
1366 if (status < 0) {
1367 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed");
1368 return status;
1369 }
1370
1371 /* extract send and reply headers members */
1372 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1373 NULL, NULL, NULL, NULL, NULL);
1374 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1375 &reply_resp_flag, &reply_error_flag,
1376 &reply_data_size);
1377
1378 if (!send_get_flag)
1379 return 0;
1380
1381 if (reply_resp_flag && !reply_error_flag) {
1382 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1383 / sizeof(unsigned int);
1384
1385 if (*reply_len < ret_size*sizeof(unsigned int)) {
1386 snd_printdd(KERN_ERR "reply too long for buf");
1387 return -EINVAL;
1388 } else if (ret_size != reply_data_size) {
1389 snd_printdd(KERN_ERR "RetLen and HdrLen .NE.");
1390 return -EINVAL;
1391 } else {
1392 *reply_len = ret_size*sizeof(unsigned int);
1393 memcpy(reply, scp_reply.data, *reply_len);
1394 }
1395 } else {
1396 snd_printdd(KERN_ERR "reply ill-formed or errflag set");
1397 return -EIO;
1398 }
1399
1400 return status;
1401}
1402
5aaca44d
IM		 1403/*
1404 * Set DSP parameters
1405 */
1406static int dspio_set_param(struct hda_codec *codec, int mod_id,
1407 int req, void *data, unsigned int len)
1408{
1409 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1410}
1411
1412static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1413 int req, unsigned int data)
1414{
1415 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1416}
1417
d5c21b88
IM		 1418/*
1419 * Allocate a DSP DMA channel via an SCP message
1420 */
01ef7dbf
IM		 1421static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1422{
1423 int status = 0;
1424 unsigned int size = sizeof(dma_chan);
1425
1426 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin");
1427 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1428 SCP_GET, NULL, 0, dma_chan, &size);
1429
1430 if (status < 0) {
1431 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed");
1432 return status;
1433 }
1434
1435 if ((*dma_chan + 1) == 0) {
1436 snd_printdd(KERN_INFO "no free dma channels to allocate");
1437 return -EBUSY;
1438 }
1439
1440 snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1441 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete");
1442
1443 return status;
1444}
1445
d5c21b88
IM		 1446/*
1447 * Free a DSP DMA via an SCP message
1448 */
01ef7dbf
IM		 1449static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1450{
1451 int status = 0;
1452 unsigned int dummy = 0;
1453
1454 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin");
1455 snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan);
1456
1457 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1458 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1459
1460 if (status < 0) {
1461 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed");
1462 return status;
1463 }
1464
1465 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete");
1466
1467 return status;
1468}
1469
1470/*
d5c21b88 1471 * (Re)start the DSP
01ef7dbf
IM		 1472 */
1473static int dsp_set_run_state(struct hda_codec *codec)
1474{
1475 unsigned int dbg_ctrl_reg;
1476 unsigned int halt_state;
1477 int err;
1478
1479 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1480 if (err < 0)
1481 return err;
1482
1483 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1484 DSP_DBGCNTL_STATE_LOBIT;
1485
1486 if (halt_state != 0) {
1487 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1488 DSP_DBGCNTL_SS_MASK);
1489 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1490 dbg_ctrl_reg);
1491 if (err < 0)
1492 return err;
1493
1494 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1495 DSP_DBGCNTL_EXEC_MASK;
1496 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1497 dbg_ctrl_reg);
1498 if (err < 0)
1499 return err;
1500 }
1501
1502 return 0;
1503}
1504
d5c21b88
IM		 1505/*
1506 * Reset the DSP
1507 */
01ef7dbf
IM		 1508static int dsp_reset(struct hda_codec *codec)
1509{
1510 unsigned int res;
1511 int retry = 20;
1512
1513 snd_printdd("dsp_reset\n");
1514 do {
1515 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1516 retry--;
1517 } while (res == -EIO && retry);
1518
1519 if (!retry) {
1520 snd_printdd("dsp_reset timeout\n");
1521 return -EIO;
1522 }
1523
1524 return 0;
1525}
1526
d5c21b88
IM		 1527/*
1528 * Convert chip address to DSP address
1529 */
01ef7dbf
IM		 1530static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1531 bool *code, bool *yram)
1532{
1533 *code = *yram = false;
1534
1535 if (UC_RANGE(chip_addx, 1)) {
1536 *code = true;
1537 return UC_OFF(chip_addx);
1538 } else if (X_RANGE_ALL(chip_addx, 1)) {
1539 return X_OFF(chip_addx);
1540 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1541 *yram = true;
1542 return Y_OFF(chip_addx);
1543 }
1544
1545 return (unsigned int)INVALID_CHIP_ADDRESS;
1546}
1547
d5c21b88
IM		 1548/*
1549 * Check if the DSP DMA is active
1550 */
01ef7dbf
IM		 1551static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1552{
1553 unsigned int dma_chnlstart_reg;
1554
1555 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1556
1557 return ((dma_chnlstart_reg & (1 <<
1558 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1559}
1560
1561static int dsp_dma_setup_common(struct hda_codec *codec,
1562 unsigned int chip_addx,
1563 unsigned int dma_chan,
1564 unsigned int port_map_mask,
1565 bool ovly)
1566{
1567 int status = 0;
1568 unsigned int chnl_prop;
1569 unsigned int dsp_addx;
1570 unsigned int active;
1571 bool code, yram;
1572
1573 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------");
1574
1575 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1576 snd_printdd(KERN_ERR "dma chan num invalid");
1577 return -EINVAL;
1578 }
1579
1580 if (dsp_is_dma_active(codec, dma_chan)) {
1581 snd_printdd(KERN_ERR "dma already active");
1582 return -EBUSY;
1583 }
1584
1585 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1586
1587 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1588 snd_printdd(KERN_ERR "invalid chip addr");
1589 return -ENXIO;
1590 }
1591
1592 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1593 active = 0;
1594
1595 snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm");
1596
1597 if (ovly) {
1598 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1599 &chnl_prop);
1600
1601 if (status < 0) {
1602 snd_printdd(KERN_ERR "read CHNLPROP Reg fail");
1603 return status;
1604 }
1605 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP");
1606 }
1607
1608 if (!code)
1609 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1610 else
1611 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1612
1613 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1614
1615 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1616 if (status < 0) {
1617 snd_printdd(KERN_ERR "write CHNLPROP Reg fail");
1618 return status;
1619 }
1620 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP");
1621
1622 if (ovly) {
1623 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1624 &active);
1625
1626 if (status < 0) {
1627 snd_printdd(KERN_ERR "read ACTIVE Reg fail");
1628 return status;
1629 }
1630 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE");
1631 }
1632
1633 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1634 DSPDMAC_ACTIVE_AAR_MASK;
1635
1636 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1637 if (status < 0) {
1638 snd_printdd(KERN_ERR "write ACTIVE Reg fail");
1639 return status;
1640 }
1641
1642 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE");
1643
1644 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1645 port_map_mask);
1646 if (status < 0) {
1647 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail");
1648 return status;
1649 }
1650 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL");
1651
1652 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1653 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1654 if (status < 0) {
1655 snd_printdd(KERN_ERR "write IRQCNT Reg fail");
1656 return status;
1657 }
1658 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT");
1659
1660 snd_printdd(
1661 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1662 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1663 chip_addx, dsp_addx, dma_chan,
1664 port_map_mask, chnl_prop, active);
1665
1666 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------");
1667
1668 return 0;
1669}
1670
d5c21b88
IM		 1671/*
1672 * Setup the DSP DMA per-transfer-specific registers
1673 */
01ef7dbf
IM		 1674static int dsp_dma_setup(struct hda_codec *codec,
1675 unsigned int chip_addx,
1676 unsigned int count,
1677 unsigned int dma_chan)
1678{
1679 int status = 0;
1680 bool code, yram;
1681 unsigned int dsp_addx;
1682 unsigned int addr_field;
1683 unsigned int incr_field;
1684 unsigned int base_cnt;
1685 unsigned int cur_cnt;
1686 unsigned int dma_cfg = 0;
1687 unsigned int adr_ofs = 0;
1688 unsigned int xfr_cnt = 0;
1689 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1690 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1691
1692 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------");
1693
1694 if (count > max_dma_count) {
1695 snd_printdd(KERN_ERR "count too big");
1696 return -EINVAL;
1697 }
1698
1699 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1700 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1701 snd_printdd(KERN_ERR "invalid chip addr");
1702 return -ENXIO;
1703 }
1704
1705 snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm");
1706
1707 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1708 incr_field = 0;
1709
1710 if (!code) {
1711 addr_field <<= 1;
1712 if (yram)
1713 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1714
1715 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1716 }
1717
1718 dma_cfg = addr_field + incr_field;
1719 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1720 dma_cfg);
1721 if (status < 0) {
1722 snd_printdd(KERN_ERR "write DMACFG Reg fail");
1723 return status;
1724 }
1725 snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG");
1726
1727 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1728 (code ? 0 : 1));
1729
1730 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1731 adr_ofs);
1732 if (status < 0) {
1733 snd_printdd(KERN_ERR "write DSPADROFS Reg fail");
1734 return status;
1735 }
1736 snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS");
1737
1738 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1739
1740 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1741
1742 xfr_cnt = base_cnt | cur_cnt;
1743
1744 status = chipio_write(codec,
1745 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1746 if (status < 0) {
1747 snd_printdd(KERN_ERR "write XFRCNT Reg fail");
1748 return status;
1749 }
1750 snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT");
1751
1752 snd_printdd(
1753 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1754 "ADROFS=0x%x, XFRCNT=0x%x\n",
1755 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1756
1757 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------");
1758
1759 return 0;
1760}
1761
d5c21b88
IM		 1762/*
1763 * Start the DSP DMA
1764 */
01ef7dbf
IM		 1765static int dsp_dma_start(struct hda_codec *codec,
1766 unsigned int dma_chan, bool ovly)
1767{
1768 unsigned int reg = 0;
1769 int status = 0;
1770
1771 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------");
1772
1773 if (ovly) {
1774 status = chipio_read(codec,
1775 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1776
1777 if (status < 0) {
1778 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1779 return status;
1780 }
1781 snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART");
1782
1783 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1784 DSPDMAC_CHNLSTART_DIS_MASK);
1785 }
1786
1787 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1788 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1789 if (status < 0) {
1790 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1791 return status;
1792 }
1793 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------");
1794
1795 return status;
1796}
1797
d5c21b88
IM		 1798/*
1799 * Stop the DSP DMA
1800 */
01ef7dbf
IM		 1801static int dsp_dma_stop(struct hda_codec *codec,
1802 unsigned int dma_chan, bool ovly)
1803{
1804 unsigned int reg = 0;
1805 int status = 0;
1806
1807 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------");
1808
1809 if (ovly) {
1810 status = chipio_read(codec,
1811 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1812
1813 if (status < 0) {
1814 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1815 return status;
1816 }
1817 snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART");
1818 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1819 DSPDMAC_CHNLSTART_DIS_MASK);
1820 }
1821
1822 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1823 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1824 if (status < 0) {
1825 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1826 return status;
1827 }
1828 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------");
1829
1830 return status;
1831}
1832
d5c21b88
IM		 1833/**
1834 * Allocate router ports
1835 *
1836 * @codec: the HDA codec
1837 * @num_chans: number of channels in the stream
1838 * @ports_per_channel: number of ports per channel
1839 * @start_device: start device
1840 * @port_map: pointer to the port list to hold the allocated ports
1841 *
1842 * Returns zero or a negative error code.
1843 */
01ef7dbf
IM		 1844static int dsp_allocate_router_ports(struct hda_codec *codec,
1845 unsigned int num_chans,
1846 unsigned int ports_per_channel,
1847 unsigned int start_device,
1848 unsigned int *port_map)
1849{
1850 int status = 0;
1851 int res;
1852 u8 val;
1853
1854 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1855 if (status < 0)
1856 return status;
1857
1858 val = start_device << 6;
1859 val |= (ports_per_channel - 1) << 4;
1860 val |= num_chans - 1;
1861
1862 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1863 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1864 val);
1865
1866 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1867 VENDOR_CHIPIO_PORT_ALLOC_SET,
1868 MEM_CONNID_DSP);
1869
1870 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1871 if (status < 0)
1872 return status;
1873
1874 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1875 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1876
1877 *port_map = res;
1878
1879 return (res < 0) ? res : 0;
1880}
1881
d5c21b88
IM		 1882/*
1883 * Free router ports
1884 */
01ef7dbf
IM		 1885static int dsp_free_router_ports(struct hda_codec *codec)
1886{
1887 int status = 0;
1888
1889 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1890 if (status < 0)
1891 return status;
1892
1893 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1894 VENDOR_CHIPIO_PORT_FREE_SET,
1895 MEM_CONNID_DSP);
1896
1897 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1898
1899 return status;
1900}
1901
d5c21b88
IM		 1902/*
1903 * Allocate DSP ports for the download stream
1904 */
01ef7dbf
IM		 1905static int dsp_allocate_ports(struct hda_codec *codec,
1906 unsigned int num_chans,
1907 unsigned int rate_multi, unsigned int *port_map)
1908{
1909 int status;
1910
1911 snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin");
1912
1913 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1914 snd_printdd(KERN_ERR "bad rate multiple");
1915 return -EINVAL;
1916 }
1917
1918 status = dsp_allocate_router_ports(codec, num_chans,
1919 rate_multi, 0, port_map);
1920
1921 snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete");
1922
1923 return status;
1924}
1925
01ef7dbf
IM		 1926static int dsp_allocate_ports_format(struct hda_codec *codec,
1927 const unsigned short fmt,
1928 unsigned int *port_map)
1929{
1930 int status;
1931 unsigned int num_chans;
1932
1933 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1934 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1935 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
1936
1937 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1938 snd_printdd(KERN_ERR "bad rate multiple");
1939 return -EINVAL;
1940 }
1941
1942 num_chans = get_hdafmt_chs(fmt) + 1;
1943
1944 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
1945
1946 return status;
1947}
1948
d5c21b88
IM		 1949/*
1950 * free DSP ports
1951 */
1952static int dsp_free_ports(struct hda_codec *codec)
1953{
1954 int status;
1955
1956 snd_printdd(KERN_INFO " dsp_free_ports() -- begin");
1957
1958 status = dsp_free_router_ports(codec);
1959 if (status < 0) {
1960 snd_printdd(KERN_ERR "free router ports fail");
1961 return status;
1962 }
1963 snd_printdd(KERN_INFO " dsp_free_ports() -- complete");
1964
1965 return status;
1966}
1967
01ef7dbf
IM		 1968/*
1969 * HDA DMA engine stuffs for DSP code download
1970 */
1971struct dma_engine {
1972 struct hda_codec *codec;
1973 unsigned short m_converter_format;
1974 struct snd_dma_buffer *dmab;
1975 unsigned int buf_size;
1976};
1977
1978
1979enum dma_state {
1980 DMA_STATE_STOP = 0,
1981 DMA_STATE_RUN = 1
1982};
1983
1984static int dma_convert_to_hda_format(
e97249dd
IM		 1985 unsigned int sample_rate,
1986 unsigned short channels,
01ef7dbf
IM		 1987 unsigned short *hda_format)
1988{
1989 unsigned int format_val;
1990
1991 format_val = snd_hda_calc_stream_format(
e97249dd
IM		 1992 sample_rate,
1993 channels,
01ef7dbf 1994 SNDRV_PCM_FORMAT_S32_LE,
e97249dd 1995 32, 0);
01ef7dbf
IM		 1996
1997 if (hda_format)
1998 *hda_format = (unsigned short)format_val;
1999
2000 return 0;
2001}
2002
d5c21b88
IM		 2003/*
2004 * Reset DMA for DSP download
2005 */
01ef7dbf
IM		 2006static int dma_reset(struct dma_engine *dma)
2007{
2008 struct hda_codec *codec = dma->codec;
2009 struct ca0132_spec *spec = codec->spec;
2010 int status;
2011
2012 if (dma->dmab)
2013 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2014
2015 status = snd_hda_codec_load_dsp_prepare(codec,
2016 dma->m_converter_format,
2017 dma->buf_size,
2018 dma->dmab);
2019 if (status < 0)
2020 return status;
2021 spec->dsp_stream_id = status;
2022 return 0;
2023}
2024
2025static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2026{
01ef7dbf
IM		 2027 bool cmd;
2028
2029 snd_printdd("dma_set_state state=%d\n", state);
2030
2031 switch (state) {
2032 case DMA_STATE_STOP:
2033 cmd = false;
2034 break;
2035 case DMA_STATE_RUN:
2036 cmd = true;
2037 break;
2038 default:
c41999a2
DH		 2039 return 0;
2040 }
01ef7dbf
IM		 2041
2042 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2043 return 0;
95c6e9cb
IM		 2044}
2045
01ef7dbf
IM		 2046static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2047{
2048 return dma->dmab->bytes;
2049}
95c6e9cb 2050
01ef7dbf
IM		 2051static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2052{
2053 return dma->dmab->area;
2054}
95c6e9cb 2055
01ef7dbf
IM		 2056static int dma_xfer(struct dma_engine *dma,
2057 const unsigned int *data,
2058 unsigned int count)
2059{
2060 memcpy(dma->dmab->area, data, count);
2061 return 0;
2062}
95c6e9cb 2063
01ef7dbf
IM		 2064static void dma_get_converter_format(
2065 struct dma_engine *dma,
2066 unsigned short *format)
2067{
2068 if (format)
2069 *format = dma->m_converter_format;
2070}
95c6e9cb 2071
01ef7dbf 2072static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2073{
01ef7dbf 2074 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2075
01ef7dbf 2076 return spec->dsp_stream_id;
95c6e9cb
IM		 2077}
2078
01ef7dbf
IM		 2079struct dsp_image_seg {
2080 u32 magic;
2081 u32 chip_addr;
2082 u32 count;
2083 u32 data[0];
2084};
2085
2086static const u32 g_magic_value = 0x4c46584d;
2087static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2088
2089static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2090{
01ef7dbf
IM		 2091 return p->magic == g_magic_value;
2092}
95c6e9cb 2093
01ef7dbf
IM		 2094static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2095{
2096 return g_chip_addr_magic_value == p->chip_addr;
2097}
95c6e9cb 2098
01ef7dbf
IM		 2099static bool is_last(const struct dsp_image_seg *p)
2100{
2101 return p->count == 0;
2102}
95c6e9cb 2103
01ef7dbf
IM		 2104static size_t dsp_sizeof(const struct dsp_image_seg *p)
2105{
2106 return sizeof(*p) + p->count*sizeof(u32);
2107}
2108
2109static const struct dsp_image_seg *get_next_seg_ptr(
2110 const struct dsp_image_seg *p)
2111{
2112 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2113}
2114
2115/*
01ef7dbf 2116 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2117 */
01ef7dbf 2118#define INVALID_DMA_CHANNEL (~0UL)
95c6e9cb 2119
d5c21b88
IM		 2120/*
2121 * Program a list of address/data pairs via the ChipIO widget.
2122 * The segment data is in the format of successive pairs of words.
2123 * These are repeated as indicated by the segment's count field.
2124 */
01ef7dbf
IM		 2125static int dspxfr_hci_write(struct hda_codec *codec,
2126 const struct dsp_image_seg *fls)
95c6e9cb 2127{
01ef7dbf
IM		 2128 int status;
2129 const u32 *data;
2130 unsigned int count;
95c6e9cb 2131
01ef7dbf
IM		 2132 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2133 snd_printdd(KERN_ERR "hci_write invalid params");
2134 return -EINVAL;
95c6e9cb
IM		 2135 }
2136
01ef7dbf
IM		 2137 count = fls->count;
2138 data = (u32 *)(fls->data);
2139 while (count >= 2) {
2140 status = chipio_write(codec, data[0], data[1]);
2141 if (status < 0) {
2142 snd_printdd(KERN_ERR "hci_write chipio failed");
2143 return status;
2144 }
2145 count -= 2;
2146 data += 2;
2147 }
2148 return 0;
95c6e9cb
IM		 2149}
2150
d5c21b88
IM		 2151/**
2152 * Write a block of data into DSP code or data RAM using pre-allocated
2153 * DMA engine.
2154 *
2155 * @codec: the HDA codec
2156 * @fls: pointer to a fast load image
2157 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2158 * no relocation
2159 * @dma_engine: pointer to DMA engine to be used for DSP download
2160 * @dma_chan: The number of DMA channels used for DSP download
2161 * @port_map_mask: port mapping
2162 * @ovly: TRUE if overlay format is required
2163 *
2164 * Returns zero or a negative error code.
2165 */
01ef7dbf
IM		 2166static int dspxfr_one_seg(struct hda_codec *codec,
2167 const struct dsp_image_seg *fls,
2168 unsigned int reloc,
2169 struct dma_engine *dma_engine,
2170 unsigned int dma_chan,
2171 unsigned int port_map_mask,
2172 bool ovly)
95c6e9cb 2173{
01ef7dbf
IM		 2174 int status;
2175 bool comm_dma_setup_done = false;
2176 const unsigned int *data;
2177 unsigned int chip_addx;
2178 unsigned int words_to_write;
2179 unsigned int buffer_size_words;
2180 unsigned char *buffer_addx;
2181 unsigned short hda_format;
2182 unsigned int sample_rate_div;
2183 unsigned int sample_rate_mul;
2184 unsigned int num_chans;
2185 unsigned int hda_frame_size_words;
2186 unsigned int remainder_words;
2187 const u32 *data_remainder;
2188 u32 chip_addx_remainder;
2189 unsigned int run_size_words;
2190 const struct dsp_image_seg *hci_write = NULL;
2191 int retry;
2192
2193 if (fls == NULL)
2194 return -EINVAL;
2195 if (is_hci_prog_list_seg(fls)) {
2196 hci_write = fls;
2197 fls = get_next_seg_ptr(fls);
2198 }
95c6e9cb 2199
01ef7dbf
IM		 2200 if (hci_write && (!fls || is_last(fls))) {
2201 snd_printdd("hci_write\n");
2202 return dspxfr_hci_write(codec, hci_write);
2203 }
95c6e9cb 2204
01ef7dbf
IM		 2205 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2206 snd_printdd("Invalid Params\n");
2207 return -EINVAL;
95c6e9cb
IM		 2208 }
2209
01ef7dbf
IM		 2210 data = fls->data;
2211 chip_addx = fls->chip_addr,
2212 words_to_write = fls->count;
2213
2214 if (!words_to_write)
2215 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2216 if (reloc)
2217 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2218
2219 if (!UC_RANGE(chip_addx, words_to_write) &&
2220 !X_RANGE_ALL(chip_addx, words_to_write) &&
2221 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2222 snd_printdd("Invalid chip_addx Params\n");
2223 return -EINVAL;
95c6e9cb
IM		 2224 }
2225
01ef7dbf
IM		 2226 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2227 sizeof(u32);
2228
2229 buffer_addx = dma_get_buffer_addr(dma_engine);
2230
2231 if (buffer_addx == NULL) {
2232 snd_printdd(KERN_ERR "dma_engine buffer NULL\n");
2233 return -EINVAL;
2234 }
2235
2236 dma_get_converter_format(dma_engine, &hda_format);
2237 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2238 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2239 num_chans = get_hdafmt_chs(hda_format) + 1;
2240
2241 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2242 (num_chans * sample_rate_mul / sample_rate_div));
2243
2244 buffer_size_words = min(buffer_size_words,
2245 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2246 65536 : 32768));
2247 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2248 snd_printdd(
2249 "chpadr=0x%08x frmsz=%u nchan=%u "
2250 "rate_mul=%u div=%u bufsz=%u\n",
2251 chip_addx, hda_frame_size_words, num_chans,
2252 sample_rate_mul, sample_rate_div, buffer_size_words);
2253
2254 if ((buffer_addx == NULL) || (hda_frame_size_words == 0) ||
2255 (buffer_size_words < hda_frame_size_words)) {
2256 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n");
2257 return -EINVAL;
2258 }
2259
2260 remainder_words = words_to_write % hda_frame_size_words;
2261 data_remainder = data;
2262 chip_addx_remainder = chip_addx;
2263
2264 data += remainder_words;
2265 chip_addx += remainder_words*sizeof(u32);
2266 words_to_write -= remainder_words;
2267
2268 while (words_to_write != 0) {
2269 run_size_words = min(buffer_size_words, words_to_write);
2270 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2271 words_to_write, run_size_words, remainder_words);
2272 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2273 if (!comm_dma_setup_done) {
2274 status = dsp_dma_stop(codec, dma_chan, ovly);
2275 if (status < 0)
2276 return -EIO;
2277 status = dsp_dma_setup_common(codec, chip_addx,
2278 dma_chan, port_map_mask, ovly);
2279 if (status < 0)
2280 return status;
2281 comm_dma_setup_done = true;
2282 }
2283
2284 status = dsp_dma_setup(codec, chip_addx,
2285 run_size_words, dma_chan);
2286 if (status < 0)
2287 return status;
2288 status = dsp_dma_start(codec, dma_chan, ovly);
2289 if (status < 0)
2290 return status;
2291 if (!dsp_is_dma_active(codec, dma_chan)) {
2292 snd_printdd(KERN_ERR "dspxfr:DMA did not start");
2293 return -EIO;
2294 }
2295 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2296 if (status < 0)
2297 return status;
2298 if (remainder_words != 0) {
2299 status = chipio_write_multiple(codec,
2300 chip_addx_remainder,
2301 data_remainder,
2302 remainder_words);
2303 remainder_words = 0;
2304 }
2305 if (hci_write) {
2306 status = dspxfr_hci_write(codec, hci_write);
2307 hci_write = NULL;
2308 }
2309 retry = 5000;
2310 while (dsp_is_dma_active(codec, dma_chan)) {
2311 if (--retry <= 0)
2312 break;
2313 }
2314 snd_printdd(KERN_INFO "+++++ DMA complete");
2315 dma_set_state(dma_engine, DMA_STATE_STOP);
2316 dma_reset(dma_engine);
2317
2318 if (status < 0)
2319 return status;
2320
2321 data += run_size_words;
2322 chip_addx += run_size_words*sizeof(u32);
2323 words_to_write -= run_size_words;
2324 }
2325
2326 if (remainder_words != 0) {
2327 status = chipio_write_multiple(codec, chip_addx_remainder,
2328 data_remainder, remainder_words);
2329 }
2330
2331 return status;
95c6e9cb
IM		 2332}
2333
d5c21b88
IM		 2334/**
2335 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2336 *
2337 * @codec: the HDA codec
2338 * @fls_data: pointer to a fast load image
2339 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2340 * no relocation
e97249dd
IM		 2341 * @sample_rate: sampling rate of the stream used for DSP download
2342 * @number_channels: channels of the stream used for DSP download
d5c21b88
IM		 2343 * @ovly: TRUE if overlay format is required
2344 *
2345 * Returns zero or a negative error code.
2346 */
01ef7dbf
IM		 2347static int dspxfr_image(struct hda_codec *codec,
2348 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2349 unsigned int reloc,
2350 unsigned int sample_rate,
2351 unsigned short channels,
01ef7dbf 2352 bool ovly)
95c6e9cb
IM		 2353{
2354 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2355 int status;
2356 unsigned short hda_format = 0;
2357 unsigned int response;
2358 unsigned char stream_id = 0;
2359 struct dma_engine *dma_engine;
2360 unsigned int dma_chan;
2361 unsigned int port_map_mask;
2362
2363 if (fls_data == NULL)
2364 return -EINVAL;
2365
2366 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
063bca09
TI		 2367 if (!dma_engine)
2368 return -ENOMEM;
95c6e9cb 2369
01ef7dbf
IM		 2370 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2371 if (!dma_engine->dmab) {
2372 status = -ENOMEM;
2373 goto exit;
2374 }
95c6e9cb 2375
01ef7dbf 2376 dma_engine->codec = codec;
e97249dd 2377 dma_convert_to_hda_format(sample_rate, channels, &hda_format);
01ef7dbf
IM		 2378 dma_engine->m_converter_format = hda_format;
2379 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2380 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2381
2382 dma_chan = 0;
2383
2384 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2385 hda_format, &response);
2386
2387 if (status < 0) {
2388 snd_printdd(KERN_ERR "set converter format fail");
2389 goto exit;
2390 }
2391
2392 status = snd_hda_codec_load_dsp_prepare(codec,
2393 dma_engine->m_converter_format,
2394 dma_engine->buf_size,
2395 dma_engine->dmab);
2396 if (status < 0)
95c6e9cb 2397 goto exit;
01ef7dbf
IM		 2398 spec->dsp_stream_id = status;
2399
2400 if (ovly) {
2401 status = dspio_alloc_dma_chan(codec, &dma_chan);
2402 if (status < 0) {
2403 snd_printdd(KERN_ERR "alloc dmachan fail");
2404 dma_chan = (unsigned int)INVALID_DMA_CHANNEL;
2405 goto exit;
2406 }
2407 }
95c6e9cb 2408
01ef7dbf
IM		 2409 port_map_mask = 0;
2410 status = dsp_allocate_ports_format(codec, hda_format,
2411 &port_map_mask);
2412 if (status < 0) {
2413 snd_printdd(KERN_ERR "alloc ports fail");
2414 goto exit;
2415 }
2416
2417 stream_id = dma_get_stream_id(dma_engine);
2418 status = codec_set_converter_stream_channel(codec,
2419 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2420 if (status < 0) {
2421 snd_printdd(KERN_ERR "set stream chan fail");
2422 goto exit;
2423 }
2424
2425 while ((fls_data != NULL) && !is_last(fls_data)) {
2426 if (!is_valid(fls_data)) {
2427 snd_printdd(KERN_ERR "FLS check fail");
2428 status = -EINVAL;
2429 goto exit;
2430 }
2431 status = dspxfr_one_seg(codec, fls_data, reloc,
2432 dma_engine, dma_chan,
2433 port_map_mask, ovly);
2434 if (status < 0)
2435 break;
2436
2437 if (is_hci_prog_list_seg(fls_data))
2438 fls_data = get_next_seg_ptr(fls_data);
2439
2440 if ((fls_data != NULL) && !is_last(fls_data))
2441 fls_data = get_next_seg_ptr(fls_data);
2442 }
2443
2444 if (port_map_mask != 0)
2445 status = dsp_free_ports(codec);
2446
2447 if (status < 0)
95c6e9cb
IM		 2448 goto exit;
2449
01ef7dbf
IM		 2450 status = codec_set_converter_stream_channel(codec,
2451 WIDGET_CHIP_CTRL, 0, 0, &response);
2452
95c6e9cb 2453exit:
01ef7dbf
IM		 2454 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2455 dspio_free_dma_chan(codec, dma_chan);
2456
2457 if (dma_engine->dmab)
2458 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2459 kfree(dma_engine->dmab);
2460 kfree(dma_engine);
2461
2462 return status;
95c6e9cb
IM		 2463}
2464
2465/*
01ef7dbf 2466 * CA0132 DSP download stuffs.
95c6e9cb 2467 */
01ef7dbf 2468static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2469{
01ef7dbf 2470 snd_printdd(KERN_INFO "---- dspload_post_setup ------");
95c6e9cb 2471
01ef7dbf
IM		 2472 /*set DSP speaker to 2.0 configuration*/
2473 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2474 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2475
01ef7dbf
IM		 2476 /*update write pointer*/
2477 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2478}
95c6e9cb 2479
d5c21b88
IM		 2480/**
2481 * Download DSP from a DSP Image Fast Load structure. This structure is a
2482 * linear, non-constant sized element array of structures, each of which
2483 * contain the count of the data to be loaded, the data itself, and the
2484 * corresponding starting chip address of the starting data location.
2485 *
2486 * @codec: the HDA codec
2487 * @fls: pointer to a fast load image
2488 * @ovly: TRUE if overlay format is required
2489 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2490 * no relocation
2491 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2492 * @router_chans: number of audio router channels to be allocated (0 means use
2493 * internal defaults; max is 32)
2494 *
2495 * Returns zero or a negative error code.
2496 */
01ef7dbf
IM		 2497static int dspload_image(struct hda_codec *codec,
2498 const struct dsp_image_seg *fls,
2499 bool ovly,
2500 unsigned int reloc,
2501 bool autostart,
2502 int router_chans)
2503{
2504 int status = 0;
e97249dd
IM		 2505 unsigned int sample_rate;
2506 unsigned short channels;
01ef7dbf
IM		 2507
2508 snd_printdd(KERN_INFO "---- dspload_image begin ------");
2509 if (router_chans == 0) {
2510 if (!ovly)
2511 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2512 else
2513 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2514 }
95c6e9cb 2515
e97249dd
IM		 2516 sample_rate = 48000;
2517 channels = (unsigned short)router_chans;
01ef7dbf 2518
e97249dd
IM		 2519 while (channels > 16) {
2520 sample_rate *= 2;
2521 channels /= 2;
01ef7dbf
IM		 2522 }
2523
01ef7dbf
IM		 2524 do {
2525 snd_printdd(KERN_INFO "Ready to program DMA");
2526 if (!ovly)
2527 status = dsp_reset(codec);
2528
2529 if (status < 0)
2530 break;
2531
2532 snd_printdd(KERN_INFO "dsp_reset() complete");
e97249dd
IM		 2533 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2534 ovly);
01ef7dbf
IM		 2535
2536 if (status < 0)
2537 break;
2538
2539 snd_printdd(KERN_INFO "dspxfr_image() complete");
2540 if (autostart && !ovly) {
2541 dspload_post_setup(codec);
2542 status = dsp_set_run_state(codec);
2543 }
2544
2545 snd_printdd(KERN_INFO "LOAD FINISHED");
2546 } while (0);
2547
2548 return status;
2549}
2550
c3b4eea2
IM		 2551static const struct firmware *fw_efx;
2552
2553static int request_firmware_cached(const struct firmware **firmware_p,
2554 const char *name, struct device *device)
2555{
2556 if (*firmware_p)
2557 return 0; /* already loaded */
2558 return request_firmware(firmware_p, name, device);
2559}
2560
2561static void release_cached_firmware(void)
2562{
2563 if (fw_efx) {
2564 release_firmware(fw_efx);
2565 fw_efx = NULL;
2566 }
2567}
2568
01ef7dbf
IM		 2569static bool dspload_is_loaded(struct hda_codec *codec)
2570{
2571 unsigned int data = 0;
2572 int status = 0;
2573
2574 status = chipio_read(codec, 0x40004, &data);
2575 if ((status < 0) || (data != 1))
2576 return false;
2577
2578 return true;
2579}
2580
2581static bool dspload_wait_loaded(struct hda_codec *codec)
2582{
2583 int retry = 100;
2584
2585 do {
2586 msleep(20);
2587 if (dspload_is_loaded(codec)) {
2588 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2589 return true;
2590 }
2591 } while (--retry);
2592
2593 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2594 return false;
95c6e9cb
IM		 2595}
2596
5aaca44d
IM		 2597/*
2598 * Controls stuffs.
2599 */
ef6b2ead
IM		 2600
2601/*
2602 * Mixer controls helpers.
2603 */
2604#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2605 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2606 .name = xname, \
2607 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2608 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2609 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2610 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2611 .info = ca0132_volume_info, \
2612 .get = ca0132_volume_get, \
2613 .put = ca0132_volume_put, \
2614 .tlv = { .c = ca0132_volume_tlv }, \
2615 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2616
2617#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2618 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2619 .name = xname, \
2620 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2621 .info = snd_hda_mixer_amp_switch_info, \
2622 .get = ca0132_switch_get, \
2623 .put = ca0132_switch_put, \
2624 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2625
2626/* stereo */
2627#define CA0132_CODEC_VOL(xname, nid, dir) \
2628 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2629#define CA0132_CODEC_MUTE(xname, nid, dir) \
2630 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2631
95c6e9cb 2632/*
27ebeb0b 2633 * PCM callbacks
95c6e9cb 2634 */
27ebeb0b
TI		 2635static int ca0132_playback_pcm_open(struct hda_pcm_stream *hinfo,
2636 struct hda_codec *codec,
2637 struct snd_pcm_substream *substream)
95c6e9cb 2638{
27ebeb0b
TI		 2639 struct ca0132_spec *spec = codec->spec;
2640 return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream,
2641 hinfo);
95c6e9cb
IM		 2642}
2643
95c6e9cb
IM		 2644static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2645 struct hda_codec *codec,
2646 unsigned int stream_tag,
2647 unsigned int format,
2648 struct snd_pcm_substream *substream)
2649{
2650 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2651 return snd_hda_multi_out_analog_prepare(codec, &spec->multiout,
2652 stream_tag, format, substream);
95c6e9cb
IM		 2653}
2654
2655static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2656 struct hda_codec *codec,
2657 struct snd_pcm_substream *substream)
2658{
2659 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2660 return snd_hda_multi_out_analog_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2661}
2662
2663/*
2664 * Digital out
2665 */
27ebeb0b
TI		 2666static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2667 struct hda_codec *codec,
2668 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2669{
2670 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2671 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2672}
2673
27ebeb0b 2674static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2675 struct hda_codec *codec,
2676 unsigned int stream_tag,
2677 unsigned int format,
2678 struct snd_pcm_substream *substream)
2679{
2680 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2681 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2682 stream_tag, format, substream);
95c6e9cb
IM		 2683}
2684
27ebeb0b 2685static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2686 struct hda_codec *codec,
95c6e9cb
IM		 2687 struct snd_pcm_substream *substream)
2688{
2689 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2690 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2691}
2692
27ebeb0b
TI		 2693static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2694 struct hda_codec *codec,
2695 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2696{
2697 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2698 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2699}
2700
5aaca44d
IM		 2701/*
2702 * Select the active output.
2703 * If autodetect is enabled, output will be selected based on jack detection.
2704 * If jack inserted, headphone will be selected, else built-in speakers
2705 * If autodetect is disabled, output will be selected based on selection.
2706 */
2707static int ca0132_select_out(struct hda_codec *codec)
2708{
2709 struct ca0132_spec *spec = codec->spec;
2710 unsigned int pin_ctl;
2711 int jack_present;
2712 int auto_jack;
2713 unsigned int tmp;
2714 int err;
2715
2716 snd_printdd(KERN_INFO "ca0132_select_out\n");
2717
2718 snd_hda_power_up(codec);
2719
2720 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
2721
2722 if (auto_jack)
2723 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
2724 else
2725 jack_present =
2726 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
2727
2728 if (jack_present)
2729 spec->cur_out_type = HEADPHONE_OUT;
2730 else
2731 spec->cur_out_type = SPEAKER_OUT;
2732
2733 if (spec->cur_out_type == SPEAKER_OUT) {
2734 snd_printdd(KERN_INFO "ca0132_select_out speaker\n");
2735 /*speaker out config*/
2736 tmp = FLOAT_ONE;
2737 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
2738 if (err < 0)
2739 goto exit;
2740 /*enable speaker EQ*/
2741 tmp = FLOAT_ONE;
2742 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
2743 if (err < 0)
2744 goto exit;
2745
2746 /* Setup EAPD */
2747 snd_hda_codec_write(codec, spec->out_pins[1], 0,
2748 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
2749 snd_hda_codec_write(codec, spec->out_pins[0], 0,
2750 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
2751 snd_hda_codec_write(codec, spec->out_pins[0], 0,
2752 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
2753 snd_hda_codec_write(codec, spec->out_pins[0], 0,
2754 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
2755
2756 /* disable headphone node */
2757 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
2758 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2759 snd_hda_codec_write(codec, spec->out_pins[1], 0,
2760 AC_VERB_SET_PIN_WIDGET_CONTROL,
2761 pin_ctl & 0xBF);
2762 /* enable speaker node */
2763 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
2764 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2765 snd_hda_codec_write(codec, spec->out_pins[0], 0,
2766 AC_VERB_SET_PIN_WIDGET_CONTROL,
2767 pin_ctl | 0x40);
2768 } else {
2769 snd_printdd(KERN_INFO "ca0132_select_out hp\n");
2770 /*headphone out config*/
2771 tmp = FLOAT_ZERO;
2772 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
2773 if (err < 0)
2774 goto exit;
2775 /*disable speaker EQ*/
2776 tmp = FLOAT_ZERO;
2777 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
2778 if (err < 0)
2779 goto exit;
2780
2781 /* Setup EAPD */
2782 snd_hda_codec_write(codec, spec->out_pins[0], 0,
2783 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
2784 snd_hda_codec_write(codec, spec->out_pins[0], 0,
2785 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
2786 snd_hda_codec_write(codec, spec->out_pins[1], 0,
2787 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
2788 snd_hda_codec_write(codec, spec->out_pins[0], 0,
2789 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
2790
2791 /* disable speaker*/
2792 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
2793 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2794 snd_hda_codec_write(codec, spec->out_pins[0], 0,
2795 AC_VERB_SET_PIN_WIDGET_CONTROL,
2796 pin_ctl & 0xBF);
2797 /* enable headphone*/
2798 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
2799 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2800 snd_hda_codec_write(codec, spec->out_pins[1], 0,
2801 AC_VERB_SET_PIN_WIDGET_CONTROL,
2802 pin_ctl | 0x40);
2803 }
2804
2805exit:
2806 snd_hda_power_down(codec);
2807
2808 return err < 0 ? err : 0;
2809}
2810
2811static void ca0132_set_dmic(struct hda_codec *codec, int enable);
2812static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
2813static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
2814
2815/*
2816 * Select the active VIP source
2817 */
2818static int ca0132_set_vipsource(struct hda_codec *codec, int val)
2819{
2820 struct ca0132_spec *spec = codec->spec;
2821 unsigned int tmp;
2822
2823 if (!dspload_is_loaded(codec))
2824 return 0;
2825
2826 /* if CrystalVoice if off, vipsource should be 0 */
2827 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
2828 (val == 0)) {
2829 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
2830 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
2831 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
2832 if (spec->cur_mic_type == DIGITAL_MIC)
2833 tmp = FLOAT_TWO;
2834 else
2835 tmp = FLOAT_ONE;
2836 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
2837 tmp = FLOAT_ZERO;
2838 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
2839 } else {
2840 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
2841 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
2842 if (spec->cur_mic_type == DIGITAL_MIC)
2843 tmp = FLOAT_TWO;
2844 else
2845 tmp = FLOAT_ONE;
2846 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
2847 tmp = FLOAT_ONE;
2848 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
2849 msleep(20);
2850 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
2851 }
2852
2853 return 1;
2854}
2855
2856/*
2857 * Select the active microphone.
2858 * If autodetect is enabled, mic will be selected based on jack detection.
2859 * If jack inserted, ext.mic will be selected, else built-in mic
2860 * If autodetect is disabled, mic will be selected based on selection.
2861 */
2862static int ca0132_select_mic(struct hda_codec *codec)
2863{
2864 struct ca0132_spec *spec = codec->spec;
2865 int jack_present;
2866 int auto_jack;
2867
2868 snd_printdd(KERN_INFO "ca0132_select_mic\n");
2869
2870 snd_hda_power_up(codec);
2871
2872 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
2873
2874 if (auto_jack)
2875 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
2876 else
2877 jack_present =
2878 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
2879
2880 if (jack_present)
2881 spec->cur_mic_type = LINE_MIC_IN;
2882 else
2883 spec->cur_mic_type = DIGITAL_MIC;
2884
2885 if (spec->cur_mic_type == DIGITAL_MIC) {
2886 /* enable digital Mic */
2887 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
2888 ca0132_set_dmic(codec, 1);
2889 ca0132_mic_boost_set(codec, 0);
2890 /* set voice focus */
2891 ca0132_effects_set(codec, VOICE_FOCUS,
2892 spec->effects_switch
2893 [VOICE_FOCUS - EFFECT_START_NID]);
2894 } else {
2895 /* disable digital Mic */
2896 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
2897 ca0132_set_dmic(codec, 0);
2898 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
2899 /* disable voice focus */
2900 ca0132_effects_set(codec, VOICE_FOCUS, 0);
2901 }
2902
2903 snd_hda_power_down(codec);
2904
2905 return 0;
2906}
2907
a7e76271
IM		 2908/*
2909 * Check if VNODE settings take effect immediately.
2910 */
2911static bool ca0132_is_vnode_effective(struct hda_codec *codec,
2912 hda_nid_t vnid,
2913 hda_nid_t *shared_nid)
2914{
2915 struct ca0132_spec *spec = codec->spec;
2916 hda_nid_t nid;
2917 bool effective = false;
2918
2919 switch (vnid) {
2920 case VNID_SPK:
2921 nid = spec->shared_out_nid;
2922 effective = true;
2923 break;
2924 case VNID_MIC:
2925 nid = spec->shared_mic_nid;
2926 effective = true;
2927 break;
2928 default:
2929 break;
2930 }
2931
2932 if (effective && shared_nid)
2933 *shared_nid = nid;
2934
2935 return effective;
2936}
2937
2938/*
2939* The following functions are control change helpers.
2940* They return 0 if no changed. Return 1 if changed.
2941*/
2942static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
2943{
2944 struct ca0132_spec *spec = codec->spec;
2945 unsigned int tmp;
2946
2947 /* based on CrystalVoice state to enable VoiceFX. */
2948 if (enable) {
2949 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
2950 FLOAT_ONE : FLOAT_ZERO;
2951 } else {
2952 tmp = FLOAT_ZERO;
2953 }
2954
2955 dspio_set_uint_param(codec, ca0132_voicefx.mid,
2956 ca0132_voicefx.reqs[0], tmp);
2957
2958 return 1;
2959}
2960
5aaca44d
IM		 2961/*
2962 * Set the effects parameters
2963 */
2964static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
2965{
2966 struct ca0132_spec *spec = codec->spec;
2967 unsigned int on;
2968 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
2969 int err = 0;
2970 int idx = nid - EFFECT_START_NID;
2971
2972 if ((idx < 0) || (idx >= num_fx))
2973 return 0; /* no changed */
2974
2975 /* for out effect, qualify with PE */
2976 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
2977 /* if PE if off, turn off out effects. */
2978 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2979 val = 0;
2980 }
2981
2982 /* for in effect, qualify with CrystalVoice */
2983 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
2984 /* if CrystalVoice if off, turn off in effects. */
2985 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2986 val = 0;
2987
2988 /* Voice Focus applies to 2-ch Mic, Digital Mic */
2989 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
2990 val = 0;
2991 }
2992
2993 snd_printdd(KERN_INFO, "ca0132_effect_set: nid=0x%x, val=%ld\n",
2994 nid, val);
2995
2996 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
2997 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
2998 ca0132_effects[idx].reqs[0], on);
2999
3000 if (err < 0)
3001 return 0; /* no changed */
3002
3003 return 1;
3004}
3005
a7e76271
IM		 3006/*
3007 * Turn on/off Playback Enhancements
3008 */
3009static int ca0132_pe_switch_set(struct hda_codec *codec)
3010{
3011 struct ca0132_spec *spec = codec->spec;
3012 hda_nid_t nid;
3013 int i, ret = 0;
3014
3015 snd_printdd(KERN_INFO "ca0132_pe_switch_set: val=%ld\n",
3016 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3017
3018 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3019 nid = OUT_EFFECT_START_NID;
3020 /* PE affects all out effects */
3021 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3022 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3023
3024 return ret;
3025}
3026
5aaca44d
IM		 3027/* Check if Mic1 is streaming, if so, stop streaming */
3028static int stop_mic1(struct hda_codec *codec)
3029{
3030 struct ca0132_spec *spec = codec->spec;
3031 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3032 AC_VERB_GET_CONV, 0);
3033 if (oldval != 0)
3034 snd_hda_codec_write(codec, spec->adcs[0], 0,
3035 AC_VERB_SET_CHANNEL_STREAMID,
3036 0);
3037 return oldval;
3038}
3039
3040/* Resume Mic1 streaming if it was stopped. */
3041static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3042{
3043 struct ca0132_spec *spec = codec->spec;
3044 /* Restore the previous stream and channel */
3045 if (oldval != 0)
3046 snd_hda_codec_write(codec, spec->adcs[0], 0,
3047 AC_VERB_SET_CHANNEL_STREAMID,
3048 oldval);
3049}
3050
3051/*
a7e76271 3052 * Turn on/off CrystalVoice
5aaca44d 3053 */
a7e76271
IM		 3054static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3055{
3056 struct ca0132_spec *spec = codec->spec;
3057 hda_nid_t nid;
3058 int i, ret = 0;
3059 unsigned int oldval;
3060
3061 snd_printdd(KERN_INFO "ca0132_cvoice_switch_set: val=%ld\n",
3062 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3063
3064 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3065 nid = IN_EFFECT_START_NID;
3066 /* CrystalVoice affects all in effects */
3067 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3068 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3069
3070 /* including VoiceFX */
3071 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3072
3073 /* set correct vipsource */
3074 oldval = stop_mic1(codec);
3075 ret |= ca0132_set_vipsource(codec, 1);
3076 resume_mic1(codec, oldval);
3077 return ret;
3078}
3079
5aaca44d
IM		 3080static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3081{
3082 struct ca0132_spec *spec = codec->spec;
3083 int ret = 0;
3084
3085 if (val) /* on */
3086 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3087 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3088 else /* off */
3089 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3090 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3091
3092 return ret;
3093}
3094
a7e76271
IM		 3095static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3096 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3097{
a7e76271
IM		 3098 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3099 hda_nid_t nid = get_amp_nid(kcontrol);
3100 hda_nid_t shared_nid = 0;
3101 bool effective;
3102 int ret = 0;
95c6e9cb 3103 struct ca0132_spec *spec = codec->spec;
a7e76271 3104 int auto_jack;
95c6e9cb 3105
a7e76271
IM		 3106 if (nid == VNID_HP_SEL) {
3107 auto_jack =
3108 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3109 if (!auto_jack)
3110 ca0132_select_out(codec);
3111 return 1;
3112 }
95c6e9cb 3113
a7e76271
IM		 3114 if (nid == VNID_AMIC1_SEL) {
3115 auto_jack =
3116 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3117 if (!auto_jack)
3118 ca0132_select_mic(codec);
3119 return 1;
3120 }
95c6e9cb 3121
a7e76271
IM		 3122 if (nid == VNID_HP_ASEL) {
3123 ca0132_select_out(codec);
3124 return 1;
3125 }
95c6e9cb 3126
a7e76271
IM		 3127 if (nid == VNID_AMIC1_ASEL) {
3128 ca0132_select_mic(codec);
3129 return 1;
95c6e9cb 3130 }
a7e76271
IM		 3131
3132 /* if effective conditions, then update hw immediately. */
3133 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3134 if (effective) {
3135 int dir = get_amp_direction(kcontrol);
3136 int ch = get_amp_channels(kcontrol);
3137 unsigned long pval;
3138
3139 mutex_lock(&codec->control_mutex);
3140 pval = kcontrol->private_value;
3141 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3142 0, dir);
3143 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3144 kcontrol->private_value = pval;
3145 mutex_unlock(&codec->control_mutex);
95c6e9cb 3146 }
95c6e9cb 3147
a7e76271 3148 return ret;
95c6e9cb 3149}
a7e76271 3150/* End of control change helpers. */
95c6e9cb 3151
a7e76271
IM		 3152static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3153 struct snd_ctl_elem_info *uinfo)
3154{
3155 unsigned int items = sizeof(ca0132_voicefx_presets)
3156 / sizeof(struct ct_voicefx_preset);
3157
3158 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3159 uinfo->count = 1;
3160 uinfo->value.enumerated.items = items;
3161 if (uinfo->value.enumerated.item >= items)
3162 uinfo->value.enumerated.item = items - 1;
3163 strcpy(uinfo->value.enumerated.name,
3164 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3165 return 0;
3166}
95c6e9cb 3167
a7e76271 3168static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3169 struct snd_ctl_elem_value *ucontrol)
3170{
3171 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3172 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3173
a7e76271 3174 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3175 return 0;
3176}
3177
a7e76271 3178static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3179 struct snd_ctl_elem_value *ucontrol)
3180{
3181 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3182 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3183 int i, err = 0;
3184 int sel = ucontrol->value.enumerated.item[0];
3185 unsigned int items = sizeof(ca0132_voicefx_presets)
3186 / sizeof(struct ct_voicefx_preset);
95c6e9cb 3187
a7e76271 3188 if (sel >= items)
95c6e9cb
IM		 3189 return 0;
3190
a7e76271
IM		 3191 snd_printdd(KERN_INFO "ca0132_voicefx_put: sel=%d, preset=%s\n",
3192 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3193
a7e76271
IM		 3194 /*
3195 * Idx 0 is default.
3196 * Default needs to qualify with CrystalVoice state.
3197 */
3198 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3199 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3200 ca0132_voicefx.reqs[i],
3201 ca0132_voicefx_presets[sel].vals[i]);
3202 if (err < 0)
3203 break;
3204 }
95c6e9cb 3205
a7e76271
IM		 3206 if (err >= 0) {
3207 spec->voicefx_val = sel;
3208 /* enable voice fx */
3209 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3210 }
95c6e9cb 3211
a7e76271 3212 return 1;
95c6e9cb
IM		 3213}
3214
a7e76271
IM		 3215static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3216 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3217{
3218 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3219 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3220 hda_nid_t nid = get_amp_nid(kcontrol);
3221 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3222 long *valp = ucontrol->value.integer.value;
3223
a7e76271
IM		 3224 /* vnode */
3225 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3226 if (ch & 1) {
3227 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3228 valp++;
3229 }
3230 if (ch & 2) {
3231 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3232 valp++;
3233 }
3234 return 0;
3235 }
3236
3237 /* effects, include PE and CrystalVoice */
3238 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3239 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3240 return 0;
3241 }
3242
3243 /* mic boost */
3244 if (nid == spec->input_pins[0]) {
3245 *valp = spec->cur_mic_boost;
3246 return 0;
3247 }
3248
95c6e9cb
IM		 3249 return 0;
3250}
3251
a7e76271
IM		 3252static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3253 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3254{
3255 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3256 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3257 hda_nid_t nid = get_amp_nid(kcontrol);
3258 int ch = get_amp_channels(kcontrol);
95c6e9cb 3259 long *valp = ucontrol->value.integer.value;
a7e76271 3260 int changed = 1;
95c6e9cb 3261
a7e76271
IM		 3262 snd_printdd(KERN_INFO "ca0132_switch_put: nid=0x%x, val=%ld\n",
3263 nid, *valp);
95c6e9cb
IM		 3264
3265 snd_hda_power_up(codec);
a7e76271
IM		 3266 /* vnode */
3267 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3268 if (ch & 1) {
3269 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3270 valp++;
3271 }
3272 if (ch & 2) {
3273 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3274 valp++;
3275 }
3276 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3277 goto exit;
3278 }
95c6e9cb 3279
a7e76271
IM		 3280 /* PE */
3281 if (nid == PLAY_ENHANCEMENT) {
3282 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3283 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3284 goto exit;
a7e76271 3285 }
95c6e9cb 3286
a7e76271
IM		 3287 /* CrystalVoice */
3288 if (nid == CRYSTAL_VOICE) {
3289 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3290 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3291 goto exit;
a7e76271 3292 }
95c6e9cb 3293
a7e76271
IM		 3294 /* out and in effects */
3295 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3296 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3297 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3298 changed = ca0132_effects_set(codec, nid, *valp);
3299 goto exit;
3300 }
3301
3302 /* mic boost */
3303 if (nid == spec->input_pins[0]) {
3304 spec->cur_mic_boost = *valp;
3305
3306 /* Mic boost does not apply to Digital Mic */
3307 if (spec->cur_mic_type != DIGITAL_MIC)
3308 changed = ca0132_mic_boost_set(codec, *valp);
3309 goto exit;
3310 }
95c6e9cb 3311
a7e76271 3312exit:
95c6e9cb 3313 snd_hda_power_down(codec);
a7e76271 3314 return changed;
95c6e9cb
IM		 3315}
3316
a7e76271
IM		 3317/*
3318 * Volume related
3319 */
3320static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3321 struct snd_ctl_elem_info *uinfo)
3322{
3323 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3324 struct ca0132_spec *spec = codec->spec;
3325 hda_nid_t nid = get_amp_nid(kcontrol);
3326 int ch = get_amp_channels(kcontrol);
3327 int dir = get_amp_direction(kcontrol);
3328 unsigned long pval;
3329 int err;
3330
3331 switch (nid) {
3332 case VNID_SPK:
3333 /* follow shared_out info */
3334 nid = spec->shared_out_nid;
3335 mutex_lock(&codec->control_mutex);
3336 pval = kcontrol->private_value;
3337 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3338 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3339 kcontrol->private_value = pval;
3340 mutex_unlock(&codec->control_mutex);
3341 break;
3342 case VNID_MIC:
3343 /* follow shared_mic info */
3344 nid = spec->shared_mic_nid;
3345 mutex_lock(&codec->control_mutex);
3346 pval = kcontrol->private_value;
3347 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3348 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3349 kcontrol->private_value = pval;
3350 mutex_unlock(&codec->control_mutex);
3351 break;
3352 default:
3353 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3354 }
3355 return err;
3356}
3357
3358static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3359 struct snd_ctl_elem_value *ucontrol)
3360{
3361 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3362 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3363 hda_nid_t nid = get_amp_nid(kcontrol);
3364 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3365 long *valp = ucontrol->value.integer.value;
3366
a7e76271
IM		 3367 /* store the left and right volume */
3368 if (ch & 1) {
3369 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3370 valp++;
3371 }
3372 if (ch & 2) {
3373 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3374 valp++;
3375 }
95c6e9cb
IM		 3376 return 0;
3377}
3378
a7e76271 3379static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3380 struct snd_ctl_elem_value *ucontrol)
3381{
3382 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3383 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3384 hda_nid_t nid = get_amp_nid(kcontrol);
3385 int ch = get_amp_channels(kcontrol);
95c6e9cb 3386 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3387 hda_nid_t shared_nid = 0;
3388 bool effective;
3389 int changed = 1;
3390
3391 /* store the left and right volume */
3392 if (ch & 1) {
3393 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3394 valp++;
3395 }
3396 if (ch & 2) {
3397 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3398 valp++;
3399 }
95c6e9cb 3400
a7e76271
IM		 3401 /* if effective conditions, then update hw immediately. */
3402 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3403 if (effective) {
3404 int dir = get_amp_direction(kcontrol);
3405 unsigned long pval;
3406
3407 snd_hda_power_up(codec);
3408 mutex_lock(&codec->control_mutex);
3409 pval = kcontrol->private_value;
3410 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3411 0, dir);
3412 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3413 kcontrol->private_value = pval;
3414 mutex_unlock(&codec->control_mutex);
3415 snd_hda_power_down(codec);
3416 }
95c6e9cb 3417
a7e76271 3418 return changed;
95c6e9cb
IM		 3419}
3420
a7e76271
IM		 3421static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3422 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3423{
a7e76271
IM		 3424 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3425 struct ca0132_spec *spec = codec->spec;
3426 hda_nid_t nid = get_amp_nid(kcontrol);
3427 int ch = get_amp_channels(kcontrol);
3428 int dir = get_amp_direction(kcontrol);
3429 unsigned long pval;
3430 int err;
3431
3432 switch (nid) {
3433 case VNID_SPK:
3434 /* follow shared_out tlv */
3435 nid = spec->shared_out_nid;
3436 mutex_lock(&codec->control_mutex);
3437 pval = kcontrol->private_value;
3438 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3439 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3440 kcontrol->private_value = pval;
3441 mutex_unlock(&codec->control_mutex);
3442 break;
3443 case VNID_MIC:
3444 /* follow shared_mic tlv */
3445 nid = spec->shared_mic_nid;
3446 mutex_lock(&codec->control_mutex);
3447 pval = kcontrol->private_value;
3448 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3449 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3450 kcontrol->private_value = pval;
3451 mutex_unlock(&codec->control_mutex);
3452 break;
3453 default:
3454 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3455 }
3456 return err;
95c6e9cb
IM		 3457}
3458
a7e76271
IM		 3459static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3460 const char *pfx, int dir)
95c6e9cb 3461{
a7e76271
IM		 3462 char namestr[44];
3463 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3464 struct snd_kcontrol_new knew =
a7e76271
IM		 3465 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3466 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3467 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3468}
3469
a7e76271 3470static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3471{
3472 struct snd_kcontrol_new knew =
a7e76271
IM		 3473 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3474 VOICEFX, 1, 0, HDA_INPUT);
3475 knew.info = ca0132_voicefx_info;
3476 knew.get = ca0132_voicefx_get;
3477 knew.put = ca0132_voicefx_put;
3478 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3479}
3480
a7e76271
IM		 3481/*
3482 * When changing Node IDs for Mixer Controls below, make sure to update
3483 * Node IDs in ca0132_config() as well.
3484 */
3485static struct snd_kcontrol_new ca0132_mixer[] = {
3486 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3487 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3488 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3489 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3490 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3491 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3492 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3493 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3494 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3495 0x12, 1, HDA_INPUT),
3496 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3497 VNID_HP_SEL, 1, HDA_OUTPUT),
3498 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3499 VNID_AMIC1_SEL, 1, HDA_INPUT),
3500 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3501 VNID_HP_ASEL, 1, HDA_OUTPUT),
3502 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3503 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3504 { } /* end */
3505};
3506
3507/*
3508 */
3509static struct hda_pcm_stream ca0132_pcm_analog_playback = {
3510 .substreams = 1,
3511 .channels_min = 2,
3512 .channels_max = 2,
3513 .ops = {
3514 .open = ca0132_playback_pcm_open,
3515 .prepare = ca0132_playback_pcm_prepare,
3516 .cleanup = ca0132_playback_pcm_cleanup
3517 },
3518};
3519
3520static struct hda_pcm_stream ca0132_pcm_analog_capture = {
3521 .substreams = 1,
3522 .channels_min = 2,
3523 .channels_max = 2,
3524};
3525
3526static struct hda_pcm_stream ca0132_pcm_digital_playback = {
3527 .substreams = 1,
3528 .channels_min = 2,
3529 .channels_max = 2,
3530 .ops = {
3531 .open = ca0132_dig_playback_pcm_open,
3532 .close = ca0132_dig_playback_pcm_close,
3533 .prepare = ca0132_dig_playback_pcm_prepare,
3534 .cleanup = ca0132_dig_playback_pcm_cleanup
3535 },
3536};
3537
3538static struct hda_pcm_stream ca0132_pcm_digital_capture = {
3539 .substreams = 1,
3540 .channels_min = 2,
3541 .channels_max = 2,
3542};
3543
3544static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 3545{
3546 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3547 struct hda_pcm *info = spec->pcm_rec;
3548
3549 codec->pcm_info = info;
3550 codec->num_pcms = 0;
3551
3552 info->name = "CA0132 Analog";
3553 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
3554 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
3555 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
3556 spec->multiout.max_channels;
3557 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
3558 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_inputs;
3559 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
3560 codec->num_pcms++;
3561
3562 if (!spec->dig_out && !spec->dig_in)
3563 return 0;
3564
3565 info++;
3566 info->name = "CA0132 Digital";
3567 info->pcm_type = HDA_PCM_TYPE_SPDIF;
3568 if (spec->dig_out) {
3569 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
3570 ca0132_pcm_digital_playback;
3571 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
3572 }
3573 if (spec->dig_in) {
3574 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
3575 ca0132_pcm_digital_capture;
3576 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
3577 }
3578 codec->num_pcms++;
95c6e9cb 3579
a7e76271 3580 return 0;
95c6e9cb
IM		 3581}
3582
3583static int ca0132_build_controls(struct hda_codec *codec)
3584{
3585 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3586 int i, num_fx;
3587 int err = 0;
95c6e9cb 3588
a7e76271
IM		 3589 /* Add Mixer controls */
3590 for (i = 0; i < spec->num_mixers; i++) {
3591 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
95c6e9cb
IM		 3592 if (err < 0)
3593 return err;
3594 }
3595
a7e76271
IM		 3596 /* Add in and out effects controls.
3597 * VoiceFX, PE and CrystalVoice are added separately.
3598 */
3599 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3600 for (i = 0; i < num_fx; i++) {
3601 err = add_fx_switch(codec, ca0132_effects[i].nid,
3602 ca0132_effects[i].name,
3603 ca0132_effects[i].direct);
95c6e9cb
IM		 3604 if (err < 0)
3605 return err;
3606 }
3607
a7e76271
IM		 3608 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3609 if (err < 0)
3610 return err;
95c6e9cb 3611
a7e76271
IM		 3612 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3613 if (err < 0)
3614 return err;
3615
3616 add_voicefx(codec);
3617
3618 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3619 if (err < 0)
3620 return err;
95c6e9cb
IM		 3621
3622 if (spec->dig_out) {
efb9f469
TI		 3623 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3624 spec->dig_out);
95c6e9cb
IM		 3625 if (err < 0)
3626 return err;
8e13fc1c 3627 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
95c6e9cb
IM		 3628 if (err < 0)
3629 return err;
8e13fc1c 3630 /* spec->multiout.share_spdif = 1; */
95c6e9cb
IM		 3631 }
3632
3633 if (spec->dig_in) {
3634 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
3635 if (err < 0)
3636 return err;
95c6e9cb
IM		 3637 }
3638 return 0;
3639}
3640
5aaca44d
IM		 3641static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
3642{
3643 unsigned int caps;
3644
3645 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
3646 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
3647 snd_hda_override_amp_caps(codec, nid, dir, caps);
3648}
3649
3650/*
3651 * Switch between Digital built-in mic and analog mic.
3652 */
3653static void ca0132_set_dmic(struct hda_codec *codec, int enable)
3654{
3655 struct ca0132_spec *spec = codec->spec;
3656 unsigned int tmp;
3657 u8 val;
3658 unsigned int oldval;
3659
3660 snd_printdd(KERN_INFO "ca0132_set_dmic: enable=%d\n", enable);
3661
3662 oldval = stop_mic1(codec);
3663 ca0132_set_vipsource(codec, 0);
3664 if (enable) {
3665 /* set DMic input as 2-ch */
3666 tmp = FLOAT_TWO;
3667 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3668
3669 val = spec->dmic_ctl;
3670 val |= 0x80;
3671 snd_hda_codec_write(codec, spec->input_pins[0], 0,
3672 VENDOR_CHIPIO_DMIC_CTL_SET, val);
3673
3674 if (!(spec->dmic_ctl & 0x20))
3675 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
3676 } else {
3677 /* set AMic input as mono */
3678 tmp = FLOAT_ONE;
3679 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3680
3681 val = spec->dmic_ctl;
3682 /* clear bit7 and bit5 to disable dmic */
3683 val &= 0x5f;
3684 snd_hda_codec_write(codec, spec->input_pins[0], 0,
3685 VENDOR_CHIPIO_DMIC_CTL_SET, val);
3686
3687 if (!(spec->dmic_ctl & 0x20))
3688 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
3689 }
3690 ca0132_set_vipsource(codec, 1);
3691 resume_mic1(codec, oldval);
3692}
3693
3694/*
3695 * Initialization for Digital Mic.
3696 */
3697static void ca0132_init_dmic(struct hda_codec *codec)
3698{
3699 struct ca0132_spec *spec = codec->spec;
3700 u8 val;
3701
3702 /* Setup Digital Mic here, but don't enable.
3703 * Enable based on jack detect.
3704 */
3705
3706 /* MCLK uses MPIO1, set to enable.
3707 * Bit 2-0: MPIO select
3708 * Bit 3: set to disable
3709 * Bit 7-4: reserved
3710 */
3711 val = 0x01;
3712 snd_hda_codec_write(codec, spec->input_pins[0], 0,
3713 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
3714
3715 /* Data1 uses MPIO3. Data2 not use
3716 * Bit 2-0: Data1 MPIO select
3717 * Bit 3: set disable Data1
3718 * Bit 6-4: Data2 MPIO select
3719 * Bit 7: set disable Data2
3720 */
3721 val = 0x83;
3722 snd_hda_codec_write(codec, spec->input_pins[0], 0,
3723 VENDOR_CHIPIO_DMIC_PIN_SET, val);
3724
3725 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
3726 * Bit 3-0: Channel mask
3727 * Bit 4: set for 48KHz, clear for 32KHz
3728 * Bit 5: mode
3729 * Bit 6: set to select Data2, clear for Data1
3730 * Bit 7: set to enable DMic, clear for AMic
3731 */
3732 val = 0x23;
3733 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
3734 spec->dmic_ctl = val;
3735 snd_hda_codec_write(codec, spec->input_pins[0], 0,
3736 VENDOR_CHIPIO_DMIC_CTL_SET, val);
3737}
3738
3739/*
3740 * Initialization for Analog Mic 2
3741 */
3742static void ca0132_init_analog_mic2(struct hda_codec *codec)
3743{
3744 struct ca0132_spec *spec = codec->spec;
3745
3746 mutex_lock(&spec->chipio_mutex);
3747 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
3748 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
3749 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
3750 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
3751 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
3752 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
3753 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
3754 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
3755 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
3756 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
3757 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
3758 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
3759 mutex_unlock(&spec->chipio_mutex);
3760}
3761
3762static void ca0132_refresh_widget_caps(struct hda_codec *codec)
3763{
3764 struct ca0132_spec *spec = codec->spec;
3765 int i;
3766 hda_nid_t nid;
3767
3768 snd_printdd(KERN_INFO "ca0132_refresh_widget_caps.\n");
3769 nid = codec->start_nid;
3770 for (i = 0; i < codec->num_nodes; i++, nid++)
3771 codec->wcaps[i] = snd_hda_param_read(codec, nid,
3772 AC_PAR_AUDIO_WIDGET_CAP);
3773
3774 for (i = 0; i < spec->multiout.num_dacs; i++)
3775 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
3776
3777 for (i = 0; i < spec->num_outputs; i++)
3778 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
3779
3780 for (i = 0; i < spec->num_inputs; i++) {
3781 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
3782 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
3783 }
3784}
3785
3786/*
3787 * Setup default parameters for DSP
3788 */
3789static void ca0132_setup_defaults(struct hda_codec *codec)
3790{
3791 unsigned int tmp;
3792 int num_fx;
3793 int idx, i;
3794
3795 if (!dspload_is_loaded(codec))
3796 return;
3797
3798 /* out, in effects + voicefx */
3799 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
3800 for (idx = 0; idx < num_fx; idx++) {
3801 for (i = 0; i <= ca0132_effects[idx].params; i++) {
3802 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3803 ca0132_effects[idx].reqs[i],
3804 ca0132_effects[idx].def_vals[i]);
3805 }
3806 }
3807
3808 /*remove DSP headroom*/
3809 tmp = FLOAT_ZERO;
3810 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
3811
3812 /*set speaker EQ bypass attenuation*/
3813 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
3814
3815 /* set AMic1 and AMic2 as mono mic */
3816 tmp = FLOAT_ONE;
3817 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3818 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
3819
3820 /* set AMic1 as CrystalVoice input */
3821 tmp = FLOAT_ONE;
3822 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3823
3824 /* set WUH source */
3825 tmp = FLOAT_TWO;
3826 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
3827}
3828
3829/*
3830 * Initialization of flags in chip
3831 */
3832static void ca0132_init_flags(struct hda_codec *codec)
3833{
3834 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
3835 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
3836 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
3837 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
3838 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
3839 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
3840}
3841
3842/*
3843 * Initialization of parameters in chip
3844 */
3845static void ca0132_init_params(struct hda_codec *codec)
3846{
3847 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
3848 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
3849}
95c6e9cb 3850
95c6e9cb
IM		 3851static void ca0132_config(struct hda_codec *codec)
3852{
3853 struct ca0132_spec *spec = codec->spec;
3854 struct auto_pin_cfg *cfg = &spec->autocfg;
3855
a7e76271
IM		 3856 spec->dacs[0] = 0x2;
3857 spec->dacs[1] = 0x3;
3858 spec->dacs[2] = 0x4;
95c6e9cb 3859
95c6e9cb 3860 spec->multiout.dac_nids = spec->dacs;
a7e76271 3861 spec->multiout.num_dacs = 3;
95c6e9cb
IM		 3862 spec->multiout.max_channels = 2;
3863
a7e76271
IM		 3864 spec->num_outputs = 2;
3865 spec->out_pins[0] = 0x0b; /* speaker out */
3866 spec->out_pins[1] = 0x10; /* headphone out */
3867 spec->shared_out_nid = 0x2;
95c6e9cb 3868
a7e76271
IM		 3869 spec->num_inputs = 3;
3870 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
3871 spec->adcs[1] = 0x8; /* analog mic2 */
3872 spec->adcs[2] = 0xa; /* what u hear */
3873 spec->shared_mic_nid = 0x7;
95c6e9cb 3874
95c6e9cb 3875 spec->input_pins[0] = 0x12;
95c6e9cb 3876 spec->input_pins[1] = 0x11;
a7e76271 3877 spec->input_pins[2] = 0x13;
8e13fc1c
TI		 3878
3879 /* SPDIF I/O */
3880 spec->dig_out = 0x05;
3881 spec->multiout.dig_out_nid = spec->dig_out;
3882 cfg->dig_out_pins[0] = 0x0c;
3883 cfg->dig_outs = 1;
3884 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
3885 spec->dig_in = 0x09;
3886 cfg->dig_in_pin = 0x0e;
3887 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
95c6e9cb
IM		 3888}
3889
5aaca44d
IM		 3890/*
3891 * Verbs tables.
3892 */
3893
3894/* Sends before DSP download. */
3895static struct hda_verb ca0132_base_init_verbs[] = {
3896 /*enable ct extension*/
3897 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
3898 /*enable DSP node unsol, needed for DSP download*/
3899 {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
3900 {}
3901};
3902
3903/* Send at exit. */
3904static struct hda_verb ca0132_base_exit_verbs[] = {
3905 /*set afg to D3*/
3906 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
3907 /*disable ct extension*/
3908 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
3909 {}
3910};
3911
3912/* Other verbs tables. Sends after DSP download. */
3913static struct hda_verb ca0132_init_verbs0[] = {
3914 /* chip init verbs */
3915 {0x15, 0x70D, 0xF0},
3916 {0x15, 0x70E, 0xFE},
3917 {0x15, 0x707, 0x75},
3918 {0x15, 0x707, 0xD3},
3919 {0x15, 0x707, 0x09},
3920 {0x15, 0x707, 0x53},
3921 {0x15, 0x707, 0xD4},
3922 {0x15, 0x707, 0xEF},
3923 {0x15, 0x707, 0x75},
3924 {0x15, 0x707, 0xD3},
3925 {0x15, 0x707, 0x09},
3926 {0x15, 0x707, 0x02},
3927 {0x15, 0x707, 0x37},
3928 {0x15, 0x707, 0x78},
3929 {0x15, 0x53C, 0xCE},
3930 {0x15, 0x575, 0xC9},
3931 {0x15, 0x53D, 0xCE},
3932 {0x15, 0x5B7, 0xC9},
3933 {0x15, 0x70D, 0xE8},
3934 {0x15, 0x70E, 0xFE},
3935 {0x15, 0x707, 0x02},
3936 {0x15, 0x707, 0x68},
3937 {0x15, 0x707, 0x62},
3938 {0x15, 0x53A, 0xCE},
3939 {0x15, 0x546, 0xC9},
3940 {0x15, 0x53B, 0xCE},
3941 {0x15, 0x5E8, 0xC9},
3942 {0x15, 0x717, 0x0D},
3943 {0x15, 0x718, 0x20},
3944 {}
3945};
3946
3947static struct hda_verb ca0132_init_verbs1[] = {
3948 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
3949 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
3950 /* config EAPD */
3951 {0x0b, 0x78D, 0x00},
3952 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
3953 /*{0x10, 0x78D, 0x02},*/
3954 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
3955 {}
3956};
3957
95c6e9cb
IM		 3958static void ca0132_init_chip(struct hda_codec *codec)
3959{
3960 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 3961 int num_fx;
3962 int i;
3963 unsigned int on;
95c6e9cb
IM		 3964
3965 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 3966
3967 spec->cur_out_type = SPEAKER_OUT;
3968 spec->cur_mic_type = DIGITAL_MIC;
3969 spec->cur_mic_boost = 0;
3970
3971 for (i = 0; i < VNODES_COUNT; i++) {
3972 spec->vnode_lvol[i] = 0x5a;
3973 spec->vnode_rvol[i] = 0x5a;
3974 spec->vnode_lswitch[i] = 0;
3975 spec->vnode_rswitch[i] = 0;
3976 }
3977
3978 /*
3979 * Default states for effects are in ca0132_effects[].
3980 */
3981 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3982 for (i = 0; i < num_fx; i++) {
3983 on = (unsigned int)ca0132_effects[i].reqs[0];
3984 spec->effects_switch[i] = on ? 1 : 0;
3985 }
3986
3987 spec->voicefx_val = 0;
3988 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
3989 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
3990
95c6e9cb
IM		 3991}
3992
3993static void ca0132_exit_chip(struct hda_codec *codec)
3994{
3995 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 3996
3997 if (dspload_is_loaded(codec))
3998 dsp_reset(codec);
95c6e9cb
IM		 3999}
4000
01ef7dbf
IM		 4001static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4002{
4003 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4004 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4005 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4006 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4007 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4008 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4009
4010 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4011 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4012 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4013}
4014
4015static bool ca0132_download_dsp_images(struct hda_codec *codec)
4016{
4017 bool dsp_loaded = false;
4018 const struct dsp_image_seg *dsp_os_image;
01ef7dbf 4019
c3b4eea2
IM		 4020 if (request_firmware_cached(&fw_efx, EFX_FILE,
4021 codec->bus->card->dev) != 0)
01ef7dbf
IM		 4022 return false;
4023
c3b4eea2 4024 dsp_os_image = (struct dsp_image_seg *)(fw_efx->data);
01ef7dbf
IM		 4025 dspload_image(codec, dsp_os_image, 0, 0, true, 0);
4026 dsp_loaded = dspload_wait_loaded(codec);
4027
01ef7dbf
IM		 4028 return dsp_loaded;
4029}
4030
4031static void ca0132_download_dsp(struct hda_codec *codec)
4032{
4033 struct ca0132_spec *spec = codec->spec;
4034
4035 spec->dsp_state = DSP_DOWNLOAD_INIT;
4036
4037 if (spec->dsp_state == DSP_DOWNLOAD_INIT) {
4038 chipio_enable_clocks(codec);
4039 spec->dsp_state = DSP_DOWNLOADING;
4040 if (!ca0132_download_dsp_images(codec))
4041 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4042 else
4043 spec->dsp_state = DSP_DOWNLOADED;
4044 }
4045
4046 if (spec->dsp_state == DSP_DOWNLOADED)
4047 ca0132_set_dsp_msr(codec, true);
4048}
4049
95c6e9cb
IM		 4050static int ca0132_init(struct hda_codec *codec)
4051{
4052 struct ca0132_spec *spec = codec->spec;
4053 struct auto_pin_cfg *cfg = &spec->autocfg;
4054 int i;
4055
5aaca44d
IM		 4056 spec->dsp_state = DSP_DOWNLOAD_INIT;
4057 spec->curr_chip_addx = (unsigned int)INVALID_CHIP_ADDRESS;
4058
4059 snd_hda_power_up(codec);
4060
4061 ca0132_init_params(codec);
4062 ca0132_init_flags(codec);
4063 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf
IM		 4064#ifdef CONFIG_SND_HDA_DSP_LOADER
4065 ca0132_download_dsp(codec);
4066#endif
5aaca44d
IM		 4067 ca0132_refresh_widget_caps(codec);
4068 ca0132_setup_defaults(codec);
4069 ca0132_init_analog_mic2(codec);
4070 ca0132_init_dmic(codec);
4071
4072 for (i = 0; i < spec->num_outputs; i++)
4073 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4074
95c6e9cb
IM		 4075 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4076
4077 for (i = 0; i < spec->num_inputs; i++)
4078 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4079
4080 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4081
5aaca44d
IM		 4082 for (i = 0; i < spec->num_init_verbs; i++)
4083 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4084
4085 ca0132_select_out(codec);
4086 ca0132_select_mic(codec);
4087
4088 snd_hda_power_down(codec);
95c6e9cb
IM		 4089
4090 return 0;
4091}
4092
95c6e9cb
IM		 4093static void ca0132_free(struct hda_codec *codec)
4094{
5aaca44d
IM		 4095 struct ca0132_spec *spec = codec->spec;
4096
4097 snd_hda_power_up(codec);
4098 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4099 ca0132_exit_chip(codec);
5aaca44d 4100 snd_hda_power_down(codec);
95c6e9cb
IM		 4101 kfree(codec->spec);
4102}
4103
4104static struct hda_codec_ops ca0132_patch_ops = {
4105 .build_controls = ca0132_build_controls,
4106 .build_pcms = ca0132_build_pcms,
4107 .init = ca0132_init,
4108 .free = ca0132_free,
4109};
4110
95c6e9cb
IM		 4111static int patch_ca0132(struct hda_codec *codec)
4112{
4113 struct ca0132_spec *spec;
4114
4115 snd_printdd("patch_ca0132\n");
4116
4117 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4118 if (!spec)
4119 return -ENOMEM;
4120 codec->spec = spec;
4121
a7e76271
IM		 4122 spec->num_mixers = 1;
4123 spec->mixers[0] = ca0132_mixer;
4124
5aaca44d
IM		 4125 spec->base_init_verbs = ca0132_base_init_verbs;
4126 spec->base_exit_verbs = ca0132_base_exit_verbs;
4127 spec->init_verbs[0] = ca0132_init_verbs0;
4128 spec->init_verbs[1] = ca0132_init_verbs1;
4129 spec->num_init_verbs = 2;
4130
95c6e9cb
IM		 4131 ca0132_init_chip(codec);
4132
4133 ca0132_config(codec);
4134
4135 codec->patch_ops = ca0132_patch_ops;
4136
4137 return 0;
4138}
4139
4140/*
4141 * patch entries
4142 */
4143static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4144 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4145 {} /* terminator */
4146};
4147
4148MODULE_ALIAS("snd-hda-codec-id:11020011");
4149
4150MODULE_LICENSE("GPL");
4151MODULE_DESCRIPTION("Creative CA0132, CA0132 HD-audio codec");
4152
4153static struct hda_codec_preset_list ca0132_list = {
4154 .preset = snd_hda_preset_ca0132,
4155 .owner = THIS_MODULE,
4156};
4157
4158static int __init patch_ca0132_init(void)
4159{
4160 return snd_hda_add_codec_preset(&ca0132_list);
4161}
4162
4163static void __exit patch_ca0132_exit(void)
4164{
c3b4eea2 4165 release_cached_firmware();
95c6e9cb
IM		 4166 snd_hda_delete_codec_preset(&ca0132_list);
4167}
4168
4169module_init(patch_ca0132_init)
4170module_exit(patch_ca0132_exit)
Linux 6.x block layer and io_uring tree(s)