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ALSA: hda: Use struct_size()
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
d9b84a15 34#include <asm/io.h>
95c6e9cb 35#include <sound/core.h>
be57bfff 36#include <sound/hda_codec.h>
95c6e9cb 37#include "hda_local.h"
128bc4ba 38#include "hda_auto_parser.h"
5aaca44d 39#include "hda_jack.h"
95c6e9cb 40
bcd109c0
IM		 41#include "ca0132_regs.h"
42
ef6b2ead
IM		 43/* Enable this to see controls for tuning purpose. */
44/*#define ENABLE_TUNING_CONTROLS*/
45
8e142e9e
TS		 46#ifdef ENABLE_TUNING_CONTROLS
47#include <sound/tlv.h>
48#endif
49
ef6b2ead
IM		 50#define FLOAT_ZERO 0x00000000
51#define FLOAT_ONE 0x3f800000
52#define FLOAT_TWO 0x40000000
38ba69ff 53#define FLOAT_THREE 0x40400000
7cb9d94c 54#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 55#define FLOAT_MINUS_5 0xc0a00000
56
ef6b2ead
IM		 57#define UNSOL_TAG_DSP 0x16
58
4aa3bb0c
IM		 59#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
60#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
61
62#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
63#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
64#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
65
66#define MASTERCONTROL 0x80
ef6b2ead
IM		 67#define MASTERCONTROL_ALLOC_DMA_CHAN 10
68#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 69
95c6e9cb
IM		 70#define WIDGET_CHIP_CTRL 0x15
71#define WIDGET_DSP_CTRL 0x16
72
4aa3bb0c
IM		 73#define MEM_CONNID_MICIN1 3
74#define MEM_CONNID_MICIN2 5
75#define MEM_CONNID_MICOUT1 12
76#define MEM_CONNID_MICOUT2 14
77#define MEM_CONNID_WUH 10
78#define MEM_CONNID_DSP 16
79#define MEM_CONNID_DMIC 100
80
81#define SCP_SET 0
82#define SCP_GET 1
83
01ef7dbf 84#define EFX_FILE "ctefx.bin"
7a928186 85#define DESKTOP_EFX_FILE "ctefx-desktop.bin"
8a19bcee 86#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 87
24f3cede 88#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 89MODULE_FIRMWARE(EFX_FILE);
7a928186 90MODULE_FIRMWARE(DESKTOP_EFX_FILE);
8a19bcee 91MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 92#endif
01ef7dbf 93
3a03f83b 94static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 95
7cb9d94c 96#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 97enum {
98 SPEAKER_OUT,
7cb9d94c
CM		 99 HEADPHONE_OUT,
100 SURROUND_OUT
ef6b2ead
IM		 101};
102
103enum {
104 DIGITAL_MIC,
105 LINE_MIC_IN
106};
107
7cb9d94c 108/* Strings for Input Source Enum Control */
3a03f83b 109static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 110#define IN_SRC_NUM_OF_INPUTS 3
111enum {
112 REAR_MIC,
113 REAR_LINE_IN,
114 FRONT_MIC,
115};
116
ef6b2ead
IM		 117enum {
118#define VNODE_START_NID 0x80
119 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
120 VNID_MIC,
121 VNID_HP_SEL,
122 VNID_AMIC1_SEL,
123 VNID_HP_ASEL,
124 VNID_AMIC1_ASEL,
125 VNODE_END_NID,
126#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
127
128#define EFFECT_START_NID 0x90
129#define OUT_EFFECT_START_NID EFFECT_START_NID
130 SURROUND = OUT_EFFECT_START_NID,
131 CRYSTALIZER,
132 DIALOG_PLUS,
133 SMART_VOLUME,
134 X_BASS,
135 EQUALIZER,
136 OUT_EFFECT_END_NID,
137#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
138
139#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
140 ECHO_CANCELLATION = IN_EFFECT_START_NID,
141 VOICE_FOCUS,
142 MIC_SVM,
143 NOISE_REDUCTION,
144 IN_EFFECT_END_NID,
145#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
146
147 VOICEFX = IN_EFFECT_END_NID,
148 PLAY_ENHANCEMENT,
149 CRYSTAL_VOICE,
7cb9d94c
CM		 150 EFFECT_END_NID,
151 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 152 INPUT_SOURCE_ENUM,
153 XBASS_XOVER,
154 EQ_PRESET_ENUM,
155 SMART_VOLUME_ENUM,
212de2e7
CM		 156 MIC_BOOST_ENUM,
157 AE5_HEADPHONE_GAIN_ENUM,
d51434d4
CM		 158 AE5_SOUND_FILTER_ENUM,
159 ZXR_HEADPHONE_GAIN
ef6b2ead
IM		 160#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
161};
162
163/* Effects values size*/
164#define EFFECT_VALS_MAX_COUNT 12
165
47cdf76e
CM		 166/*
167 * Default values for the effect slider controls, they are in order of their
168 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
169 * X-bass.
170 */
171static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
172/* Amount of effect level sliders for ca0132_alt controls. */
173#define EFFECT_LEVEL_SLIDERS 5
174
e8412ca4
DR		 175/* Latency introduced by DSP blocks in milliseconds. */
176#define DSP_CAPTURE_INIT_LATENCY 0
177#define DSP_CRYSTAL_VOICE_LATENCY 124
178#define DSP_PLAYBACK_INIT_LATENCY 13
179#define DSP_PLAY_ENHANCEMENT_LATENCY 30
180#define DSP_SPEAKER_OUT_LATENCY 7
181
ef6b2ead 182struct ct_effect {
975cc02a 183 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 184 hda_nid_t nid;
185 int mid; /*effect module ID*/
186 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
187 int direct; /* 0:output; 1:input*/
188 int params; /* number of default non-on/off params */
189 /*effect default values, 1st is on/off. */
190 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
191};
192
193#define EFX_DIR_OUT 0
194#define EFX_DIR_IN 1
195
862154bb 196static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 197 { .name = "Surround",
198 .nid = SURROUND,
199 .mid = 0x96,
200 .reqs = {0, 1},
201 .direct = EFX_DIR_OUT,
202 .params = 1,
203 .def_vals = {0x3F800000, 0x3F2B851F}
204 },
205 { .name = "Crystalizer",
206 .nid = CRYSTALIZER,
207 .mid = 0x96,
208 .reqs = {7, 8},
209 .direct = EFX_DIR_OUT,
210 .params = 1,
211 .def_vals = {0x3F800000, 0x3F266666}
212 },
213 { .name = "Dialog Plus",
214 .nid = DIALOG_PLUS,
215 .mid = 0x96,
216 .reqs = {2, 3},
217 .direct = EFX_DIR_OUT,
218 .params = 1,
219 .def_vals = {0x00000000, 0x3F000000}
220 },
221 { .name = "Smart Volume",
222 .nid = SMART_VOLUME,
223 .mid = 0x96,
224 .reqs = {4, 5, 6},
225 .direct = EFX_DIR_OUT,
226 .params = 2,
227 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
228 },
229 { .name = "X-Bass",
230 .nid = X_BASS,
231 .mid = 0x96,
232 .reqs = {24, 23, 25},
233 .direct = EFX_DIR_OUT,
234 .params = 2,
235 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
236 },
237 { .name = "Equalizer",
238 .nid = EQUALIZER,
239 .mid = 0x96,
240 .reqs = {9, 10, 11, 12, 13, 14,
241 15, 16, 17, 18, 19, 20},
242 .direct = EFX_DIR_OUT,
243 .params = 11,
244 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
245 0x00000000, 0x00000000, 0x00000000, 0x00000000,
246 0x00000000, 0x00000000, 0x00000000, 0x00000000}
247 },
248 { .name = "Echo Cancellation",
249 .nid = ECHO_CANCELLATION,
250 .mid = 0x95,
251 .reqs = {0, 1, 2, 3},
252 .direct = EFX_DIR_IN,
253 .params = 3,
254 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
255 },
256 { .name = "Voice Focus",
257 .nid = VOICE_FOCUS,
258 .mid = 0x95,
259 .reqs = {6, 7, 8, 9},
260 .direct = EFX_DIR_IN,
261 .params = 3,
262 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
263 },
264 { .name = "Mic SVM",
265 .nid = MIC_SVM,
266 .mid = 0x95,
267 .reqs = {44, 45},
268 .direct = EFX_DIR_IN,
269 .params = 1,
270 .def_vals = {0x00000000, 0x3F3D70A4}
271 },
272 { .name = "Noise Reduction",
273 .nid = NOISE_REDUCTION,
274 .mid = 0x95,
275 .reqs = {4, 5},
276 .direct = EFX_DIR_IN,
277 .params = 1,
278 .def_vals = {0x3F800000, 0x3F000000}
279 },
280 { .name = "VoiceFX",
281 .nid = VOICEFX,
282 .mid = 0x95,
283 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
284 .direct = EFX_DIR_IN,
285 .params = 8,
286 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
287 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
288 0x00000000}
289 }
290};
291
292/* Tuning controls */
293#ifdef ENABLE_TUNING_CONTROLS
294
295enum {
296#define TUNING_CTL_START_NID 0xC0
297 WEDGE_ANGLE = TUNING_CTL_START_NID,
298 SVM_LEVEL,
299 EQUALIZER_BAND_0,
300 EQUALIZER_BAND_1,
301 EQUALIZER_BAND_2,
302 EQUALIZER_BAND_3,
303 EQUALIZER_BAND_4,
304 EQUALIZER_BAND_5,
305 EQUALIZER_BAND_6,
306 EQUALIZER_BAND_7,
307 EQUALIZER_BAND_8,
308 EQUALIZER_BAND_9,
309 TUNING_CTL_END_NID
310#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
311};
312
313struct ct_tuning_ctl {
975cc02a 314 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 315 hda_nid_t parent_nid;
316 hda_nid_t nid;
317 int mid; /*effect module ID*/
318 int req; /*effect module request*/
319 int direct; /* 0:output; 1:input*/
320 unsigned int def_val;/*effect default values*/
321};
322
862154bb 323static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 324 { .name = "Wedge Angle",
325 .parent_nid = VOICE_FOCUS,
326 .nid = WEDGE_ANGLE,
327 .mid = 0x95,
328 .req = 8,
329 .direct = EFX_DIR_IN,
330 .def_val = 0x41F00000
331 },
332 { .name = "SVM Level",
333 .parent_nid = MIC_SVM,
334 .nid = SVM_LEVEL,
335 .mid = 0x95,
336 .req = 45,
337 .direct = EFX_DIR_IN,
338 .def_val = 0x3F3D70A4
339 },
340 { .name = "EQ Band0",
341 .parent_nid = EQUALIZER,
342 .nid = EQUALIZER_BAND_0,
343 .mid = 0x96,
344 .req = 11,
345 .direct = EFX_DIR_OUT,
346 .def_val = 0x00000000
347 },
348 { .name = "EQ Band1",
349 .parent_nid = EQUALIZER,
350 .nid = EQUALIZER_BAND_1,
351 .mid = 0x96,
352 .req = 12,
353 .direct = EFX_DIR_OUT,
354 .def_val = 0x00000000
355 },
356 { .name = "EQ Band2",
357 .parent_nid = EQUALIZER,
358 .nid = EQUALIZER_BAND_2,
359 .mid = 0x96,
360 .req = 13,
361 .direct = EFX_DIR_OUT,
362 .def_val = 0x00000000
363 },
364 { .name = "EQ Band3",
365 .parent_nid = EQUALIZER,
366 .nid = EQUALIZER_BAND_3,
367 .mid = 0x96,
368 .req = 14,
369 .direct = EFX_DIR_OUT,
370 .def_val = 0x00000000
371 },
372 { .name = "EQ Band4",
373 .parent_nid = EQUALIZER,
374 .nid = EQUALIZER_BAND_4,
375 .mid = 0x96,
376 .req = 15,
377 .direct = EFX_DIR_OUT,
378 .def_val = 0x00000000
379 },
380 { .name = "EQ Band5",
381 .parent_nid = EQUALIZER,
382 .nid = EQUALIZER_BAND_5,
383 .mid = 0x96,
384 .req = 16,
385 .direct = EFX_DIR_OUT,
386 .def_val = 0x00000000
387 },
388 { .name = "EQ Band6",
389 .parent_nid = EQUALIZER,
390 .nid = EQUALIZER_BAND_6,
391 .mid = 0x96,
392 .req = 17,
393 .direct = EFX_DIR_OUT,
394 .def_val = 0x00000000
395 },
396 { .name = "EQ Band7",
397 .parent_nid = EQUALIZER,
398 .nid = EQUALIZER_BAND_7,
399 .mid = 0x96,
400 .req = 18,
401 .direct = EFX_DIR_OUT,
402 .def_val = 0x00000000
403 },
404 { .name = "EQ Band8",
405 .parent_nid = EQUALIZER,
406 .nid = EQUALIZER_BAND_8,
407 .mid = 0x96,
408 .req = 19,
409 .direct = EFX_DIR_OUT,
410 .def_val = 0x00000000
411 },
412 { .name = "EQ Band9",
413 .parent_nid = EQUALIZER,
414 .nid = EQUALIZER_BAND_9,
415 .mid = 0x96,
416 .req = 20,
417 .direct = EFX_DIR_OUT,
418 .def_val = 0x00000000
419 }
420};
421#endif
422
423/* Voice FX Presets */
424#define VOICEFX_MAX_PARAM_COUNT 9
425
426struct ct_voicefx {
427 char *name;
428 hda_nid_t nid;
429 int mid;
430 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
431};
432
433struct ct_voicefx_preset {
434 char *name; /*preset name*/
435 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
436};
437
862154bb 438static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 439 .name = "VoiceFX Capture Switch",
440 .nid = VOICEFX,
441 .mid = 0x95,
442 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
443};
444
862154bb 445static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 446 { .name = "Neutral",
447 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
448 0x44FA0000, 0x3F800000, 0x3F800000,
449 0x3F800000, 0x00000000, 0x00000000 }
450 },
451 { .name = "Female2Male",
452 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
453 0x44FA0000, 0x3F19999A, 0x3F866666,
454 0x3F800000, 0x00000000, 0x00000000 }
455 },
456 { .name = "Male2Female",
457 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
458 0x450AC000, 0x4017AE14, 0x3F6B851F,
459 0x3F800000, 0x00000000, 0x00000000 }
460 },
461 { .name = "ScrappyKid",
462 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
463 0x44FA0000, 0x40400000, 0x3F28F5C3,
464 0x3F800000, 0x00000000, 0x00000000 }
465 },
466 { .name = "Elderly",
467 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
468 0x44E10000, 0x3FB33333, 0x3FB9999A,
469 0x3F800000, 0x3E3A2E43, 0x00000000 }
470 },
471 { .name = "Orc",
472 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
473 0x45098000, 0x3F266666, 0x3FC00000,
474 0x3F800000, 0x00000000, 0x00000000 }
475 },
476 { .name = "Elf",
477 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
478 0x45193000, 0x3F8E147B, 0x3F75C28F,
479 0x3F800000, 0x00000000, 0x00000000 }
480 },
481 { .name = "Dwarf",
482 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
483 0x45007000, 0x3F451EB8, 0x3F7851EC,
484 0x3F800000, 0x00000000, 0x00000000 }
485 },
486 { .name = "AlienBrute",
487 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
488 0x451F6000, 0x3F266666, 0x3FA7D945,
489 0x3F800000, 0x3CF5C28F, 0x00000000 }
490 },
491 { .name = "Robot",
492 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
493 0x44FA0000, 0x3FB2718B, 0x3F800000,
494 0xBC07010E, 0x00000000, 0x00000000 }
495 },
496 { .name = "Marine",
497 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
498 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
499 0x3F0A3D71, 0x00000000, 0x00000000 }
500 },
501 { .name = "Emo",
502 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
503 0x44FA0000, 0x3F800000, 0x3F800000,
504 0x3E4CCCCD, 0x00000000, 0x00000000 }
505 },
506 { .name = "DeepVoice",
507 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
508 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
509 0x3F800000, 0x00000000, 0x00000000 }
510 },
511 { .name = "Munchkin",
512 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
513 0x44FA0000, 0x3F800000, 0x3F1A043C,
514 0x3F800000, 0x00000000, 0x00000000 }
515 }
516};
517
47cdf76e
CM		 518/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
519
520#define EQ_PRESET_MAX_PARAM_COUNT 11
521
522struct ct_eq {
523 char *name;
524 hda_nid_t nid;
525 int mid;
526 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
527};
528
529struct ct_eq_preset {
530 char *name; /*preset name*/
531 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
532};
533
862154bb 534static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 535 .name = "FX: Equalizer Preset Switch",
536 .nid = EQ_PRESET_ENUM,
537 .mid = 0x96,
538 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
539};
540
541
862154bb 542static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 543 { .name = "Flat",
544 .vals = { 0x00000000, 0x00000000, 0x00000000,
545 0x00000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x00000000,
547 0x00000000, 0x00000000 }
548 },
549 { .name = "Acoustic",
550 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
551 0x40000000, 0x00000000, 0x00000000,
552 0x00000000, 0x00000000, 0x40000000,
553 0x40000000, 0x40000000 }
554 },
555 { .name = "Classical",
556 .vals = { 0x00000000, 0x00000000, 0x40C00000,
557 0x40C00000, 0x40466666, 0x00000000,
558 0x00000000, 0x00000000, 0x00000000,
559 0x40466666, 0x40466666 }
560 },
561 { .name = "Country",
562 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
563 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
564 0x00000000, 0x00000000, 0x40000000,
565 0x40466666, 0x40800000 }
566 },
567 { .name = "Dance",
568 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
569 0x40466666, 0x40866666, 0xBF99999A,
570 0xBF99999A, 0x00000000, 0x00000000,
571 0x40800000, 0x40800000 }
572 },
573 { .name = "Jazz",
574 .vals = { 0x00000000, 0x00000000, 0x00000000,
575 0x3F8CCCCD, 0x40800000, 0x40800000,
576 0x40800000, 0x00000000, 0x3F8CCCCD,
577 0x40466666, 0x40466666 }
578 },
579 { .name = "New Age",
580 .vals = { 0x00000000, 0x00000000, 0x40000000,
581 0x40000000, 0x00000000, 0x00000000,
582 0x00000000, 0x3F8CCCCD, 0x40000000,
583 0x40000000, 0x40000000 }
584 },
585 { .name = "Pop",
586 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
587 0x40000000, 0x40000000, 0x00000000,
588 0xBF99999A, 0xBF99999A, 0x00000000,
589 0x40466666, 0x40C00000 }
590 },
591 { .name = "Rock",
592 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
593 0x3F8CCCCD, 0x40000000, 0xBF99999A,
594 0xBF99999A, 0x00000000, 0x00000000,
595 0x40800000, 0x40800000 }
596 },
597 { .name = "Vocal",
598 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
599 0xBF99999A, 0x00000000, 0x40466666,
600 0x40800000, 0x40466666, 0x00000000,
601 0x00000000, 0x3F8CCCCD }
602 }
603};
604
7cb9d94c
CM		 605/* DSP command sequences for ca0132_alt_select_out */
606#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
607struct ca0132_alt_out_set {
608 char *name; /*preset name*/
609 unsigned char commands;
610 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
611 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
612 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
613};
614
615static const struct ca0132_alt_out_set alt_out_presets[] = {
616 { .name = "Line Out",
617 .commands = 7,
618 .mids = { 0x96, 0x96, 0x96, 0x8F,
619 0x96, 0x96, 0x96 },
620 .reqs = { 0x19, 0x17, 0x18, 0x01,
621 0x1F, 0x15, 0x3A },
622 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
623 0x00000000, 0x00000000, 0x00000000,
624 0x00000000 }
625 },
626 { .name = "Headphone",
627 .commands = 7,
628 .mids = { 0x96, 0x96, 0x96, 0x8F,
629 0x96, 0x96, 0x96 },
630 .reqs = { 0x19, 0x17, 0x18, 0x01,
631 0x1F, 0x15, 0x3A },
632 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
633 0x00000000, 0x00000000, 0x00000000,
634 0x00000000 }
635 },
636 { .name = "Surround",
637 .commands = 8,
638 .mids = { 0x96, 0x8F, 0x96, 0x96,
639 0x96, 0x96, 0x96, 0x96 },
640 .reqs = { 0x18, 0x01, 0x1F, 0x15,
641 0x3A, 0x1A, 0x1B, 0x1C },
642 .vals = { 0x00000000, 0x00000000, 0x00000000,
643 0x00000000, 0x00000000, 0x00000000,
644 0x00000000, 0x00000000 }
645 }
646};
647
017310fb
CM		 648/*
649 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
650 * and I don't know what the third req is, but it's always zero. I assume it's
651 * some sort of update or set command to tell the DSP there's new volume info.
652 */
653#define DSP_VOL_OUT 0
654#define DSP_VOL_IN 1
655
656struct ct_dsp_volume_ctl {
657 hda_nid_t vnid;
658 int mid; /* module ID*/
659 unsigned int reqs[3]; /* scp req ID */
660};
661
862154bb 662static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 663 { .vnid = VNID_SPK,
664 .mid = 0x32,
665 .reqs = {3, 4, 2}
666 },
667 { .vnid = VNID_MIC,
668 .mid = 0x37,
669 .reqs = {2, 3, 1}
670 }
671};
672
2283c85b
CM		 673/* Values for ca0113_mmio_command_set for selecting output. */
674#define AE5_CA0113_OUT_SET_COMMANDS 6
675struct ae5_ca0113_output_set {
676 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS];
677 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS];
678 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS];
679};
680
681static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = {
682 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
683 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
684 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
685 },
686 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
687 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
688 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 }
689 },
690 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
691 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
692 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
693 }
694};
695
212de2e7
CM		 696/* ae5 ca0113 command sequences to set headphone gain levels. */
697#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
698struct ae5_headphone_gain_set {
699 char *name;
700 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
701};
702
703static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
704 { .name = "Low (16-31",
705 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
706 },
707 { .name = "Medium (32-149",
708 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
709 },
710 { .name = "High (150-600",
711 .vals = { 0xff, 0xff, 0xff, 0x7f }
712 }
713};
714
715struct ae5_filter_set {
716 char *name;
717 unsigned int val;
718};
719
720static const struct ae5_filter_set ae5_filter_presets[] = {
721 { .name = "Slow Roll Off",
722 .val = 0xa0
723 },
724 { .name = "Minimum Phase",
725 .val = 0xc0
726 },
727 { .name = "Fast Roll Off",
728 .val = 0x80
729 }
730};
731
95c6e9cb
IM		 732enum hda_cmd_vendor_io {
733 /* for DspIO node */
734 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
735 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
736
737 VENDOR_DSPIO_STATUS = 0xF01,
738 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
739 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
740 VENDOR_DSPIO_DSP_INIT = 0x703,
741 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
742 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
743
744 /* for ChipIO node */
745 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
746 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
747 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
748 VENDOR_CHIPIO_DATA_LOW = 0x300,
749 VENDOR_CHIPIO_DATA_HIGH = 0x400,
750
bf85a91c
CM		 751 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
752 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
753
95c6e9cb
IM		 754 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
755 VENDOR_CHIPIO_STATUS = 0xF01,
756 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
757 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
758
4aa3bb0c
IM		 759 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
760 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
bf85a91c
CM		 761 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
762 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
763 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
4aa3bb0c 764
95c6e9cb 765 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 766 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 767
768 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
769 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
770 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
771 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
772 VENDOR_CHIPIO_FLAG_SET = 0x70F,
773 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 774 VENDOR_CHIPIO_PARAM_SET = 0x710,
775 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 776
777 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
778 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
779 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
780 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
781
4aa3bb0c
IM		 782 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
783 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
784 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
785 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
786
787 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
788 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
789 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
790 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
791 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
792 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
793
794 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 795};
796
797/*
798 * Control flag IDs
799 */
800enum control_flag_id {
801 /* Connection manager stream setup is bypassed/enabled */
802 CONTROL_FLAG_C_MGR = 0,
803 /* DSP DMA is bypassed/enabled */
804 CONTROL_FLAG_DMA = 1,
805 /* 8051 'idle' mode is disabled/enabled */
806 CONTROL_FLAG_IDLE_ENABLE = 2,
807 /* Tracker for the SPDIF-in path is bypassed/enabled */
808 CONTROL_FLAG_TRACKER = 3,
809 /* DigitalOut to Spdif2Out connection is disabled/enabled */
810 CONTROL_FLAG_SPDIF2OUT = 4,
811 /* Digital Microphone is disabled/enabled */
812 CONTROL_FLAG_DMIC = 5,
813 /* ADC_B rate is 48 kHz/96 kHz */
814 CONTROL_FLAG_ADC_B_96KHZ = 6,
815 /* ADC_C rate is 48 kHz/96 kHz */
816 CONTROL_FLAG_ADC_C_96KHZ = 7,
817 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
818 CONTROL_FLAG_DAC_96KHZ = 8,
819 /* DSP rate is 48 kHz/96 kHz */
820 CONTROL_FLAG_DSP_96KHZ = 9,
821 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
822 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
823 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
824 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
825 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
826 CONTROL_FLAG_DECODE_LOOP = 12,
827 /* De-emphasis filter on DAC-1 disabled/enabled */
828 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
829 /* De-emphasis filter on DAC-2 disabled/enabled */
830 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
831 /* De-emphasis filter on DAC-3 disabled/enabled */
832 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
833 /* High-pass filter on ADC_B disabled/enabled */
834 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
835 /* High-pass filter on ADC_C disabled/enabled */
836 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
837 /* Common mode on Port_A disabled/enabled */
838 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
839 /* Common mode on Port_D disabled/enabled */
840 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
841 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
842 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
843 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 844 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 845 /* ASI rate is 48kHz/96kHz */
846 CONTROL_FLAG_ASI_96KHZ = 22,
847 /* DAC power settings able to control attached ports no/yes */
848 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
849 /* Clock Stop OK reporting is disabled/enabled */
850 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
851 /* Number of control flags */
852 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
853};
854
855/*
856 * Control parameter IDs
857 */
4aa3bb0c 858enum control_param_id {
ef6b2ead
IM		 859 /* 0: None, 1: Mic1In*/
860 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 861 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
862 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 863 /* Port A output stage gain setting to use when 16 Ohm output
864 * impedance is selected*/
865 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
866 /* Port D output stage gain setting to use when 16 Ohm output
867 * impedance is selected*/
868 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb 869
bf85a91c
CM		 870 /*
871 * This control param name was found in the 8051 memory, and makes
872 * sense given the fact the AE-5 uses it and has the ASI flag set.
873 */
874 CONTROL_PARAM_ASI = 23,
875
95c6e9cb
IM		 876 /* Stream Control */
877
878 /* Select stream with the given ID */
879 CONTROL_PARAM_STREAM_ID = 24,
880 /* Source connection point for the selected stream */
881 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
882 /* Destination connection point for the selected stream */
883 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
884 /* Number of audio channels in the selected stream */
885 CONTROL_PARAM_STREAMS_CHANNELS = 27,
886 /*Enable control for the selected stream */
887 CONTROL_PARAM_STREAM_CONTROL = 28,
888
889 /* Connection Point Control */
890
891 /* Select connection point with the given ID */
892 CONTROL_PARAM_CONN_POINT_ID = 29,
893 /* Connection point sample rate */
894 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
895
896 /* Node Control */
897
898 /* Select HDA node with the given ID */
899 CONTROL_PARAM_NODE_ID = 31
900};
901
902/*
903 * Dsp Io Status codes
904 */
905enum hda_vendor_status_dspio {
906 /* Success */
907 VENDOR_STATUS_DSPIO_OK = 0x00,
908 /* Busy, unable to accept new command, the host must retry */
909 VENDOR_STATUS_DSPIO_BUSY = 0x01,
910 /* SCP command queue is full */
911 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
912 /* SCP response queue is empty */
913 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
914};
915
916/*
917 * Chip Io Status codes
918 */
919enum hda_vendor_status_chipio {
920 /* Success */
921 VENDOR_STATUS_CHIPIO_OK = 0x00,
922 /* Busy, unable to accept new command, the host must retry */
923 VENDOR_STATUS_CHIPIO_BUSY = 0x01
924};
925
926/*
927 * CA0132 sample rate
928 */
929enum ca0132_sample_rate {
930 SR_6_000 = 0x00,
931 SR_8_000 = 0x01,
932 SR_9_600 = 0x02,
933 SR_11_025 = 0x03,
934 SR_16_000 = 0x04,
935 SR_22_050 = 0x05,
936 SR_24_000 = 0x06,
937 SR_32_000 = 0x07,
938 SR_44_100 = 0x08,
939 SR_48_000 = 0x09,
940 SR_88_200 = 0x0A,
941 SR_96_000 = 0x0B,
942 SR_144_000 = 0x0C,
943 SR_176_400 = 0x0D,
944 SR_192_000 = 0x0E,
945 SR_384_000 = 0x0F,
946
947 SR_COUNT = 0x10,
948
949 SR_RATE_UNKNOWN = 0x1F
950};
951
01ef7dbf
IM		 952enum dsp_download_state {
953 DSP_DOWNLOAD_FAILED = -1,
954 DSP_DOWNLOAD_INIT = 0,
955 DSP_DOWNLOADING = 1,
956 DSP_DOWNLOADED = 2
957};
958
01ef7dbf
IM		 959/* retrieve parameters from hda format */
960#define get_hdafmt_chs(fmt) (fmt & 0xf)
961#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
962#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
963#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
964
965/*
966 * CA0132 specific
967 */
968
969struct ca0132_spec {
b0eaa072 970 const struct snd_kcontrol_new *mixers[5];
a7e76271 971 unsigned int num_mixers;
5aaca44d
IM		 972 const struct hda_verb *base_init_verbs;
973 const struct hda_verb *base_exit_verbs;
d5c016b5 974 const struct hda_verb *chip_init_verbs;
e42c7c73 975 const struct hda_verb *desktop_init_verbs;
d5c016b5 976 struct hda_verb *spec_init_verbs;
01ef7dbf 977 struct auto_pin_cfg autocfg;
5aaca44d
IM		 978
979 /* Nodes configurations */
01ef7dbf
IM		 980 struct hda_multi_out multiout;
981 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
982 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 983 unsigned int num_outputs;
01ef7dbf
IM		 984 hda_nid_t input_pins[AUTO_PIN_LAST];
985 hda_nid_t adcs[AUTO_PIN_LAST];
986 hda_nid_t dig_out;
987 hda_nid_t dig_in;
988 unsigned int num_inputs;
a7e76271
IM		 989 hda_nid_t shared_mic_nid;
990 hda_nid_t shared_out_nid;
d5c016b5 991 hda_nid_t unsol_tag_hp;
63177afc 992 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 993 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 994
995 /* chip access */
996 struct mutex chipio_mutex; /* chip access mutex */
997 u32 curr_chip_addx;
998
999 /* DSP download related */
1000 enum dsp_download_state dsp_state;
1001 unsigned int dsp_stream_id;
1002 unsigned int wait_scp;
1003 unsigned int wait_scp_header;
1004 unsigned int wait_num_data;
1005 unsigned int scp_resp_header;
1006 unsigned int scp_resp_data[4];
1007 unsigned int scp_resp_count;
38ba69ff 1008 bool startup_check_entered;
e93ac30a 1009 bool dsp_reload;
5aaca44d
IM		 1010
1011 /* mixer and effects related */
1012 unsigned char dmic_ctl;
1013 int cur_out_type;
1014 int cur_mic_type;
1015 long vnode_lvol[VNODES_COUNT];
1016 long vnode_rvol[VNODES_COUNT];
1017 long vnode_lswitch[VNODES_COUNT];
1018 long vnode_rswitch[VNODES_COUNT];
1019 long effects_switch[EFFECTS_COUNT];
1020 long voicefx_val;
1021 long cur_mic_boost;
7cb9d94c
CM		 1022 /* ca0132_alt control related values */
1023 unsigned char in_enum_val;
1024 unsigned char out_enum_val;
47cdf76e
CM		 1025 unsigned char mic_boost_enum_val;
1026 unsigned char smart_volume_setting;
1027 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1028 long xbass_xover_freq;
1029 long eq_preset_val;
1030 unsigned int tlv[4];
1031 struct hda_vmaster_mute_hook vmaster_mute;
212de2e7
CM		 1032 /* AE-5 Control values */
1033 unsigned char ae5_headphone_gain_val;
1034 unsigned char ae5_filter_val;
d51434d4
CM		 1035 /* ZxR Control Values */
1036 unsigned char zxr_gain_set;
44f0c978 1037
993884f6
CCC		 1038 struct hda_codec *codec;
1039 struct delayed_work unsol_hp_work;
d5c016b5 1040 int quirk;
993884f6 1041
44f0c978
IM		 1042#ifdef ENABLE_TUNING_CONTROLS
1043 long cur_ctl_vals[TUNING_CTLS_COUNT];
1044#endif
aa31704f 1045 /*
08eca6b1
CM		 1046 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1047 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1048 * things.
aa31704f 1049 */
08eca6b1 1050 bool use_pci_mmio;
aa31704f 1051 void __iomem *mem_base;
009b8f97
CM		 1052
1053 /*
1054 * Whether or not to use the alt functions like alt_select_out,
1055 * alt_select_in, etc. Only used on desktop codecs for now, because of
1056 * surround sound support.
1057 */
1058 bool use_alt_functions;
47cdf76e
CM		 1059
1060 /*
1061 * Whether or not to use alt controls: volume effect sliders, EQ
1062 * presets, smart volume presets, and new control names with FX prefix.
1063 * Renames PlayEnhancement and CrystalVoice too.
1064 */
1065 bool use_alt_controls;
01ef7dbf
IM		 1066};
1067
d5c016b5
GM		 1068/*
1069 * CA0132 quirks table
1070 */
1071enum {
1072 QUIRK_NONE,
1073 QUIRK_ALIENWARE,
a57a46b9 1074 QUIRK_ALIENWARE_M17XR4,
8a19bcee 1075 QUIRK_SBZ,
b29733db
CM		 1076 QUIRK_ZXR,
1077 QUIRK_ZXR_DBPRO,
8a19bcee 1078 QUIRK_R3DI,
8f8c523c 1079 QUIRK_R3D,
f6276463 1080 QUIRK_AE5,
d5c016b5
GM		 1081};
1082
6da8f446
TI		 1083#ifdef CONFIG_PCI
1084#define ca0132_quirk(spec) ((spec)->quirk)
1085#define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1086#define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1087#define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1088#else
1089#define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
1090#define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
1091#define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
1092#define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
1093#endif
1094
fe14f39e
TI		 1095static const struct hda_pintbl alienware_pincfgs[] = {
1096 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1097 { 0x0c, 0x411111f0 }, /* N/A */
1098 { 0x0d, 0x411111f0 }, /* N/A */
1099 { 0x0e, 0x411111f0 }, /* N/A */
1100 { 0x0f, 0x0321101f }, /* HP */
1101 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1102 { 0x11, 0x03a11021 }, /* Mic */
1103 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1104 { 0x13, 0x411111f0 }, /* N/A */
1105 { 0x18, 0x411111f0 }, /* N/A */
1106 {}
1107};
1108
63177afc
CM		 1109/* Sound Blaster Z pin configs taken from Windows Driver */
1110static const struct hda_pintbl sbz_pincfgs[] = {
1111 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1112 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1113 { 0x0d, 0x014510f0 }, /* Digital Out */
1114 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1115 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1116 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1117 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1118 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1119 { 0x13, 0x908700f0 }, /* What U Hear In*/
1120 { 0x18, 0x50d000f0 }, /* N/A */
1121 {}
1122};
1123
6dcd7244
CM		 1124/* Sound Blaster ZxR pin configs taken from Windows Driver */
1125static const struct hda_pintbl zxr_pincfgs[] = {
1126 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1127 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1128 { 0x0d, 0x014510f0 }, /* Digital Out */
1129 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1130 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1131 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1132 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1133 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1134 { 0x13, 0x908700f0 }, /* What U Hear In*/
1135 { 0x18, 0x50d000f0 }, /* N/A */
1136 {}
1137};
1138
7f73df95
CM		 1139/* Recon3D pin configs taken from Windows Driver */
1140static const struct hda_pintbl r3d_pincfgs[] = {
1141 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1142 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1143 { 0x0d, 0x014510f0 }, /* Digital Out */
1144 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1145 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1146 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1147 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1148 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1149 { 0x13, 0x908700f0 }, /* What U Hear In*/
1150 { 0x18, 0x50d000f0 }, /* N/A */
1151 {}
1152};
1153
d06feaf0
CM		 1154/* Sound Blaster AE-5 pin configs taken from Windows Driver */
1155static const struct hda_pintbl ae5_pincfgs[] = {
1156 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1157 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1158 { 0x0d, 0x014510f0 }, /* Digital Out */
1159 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1160 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1161 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1162 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1163 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1164 { 0x13, 0x908700f0 }, /* What U Hear In*/
1165 { 0x18, 0x50d000f0 }, /* N/A */
1166 {}
1167};
1168
63177afc
CM		 1169/* Recon3D integrated pin configs taken from Windows Driver */
1170static const struct hda_pintbl r3di_pincfgs[] = {
1171 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1172 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1173 { 0x0d, 0x014510f0 }, /* Digital Out */
1174 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1175 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1176 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1177 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1178 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1179 { 0x13, 0x908700f0 }, /* What U Hear In*/
1180 { 0x18, 0x500000f0 }, /* N/A */
1181 {}
1182};
1183
d5c016b5 1184static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1185 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1186 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1187 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1188 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1189 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1190 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
cce99729 1191 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
8a19bcee 1192 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1193 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1194 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
8f8c523c 1195 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
f6276463 1196 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
d5c016b5
GM		 1197 {}
1198};
1199
01ef7dbf
IM		 1200/*
1201 * CA0132 codec access
1202 */
399ae725 1203static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1204 unsigned int verb, unsigned int parm, unsigned int *res)
1205{
1206 unsigned int response;
1207 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1208 *res = response;
1209
1210 return ((response == -1) ? -1 : 0);
1211}
1212
1213static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1214 unsigned short converter_format, unsigned int *res)
1215{
1216 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1217 converter_format & 0xffff, res);
1218}
1219
1220static int codec_set_converter_stream_channel(struct hda_codec *codec,
1221 hda_nid_t nid, unsigned char stream,
1222 unsigned char channel, unsigned int *res)
1223{
1224 unsigned char converter_stream_channel = 0;
1225
1226 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1227 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1228 converter_stream_channel, res);
1229}
1230
1231/* Chip access helper function */
1232static int chipio_send(struct hda_codec *codec,
1233 unsigned int reg,
1234 unsigned int data)
1235{
1236 unsigned int res;
6d67530e 1237 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1238
1239 /* send bits of data specified by reg */
1240 do {
1241 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1242 reg, data);
1243 if (res == VENDOR_STATUS_CHIPIO_OK)
1244 return 0;
6d67530e
IM		 1245 msleep(20);
1246 } while (time_before(jiffies, timeout));
1247
01ef7dbf
IM		 1248 return -EIO;
1249}
1250
1251/*
1252 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1253 */
1254static int chipio_write_address(struct hda_codec *codec,
1255 unsigned int chip_addx)
1256{
4861af80 1257 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1258 int res;
1259
4861af80
IM		 1260 if (spec->curr_chip_addx == chip_addx)
1261 return 0;
1262
01ef7dbf
IM		 1263 /* send low 16 bits of the address */
1264 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1265 chip_addx & 0xffff);
1266
1267 if (res != -EIO) {
1268 /* send high 16 bits of the address */
1269 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1270 chip_addx >> 16);
1271 }
1272
d1600401 1273 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1274
4861af80 1275 return res;
01ef7dbf
IM		 1276}
1277
1278/*
1279 * Write data through the vendor widget -- NOT protected by the Mutex!
1280 */
01ef7dbf
IM		 1281static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1282{
5aaca44d 1283 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1284 int res;
1285
1286 /* send low 16 bits of the data */
1287 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1288
1289 if (res != -EIO) {
1290 /* send high 16 bits of the data */
1291 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1292 data >> 16);
1293 }
1294
5aaca44d
IM		 1295 /*If no error encountered, automatically increment the address
1296 as per chip behaviour*/
1297 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1298 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1299 return res;
1300}
1301
d5c21b88
IM		 1302/*
1303 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1304 */
01ef7dbf
IM		 1305static int chipio_write_data_multiple(struct hda_codec *codec,
1306 const u32 *data,
1307 unsigned int count)
1308{
1309 int status = 0;
1310
1311 if (data == NULL) {
4e76a883 1312 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1313 return -EINVAL;
1314 }
1315
1316 while ((count-- != 0) && (status == 0))
1317 status = chipio_write_data(codec, *data++);
1318
1319 return status;
1320}
1321
1322
1323/*
1324 * Read data through the vendor widget -- NOT protected by the Mutex!
1325 */
1326static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1327{
5aaca44d 1328 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1329 int res;
1330
1331 /* post read */
1332 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1333
1334 if (res != -EIO) {
1335 /* read status */
1336 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1337 }
1338
1339 if (res != -EIO) {
1340 /* read data */
1341 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1342 VENDOR_CHIPIO_HIC_READ_DATA,
1343 0);
1344 }
1345
5aaca44d
IM		 1346 /*If no error encountered, automatically increment the address
1347 as per chip behaviour*/
1348 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1349 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1350 return res;
1351}
1352
1353/*
1354 * Write given value to the given address through the chip I/O widget.
1355 * protected by the Mutex
1356 */
1357static int chipio_write(struct hda_codec *codec,
1358 unsigned int chip_addx, const unsigned int data)
1359{
1360 struct ca0132_spec *spec = codec->spec;
1361 int err;
1362
1363 mutex_lock(&spec->chipio_mutex);
1364
1365 /* write the address, and if successful proceed to write data */
1366 err = chipio_write_address(codec, chip_addx);
1367 if (err < 0)
1368 goto exit;
1369
1370 err = chipio_write_data(codec, data);
1371 if (err < 0)
1372 goto exit;
1373
1374exit:
1375 mutex_unlock(&spec->chipio_mutex);
1376 return err;
1377}
1378
38ba69ff
CM		 1379/*
1380 * Write given value to the given address through the chip I/O widget.
1381 * not protected by the Mutex
1382 */
1383static int chipio_write_no_mutex(struct hda_codec *codec,
1384 unsigned int chip_addx, const unsigned int data)
1385{
1386 int err;
1387
1388
1389 /* write the address, and if successful proceed to write data */
1390 err = chipio_write_address(codec, chip_addx);
1391 if (err < 0)
1392 goto exit;
1393
1394 err = chipio_write_data(codec, data);
1395 if (err < 0)
1396 goto exit;
1397
1398exit:
1399 return err;
1400}
1401
d5c21b88
IM		 1402/*
1403 * Write multiple values to the given address through the chip I/O widget.
1404 * protected by the Mutex
1405 */
01ef7dbf
IM		 1406static int chipio_write_multiple(struct hda_codec *codec,
1407 u32 chip_addx,
1408 const u32 *data,
1409 unsigned int count)
1410{
1411 struct ca0132_spec *spec = codec->spec;
1412 int status;
1413
1414 mutex_lock(&spec->chipio_mutex);
4861af80 1415 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1416 if (status < 0)
1417 goto error;
1418
1419 status = chipio_write_data_multiple(codec, data, count);
1420error:
1421 mutex_unlock(&spec->chipio_mutex);
1422
1423 return status;
1424}
1425
1426/*
1427 * Read the given address through the chip I/O widget
1428 * protected by the Mutex
1429 */
1430static int chipio_read(struct hda_codec *codec,
1431 unsigned int chip_addx, unsigned int *data)
1432{
1433 struct ca0132_spec *spec = codec->spec;
1434 int err;
1435
1436 mutex_lock(&spec->chipio_mutex);
1437
1438 /* write the address, and if successful proceed to write data */
1439 err = chipio_write_address(codec, chip_addx);
1440 if (err < 0)
1441 goto exit;
1442
1443 err = chipio_read_data(codec, data);
1444 if (err < 0)
1445 goto exit;
1446
1447exit:
1448 mutex_unlock(&spec->chipio_mutex);
1449 return err;
1450}
1451
d5c21b88
IM		 1452/*
1453 * Set chip control flags through the chip I/O widget.
1454 */
01ef7dbf
IM		 1455static void chipio_set_control_flag(struct hda_codec *codec,
1456 enum control_flag_id flag_id,
1457 bool flag_state)
1458{
1459 unsigned int val;
1460 unsigned int flag_bit;
1461
1462 flag_bit = (flag_state ? 1 : 0);
1463 val = (flag_bit << 7) | (flag_id);
1464 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1465 VENDOR_CHIPIO_FLAG_SET, val);
1466}
1467
d5c21b88
IM		 1468/*
1469 * Set chip parameters through the chip I/O widget.
1470 */
01ef7dbf
IM		 1471static void chipio_set_control_param(struct hda_codec *codec,
1472 enum control_param_id param_id, int param_val)
1473{
1474 struct ca0132_spec *spec = codec->spec;
1475 int val;
1476
1477 if ((param_id < 32) && (param_val < 8)) {
1478 val = (param_val << 5) | (param_id);
1479 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1480 VENDOR_CHIPIO_PARAM_SET, val);
1481 } else {
1482 mutex_lock(&spec->chipio_mutex);
1483 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1484 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1485 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1486 param_id);
1487 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1488 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1489 param_val);
1490 }
1491 mutex_unlock(&spec->chipio_mutex);
1492 }
1493}
1494
009b8f97
CM		 1495/*
1496 * Set chip parameters through the chip I/O widget. NO MUTEX.
1497 */
1498static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1499 enum control_param_id param_id, int param_val)
1500{
1501 int val;
1502
1503 if ((param_id < 32) && (param_val < 8)) {
1504 val = (param_val << 5) | (param_id);
1505 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1506 VENDOR_CHIPIO_PARAM_SET, val);
1507 } else {
1508 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1509 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1510 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1511 param_id);
1512 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1513 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1514 param_val);
1515 }
1516 }
1517}
38ba69ff
CM		 1518/*
1519 * Connect stream to a source point, and then connect
1520 * that source point to a destination point.
1521 */
1522static void chipio_set_stream_source_dest(struct hda_codec *codec,
1523 int streamid, int source_point, int dest_point)
1524{
1525 chipio_set_control_param_no_mutex(codec,
1526 CONTROL_PARAM_STREAM_ID, streamid);
1527 chipio_set_control_param_no_mutex(codec,
1528 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1529 chipio_set_control_param_no_mutex(codec,
1530 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1531}
1532
1533/*
1534 * Set number of channels in the selected stream.
1535 */
1536static void chipio_set_stream_channels(struct hda_codec *codec,
1537 int streamid, unsigned int channels)
1538{
1539 chipio_set_control_param_no_mutex(codec,
1540 CONTROL_PARAM_STREAM_ID, streamid);
1541 chipio_set_control_param_no_mutex(codec,
1542 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1543}
009b8f97
CM		 1544
1545/*
1546 * Enable/Disable audio stream.
1547 */
1548static void chipio_set_stream_control(struct hda_codec *codec,
1549 int streamid, int enable)
1550{
1551 chipio_set_control_param_no_mutex(codec,
1552 CONTROL_PARAM_STREAM_ID, streamid);
1553 chipio_set_control_param_no_mutex(codec,
1554 CONTROL_PARAM_STREAM_CONTROL, enable);
1555}
1556
38ba69ff
CM		 1557
1558/*
1559 * Set sampling rate of the connection point. NO MUTEX.
1560 */
1561static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1562 int connid, enum ca0132_sample_rate rate)
1563{
1564 chipio_set_control_param_no_mutex(codec,
1565 CONTROL_PARAM_CONN_POINT_ID, connid);
1566 chipio_set_control_param_no_mutex(codec,
1567 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1568}
1569
d5c21b88
IM		 1570/*
1571 * Set sampling rate of the connection point.
1572 */
01ef7dbf
IM		 1573static void chipio_set_conn_rate(struct hda_codec *codec,
1574 int connid, enum ca0132_sample_rate rate)
1575{
1576 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1577 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1578 rate);
1579}
1580
b9b41345
CM		 1581/*
1582 * Writes to the 8051's internal address space directly instead of indirectly,
1583 * giving access to the special function registers located at addresses
1584 * 0x80-0xFF.
1585 */
1586static void chipio_8051_write_direct(struct hda_codec *codec,
1587 unsigned int addr, unsigned int data)
1588{
1589 unsigned int verb;
1590
1591 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1592 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1593}
1594
d5c21b88
IM		 1595/*
1596 * Enable clocks.
1597 */
01ef7dbf
IM		 1598static void chipio_enable_clocks(struct hda_codec *codec)
1599{
1600 struct ca0132_spec *spec = codec->spec;
1601
1602 mutex_lock(&spec->chipio_mutex);
1603 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1604 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1605 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1606 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1607 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1608 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1609 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1610 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1611 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1612 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1613 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1614 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1615 mutex_unlock(&spec->chipio_mutex);
1616}
1617
1618/*
1619 * CA0132 DSP IO stuffs
1620 */
1621static int dspio_send(struct hda_codec *codec, unsigned int reg,
1622 unsigned int data)
1623{
b645d796 1624 int res;
6d67530e 1625 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1626
1627 /* send bits of data specified by reg to dsp */
1628 do {
1629 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1630 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1631 return res;
6d67530e
IM		 1632 msleep(20);
1633 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1634
1635 return -EIO;
1636}
1637
d5c21b88
IM		 1638/*
1639 * Wait for DSP to be ready for commands
1640 */
01ef7dbf
IM		 1641static void dspio_write_wait(struct hda_codec *codec)
1642{
4861af80
IM		 1643 int status;
1644 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1645
01ef7dbf 1646 do {
4861af80
IM		 1647 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1648 VENDOR_DSPIO_STATUS, 0);
1649 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1650 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1651 break;
1652 msleep(1);
1653 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1654}
1655
d5c21b88
IM		 1656/*
1657 * Write SCP data to DSP
1658 */
01ef7dbf
IM		 1659static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1660{
1661 struct ca0132_spec *spec = codec->spec;
1662 int status;
1663
1664 dspio_write_wait(codec);
1665
1666 mutex_lock(&spec->chipio_mutex);
1667 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1668 scp_data & 0xffff);
1669 if (status < 0)
1670 goto error;
1671
1672 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1673 scp_data >> 16);
1674 if (status < 0)
1675 goto error;
1676
1677 /* OK, now check if the write itself has executed*/
1678 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1679 VENDOR_DSPIO_STATUS, 0);
1680error:
1681 mutex_unlock(&spec->chipio_mutex);
1682
1683 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1684 -EIO : 0;
1685}
1686
d5c21b88
IM		 1687/*
1688 * Write multiple SCP data to DSP
1689 */
01ef7dbf
IM		 1690static int dspio_write_multiple(struct hda_codec *codec,
1691 unsigned int *buffer, unsigned int size)
1692{
1693 int status = 0;
1694 unsigned int count;
1695
a16fbb85 1696 if (buffer == NULL)
01ef7dbf
IM		 1697 return -EINVAL;
1698
1699 count = 0;
1700 while (count < size) {
1701 status = dspio_write(codec, *buffer++);
1702 if (status != 0)
1703 break;
1704 count++;
1705 }
1706
1707 return status;
1708}
1709
a73d511c
IM		 1710static int dspio_read(struct hda_codec *codec, unsigned int *data)
1711{
1712 int status;
1713
1714 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1715 if (status == -EIO)
1716 return status;
1717
1718 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1719 if (status == -EIO ||
1720 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1721 return -EIO;
1722
1723 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1724 VENDOR_DSPIO_SCP_READ_DATA, 0);
1725
1726 return 0;
1727}
1728
1729static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1730 unsigned int *buf_size, unsigned int size_count)
1731{
1732 int status = 0;
1733 unsigned int size = *buf_size;
1734 unsigned int count;
1735 unsigned int skip_count;
1736 unsigned int dummy;
1737
a16fbb85 1738 if (buffer == NULL)
a73d511c
IM		 1739 return -1;
1740
1741 count = 0;
1742 while (count < size && count < size_count) {
1743 status = dspio_read(codec, buffer++);
1744 if (status != 0)
1745 break;
1746 count++;
1747 }
1748
1749 skip_count = count;
1750 if (status == 0) {
1751 while (skip_count < size) {
1752 status = dspio_read(codec, &dummy);
1753 if (status != 0)
1754 break;
1755 skip_count++;
1756 }
1757 }
1758 *buf_size = count;
1759
1760 return status;
1761}
1762
d5c21b88
IM		 1763/*
1764 * Construct the SCP header using corresponding fields
1765 */
01ef7dbf
IM		 1766static inline unsigned int
1767make_scp_header(unsigned int target_id, unsigned int source_id,
1768 unsigned int get_flag, unsigned int req,
1769 unsigned int device_flag, unsigned int resp_flag,
1770 unsigned int error_flag, unsigned int data_size)
1771{
1772 unsigned int header = 0;
1773
1774 header = (data_size & 0x1f) << 27;
1775 header |= (error_flag & 0x01) << 26;
1776 header |= (resp_flag & 0x01) << 25;
1777 header |= (device_flag & 0x01) << 24;
1778 header |= (req & 0x7f) << 17;
1779 header |= (get_flag & 0x01) << 16;
1780 header |= (source_id & 0xff) << 8;
1781 header |= target_id & 0xff;
1782
1783 return header;
1784}
1785
d5c21b88
IM		 1786/*
1787 * Extract corresponding fields from SCP header
1788 */
01ef7dbf
IM		 1789static inline void
1790extract_scp_header(unsigned int header,
1791 unsigned int *target_id, unsigned int *source_id,
1792 unsigned int *get_flag, unsigned int *req,
1793 unsigned int *device_flag, unsigned int *resp_flag,
1794 unsigned int *error_flag, unsigned int *data_size)
1795{
1796 if (data_size)
1797 *data_size = (header >> 27) & 0x1f;
1798 if (error_flag)
1799 *error_flag = (header >> 26) & 0x01;
1800 if (resp_flag)
1801 *resp_flag = (header >> 25) & 0x01;
1802 if (device_flag)
1803 *device_flag = (header >> 24) & 0x01;
1804 if (req)
1805 *req = (header >> 17) & 0x7f;
1806 if (get_flag)
1807 *get_flag = (header >> 16) & 0x01;
1808 if (source_id)
1809 *source_id = (header >> 8) & 0xff;
1810 if (target_id)
1811 *target_id = header & 0xff;
1812}
1813
1814#define SCP_MAX_DATA_WORDS (16)
1815
1816/* Structure to contain any SCP message */
1817struct scp_msg {
1818 unsigned int hdr;
1819 unsigned int data[SCP_MAX_DATA_WORDS];
1820};
1821
a73d511c
IM		 1822static void dspio_clear_response_queue(struct hda_codec *codec)
1823{
1824 unsigned int dummy = 0;
1825 int status = -1;
1826
1827 /* clear all from the response queue */
1828 do {
1829 status = dspio_read(codec, &dummy);
1830 } while (status == 0);
1831}
1832
1833static int dspio_get_response_data(struct hda_codec *codec)
1834{
1835 struct ca0132_spec *spec = codec->spec;
1836 unsigned int data = 0;
1837 unsigned int count;
1838
1839 if (dspio_read(codec, &data) < 0)
1840 return -EIO;
1841
1842 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1843 spec->scp_resp_header = data;
1844 spec->scp_resp_count = data >> 27;
1845 count = spec->wait_num_data;
1846 dspio_read_multiple(codec, spec->scp_resp_data,
1847 &spec->scp_resp_count, count);
1848 return 0;
1849 }
1850
1851 return -EIO;
1852}
1853
d5c21b88
IM		 1854/*
1855 * Send SCP message to DSP
1856 */
01ef7dbf
IM		 1857static int dspio_send_scp_message(struct hda_codec *codec,
1858 unsigned char *send_buf,
1859 unsigned int send_buf_size,
1860 unsigned char *return_buf,
1861 unsigned int return_buf_size,
1862 unsigned int *bytes_returned)
1863{
1864 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1865 int status = -1;
1866 unsigned int scp_send_size = 0;
1867 unsigned int total_size;
1868 bool waiting_for_resp = false;
1869 unsigned int header;
1870 struct scp_msg *ret_msg;
1871 unsigned int resp_src_id, resp_target_id;
1872 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1873
1874 if (bytes_returned)
1875 *bytes_returned = 0;
1876
1877 /* get scp header from buffer */
1878 header = *((unsigned int *)send_buf);
1879 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1880 &device_flag, NULL, NULL, &data_size);
1881 scp_send_size = data_size + 1;
1882 total_size = (scp_send_size * 4);
1883
1884 if (send_buf_size < total_size)
1885 return -EINVAL;
1886
1887 if (get_flag || device_flag) {
1888 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1889 return -EINVAL;
1890
1891 spec->wait_scp_header = *((unsigned int *)send_buf);
1892
1893 /* swap source id with target id */
1894 resp_target_id = src_id;
1895 resp_src_id = target_id;
1896 spec->wait_scp_header &= 0xffff0000;
1897 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1898 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1899 spec->wait_scp = 1;
1900 waiting_for_resp = true;
1901 }
1902
1903 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1904 scp_send_size);
1905 if (status < 0) {
1906 spec->wait_scp = 0;
1907 return status;
1908 }
1909
1910 if (waiting_for_resp) {
6d67530e 1911 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1912 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1913 do {
1914 msleep(20);
6d67530e 1915 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1916 waiting_for_resp = false;
6d67530e 1917 if (!spec->wait_scp) {
01ef7dbf
IM		 1918 ret_msg = (struct scp_msg *)return_buf;
1919 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1920 memcpy(&ret_msg->data, spec->scp_resp_data,
1921 spec->wait_num_data);
1922 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1923 status = 0;
1924 } else {
1925 status = -EIO;
1926 }
1927 spec->wait_scp = 0;
1928 }
1929
1930 return status;
1931}
1932
d5c21b88
IM		 1933/**
1934 * Prepare and send the SCP message to DSP
1935 * @codec: the HDA codec
1936 * @mod_id: ID of the DSP module to send the command
1937 * @req: ID of request to send to the DSP module
1938 * @dir: SET or GET
1939 * @data: pointer to the data to send with the request, request specific
1940 * @len: length of the data, in bytes
1941 * @reply: point to the buffer to hold data returned for a reply
1942 * @reply_len: length of the reply buffer returned from GET
1943 *
1944 * Returns zero or a negative error code.
1945 */
01ef7dbf 1946static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1947 int mod_id, int src_id, int req, int dir, const void *data,
1948 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1949{
1950 int status = 0;
1951 struct scp_msg scp_send, scp_reply;
1952 unsigned int ret_bytes, send_size, ret_size;
1953 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1954 unsigned int reply_data_size;
1955
1956 memset(&scp_send, 0, sizeof(scp_send));
1957 memset(&scp_reply, 0, sizeof(scp_reply));
1958
1959 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1960 return -EINVAL;
1961
1962 if (dir == SCP_GET && reply == NULL) {
4e76a883 1963 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1964 return -EINVAL;
1965 }
1966
1967 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1968 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1969 return -EINVAL;
1970 }
1971
447fd8e9 1972 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1973 0, 0, 0, len/sizeof(unsigned int));
1974 if (data != NULL && len > 0) {
1975 len = min((unsigned int)(sizeof(scp_send.data)), len);
1976 memcpy(scp_send.data, data, len);
1977 }
1978
1979 ret_bytes = 0;
1980 send_size = sizeof(unsigned int) + len;
1981 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1982 send_size, (unsigned char *)&scp_reply,
1983 sizeof(scp_reply), &ret_bytes);
1984
1985 if (status < 0) {
4e76a883 1986 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1987 return status;
1988 }
1989
1990 /* extract send and reply headers members */
1991 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1992 NULL, NULL, NULL, NULL, NULL);
1993 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1994 &reply_resp_flag, &reply_error_flag,
1995 &reply_data_size);
1996
1997 if (!send_get_flag)
1998 return 0;
1999
2000 if (reply_resp_flag && !reply_error_flag) {
2001 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2002 / sizeof(unsigned int);
2003
2004 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 2005 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 2006 return -EINVAL;
2007 } else if (ret_size != reply_data_size) {
4e76a883 2008 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 2009 return -EINVAL;
46a049da
AB		 2010 } else if (!reply) {
2011 codec_dbg(codec, "NULL reply\n");
2012 return -EINVAL;
01ef7dbf
IM		 2013 } else {
2014 *reply_len = ret_size*sizeof(unsigned int);
2015 memcpy(reply, scp_reply.data, *reply_len);
2016 }
2017 } else {
4e76a883 2018 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 2019 return -EIO;
2020 }
2021
2022 return status;
2023}
2024
5aaca44d
IM		 2025/*
2026 * Set DSP parameters
2027 */
2028static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 2029 int src_id, int req, const void *data, unsigned int len)
5aaca44d 2030{
447fd8e9
CM		 2031 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2032 NULL);
5aaca44d
IM		 2033}
2034
2035static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 2036 int req, const unsigned int data)
5aaca44d 2037{
447fd8e9
CM		 2038 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2039 sizeof(unsigned int));
2040}
2041
2042static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2043 int req, const unsigned int data)
2044{
2045 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2046 sizeof(unsigned int));
5aaca44d
IM		 2047}
2048
d5c21b88
IM		 2049/*
2050 * Allocate a DSP DMA channel via an SCP message
2051 */
01ef7dbf
IM		 2052static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2053{
2054 int status = 0;
2055 unsigned int size = sizeof(dma_chan);
2056
4e76a883 2057 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 2058 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2059 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2060 dma_chan, &size);
01ef7dbf
IM		 2061
2062 if (status < 0) {
4e76a883 2063 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2064 return status;
2065 }
2066
2067 if ((*dma_chan + 1) == 0) {
4e76a883 2068 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 2069 return -EBUSY;
2070 }
2071
4e76a883
TI		 2072 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2073 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 2074
2075 return status;
2076}
2077
d5c21b88
IM		 2078/*
2079 * Free a DSP DMA via an SCP message
2080 */
01ef7dbf
IM		 2081static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2082{
2083 int status = 0;
2084 unsigned int dummy = 0;
2085
4e76a883
TI		 2086 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2087 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 2088
447fd8e9
CM		 2089 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2090 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2091 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 2092
2093 if (status < 0) {
4e76a883 2094 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2095 return status;
2096 }
2097
4e76a883 2098 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 2099
2100 return status;
2101}
2102
2103/*
d5c21b88 2104 * (Re)start the DSP
01ef7dbf
IM		 2105 */
2106static int dsp_set_run_state(struct hda_codec *codec)
2107{
2108 unsigned int dbg_ctrl_reg;
2109 unsigned int halt_state;
2110 int err;
2111
2112 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2113 if (err < 0)
2114 return err;
2115
2116 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2117 DSP_DBGCNTL_STATE_LOBIT;
2118
2119 if (halt_state != 0) {
2120 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2121 DSP_DBGCNTL_SS_MASK);
2122 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2123 dbg_ctrl_reg);
2124 if (err < 0)
2125 return err;
2126
2127 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2128 DSP_DBGCNTL_EXEC_MASK;
2129 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2130 dbg_ctrl_reg);
2131 if (err < 0)
2132 return err;
2133 }
2134
2135 return 0;
2136}
2137
d5c21b88
IM		 2138/*
2139 * Reset the DSP
2140 */
01ef7dbf
IM		 2141static int dsp_reset(struct hda_codec *codec)
2142{
2143 unsigned int res;
2144 int retry = 20;
2145
4e76a883 2146 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 2147 do {
2148 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2149 retry--;
2150 } while (res == -EIO && retry);
2151
2152 if (!retry) {
4e76a883 2153 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 2154 return -EIO;
2155 }
2156
2157 return 0;
2158}
2159
d5c21b88
IM		 2160/*
2161 * Convert chip address to DSP address
2162 */
01ef7dbf
IM		 2163static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2164 bool *code, bool *yram)
2165{
2166 *code = *yram = false;
2167
2168 if (UC_RANGE(chip_addx, 1)) {
2169 *code = true;
2170 return UC_OFF(chip_addx);
2171 } else if (X_RANGE_ALL(chip_addx, 1)) {
2172 return X_OFF(chip_addx);
2173 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2174 *yram = true;
2175 return Y_OFF(chip_addx);
2176 }
2177
4a8b89f9 2178 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2179}
2180
d5c21b88
IM		 2181/*
2182 * Check if the DSP DMA is active
2183 */
01ef7dbf
IM		 2184static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2185{
2186 unsigned int dma_chnlstart_reg;
2187
2188 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2189
2190 return ((dma_chnlstart_reg & (1 <<
2191 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2192}
2193
2194static int dsp_dma_setup_common(struct hda_codec *codec,
2195 unsigned int chip_addx,
2196 unsigned int dma_chan,
2197 unsigned int port_map_mask,
2198 bool ovly)
2199{
2200 int status = 0;
2201 unsigned int chnl_prop;
2202 unsigned int dsp_addx;
2203 unsigned int active;
2204 bool code, yram;
2205
4e76a883 2206 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2207
2208 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2209 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2210 return -EINVAL;
2211 }
2212
2213 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2214 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2215 return -EBUSY;
2216 }
2217
2218 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2219
2220 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2221 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2222 return -ENXIO;
2223 }
2224
2225 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2226 active = 0;
2227
4e76a883 2228 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2229
2230 if (ovly) {
2231 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2232 &chnl_prop);
2233
2234 if (status < 0) {
4e76a883 2235 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2236 return status;
2237 }
4e76a883 2238 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2239 }
2240
2241 if (!code)
2242 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2243 else
2244 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2245
2246 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2247
2248 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2249 if (status < 0) {
4e76a883 2250 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2251 return status;
2252 }
4e76a883 2253 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2254
2255 if (ovly) {
2256 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2257 &active);
2258
2259 if (status < 0) {
4e76a883 2260 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2261 return status;
2262 }
4e76a883 2263 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2264 }
2265
2266 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2267 DSPDMAC_ACTIVE_AAR_MASK;
2268
2269 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2270 if (status < 0) {
4e76a883 2271 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2272 return status;
2273 }
2274
4e76a883 2275 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2276
2277 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2278 port_map_mask);
2279 if (status < 0) {
4e76a883 2280 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2281 return status;
2282 }
4e76a883 2283 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2284
2285 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2286 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2287 if (status < 0) {
4e76a883 2288 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2289 return status;
2290 }
4e76a883 2291 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2292
4e76a883 2293 codec_dbg(codec,
01ef7dbf
IM		 2294 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2295 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2296 chip_addx, dsp_addx, dma_chan,
2297 port_map_mask, chnl_prop, active);
2298
4e76a883 2299 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2300
2301 return 0;
2302}
2303
d5c21b88
IM		 2304/*
2305 * Setup the DSP DMA per-transfer-specific registers
2306 */
01ef7dbf
IM		 2307static int dsp_dma_setup(struct hda_codec *codec,
2308 unsigned int chip_addx,
2309 unsigned int count,
2310 unsigned int dma_chan)
2311{
2312 int status = 0;
2313 bool code, yram;
2314 unsigned int dsp_addx;
2315 unsigned int addr_field;
2316 unsigned int incr_field;
2317 unsigned int base_cnt;
2318 unsigned int cur_cnt;
2319 unsigned int dma_cfg = 0;
2320 unsigned int adr_ofs = 0;
2321 unsigned int xfr_cnt = 0;
2322 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2323 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2324
4e76a883 2325 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2326
2327 if (count > max_dma_count) {
4e76a883 2328 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2329 return -EINVAL;
2330 }
2331
2332 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2333 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2334 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2335 return -ENXIO;
2336 }
2337
4e76a883 2338 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2339
2340 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2341 incr_field = 0;
2342
2343 if (!code) {
2344 addr_field <<= 1;
2345 if (yram)
2346 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2347
2348 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2349 }
2350
2351 dma_cfg = addr_field + incr_field;
2352 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2353 dma_cfg);
2354 if (status < 0) {
4e76a883 2355 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2356 return status;
2357 }
4e76a883 2358 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2359
2360 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2361 (code ? 0 : 1));
2362
2363 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2364 adr_ofs);
2365 if (status < 0) {
4e76a883 2366 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2367 return status;
2368 }
4e76a883 2369 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2370
2371 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2372
2373 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2374
2375 xfr_cnt = base_cnt | cur_cnt;
2376
2377 status = chipio_write(codec,
2378 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2379 if (status < 0) {
4e76a883 2380 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2381 return status;
2382 }
4e76a883 2383 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2384
4e76a883 2385 codec_dbg(codec,
01ef7dbf
IM		 2386 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2387 "ADROFS=0x%x, XFRCNT=0x%x\n",
2388 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2389
4e76a883 2390 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2391
2392 return 0;
2393}
2394
d5c21b88
IM		 2395/*
2396 * Start the DSP DMA
2397 */
01ef7dbf
IM		 2398static int dsp_dma_start(struct hda_codec *codec,
2399 unsigned int dma_chan, bool ovly)
2400{
2401 unsigned int reg = 0;
2402 int status = 0;
2403
4e76a883 2404 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2405
2406 if (ovly) {
2407 status = chipio_read(codec,
2408 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2409
2410 if (status < 0) {
4e76a883 2411 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2412 return status;
2413 }
4e76a883 2414 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2415
2416 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2417 DSPDMAC_CHNLSTART_DIS_MASK);
2418 }
2419
2420 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2421 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2422 if (status < 0) {
4e76a883 2423 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2424 return status;
2425 }
4e76a883 2426 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2427
2428 return status;
2429}
2430
d5c21b88
IM		 2431/*
2432 * Stop the DSP DMA
2433 */
01ef7dbf
IM		 2434static int dsp_dma_stop(struct hda_codec *codec,
2435 unsigned int dma_chan, bool ovly)
2436{
2437 unsigned int reg = 0;
2438 int status = 0;
2439
4e76a883 2440 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2441
2442 if (ovly) {
2443 status = chipio_read(codec,
2444 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2445
2446 if (status < 0) {
4e76a883 2447 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2448 return status;
2449 }
4e76a883 2450 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2451 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2452 DSPDMAC_CHNLSTART_DIS_MASK);
2453 }
2454
2455 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2456 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2457 if (status < 0) {
4e76a883 2458 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2459 return status;
2460 }
4e76a883 2461 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2462
2463 return status;
2464}
2465
d5c21b88
IM		 2466/**
2467 * Allocate router ports
2468 *
2469 * @codec: the HDA codec
2470 * @num_chans: number of channels in the stream
2471 * @ports_per_channel: number of ports per channel
2472 * @start_device: start device
2473 * @port_map: pointer to the port list to hold the allocated ports
2474 *
2475 * Returns zero or a negative error code.
2476 */
01ef7dbf
IM		 2477static int dsp_allocate_router_ports(struct hda_codec *codec,
2478 unsigned int num_chans,
2479 unsigned int ports_per_channel,
2480 unsigned int start_device,
2481 unsigned int *port_map)
2482{
2483 int status = 0;
2484 int res;
2485 u8 val;
2486
2487 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2488 if (status < 0)
2489 return status;
2490
2491 val = start_device << 6;
2492 val |= (ports_per_channel - 1) << 4;
2493 val |= num_chans - 1;
2494
2495 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2496 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2497 val);
2498
2499 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2500 VENDOR_CHIPIO_PORT_ALLOC_SET,
2501 MEM_CONNID_DSP);
2502
2503 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2504 if (status < 0)
2505 return status;
2506
2507 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2508 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2509
2510 *port_map = res;
2511
2512 return (res < 0) ? res : 0;
2513}
2514
d5c21b88
IM		 2515/*
2516 * Free router ports
2517 */
01ef7dbf
IM		 2518static int dsp_free_router_ports(struct hda_codec *codec)
2519{
2520 int status = 0;
2521
2522 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2523 if (status < 0)
2524 return status;
2525
2526 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2527 VENDOR_CHIPIO_PORT_FREE_SET,
2528 MEM_CONNID_DSP);
2529
2530 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2531
2532 return status;
2533}
2534
d5c21b88
IM		 2535/*
2536 * Allocate DSP ports for the download stream
2537 */
01ef7dbf
IM		 2538static int dsp_allocate_ports(struct hda_codec *codec,
2539 unsigned int num_chans,
2540 unsigned int rate_multi, unsigned int *port_map)
2541{
2542 int status;
2543
4e76a883 2544 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2545
2546 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2547 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2548 return -EINVAL;
2549 }
2550
2551 status = dsp_allocate_router_ports(codec, num_chans,
2552 rate_multi, 0, port_map);
2553
4e76a883 2554 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2555
2556 return status;
2557}
2558
01ef7dbf
IM		 2559static int dsp_allocate_ports_format(struct hda_codec *codec,
2560 const unsigned short fmt,
2561 unsigned int *port_map)
2562{
2563 int status;
2564 unsigned int num_chans;
2565
2566 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2567 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2568 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2569
2570 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2571 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2572 return -EINVAL;
2573 }
2574
2575 num_chans = get_hdafmt_chs(fmt) + 1;
2576
2577 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2578
2579 return status;
2580}
2581
d5c21b88
IM		 2582/*
2583 * free DSP ports
2584 */
2585static int dsp_free_ports(struct hda_codec *codec)
2586{
2587 int status;
2588
4e76a883 2589 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2590
2591 status = dsp_free_router_ports(codec);
2592 if (status < 0) {
4e76a883 2593 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2594 return status;
2595 }
4e76a883 2596 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2597
2598 return status;
2599}
2600
01ef7dbf
IM		 2601/*
2602 * HDA DMA engine stuffs for DSP code download
2603 */
2604struct dma_engine {
2605 struct hda_codec *codec;
2606 unsigned short m_converter_format;
2607 struct snd_dma_buffer *dmab;
2608 unsigned int buf_size;
2609};
2610
2611
2612enum dma_state {
2613 DMA_STATE_STOP = 0,
2614 DMA_STATE_RUN = 1
2615};
2616
6194b99d 2617static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2618 unsigned int sample_rate,
2619 unsigned short channels,
01ef7dbf
IM		 2620 unsigned short *hda_format)
2621{
2622 unsigned int format_val;
2623
b7d023e1
TI		 2624 format_val = snd_hdac_calc_stream_format(sample_rate,
2625 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2626
2627 if (hda_format)
2628 *hda_format = (unsigned short)format_val;
2629
2630 return 0;
2631}
2632
d5c21b88
IM		 2633/*
2634 * Reset DMA for DSP download
2635 */
01ef7dbf
IM		 2636static int dma_reset(struct dma_engine *dma)
2637{
2638 struct hda_codec *codec = dma->codec;
2639 struct ca0132_spec *spec = codec->spec;
2640 int status;
2641
b3667bd7 2642 if (dma->dmab->area)
01ef7dbf
IM		 2643 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2644
2645 status = snd_hda_codec_load_dsp_prepare(codec,
2646 dma->m_converter_format,
2647 dma->buf_size,
2648 dma->dmab);
2649 if (status < 0)
2650 return status;
2651 spec->dsp_stream_id = status;
2652 return 0;
2653}
2654
2655static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2656{
01ef7dbf
IM		 2657 bool cmd;
2658
01ef7dbf
IM		 2659 switch (state) {
2660 case DMA_STATE_STOP:
2661 cmd = false;
2662 break;
2663 case DMA_STATE_RUN:
2664 cmd = true;
2665 break;
2666 default:
c41999a2
DH		 2667 return 0;
2668 }
01ef7dbf
IM		 2669
2670 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2671 return 0;
95c6e9cb
IM		 2672}
2673
01ef7dbf
IM		 2674static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2675{
2676 return dma->dmab->bytes;
2677}
95c6e9cb 2678
01ef7dbf
IM		 2679static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2680{
2681 return dma->dmab->area;
2682}
95c6e9cb 2683
01ef7dbf
IM		 2684static int dma_xfer(struct dma_engine *dma,
2685 const unsigned int *data,
2686 unsigned int count)
2687{
2688 memcpy(dma->dmab->area, data, count);
2689 return 0;
2690}
95c6e9cb 2691
01ef7dbf
IM		 2692static void dma_get_converter_format(
2693 struct dma_engine *dma,
2694 unsigned short *format)
2695{
2696 if (format)
2697 *format = dma->m_converter_format;
2698}
95c6e9cb 2699
01ef7dbf 2700static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2701{
01ef7dbf 2702 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2703
01ef7dbf 2704 return spec->dsp_stream_id;
95c6e9cb
IM		 2705}
2706
01ef7dbf
IM		 2707struct dsp_image_seg {
2708 u32 magic;
2709 u32 chip_addr;
2710 u32 count;
2711 u32 data[0];
2712};
2713
2714static const u32 g_magic_value = 0x4c46584d;
2715static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2716
2717static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2718{
01ef7dbf
IM		 2719 return p->magic == g_magic_value;
2720}
95c6e9cb 2721
01ef7dbf
IM		 2722static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2723{
2724 return g_chip_addr_magic_value == p->chip_addr;
2725}
95c6e9cb 2726
01ef7dbf
IM		 2727static bool is_last(const struct dsp_image_seg *p)
2728{
2729 return p->count == 0;
2730}
95c6e9cb 2731
01ef7dbf
IM		 2732static size_t dsp_sizeof(const struct dsp_image_seg *p)
2733{
2734 return sizeof(*p) + p->count*sizeof(u32);
2735}
2736
2737static const struct dsp_image_seg *get_next_seg_ptr(
2738 const struct dsp_image_seg *p)
2739{
2740 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2741}
2742
2743/*
01ef7dbf 2744 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2745 */
8ae3124b 2746#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2747
d5c21b88
IM		 2748/*
2749 * Program a list of address/data pairs via the ChipIO widget.
2750 * The segment data is in the format of successive pairs of words.
2751 * These are repeated as indicated by the segment's count field.
2752 */
01ef7dbf
IM		 2753static int dspxfr_hci_write(struct hda_codec *codec,
2754 const struct dsp_image_seg *fls)
95c6e9cb 2755{
01ef7dbf
IM		 2756 int status;
2757 const u32 *data;
2758 unsigned int count;
95c6e9cb 2759
01ef7dbf 2760 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2761 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2762 return -EINVAL;
95c6e9cb
IM		 2763 }
2764
01ef7dbf
IM		 2765 count = fls->count;
2766 data = (u32 *)(fls->data);
2767 while (count >= 2) {
2768 status = chipio_write(codec, data[0], data[1]);
2769 if (status < 0) {
4e76a883 2770 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2771 return status;
2772 }
2773 count -= 2;
2774 data += 2;
2775 }
2776 return 0;
95c6e9cb
IM		 2777}
2778
d5c21b88
IM		 2779/**
2780 * Write a block of data into DSP code or data RAM using pre-allocated
2781 * DMA engine.
2782 *
2783 * @codec: the HDA codec
2784 * @fls: pointer to a fast load image
2785 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2786 * no relocation
2787 * @dma_engine: pointer to DMA engine to be used for DSP download
2788 * @dma_chan: The number of DMA channels used for DSP download
2789 * @port_map_mask: port mapping
2790 * @ovly: TRUE if overlay format is required
2791 *
2792 * Returns zero or a negative error code.
2793 */
01ef7dbf
IM		 2794static int dspxfr_one_seg(struct hda_codec *codec,
2795 const struct dsp_image_seg *fls,
2796 unsigned int reloc,
2797 struct dma_engine *dma_engine,
2798 unsigned int dma_chan,
2799 unsigned int port_map_mask,
2800 bool ovly)
95c6e9cb 2801{
406261ce 2802 int status = 0;
01ef7dbf
IM		 2803 bool comm_dma_setup_done = false;
2804 const unsigned int *data;
2805 unsigned int chip_addx;
2806 unsigned int words_to_write;
2807 unsigned int buffer_size_words;
2808 unsigned char *buffer_addx;
2809 unsigned short hda_format;
2810 unsigned int sample_rate_div;
2811 unsigned int sample_rate_mul;
2812 unsigned int num_chans;
2813 unsigned int hda_frame_size_words;
2814 unsigned int remainder_words;
2815 const u32 *data_remainder;
2816 u32 chip_addx_remainder;
2817 unsigned int run_size_words;
2818 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2819 unsigned long timeout;
2820 bool dma_active;
01ef7dbf
IM		 2821
2822 if (fls == NULL)
2823 return -EINVAL;
2824 if (is_hci_prog_list_seg(fls)) {
2825 hci_write = fls;
2826 fls = get_next_seg_ptr(fls);
2827 }
95c6e9cb 2828
01ef7dbf 2829 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2830 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2831 return dspxfr_hci_write(codec, hci_write);
2832 }
95c6e9cb 2833
01ef7dbf 2834 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2835 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2836 return -EINVAL;
95c6e9cb
IM		 2837 }
2838
01ef7dbf
IM		 2839 data = fls->data;
2840 chip_addx = fls->chip_addr,
2841 words_to_write = fls->count;
2842
2843 if (!words_to_write)
2844 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2845 if (reloc)
2846 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2847
2848 if (!UC_RANGE(chip_addx, words_to_write) &&
2849 !X_RANGE_ALL(chip_addx, words_to_write) &&
2850 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2851 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2852 return -EINVAL;
95c6e9cb
IM		 2853 }
2854
01ef7dbf
IM		 2855 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2856 sizeof(u32);
2857
2858 buffer_addx = dma_get_buffer_addr(dma_engine);
2859
2860 if (buffer_addx == NULL) {
4e76a883 2861 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2862 return -EINVAL;
2863 }
2864
2865 dma_get_converter_format(dma_engine, &hda_format);
2866 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2867 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2868 num_chans = get_hdafmt_chs(hda_format) + 1;
2869
2870 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2871 (num_chans * sample_rate_mul / sample_rate_div));
2872
3bc085a1 2873 if (hda_frame_size_words == 0) {
4e76a883 2874 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2875 return -EINVAL;
2876 }
2877
01ef7dbf
IM		 2878 buffer_size_words = min(buffer_size_words,
2879 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2880 65536 : 32768));
2881 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2882 codec_dbg(codec,
01ef7dbf
IM		 2883 "chpadr=0x%08x frmsz=%u nchan=%u "
2884 "rate_mul=%u div=%u bufsz=%u\n",
2885 chip_addx, hda_frame_size_words, num_chans,
2886 sample_rate_mul, sample_rate_div, buffer_size_words);
2887
3bc085a1 2888 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2889 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2890 return -EINVAL;
2891 }
2892
2893 remainder_words = words_to_write % hda_frame_size_words;
2894 data_remainder = data;
2895 chip_addx_remainder = chip_addx;
2896
2897 data += remainder_words;
2898 chip_addx += remainder_words*sizeof(u32);
2899 words_to_write -= remainder_words;
2900
2901 while (words_to_write != 0) {
2902 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2903 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2904 words_to_write, run_size_words, remainder_words);
2905 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2906 if (!comm_dma_setup_done) {
2907 status = dsp_dma_stop(codec, dma_chan, ovly);
2908 if (status < 0)
425a7880 2909 return status;
01ef7dbf
IM		 2910 status = dsp_dma_setup_common(codec, chip_addx,
2911 dma_chan, port_map_mask, ovly);
2912 if (status < 0)
2913 return status;
2914 comm_dma_setup_done = true;
2915 }
2916
2917 status = dsp_dma_setup(codec, chip_addx,
2918 run_size_words, dma_chan);
2919 if (status < 0)
2920 return status;
2921 status = dsp_dma_start(codec, dma_chan, ovly);
2922 if (status < 0)
2923 return status;
2924 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2925 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2926 return -EIO;
2927 }
2928 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2929 if (status < 0)
2930 return status;
2931 if (remainder_words != 0) {
2932 status = chipio_write_multiple(codec,
2933 chip_addx_remainder,
2934 data_remainder,
2935 remainder_words);
b3667bd7
TI		 2936 if (status < 0)
2937 return status;
01ef7dbf
IM		 2938 remainder_words = 0;
2939 }
2940 if (hci_write) {
2941 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2942 if (status < 0)
2943 return status;
01ef7dbf
IM		 2944 hci_write = NULL;
2945 }
6d67530e
IM		 2946
2947 timeout = jiffies + msecs_to_jiffies(2000);
2948 do {
2949 dma_active = dsp_is_dma_active(codec, dma_chan);
2950 if (!dma_active)
01ef7dbf 2951 break;
6d67530e
IM		 2952 msleep(20);
2953 } while (time_before(jiffies, timeout));
2954 if (dma_active)
2955 break;
2956
4e76a883 2957 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2958 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2959 status = dma_reset(dma_engine);
01ef7dbf
IM		 2960
2961 if (status < 0)
2962 return status;
2963
2964 data += run_size_words;
2965 chip_addx += run_size_words*sizeof(u32);
2966 words_to_write -= run_size_words;
2967 }
2968
2969 if (remainder_words != 0) {
2970 status = chipio_write_multiple(codec, chip_addx_remainder,
2971 data_remainder, remainder_words);
2972 }
2973
2974 return status;
95c6e9cb
IM		 2975}
2976
d5c21b88
IM		 2977/**
2978 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2979 *
2980 * @codec: the HDA codec
2981 * @fls_data: pointer to a fast load image
2982 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2983 * no relocation
e97249dd 2984 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2985 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2986 * @ovly: TRUE if overlay format is required
2987 *
2988 * Returns zero or a negative error code.
2989 */
01ef7dbf
IM		 2990static int dspxfr_image(struct hda_codec *codec,
2991 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2992 unsigned int reloc,
2993 unsigned int sample_rate,
2994 unsigned short channels,
01ef7dbf 2995 bool ovly)
95c6e9cb
IM		 2996{
2997 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2998 int status;
2999 unsigned short hda_format = 0;
3000 unsigned int response;
3001 unsigned char stream_id = 0;
3002 struct dma_engine *dma_engine;
3003 unsigned int dma_chan;
3004 unsigned int port_map_mask;
3005
3006 if (fls_data == NULL)
3007 return -EINVAL;
3008
3009 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 3010 if (!dma_engine)
3011 return -ENOMEM;
95c6e9cb 3012
01ef7dbf
IM		 3013 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3014 if (!dma_engine->dmab) {
549e8292
TI		 3015 kfree(dma_engine);
3016 return -ENOMEM;
01ef7dbf 3017 }
95c6e9cb 3018
01ef7dbf 3019 dma_engine->codec = codec;
6194b99d 3020 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 3021 dma_engine->m_converter_format = hda_format;
3022 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3023 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3024
8ae3124b 3025 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 3026
3027 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3028 hda_format, &response);
3029
3030 if (status < 0) {
4e76a883 3031 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 3032 goto exit;
3033 }
3034
3035 status = snd_hda_codec_load_dsp_prepare(codec,
3036 dma_engine->m_converter_format,
3037 dma_engine->buf_size,
3038 dma_engine->dmab);
3039 if (status < 0)
95c6e9cb 3040 goto exit;
01ef7dbf
IM		 3041 spec->dsp_stream_id = status;
3042
3043 if (ovly) {
3044 status = dspio_alloc_dma_chan(codec, &dma_chan);
3045 if (status < 0) {
4e76a883 3046 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 3047 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 3048 goto exit;
3049 }
3050 }
95c6e9cb 3051
01ef7dbf
IM		 3052 port_map_mask = 0;
3053 status = dsp_allocate_ports_format(codec, hda_format,
3054 &port_map_mask);
3055 if (status < 0) {
4e76a883 3056 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 3057 goto exit;
3058 }
3059
3060 stream_id = dma_get_stream_id(dma_engine);
3061 status = codec_set_converter_stream_channel(codec,
3062 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3063 if (status < 0) {
4e76a883 3064 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 3065 goto exit;
3066 }
3067
3068 while ((fls_data != NULL) && !is_last(fls_data)) {
3069 if (!is_valid(fls_data)) {
4e76a883 3070 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 3071 status = -EINVAL;
3072 goto exit;
3073 }
3074 status = dspxfr_one_seg(codec, fls_data, reloc,
3075 dma_engine, dma_chan,
3076 port_map_mask, ovly);
3077 if (status < 0)
3078 break;
3079
3080 if (is_hci_prog_list_seg(fls_data))
3081 fls_data = get_next_seg_ptr(fls_data);
3082
3083 if ((fls_data != NULL) && !is_last(fls_data))
3084 fls_data = get_next_seg_ptr(fls_data);
3085 }
3086
3087 if (port_map_mask != 0)
3088 status = dsp_free_ports(codec);
3089
3090 if (status < 0)
95c6e9cb
IM		 3091 goto exit;
3092
01ef7dbf
IM		 3093 status = codec_set_converter_stream_channel(codec,
3094 WIDGET_CHIP_CTRL, 0, 0, &response);
3095
95c6e9cb 3096exit:
01ef7dbf
IM		 3097 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3098 dspio_free_dma_chan(codec, dma_chan);
3099
b3667bd7 3100 if (dma_engine->dmab->area)
01ef7dbf
IM		 3101 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3102 kfree(dma_engine->dmab);
3103 kfree(dma_engine);
3104
3105 return status;
95c6e9cb
IM		 3106}
3107
3108/*
01ef7dbf 3109 * CA0132 DSP download stuffs.
95c6e9cb 3110 */
01ef7dbf 3111static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 3112{
009b8f97 3113 struct ca0132_spec *spec = codec->spec;
4e76a883 3114 codec_dbg(codec, "---- dspload_post_setup ------\n");
6da8f446 3115 if (!ca0132_use_alt_functions(spec)) {
009b8f97
CM		 3116 /*set DSP speaker to 2.0 configuration*/
3117 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3118 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 3119
009b8f97
CM		 3120 /*update write pointer*/
3121 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3122 }
01ef7dbf 3123}
95c6e9cb 3124
d5c21b88 3125/**
e60b2c7f 3126 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 3127 *
3128 * @codec: the HDA codec
3129 * @fls: pointer to a fast load image
3130 * @ovly: TRUE if overlay format is required
3131 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3132 * no relocation
3133 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3134 * @router_chans: number of audio router channels to be allocated (0 means use
3135 * internal defaults; max is 32)
3136 *
e60b2c7f
TI		 3137 * Download DSP from a DSP Image Fast Load structure. This structure is a
3138 * linear, non-constant sized element array of structures, each of which
3139 * contain the count of the data to be loaded, the data itself, and the
3140 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 3141 * Returns zero or a negative error code.
3142 */
01ef7dbf
IM		 3143static int dspload_image(struct hda_codec *codec,
3144 const struct dsp_image_seg *fls,
3145 bool ovly,
3146 unsigned int reloc,
3147 bool autostart,
3148 int router_chans)
3149{
3150 int status = 0;
e97249dd
IM		 3151 unsigned int sample_rate;
3152 unsigned short channels;
01ef7dbf 3153
4e76a883 3154 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 3155 if (router_chans == 0) {
3156 if (!ovly)
3157 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3158 else
3159 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3160 }
95c6e9cb 3161
e97249dd
IM		 3162 sample_rate = 48000;
3163 channels = (unsigned short)router_chans;
01ef7dbf 3164
e97249dd
IM		 3165 while (channels > 16) {
3166 sample_rate *= 2;
3167 channels /= 2;
01ef7dbf
IM		 3168 }
3169
01ef7dbf 3170 do {
4e76a883 3171 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3172 if (!ovly)
3173 status = dsp_reset(codec);
3174
3175 if (status < 0)
3176 break;
3177
4e76a883 3178 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3179 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3180 ovly);
01ef7dbf
IM		 3181
3182 if (status < 0)
3183 break;
3184
4e76a883 3185 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3186 if (autostart && !ovly) {
3187 dspload_post_setup(codec);
3188 status = dsp_set_run_state(codec);
3189 }
3190
4e76a883 3191 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3192 } while (0);
3193
3194 return status;
3195}
3196
f664417e 3197#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3198static bool dspload_is_loaded(struct hda_codec *codec)
3199{
3200 unsigned int data = 0;
3201 int status = 0;
3202
3203 status = chipio_read(codec, 0x40004, &data);
3204 if ((status < 0) || (data != 1))
3205 return false;
3206
3207 return true;
3208}
f664417e
TI		 3209#else
3210#define dspload_is_loaded(codec) false
3211#endif
01ef7dbf
IM		 3212
3213static bool dspload_wait_loaded(struct hda_codec *codec)
3214{
6d67530e 3215 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3216
3217 do {
01ef7dbf 3218 if (dspload_is_loaded(codec)) {
d9684bb5 3219 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3220 return true;
3221 }
6d67530e
IM		 3222 msleep(20);
3223 } while (time_before(jiffies, timeout));
01ef7dbf 3224
d9684bb5 3225 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3226 return false;
95c6e9cb
IM		 3227}
3228
e93ac30a 3229/*
b9b41345
CM		 3230 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3231 * based cards, and has a second mmio region, region2, that's used for special
3232 * commands.
e93ac30a
CM		 3233 */
3234
a62e4739
CM		 3235/*
3236 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3237 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3238 * The first eight bits are just the number of the pin. So far, I've only seen
3239 * this number go to 7.
b9b41345
CM		 3240 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3241 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3242 * then off to send that bit.
a62e4739 3243 */
b9b41345 3244static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
a62e4739
CM		 3245 bool enable)
3246{
3247 struct ca0132_spec *spec = codec->spec;
3248 unsigned short gpio_data;
3249
3250 gpio_data = gpio_pin & 0xF;
3251 gpio_data |= ((enable << 8) & 0x100);
3252
3253 writew(gpio_data, spec->mem_base + 0x320);
3254}
3255
b9b41345
CM		 3256/*
3257 * Special pci region2 commands that are only used by the AE-5. They follow
3258 * a set format, and require reads at certain points to seemingly 'clear'
3259 * the response data. My first tests didn't do these reads, and would cause
3260 * the card to get locked up until the memory was read. These commands
3261 * seem to work with three distinct values that I've taken to calling group,
3262 * target-id, and value.
3263 */
3264static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3265 unsigned int target, unsigned int value)
3266{
3267 struct ca0132_spec *spec = codec->spec;
3268 unsigned int write_val;
3269
3270 writel(0x0000007e, spec->mem_base + 0x210);
3271 readl(spec->mem_base + 0x210);
3272 writel(0x0000005a, spec->mem_base + 0x210);
3273 readl(spec->mem_base + 0x210);
3274 readl(spec->mem_base + 0x210);
3275
3276 writel(0x00800005, spec->mem_base + 0x20c);
3277 writel(group, spec->mem_base + 0x804);
3278
3279 writel(0x00800005, spec->mem_base + 0x20c);
3280 write_val = (target & 0xff);
3281 write_val |= (value << 8);
3282
3283
3284 writel(write_val, spec->mem_base + 0x204);
3285 /*
3286 * Need delay here or else it goes too fast and works inconsistently.
3287 */
3288 msleep(20);
3289
3290 readl(spec->mem_base + 0x860);
3291 readl(spec->mem_base + 0x854);
3292 readl(spec->mem_base + 0x840);
3293
3294 writel(0x00800004, spec->mem_base + 0x20c);
3295 writel(0x00000000, spec->mem_base + 0x210);
3296 readl(spec->mem_base + 0x210);
3297 readl(spec->mem_base + 0x210);
3298}
3299
212de2e7
CM		 3300/*
3301 * This second type of command is used for setting the sound filter type.
3302 */
3303static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3304 unsigned int group, unsigned int target, unsigned int value)
3305{
3306 struct ca0132_spec *spec = codec->spec;
3307 unsigned int write_val;
3308
3309 writel(0x0000007e, spec->mem_base + 0x210);
3310 readl(spec->mem_base + 0x210);
3311 writel(0x0000005a, spec->mem_base + 0x210);
3312 readl(spec->mem_base + 0x210);
3313 readl(spec->mem_base + 0x210);
3314
3315 writel(0x00800003, spec->mem_base + 0x20c);
3316 writel(group, spec->mem_base + 0x804);
3317
3318 writel(0x00800005, spec->mem_base + 0x20c);
3319 write_val = (target & 0xff);
3320 write_val |= (value << 8);
3321
3322
3323 writel(write_val, spec->mem_base + 0x204);
3324 msleep(20);
3325 readl(spec->mem_base + 0x860);
3326 readl(spec->mem_base + 0x854);
3327 readl(spec->mem_base + 0x840);
3328
3329 writel(0x00800004, spec->mem_base + 0x20c);
3330 writel(0x00000000, spec->mem_base + 0x210);
3331 readl(spec->mem_base + 0x210);
3332 readl(spec->mem_base + 0x210);
3333}
3334
b9b41345
CM		 3335/*
3336 * Setup GPIO for the other variants of Core3D.
3337 */
3338
e93ac30a
CM		 3339/*
3340 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3341 * the card shows as having no GPIO pins.
3342 */
3343static void ca0132_gpio_init(struct hda_codec *codec)
3344{
3345 struct ca0132_spec *spec = codec->spec;
3346
6da8f446 3347 switch (ca0132_quirk(spec)) {
e93ac30a 3348 case QUIRK_SBZ:
03c9b6b1 3349 case QUIRK_AE5:
e93ac30a
CM		 3350 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3351 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3352 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3353 break;
3354 case QUIRK_R3DI:
3355 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3356 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3357 break;
6da8f446
TI		 3358 default:
3359 break;
e93ac30a
CM		 3360 }
3361
3362}
3363
3364/* Sets the GPIO for audio output. */
3365static void ca0132_gpio_setup(struct hda_codec *codec)
3366{
3367 struct ca0132_spec *spec = codec->spec;
3368
6da8f446 3369 switch (ca0132_quirk(spec)) {
e93ac30a
CM		 3370 case QUIRK_SBZ:
3371 snd_hda_codec_write(codec, 0x01, 0,
3372 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3373 snd_hda_codec_write(codec, 0x01, 0,
3374 AC_VERB_SET_GPIO_MASK, 0x07);
3375 snd_hda_codec_write(codec, 0x01, 0,
3376 AC_VERB_SET_GPIO_DATA, 0x04);
3377 snd_hda_codec_write(codec, 0x01, 0,
3378 AC_VERB_SET_GPIO_DATA, 0x06);
3379 break;
3380 case QUIRK_R3DI:
3381 snd_hda_codec_write(codec, 0x01, 0,
3382 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3383 snd_hda_codec_write(codec, 0x01, 0,
3384 AC_VERB_SET_GPIO_MASK, 0x1F);
3385 snd_hda_codec_write(codec, 0x01, 0,
3386 AC_VERB_SET_GPIO_DATA, 0x0C);
3387 break;
6da8f446
TI		 3388 default:
3389 break;
e93ac30a
CM		 3390 }
3391}
3392
7e6ed62e
CM		 3393/*
3394 * GPIO control functions for the Recon3D integrated.
3395 */
3396
3397enum r3di_gpio_bit {
3398 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3399 R3DI_MIC_SELECT_BIT = 1,
3400 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3401 R3DI_OUT_SELECT_BIT = 2,
3402 /*
3403 * I dunno what this actually does, but it stays on until the dsp
3404 * is downloaded.
3405 */
3406 R3DI_GPIO_DSP_DOWNLOADING = 3,
3407 /*
3408 * Same as above, no clue what it does, but it comes on after the dsp
3409 * is downloaded.
3410 */
3411 R3DI_GPIO_DSP_DOWNLOADED = 4
3412};
3413
3414enum r3di_mic_select {
3415 /* Set GPIO bit 1 to 0 for rear mic */
3416 R3DI_REAR_MIC = 0,
3417 /* Set GPIO bit 1 to 1 for front microphone*/
3418 R3DI_FRONT_MIC = 1
3419};
3420
3421enum r3di_out_select {
3422 /* Set GPIO bit 2 to 0 for headphone */
3423 R3DI_HEADPHONE_OUT = 0,
3424 /* Set GPIO bit 2 to 1 for speaker */
3425 R3DI_LINE_OUT = 1
3426};
3427enum r3di_dsp_status {
3428 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3429 R3DI_DSP_DOWNLOADING = 0,
3430 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3431 R3DI_DSP_DOWNLOADED = 1
3432};
3433
7cb9d94c
CM		 3434
3435static void r3di_gpio_mic_set(struct hda_codec *codec,
3436 enum r3di_mic_select cur_mic)
3437{
3438 unsigned int cur_gpio;
3439
3440 /* Get the current GPIO Data setup */
3441 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3442
3443 switch (cur_mic) {
3444 case R3DI_REAR_MIC:
3445 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3446 break;
3447 case R3DI_FRONT_MIC:
3448 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3449 break;
3450 }
3451 snd_hda_codec_write(codec, codec->core.afg, 0,
3452 AC_VERB_SET_GPIO_DATA, cur_gpio);
3453}
3454
3455static void r3di_gpio_out_set(struct hda_codec *codec,
3456 enum r3di_out_select cur_out)
3457{
3458 unsigned int cur_gpio;
3459
3460 /* Get the current GPIO Data setup */
3461 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3462
3463 switch (cur_out) {
3464 case R3DI_HEADPHONE_OUT:
3465 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3466 break;
3467 case R3DI_LINE_OUT:
3468 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3469 break;
3470 }
3471 snd_hda_codec_write(codec, codec->core.afg, 0,
3472 AC_VERB_SET_GPIO_DATA, cur_gpio);
3473}
3474
7e6ed62e
CM		 3475static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3476 enum r3di_dsp_status dsp_status)
3477{
3478 unsigned int cur_gpio;
3479
3480 /* Get the current GPIO Data setup */
3481 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3482
3483 switch (dsp_status) {
3484 case R3DI_DSP_DOWNLOADING:
3485 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3486 snd_hda_codec_write(codec, codec->core.afg, 0,
3487 AC_VERB_SET_GPIO_DATA, cur_gpio);
3488 break;
3489 case R3DI_DSP_DOWNLOADED:
3490 /* Set DOWNLOADING bit to 0. */
3491 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3492
3493 snd_hda_codec_write(codec, codec->core.afg, 0,
3494 AC_VERB_SET_GPIO_DATA, cur_gpio);
3495
3496 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3497 break;
3498 }
3499
3500 snd_hda_codec_write(codec, codec->core.afg, 0,
3501 AC_VERB_SET_GPIO_DATA, cur_gpio);
3502}
3503
825315bc
IM		 3504/*
3505 * PCM callbacks
3506 */
95c6e9cb
IM		 3507static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3508 struct hda_codec *codec,
3509 unsigned int stream_tag,
3510 unsigned int format,
3511 struct snd_pcm_substream *substream)
3512{
3513 struct ca0132_spec *spec = codec->spec;
825315bc 3514
28fba950 3515 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3516
3517 return 0;
95c6e9cb
IM		 3518}
3519
3520static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3521 struct hda_codec *codec,
3522 struct snd_pcm_substream *substream)
3523{
3524 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3525
3526 if (spec->dsp_state == DSP_DOWNLOADING)
3527 return 0;
3528
3529 /*If Playback effects are on, allow stream some time to flush
3530 *effects tail*/
3531 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3532 msleep(50);
3533
28fba950 3534 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3535
3536 return 0;
95c6e9cb
IM		 3537}
3538
e8412ca4
DR		 3539static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3540 struct hda_codec *codec,
3541 struct snd_pcm_substream *substream)
3542{
3543 struct ca0132_spec *spec = codec->spec;
3544 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3545 struct snd_pcm_runtime *runtime = substream->runtime;
3546
3547 if (spec->dsp_state != DSP_DOWNLOADED)
3548 return 0;
3549
3550 /* Add latency if playback enhancement and either effect is enabled. */
3551 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3552 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3553 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3554 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3555 }
3556
3557 /* Applying Speaker EQ adds latency as well. */
3558 if (spec->cur_out_type == SPEAKER_OUT)
3559 latency += DSP_SPEAKER_OUT_LATENCY;
3560
3561 return (latency * runtime->rate) / 1000;
3562}
3563
95c6e9cb
IM		 3564/*
3565 * Digital out
3566 */
27ebeb0b
TI		 3567static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3568 struct hda_codec *codec,
3569 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3570{
3571 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3572 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3573}
3574
27ebeb0b 3575static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3576 struct hda_codec *codec,
3577 unsigned int stream_tag,
3578 unsigned int format,
3579 struct snd_pcm_substream *substream)
3580{
3581 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3582 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3583 stream_tag, format, substream);
95c6e9cb
IM		 3584}
3585
27ebeb0b 3586static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3587 struct hda_codec *codec,
95c6e9cb
IM		 3588 struct snd_pcm_substream *substream)
3589{
3590 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3591 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3592}
3593
27ebeb0b
TI		 3594static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3595 struct hda_codec *codec,
3596 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3597{
3598 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3599 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3600}
3601
825315bc
IM		 3602/*
3603 * Analog capture
3604 */
3605static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3606 struct hda_codec *codec,
3607 unsigned int stream_tag,
3608 unsigned int format,
3609 struct snd_pcm_substream *substream)
3610{
13c12dbe 3611 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3612 stream_tag, 0, format);
825315bc
IM		 3613
3614 return 0;
3615}
3616
3617static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3618 struct hda_codec *codec,
3619 struct snd_pcm_substream *substream)
3620{
3621 struct ca0132_spec *spec = codec->spec;
3622
3623 if (spec->dsp_state == DSP_DOWNLOADING)
3624 return 0;
3625
28fba950 3626 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3627 return 0;
3628}
3629
e8412ca4
DR		 3630static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3631 struct hda_codec *codec,
3632 struct snd_pcm_substream *substream)
3633{
3634 struct ca0132_spec *spec = codec->spec;
3635 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3636 struct snd_pcm_runtime *runtime = substream->runtime;
3637
3638 if (spec->dsp_state != DSP_DOWNLOADED)
3639 return 0;
3640
3641 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3642 latency += DSP_CRYSTAL_VOICE_LATENCY;
3643
3644 return (latency * runtime->rate) / 1000;
3645}
3646
e90f29e4
IM		 3647/*
3648 * Controls stuffs.
3649 */
3650
3651/*
3652 * Mixer controls helpers.
3653 */
3654#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3655 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3656 .name = xname, \
3657 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3658 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3659 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3660 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3661 .info = ca0132_volume_info, \
3662 .get = ca0132_volume_get, \
3663 .put = ca0132_volume_put, \
3664 .tlv = { .c = ca0132_volume_tlv }, \
3665 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3666
017310fb
CM		 3667/*
3668 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3669 * volume put, which is used for setting the DSP volume. This was done because
3670 * the ca0132 functions were taking too much time and causing lag.
3671 */
3672#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3673 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3674 .name = xname, \
3675 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3676 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3677 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3678 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3679 .info = snd_hda_mixer_amp_volume_info, \
3680 .get = snd_hda_mixer_amp_volume_get, \
3681 .put = ca0132_alt_volume_put, \
3682 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3683 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3684
e90f29e4
IM		 3685#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3686 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3687 .name = xname, \
3688 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3689 .info = snd_hda_mixer_amp_switch_info, \
3690 .get = ca0132_switch_get, \
3691 .put = ca0132_switch_put, \
3692 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3693
3694/* stereo */
3695#define CA0132_CODEC_VOL(xname, nid, dir) \
3696 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3697#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3698 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3699#define CA0132_CODEC_MUTE(xname, nid, dir) \
3700 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3701
017310fb
CM		 3702/* lookup tables */
3703/*
3704 * Lookup table with decibel values for the DSP. When volume is changed in
3705 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3706 * these values have decimal points, probably because the Windows driver
3707 * actually uses floating point. We can't here, so I made a lookup table of
3708 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3709 * DAC's, and 9 is the maximum.
3710 */
3711static const unsigned int float_vol_db_lookup[] = {
37120xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
37130xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
37140xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
37150xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
37160xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
37170xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
37180xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
37190xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
37200xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
37210xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
37220xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
37230xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
37240xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
37250xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
37260xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
37270x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
37280x40C00000, 0x40E00000, 0x41000000, 0x41100000
3729};
3730
47cdf76e
CM		 3731/*
3732 * This table counts from float 0 to 1 in increments of .01, which is
3733 * useful for a few different sliders.
3734 */
3735static const unsigned int float_zero_to_one_lookup[] = {
37360x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37370x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37380x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37390x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
37400x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
37410x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
37420x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
37430x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
37440x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
37450x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
37460x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
37470x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
37480x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
37490x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
37500x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
37510x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
37520x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3753};
3754
3755/*
3756 * This table counts from float 10 to 1000, which is the range of the x-bass
3757 * crossover slider in Windows.
3758 */
3759static const unsigned int float_xbass_xover_lookup[] = {
37600x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
37610x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
37620x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
37630x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
37640x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
37650x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
37660x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
37670x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
37680x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
37690x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
37700x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
37710x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
37720x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
37730x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
37740x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
37750x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
37760x44728000, 0x44750000, 0x44778000, 0x447A0000
3777};
3778
4091fb95 3779/* The following are for tuning of products */
44f0c978
IM		 3780#ifdef ENABLE_TUNING_CONTROLS
3781
3782static unsigned int voice_focus_vals_lookup[] = {
37830x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
37840x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
37850x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
37860x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
37870x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
37880x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
37890x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
37900x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
37910x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
37920x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
37930x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
37940x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
37950x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
37960x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
37970x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
37980x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
37990x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
38000x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
38010x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
38020x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
38030x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
38040x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
38050x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
38060x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
38070x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
38080x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
38090x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3810};
3811
3812static unsigned int mic_svm_vals_lookup[] = {
38130x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
38140x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
38150x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
38160x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
38170x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
38180x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
38190x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
38200x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
38210x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
38220x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
38230x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
38240x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
38250x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
38260x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
38270x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
38280x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
38290x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3830};
3831
3832static unsigned int equalizer_vals_lookup[] = {
38330xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
38340xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
38350xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
38360xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
38370x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
38380x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
38390x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
38400x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
38410x41C00000
3842};
3843
3844static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3845 unsigned int *lookup, int idx)
3846{
3847 int i = 0;
3848
3849 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3850 if (nid == ca0132_tuning_ctls[i].nid)
3851 break;
3852
3853 snd_hda_power_up(codec);
447fd8e9 3854 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3855 ca0132_tuning_ctls[i].req,
3856 &(lookup[idx]), sizeof(unsigned int));
3857 snd_hda_power_down(codec);
3858
3859 return 1;
3860}
3861
3862static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3863 struct snd_ctl_elem_value *ucontrol)
3864{
3865 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3866 struct ca0132_spec *spec = codec->spec;
3867 hda_nid_t nid = get_amp_nid(kcontrol);
3868 long *valp = ucontrol->value.integer.value;
3869 int idx = nid - TUNING_CTL_START_NID;
3870
3871 *valp = spec->cur_ctl_vals[idx];
3872 return 0;
3873}
3874
3875static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3876 struct snd_ctl_elem_info *uinfo)
3877{
3878 int chs = get_amp_channels(kcontrol);
3879 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3880 uinfo->count = chs == 3 ? 2 : 1;
3881 uinfo->value.integer.min = 20;
3882 uinfo->value.integer.max = 180;
3883 uinfo->value.integer.step = 1;
3884
3885 return 0;
3886}
3887
3888static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3889 struct snd_ctl_elem_value *ucontrol)
3890{
3891 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3892 struct ca0132_spec *spec = codec->spec;
3893 hda_nid_t nid = get_amp_nid(kcontrol);
3894 long *valp = ucontrol->value.integer.value;
3895 int idx;
3896
3897 idx = nid - TUNING_CTL_START_NID;
3898 /* any change? */
3899 if (spec->cur_ctl_vals[idx] == *valp)
3900 return 0;
3901
3902 spec->cur_ctl_vals[idx] = *valp;
3903
3904 idx = *valp - 20;
3905 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3906
3907 return 1;
3908}
3909
3910static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3911 struct snd_ctl_elem_info *uinfo)
3912{
3913 int chs = get_amp_channels(kcontrol);
3914 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3915 uinfo->count = chs == 3 ? 2 : 1;
3916 uinfo->value.integer.min = 0;
3917 uinfo->value.integer.max = 100;
3918 uinfo->value.integer.step = 1;
3919
3920 return 0;
3921}
3922
3923static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3924 struct snd_ctl_elem_value *ucontrol)
3925{
3926 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3927 struct ca0132_spec *spec = codec->spec;
3928 hda_nid_t nid = get_amp_nid(kcontrol);
3929 long *valp = ucontrol->value.integer.value;
3930 int idx;
3931
3932 idx = nid - TUNING_CTL_START_NID;
3933 /* any change? */
3934 if (spec->cur_ctl_vals[idx] == *valp)
3935 return 0;
3936
3937 spec->cur_ctl_vals[idx] = *valp;
3938
3939 idx = *valp;
3940 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3941
3942 return 0;
3943}
3944
3945static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3946 struct snd_ctl_elem_info *uinfo)
3947{
3948 int chs = get_amp_channels(kcontrol);
3949 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3950 uinfo->count = chs == 3 ? 2 : 1;
3951 uinfo->value.integer.min = 0;
3952 uinfo->value.integer.max = 48;
3953 uinfo->value.integer.step = 1;
3954
3955 return 0;
3956}
3957
3958static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3959 struct snd_ctl_elem_value *ucontrol)
3960{
3961 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3962 struct ca0132_spec *spec = codec->spec;
3963 hda_nid_t nid = get_amp_nid(kcontrol);
3964 long *valp = ucontrol->value.integer.value;
3965 int idx;
3966
3967 idx = nid - TUNING_CTL_START_NID;
3968 /* any change? */
3969 if (spec->cur_ctl_vals[idx] == *valp)
3970 return 0;
3971
3972 spec->cur_ctl_vals[idx] = *valp;
3973
3974 idx = *valp;
3975 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3976
3977 return 1;
3978}
3979
8e142e9e
TS		 3980static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3981static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3982
3983static int add_tuning_control(struct hda_codec *codec,
3984 hda_nid_t pnid, hda_nid_t nid,
3985 const char *name, int dir)
3986{
975cc02a 3987 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3988 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3989 struct snd_kcontrol_new knew =
3990 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3991
3992 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3993 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3994 knew.tlv.c = 0;
3995 knew.tlv.p = 0;
3996 switch (pnid) {
3997 case VOICE_FOCUS:
3998 knew.info = voice_focus_ctl_info;
3999 knew.get = tuning_ctl_get;
4000 knew.put = voice_focus_ctl_put;
4001 knew.tlv.p = voice_focus_db_scale;
4002 break;
4003 case MIC_SVM:
4004 knew.info = mic_svm_ctl_info;
4005 knew.get = tuning_ctl_get;
4006 knew.put = mic_svm_ctl_put;
4007 break;
4008 case EQUALIZER:
4009 knew.info = equalizer_ctl_info;
4010 knew.get = tuning_ctl_get;
4011 knew.put = equalizer_ctl_put;
4012 knew.tlv.p = eq_db_scale;
4013 break;
4014 default:
4015 return 0;
4016 }
4017 knew.private_value =
4018 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4019 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4020 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4021}
4022
4023static int add_tuning_ctls(struct hda_codec *codec)
4024{
4025 int i;
4026 int err;
4027
4028 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4029 err = add_tuning_control(codec,
4030 ca0132_tuning_ctls[i].parent_nid,
4031 ca0132_tuning_ctls[i].nid,
4032 ca0132_tuning_ctls[i].name,
4033 ca0132_tuning_ctls[i].direct);
4034 if (err < 0)
4035 return err;
4036 }
4037
4038 return 0;
4039}
4040
4041static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4042{
4043 struct ca0132_spec *spec = codec->spec;
4044 int i;
4045
4046 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4047 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4048 /* SVM level defaults to 0.74. */
4049 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4050
4051 /* EQ defaults to 0dB. */
4052 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4053 spec->cur_ctl_vals[i] = 24;
4054}
4055#endif /*ENABLE_TUNING_CONTROLS*/
4056
5aaca44d
IM		 4057/*
4058 * Select the active output.
4059 * If autodetect is enabled, output will be selected based on jack detection.
4060 * If jack inserted, headphone will be selected, else built-in speakers
4061 * If autodetect is disabled, output will be selected based on selection.
4062 */
4063static int ca0132_select_out(struct hda_codec *codec)
4064{
4065 struct ca0132_spec *spec = codec->spec;
4066 unsigned int pin_ctl;
4067 int jack_present;
4068 int auto_jack;
4069 unsigned int tmp;
4070 int err;
4071
4e76a883 4072 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 4073
664c7155 4074 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4075
4076 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4077
4078 if (auto_jack)
fe14f39e 4079 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 4080 else
4081 jack_present =
4082 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4083
4084 if (jack_present)
4085 spec->cur_out_type = HEADPHONE_OUT;
4086 else
4087 spec->cur_out_type = SPEAKER_OUT;
4088
4089 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 4090 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 4091 /*speaker out config*/
4092 tmp = FLOAT_ONE;
4093 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4094 if (err < 0)
4095 goto exit;
4096 /*enable speaker EQ*/
4097 tmp = FLOAT_ONE;
4098 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4099 if (err < 0)
4100 goto exit;
4101
4102 /* Setup EAPD */
4103 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4104 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4105 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4106 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4107 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4108 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4109 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4110 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4111
4112 /* disable headphone node */
4113 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4114 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4115 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4116 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4117 /* enable speaker node */
4118 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 4119 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4120 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4121 pin_ctl | PIN_OUT);
5aaca44d 4122 } else {
4e76a883 4123 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 4124 /*headphone out config*/
4125 tmp = FLOAT_ZERO;
4126 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4127 if (err < 0)
4128 goto exit;
4129 /*disable speaker EQ*/
4130 tmp = FLOAT_ZERO;
4131 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4132 if (err < 0)
4133 goto exit;
4134
4135 /* Setup EAPD */
4136 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4137 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4138 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4139 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4140 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4141 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4142 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4143 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4144
4145 /* disable speaker*/
4146 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4147 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4148 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4149 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4150 /* enable headphone*/
4151 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4152 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4153 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4154 pin_ctl | PIN_HP);
5aaca44d
IM		 4155 }
4156
4157exit:
664c7155 4158 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4159
4160 return err < 0 ? err : 0;
4161}
4162
212de2e7 4163static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
d51434d4 4164static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
8e6bc6b3 4165static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
212de2e7 4166
2283c85b
CM		 4167static void ae5_mmio_select_out(struct hda_codec *codec)
4168{
4169 struct ca0132_spec *spec = codec->spec;
4170 unsigned int i;
4171
4172 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++)
4173 ca0113_mmio_command_set(codec,
4174 ae5_ca0113_output_presets[spec->cur_out_type].group[i],
4175 ae5_ca0113_output_presets[spec->cur_out_type].target[i],
4176 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]);
4177}
4178
746fc9de
CM		 4179/*
4180 * These are the commands needed to setup output on each of the different card
4181 * types.
4182 */
4183static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4184{
4185 struct ca0132_spec *spec = codec->spec;
2283c85b 4186 unsigned int tmp;
746fc9de
CM		 4187
4188 switch (spec->cur_out_type) {
4189 case SPEAKER_OUT:
6da8f446 4190 switch (ca0132_quirk(spec)) {
746fc9de
CM		 4191 case QUIRK_SBZ:
4192 ca0113_mmio_gpio_set(codec, 7, false);
4193 ca0113_mmio_gpio_set(codec, 4, true);
4194 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4195 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de 4196 break;
55845949
CM		 4197 case QUIRK_ZXR:
4198 ca0113_mmio_gpio_set(codec, 2, true);
4199 ca0113_mmio_gpio_set(codec, 3, true);
4200 ca0113_mmio_gpio_set(codec, 5, false);
d51434d4 4201 zxr_headphone_gain_set(codec, 0);
55845949
CM		 4202 chipio_set_control_param(codec, 0x0d, 0x24);
4203 break;
746fc9de 4204 case QUIRK_R3DI:
2283c85b 4205 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4206 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4207 break;
4208 case QUIRK_R3D:
2283c85b 4209 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4210 ca0113_mmio_gpio_set(codec, 1, true);
4211 break;
2283c85b
CM		 4212 case QUIRK_AE5:
4213 ae5_mmio_select_out(codec);
212de2e7 4214 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4215 tmp = FLOAT_ZERO;
4216 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4217 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4218 chipio_set_control_param(codec, 0x0d, 0xa4);
4219 chipio_write(codec, 0x18b03c, 0x00000012);
4220 break;
6da8f446
TI		 4221 default:
4222 break;
746fc9de
CM		 4223 }
4224 break;
4225 case HEADPHONE_OUT:
6da8f446 4226 switch (ca0132_quirk(spec)) {
746fc9de
CM		 4227 case QUIRK_SBZ:
4228 ca0113_mmio_gpio_set(codec, 7, true);
4229 ca0113_mmio_gpio_set(codec, 4, true);
4230 ca0113_mmio_gpio_set(codec, 1, false);
2283c85b 4231 chipio_set_control_param(codec, 0x0d, 0x12);
746fc9de 4232 break;
55845949
CM		 4233 case QUIRK_ZXR:
4234 ca0113_mmio_gpio_set(codec, 2, false);
4235 ca0113_mmio_gpio_set(codec, 3, false);
4236 ca0113_mmio_gpio_set(codec, 5, true);
d51434d4 4237 zxr_headphone_gain_set(codec, spec->zxr_gain_set);
55845949
CM		 4238 chipio_set_control_param(codec, 0x0d, 0x21);
4239 break;
746fc9de 4240 case QUIRK_R3DI:
2283c85b 4241 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4242 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4243 break;
4244 case QUIRK_R3D:
2283c85b 4245 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4246 ca0113_mmio_gpio_set(codec, 0x1, false);
4247 break;
2283c85b
CM		 4248 case QUIRK_AE5:
4249 ae5_mmio_select_out(codec);
212de2e7
CM		 4250 ae5_headphone_gain_set(codec,
4251 spec->ae5_headphone_gain_val);
2283c85b
CM		 4252 tmp = FLOAT_ONE;
4253 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4254 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4255 chipio_set_control_param(codec, 0x0d, 0xa1);
4256 chipio_write(codec, 0x18b03c, 0x00000012);
4257 break;
6da8f446
TI		 4258 default:
4259 break;
746fc9de
CM		 4260 }
4261 break;
4262 case SURROUND_OUT:
6da8f446 4263 switch (ca0132_quirk(spec)) {
746fc9de
CM		 4264 case QUIRK_SBZ:
4265 ca0113_mmio_gpio_set(codec, 7, false);
4266 ca0113_mmio_gpio_set(codec, 4, true);
4267 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4268 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de 4269 break;
55845949
CM		 4270 case QUIRK_ZXR:
4271 ca0113_mmio_gpio_set(codec, 2, true);
4272 ca0113_mmio_gpio_set(codec, 3, true);
4273 ca0113_mmio_gpio_set(codec, 5, false);
d51434d4 4274 zxr_headphone_gain_set(codec, 0);
55845949
CM		 4275 chipio_set_control_param(codec, 0x0d, 0x24);
4276 break;
746fc9de 4277 case QUIRK_R3DI:
2283c85b 4278 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4279 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4280 break;
4281 case QUIRK_R3D:
4282 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b
CM		 4283 chipio_set_control_param(codec, 0x0d, 0x24);
4284 break;
4285 case QUIRK_AE5:
4286 ae5_mmio_select_out(codec);
212de2e7 4287 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4288 tmp = FLOAT_ZERO;
4289 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4290 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4291 chipio_set_control_param(codec, 0x0d, 0xa4);
4292 chipio_write(codec, 0x18b03c, 0x00000012);
746fc9de 4293 break;
6da8f446
TI		 4294 default:
4295 break;
746fc9de
CM		 4296 }
4297 break;
4298 }
4299}
4300
7cb9d94c
CM		 4301/*
4302 * This function behaves similarly to the ca0132_select_out funciton above,
4303 * except with a few differences. It adds the ability to select the current
4304 * output with an enumerated control "output source" if the auto detect
4305 * mute switch is set to off. If the auto detect mute switch is enabled, it
4306 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4307 * It also adds the ability to auto-detect the front headphone port. The only
4308 * way to select surround is to disable auto detect, and set Surround with the
4309 * enumerated control.
4310 */
4311static int ca0132_alt_select_out(struct hda_codec *codec)
4312{
4313 struct ca0132_spec *spec = codec->spec;
4314 unsigned int pin_ctl;
4315 int jack_present;
4316 int auto_jack;
4317 unsigned int i;
4318 unsigned int tmp;
4319 int err;
4320 /* Default Headphone is rear headphone */
4321 hda_nid_t headphone_nid = spec->out_pins[1];
4322
4323 codec_dbg(codec, "%s\n", __func__);
4324
4325 snd_hda_power_up_pm(codec);
4326
4327 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4328
4329 /*
4330 * If headphone rear or front is plugged in, set to headphone.
4331 * If neither is plugged in, set to rear line out. Only if
4332 * hp/speaker auto detect is enabled.
4333 */
4334 if (auto_jack) {
4335 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4336 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4337
4338 if (jack_present)
4339 spec->cur_out_type = HEADPHONE_OUT;
4340 else
4341 spec->cur_out_type = SPEAKER_OUT;
4342 } else
4343 spec->cur_out_type = spec->out_enum_val;
4344
4345 /* Begin DSP output switch */
4346 tmp = FLOAT_ONE;
4347 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4348 if (err < 0)
4349 goto exit;
4350
746fc9de
CM		 4351 ca0132_alt_select_out_quirk_handler(codec);
4352
7cb9d94c
CM		 4353 switch (spec->cur_out_type) {
4354 case SPEAKER_OUT:
4355 codec_dbg(codec, "%s speaker\n", __func__);
7cb9d94c
CM		 4356
4357 /* disable headphone node */
4358 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4359 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4360 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4361 pin_ctl & ~PIN_HP);
4362 /* enable line-out node */
4363 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4364 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4365 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4366 pin_ctl | PIN_OUT);
4367 /* Enable EAPD */
4368 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4369 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4370
4371 /* If PlayEnhancement is enabled, set different source */
4372 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4373 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4374 else
4375 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4376 break;
4377 case HEADPHONE_OUT:
4378 codec_dbg(codec, "%s hp\n", __func__);
7cb9d94c
CM		 4379
4380 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4381 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4382
4383 /* disable speaker*/
4384 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4385 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4386 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4387 pin_ctl & ~PIN_HP);
4388
4389 /* enable headphone, either front or rear */
4390
4391 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4392 headphone_nid = spec->out_pins[2];
4393 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4394 headphone_nid = spec->out_pins[1];
4395
4396 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4397 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4398 snd_hda_set_pin_ctl(codec, headphone_nid,
4399 pin_ctl | PIN_HP);
4400
4401 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4402 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4403 else
4404 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4405 break;
4406 case SURROUND_OUT:
4407 codec_dbg(codec, "%s surround\n", __func__);
746fc9de 4408
7cb9d94c
CM		 4409 /* enable line out node */
4410 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4411 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4412 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4413 pin_ctl | PIN_OUT);
4414 /* Disable headphone out */
4415 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4416 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4417 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4418 pin_ctl & ~PIN_HP);
4419 /* Enable EAPD on line out */
4420 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4421 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4422 /* enable center/lfe out node */
4423 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4424 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4425 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4426 pin_ctl | PIN_OUT);
4427 /* Now set rear surround node as out. */
4428 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4429 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4430 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4431 pin_ctl | PIN_OUT);
4432
8e6bc6b3 4433 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
7cb9d94c
CM		 4434 break;
4435 }
8e6bc6b3
CM		 4436 /*
4437 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT.
4438 * With this set though, X_BASS cannot be enabled. So, if we have OutFX
4439 * enabled, we need to make sure X_BASS is off, otherwise everything
4440 * sounds all muffled. Running ca0132_effects_set with X_BASS as the
4441 * effect should sort this out.
4442 */
4443 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4444 ca0132_effects_set(codec, X_BASS,
4445 spec->effects_switch[X_BASS - EFFECT_START_NID]);
7cb9d94c 4446
2283c85b 4447 /* run through the output dsp commands for the selected output. */
7cb9d94c
CM		 4448 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4449 err = dspio_set_uint_param(codec,
4450 alt_out_presets[spec->cur_out_type].mids[i],
4451 alt_out_presets[spec->cur_out_type].reqs[i],
4452 alt_out_presets[spec->cur_out_type].vals[i]);
4453
4454 if (err < 0)
4455 goto exit;
4456 }
4457
4458exit:
4459 snd_hda_power_down_pm(codec);
4460
4461 return err < 0 ? err : 0;
4462}
4463
993884f6
CCC		 4464static void ca0132_unsol_hp_delayed(struct work_struct *work)
4465{
4466 struct ca0132_spec *spec = container_of(
4467 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4468 struct hda_jack_tbl *jack;
4469
6da8f446 4470 if (ca0132_use_alt_functions(spec))
7cb9d94c
CM		 4471 ca0132_alt_select_out(spec->codec);
4472 else
4473 ca0132_select_out(spec->codec);
4474
d5c016b5 4475 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4476 if (jack) {
4477 jack->block_report = 0;
4478 snd_hda_jack_report_sync(spec->codec);
4479 }
993884f6
CCC		 4480}
4481
5aaca44d
IM		 4482static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4483static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
e0026d03
CM		 4484static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4485static int stop_mic1(struct hda_codec *codec);
4486static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4487static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4488
4489/*
4490 * Select the active VIP source
4491 */
4492static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4493{
4494 struct ca0132_spec *spec = codec->spec;
4495 unsigned int tmp;
4496
e8f1bd5d 4497 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4498 return 0;
4499
4500 /* if CrystalVoice if off, vipsource should be 0 */
4501 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4502 (val == 0)) {
4503 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4504 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4505 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4506 if (spec->cur_mic_type == DIGITAL_MIC)
4507 tmp = FLOAT_TWO;
4508 else
4509 tmp = FLOAT_ONE;
4510 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4511 tmp = FLOAT_ZERO;
4512 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4513 } else {
4514 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4515 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4516 if (spec->cur_mic_type == DIGITAL_MIC)
4517 tmp = FLOAT_TWO;
4518 else
4519 tmp = FLOAT_ONE;
4520 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4521 tmp = FLOAT_ONE;
4522 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4523 msleep(20);
4524 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4525 }
4526
4527 return 1;
4528}
4529
e0026d03
CM		 4530static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4531{
4532 struct ca0132_spec *spec = codec->spec;
4533 unsigned int tmp;
4534
4535 if (spec->dsp_state != DSP_DOWNLOADED)
4536 return 0;
4537
4538 codec_dbg(codec, "%s\n", __func__);
4539
4540 chipio_set_stream_control(codec, 0x03, 0);
4541 chipio_set_stream_control(codec, 0x04, 0);
4542
4543 /* if CrystalVoice is off, vipsource should be 0 */
4544 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4545 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4546 codec_dbg(codec, "%s: off.", __func__);
4547 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4548
4549 tmp = FLOAT_ZERO;
4550 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4551
4552 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4553 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 4554 if (ca0132_quirk(spec) == QUIRK_R3DI)
e0026d03
CM		 4555 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4556
4557
4558 if (spec->in_enum_val == REAR_LINE_IN)
4559 tmp = FLOAT_ZERO;
4560 else {
6da8f446 4561 if (ca0132_quirk(spec) == QUIRK_SBZ)
e0026d03
CM		 4562 tmp = FLOAT_THREE;
4563 else
4564 tmp = FLOAT_ONE;
4565 }
4566
4567 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4568
4569 } else {
4570 codec_dbg(codec, "%s: on.", __func__);
4571 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4572 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
6da8f446 4573 if (ca0132_quirk(spec) == QUIRK_R3DI)
e0026d03
CM		 4574 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4575
4576 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4577 tmp = FLOAT_TWO;
4578 else
4579 tmp = FLOAT_ONE;
4580 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4581
4582 tmp = FLOAT_ONE;
4583 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4584
4585 msleep(20);
4586 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4587 }
4588
4589 chipio_set_stream_control(codec, 0x03, 1);
4590 chipio_set_stream_control(codec, 0x04, 1);
4591
4592 return 1;
4593}
4594
5aaca44d
IM		 4595/*
4596 * Select the active microphone.
4597 * If autodetect is enabled, mic will be selected based on jack detection.
4598 * If jack inserted, ext.mic will be selected, else built-in mic
4599 * If autodetect is disabled, mic will be selected based on selection.
4600 */
4601static int ca0132_select_mic(struct hda_codec *codec)
4602{
4603 struct ca0132_spec *spec = codec->spec;
4604 int jack_present;
4605 int auto_jack;
4606
4e76a883 4607 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4608
664c7155 4609 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4610
4611 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4612
4613 if (auto_jack)
fe14f39e 4614 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4615 else
4616 jack_present =
4617 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4618
4619 if (jack_present)
4620 spec->cur_mic_type = LINE_MIC_IN;
4621 else
4622 spec->cur_mic_type = DIGITAL_MIC;
4623
4624 if (spec->cur_mic_type == DIGITAL_MIC) {
4625 /* enable digital Mic */
4626 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4627 ca0132_set_dmic(codec, 1);
4628 ca0132_mic_boost_set(codec, 0);
4629 /* set voice focus */
4630 ca0132_effects_set(codec, VOICE_FOCUS,
4631 spec->effects_switch
4632 [VOICE_FOCUS - EFFECT_START_NID]);
4633 } else {
4634 /* disable digital Mic */
4635 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4636 ca0132_set_dmic(codec, 0);
4637 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4638 /* disable voice focus */
4639 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4640 }
4641
664c7155 4642 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4643
4644 return 0;
4645}
4646
7cb9d94c
CM		 4647/*
4648 * Select the active input.
4649 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4650 * The front mic has no jack-detection, so the only way to switch to it
4651 * is to do it manually in alsamixer.
4652 */
4653static int ca0132_alt_select_in(struct hda_codec *codec)
4654{
4655 struct ca0132_spec *spec = codec->spec;
4656 unsigned int tmp;
4657
4658 codec_dbg(codec, "%s\n", __func__);
4659
4660 snd_hda_power_up_pm(codec);
4661
4662 chipio_set_stream_control(codec, 0x03, 0);
4663 chipio_set_stream_control(codec, 0x04, 0);
4664
4665 spec->cur_mic_type = spec->in_enum_val;
4666
4667 switch (spec->cur_mic_type) {
4668 case REAR_MIC:
6da8f446 4669 switch (ca0132_quirk(spec)) {
7cb9d94c 4670 case QUIRK_SBZ:
42aa3a16 4671 case QUIRK_R3D:
b9b41345 4672 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4673 tmp = FLOAT_THREE;
4674 break;
55845949
CM		 4675 case QUIRK_ZXR:
4676 tmp = FLOAT_THREE;
4677 break;
7cb9d94c
CM		 4678 case QUIRK_R3DI:
4679 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4680 tmp = FLOAT_ONE;
4681 break;
f231daaf
CM		 4682 case QUIRK_AE5:
4683 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4684 tmp = FLOAT_THREE;
4685 break;
7cb9d94c
CM		 4686 default:
4687 tmp = FLOAT_ONE;
4688 break;
4689 }
4690
4691 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4692 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 4693 if (ca0132_quirk(spec) == QUIRK_R3DI)
7cb9d94c
CM		 4694 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4695
4696 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4697
4698 chipio_set_stream_control(codec, 0x03, 1);
4699 chipio_set_stream_control(codec, 0x04, 1);
6da8f446 4700 switch (ca0132_quirk(spec)) {
f231daaf 4701 case QUIRK_SBZ:
7cb9d94c
CM		 4702 chipio_write(codec, 0x18B098, 0x0000000C);
4703 chipio_write(codec, 0x18B09C, 0x0000000C);
f231daaf 4704 break;
55845949
CM		 4705 case QUIRK_ZXR:
4706 chipio_write(codec, 0x18B098, 0x0000000C);
4707 chipio_write(codec, 0x18B09C, 0x000000CC);
4708 break;
f231daaf
CM		 4709 case QUIRK_AE5:
4710 chipio_write(codec, 0x18B098, 0x0000000C);
4711 chipio_write(codec, 0x18B09C, 0x0000004C);
4712 break;
6da8f446
TI		 4713 default:
4714 break;
7cb9d94c 4715 }
47cdf76e 4716 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4717 break;
4718 case REAR_LINE_IN:
4719 ca0132_mic_boost_set(codec, 0);
6da8f446 4720 switch (ca0132_quirk(spec)) {
7cb9d94c 4721 case QUIRK_SBZ:
42aa3a16 4722 case QUIRK_R3D:
b9b41345 4723 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4724 break;
4725 case QUIRK_R3DI:
4726 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4727 break;
f231daaf
CM		 4728 case QUIRK_AE5:
4729 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4730 break;
6da8f446
TI		 4731 default:
4732 break;
7cb9d94c
CM		 4733 }
4734
4735 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4736 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 4737 if (ca0132_quirk(spec) == QUIRK_R3DI)
7cb9d94c
CM		 4738 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4739
4740 tmp = FLOAT_ZERO;
4741 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4742
6da8f446 4743 switch (ca0132_quirk(spec)) {
f231daaf
CM		 4744 case QUIRK_SBZ:
4745 case QUIRK_AE5:
7cb9d94c
CM		 4746 chipio_write(codec, 0x18B098, 0x00000000);
4747 chipio_write(codec, 0x18B09C, 0x00000000);
f231daaf 4748 break;
6da8f446
TI		 4749 default:
4750 break;
7cb9d94c 4751 }
7cb9d94c
CM		 4752 chipio_set_stream_control(codec, 0x03, 1);
4753 chipio_set_stream_control(codec, 0x04, 1);
4754 break;
4755 case FRONT_MIC:
6da8f446 4756 switch (ca0132_quirk(spec)) {
7cb9d94c 4757 case QUIRK_SBZ:
42aa3a16 4758 case QUIRK_R3D:
b9b41345
CM		 4759 ca0113_mmio_gpio_set(codec, 0, true);
4760 ca0113_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4761 tmp = FLOAT_THREE;
4762 break;
4763 case QUIRK_R3DI:
4764 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4765 tmp = FLOAT_ONE;
4766 break;
f231daaf
CM		 4767 case QUIRK_AE5:
4768 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f);
4769 tmp = FLOAT_THREE;
4770 break;
7cb9d94c
CM		 4771 default:
4772 tmp = FLOAT_ONE;
4773 break;
4774 }
4775
4776 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4777 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 4778 if (ca0132_quirk(spec) == QUIRK_R3DI)
7cb9d94c
CM		 4779 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4780
4781 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4782
4783 chipio_set_stream_control(codec, 0x03, 1);
4784 chipio_set_stream_control(codec, 0x04, 1);
4785
6da8f446 4786 switch (ca0132_quirk(spec)) {
f231daaf 4787 case QUIRK_SBZ:
7cb9d94c
CM		 4788 chipio_write(codec, 0x18B098, 0x0000000C);
4789 chipio_write(codec, 0x18B09C, 0x000000CC);
f231daaf
CM		 4790 break;
4791 case QUIRK_AE5:
4792 chipio_write(codec, 0x18B098, 0x0000000C);
4793 chipio_write(codec, 0x18B09C, 0x0000004C);
4794 break;
6da8f446
TI		 4795 default:
4796 break;
7cb9d94c 4797 }
47cdf76e 4798 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4799 break;
4800 }
e0026d03 4801 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4802
4803 snd_hda_power_down_pm(codec);
4804 return 0;
7cb9d94c
CM		 4805}
4806
a7e76271
IM		 4807/*
4808 * Check if VNODE settings take effect immediately.
4809 */
4810static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4811 hda_nid_t vnid,
4812 hda_nid_t *shared_nid)
4813{
4814 struct ca0132_spec *spec = codec->spec;
4815 hda_nid_t nid;
a7e76271
IM		 4816
4817 switch (vnid) {
4818 case VNID_SPK:
4819 nid = spec->shared_out_nid;
a7e76271
IM		 4820 break;
4821 case VNID_MIC:
4822 nid = spec->shared_mic_nid;
a7e76271
IM		 4823 break;
4824 default:
9a0869f4 4825 return false;
a7e76271
IM		 4826 }
4827
9a0869f4 4828 if (shared_nid)
a7e76271
IM		 4829 *shared_nid = nid;
4830
9a0869f4 4831 return true;
a7e76271
IM		 4832}
4833
4834/*
4835* The following functions are control change helpers.
4836* They return 0 if no changed. Return 1 if changed.
4837*/
4838static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4839{
4840 struct ca0132_spec *spec = codec->spec;
4841 unsigned int tmp;
4842
4843 /* based on CrystalVoice state to enable VoiceFX. */
4844 if (enable) {
4845 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4846 FLOAT_ONE : FLOAT_ZERO;
4847 } else {
4848 tmp = FLOAT_ZERO;
4849 }
4850
4851 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4852 ca0132_voicefx.reqs[0], tmp);
4853
4854 return 1;
4855}
4856
5aaca44d
IM		 4857/*
4858 * Set the effects parameters
4859 */
4860static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4861{
4862 struct ca0132_spec *spec = codec->spec;
009b8f97 4863 unsigned int on, tmp;
5aaca44d
IM		 4864 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4865 int err = 0;
4866 int idx = nid - EFFECT_START_NID;
4867
4868 if ((idx < 0) || (idx >= num_fx))
4869 return 0; /* no changed */
4870
4871 /* for out effect, qualify with PE */
4872 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4873 /* if PE if off, turn off out effects. */
4874 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4875 val = 0;
8e6bc6b3
CM		 4876 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS)
4877 val = 0;
5aaca44d
IM		 4878 }
4879
4880 /* for in effect, qualify with CrystalVoice */
4881 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4882 /* if CrystalVoice if off, turn off in effects. */
4883 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4884 val = 0;
4885
4886 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4887 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4888 val = 0;
009b8f97
CM		 4889
4890 /* If Voice Focus on SBZ, set to two channel. */
6da8f446 4891 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
7cb9d94c 4892 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4893 if (spec->effects_switch[CRYSTAL_VOICE -
4894 EFFECT_START_NID]) {
4895
4896 if (spec->effects_switch[VOICE_FOCUS -
4897 EFFECT_START_NID]) {
4898 tmp = FLOAT_TWO;
4899 val = 1;
4900 } else
4901 tmp = FLOAT_ONE;
4902
4903 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4904 }
4905 }
4906 /*
4907 * For SBZ noise reduction, there's an extra command
4908 * to module ID 0x47. No clue why.
4909 */
6da8f446 4910 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
7cb9d94c 4911 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4912 if (spec->effects_switch[CRYSTAL_VOICE -
4913 EFFECT_START_NID]) {
4914 if (spec->effects_switch[NOISE_REDUCTION -
4915 EFFECT_START_NID])
4916 tmp = FLOAT_ONE;
4917 else
4918 tmp = FLOAT_ZERO;
4919 } else
4920 tmp = FLOAT_ZERO;
4921
4922 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4923 }
7cb9d94c
CM		 4924
4925 /* If rear line in disable effects. */
6da8f446 4926 if (ca0132_use_alt_functions(spec) &&
7cb9d94c
CM		 4927 spec->in_enum_val == REAR_LINE_IN)
4928 val = 0;
5aaca44d
IM		 4929 }
4930
4e76a883 4931 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4932 nid, val);
4933
4934 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4935 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4936 ca0132_effects[idx].reqs[0], on);
4937
4938 if (err < 0)
4939 return 0; /* no changed */
4940
4941 return 1;
4942}
4943
a7e76271
IM		 4944/*
4945 * Turn on/off Playback Enhancements
4946 */
4947static int ca0132_pe_switch_set(struct hda_codec *codec)
4948{
4949 struct ca0132_spec *spec = codec->spec;
4950 hda_nid_t nid;
4951 int i, ret = 0;
4952
4e76a883 4953 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4954 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4955
6da8f446 4956 if (ca0132_use_alt_functions(spec))
7cb9d94c
CM		 4957 ca0132_alt_select_out(codec);
4958
a7e76271
IM		 4959 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4960 nid = OUT_EFFECT_START_NID;
4961 /* PE affects all out effects */
4962 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4963 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4964
4965 return ret;
4966}
4967
5aaca44d
IM		 4968/* Check if Mic1 is streaming, if so, stop streaming */
4969static int stop_mic1(struct hda_codec *codec)
4970{
4971 struct ca0132_spec *spec = codec->spec;
4972 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4973 AC_VERB_GET_CONV, 0);
4974 if (oldval != 0)
4975 snd_hda_codec_write(codec, spec->adcs[0], 0,
4976 AC_VERB_SET_CHANNEL_STREAMID,
4977 0);
4978 return oldval;
4979}
4980
4981/* Resume Mic1 streaming if it was stopped. */
4982static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4983{
4984 struct ca0132_spec *spec = codec->spec;
4985 /* Restore the previous stream and channel */
4986 if (oldval != 0)
4987 snd_hda_codec_write(codec, spec->adcs[0], 0,
4988 AC_VERB_SET_CHANNEL_STREAMID,
4989 oldval);
4990}
4991
4992/*
a7e76271 4993 * Turn on/off CrystalVoice
5aaca44d 4994 */
a7e76271
IM		 4995static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4996{
4997 struct ca0132_spec *spec = codec->spec;
4998 hda_nid_t nid;
4999 int i, ret = 0;
5000 unsigned int oldval;
5001
4e76a883 5002 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 5003 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5004
5005 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5006 nid = IN_EFFECT_START_NID;
5007 /* CrystalVoice affects all in effects */
5008 for (; nid < IN_EFFECT_END_NID; nid++, i++)
5009 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5010
5011 /* including VoiceFX */
5012 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5013
5014 /* set correct vipsource */
5015 oldval = stop_mic1(codec);
6da8f446 5016 if (ca0132_use_alt_functions(spec))
e0026d03
CM		 5017 ret |= ca0132_alt_set_vipsource(codec, 1);
5018 else
5019 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 5020 resume_mic1(codec, oldval);
5021 return ret;
5022}
5023
5aaca44d
IM		 5024static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5025{
5026 struct ca0132_spec *spec = codec->spec;
5027 int ret = 0;
5028
5029 if (val) /* on */
5030 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5031 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5032 else /* off */
5033 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5034 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5035
5036 return ret;
5037}
5038
47cdf76e
CM		 5039static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5040{
5041 struct ca0132_spec *spec = codec->spec;
5042 int ret = 0;
5043
5044 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5045 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5046 return ret;
5047}
5048
212de2e7
CM		 5049static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5050{
5051 unsigned int i;
5052
5053 for (i = 0; i < 4; i++)
5054 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5055 ae5_headphone_gain_presets[val].vals[i]);
5056 return 0;
5057}
5058
d51434d4
CM		 5059/*
5060 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5061 * amplifier to handle a 600 ohm load.
5062 */
5063static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5064{
5065 ca0113_mmio_gpio_set(codec, 1, val);
5066
5067 return 0;
5068}
5069
a7e76271
IM		 5070static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5071 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 5072{
a7e76271
IM		 5073 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5074 hda_nid_t nid = get_amp_nid(kcontrol);
5075 hda_nid_t shared_nid = 0;
5076 bool effective;
5077 int ret = 0;
95c6e9cb 5078 struct ca0132_spec *spec = codec->spec;
a7e76271 5079 int auto_jack;
95c6e9cb 5080
a7e76271
IM		 5081 if (nid == VNID_HP_SEL) {
5082 auto_jack =
5083 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c 5084 if (!auto_jack) {
6da8f446 5085 if (ca0132_use_alt_functions(spec))
7cb9d94c
CM		 5086 ca0132_alt_select_out(codec);
5087 else
5088 ca0132_select_out(codec);
5089 }
a7e76271
IM		 5090 return 1;
5091 }
95c6e9cb 5092
a7e76271
IM		 5093 if (nid == VNID_AMIC1_SEL) {
5094 auto_jack =
5095 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5096 if (!auto_jack)
5097 ca0132_select_mic(codec);
5098 return 1;
5099 }
95c6e9cb 5100
a7e76271 5101 if (nid == VNID_HP_ASEL) {
6da8f446 5102 if (ca0132_use_alt_functions(spec))
7cb9d94c
CM		 5103 ca0132_alt_select_out(codec);
5104 else
5105 ca0132_select_out(codec);
a7e76271
IM		 5106 return 1;
5107 }
95c6e9cb 5108
a7e76271
IM		 5109 if (nid == VNID_AMIC1_ASEL) {
5110 ca0132_select_mic(codec);
5111 return 1;
95c6e9cb 5112 }
a7e76271
IM		 5113
5114 /* if effective conditions, then update hw immediately. */
5115 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5116 if (effective) {
5117 int dir = get_amp_direction(kcontrol);
5118 int ch = get_amp_channels(kcontrol);
5119 unsigned long pval;
5120
5121 mutex_lock(&codec->control_mutex);
5122 pval = kcontrol->private_value;
5123 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5124 0, dir);
5125 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5126 kcontrol->private_value = pval;
5127 mutex_unlock(&codec->control_mutex);
95c6e9cb 5128 }
95c6e9cb 5129
a7e76271 5130 return ret;
95c6e9cb 5131}
a7e76271 5132/* End of control change helpers. */
47cdf76e
CM		 5133/*
5134 * Below I've added controls to mess with the effect levels, I've only enabled
5135 * them on the Sound Blaster Z, but they would probably also work on the
5136 * Chromebook. I figured they were probably tuned specifically for it, and left
5137 * out for a reason.
5138 */
5139
5140/* Sets DSP effect level from the sliders above the controls */
5141static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5142 const unsigned int *lookup, int idx)
5143{
5144 int i = 0;
5145 unsigned int y;
5146 /*
5147 * For X_BASS, req 2 is actually crossover freq instead of
5148 * effect level
5149 */
5150 if (nid == X_BASS)
5151 y = 2;
5152 else
5153 y = 1;
5154
5155 snd_hda_power_up(codec);
5156 if (nid == XBASS_XOVER) {
5157 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5158 if (ca0132_effects[i].nid == X_BASS)
5159 break;
5160
5161 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5162 ca0132_effects[i].reqs[1],
5163 &(lookup[idx - 1]), sizeof(unsigned int));
5164 } else {
5165 /* Find the actual effect structure */
5166 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5167 if (nid == ca0132_effects[i].nid)
5168 break;
5169
5170 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5171 ca0132_effects[i].reqs[y],
5172 &(lookup[idx]), sizeof(unsigned int));
5173 }
5174
5175 snd_hda_power_down(codec);
5176
5177 return 0;
5178}
5179
5180static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5181 struct snd_ctl_elem_value *ucontrol)
5182{
5183 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5184 struct ca0132_spec *spec = codec->spec;
5185 long *valp = ucontrol->value.integer.value;
5186
5187 *valp = spec->xbass_xover_freq;
5188 return 0;
5189}
5190
5191static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5192 struct snd_ctl_elem_value *ucontrol)
5193{
5194 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5195 struct ca0132_spec *spec = codec->spec;
5196 hda_nid_t nid = get_amp_nid(kcontrol);
5197 long *valp = ucontrol->value.integer.value;
5198 int idx = nid - OUT_EFFECT_START_NID;
5199
5200 *valp = spec->fx_ctl_val[idx];
5201 return 0;
5202}
5203
5204/*
5205 * The X-bass crossover starts at 10hz, so the min is 1. The
5206 * frequency is set in multiples of 10.
5207 */
5208static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5209 struct snd_ctl_elem_info *uinfo)
5210{
5211 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5212 uinfo->count = 1;
5213 uinfo->value.integer.min = 1;
5214 uinfo->value.integer.max = 100;
5215 uinfo->value.integer.step = 1;
5216
5217 return 0;
5218}
5219
5220static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5221 struct snd_ctl_elem_info *uinfo)
5222{
5223 int chs = get_amp_channels(kcontrol);
5224
5225 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5226 uinfo->count = chs == 3 ? 2 : 1;
5227 uinfo->value.integer.min = 0;
5228 uinfo->value.integer.max = 100;
5229 uinfo->value.integer.step = 1;
5230
5231 return 0;
5232}
5233
5234static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5235 struct snd_ctl_elem_value *ucontrol)
5236{
5237 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5238 struct ca0132_spec *spec = codec->spec;
5239 hda_nid_t nid = get_amp_nid(kcontrol);
5240 long *valp = ucontrol->value.integer.value;
5241 int idx;
5242
5243 /* any change? */
5244 if (spec->xbass_xover_freq == *valp)
5245 return 0;
5246
5247 spec->xbass_xover_freq = *valp;
5248
5249 idx = *valp;
5250 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5251
5252 return 0;
5253}
5254
5255static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5256 struct snd_ctl_elem_value *ucontrol)
5257{
5258 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5259 struct ca0132_spec *spec = codec->spec;
5260 hda_nid_t nid = get_amp_nid(kcontrol);
5261 long *valp = ucontrol->value.integer.value;
5262 int idx;
5263
5264 idx = nid - EFFECT_START_NID;
5265 /* any change? */
5266 if (spec->fx_ctl_val[idx] == *valp)
5267 return 0;
5268
5269 spec->fx_ctl_val[idx] = *valp;
5270
5271 idx = *valp;
5272 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5273
5274 return 0;
5275}
5276
5277
5278/*
5279 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5280 * only has off or full 30 dB, and didn't like making a volume slider that has
5281 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5282 */
5283#define MIC_BOOST_NUM_OF_STEPS 4
5284#define MIC_BOOST_ENUM_MAX_STRLEN 10
5285
5286static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5287 struct snd_ctl_elem_info *uinfo)
5288{
5289 char *sfx = "dB";
5290 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5291
5292 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5293 uinfo->count = 1;
5294 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5295 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5296 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5297 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5298 strcpy(uinfo->value.enumerated.name, namestr);
5299 return 0;
5300}
5301
5302static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5303 struct snd_ctl_elem_value *ucontrol)
5304{
5305 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5306 struct ca0132_spec *spec = codec->spec;
5307
5308 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5309 return 0;
5310}
5311
5312static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5313 struct snd_ctl_elem_value *ucontrol)
5314{
5315 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5316 struct ca0132_spec *spec = codec->spec;
5317 int sel = ucontrol->value.enumerated.item[0];
5318 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5319
5320 if (sel >= items)
5321 return 0;
5322
5323 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5324 sel);
5325
5326 spec->mic_boost_enum_val = sel;
5327
5328 if (spec->in_enum_val != REAR_LINE_IN)
5329 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5330
5331 return 1;
5332}
5333
212de2e7
CM		 5334/*
5335 * Sound BlasterX AE-5 Headphone Gain Controls.
5336 */
5337#define AE5_HEADPHONE_GAIN_MAX 3
5338static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5339 struct snd_ctl_elem_info *uinfo)
5340{
5341 char *sfx = " Ohms)";
5342 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5343
5344 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5345 uinfo->count = 1;
5346 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5347 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5348 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5349 sprintf(namestr, "%s %s",
5350 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5351 sfx);
5352 strcpy(uinfo->value.enumerated.name, namestr);
5353 return 0;
5354}
5355
5356static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5357 struct snd_ctl_elem_value *ucontrol)
5358{
5359 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5360 struct ca0132_spec *spec = codec->spec;
5361
5362 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5363 return 0;
5364}
5365
5366static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5367 struct snd_ctl_elem_value *ucontrol)
5368{
5369 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5370 struct ca0132_spec *spec = codec->spec;
5371 int sel = ucontrol->value.enumerated.item[0];
5372 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5373
5374 if (sel >= items)
5375 return 0;
5376
5377 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5378 sel);
5379
5380 spec->ae5_headphone_gain_val = sel;
5381
5382 if (spec->out_enum_val == HEADPHONE_OUT)
5383 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5384
5385 return 1;
5386}
5387
5388/*
5389 * Sound BlasterX AE-5 sound filter enumerated control.
5390 */
5391#define AE5_SOUND_FILTER_MAX 3
5392
5393static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5394 struct snd_ctl_elem_info *uinfo)
5395{
5396 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5397
5398 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5399 uinfo->count = 1;
5400 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5401 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5402 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5403 sprintf(namestr, "%s",
5404 ae5_filter_presets[uinfo->value.enumerated.item].name);
5405 strcpy(uinfo->value.enumerated.name, namestr);
5406 return 0;
5407}
5408
5409static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5410 struct snd_ctl_elem_value *ucontrol)
5411{
5412 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5413 struct ca0132_spec *spec = codec->spec;
5414
5415 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5416 return 0;
5417}
5418
5419static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5420 struct snd_ctl_elem_value *ucontrol)
5421{
5422 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5423 struct ca0132_spec *spec = codec->spec;
5424 int sel = ucontrol->value.enumerated.item[0];
5425 unsigned int items = AE5_SOUND_FILTER_MAX;
5426
5427 if (sel >= items)
5428 return 0;
5429
5430 codec_dbg(codec, "ae5_sound_filter: %s\n",
5431 ae5_filter_presets[sel].name);
5432
5433 spec->ae5_filter_val = sel;
5434
5435 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5436 ae5_filter_presets[sel].val);
5437
5438 return 1;
5439}
95c6e9cb 5440
7cb9d94c
CM		 5441/*
5442 * Input Select Control for alternative ca0132 codecs. This exists because
5443 * front microphone has no auto-detect, and we need a way to set the rear
5444 * as line-in
5445 */
5446static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5447 struct snd_ctl_elem_info *uinfo)
5448{
5449 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5450 uinfo->count = 1;
5451 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5452 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5453 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5454 strcpy(uinfo->value.enumerated.name,
5455 in_src_str[uinfo->value.enumerated.item]);
5456 return 0;
5457}
5458
5459static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5460 struct snd_ctl_elem_value *ucontrol)
5461{
5462 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5463 struct ca0132_spec *spec = codec->spec;
5464
5465 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5466 return 0;
5467}
5468
5469static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5470 struct snd_ctl_elem_value *ucontrol)
5471{
5472 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5473 struct ca0132_spec *spec = codec->spec;
5474 int sel = ucontrol->value.enumerated.item[0];
5475 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5476
5477 if (sel >= items)
5478 return 0;
5479
5480 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5481 sel, in_src_str[sel]);
5482
5483 spec->in_enum_val = sel;
5484
5485 ca0132_alt_select_in(codec);
5486
5487 return 1;
5488}
5489
5490/* Sound Blaster Z Output Select Control */
5491static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5492 struct snd_ctl_elem_info *uinfo)
5493{
5494 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5495 uinfo->count = 1;
5496 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5497 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5498 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5499 strcpy(uinfo->value.enumerated.name,
5500 alt_out_presets[uinfo->value.enumerated.item].name);
5501 return 0;
5502}
5503
5504static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5505 struct snd_ctl_elem_value *ucontrol)
5506{
5507 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5508 struct ca0132_spec *spec = codec->spec;
5509
5510 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5511 return 0;
5512}
5513
5514static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5515 struct snd_ctl_elem_value *ucontrol)
5516{
5517 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5518 struct ca0132_spec *spec = codec->spec;
5519 int sel = ucontrol->value.enumerated.item[0];
5520 unsigned int items = NUM_OF_OUTPUTS;
5521 unsigned int auto_jack;
5522
5523 if (sel >= items)
5524 return 0;
5525
5526 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5527 sel, alt_out_presets[sel].name);
5528
5529 spec->out_enum_val = sel;
5530
5531 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5532
5533 if (!auto_jack)
5534 ca0132_alt_select_out(codec);
5535
5536 return 1;
5537}
5538
47cdf76e
CM		 5539/*
5540 * Smart Volume output setting control. Three different settings, Normal,
5541 * which takes the value from the smart volume slider. The two others, loud
5542 * and night, disregard the slider value and have uneditable values.
5543 */
5544#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5545static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5546
5547static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5548 struct snd_ctl_elem_info *uinfo)
5549{
5550 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5551 uinfo->count = 1;
5552 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5553 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5554 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5555 strcpy(uinfo->value.enumerated.name,
5556 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5557 return 0;
5558}
5559
5560static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5561 struct snd_ctl_elem_value *ucontrol)
5562{
5563 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5564 struct ca0132_spec *spec = codec->spec;
5565
5566 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5567 return 0;
5568}
5569
5570static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5571 struct snd_ctl_elem_value *ucontrol)
5572{
5573 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5574 struct ca0132_spec *spec = codec->spec;
5575 int sel = ucontrol->value.enumerated.item[0];
5576 unsigned int items = NUM_OF_SVM_SETTINGS;
5577 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5578 unsigned int tmp;
5579
5580 if (sel >= items)
5581 return 0;
5582
5583 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5584 sel, out_svm_set_enum_str[sel]);
5585
5586 spec->smart_volume_setting = sel;
5587
5588 switch (sel) {
5589 case 0:
5590 tmp = FLOAT_ZERO;
5591 break;
5592 case 1:
5593 tmp = FLOAT_ONE;
5594 break;
5595 case 2:
5596 tmp = FLOAT_TWO;
5597 break;
5598 default:
5599 tmp = FLOAT_ZERO;
5600 break;
5601 }
5602 /* Req 2 is the Smart Volume Setting req. */
5603 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5604 ca0132_effects[idx].reqs[2], tmp);
5605 return 1;
5606}
5607
5608/* Sound Blaster Z EQ preset controls */
5609static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5610 struct snd_ctl_elem_info *uinfo)
5611{
c5f13d75 5612 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5613
5614 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5615 uinfo->count = 1;
5616 uinfo->value.enumerated.items = items;
5617 if (uinfo->value.enumerated.item >= items)
5618 uinfo->value.enumerated.item = items - 1;
5619 strcpy(uinfo->value.enumerated.name,
5620 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5621 return 0;
5622}
5623
5624static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5625 struct snd_ctl_elem_value *ucontrol)
5626{
5627 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5628 struct ca0132_spec *spec = codec->spec;
5629
5630 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5631 return 0;
5632}
5633
5634static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5635 struct snd_ctl_elem_value *ucontrol)
5636{
5637 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5638 struct ca0132_spec *spec = codec->spec;
5639 int i, err = 0;
5640 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5641 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5642
5643 if (sel >= items)
5644 return 0;
5645
5646 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5647 ca0132_alt_eq_presets[sel].name);
5648 /*
5649 * Idx 0 is default.
5650 * Default needs to qualify with CrystalVoice state.
5651 */
5652 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5653 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5654 ca0132_alt_eq_enum.reqs[i],
5655 ca0132_alt_eq_presets[sel].vals[i]);
5656 if (err < 0)
5657 break;
5658 }
5659
5660 if (err >= 0)
5661 spec->eq_preset_val = sel;
5662
5663 return 1;
5664}
5665
a7e76271
IM		 5666static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5667 struct snd_ctl_elem_info *uinfo)
5668{
a9291f46 5669 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5670
5671 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5672 uinfo->count = 1;
5673 uinfo->value.enumerated.items = items;
5674 if (uinfo->value.enumerated.item >= items)
5675 uinfo->value.enumerated.item = items - 1;
5676 strcpy(uinfo->value.enumerated.name,
5677 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5678 return 0;
5679}
95c6e9cb 5680
a7e76271 5681static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5682 struct snd_ctl_elem_value *ucontrol)
5683{
5684 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5685 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5686
a7e76271 5687 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5688 return 0;
5689}
5690
a7e76271 5691static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5692 struct snd_ctl_elem_value *ucontrol)
5693{
5694 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5695 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5696 int i, err = 0;
5697 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5698
a9291f46 5699 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5700 return 0;
5701
4e76a883 5702 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5703 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5704
a7e76271
IM		 5705 /*
5706 * Idx 0 is default.
5707 * Default needs to qualify with CrystalVoice state.
5708 */
5709 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5710 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5711 ca0132_voicefx.reqs[i],
5712 ca0132_voicefx_presets[sel].vals[i]);
5713 if (err < 0)
5714 break;
5715 }
95c6e9cb 5716
a7e76271
IM		 5717 if (err >= 0) {
5718 spec->voicefx_val = sel;
5719 /* enable voice fx */
5720 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5721 }
95c6e9cb 5722
a7e76271 5723 return 1;
95c6e9cb
IM		 5724}
5725
a7e76271
IM		 5726static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5727 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5728{
5729 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5730 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5731 hda_nid_t nid = get_amp_nid(kcontrol);
5732 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5733 long *valp = ucontrol->value.integer.value;
5734
a7e76271
IM		 5735 /* vnode */
5736 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5737 if (ch & 1) {
5738 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5739 valp++;
5740 }
5741 if (ch & 2) {
5742 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5743 valp++;
5744 }
5745 return 0;
5746 }
5747
5748 /* effects, include PE and CrystalVoice */
5749 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5750 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5751 return 0;
5752 }
5753
5754 /* mic boost */
5755 if (nid == spec->input_pins[0]) {
5756 *valp = spec->cur_mic_boost;
5757 return 0;
5758 }
5759
95c6e9cb
IM		 5760 return 0;
5761}
5762
a7e76271
IM		 5763static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5764 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5765{
5766 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5767 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5768 hda_nid_t nid = get_amp_nid(kcontrol);
5769 int ch = get_amp_channels(kcontrol);
95c6e9cb 5770 long *valp = ucontrol->value.integer.value;
a7e76271 5771 int changed = 1;
95c6e9cb 5772
4e76a883 5773 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5774 nid, *valp);
95c6e9cb
IM		 5775
5776 snd_hda_power_up(codec);
a7e76271
IM		 5777 /* vnode */
5778 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5779 if (ch & 1) {
5780 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5781 valp++;
5782 }
5783 if (ch & 2) {
5784 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5785 valp++;
5786 }
5787 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5788 goto exit;
5789 }
95c6e9cb 5790
a7e76271
IM		 5791 /* PE */
5792 if (nid == PLAY_ENHANCEMENT) {
5793 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5794 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5795 goto exit;
a7e76271 5796 }
95c6e9cb 5797
a7e76271
IM		 5798 /* CrystalVoice */
5799 if (nid == CRYSTAL_VOICE) {
5800 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5801 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5802 goto exit;
a7e76271 5803 }
95c6e9cb 5804
a7e76271
IM		 5805 /* out and in effects */
5806 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5807 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5808 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5809 changed = ca0132_effects_set(codec, nid, *valp);
5810 goto exit;
5811 }
5812
5813 /* mic boost */
5814 if (nid == spec->input_pins[0]) {
5815 spec->cur_mic_boost = *valp;
6da8f446 5816 if (ca0132_use_alt_functions(spec)) {
7cb9d94c
CM		 5817 if (spec->in_enum_val != REAR_LINE_IN)
5818 changed = ca0132_mic_boost_set(codec, *valp);
5819 } else {
5820 /* Mic boost does not apply to Digital Mic */
5821 if (spec->cur_mic_type != DIGITAL_MIC)
5822 changed = ca0132_mic_boost_set(codec, *valp);
5823 }
a7e76271 5824
a7e76271
IM		 5825 goto exit;
5826 }
95c6e9cb 5827
d51434d4
CM		 5828 if (nid == ZXR_HEADPHONE_GAIN) {
5829 spec->zxr_gain_set = *valp;
5830 if (spec->cur_out_type == HEADPHONE_OUT)
5831 changed = zxr_headphone_gain_set(codec, *valp);
5832 else
5833 changed = 0;
5834
5835 goto exit;
5836 }
5837
a7e76271 5838exit:
95c6e9cb 5839 snd_hda_power_down(codec);
a7e76271 5840 return changed;
95c6e9cb
IM		 5841}
5842
a7e76271
IM		 5843/*
5844 * Volume related
5845 */
017310fb
CM		 5846/*
5847 * Sets the internal DSP decibel level to match the DAC for output, and the
5848 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5849 * all alternative codecs set DSP playback volume.
5850 */
5851static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5852{
5853 struct ca0132_spec *spec = codec->spec;
5854 unsigned int dsp_dir;
5855 unsigned int lookup_val;
5856
5857 if (nid == VNID_SPK)
5858 dsp_dir = DSP_VOL_OUT;
5859 else
5860 dsp_dir = DSP_VOL_IN;
5861
5862 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5863
5864 dspio_set_uint_param(codec,
5865 ca0132_alt_vol_ctls[dsp_dir].mid,
5866 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5867 float_vol_db_lookup[lookup_val]);
5868
5869 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5870
5871 dspio_set_uint_param(codec,
5872 ca0132_alt_vol_ctls[dsp_dir].mid,
5873 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5874 float_vol_db_lookup[lookup_val]);
5875
5876 dspio_set_uint_param(codec,
5877 ca0132_alt_vol_ctls[dsp_dir].mid,
5878 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5879}
5880
a7e76271
IM		 5881static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5882 struct snd_ctl_elem_info *uinfo)
5883{
5884 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5885 struct ca0132_spec *spec = codec->spec;
5886 hda_nid_t nid = get_amp_nid(kcontrol);
5887 int ch = get_amp_channels(kcontrol);
5888 int dir = get_amp_direction(kcontrol);
5889 unsigned long pval;
5890 int err;
5891
5892 switch (nid) {
5893 case VNID_SPK:
5894 /* follow shared_out info */
5895 nid = spec->shared_out_nid;
5896 mutex_lock(&codec->control_mutex);
5897 pval = kcontrol->private_value;
5898 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5899 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5900 kcontrol->private_value = pval;
5901 mutex_unlock(&codec->control_mutex);
5902 break;
5903 case VNID_MIC:
5904 /* follow shared_mic info */
5905 nid = spec->shared_mic_nid;
5906 mutex_lock(&codec->control_mutex);
5907 pval = kcontrol->private_value;
5908 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5909 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5910 kcontrol->private_value = pval;
5911 mutex_unlock(&codec->control_mutex);
5912 break;
5913 default:
5914 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5915 }
5916 return err;
5917}
5918
5919static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5920 struct snd_ctl_elem_value *ucontrol)
5921{
5922 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5923 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5924 hda_nid_t nid = get_amp_nid(kcontrol);
5925 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5926 long *valp = ucontrol->value.integer.value;
5927
a7e76271
IM		 5928 /* store the left and right volume */
5929 if (ch & 1) {
5930 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5931 valp++;
5932 }
5933 if (ch & 2) {
5934 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5935 valp++;
5936 }
95c6e9cb
IM		 5937 return 0;
5938}
5939
a7e76271 5940static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5941 struct snd_ctl_elem_value *ucontrol)
5942{
5943 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5944 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5945 hda_nid_t nid = get_amp_nid(kcontrol);
5946 int ch = get_amp_channels(kcontrol);
95c6e9cb 5947 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5948 hda_nid_t shared_nid = 0;
5949 bool effective;
5950 int changed = 1;
5951
5952 /* store the left and right volume */
5953 if (ch & 1) {
5954 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5955 valp++;
5956 }
5957 if (ch & 2) {
5958 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5959 valp++;
5960 }
95c6e9cb 5961
a7e76271
IM		 5962 /* if effective conditions, then update hw immediately. */
5963 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5964 if (effective) {
5965 int dir = get_amp_direction(kcontrol);
5966 unsigned long pval;
5967
5968 snd_hda_power_up(codec);
5969 mutex_lock(&codec->control_mutex);
5970 pval = kcontrol->private_value;
5971 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5972 0, dir);
5973 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5974 kcontrol->private_value = pval;
5975 mutex_unlock(&codec->control_mutex);
5976 snd_hda_power_down(codec);
5977 }
95c6e9cb 5978
a7e76271 5979 return changed;
95c6e9cb
IM		 5980}
5981
017310fb
CM		 5982/*
5983 * This function is the same as the one above, because using an if statement
5984 * inside of the above volume control for the DSP volume would cause too much
5985 * lag. This is a lot more smooth.
5986 */
5987static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5988 struct snd_ctl_elem_value *ucontrol)
5989{
5990 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5991 struct ca0132_spec *spec = codec->spec;
5992 hda_nid_t nid = get_amp_nid(kcontrol);
5993 int ch = get_amp_channels(kcontrol);
5994 long *valp = ucontrol->value.integer.value;
5995 hda_nid_t vnid = 0;
5996 int changed = 1;
5997
5998 switch (nid) {
5999 case 0x02:
6000 vnid = VNID_SPK;
6001 break;
6002 case 0x07:
6003 vnid = VNID_MIC;
6004 break;
6005 }
6006
6007 /* store the left and right volume */
6008 if (ch & 1) {
6009 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6010 valp++;
6011 }
6012 if (ch & 2) {
6013 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6014 valp++;
6015 }
6016
6017 snd_hda_power_up(codec);
6018 ca0132_alt_dsp_volume_put(codec, vnid);
6019 mutex_lock(&codec->control_mutex);
6020 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6021 mutex_unlock(&codec->control_mutex);
6022 snd_hda_power_down(codec);
6023
6024 return changed;
6025}
6026
a7e76271
IM		 6027static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6028 unsigned int size, unsigned int __user *tlv)
95c6e9cb 6029{
a7e76271
IM		 6030 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6031 struct ca0132_spec *spec = codec->spec;
6032 hda_nid_t nid = get_amp_nid(kcontrol);
6033 int ch = get_amp_channels(kcontrol);
6034 int dir = get_amp_direction(kcontrol);
6035 unsigned long pval;
6036 int err;
6037
6038 switch (nid) {
6039 case VNID_SPK:
6040 /* follow shared_out tlv */
6041 nid = spec->shared_out_nid;
6042 mutex_lock(&codec->control_mutex);
6043 pval = kcontrol->private_value;
6044 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6045 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6046 kcontrol->private_value = pval;
6047 mutex_unlock(&codec->control_mutex);
6048 break;
6049 case VNID_MIC:
6050 /* follow shared_mic tlv */
6051 nid = spec->shared_mic_nid;
6052 mutex_lock(&codec->control_mutex);
6053 pval = kcontrol->private_value;
6054 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6055 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6056 kcontrol->private_value = pval;
6057 mutex_unlock(&codec->control_mutex);
6058 break;
6059 default:
6060 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6061 }
6062 return err;
95c6e9cb
IM		 6063}
6064
47cdf76e
CM		 6065/* Add volume slider control for effect level */
6066static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6067 const char *pfx, int dir)
6068{
47cdf76e
CM		 6069 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6070 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6071 struct snd_kcontrol_new knew =
6072 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6073
0cc1aa71 6074 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 6075
bb86124c 6076 knew.tlv.c = NULL;
47cdf76e
CM		 6077
6078 switch (nid) {
6079 case XBASS_XOVER:
6080 knew.info = ca0132_alt_xbass_xover_slider_info;
6081 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6082 knew.put = ca0132_alt_xbass_xover_slider_put;
6083 break;
6084 default:
6085 knew.info = ca0132_alt_effect_slider_info;
6086 knew.get = ca0132_alt_slider_ctl_get;
6087 knew.put = ca0132_alt_effect_slider_put;
6088 knew.private_value =
6089 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6090 break;
6091 }
6092
6093 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6094}
6095
6096/*
6097 * Added FX: prefix for the alternative codecs, because otherwise the surround
6098 * effect would conflict with the Surround sound volume control. Also seems more
6099 * clear as to what the switches do. Left alone for others.
6100 */
a7e76271
IM		 6101static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6102 const char *pfx, int dir)
95c6e9cb 6103{
47cdf76e 6104 struct ca0132_spec *spec = codec->spec;
975cc02a 6105 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 6106 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 6107 struct snd_kcontrol_new knew =
a7e76271 6108 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 6109 /* If using alt_controls, add FX: prefix. But, don't add FX:
6110 * prefix to OutFX or InFX enable controls.
6111 */
6da8f446 6112 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 6113 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 6114 else
6115 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6116
95c6e9cb
IM		 6117 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6118}
6119
a7e76271 6120static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 6121{
6122 struct snd_kcontrol_new knew =
a7e76271
IM		 6123 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6124 VOICEFX, 1, 0, HDA_INPUT);
6125 knew.info = ca0132_voicefx_info;
6126 knew.get = ca0132_voicefx_get;
6127 knew.put = ca0132_voicefx_put;
6128 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 6129}
6130
47cdf76e
CM		 6131/* Create the EQ Preset control */
6132static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6133{
6134 struct snd_kcontrol_new knew =
6135 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6136 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6137 knew.info = ca0132_alt_eq_preset_info;
6138 knew.get = ca0132_alt_eq_preset_get;
6139 knew.put = ca0132_alt_eq_preset_put;
6140 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6141 snd_ctl_new1(&knew, codec));
6142}
6143
6144/*
6145 * Add enumerated control for the three different settings of the smart volume
6146 * output effect. Normal just uses the slider value, and loud and night are
6147 * their own things that ignore that value.
6148 */
6149static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6150{
6151 struct snd_kcontrol_new knew =
6152 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6153 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6154 knew.info = ca0132_alt_svm_setting_info;
6155 knew.get = ca0132_alt_svm_setting_get;
6156 knew.put = ca0132_alt_svm_setting_put;
6157 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6158 snd_ctl_new1(&knew, codec));
6159
6160}
6161
7cb9d94c
CM		 6162/*
6163 * Create an Output Select enumerated control for codecs with surround
6164 * out capabilities.
6165 */
6166static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6167{
6168 struct snd_kcontrol_new knew =
6169 HDA_CODEC_MUTE_MONO("Output Select",
6170 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6171 knew.info = ca0132_alt_output_select_get_info;
6172 knew.get = ca0132_alt_output_select_get;
6173 knew.put = ca0132_alt_output_select_put;
6174 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6175 snd_ctl_new1(&knew, codec));
6176}
6177
6178/*
6179 * Create an Input Source enumerated control for the alternate ca0132 codecs
6180 * because the front microphone has no auto-detect, and Line-in has to be set
6181 * somehow.
6182 */
6183static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6184{
6185 struct snd_kcontrol_new knew =
6186 HDA_CODEC_MUTE_MONO("Input Source",
6187 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6188 knew.info = ca0132_alt_input_source_info;
6189 knew.get = ca0132_alt_input_source_get;
6190 knew.put = ca0132_alt_input_source_put;
6191 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6192 snd_ctl_new1(&knew, codec));
6193}
6194
47cdf76e
CM		 6195/*
6196 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6197 * more control than the original mic boost, which is either full 30dB or off.
6198 */
6199static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6200{
6201 struct snd_kcontrol_new knew =
6202 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6203 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6204 knew.info = ca0132_alt_mic_boost_info;
6205 knew.get = ca0132_alt_mic_boost_get;
6206 knew.put = ca0132_alt_mic_boost_put;
6207 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6208 snd_ctl_new1(&knew, codec));
6209
6210}
6211
212de2e7
CM		 6212/*
6213 * Add headphone gain enumerated control for the AE-5. This switches between
6214 * three modes, low, medium, and high. When non-headphone outputs are selected,
6215 * it is automatically set to high. This is the same behavior as Windows.
6216 */
6217static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6218{
6219 struct snd_kcontrol_new knew =
6220 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
4b432ad4 6221 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6222 knew.info = ae5_headphone_gain_info;
6223 knew.get = ae5_headphone_gain_get;
6224 knew.put = ae5_headphone_gain_put;
6225 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6226 snd_ctl_new1(&knew, codec));
6227}
6228
6229/*
6230 * Add sound filter enumerated control for the AE-5. This adds three different
6231 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6232 * read into it, it changes the DAC's interpolation filter.
6233 */
6234static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6235{
6236 struct snd_kcontrol_new knew =
6237 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
4b432ad4 6238 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6239 knew.info = ae5_sound_filter_info;
6240 knew.get = ae5_sound_filter_get;
6241 knew.put = ae5_sound_filter_put;
6242 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6243 snd_ctl_new1(&knew, codec));
6244}
6245
d51434d4
CM		 6246static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6247{
6248 struct snd_kcontrol_new knew =
6249 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6250 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6251
6252 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6253 snd_ctl_new1(&knew, codec));
6254}
6255
47cdf76e
CM		 6256/*
6257 * Need to create slave controls for the alternate codecs that have surround
6258 * capabilities.
6259 */
6260static const char * const ca0132_alt_slave_pfxs[] = {
6261 "Front", "Surround", "Center", "LFE", NULL,
6262};
6263
6264/*
6265 * Also need special channel map, because the default one is incorrect.
6266 * I think this has to do with the pin for rear surround being 0x11,
6267 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6268 */
9c4a665e 6269static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 6270 { .channels = 2,
6271 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6272 { .channels = 4,
6273 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6274 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6275 { .channels = 6,
6276 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6277 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6278 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6279 { }
6280};
6281
6282/* Add the correct chmap for streams with 6 channels. */
6283static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6284{
6285 int err = 0;
6286 struct hda_pcm *pcm;
6287
6288 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6289 struct hda_pcm_stream *hinfo =
6290 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6291 struct snd_pcm_chmap *chmap;
6292 const struct snd_pcm_chmap_elem *elem;
6293
6294 elem = ca0132_alt_chmaps;
6295 if (hinfo->channels_max == 6) {
6296 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6297 SNDRV_PCM_STREAM_PLAYBACK,
6298 elem, hinfo->channels_max, 0, &chmap);
6299 if (err < 0)
6300 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6301 }
6302 }
6303}
6304
a7e76271
IM		 6305/*
6306 * When changing Node IDs for Mixer Controls below, make sure to update
6307 * Node IDs in ca0132_config() as well.
6308 */
b0eaa072 6309static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 6310 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6311 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6312 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6313 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6314 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6315 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6316 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6317 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6318 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6319 0x12, 1, HDA_INPUT),
6320 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6321 VNID_HP_SEL, 1, HDA_OUTPUT),
6322 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6323 VNID_AMIC1_SEL, 1, HDA_INPUT),
6324 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6325 VNID_HP_ASEL, 1, HDA_OUTPUT),
6326 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6327 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6328 { } /* end */
6329};
6330
017310fb 6331/*
e25e3445
CM		 6332 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6333 * surround controls. Also sets both the Front Playback and Capture Volume
6334 * controls to alt so they set the DSP's decibel level.
017310fb 6335 */
e25e3445 6336static const struct snd_kcontrol_new desktop_mixer[] = {
017310fb
CM		 6337 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6338 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6339 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6340 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6341 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6342 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6343 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6344 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6345 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6346 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6347 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6348 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6349 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6350 VNID_HP_ASEL, 1, HDA_OUTPUT),
6351 { } /* end */
6352};
6353
6354/*
6355 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6356 * because it doesn't set decibel levels for the DSP for capture.
6357 */
b0eaa072 6358static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 6359 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6360 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6361 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6362 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6363 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6364 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6365 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6366 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6367 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6368 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6369 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6370 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6371 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6372 VNID_HP_ASEL, 1, HDA_OUTPUT),
6373 { } /* end */
6374};
6375
e90f29e4
IM		 6376static int ca0132_build_controls(struct hda_codec *codec)
6377{
6378 struct ca0132_spec *spec = codec->spec;
47cdf76e 6379 int i, num_fx, num_sliders;
e90f29e4
IM		 6380 int err = 0;
6381
6382 /* Add Mixer controls */
6383 for (i = 0; i < spec->num_mixers; i++) {
6384 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6385 if (err < 0)
6386 return err;
6387 }
47cdf76e 6388 /* Setup vmaster with surround slaves for desktop ca0132 devices */
6da8f446 6389 if (ca0132_use_alt_functions(spec)) {
47cdf76e
CM		 6390 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6391 spec->tlv);
6392 snd_hda_add_vmaster(codec, "Master Playback Volume",
6393 spec->tlv, ca0132_alt_slave_pfxs,
6394 "Playback Volume");
6395 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6396 NULL, ca0132_alt_slave_pfxs,
6397 "Playback Switch",
6398 true, &spec->vmaster_mute.sw_kctl);
1502b432
CM		 6399 if (err < 0)
6400 return err;
47cdf76e 6401 }
e90f29e4
IM		 6402
6403 /* Add in and out effects controls.
6404 * VoiceFX, PE and CrystalVoice are added separately.
6405 */
6406 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6407 for (i = 0; i < num_fx; i++) {
7a2dc84f 6408 /* Desktop cards break if Echo Cancellation is used. */
6da8f446 6409 if (ca0132_use_pci_mmio(spec)) {
47cdf76e
CM		 6410 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6411 OUT_EFFECTS_COUNT))
6412 continue;
6413 }
6414
e90f29e4
IM		 6415 err = add_fx_switch(codec, ca0132_effects[i].nid,
6416 ca0132_effects[i].name,
6417 ca0132_effects[i].direct);
6418 if (err < 0)
6419 return err;
6420 }
47cdf76e
CM		 6421 /*
6422 * If codec has use_alt_controls set to true, add effect level sliders,
6423 * EQ presets, and Smart Volume presets. Also, change names to add FX
6424 * prefix, and change PlayEnhancement and CrystalVoice to match.
6425 */
6da8f446 6426 if (ca0132_use_alt_controls(spec)) {
1502b432
CM		 6427 err = ca0132_alt_add_svm_enum(codec);
6428 if (err < 0)
6429 return err;
6430
6431 err = add_ca0132_alt_eq_presets(codec);
6432 if (err < 0)
6433 return err;
6434
47cdf76e
CM		 6435 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6436 "Enable OutFX", 0);
6437 if (err < 0)
6438 return err;
e90f29e4 6439
47cdf76e
CM		 6440 err = add_fx_switch(codec, CRYSTAL_VOICE,
6441 "Enable InFX", 1);
6442 if (err < 0)
6443 return err;
e90f29e4 6444
47cdf76e
CM		 6445 num_sliders = OUT_EFFECTS_COUNT - 1;
6446 for (i = 0; i < num_sliders; i++) {
6447 err = ca0132_alt_add_effect_slider(codec,
6448 ca0132_effects[i].nid,
6449 ca0132_effects[i].name,
6450 ca0132_effects[i].direct);
6451 if (err < 0)
6452 return err;
6453 }
6454
6455 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6456 "X-Bass Crossover", EFX_DIR_OUT);
6457
6458 if (err < 0)
6459 return err;
6460 } else {
6461 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6462 "PlayEnhancement", 0);
6463 if (err < 0)
6464 return err;
e90f29e4 6465
47cdf76e
CM		 6466 err = add_fx_switch(codec, CRYSTAL_VOICE,
6467 "CrystalVoice", 1);
6468 if (err < 0)
6469 return err;
6470 }
1502b432
CM		 6471 err = add_voicefx(codec);
6472 if (err < 0)
6473 return err;
e90f29e4 6474
7cb9d94c
CM		 6475 /*
6476 * If the codec uses alt_functions, you need the enumerated controls
6477 * to select the new outputs and inputs, plus add the new mic boost
6478 * setting control.
6479 */
6da8f446 6480 if (ca0132_use_alt_functions(spec)) {
1502b432
CM		 6481 err = ca0132_alt_add_output_enum(codec);
6482 if (err < 0)
6483 return err;
6484 err = ca0132_alt_add_mic_boost_enum(codec);
6485 if (err < 0)
6486 return err;
76dea4db
CM		 6487 /*
6488 * ZxR only has microphone input, there is no front panel
6489 * header on the card, and aux-in is handled by the DBPro board.
6490 */
6da8f446 6491 if (ca0132_quirk(spec) != QUIRK_ZXR) {
1502b432
CM		 6492 err = ca0132_alt_add_input_enum(codec);
6493 if (err < 0)
6494 return err;
6495 }
7cb9d94c 6496 }
212de2e7 6497
6da8f446 6498 if (ca0132_quirk(spec) == QUIRK_AE5) {
1502b432
CM		 6499 err = ae5_add_headphone_gain_enum(codec);
6500 if (err < 0)
6501 return err;
6502 err = ae5_add_sound_filter_enum(codec);
6503 if (err < 0)
6504 return err;
212de2e7 6505 }
d51434d4 6506
6da8f446 6507 if (ca0132_quirk(spec) == QUIRK_ZXR) {
1502b432
CM		 6508 err = zxr_add_headphone_gain_switch(codec);
6509 if (err < 0)
6510 return err;
6511 }
e90f29e4
IM		 6512#ifdef ENABLE_TUNING_CONTROLS
6513 add_tuning_ctls(codec);
6514#endif
6515
6516 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6517 if (err < 0)
6518 return err;
6519
6520 if (spec->dig_out) {
6521 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6522 spec->dig_out);
6523 if (err < 0)
6524 return err;
6525 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6526 if (err < 0)
6527 return err;
6528 /* spec->multiout.share_spdif = 1; */
6529 }
6530
6531 if (spec->dig_in) {
6532 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6533 if (err < 0)
6534 return err;
6535 }
47cdf76e 6536
6da8f446 6537 if (ca0132_use_alt_functions(spec))
47cdf76e
CM		 6538 ca0132_alt_add_chmap_ctls(codec);
6539
e90f29e4
IM		 6540 return 0;
6541}
6542
7675a2a9
CM		 6543static int dbpro_build_controls(struct hda_codec *codec)
6544{
6545 struct ca0132_spec *spec = codec->spec;
6546 int err = 0;
6547
6548 if (spec->dig_out) {
6549 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6550 spec->dig_out);
6551 if (err < 0)
6552 return err;
6553 }
6554
6555 if (spec->dig_in) {
6556 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6557 if (err < 0)
6558 return err;
6559 }
6560
6561 return 0;
6562}
6563
a7e76271 6564/*
e90f29e4 6565 * PCM
a7e76271 6566 */
071f1344 6567static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 6568 .substreams = 1,
6569 .channels_min = 2,
825315bc 6570 .channels_max = 6,
a7e76271 6571 .ops = {
a7e76271 6572 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 6573 .cleanup = ca0132_playback_pcm_cleanup,
6574 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 6575 },
6576};
6577
071f1344 6578static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 6579 .substreams = 1,
6580 .channels_min = 2,
6581 .channels_max = 2,
825315bc
IM		 6582 .ops = {
6583 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 6584 .cleanup = ca0132_capture_pcm_cleanup,
6585 .get_delay = ca0132_capture_pcm_delay,
825315bc 6586 },
a7e76271
IM		 6587};
6588
071f1344 6589static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 6590 .substreams = 1,
6591 .channels_min = 2,
6592 .channels_max = 2,
6593 .ops = {
6594 .open = ca0132_dig_playback_pcm_open,
6595 .close = ca0132_dig_playback_pcm_close,
6596 .prepare = ca0132_dig_playback_pcm_prepare,
6597 .cleanup = ca0132_dig_playback_pcm_cleanup
6598 },
6599};
6600
071f1344 6601static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 6602 .substreams = 1,
6603 .channels_min = 2,
6604 .channels_max = 2,
6605};
6606
6607static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 6608{
6609 struct ca0132_spec *spec = codec->spec;
bbbc7e85 6610 struct hda_pcm *info;
a7e76271 6611
bbbc7e85
TI		 6612 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6613 if (!info)
6614 return -ENOMEM;
6da8f446 6615 if (ca0132_use_alt_functions(spec)) {
47cdf76e
CM		 6616 info->own_chmap = true;
6617 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6618 = ca0132_alt_chmaps;
6619 }
a7e76271
IM		 6620 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6621 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6622 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6623 spec->multiout.max_channels;
6624 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 6625 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 6626 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 6627
009b8f97 6628 /* With the DSP enabled, desktops don't use this ADC. */
6da8f446 6629 if (!ca0132_use_alt_functions(spec)) {
009b8f97
CM		 6630 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6631 if (!info)
6632 return -ENOMEM;
6633 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6634 ca0132_pcm_analog_capture;
6635 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6636 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6637 }
825315bc 6638
bbbc7e85
TI		 6639 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6640 if (!info)
6641 return -ENOMEM;
825315bc
IM		 6642 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6643 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6644 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6645
a7e76271
IM		 6646 if (!spec->dig_out && !spec->dig_in)
6647 return 0;
6648
bbbc7e85
TI		 6649 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6650 if (!info)
6651 return -ENOMEM;
a7e76271
IM		 6652 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6653 if (spec->dig_out) {
6654 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6655 ca0132_pcm_digital_playback;
6656 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6657 }
6658 if (spec->dig_in) {
6659 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6660 ca0132_pcm_digital_capture;
6661 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6662 }
95c6e9cb 6663
a7e76271 6664 return 0;
95c6e9cb
IM		 6665}
6666
7675a2a9
CM		 6667static int dbpro_build_pcms(struct hda_codec *codec)
6668{
6669 struct ca0132_spec *spec = codec->spec;
6670 struct hda_pcm *info;
6671
6672 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
6673 if (!info)
6674 return -ENOMEM;
6675 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6676 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6677 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6678
6679
6680 if (!spec->dig_out && !spec->dig_in)
6681 return 0;
6682
6683 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6684 if (!info)
6685 return -ENOMEM;
6686 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6687 if (spec->dig_out) {
6688 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6689 ca0132_pcm_digital_playback;
6690 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6691 }
6692 if (spec->dig_in) {
6693 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6694 ca0132_pcm_digital_capture;
6695 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6696 }
6697
6698 return 0;
6699}
6700
441aa6a0
IM		 6701static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6702{
6703 if (pin) {
a0c041cb 6704 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6705 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6706 snd_hda_codec_write(codec, pin, 0,
6707 AC_VERB_SET_AMP_GAIN_MUTE,
6708 AMP_OUT_UNMUTE);
6709 }
6710 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6711 snd_hda_codec_write(codec, dac, 0,
6712 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6713}
6714
6715static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6716{
6717 if (pin) {
a0c041cb 6718 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6719 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6720 snd_hda_codec_write(codec, pin, 0,
6721 AC_VERB_SET_AMP_GAIN_MUTE,
6722 AMP_IN_UNMUTE(0));
6723 }
6724 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6725 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6726 AMP_IN_UNMUTE(0));
6727
6728 /* init to 0 dB and unmute. */
6729 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6730 HDA_AMP_VOLMASK, 0x5a);
6731 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6732 HDA_AMP_MUTE, 0);
6733 }
6734}
6735
5aaca44d
IM		 6736static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6737{
6738 unsigned int caps;
6739
6740 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6741 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6742 snd_hda_override_amp_caps(codec, nid, dir, caps);
6743}
6744
6745/*
6746 * Switch between Digital built-in mic and analog mic.
6747 */
6748static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6749{
6750 struct ca0132_spec *spec = codec->spec;
6751 unsigned int tmp;
6752 u8 val;
6753 unsigned int oldval;
6754
4e76a883 6755 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6756
6757 oldval = stop_mic1(codec);
6758 ca0132_set_vipsource(codec, 0);
6759 if (enable) {
6760 /* set DMic input as 2-ch */
6761 tmp = FLOAT_TWO;
6762 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6763
6764 val = spec->dmic_ctl;
6765 val |= 0x80;
6766 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6767 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6768
6769 if (!(spec->dmic_ctl & 0x20))
6770 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6771 } else {
6772 /* set AMic input as mono */
6773 tmp = FLOAT_ONE;
6774 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6775
6776 val = spec->dmic_ctl;
6777 /* clear bit7 and bit5 to disable dmic */
6778 val &= 0x5f;
6779 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6780 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6781
6782 if (!(spec->dmic_ctl & 0x20))
6783 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6784 }
6785 ca0132_set_vipsource(codec, 1);
6786 resume_mic1(codec, oldval);
6787}
6788
6789/*
6790 * Initialization for Digital Mic.
6791 */
6792static void ca0132_init_dmic(struct hda_codec *codec)
6793{
6794 struct ca0132_spec *spec = codec->spec;
6795 u8 val;
6796
6797 /* Setup Digital Mic here, but don't enable.
6798 * Enable based on jack detect.
6799 */
6800
6801 /* MCLK uses MPIO1, set to enable.
6802 * Bit 2-0: MPIO select
6803 * Bit 3: set to disable
6804 * Bit 7-4: reserved
6805 */
6806 val = 0x01;
6807 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6808 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6809
6810 /* Data1 uses MPIO3. Data2 not use
6811 * Bit 2-0: Data1 MPIO select
6812 * Bit 3: set disable Data1
6813 * Bit 6-4: Data2 MPIO select
6814 * Bit 7: set disable Data2
6815 */
6816 val = 0x83;
6817 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6818 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6819
6820 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6821 * Bit 3-0: Channel mask
6822 * Bit 4: set for 48KHz, clear for 32KHz
6823 * Bit 5: mode
6824 * Bit 6: set to select Data2, clear for Data1
6825 * Bit 7: set to enable DMic, clear for AMic
6826 */
6da8f446 6827 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
a57a46b9
AB		 6828 val = 0x33;
6829 else
6830 val = 0x23;
5aaca44d
IM		 6831 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6832 spec->dmic_ctl = val;
6833 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6834 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6835}
6836
6837/*
6838 * Initialization for Analog Mic 2
6839 */
6840static void ca0132_init_analog_mic2(struct hda_codec *codec)
6841{
6842 struct ca0132_spec *spec = codec->spec;
6843
6844 mutex_lock(&spec->chipio_mutex);
6845 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6846 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6847 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6848 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6849 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6850 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6851 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6852 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6853 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6854 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6855 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6856 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6857 mutex_unlock(&spec->chipio_mutex);
6858}
6859
6860static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6861{
6862 struct ca0132_spec *spec = codec->spec;
6863 int i;
5aaca44d 6864
4e76a883 6865 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6866 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6867
6868 for (i = 0; i < spec->multiout.num_dacs; i++)
6869 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6870
6871 for (i = 0; i < spec->num_outputs; i++)
6872 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6873
6874 for (i = 0; i < spec->num_inputs; i++) {
6875 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6876 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6877 }
6878}
6879
7e6ed62e 6880/*
6ef0e91e
CM		 6881 * Creates a dummy stream to bind the output to. This seems to have to be done
6882 * after changing the main outputs source and destination streams.
7e6ed62e 6883 */
6ef0e91e 6884static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
447fd8e9 6885{
6ef0e91e
CM		 6886 struct ca0132_spec *spec = codec->spec;
6887 unsigned int stream_format;
447fd8e9 6888
6ef0e91e
CM		 6889 stream_format = snd_hdac_calc_stream_format(48000, 2,
6890 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7e6ed62e 6891
6ef0e91e
CM		 6892 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6893 0, stream_format);
7e6ed62e 6894
6ef0e91e 6895 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7e6ed62e
CM		 6896}
6897
38ba69ff 6898/*
6ef0e91e 6899 * Initialize mic for non-chromebook ca0132 implementations.
38ba69ff 6900 */
6ef0e91e 6901static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
38ba69ff 6902{
6ef0e91e 6903 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6904 unsigned int tmp;
6905
6906 /* Mic 1 Setup */
6907 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6908 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 6909 if (ca0132_quirk(spec) == QUIRK_R3DI) {
6ef0e91e
CM		 6910 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6911 tmp = FLOAT_ONE;
6912 } else
6913 tmp = FLOAT_THREE;
38ba69ff
CM		 6914 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6915
6ef0e91e 6916 /* Mic 2 setup (not present on desktop cards) */
38ba69ff
CM		 6917 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6918 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6da8f446 6919 if (ca0132_quirk(spec) == QUIRK_R3DI)
6ef0e91e 6920 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
38ba69ff
CM		 6921 tmp = FLOAT_ZERO;
6922 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
38ba69ff
CM		 6923}
6924
6925/*
6926 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6927 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6928 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6929 * having an updated DAC, which changes the destination to that DAC.
6930 */
6931static void sbz_connect_streams(struct hda_codec *codec)
6932{
6933 struct ca0132_spec *spec = codec->spec;
6934
6935 mutex_lock(&spec->chipio_mutex);
6936
6937 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6938
6939 chipio_set_stream_channels(codec, 0x0C, 6);
6940 chipio_set_stream_control(codec, 0x0C, 1);
6941
6942 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6943 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6944
6945 /* Setup stream 0x14 with it's source and destination points */
6946 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6947 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6948 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6949 chipio_set_stream_channels(codec, 0x14, 2);
6950 chipio_set_stream_control(codec, 0x14, 1);
6951
6952 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6953
6954 mutex_unlock(&spec->chipio_mutex);
38ba69ff
CM		 6955}
6956
6957/*
6958 * Write data through ChipIO to setup proper stream destinations.
6959 * Not sure how it exactly works, but it seems to direct data
6960 * to different destinations. Example is f8 to c0, e0 to c0.
6961 * All I know is, if you don't set these, you get no sound.
6962 */
6963static void sbz_chipio_startup_data(struct hda_codec *codec)
6964{
6965 struct ca0132_spec *spec = codec->spec;
6966
6967 mutex_lock(&spec->chipio_mutex);
6968 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6969
6970 /* These control audio output */
6971 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6972 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6973 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6974 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6975 /* Signal to update I think */
6976 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6977
6978 chipio_set_stream_channels(codec, 0x0C, 6);
6979 chipio_set_stream_control(codec, 0x0C, 1);
6980 /* No clue what these control */
6da8f446 6981 if (ca0132_quirk(spec) == QUIRK_SBZ) {
c25c73e0
CM		 6982 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6983 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6984 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6985 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6986 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6987 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6988 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6989 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6990 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6991 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6992 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6993 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6da8f446 6994 } else if (ca0132_quirk(spec) == QUIRK_ZXR) {
c25c73e0
CM		 6995 chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
6996 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
6997 chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
6998 chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
6999 chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
7000 chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
7001 chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
7002 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
7003 }
38ba69ff
CM		 7004 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7005
7006 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7007 mutex_unlock(&spec->chipio_mutex);
7008}
7009
447fd8e9 7010/*
6ef0e91e
CM		 7011 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
7012 * done after the DSP is loaded.
447fd8e9 7013 */
6ef0e91e 7014static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
447fd8e9 7015{
6ef0e91e 7016 struct ca0132_spec *spec = codec->spec;
b5a22935 7017 unsigned int tmp, i;
447fd8e9 7018
b5a22935
CM		 7019 /*
7020 * Gotta run these twice, or else mic works inconsistently. Not clear
7021 * why this is, but multiple tests have confirmed it.
7022 */
7023 for (i = 0; i < 2; i++) {
6da8f446 7024 switch (ca0132_quirk(spec)) {
b5a22935
CM		 7025 case QUIRK_SBZ:
7026 case QUIRK_AE5:
7027 tmp = 0x00000003;
7028 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7029 tmp = 0x00000000;
7030 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7031 tmp = 0x00000001;
7032 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7033 tmp = 0x00000004;
7034 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7035 tmp = 0x00000005;
7036 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7037 tmp = 0x00000000;
7038 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7039 break;
7040 case QUIRK_R3D:
7041 case QUIRK_R3DI:
7042 tmp = 0x00000000;
7043 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7044 tmp = 0x00000001;
7045 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7046 tmp = 0x00000004;
7047 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7048 tmp = 0x00000005;
7049 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7050 tmp = 0x00000000;
7051 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7052 break;
6da8f446
TI		 7053 default:
7054 break;
b5a22935
CM		 7055 }
7056 msleep(100);
6ef0e91e 7057 }
447fd8e9
CM		 7058}
7059
6ef0e91e 7060static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
38ba69ff 7061{
6ef0e91e 7062 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 7063 unsigned int tmp;
7064
7065 chipio_set_stream_control(codec, 0x03, 0);
7066 chipio_set_stream_control(codec, 0x04, 0);
7067
7068 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7069 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7070
7071 tmp = FLOAT_THREE;
7072 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7073
7074 chipio_set_stream_control(codec, 0x03, 1);
7075 chipio_set_stream_control(codec, 0x04, 1);
7076
6da8f446 7077 switch (ca0132_quirk(spec)) {
6ef0e91e
CM		 7078 case QUIRK_SBZ:
7079 chipio_write(codec, 0x18b098, 0x0000000c);
7080 chipio_write(codec, 0x18b09C, 0x0000000c);
7081 break;
7082 case QUIRK_AE5:
7083 chipio_write(codec, 0x18b098, 0x0000000c);
7084 chipio_write(codec, 0x18b09c, 0x0000004c);
7085 break;
6da8f446
TI		 7086 default:
7087 break;
6ef0e91e 7088 }
38ba69ff
CM		 7089}
7090
415cd844
CM		 7091static void ae5_post_dsp_register_set(struct hda_codec *codec)
7092{
7093 struct ca0132_spec *spec = codec->spec;
7094
7095 chipio_8051_write_direct(codec, 0x93, 0x10);
7096 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7097 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7098 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7099 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7100
7101 writeb(0xff, spec->mem_base + 0x304);
7102 writeb(0xff, spec->mem_base + 0x304);
7103 writeb(0xff, spec->mem_base + 0x304);
7104 writeb(0xff, spec->mem_base + 0x304);
7105 writeb(0x00, spec->mem_base + 0x100);
7106 writeb(0xff, spec->mem_base + 0x304);
7107 writeb(0x00, spec->mem_base + 0x100);
7108 writeb(0xff, spec->mem_base + 0x304);
7109 writeb(0x00, spec->mem_base + 0x100);
7110 writeb(0xff, spec->mem_base + 0x304);
7111 writeb(0x00, spec->mem_base + 0x100);
7112 writeb(0xff, spec->mem_base + 0x304);
7113
7114 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7115 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7116 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7117}
7118
7119static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7120{
7121 /*
7122 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7123 * which seems to be 'multichannel'. This is also mentioned in the
7124 * AE-5's registry values in Windows.
7125 */
7126 chipio_set_control_param(codec, 3, 0);
7127 /*
7128 * I believe ASI is 'audio serial interface' and that it's used to
7129 * change colors on the external LED strip connected to the AE-5.
7130 */
7131 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7132
7133 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7134 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7135
7136 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7137 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
7138 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7139 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
7140 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7141 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
7142}
7143
7144static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7145{
7146 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7147 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7148 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7149 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7150
7151 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7152 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7153 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7154 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7155
7156 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7157 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7158 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7159 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7160
7161 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7162 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7163 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7164 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7165
7166 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7167 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7168 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7169 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7170}
7171
7172static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7173{
7174 struct ca0132_spec *spec = codec->spec;
7175
7176 mutex_lock(&spec->chipio_mutex);
7177
7178 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7179
7180 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7181
7182 chipio_set_stream_channels(codec, 0x0C, 6);
7183 chipio_set_stream_control(codec, 0x0C, 1);
7184
7185 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7186
7187 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7188 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7189 chipio_set_stream_channels(codec, 0x18, 6);
7190 chipio_set_stream_control(codec, 0x18, 1);
7191
7192 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7193
7194 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7195 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7196 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7197 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7198
7199 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7200
7201 mutex_unlock(&spec->chipio_mutex);
7202}
7203
7204static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7205{
7206 struct ca0132_spec *spec = codec->spec;
7207
7208 mutex_lock(&spec->chipio_mutex);
7209
7210 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7211 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7212 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7213 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7214
7215 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7216 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7217 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7218 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7219 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7220 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7221 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7222 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7223 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7224 ca0113_mmio_gpio_set(codec, 0, true);
7225 ca0113_mmio_gpio_set(codec, 1, true);
7226 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7227
7228 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7229
7230 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7231 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7232
7233 mutex_unlock(&spec->chipio_mutex);
7234}
7235
5aaca44d
IM		 7236/*
7237 * Setup default parameters for DSP
7238 */
7239static void ca0132_setup_defaults(struct hda_codec *codec)
7240{
e8f1bd5d 7241 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7242 unsigned int tmp;
7243 int num_fx;
7244 int idx, i;
7245
e8f1bd5d 7246 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 7247 return;
7248
7249 /* out, in effects + voicefx */
7250 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7251 for (idx = 0; idx < num_fx; idx++) {
7252 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7253 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
7254 ca0132_effects[idx].reqs[i],
7255 ca0132_effects[idx].def_vals[i]);
7256 }
7257 }
7258
7259 /*remove DSP headroom*/
7260 tmp = FLOAT_ZERO;
7261 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7262
7263 /*set speaker EQ bypass attenuation*/
7264 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
7265
7266 /* set AMic1 and AMic2 as mono mic */
7267 tmp = FLOAT_ONE;
7268 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7269 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7270
7271 /* set AMic1 as CrystalVoice input */
7272 tmp = FLOAT_ONE;
7273 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
7274
7275 /* set WUH source */
7276 tmp = FLOAT_TWO;
7277 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7278}
7279
7e6ed62e 7280/*
c986f50c 7281 * Setup default parameters for Recon3D/Recon3Di DSP.
7e6ed62e
CM		 7282 */
7283
c986f50c 7284static void r3d_setup_defaults(struct hda_codec *codec)
7e6ed62e
CM		 7285{
7286 struct ca0132_spec *spec = codec->spec;
7287 unsigned int tmp;
7288 int num_fx;
7289 int idx, i;
7290
7291 if (spec->dsp_state != DSP_DOWNLOADED)
7292 return;
7293
6ef0e91e
CM		 7294 ca0132_alt_dsp_scp_startup(codec);
7295 ca0132_alt_init_analog_mics(codec);
7e6ed62e
CM		 7296
7297 /*remove DSP headroom*/
7298 tmp = FLOAT_ZERO;
7299 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7300
7301 /* set WUH source */
7302 tmp = FLOAT_TWO;
7303 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7304 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7305
7306 /* Set speaker source? */
7307 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7308
6da8f446 7309 if (ca0132_quirk(spec) == QUIRK_R3DI)
c986f50c 7310 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7e6ed62e
CM		 7311
7312 /* Setup effect defaults */
7313 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7314 for (idx = 0; idx < num_fx; idx++) {
7315 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7316 dspio_set_uint_param(codec,
7317 ca0132_effects[idx].mid,
7318 ca0132_effects[idx].reqs[i],
7319 ca0132_effects[idx].def_vals[i]);
7320 }
7321 }
7e6ed62e
CM		 7322}
7323
38ba69ff
CM		 7324/*
7325 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
7326 * than the Chromebook setup.
7327 */
7328static void sbz_setup_defaults(struct hda_codec *codec)
7329{
7330 struct ca0132_spec *spec = codec->spec;
6ef0e91e 7331 unsigned int tmp;
38ba69ff
CM		 7332 int num_fx;
7333 int idx, i;
7334
7335 if (spec->dsp_state != DSP_DOWNLOADED)
7336 return;
7337
6ef0e91e
CM		 7338 ca0132_alt_dsp_scp_startup(codec);
7339 ca0132_alt_init_analog_mics(codec);
38ba69ff 7340 sbz_connect_streams(codec);
38ba69ff
CM		 7341 sbz_chipio_startup_data(codec);
7342
7343 chipio_set_stream_control(codec, 0x03, 1);
7344 chipio_set_stream_control(codec, 0x04, 1);
7345
7346 /*
7347 * Sets internal input loopback to off, used to have a switch to
7348 * enable input loopback, but turned out to be way too buggy.
7349 */
7350 tmp = FLOAT_ONE;
7351 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7352 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7353
7354 /*remove DSP headroom*/
7355 tmp = FLOAT_ZERO;
7356 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7357
7358 /* set WUH source */
7359 tmp = FLOAT_TWO;
7360 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7361 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7362
7363 /* Set speaker source? */
7364 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7365
6ef0e91e 7366 ca0132_alt_dsp_initial_mic_setup(codec);
38ba69ff
CM		 7367
7368 /* out, in effects + voicefx */
7369 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7370 for (idx = 0; idx < num_fx; idx++) {
7371 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7372 dspio_set_uint_param(codec,
7373 ca0132_effects[idx].mid,
7374 ca0132_effects[idx].reqs[i],
7375 ca0132_effects[idx].def_vals[i]);
7376 }
7377 }
7378
6ef0e91e 7379 ca0132_alt_create_dummy_stream(codec);
38ba69ff
CM		 7380}
7381
415cd844
CM		 7382/*
7383 * Setup default parameters for the Sound BlasterX AE-5 DSP.
7384 */
7385static void ae5_setup_defaults(struct hda_codec *codec)
7386{
7387 struct ca0132_spec *spec = codec->spec;
7388 unsigned int tmp;
7389 int num_fx;
7390 int idx, i;
7391
7392 if (spec->dsp_state != DSP_DOWNLOADED)
7393 return;
7394
7395 ca0132_alt_dsp_scp_startup(codec);
7396 ca0132_alt_init_analog_mics(codec);
7397 chipio_set_stream_control(codec, 0x03, 1);
7398 chipio_set_stream_control(codec, 0x04, 1);
7399
7400 /* New, unknown SCP req's */
7401 tmp = FLOAT_ZERO;
7402 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
7403 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
7404 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
7405 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
7406
7407 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
7408 ca0113_mmio_gpio_set(codec, 0, false);
7409 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
7410
7411 /* Internal loopback off */
7412 tmp = FLOAT_ONE;
7413 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7414 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7415
7416 /*remove DSP headroom*/
7417 tmp = FLOAT_ZERO;
7418 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7419
7420 /* set WUH source */
7421 tmp = FLOAT_TWO;
7422 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7423 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7424
7425 /* Set speaker source? */
7426 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7427
7428 ca0132_alt_dsp_initial_mic_setup(codec);
7429 ae5_post_dsp_register_set(codec);
7430 ae5_post_dsp_param_setup(codec);
7431 ae5_post_dsp_pll_setup(codec);
7432 ae5_post_dsp_stream_setup(codec);
7433 ae5_post_dsp_startup_data(codec);
7434
7435 /* out, in effects + voicefx */
7436 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7437 for (idx = 0; idx < num_fx; idx++) {
7438 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7439 dspio_set_uint_param(codec,
7440 ca0132_effects[idx].mid,
7441 ca0132_effects[idx].reqs[i],
7442 ca0132_effects[idx].def_vals[i]);
7443 }
7444 }
7445
7446 ca0132_alt_create_dummy_stream(codec);
7447}
7448
5aaca44d
IM		 7449/*
7450 * Initialization of flags in chip
7451 */
7452static void ca0132_init_flags(struct hda_codec *codec)
7453{
009b8f97
CM		 7454 struct ca0132_spec *spec = codec->spec;
7455
6da8f446 7456 if (ca0132_use_alt_functions(spec)) {
009b8f97
CM		 7457 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
7458 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
7459 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
7460 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
7461 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
7462 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7463 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
7464 chipio_set_control_flag(codec,
7465 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7466 chipio_set_control_flag(codec,
7467 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
7468 } else {
7469 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7470 chipio_set_control_flag(codec,
7471 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
7472 chipio_set_control_flag(codec,
7473 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
7474 chipio_set_control_flag(codec,
7475 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
7476 chipio_set_control_flag(codec,
7477 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7478 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
7479 }
5aaca44d
IM		 7480}
7481
7482/*
7483 * Initialization of parameters in chip
7484 */
7485static void ca0132_init_params(struct hda_codec *codec)
7486{
009b8f97
CM		 7487 struct ca0132_spec *spec = codec->spec;
7488
6da8f446 7489 if (ca0132_use_alt_functions(spec)) {
009b8f97
CM		 7490 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7491 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
7492 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
7493 chipio_set_control_param(codec, 0, 0);
7494 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
7495 }
7496
5aaca44d
IM		 7497 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
7498 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
7499}
95c6e9cb 7500
e90f29e4
IM		 7501static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
7502{
7503 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
7504 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
7505 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
7506 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
7507 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
7508 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
7509
406261ce
IM		 7510 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7511 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 7512 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7513}
7514
7515static bool ca0132_download_dsp_images(struct hda_codec *codec)
7516{
7517 bool dsp_loaded = false;
8a19bcee 7518 struct ca0132_spec *spec = codec->spec;
e90f29e4 7519 const struct dsp_image_seg *dsp_os_image;
4fc90fb8 7520 const struct firmware *fw_entry = NULL;
8a19bcee
CM		 7521 /*
7522 * Alternate firmwares for different variants. The Recon3Di apparently
7523 * can use the default firmware, but I'll leave the option in case
7524 * it needs it again.
7525 */
6da8f446 7526 switch (ca0132_quirk(spec)) {
8a19bcee 7527 case QUIRK_SBZ:
7a928186
CM		 7528 case QUIRK_R3D:
7529 case QUIRK_AE5:
7530 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
4fc90fb8 7531 codec->card->dev) != 0)
6ef0e91e 7532 codec_dbg(codec, "Desktop firmware not found.");
4fc90fb8 7533 else
7a928186 7534 codec_dbg(codec, "Desktop firmware selected.");
8a19bcee
CM		 7535 break;
7536 case QUIRK_R3DI:
7537 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
4fc90fb8 7538 codec->card->dev) != 0)
8a19bcee 7539 codec_dbg(codec, "Recon3Di alt firmware not detected.");
4fc90fb8 7540 else
8a19bcee 7541 codec_dbg(codec, "Recon3Di firmware selected.");
8a19bcee
CM		 7542 break;
7543 default:
8a19bcee
CM		 7544 break;
7545 }
7546 /*
7547 * Use default ctefx.bin if no alt firmware is detected, or if none
7548 * exists for your particular codec.
7549 */
4fc90fb8 7550 if (!fw_entry) {
8a19bcee
CM		 7551 codec_dbg(codec, "Default firmware selected.");
7552 if (request_firmware(&fw_entry, EFX_FILE,
7553 codec->card->dev) != 0)
7554 return false;
7555 }
e90f29e4 7556
15e4ba66 7557 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 7558 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 7559 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 7560 goto exit_download;
7561 }
7562
e90f29e4
IM		 7563 dsp_loaded = dspload_wait_loaded(codec);
7564
d1d28500 7565exit_download:
15e4ba66
TI		 7566 release_firmware(fw_entry);
7567
e90f29e4
IM		 7568 return dsp_loaded;
7569}
7570
7571static void ca0132_download_dsp(struct hda_codec *codec)
7572{
7573 struct ca0132_spec *spec = codec->spec;
7574
9a0869f4
TI		 7575#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7576 return; /* NOP */
7577#endif
e90f29e4 7578
e24aa0a4
TI		 7579 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7580 return; /* don't retry failures */
7581
b714a710 7582 chipio_enable_clocks(codec);
e93ac30a
CM		 7583 if (spec->dsp_state != DSP_DOWNLOADED) {
7584 spec->dsp_state = DSP_DOWNLOADING;
7585
7586 if (!ca0132_download_dsp_images(codec))
7587 spec->dsp_state = DSP_DOWNLOAD_FAILED;
7588 else
7589 spec->dsp_state = DSP_DOWNLOADED;
7590 }
e90f29e4 7591
009b8f97 7592 /* For codecs using alt functions, this is already done earlier */
6da8f446 7593 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
e90f29e4
IM		 7594 ca0132_set_dsp_msr(codec, true);
7595}
7596
f8fb1170
TI		 7597static void ca0132_process_dsp_response(struct hda_codec *codec,
7598 struct hda_jack_callback *callback)
e90f29e4
IM		 7599{
7600 struct ca0132_spec *spec = codec->spec;
7601
4e76a883 7602 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 7603 if (spec->wait_scp) {
7604 if (dspio_get_response_data(codec) >= 0)
7605 spec->wait_scp = 0;
7606 }
7607
7608 dspio_clear_response_queue(codec);
7609}
7610
f8fb1170 7611static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 7612{
993884f6 7613 struct ca0132_spec *spec = codec->spec;
2ebab40e 7614 struct hda_jack_tbl *tbl;
e90f29e4 7615
f8fb1170
TI		 7616 /* Delay enabling the HP amp, to let the mic-detection
7617 * state machine run.
7618 */
7619 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 7620 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 7621 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7622 if (tbl)
7623 tbl->block_report = 1;
f8fb1170
TI		 7624}
7625
7626static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7627{
a1b7f016
CM		 7628 struct ca0132_spec *spec = codec->spec;
7629
6da8f446 7630 if (ca0132_use_alt_functions(spec))
a1b7f016
CM		 7631 ca0132_alt_select_in(codec);
7632 else
7633 ca0132_select_mic(codec);
f8fb1170
TI		 7634}
7635
7636static void ca0132_init_unsol(struct hda_codec *codec)
7637{
d5c016b5
GM		 7638 struct ca0132_spec *spec = codec->spec;
7639 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7640 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 7641 amic_callback);
7642 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7643 ca0132_process_dsp_response);
63177afc 7644 /* Front headphone jack detection */
6da8f446 7645 if (ca0132_use_alt_functions(spec))
63177afc
CM		 7646 snd_hda_jack_detect_enable_callback(codec,
7647 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 7648}
7649
5aaca44d
IM		 7650/*
7651 * Verbs tables.
7652 */
7653
7654/* Sends before DSP download. */
7655static struct hda_verb ca0132_base_init_verbs[] = {
7656 /*enable ct extension*/
7657 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 7658 {}
7659};
7660
7661/* Send at exit. */
7662static struct hda_verb ca0132_base_exit_verbs[] = {
7663 /*set afg to D3*/
7664 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7665 /*disable ct extension*/
7666 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7667 {}
7668};
7669
8a19bcee 7670/* Other verbs tables. Sends after DSP download. */
e93ac30a 7671
5aaca44d
IM		 7672static struct hda_verb ca0132_init_verbs0[] = {
7673 /* chip init verbs */
7674 {0x15, 0x70D, 0xF0},
7675 {0x15, 0x70E, 0xFE},
7676 {0x15, 0x707, 0x75},
7677 {0x15, 0x707, 0xD3},
7678 {0x15, 0x707, 0x09},
7679 {0x15, 0x707, 0x53},
7680 {0x15, 0x707, 0xD4},
7681 {0x15, 0x707, 0xEF},
7682 {0x15, 0x707, 0x75},
7683 {0x15, 0x707, 0xD3},
7684 {0x15, 0x707, 0x09},
7685 {0x15, 0x707, 0x02},
7686 {0x15, 0x707, 0x37},
7687 {0x15, 0x707, 0x78},
7688 {0x15, 0x53C, 0xCE},
7689 {0x15, 0x575, 0xC9},
7690 {0x15, 0x53D, 0xCE},
7691 {0x15, 0x5B7, 0xC9},
7692 {0x15, 0x70D, 0xE8},
7693 {0x15, 0x70E, 0xFE},
7694 {0x15, 0x707, 0x02},
7695 {0x15, 0x707, 0x68},
7696 {0x15, 0x707, 0x62},
7697 {0x15, 0x53A, 0xCE},
7698 {0x15, 0x546, 0xC9},
7699 {0x15, 0x53B, 0xCE},
7700 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 7701 {}
7702};
7703
e42c7c73
CM		 7704/* Extra init verbs for desktop cards. */
7705static struct hda_verb ca0132_init_verbs1[] = {
e93ac30a
CM		 7706 {0x15, 0x70D, 0x20},
7707 {0x15, 0x70E, 0x19},
7708 {0x15, 0x707, 0x00},
7709 {0x15, 0x539, 0xCE},
7710 {0x15, 0x546, 0xC9},
7711 {0x15, 0x70D, 0xB7},
7712 {0x15, 0x70E, 0x09},
7713 {0x15, 0x707, 0x10},
7714 {0x15, 0x70D, 0xAF},
7715 {0x15, 0x70E, 0x09},
7716 {0x15, 0x707, 0x01},
7717 {0x15, 0x707, 0x05},
7718 {0x15, 0x70D, 0x73},
7719 {0x15, 0x70E, 0x09},
7720 {0x15, 0x707, 0x14},
7721 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 7722 {}
7723};
7724
95c6e9cb
IM		 7725static void ca0132_init_chip(struct hda_codec *codec)
7726{
7727 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7728 int num_fx;
7729 int i;
7730 unsigned int on;
95c6e9cb
IM		 7731
7732 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 7733
7734 spec->cur_out_type = SPEAKER_OUT;
6da8f446 7735 if (!ca0132_use_alt_functions(spec))
7cb9d94c
CM		 7736 spec->cur_mic_type = DIGITAL_MIC;
7737 else
7738 spec->cur_mic_type = REAR_MIC;
7739
5aaca44d
IM		 7740 spec->cur_mic_boost = 0;
7741
7742 for (i = 0; i < VNODES_COUNT; i++) {
7743 spec->vnode_lvol[i] = 0x5a;
7744 spec->vnode_rvol[i] = 0x5a;
7745 spec->vnode_lswitch[i] = 0;
7746 spec->vnode_rswitch[i] = 0;
7747 }
7748
7749 /*
7750 * Default states for effects are in ca0132_effects[].
7751 */
7752 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7753 for (i = 0; i < num_fx; i++) {
7754 on = (unsigned int)ca0132_effects[i].reqs[0];
7755 spec->effects_switch[i] = on ? 1 : 0;
7756 }
47cdf76e
CM		 7757 /*
7758 * Sets defaults for the effect slider controls, only for alternative
7759 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7760 */
6da8f446 7761 if (ca0132_use_alt_controls(spec)) {
47cdf76e
CM		 7762 spec->xbass_xover_freq = 8;
7763 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7764 spec->fx_ctl_val[i] = effect_slider_defaults[i];
7765 }
5aaca44d
IM		 7766
7767 spec->voicefx_val = 0;
7768 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7769 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7770
76dea4db
CM		 7771 /*
7772 * The ZxR doesn't have a front panel header, and it's line-in is on
7773 * the daughter board. So, there is no input enum control, and we need
7774 * to make sure that spec->in_enum_val is set properly.
7775 */
6da8f446 7776 if (ca0132_quirk(spec) == QUIRK_ZXR)
76dea4db
CM		 7777 spec->in_enum_val = REAR_MIC;
7778
44f0c978
IM		 7779#ifdef ENABLE_TUNING_CONTROLS
7780 ca0132_init_tuning_defaults(codec);
7781#endif
95c6e9cb
IM		 7782}
7783
2e48b2b7
CM		 7784/*
7785 * Recon3Di exit specific commands.
7786 */
7787/* prevents popping noise on shutdown */
7788static void r3di_gpio_shutdown(struct hda_codec *codec)
7789{
7790 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7791}
7792
7793/*
7794 * Sound Blaster Z exit specific commands.
7795 */
7796static void sbz_region2_exit(struct hda_codec *codec)
7797{
7798 struct ca0132_spec *spec = codec->spec;
7799 unsigned int i;
7800
7801 for (i = 0; i < 4; i++)
7802 writeb(0x0, spec->mem_base + 0x100);
7803 for (i = 0; i < 8; i++)
7804 writeb(0xb3, spec->mem_base + 0x304);
a62e4739 7805
b9b41345
CM		 7806 ca0113_mmio_gpio_set(codec, 0, false);
7807 ca0113_mmio_gpio_set(codec, 1, false);
7808 ca0113_mmio_gpio_set(codec, 4, true);
7809 ca0113_mmio_gpio_set(codec, 5, false);
7810 ca0113_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 7811}
7812
7813static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7814{
7815 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7816 unsigned int i;
7817
7818 snd_hda_codec_write(codec, 0x11, 0,
7819 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7820
7821 for (i = 0; i < 5; i++)
7822 snd_hda_codec_write(codec, pins[i], 0,
7823 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7824}
7825
2f295f91 7826static void ca0132_clear_unsolicited(struct hda_codec *codec)
2e48b2b7
CM		 7827{
7828 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7829 unsigned int i;
7830
7831 for (i = 0; i < 7; i++) {
7832 snd_hda_codec_write(codec, pins[i], 0,
7833 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7834 }
7835}
7836
7837/* On shutdown, sends commands in sets of three */
7838static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7839 int mask, int data)
7840{
7841 if (dir >= 0)
7842 snd_hda_codec_write(codec, 0x01, 0,
7843 AC_VERB_SET_GPIO_DIRECTION, dir);
7844 if (mask >= 0)
7845 snd_hda_codec_write(codec, 0x01, 0,
7846 AC_VERB_SET_GPIO_MASK, mask);
7847
7848 if (data >= 0)
7849 snd_hda_codec_write(codec, 0x01, 0,
7850 AC_VERB_SET_GPIO_DATA, data);
7851}
7852
7675a2a9
CM		 7853static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
7854{
7855 hda_nid_t pins[7] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
7856 unsigned int i;
7857
7858 for (i = 0; i < 7; i++)
7859 snd_hda_codec_write(codec, pins[i], 0,
7860 AC_VERB_SET_POWER_STATE, 0x03);
7861}
7862
2e48b2b7
CM		 7863static void sbz_exit_chip(struct hda_codec *codec)
7864{
009b8f97
CM		 7865 chipio_set_stream_control(codec, 0x03, 0);
7866 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 7867
7868 /* Mess with GPIO */
7869 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7870 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7871 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7872
009b8f97
CM		 7873 chipio_set_stream_control(codec, 0x14, 0);
7874 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7875
7876 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7877 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7878
7879 chipio_write(codec, 0x18a020, 0x00000083);
7880
7881 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7882 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7883 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7884
009b8f97 7885 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7886
7887 chipio_set_control_param(codec, 0x0D, 0x24);
7888
2f295f91 7889 ca0132_clear_unsolicited(codec);
2e48b2b7
CM		 7890 sbz_set_pin_ctl_default(codec);
7891
7892 snd_hda_codec_write(codec, 0x0B, 0,
7893 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7894
2e48b2b7
CM		 7895 sbz_region2_exit(codec);
7896}
7897
2f295f91
CM		 7898static void r3d_exit_chip(struct hda_codec *codec)
7899{
7900 ca0132_clear_unsolicited(codec);
7901 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7902 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7903}
7904
edb1b3ab
CM		 7905static void ae5_exit_chip(struct hda_codec *codec)
7906{
7907 chipio_set_stream_control(codec, 0x03, 0);
7908 chipio_set_stream_control(codec, 0x04, 0);
7909
7910 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7911 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7912 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7913 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7914 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7915 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
7916 ca0113_mmio_gpio_set(codec, 0, false);
7917 ca0113_mmio_gpio_set(codec, 1, false);
7918
7919 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7920 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7921
7922 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7923
7924 chipio_set_stream_control(codec, 0x18, 0);
7925 chipio_set_stream_control(codec, 0x0c, 0);
7926
7927 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
7928}
7929
96395e86
CM		 7930static void zxr_exit_chip(struct hda_codec *codec)
7931{
7932 chipio_set_stream_control(codec, 0x03, 0);
7933 chipio_set_stream_control(codec, 0x04, 0);
7934 chipio_set_stream_control(codec, 0x14, 0);
7935 chipio_set_stream_control(codec, 0x0C, 0);
7936
7937 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7938 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7939
7940 chipio_write(codec, 0x18a020, 0x00000083);
7941
7942 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7943 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7944
7945 ca0132_clear_unsolicited(codec);
7946 sbz_set_pin_ctl_default(codec);
7947 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7948
7949 ca0113_mmio_gpio_set(codec, 5, false);
7950 ca0113_mmio_gpio_set(codec, 2, false);
7951 ca0113_mmio_gpio_set(codec, 3, false);
7952 ca0113_mmio_gpio_set(codec, 0, false);
7953 ca0113_mmio_gpio_set(codec, 4, true);
7954 ca0113_mmio_gpio_set(codec, 0, true);
7955 ca0113_mmio_gpio_set(codec, 5, true);
7956 ca0113_mmio_gpio_set(codec, 2, false);
7957 ca0113_mmio_gpio_set(codec, 3, false);
7958}
7959
95c6e9cb
IM		 7960static void ca0132_exit_chip(struct hda_codec *codec)
7961{
7962 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7963
7964 if (dspload_is_loaded(codec))
7965 dsp_reset(codec);
95c6e9cb
IM		 7966}
7967
38ba69ff
CM		 7968/*
7969 * This fixes a problem that was hard to reproduce. Very rarely, I would
7970 * boot up, and there would be no sound, but the DSP indicated it had loaded
7971 * properly. I did a few memory dumps to see if anything was different, and
7972 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7973 * checks if those areas are uninitialized, and if they are, it'll attempt to
7974 * reload the card 3 times. Usually it fixes by the second.
7975 */
7976static void sbz_dsp_startup_check(struct hda_codec *codec)
7977{
7978 struct ca0132_spec *spec = codec->spec;
7979 unsigned int dsp_data_check[4];
7980 unsigned int cur_address = 0x390;
7981 unsigned int i;
7982 unsigned int failure = 0;
7983 unsigned int reload = 3;
7984
7985 if (spec->startup_check_entered)
7986 return;
7987
7988 spec->startup_check_entered = true;
7989
7990 for (i = 0; i < 4; i++) {
7991 chipio_read(codec, cur_address, &dsp_data_check[i]);
7992 cur_address += 0x4;
7993 }
7994 for (i = 0; i < 4; i++) {
7995 if (dsp_data_check[i] == 0xa1a2a3a4)
7996 failure = 1;
7997 }
7998
7999 codec_dbg(codec, "Startup Check: %d ", failure);
8000 if (failure)
8001 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
8002 /*
8003 * While the failure condition is true, and we haven't reached our
8004 * three reload limit, continue trying to reload the driver and
8005 * fix the issue.
8006 */
8007 while (failure && (reload != 0)) {
8008 codec_info(codec, "Reloading... Tries left: %d", reload);
8009 sbz_exit_chip(codec);
8010 spec->dsp_state = DSP_DOWNLOAD_INIT;
8011 codec->patch_ops.init(codec);
8012 failure = 0;
8013 for (i = 0; i < 4; i++) {
8014 chipio_read(codec, cur_address, &dsp_data_check[i]);
8015 cur_address += 0x4;
8016 }
8017 for (i = 0; i < 4; i++) {
8018 if (dsp_data_check[i] == 0xa1a2a3a4)
8019 failure = 1;
8020 }
8021 reload--;
8022 }
8023
8024 if (!failure && reload < 3)
8025 codec_info(codec, "DSP fixed.");
8026
8027 if (!failure)
8028 return;
8029
8030 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
8031}
8032
e93ac30a
CM		 8033/*
8034 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
8035 * extra precision for decibel values. If you had the dB value in floating point
8036 * you would take the value after the decimal point, multiply by 64, and divide
8037 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
8038 * implement fixed point or floating point dB volumes. For now, I'll set them
8039 * to 0 just incase a value has lingered from a boot into Windows.
8040 */
8041static void ca0132_alt_vol_setup(struct hda_codec *codec)
8042{
8043 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
8044 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
8045 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
8046 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
8047 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
8048 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
8049 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
8050 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
8051}
8052
8053/*
8054 * Extra commands that don't really fit anywhere else.
8055 */
8056static void sbz_pre_dsp_setup(struct hda_codec *codec)
8057{
8058 struct ca0132_spec *spec = codec->spec;
8059
8060 writel(0x00820680, spec->mem_base + 0x01C);
8061 writel(0x00820680, spec->mem_base + 0x01C);
8062
e93ac30a
CM		 8063 chipio_write(codec, 0x18b0a4, 0x000000c2);
8064
8065 snd_hda_codec_write(codec, 0x11, 0,
8066 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8067}
8068
e42c7c73
CM		 8069static void r3d_pre_dsp_setup(struct hda_codec *codec)
8070{
e42c7c73
CM		 8071 chipio_write(codec, 0x18b0a4, 0x000000c2);
8072
8073 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8074 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8075 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8076 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8077 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8078 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8079
8080 snd_hda_codec_write(codec, 0x11, 0,
8081 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8082}
8083
e93ac30a
CM		 8084static void r3di_pre_dsp_setup(struct hda_codec *codec)
8085{
8086 chipio_write(codec, 0x18b0a4, 0x000000c2);
8087
8088 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8089 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8090 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8091 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8092 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8093 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8094
8095 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8096 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
8097 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8098 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
8099 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8100 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
8101 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8102 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
8103
8104 snd_hda_codec_write(codec, 0x11, 0,
8105 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
8106}
8107
e93ac30a
CM		 8108/*
8109 * These are sent before the DSP is downloaded. Not sure
8110 * what they do, or if they're necessary. Could possibly
8111 * be removed. Figure they're better to leave in.
8112 */
e42c7c73 8113static void ca0132_mmio_init(struct hda_codec *codec)
e93ac30a
CM		 8114{
8115 struct ca0132_spec *spec = codec->spec;
8116
6da8f446 8117 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8118 writel(0x00000001, spec->mem_base + 0x400);
8119 else
8120 writel(0x00000000, spec->mem_base + 0x400);
8121
6da8f446 8122 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8123 writel(0x00000001, spec->mem_base + 0x408);
8124 else
8125 writel(0x00000000, spec->mem_base + 0x408);
8126
6da8f446 8127 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8128 writel(0x00000001, spec->mem_base + 0x40c);
8129 else
8130 writel(0x00000000, spec->mem_base + 0x40C);
8131
6da8f446 8132 if (ca0132_quirk(spec) == QUIRK_ZXR)
2e492b8e
CM		 8133 writel(0x00880640, spec->mem_base + 0x01C);
8134 else
8135 writel(0x00880680, spec->mem_base + 0x01C);
ce715448 8136
6da8f446 8137 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8138 writel(0x00000080, spec->mem_base + 0xC0C);
8139 else
8140 writel(0x00000083, spec->mem_base + 0xC0C);
8141
e93ac30a
CM		 8142 writel(0x00000030, spec->mem_base + 0xC00);
8143 writel(0x00000000, spec->mem_base + 0xC04);
ce715448 8144
6da8f446 8145 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8146 writel(0x00000000, spec->mem_base + 0xC0C);
8147 else
8148 writel(0x00000003, spec->mem_base + 0xC0C);
8149
e93ac30a
CM		 8150 writel(0x00000003, spec->mem_base + 0xC0C);
8151 writel(0x00000003, spec->mem_base + 0xC0C);
8152 writel(0x00000003, spec->mem_base + 0xC0C);
ce715448 8153
6da8f446 8154 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8155 writel(0x00000001, spec->mem_base + 0xC08);
8156 else
8157 writel(0x000000C1, spec->mem_base + 0xC08);
8158
e93ac30a
CM		 8159 writel(0x000000F1, spec->mem_base + 0xC08);
8160 writel(0x00000001, spec->mem_base + 0xC08);
8161 writel(0x000000C7, spec->mem_base + 0xC08);
8162 writel(0x000000C1, spec->mem_base + 0xC08);
8163 writel(0x00000080, spec->mem_base + 0xC04);
ce715448 8164
6da8f446 8165 if (ca0132_quirk(spec) == QUIRK_AE5) {
ce715448
CM		 8166 writel(0x00000000, spec->mem_base + 0x42c);
8167 writel(0x00000000, spec->mem_base + 0x46c);
8168 writel(0x00000000, spec->mem_base + 0x4ac);
8169 writel(0x00000000, spec->mem_base + 0x4ec);
8170 writel(0x00000000, spec->mem_base + 0x43c);
8171 writel(0x00000000, spec->mem_base + 0x47c);
8172 writel(0x00000000, spec->mem_base + 0x4bc);
8173 writel(0x00000000, spec->mem_base + 0x4fc);
8174 writel(0x00000600, spec->mem_base + 0x100);
8175 writel(0x00000014, spec->mem_base + 0x410);
8176 writel(0x0000060f, spec->mem_base + 0x100);
8177 writel(0x0000070f, spec->mem_base + 0x100);
8178 writel(0x00000aff, spec->mem_base + 0x830);
8179 writel(0x00000000, spec->mem_base + 0x86c);
8180 writel(0x0000006b, spec->mem_base + 0x800);
8181 writel(0x00000001, spec->mem_base + 0x86c);
8182 writel(0x0000006b, spec->mem_base + 0x800);
8183 writel(0x00000057, spec->mem_base + 0x804);
8184 writel(0x00800000, spec->mem_base + 0x20c);
8185 }
e93ac30a
CM		 8186}
8187
b9b41345
CM		 8188/*
8189 * This function writes to some SFR's, does some region2 writes, and then
8190 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
8191 * what it does.
8192 */
8193static void ae5_register_set(struct hda_codec *codec)
8194{
8195 struct ca0132_spec *spec = codec->spec;
8196
8197 chipio_8051_write_direct(codec, 0x93, 0x10);
8198 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8199 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8200 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8201 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8202
8203 writeb(0x0f, spec->mem_base + 0x304);
8204 writeb(0x0f, spec->mem_base + 0x304);
8205 writeb(0x0f, spec->mem_base + 0x304);
8206 writeb(0x0f, spec->mem_base + 0x304);
8207 writeb(0x0e, spec->mem_base + 0x100);
8208 writeb(0x1f, spec->mem_base + 0x304);
8209 writeb(0x0c, spec->mem_base + 0x100);
8210 writeb(0x3f, spec->mem_base + 0x304);
8211 writeb(0x08, spec->mem_base + 0x100);
8212 writeb(0x7f, spec->mem_base + 0x304);
8213 writeb(0x00, spec->mem_base + 0x100);
8214 writeb(0xff, spec->mem_base + 0x304);
8215
8216 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
8217
8218 chipio_8051_write_direct(codec, 0x90, 0x00);
8219 chipio_8051_write_direct(codec, 0x90, 0x10);
8220
8221 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8222
8223 chipio_write(codec, 0x18b0a4, 0x000000c2);
8224
8225 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8226 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8227}
8228
e93ac30a
CM		 8229/*
8230 * Extra init functions for alternative ca0132 codecs. Done
8231 * here so they don't clutter up the main ca0132_init function
8232 * anymore than they have to.
8233 */
8234static void ca0132_alt_init(struct hda_codec *codec)
8235{
8236 struct ca0132_spec *spec = codec->spec;
8237
8238 ca0132_alt_vol_setup(codec);
8239
6da8f446 8240 switch (ca0132_quirk(spec)) {
e93ac30a
CM		 8241 case QUIRK_SBZ:
8242 codec_dbg(codec, "SBZ alt_init");
8243 ca0132_gpio_init(codec);
8244 sbz_pre_dsp_setup(codec);
8245 snd_hda_sequence_write(codec, spec->chip_init_verbs);
e42c7c73 8246 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
e93ac30a
CM		 8247 break;
8248 case QUIRK_R3DI:
8249 codec_dbg(codec, "R3DI alt_init");
8250 ca0132_gpio_init(codec);
8251 ca0132_gpio_setup(codec);
7e6ed62e 8252 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 8253 r3di_pre_dsp_setup(codec);
8254 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8255 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
8256 break;
e42c7c73
CM		 8257 case QUIRK_R3D:
8258 r3d_pre_dsp_setup(codec);
8259 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8260 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8261 break;
03c9b6b1
CM		 8262 case QUIRK_AE5:
8263 ca0132_gpio_init(codec);
8264 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8265 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
8266 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8267 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
8268 chipio_write(codec, 0x18b030, 0x00000020);
8269 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8270 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8271 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8272 break;
2e492b8e
CM		 8273 case QUIRK_ZXR:
8274 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8275 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8276 break;
6da8f446
TI		 8277 default:
8278 break;
e93ac30a
CM		 8279 }
8280}
8281
95c6e9cb
IM		 8282static int ca0132_init(struct hda_codec *codec)
8283{
8284 struct ca0132_spec *spec = codec->spec;
8285 struct auto_pin_cfg *cfg = &spec->autocfg;
8286 int i;
e93ac30a
CM		 8287 bool dsp_loaded;
8288
8289 /*
8290 * If the DSP is already downloaded, and init has been entered again,
8291 * there's only two reasons for it. One, the codec has awaken from a
8292 * suspended state, and in that case dspload_is_loaded will return
8293 * false, and the init will be ran again. The other reason it gets
8294 * re entered is on startup for some reason it triggers a suspend and
8295 * resume state. In this case, it will check if the DSP is downloaded,
8296 * and not run the init function again. For codecs using alt_functions,
8297 * it will check if the DSP is loaded properly.
8298 */
8299 if (spec->dsp_state == DSP_DOWNLOADED) {
8300 dsp_loaded = dspload_is_loaded(codec);
8301 if (!dsp_loaded) {
8302 spec->dsp_reload = true;
8303 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff 8304 } else {
6da8f446 8305 if (ca0132_quirk(spec) == QUIRK_SBZ)
38ba69ff 8306 sbz_dsp_startup_check(codec);
e93ac30a 8307 return 0;
38ba69ff 8308 }
e93ac30a 8309 }
95c6e9cb 8310
e24aa0a4
TI		 8311 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
8312 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 8313 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 8314
6da8f446 8315 if (ca0132_use_pci_mmio(spec))
e42c7c73 8316 ca0132_mmio_init(codec);
e93ac30a 8317
664c7155 8318 snd_hda_power_up_pm(codec);
5aaca44d 8319
6da8f446 8320 if (ca0132_quirk(spec) == QUIRK_AE5)
b9b41345
CM		 8321 ae5_register_set(codec);
8322
f8fb1170 8323 ca0132_init_unsol(codec);
5aaca44d
IM		 8324 ca0132_init_params(codec);
8325 ca0132_init_flags(codec);
7e6ed62e 8326
5aaca44d 8327 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 8328
6da8f446 8329 if (ca0132_use_alt_functions(spec))
e93ac30a
CM		 8330 ca0132_alt_init(codec);
8331
01ef7dbf 8332 ca0132_download_dsp(codec);
7e6ed62e 8333
5aaca44d 8334 ca0132_refresh_widget_caps(codec);
e93ac30a 8335
6da8f446 8336 switch (ca0132_quirk(spec)) {
7e6ed62e 8337 case QUIRK_R3DI:
c986f50c
CM		 8338 case QUIRK_R3D:
8339 r3d_setup_defaults(codec);
7e6ed62e 8340 break;
126b75e0 8341 case QUIRK_SBZ:
c25c73e0 8342 case QUIRK_ZXR:
d97420d2 8343 sbz_setup_defaults(codec);
126b75e0 8344 break;
415cd844
CM		 8345 case QUIRK_AE5:
8346 ae5_setup_defaults(codec);
8347 break;
126b75e0 8348 default:
38ba69ff
CM		 8349 ca0132_setup_defaults(codec);
8350 ca0132_init_analog_mic2(codec);
8351 ca0132_init_dmic(codec);
7e6ed62e 8352 break;
38ba69ff 8353 }
5aaca44d
IM		 8354
8355 for (i = 0; i < spec->num_outputs; i++)
8356 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 8357
95c6e9cb
IM		 8358 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8359
8360 for (i = 0; i < spec->num_inputs; i++)
8361 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8362
8363 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8364
6da8f446 8365 if (!ca0132_use_alt_functions(spec)) {
e93ac30a
CM		 8366 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8367 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8368 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
8369 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8370 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
8371 }
8372
6da8f446 8373 if (ca0132_quirk(spec) == QUIRK_SBZ)
e93ac30a
CM		 8374 ca0132_gpio_setup(codec);
8375
d5c016b5 8376 snd_hda_sequence_write(codec, spec->spec_init_verbs);
6da8f446 8377 if (ca0132_use_alt_functions(spec)) {
7cb9d94c
CM		 8378 ca0132_alt_select_out(codec);
8379 ca0132_alt_select_in(codec);
d97420d2 8380 } else {
7cb9d94c
CM		 8381 ca0132_select_out(codec);
8382 ca0132_select_mic(codec);
7cb9d94c 8383 }
5aaca44d 8384
a73d511c
IM		 8385 snd_hda_jack_report_sync(codec);
8386
e93ac30a
CM		 8387 /*
8388 * Re set the PlayEnhancement switch on a resume event, because the
8389 * controls will not be reloaded.
8390 */
8391 if (spec->dsp_reload) {
8392 spec->dsp_reload = false;
8393 ca0132_pe_switch_set(codec);
8394 }
8395
664c7155 8396 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 8397
8398 return 0;
8399}
8400
7675a2a9
CM		 8401static int dbpro_init(struct hda_codec *codec)
8402{
8403 struct ca0132_spec *spec = codec->spec;
8404 struct auto_pin_cfg *cfg = &spec->autocfg;
8405 unsigned int i;
8406
8407 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8408 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8409
8410 for (i = 0; i < spec->num_inputs; i++)
8411 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8412
8413 return 0;
8414}
8415
95c6e9cb
IM		 8416static void ca0132_free(struct hda_codec *codec)
8417{
5aaca44d
IM		 8418 struct ca0132_spec *spec = codec->spec;
8419
993884f6 8420 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 8421 snd_hda_power_up(codec);
6da8f446 8422 switch (ca0132_quirk(spec)) {
2e48b2b7
CM		 8423 case QUIRK_SBZ:
8424 sbz_exit_chip(codec);
8425 break;
96395e86
CM		 8426 case QUIRK_ZXR:
8427 zxr_exit_chip(codec);
8428 break;
2f295f91
CM		 8429 case QUIRK_R3D:
8430 r3d_exit_chip(codec);
8431 break;
edb1b3ab
CM		 8432 case QUIRK_AE5:
8433 ae5_exit_chip(codec);
8434 break;
2e48b2b7
CM		 8435 case QUIRK_R3DI:
8436 r3di_gpio_shutdown(codec);
2e48b2b7 8437 break;
6da8f446
TI		 8438 default:
8439 break;
2e48b2b7 8440 }
2f295f91
CM		 8441
8442 snd_hda_sequence_write(codec, spec->base_exit_verbs);
8443 ca0132_exit_chip(codec);
8444
5aaca44d 8445 snd_hda_power_down(codec);
c97617a8
TI		 8446#ifdef CONFIG_PCI
8447 if (spec->mem_base)
d99501b8 8448 pci_iounmap(codec->bus->pci, spec->mem_base);
c97617a8 8449#endif
d5c016b5 8450 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 8451 kfree(codec->spec);
8452}
8453
7675a2a9
CM		 8454static void dbpro_free(struct hda_codec *codec)
8455{
8456 struct ca0132_spec *spec = codec->spec;
8457
8458 zxr_dbpro_power_state_shutdown(codec);
8459
8460 kfree(spec->spec_init_verbs);
8461 kfree(codec->spec);
8462}
8463
2e48b2b7
CM		 8464static void ca0132_reboot_notify(struct hda_codec *codec)
8465{
8466 codec->patch_ops.free(codec);
8467}
8468
071f1344 8469static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 8470 .build_controls = ca0132_build_controls,
8471 .build_pcms = ca0132_build_pcms,
8472 .init = ca0132_init,
8473 .free = ca0132_free,
f8fb1170 8474 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 8475 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 8476};
8477
7675a2a9
CM		 8478static const struct hda_codec_ops dbpro_patch_ops = {
8479 .build_controls = dbpro_build_controls,
8480 .build_pcms = dbpro_build_pcms,
8481 .init = dbpro_init,
8482 .free = dbpro_free,
8483};
8484
441aa6a0
IM		 8485static void ca0132_config(struct hda_codec *codec)
8486{
8487 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 8488
8489 spec->dacs[0] = 0x2;
8490 spec->dacs[1] = 0x3;
8491 spec->dacs[2] = 0x4;
8492
8493 spec->multiout.dac_nids = spec->dacs;
8494 spec->multiout.num_dacs = 3;
441aa6a0 8495
6da8f446 8496 if (!ca0132_use_alt_functions(spec))
63177afc
CM		 8497 spec->multiout.max_channels = 2;
8498 else
8499 spec->multiout.max_channels = 6;
8500
6da8f446 8501 switch (ca0132_quirk(spec)) {
63177afc 8502 case QUIRK_ALIENWARE:
d06feaf0 8503 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
fe14f39e 8504 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
d06feaf0
CM		 8505 break;
8506 case QUIRK_SBZ:
8507 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
8508 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
8509 break;
6dcd7244
CM		 8510 case QUIRK_ZXR:
8511 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
8512 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
8513 break;
d06feaf0
CM		 8514 case QUIRK_R3D:
8515 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
8516 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
8517 break;
8518 case QUIRK_R3DI:
8519 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
8520 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8521 break;
8522 case QUIRK_AE5:
8523 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
a6b0961b 8524 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
d06feaf0 8525 break;
6da8f446
TI		 8526 default:
8527 break;
d06feaf0 8528 }
fe14f39e 8529
6da8f446 8530 switch (ca0132_quirk(spec)) {
d06feaf0 8531 case QUIRK_ALIENWARE:
fe14f39e
TI		 8532 spec->num_outputs = 2;
8533 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8534 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 8535 spec->shared_out_nid = 0x2;
8536 spec->unsol_tag_hp = 0x0f;
8537
8538 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8539 spec->adcs[1] = 0x8; /* analog mic2 */
8540 spec->adcs[2] = 0xa; /* what u hear */
8541
8542 spec->num_inputs = 3;
8543 spec->input_pins[0] = 0x12;
8544 spec->input_pins[1] = 0x11;
8545 spec->input_pins[2] = 0x13;
8546 spec->shared_mic_nid = 0x7;
8547 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 8548 break;
8549 case QUIRK_SBZ:
7f73df95 8550 case QUIRK_R3D:
63177afc
CM		 8551 spec->num_outputs = 2;
8552 spec->out_pins[0] = 0x0B; /* Line out */
8553 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8554 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8555 spec->out_pins[3] = 0x11; /* Rear surround */
8556 spec->shared_out_nid = 0x2;
8557 spec->unsol_tag_hp = spec->out_pins[1];
8558 spec->unsol_tag_front_hp = spec->out_pins[2];
8559
8560 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8561 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8562 spec->adcs[2] = 0xa; /* what u hear */
8563
8564 spec->num_inputs = 2;
8565 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8566 spec->input_pins[1] = 0x13; /* What U Hear */
8567 spec->shared_mic_nid = 0x7;
8568 spec->unsol_tag_amic1 = spec->input_pins[0];
8569
8570 /* SPDIF I/O */
8571 spec->dig_out = 0x05;
8572 spec->multiout.dig_out_nid = spec->dig_out;
6dcd7244
CM		 8573 spec->dig_in = 0x09;
8574 break;
8575 case QUIRK_ZXR:
8576 spec->num_outputs = 2;
8577 spec->out_pins[0] = 0x0B; /* Line out */
8578 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8579 spec->out_pins[2] = 0x10; /* Center/LFE */
8580 spec->out_pins[3] = 0x11; /* Rear surround */
8581 spec->shared_out_nid = 0x2;
8582 spec->unsol_tag_hp = spec->out_pins[1];
8583 spec->unsol_tag_front_hp = spec->out_pins[2];
8584
8585 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8586 spec->adcs[1] = 0x8; /* Not connected, no front mic */
8587 spec->adcs[2] = 0xa; /* what u hear */
8588
8589 spec->num_inputs = 2;
8590 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8591 spec->input_pins[1] = 0x13; /* What U Hear */
8592 spec->shared_mic_nid = 0x7;
8593 spec->unsol_tag_amic1 = spec->input_pins[0];
8594 break;
8595 case QUIRK_ZXR_DBPRO:
8596 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
8597
8598 spec->num_inputs = 1;
8599 spec->input_pins[0] = 0x11; /* RCA Line-in */
8600
8601 spec->dig_out = 0x05;
8602 spec->multiout.dig_out_nid = spec->dig_out;
8603
63177afc 8604 spec->dig_in = 0x09;
63177afc 8605 break;
d06feaf0
CM		 8606 case QUIRK_AE5:
8607 spec->num_outputs = 2;
8608 spec->out_pins[0] = 0x0B; /* Line out */
8609 spec->out_pins[1] = 0x11; /* Rear headphone out */
8610 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8611 spec->out_pins[3] = 0x0F; /* Rear surround */
8612 spec->shared_out_nid = 0x2;
8613 spec->unsol_tag_hp = spec->out_pins[1];
8614 spec->unsol_tag_front_hp = spec->out_pins[2];
8615
8616 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8617 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8618 spec->adcs[2] = 0xa; /* what u hear */
63177afc 8619
d06feaf0
CM		 8620 spec->num_inputs = 2;
8621 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8622 spec->input_pins[1] = 0x13; /* What U Hear */
8623 spec->shared_mic_nid = 0x7;
8624 spec->unsol_tag_amic1 = spec->input_pins[0];
8625
8626 /* SPDIF I/O */
8627 spec->dig_out = 0x05;
8628 spec->multiout.dig_out_nid = spec->dig_out;
8629 break;
8630 case QUIRK_R3DI:
63177afc
CM		 8631 spec->num_outputs = 2;
8632 spec->out_pins[0] = 0x0B; /* Line out */
8633 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8634 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8635 spec->out_pins[3] = 0x11; /* Rear surround */
8636 spec->shared_out_nid = 0x2;
8637 spec->unsol_tag_hp = spec->out_pins[1];
8638 spec->unsol_tag_front_hp = spec->out_pins[2];
8639
8640 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
8641 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
8642 spec->adcs[2] = 0x0a; /* what u hear */
8643
8644 spec->num_inputs = 2;
8645 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8646 spec->input_pins[1] = 0x13; /* What U Hear */
8647 spec->shared_mic_nid = 0x7;
8648 spec->unsol_tag_amic1 = spec->input_pins[0];
8649
8650 /* SPDIF I/O */
8651 spec->dig_out = 0x05;
8652 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 8653 break;
8654 default:
fe14f39e
TI		 8655 spec->num_outputs = 2;
8656 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8657 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 8658 spec->shared_out_nid = 0x2;
8659 spec->unsol_tag_hp = spec->out_pins[1];
8660
8661 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8662 spec->adcs[1] = 0x8; /* analog mic2 */
8663 spec->adcs[2] = 0xa; /* what u hear */
8664
8665 spec->num_inputs = 3;
8666 spec->input_pins[0] = 0x12;
8667 spec->input_pins[1] = 0x11;
8668 spec->input_pins[2] = 0x13;
8669 spec->shared_mic_nid = 0x7;
8670 spec->unsol_tag_amic1 = spec->input_pins[0];
8671
8672 /* SPDIF I/O */
8673 spec->dig_out = 0x05;
8674 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 8675 spec->dig_in = 0x09;
63177afc 8676 break;
d5c016b5 8677 }
441aa6a0
IM		 8678}
8679
d5c016b5
GM		 8680static int ca0132_prepare_verbs(struct hda_codec *codec)
8681{
8682/* Verbs + terminator (an empty element) */
a3d90d67 8683#define NUM_SPEC_VERBS 2
d5c016b5
GM		 8684 struct ca0132_spec *spec = codec->spec;
8685
8686 spec->chip_init_verbs = ca0132_init_verbs0;
88268ce8
CM		 8687 /*
8688 * Since desktop cards use pci_mmio, this can be used to determine
8689 * whether or not to use these verbs instead of a separate bool.
8690 */
6da8f446 8691 if (ca0132_use_pci_mmio(spec))
e42c7c73 8692 spec->desktop_init_verbs = ca0132_init_verbs1;
6396bb22
KC		 8693 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
8694 sizeof(struct hda_verb),
8695 GFP_KERNEL);
d5c016b5
GM		 8696 if (!spec->spec_init_verbs)
8697 return -ENOMEM;
8698
d5c016b5 8699 /* config EAPD */
a3d90d67
AB		 8700 spec->spec_init_verbs[0].nid = 0x0b;
8701 spec->spec_init_verbs[0].param = 0x78D;
8702 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 8703
8704 /* Previously commented configuration */
8705 /*
a3d90d67
AB		 8706 spec->spec_init_verbs[2].nid = 0x0b;
8707 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8708 spec->spec_init_verbs[2].verb = 0x02;
8709
8710 spec->spec_init_verbs[3].nid = 0x10;
8711 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 8712 spec->spec_init_verbs[3].verb = 0x02;
8713
8714 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 8715 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 8716 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 8717 */
8718
8719 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8720 return 0;
8721}
8722
b29733db
CM		 8723/*
8724 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
8725 * Sound Blaster Z cards. However, they have different HDA codec subsystem
8726 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
8727 * daughter boards ID.
8728 */
8729static void sbz_detect_quirk(struct hda_codec *codec)
8730{
8731 struct ca0132_spec *spec = codec->spec;
8732
8733 switch (codec->core.subsystem_id) {
8734 case 0x11020033:
8735 spec->quirk = QUIRK_ZXR;
8736 break;
8737 case 0x1102003f:
8738 spec->quirk = QUIRK_ZXR_DBPRO;
8739 break;
8740 default:
8741 spec->quirk = QUIRK_SBZ;
8742 break;
8743 }
8744}
8745
95c6e9cb
IM		 8746static int patch_ca0132(struct hda_codec *codec)
8747{
8748 struct ca0132_spec *spec;
a73d511c 8749 int err;
d5c016b5 8750 const struct snd_pci_quirk *quirk;
95c6e9cb 8751
4e76a883 8752 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 8753
8754 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8755 if (!spec)
8756 return -ENOMEM;
8757 codec->spec = spec;
993884f6 8758 spec->codec = codec;
95c6e9cb 8759
d5c016b5
GM		 8760 /* Detect codec quirk */
8761 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8762 if (quirk)
8763 spec->quirk = quirk->value;
8764 else
8765 spec->quirk = QUIRK_NONE;
6da8f446 8766 if (ca0132_quirk(spec) == QUIRK_SBZ)
b29733db
CM		 8767 sbz_detect_quirk(codec);
8768
6da8f446 8769 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
ebabde1e
CM		 8770 codec->patch_ops = dbpro_patch_ops;
8771 else
8772 codec->patch_ops = ca0132_patch_ops;
8773
8774 codec->pcm_format_first = 1;
8775 codec->no_sticky_stream = 1;
8776
8777
e24aa0a4 8778 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 8779 spec->num_mixers = 1;
017310fb
CM		 8780
8781 /* Set which mixers each quirk uses. */
6da8f446 8782 switch (ca0132_quirk(spec)) {
017310fb 8783 case QUIRK_SBZ:
e25e3445 8784 spec->mixers[0] = desktop_mixer;
017310fb
CM		 8785 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8786 break;
2e492b8e
CM		 8787 case QUIRK_ZXR:
8788 spec->mixers[0] = desktop_mixer;
8789 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
8790 break;
7675a2a9 8791 case QUIRK_ZXR_DBPRO:
7675a2a9 8792 break;
e25e3445
CM		 8793 case QUIRK_R3D:
8794 spec->mixers[0] = desktop_mixer;
8795 snd_hda_codec_set_name(codec, "Recon3D");
8796 break;
017310fb
CM		 8797 case QUIRK_R3DI:
8798 spec->mixers[0] = r3di_mixer;
8799 snd_hda_codec_set_name(codec, "Recon3Di");
8800 break;
88268ce8
CM		 8801 case QUIRK_AE5:
8802 spec->mixers[0] = desktop_mixer;
8803 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8804 break;
017310fb
CM		 8805 default:
8806 spec->mixers[0] = ca0132_mixer;
8807 break;
8808 }
a7e76271 8809
08eca6b1 8810 /* Setup whether or not to use alt functions/controls/pci_mmio */
6da8f446 8811 switch (ca0132_quirk(spec)) {
009b8f97 8812 case QUIRK_SBZ:
e42c7c73 8813 case QUIRK_R3D:
88268ce8 8814 case QUIRK_AE5:
2e492b8e 8815 case QUIRK_ZXR:
08eca6b1
CM		 8816 spec->use_alt_controls = true;
8817 spec->use_alt_functions = true;
8818 spec->use_pci_mmio = true;
8819 break;
009b8f97 8820 case QUIRK_R3DI:
47cdf76e 8821 spec->use_alt_controls = true;
009b8f97 8822 spec->use_alt_functions = true;
08eca6b1 8823 spec->use_pci_mmio = false;
009b8f97
CM		 8824 break;
8825 default:
47cdf76e 8826 spec->use_alt_controls = false;
009b8f97 8827 spec->use_alt_functions = false;
08eca6b1 8828 spec->use_pci_mmio = false;
009b8f97
CM		 8829 break;
8830 }
8831
6da8f446 8832#ifdef CONFIG_PCI
08eca6b1
CM		 8833 if (spec->use_pci_mmio) {
8834 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8835 if (spec->mem_base == NULL) {
8836 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8837 spec->quirk = QUIRK_NONE;
8838 }
8839 }
6da8f446 8840#endif
08eca6b1 8841
5aaca44d
IM		 8842 spec->base_init_verbs = ca0132_base_init_verbs;
8843 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 8844
993884f6
CCC		 8845 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8846
95c6e9cb
IM		 8847 ca0132_init_chip(codec);
8848
8849 ca0132_config(codec);
8850
d5c016b5
GM		 8851 err = ca0132_prepare_verbs(codec);
8852 if (err < 0)
cc91ceaf 8853 goto error;
d5c016b5 8854
a73d511c
IM		 8855 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8856 if (err < 0)
cc91ceaf 8857 goto error;
a73d511c 8858
95c6e9cb 8859 return 0;
cc91ceaf
TI		 8860
8861 error:
8862 ca0132_free(codec);
8863 return err;
95c6e9cb
IM		 8864}
8865
8866/*
8867 * patch entries
8868 */
b9a94a9c
TI		 8869static struct hda_device_id snd_hda_id_ca0132[] = {
8870 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 8871 {} /* terminator */
8872};
b9a94a9c 8873MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 8874
8875MODULE_LICENSE("GPL");
406261ce 8876MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 8877
d8a766a1 8878static struct hda_codec_driver ca0132_driver = {
b9a94a9c 8879 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 8880};
8881
d8a766a1 8882module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)