projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda/ca0132 - Add alt_functions unsolicited response
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb
IM		 34#include <sound/core.h>
35#include "hda_codec.h"
36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
38ba69ff 52#define FLOAT_THREE 0x40400000
7cb9d94c 53#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 54#define FLOAT_MINUS_5 0xc0a00000
55
ef6b2ead
IM		 56#define UNSOL_TAG_DSP 0x16
57
4aa3bb0c
IM		 58#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
ef6b2ead
IM		 66#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 68
95c6e9cb
IM		 69#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
4aa3bb0c
IM		 72#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
01ef7dbf 83#define EFX_FILE "ctefx.bin"
8a19bcee
CM		 84#define SBZ_EFX_FILE "ctefx-sbz.bin"
85#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 86
24f3cede 87#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 88MODULE_FIRMWARE(EFX_FILE);
8a19bcee
CM		 89MODULE_FIRMWARE(SBZ_EFX_FILE);
90MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 91#endif
01ef7dbf 92
3a03f83b 93static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 94
7cb9d94c 95#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 96enum {
97 SPEAKER_OUT,
7cb9d94c
CM		 98 HEADPHONE_OUT,
99 SURROUND_OUT
ef6b2ead
IM		 100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
7cb9d94c 107/* Strings for Input Source Enum Control */
3a03f83b 108static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
ef6b2ead
IM		 116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
7cb9d94c
CM		 149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
155 MIC_BOOST_ENUM
ef6b2ead
IM		 156#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
157};
158
159/* Effects values size*/
160#define EFFECT_VALS_MAX_COUNT 12
161
47cdf76e
CM		 162/*
163 * Default values for the effect slider controls, they are in order of their
164 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
165 * X-bass.
166 */
167static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
168/* Amount of effect level sliders for ca0132_alt controls. */
169#define EFFECT_LEVEL_SLIDERS 5
170
e8412ca4
DR		 171/* Latency introduced by DSP blocks in milliseconds. */
172#define DSP_CAPTURE_INIT_LATENCY 0
173#define DSP_CRYSTAL_VOICE_LATENCY 124
174#define DSP_PLAYBACK_INIT_LATENCY 13
175#define DSP_PLAY_ENHANCEMENT_LATENCY 30
176#define DSP_SPEAKER_OUT_LATENCY 7
177
ef6b2ead 178struct ct_effect {
975cc02a 179 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 180 hda_nid_t nid;
181 int mid; /*effect module ID*/
182 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
183 int direct; /* 0:output; 1:input*/
184 int params; /* number of default non-on/off params */
185 /*effect default values, 1st is on/off. */
186 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
187};
188
189#define EFX_DIR_OUT 0
190#define EFX_DIR_IN 1
191
862154bb 192static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 193 { .name = "Surround",
194 .nid = SURROUND,
195 .mid = 0x96,
196 .reqs = {0, 1},
197 .direct = EFX_DIR_OUT,
198 .params = 1,
199 .def_vals = {0x3F800000, 0x3F2B851F}
200 },
201 { .name = "Crystalizer",
202 .nid = CRYSTALIZER,
203 .mid = 0x96,
204 .reqs = {7, 8},
205 .direct = EFX_DIR_OUT,
206 .params = 1,
207 .def_vals = {0x3F800000, 0x3F266666}
208 },
209 { .name = "Dialog Plus",
210 .nid = DIALOG_PLUS,
211 .mid = 0x96,
212 .reqs = {2, 3},
213 .direct = EFX_DIR_OUT,
214 .params = 1,
215 .def_vals = {0x00000000, 0x3F000000}
216 },
217 { .name = "Smart Volume",
218 .nid = SMART_VOLUME,
219 .mid = 0x96,
220 .reqs = {4, 5, 6},
221 .direct = EFX_DIR_OUT,
222 .params = 2,
223 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
224 },
225 { .name = "X-Bass",
226 .nid = X_BASS,
227 .mid = 0x96,
228 .reqs = {24, 23, 25},
229 .direct = EFX_DIR_OUT,
230 .params = 2,
231 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
232 },
233 { .name = "Equalizer",
234 .nid = EQUALIZER,
235 .mid = 0x96,
236 .reqs = {9, 10, 11, 12, 13, 14,
237 15, 16, 17, 18, 19, 20},
238 .direct = EFX_DIR_OUT,
239 .params = 11,
240 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
241 0x00000000, 0x00000000, 0x00000000, 0x00000000,
242 0x00000000, 0x00000000, 0x00000000, 0x00000000}
243 },
244 { .name = "Echo Cancellation",
245 .nid = ECHO_CANCELLATION,
246 .mid = 0x95,
247 .reqs = {0, 1, 2, 3},
248 .direct = EFX_DIR_IN,
249 .params = 3,
250 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
251 },
252 { .name = "Voice Focus",
253 .nid = VOICE_FOCUS,
254 .mid = 0x95,
255 .reqs = {6, 7, 8, 9},
256 .direct = EFX_DIR_IN,
257 .params = 3,
258 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
259 },
260 { .name = "Mic SVM",
261 .nid = MIC_SVM,
262 .mid = 0x95,
263 .reqs = {44, 45},
264 .direct = EFX_DIR_IN,
265 .params = 1,
266 .def_vals = {0x00000000, 0x3F3D70A4}
267 },
268 { .name = "Noise Reduction",
269 .nid = NOISE_REDUCTION,
270 .mid = 0x95,
271 .reqs = {4, 5},
272 .direct = EFX_DIR_IN,
273 .params = 1,
274 .def_vals = {0x3F800000, 0x3F000000}
275 },
276 { .name = "VoiceFX",
277 .nid = VOICEFX,
278 .mid = 0x95,
279 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
280 .direct = EFX_DIR_IN,
281 .params = 8,
282 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
283 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
284 0x00000000}
285 }
286};
287
288/* Tuning controls */
289#ifdef ENABLE_TUNING_CONTROLS
290
291enum {
292#define TUNING_CTL_START_NID 0xC0
293 WEDGE_ANGLE = TUNING_CTL_START_NID,
294 SVM_LEVEL,
295 EQUALIZER_BAND_0,
296 EQUALIZER_BAND_1,
297 EQUALIZER_BAND_2,
298 EQUALIZER_BAND_3,
299 EQUALIZER_BAND_4,
300 EQUALIZER_BAND_5,
301 EQUALIZER_BAND_6,
302 EQUALIZER_BAND_7,
303 EQUALIZER_BAND_8,
304 EQUALIZER_BAND_9,
305 TUNING_CTL_END_NID
306#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
307};
308
309struct ct_tuning_ctl {
975cc02a 310 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 311 hda_nid_t parent_nid;
312 hda_nid_t nid;
313 int mid; /*effect module ID*/
314 int req; /*effect module request*/
315 int direct; /* 0:output; 1:input*/
316 unsigned int def_val;/*effect default values*/
317};
318
862154bb 319static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 320 { .name = "Wedge Angle",
321 .parent_nid = VOICE_FOCUS,
322 .nid = WEDGE_ANGLE,
323 .mid = 0x95,
324 .req = 8,
325 .direct = EFX_DIR_IN,
326 .def_val = 0x41F00000
327 },
328 { .name = "SVM Level",
329 .parent_nid = MIC_SVM,
330 .nid = SVM_LEVEL,
331 .mid = 0x95,
332 .req = 45,
333 .direct = EFX_DIR_IN,
334 .def_val = 0x3F3D70A4
335 },
336 { .name = "EQ Band0",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_0,
339 .mid = 0x96,
340 .req = 11,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
343 },
344 { .name = "EQ Band1",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_1,
347 .mid = 0x96,
348 .req = 12,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
351 },
352 { .name = "EQ Band2",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_2,
355 .mid = 0x96,
356 .req = 13,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
359 },
360 { .name = "EQ Band3",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_3,
363 .mid = 0x96,
364 .req = 14,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
367 },
368 { .name = "EQ Band4",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_4,
371 .mid = 0x96,
372 .req = 15,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
375 },
376 { .name = "EQ Band5",
377 .parent_nid = EQUALIZER,
378 .nid = EQUALIZER_BAND_5,
379 .mid = 0x96,
380 .req = 16,
381 .direct = EFX_DIR_OUT,
382 .def_val = 0x00000000
383 },
384 { .name = "EQ Band6",
385 .parent_nid = EQUALIZER,
386 .nid = EQUALIZER_BAND_6,
387 .mid = 0x96,
388 .req = 17,
389 .direct = EFX_DIR_OUT,
390 .def_val = 0x00000000
391 },
392 { .name = "EQ Band7",
393 .parent_nid = EQUALIZER,
394 .nid = EQUALIZER_BAND_7,
395 .mid = 0x96,
396 .req = 18,
397 .direct = EFX_DIR_OUT,
398 .def_val = 0x00000000
399 },
400 { .name = "EQ Band8",
401 .parent_nid = EQUALIZER,
402 .nid = EQUALIZER_BAND_8,
403 .mid = 0x96,
404 .req = 19,
405 .direct = EFX_DIR_OUT,
406 .def_val = 0x00000000
407 },
408 { .name = "EQ Band9",
409 .parent_nid = EQUALIZER,
410 .nid = EQUALIZER_BAND_9,
411 .mid = 0x96,
412 .req = 20,
413 .direct = EFX_DIR_OUT,
414 .def_val = 0x00000000
415 }
416};
417#endif
418
419/* Voice FX Presets */
420#define VOICEFX_MAX_PARAM_COUNT 9
421
422struct ct_voicefx {
423 char *name;
424 hda_nid_t nid;
425 int mid;
426 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
427};
428
429struct ct_voicefx_preset {
430 char *name; /*preset name*/
431 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
432};
433
862154bb 434static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 435 .name = "VoiceFX Capture Switch",
436 .nid = VOICEFX,
437 .mid = 0x95,
438 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
439};
440
862154bb 441static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 442 { .name = "Neutral",
443 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
444 0x44FA0000, 0x3F800000, 0x3F800000,
445 0x3F800000, 0x00000000, 0x00000000 }
446 },
447 { .name = "Female2Male",
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3F19999A, 0x3F866666,
450 0x3F800000, 0x00000000, 0x00000000 }
451 },
452 { .name = "Male2Female",
453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
454 0x450AC000, 0x4017AE14, 0x3F6B851F,
455 0x3F800000, 0x00000000, 0x00000000 }
456 },
457 { .name = "ScrappyKid",
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x40400000, 0x3F28F5C3,
460 0x3F800000, 0x00000000, 0x00000000 }
461 },
462 { .name = "Elderly",
463 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
464 0x44E10000, 0x3FB33333, 0x3FB9999A,
465 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 },
467 { .name = "Orc",
468 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
469 0x45098000, 0x3F266666, 0x3FC00000,
470 0x3F800000, 0x00000000, 0x00000000 }
471 },
472 { .name = "Elf",
473 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
474 0x45193000, 0x3F8E147B, 0x3F75C28F,
475 0x3F800000, 0x00000000, 0x00000000 }
476 },
477 { .name = "Dwarf",
478 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
479 0x45007000, 0x3F451EB8, 0x3F7851EC,
480 0x3F800000, 0x00000000, 0x00000000 }
481 },
482 { .name = "AlienBrute",
483 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
484 0x451F6000, 0x3F266666, 0x3FA7D945,
485 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 },
487 { .name = "Robot",
488 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
489 0x44FA0000, 0x3FB2718B, 0x3F800000,
490 0xBC07010E, 0x00000000, 0x00000000 }
491 },
492 { .name = "Marine",
493 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
494 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
495 0x3F0A3D71, 0x00000000, 0x00000000 }
496 },
497 { .name = "Emo",
498 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
499 0x44FA0000, 0x3F800000, 0x3F800000,
500 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 },
502 { .name = "DeepVoice",
503 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
504 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
505 0x3F800000, 0x00000000, 0x00000000 }
506 },
507 { .name = "Munchkin",
508 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
509 0x44FA0000, 0x3F800000, 0x3F1A043C,
510 0x3F800000, 0x00000000, 0x00000000 }
511 }
512};
513
47cdf76e
CM		 514/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
515
516#define EQ_PRESET_MAX_PARAM_COUNT 11
517
518struct ct_eq {
519 char *name;
520 hda_nid_t nid;
521 int mid;
522 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
523};
524
525struct ct_eq_preset {
526 char *name; /*preset name*/
527 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
528};
529
862154bb 530static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 531 .name = "FX: Equalizer Preset Switch",
532 .nid = EQ_PRESET_ENUM,
533 .mid = 0x96,
534 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
535};
536
537
862154bb 538static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 539 { .name = "Flat",
540 .vals = { 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000, 0x00000000,
542 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000 }
544 },
545 { .name = "Acoustic",
546 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
547 0x40000000, 0x00000000, 0x00000000,
548 0x00000000, 0x00000000, 0x40000000,
549 0x40000000, 0x40000000 }
550 },
551 { .name = "Classical",
552 .vals = { 0x00000000, 0x00000000, 0x40C00000,
553 0x40C00000, 0x40466666, 0x00000000,
554 0x00000000, 0x00000000, 0x00000000,
555 0x40466666, 0x40466666 }
556 },
557 { .name = "Country",
558 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
559 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
560 0x00000000, 0x00000000, 0x40000000,
561 0x40466666, 0x40800000 }
562 },
563 { .name = "Dance",
564 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
565 0x40466666, 0x40866666, 0xBF99999A,
566 0xBF99999A, 0x00000000, 0x00000000,
567 0x40800000, 0x40800000 }
568 },
569 { .name = "Jazz",
570 .vals = { 0x00000000, 0x00000000, 0x00000000,
571 0x3F8CCCCD, 0x40800000, 0x40800000,
572 0x40800000, 0x00000000, 0x3F8CCCCD,
573 0x40466666, 0x40466666 }
574 },
575 { .name = "New Age",
576 .vals = { 0x00000000, 0x00000000, 0x40000000,
577 0x40000000, 0x00000000, 0x00000000,
578 0x00000000, 0x3F8CCCCD, 0x40000000,
579 0x40000000, 0x40000000 }
580 },
581 { .name = "Pop",
582 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
583 0x40000000, 0x40000000, 0x00000000,
584 0xBF99999A, 0xBF99999A, 0x00000000,
585 0x40466666, 0x40C00000 }
586 },
587 { .name = "Rock",
588 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
589 0x3F8CCCCD, 0x40000000, 0xBF99999A,
590 0xBF99999A, 0x00000000, 0x00000000,
591 0x40800000, 0x40800000 }
592 },
593 { .name = "Vocal",
594 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
595 0xBF99999A, 0x00000000, 0x40466666,
596 0x40800000, 0x40466666, 0x00000000,
597 0x00000000, 0x3F8CCCCD }
598 }
599};
600
7cb9d94c
CM		 601/* DSP command sequences for ca0132_alt_select_out */
602#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
603struct ca0132_alt_out_set {
604 char *name; /*preset name*/
605 unsigned char commands;
606 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
607 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
608 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
609};
610
611static const struct ca0132_alt_out_set alt_out_presets[] = {
612 { .name = "Line Out",
613 .commands = 7,
614 .mids = { 0x96, 0x96, 0x96, 0x8F,
615 0x96, 0x96, 0x96 },
616 .reqs = { 0x19, 0x17, 0x18, 0x01,
617 0x1F, 0x15, 0x3A },
618 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
619 0x00000000, 0x00000000, 0x00000000,
620 0x00000000 }
621 },
622 { .name = "Headphone",
623 .commands = 7,
624 .mids = { 0x96, 0x96, 0x96, 0x8F,
625 0x96, 0x96, 0x96 },
626 .reqs = { 0x19, 0x17, 0x18, 0x01,
627 0x1F, 0x15, 0x3A },
628 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
629 0x00000000, 0x00000000, 0x00000000,
630 0x00000000 }
631 },
632 { .name = "Surround",
633 .commands = 8,
634 .mids = { 0x96, 0x8F, 0x96, 0x96,
635 0x96, 0x96, 0x96, 0x96 },
636 .reqs = { 0x18, 0x01, 0x1F, 0x15,
637 0x3A, 0x1A, 0x1B, 0x1C },
638 .vals = { 0x00000000, 0x00000000, 0x00000000,
639 0x00000000, 0x00000000, 0x00000000,
640 0x00000000, 0x00000000 }
641 }
642};
643
017310fb
CM		 644/*
645 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
646 * and I don't know what the third req is, but it's always zero. I assume it's
647 * some sort of update or set command to tell the DSP there's new volume info.
648 */
649#define DSP_VOL_OUT 0
650#define DSP_VOL_IN 1
651
652struct ct_dsp_volume_ctl {
653 hda_nid_t vnid;
654 int mid; /* module ID*/
655 unsigned int reqs[3]; /* scp req ID */
656};
657
862154bb 658static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 659 { .vnid = VNID_SPK,
660 .mid = 0x32,
661 .reqs = {3, 4, 2}
662 },
663 { .vnid = VNID_MIC,
664 .mid = 0x37,
665 .reqs = {2, 3, 1}
666 }
667};
668
95c6e9cb
IM		 669enum hda_cmd_vendor_io {
670 /* for DspIO node */
671 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
672 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
673
674 VENDOR_DSPIO_STATUS = 0xF01,
675 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
676 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
677 VENDOR_DSPIO_DSP_INIT = 0x703,
678 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
679 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
680
681 /* for ChipIO node */
682 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
683 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
684 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
685 VENDOR_CHIPIO_DATA_LOW = 0x300,
686 VENDOR_CHIPIO_DATA_HIGH = 0x400,
687
688 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
689 VENDOR_CHIPIO_STATUS = 0xF01,
690 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
691 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
692
4aa3bb0c
IM		 693 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
694 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
695
95c6e9cb 696 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 697 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 698
699 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
700 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
701 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
702 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
703 VENDOR_CHIPIO_FLAG_SET = 0x70F,
704 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 705 VENDOR_CHIPIO_PARAM_SET = 0x710,
706 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 707
708 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
709 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
710 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
711 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
712
4aa3bb0c
IM		 713 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
714 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
715 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
716 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
717
718 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
719 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
720 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
721 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
722 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
723 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
724
725 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 726};
727
728/*
729 * Control flag IDs
730 */
731enum control_flag_id {
732 /* Connection manager stream setup is bypassed/enabled */
733 CONTROL_FLAG_C_MGR = 0,
734 /* DSP DMA is bypassed/enabled */
735 CONTROL_FLAG_DMA = 1,
736 /* 8051 'idle' mode is disabled/enabled */
737 CONTROL_FLAG_IDLE_ENABLE = 2,
738 /* Tracker for the SPDIF-in path is bypassed/enabled */
739 CONTROL_FLAG_TRACKER = 3,
740 /* DigitalOut to Spdif2Out connection is disabled/enabled */
741 CONTROL_FLAG_SPDIF2OUT = 4,
742 /* Digital Microphone is disabled/enabled */
743 CONTROL_FLAG_DMIC = 5,
744 /* ADC_B rate is 48 kHz/96 kHz */
745 CONTROL_FLAG_ADC_B_96KHZ = 6,
746 /* ADC_C rate is 48 kHz/96 kHz */
747 CONTROL_FLAG_ADC_C_96KHZ = 7,
748 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
749 CONTROL_FLAG_DAC_96KHZ = 8,
750 /* DSP rate is 48 kHz/96 kHz */
751 CONTROL_FLAG_DSP_96KHZ = 9,
752 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
753 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
754 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
755 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
756 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
757 CONTROL_FLAG_DECODE_LOOP = 12,
758 /* De-emphasis filter on DAC-1 disabled/enabled */
759 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
760 /* De-emphasis filter on DAC-2 disabled/enabled */
761 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
762 /* De-emphasis filter on DAC-3 disabled/enabled */
763 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
764 /* High-pass filter on ADC_B disabled/enabled */
765 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
766 /* High-pass filter on ADC_C disabled/enabled */
767 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
768 /* Common mode on Port_A disabled/enabled */
769 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
770 /* Common mode on Port_D disabled/enabled */
771 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
772 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
773 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
774 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 775 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 776 /* ASI rate is 48kHz/96kHz */
777 CONTROL_FLAG_ASI_96KHZ = 22,
778 /* DAC power settings able to control attached ports no/yes */
779 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
780 /* Clock Stop OK reporting is disabled/enabled */
781 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
782 /* Number of control flags */
783 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
784};
785
786/*
787 * Control parameter IDs
788 */
4aa3bb0c 789enum control_param_id {
ef6b2ead
IM		 790 /* 0: None, 1: Mic1In*/
791 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 792 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
793 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 794 /* Port A output stage gain setting to use when 16 Ohm output
795 * impedance is selected*/
796 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
797 /* Port D output stage gain setting to use when 16 Ohm output
798 * impedance is selected*/
799 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 800
801 /* Stream Control */
802
803 /* Select stream with the given ID */
804 CONTROL_PARAM_STREAM_ID = 24,
805 /* Source connection point for the selected stream */
806 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
807 /* Destination connection point for the selected stream */
808 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
809 /* Number of audio channels in the selected stream */
810 CONTROL_PARAM_STREAMS_CHANNELS = 27,
811 /*Enable control for the selected stream */
812 CONTROL_PARAM_STREAM_CONTROL = 28,
813
814 /* Connection Point Control */
815
816 /* Select connection point with the given ID */
817 CONTROL_PARAM_CONN_POINT_ID = 29,
818 /* Connection point sample rate */
819 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
820
821 /* Node Control */
822
823 /* Select HDA node with the given ID */
824 CONTROL_PARAM_NODE_ID = 31
825};
826
827/*
828 * Dsp Io Status codes
829 */
830enum hda_vendor_status_dspio {
831 /* Success */
832 VENDOR_STATUS_DSPIO_OK = 0x00,
833 /* Busy, unable to accept new command, the host must retry */
834 VENDOR_STATUS_DSPIO_BUSY = 0x01,
835 /* SCP command queue is full */
836 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
837 /* SCP response queue is empty */
838 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
839};
840
841/*
842 * Chip Io Status codes
843 */
844enum hda_vendor_status_chipio {
845 /* Success */
846 VENDOR_STATUS_CHIPIO_OK = 0x00,
847 /* Busy, unable to accept new command, the host must retry */
848 VENDOR_STATUS_CHIPIO_BUSY = 0x01
849};
850
851/*
852 * CA0132 sample rate
853 */
854enum ca0132_sample_rate {
855 SR_6_000 = 0x00,
856 SR_8_000 = 0x01,
857 SR_9_600 = 0x02,
858 SR_11_025 = 0x03,
859 SR_16_000 = 0x04,
860 SR_22_050 = 0x05,
861 SR_24_000 = 0x06,
862 SR_32_000 = 0x07,
863 SR_44_100 = 0x08,
864 SR_48_000 = 0x09,
865 SR_88_200 = 0x0A,
866 SR_96_000 = 0x0B,
867 SR_144_000 = 0x0C,
868 SR_176_400 = 0x0D,
869 SR_192_000 = 0x0E,
870 SR_384_000 = 0x0F,
871
872 SR_COUNT = 0x10,
873
874 SR_RATE_UNKNOWN = 0x1F
875};
876
01ef7dbf
IM		 877enum dsp_download_state {
878 DSP_DOWNLOAD_FAILED = -1,
879 DSP_DOWNLOAD_INIT = 0,
880 DSP_DOWNLOADING = 1,
881 DSP_DOWNLOADED = 2
882};
883
01ef7dbf
IM		 884/* retrieve parameters from hda format */
885#define get_hdafmt_chs(fmt) (fmt & 0xf)
886#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
887#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
888#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
889
890/*
891 * CA0132 specific
892 */
893
894struct ca0132_spec {
b0eaa072 895 const struct snd_kcontrol_new *mixers[5];
a7e76271 896 unsigned int num_mixers;
5aaca44d
IM		 897 const struct hda_verb *base_init_verbs;
898 const struct hda_verb *base_exit_verbs;
d5c016b5 899 const struct hda_verb *chip_init_verbs;
e93ac30a 900 const struct hda_verb *sbz_init_verbs;
d5c016b5 901 struct hda_verb *spec_init_verbs;
01ef7dbf 902 struct auto_pin_cfg autocfg;
5aaca44d
IM		 903
904 /* Nodes configurations */
01ef7dbf
IM		 905 struct hda_multi_out multiout;
906 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
907 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 908 unsigned int num_outputs;
01ef7dbf
IM		 909 hda_nid_t input_pins[AUTO_PIN_LAST];
910 hda_nid_t adcs[AUTO_PIN_LAST];
911 hda_nid_t dig_out;
912 hda_nid_t dig_in;
913 unsigned int num_inputs;
a7e76271
IM		 914 hda_nid_t shared_mic_nid;
915 hda_nid_t shared_out_nid;
d5c016b5 916 hda_nid_t unsol_tag_hp;
63177afc 917 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 918 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 919
920 /* chip access */
921 struct mutex chipio_mutex; /* chip access mutex */
922 u32 curr_chip_addx;
923
924 /* DSP download related */
925 enum dsp_download_state dsp_state;
926 unsigned int dsp_stream_id;
927 unsigned int wait_scp;
928 unsigned int wait_scp_header;
929 unsigned int wait_num_data;
930 unsigned int scp_resp_header;
931 unsigned int scp_resp_data[4];
932 unsigned int scp_resp_count;
8a19bcee 933 bool alt_firmware_present;
38ba69ff 934 bool startup_check_entered;
e93ac30a 935 bool dsp_reload;
5aaca44d
IM		 936
937 /* mixer and effects related */
938 unsigned char dmic_ctl;
939 int cur_out_type;
940 int cur_mic_type;
941 long vnode_lvol[VNODES_COUNT];
942 long vnode_rvol[VNODES_COUNT];
943 long vnode_lswitch[VNODES_COUNT];
944 long vnode_rswitch[VNODES_COUNT];
945 long effects_switch[EFFECTS_COUNT];
946 long voicefx_val;
947 long cur_mic_boost;
7cb9d94c
CM		 948 /* ca0132_alt control related values */
949 unsigned char in_enum_val;
950 unsigned char out_enum_val;
47cdf76e
CM		 951 unsigned char mic_boost_enum_val;
952 unsigned char smart_volume_setting;
953 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
954 long xbass_xover_freq;
955 long eq_preset_val;
956 unsigned int tlv[4];
957 struct hda_vmaster_mute_hook vmaster_mute;
958
44f0c978 959
993884f6
CCC		 960 struct hda_codec *codec;
961 struct delayed_work unsol_hp_work;
d5c016b5 962 int quirk;
993884f6 963
44f0c978
IM		 964#ifdef ENABLE_TUNING_CONTROLS
965 long cur_ctl_vals[TUNING_CTLS_COUNT];
966#endif
aa31704f
CM		 967 /*
968 * Sound Blaster Z PCI region 2 iomem, used for input and output
969 * switching, and other unknown commands.
970 */
971 void __iomem *mem_base;
009b8f97
CM		 972
973 /*
974 * Whether or not to use the alt functions like alt_select_out,
975 * alt_select_in, etc. Only used on desktop codecs for now, because of
976 * surround sound support.
977 */
978 bool use_alt_functions;
47cdf76e
CM		 979
980 /*
981 * Whether or not to use alt controls: volume effect sliders, EQ
982 * presets, smart volume presets, and new control names with FX prefix.
983 * Renames PlayEnhancement and CrystalVoice too.
984 */
985 bool use_alt_controls;
01ef7dbf
IM		 986};
987
d5c016b5
GM		 988/*
989 * CA0132 quirks table
990 */
991enum {
992 QUIRK_NONE,
993 QUIRK_ALIENWARE,
a57a46b9 994 QUIRK_ALIENWARE_M17XR4,
8a19bcee
CM		 995 QUIRK_SBZ,
996 QUIRK_R3DI,
d5c016b5
GM		 997};
998
fe14f39e
TI		 999static const struct hda_pintbl alienware_pincfgs[] = {
1000 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1001 { 0x0c, 0x411111f0 }, /* N/A */
1002 { 0x0d, 0x411111f0 }, /* N/A */
1003 { 0x0e, 0x411111f0 }, /* N/A */
1004 { 0x0f, 0x0321101f }, /* HP */
1005 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1006 { 0x11, 0x03a11021 }, /* Mic */
1007 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1008 { 0x13, 0x411111f0 }, /* N/A */
1009 { 0x18, 0x411111f0 }, /* N/A */
1010 {}
1011};
1012
63177afc
CM		 1013/* Sound Blaster Z pin configs taken from Windows Driver */
1014static const struct hda_pintbl sbz_pincfgs[] = {
1015 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1016 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1017 { 0x0d, 0x014510f0 }, /* Digital Out */
1018 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1019 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1020 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1021 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1022 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1023 { 0x13, 0x908700f0 }, /* What U Hear In*/
1024 { 0x18, 0x50d000f0 }, /* N/A */
1025 {}
1026};
1027
1028/* Recon3D integrated pin configs taken from Windows Driver */
1029static const struct hda_pintbl r3di_pincfgs[] = {
1030 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1031 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1032 { 0x0d, 0x014510f0 }, /* Digital Out */
1033 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1034 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1035 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1036 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1037 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1038 { 0x13, 0x908700f0 }, /* What U Hear In*/
1039 { 0x18, 0x500000f0 }, /* N/A */
1040 {}
1041};
1042
d5c016b5 1043static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1044 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1045 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1046 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1047 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1048 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1049 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1050 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1051 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1052 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
d5c016b5
GM		 1053 {}
1054};
1055
01ef7dbf
IM		 1056/*
1057 * CA0132 codec access
1058 */
399ae725 1059static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1060 unsigned int verb, unsigned int parm, unsigned int *res)
1061{
1062 unsigned int response;
1063 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1064 *res = response;
1065
1066 return ((response == -1) ? -1 : 0);
1067}
1068
1069static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1070 unsigned short converter_format, unsigned int *res)
1071{
1072 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1073 converter_format & 0xffff, res);
1074}
1075
1076static int codec_set_converter_stream_channel(struct hda_codec *codec,
1077 hda_nid_t nid, unsigned char stream,
1078 unsigned char channel, unsigned int *res)
1079{
1080 unsigned char converter_stream_channel = 0;
1081
1082 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1083 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1084 converter_stream_channel, res);
1085}
1086
1087/* Chip access helper function */
1088static int chipio_send(struct hda_codec *codec,
1089 unsigned int reg,
1090 unsigned int data)
1091{
1092 unsigned int res;
6d67530e 1093 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1094
1095 /* send bits of data specified by reg */
1096 do {
1097 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1098 reg, data);
1099 if (res == VENDOR_STATUS_CHIPIO_OK)
1100 return 0;
6d67530e
IM		 1101 msleep(20);
1102 } while (time_before(jiffies, timeout));
1103
01ef7dbf
IM		 1104 return -EIO;
1105}
1106
1107/*
1108 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1109 */
1110static int chipio_write_address(struct hda_codec *codec,
1111 unsigned int chip_addx)
1112{
4861af80 1113 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1114 int res;
1115
4861af80
IM		 1116 if (spec->curr_chip_addx == chip_addx)
1117 return 0;
1118
01ef7dbf
IM		 1119 /* send low 16 bits of the address */
1120 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1121 chip_addx & 0xffff);
1122
1123 if (res != -EIO) {
1124 /* send high 16 bits of the address */
1125 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1126 chip_addx >> 16);
1127 }
1128
d1600401 1129 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1130
4861af80 1131 return res;
01ef7dbf
IM		 1132}
1133
1134/*
1135 * Write data through the vendor widget -- NOT protected by the Mutex!
1136 */
01ef7dbf
IM		 1137static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1138{
5aaca44d 1139 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1140 int res;
1141
1142 /* send low 16 bits of the data */
1143 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1144
1145 if (res != -EIO) {
1146 /* send high 16 bits of the data */
1147 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1148 data >> 16);
1149 }
1150
5aaca44d
IM		 1151 /*If no error encountered, automatically increment the address
1152 as per chip behaviour*/
1153 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1154 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1155 return res;
1156}
1157
d5c21b88
IM		 1158/*
1159 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1160 */
01ef7dbf
IM		 1161static int chipio_write_data_multiple(struct hda_codec *codec,
1162 const u32 *data,
1163 unsigned int count)
1164{
1165 int status = 0;
1166
1167 if (data == NULL) {
4e76a883 1168 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1169 return -EINVAL;
1170 }
1171
1172 while ((count-- != 0) && (status == 0))
1173 status = chipio_write_data(codec, *data++);
1174
1175 return status;
1176}
1177
1178
1179/*
1180 * Read data through the vendor widget -- NOT protected by the Mutex!
1181 */
1182static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1183{
5aaca44d 1184 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1185 int res;
1186
1187 /* post read */
1188 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1189
1190 if (res != -EIO) {
1191 /* read status */
1192 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1193 }
1194
1195 if (res != -EIO) {
1196 /* read data */
1197 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1198 VENDOR_CHIPIO_HIC_READ_DATA,
1199 0);
1200 }
1201
5aaca44d
IM		 1202 /*If no error encountered, automatically increment the address
1203 as per chip behaviour*/
1204 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1205 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1206 return res;
1207}
1208
1209/*
1210 * Write given value to the given address through the chip I/O widget.
1211 * protected by the Mutex
1212 */
1213static int chipio_write(struct hda_codec *codec,
1214 unsigned int chip_addx, const unsigned int data)
1215{
1216 struct ca0132_spec *spec = codec->spec;
1217 int err;
1218
1219 mutex_lock(&spec->chipio_mutex);
1220
1221 /* write the address, and if successful proceed to write data */
1222 err = chipio_write_address(codec, chip_addx);
1223 if (err < 0)
1224 goto exit;
1225
1226 err = chipio_write_data(codec, data);
1227 if (err < 0)
1228 goto exit;
1229
1230exit:
1231 mutex_unlock(&spec->chipio_mutex);
1232 return err;
1233}
1234
38ba69ff
CM		 1235/*
1236 * Write given value to the given address through the chip I/O widget.
1237 * not protected by the Mutex
1238 */
1239static int chipio_write_no_mutex(struct hda_codec *codec,
1240 unsigned int chip_addx, const unsigned int data)
1241{
1242 int err;
1243
1244
1245 /* write the address, and if successful proceed to write data */
1246 err = chipio_write_address(codec, chip_addx);
1247 if (err < 0)
1248 goto exit;
1249
1250 err = chipio_write_data(codec, data);
1251 if (err < 0)
1252 goto exit;
1253
1254exit:
1255 return err;
1256}
1257
d5c21b88
IM		 1258/*
1259 * Write multiple values to the given address through the chip I/O widget.
1260 * protected by the Mutex
1261 */
01ef7dbf
IM		 1262static int chipio_write_multiple(struct hda_codec *codec,
1263 u32 chip_addx,
1264 const u32 *data,
1265 unsigned int count)
1266{
1267 struct ca0132_spec *spec = codec->spec;
1268 int status;
1269
1270 mutex_lock(&spec->chipio_mutex);
4861af80 1271 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1272 if (status < 0)
1273 goto error;
1274
1275 status = chipio_write_data_multiple(codec, data, count);
1276error:
1277 mutex_unlock(&spec->chipio_mutex);
1278
1279 return status;
1280}
1281
1282/*
1283 * Read the given address through the chip I/O widget
1284 * protected by the Mutex
1285 */
1286static int chipio_read(struct hda_codec *codec,
1287 unsigned int chip_addx, unsigned int *data)
1288{
1289 struct ca0132_spec *spec = codec->spec;
1290 int err;
1291
1292 mutex_lock(&spec->chipio_mutex);
1293
1294 /* write the address, and if successful proceed to write data */
1295 err = chipio_write_address(codec, chip_addx);
1296 if (err < 0)
1297 goto exit;
1298
1299 err = chipio_read_data(codec, data);
1300 if (err < 0)
1301 goto exit;
1302
1303exit:
1304 mutex_unlock(&spec->chipio_mutex);
1305 return err;
1306}
1307
d5c21b88
IM		 1308/*
1309 * Set chip control flags through the chip I/O widget.
1310 */
01ef7dbf
IM		 1311static void chipio_set_control_flag(struct hda_codec *codec,
1312 enum control_flag_id flag_id,
1313 bool flag_state)
1314{
1315 unsigned int val;
1316 unsigned int flag_bit;
1317
1318 flag_bit = (flag_state ? 1 : 0);
1319 val = (flag_bit << 7) | (flag_id);
1320 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1321 VENDOR_CHIPIO_FLAG_SET, val);
1322}
1323
d5c21b88
IM		 1324/*
1325 * Set chip parameters through the chip I/O widget.
1326 */
01ef7dbf
IM		 1327static void chipio_set_control_param(struct hda_codec *codec,
1328 enum control_param_id param_id, int param_val)
1329{
1330 struct ca0132_spec *spec = codec->spec;
1331 int val;
1332
1333 if ((param_id < 32) && (param_val < 8)) {
1334 val = (param_val << 5) | (param_id);
1335 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1336 VENDOR_CHIPIO_PARAM_SET, val);
1337 } else {
1338 mutex_lock(&spec->chipio_mutex);
1339 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1340 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1341 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1342 param_id);
1343 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1344 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1345 param_val);
1346 }
1347 mutex_unlock(&spec->chipio_mutex);
1348 }
1349}
1350
009b8f97
CM		 1351/*
1352 * Set chip parameters through the chip I/O widget. NO MUTEX.
1353 */
1354static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1355 enum control_param_id param_id, int param_val)
1356{
1357 int val;
1358
1359 if ((param_id < 32) && (param_val < 8)) {
1360 val = (param_val << 5) | (param_id);
1361 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1362 VENDOR_CHIPIO_PARAM_SET, val);
1363 } else {
1364 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1365 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1366 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1367 param_id);
1368 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1369 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1370 param_val);
1371 }
1372 }
1373}
38ba69ff
CM		 1374/*
1375 * Connect stream to a source point, and then connect
1376 * that source point to a destination point.
1377 */
1378static void chipio_set_stream_source_dest(struct hda_codec *codec,
1379 int streamid, int source_point, int dest_point)
1380{
1381 chipio_set_control_param_no_mutex(codec,
1382 CONTROL_PARAM_STREAM_ID, streamid);
1383 chipio_set_control_param_no_mutex(codec,
1384 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1385 chipio_set_control_param_no_mutex(codec,
1386 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1387}
1388
1389/*
1390 * Set number of channels in the selected stream.
1391 */
1392static void chipio_set_stream_channels(struct hda_codec *codec,
1393 int streamid, unsigned int channels)
1394{
1395 chipio_set_control_param_no_mutex(codec,
1396 CONTROL_PARAM_STREAM_ID, streamid);
1397 chipio_set_control_param_no_mutex(codec,
1398 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1399}
009b8f97
CM		 1400
1401/*
1402 * Enable/Disable audio stream.
1403 */
1404static void chipio_set_stream_control(struct hda_codec *codec,
1405 int streamid, int enable)
1406{
1407 chipio_set_control_param_no_mutex(codec,
1408 CONTROL_PARAM_STREAM_ID, streamid);
1409 chipio_set_control_param_no_mutex(codec,
1410 CONTROL_PARAM_STREAM_CONTROL, enable);
1411}
1412
38ba69ff
CM		 1413
1414/*
1415 * Set sampling rate of the connection point. NO MUTEX.
1416 */
1417static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1418 int connid, enum ca0132_sample_rate rate)
1419{
1420 chipio_set_control_param_no_mutex(codec,
1421 CONTROL_PARAM_CONN_POINT_ID, connid);
1422 chipio_set_control_param_no_mutex(codec,
1423 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1424}
1425
d5c21b88
IM		 1426/*
1427 * Set sampling rate of the connection point.
1428 */
01ef7dbf
IM		 1429static void chipio_set_conn_rate(struct hda_codec *codec,
1430 int connid, enum ca0132_sample_rate rate)
1431{
1432 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1433 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1434 rate);
1435}
1436
d5c21b88
IM		 1437/*
1438 * Enable clocks.
1439 */
01ef7dbf
IM		 1440static void chipio_enable_clocks(struct hda_codec *codec)
1441{
1442 struct ca0132_spec *spec = codec->spec;
1443
1444 mutex_lock(&spec->chipio_mutex);
1445 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1446 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1447 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1448 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1449 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1450 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1451 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1452 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1453 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1454 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1455 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1456 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1457 mutex_unlock(&spec->chipio_mutex);
1458}
1459
1460/*
1461 * CA0132 DSP IO stuffs
1462 */
1463static int dspio_send(struct hda_codec *codec, unsigned int reg,
1464 unsigned int data)
1465{
b645d796 1466 int res;
6d67530e 1467 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1468
1469 /* send bits of data specified by reg to dsp */
1470 do {
1471 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1472 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1473 return res;
6d67530e
IM		 1474 msleep(20);
1475 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1476
1477 return -EIO;
1478}
1479
d5c21b88
IM		 1480/*
1481 * Wait for DSP to be ready for commands
1482 */
01ef7dbf
IM		 1483static void dspio_write_wait(struct hda_codec *codec)
1484{
4861af80
IM		 1485 int status;
1486 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1487
01ef7dbf 1488 do {
4861af80
IM		 1489 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1490 VENDOR_DSPIO_STATUS, 0);
1491 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1492 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1493 break;
1494 msleep(1);
1495 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1496}
1497
d5c21b88
IM		 1498/*
1499 * Write SCP data to DSP
1500 */
01ef7dbf
IM		 1501static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1502{
1503 struct ca0132_spec *spec = codec->spec;
1504 int status;
1505
1506 dspio_write_wait(codec);
1507
1508 mutex_lock(&spec->chipio_mutex);
1509 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1510 scp_data & 0xffff);
1511 if (status < 0)
1512 goto error;
1513
1514 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1515 scp_data >> 16);
1516 if (status < 0)
1517 goto error;
1518
1519 /* OK, now check if the write itself has executed*/
1520 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1521 VENDOR_DSPIO_STATUS, 0);
1522error:
1523 mutex_unlock(&spec->chipio_mutex);
1524
1525 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1526 -EIO : 0;
1527}
1528
d5c21b88
IM		 1529/*
1530 * Write multiple SCP data to DSP
1531 */
01ef7dbf
IM		 1532static int dspio_write_multiple(struct hda_codec *codec,
1533 unsigned int *buffer, unsigned int size)
1534{
1535 int status = 0;
1536 unsigned int count;
1537
a16fbb85 1538 if (buffer == NULL)
01ef7dbf
IM		 1539 return -EINVAL;
1540
1541 count = 0;
1542 while (count < size) {
1543 status = dspio_write(codec, *buffer++);
1544 if (status != 0)
1545 break;
1546 count++;
1547 }
1548
1549 return status;
1550}
1551
a73d511c
IM		 1552static int dspio_read(struct hda_codec *codec, unsigned int *data)
1553{
1554 int status;
1555
1556 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1557 if (status == -EIO)
1558 return status;
1559
1560 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1561 if (status == -EIO ||
1562 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1563 return -EIO;
1564
1565 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1566 VENDOR_DSPIO_SCP_READ_DATA, 0);
1567
1568 return 0;
1569}
1570
1571static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1572 unsigned int *buf_size, unsigned int size_count)
1573{
1574 int status = 0;
1575 unsigned int size = *buf_size;
1576 unsigned int count;
1577 unsigned int skip_count;
1578 unsigned int dummy;
1579
a16fbb85 1580 if (buffer == NULL)
a73d511c
IM		 1581 return -1;
1582
1583 count = 0;
1584 while (count < size && count < size_count) {
1585 status = dspio_read(codec, buffer++);
1586 if (status != 0)
1587 break;
1588 count++;
1589 }
1590
1591 skip_count = count;
1592 if (status == 0) {
1593 while (skip_count < size) {
1594 status = dspio_read(codec, &dummy);
1595 if (status != 0)
1596 break;
1597 skip_count++;
1598 }
1599 }
1600 *buf_size = count;
1601
1602 return status;
1603}
1604
d5c21b88
IM		 1605/*
1606 * Construct the SCP header using corresponding fields
1607 */
01ef7dbf
IM		 1608static inline unsigned int
1609make_scp_header(unsigned int target_id, unsigned int source_id,
1610 unsigned int get_flag, unsigned int req,
1611 unsigned int device_flag, unsigned int resp_flag,
1612 unsigned int error_flag, unsigned int data_size)
1613{
1614 unsigned int header = 0;
1615
1616 header = (data_size & 0x1f) << 27;
1617 header |= (error_flag & 0x01) << 26;
1618 header |= (resp_flag & 0x01) << 25;
1619 header |= (device_flag & 0x01) << 24;
1620 header |= (req & 0x7f) << 17;
1621 header |= (get_flag & 0x01) << 16;
1622 header |= (source_id & 0xff) << 8;
1623 header |= target_id & 0xff;
1624
1625 return header;
1626}
1627
d5c21b88
IM		 1628/*
1629 * Extract corresponding fields from SCP header
1630 */
01ef7dbf
IM		 1631static inline void
1632extract_scp_header(unsigned int header,
1633 unsigned int *target_id, unsigned int *source_id,
1634 unsigned int *get_flag, unsigned int *req,
1635 unsigned int *device_flag, unsigned int *resp_flag,
1636 unsigned int *error_flag, unsigned int *data_size)
1637{
1638 if (data_size)
1639 *data_size = (header >> 27) & 0x1f;
1640 if (error_flag)
1641 *error_flag = (header >> 26) & 0x01;
1642 if (resp_flag)
1643 *resp_flag = (header >> 25) & 0x01;
1644 if (device_flag)
1645 *device_flag = (header >> 24) & 0x01;
1646 if (req)
1647 *req = (header >> 17) & 0x7f;
1648 if (get_flag)
1649 *get_flag = (header >> 16) & 0x01;
1650 if (source_id)
1651 *source_id = (header >> 8) & 0xff;
1652 if (target_id)
1653 *target_id = header & 0xff;
1654}
1655
1656#define SCP_MAX_DATA_WORDS (16)
1657
1658/* Structure to contain any SCP message */
1659struct scp_msg {
1660 unsigned int hdr;
1661 unsigned int data[SCP_MAX_DATA_WORDS];
1662};
1663
a73d511c
IM		 1664static void dspio_clear_response_queue(struct hda_codec *codec)
1665{
1666 unsigned int dummy = 0;
1667 int status = -1;
1668
1669 /* clear all from the response queue */
1670 do {
1671 status = dspio_read(codec, &dummy);
1672 } while (status == 0);
1673}
1674
1675static int dspio_get_response_data(struct hda_codec *codec)
1676{
1677 struct ca0132_spec *spec = codec->spec;
1678 unsigned int data = 0;
1679 unsigned int count;
1680
1681 if (dspio_read(codec, &data) < 0)
1682 return -EIO;
1683
1684 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1685 spec->scp_resp_header = data;
1686 spec->scp_resp_count = data >> 27;
1687 count = spec->wait_num_data;
1688 dspio_read_multiple(codec, spec->scp_resp_data,
1689 &spec->scp_resp_count, count);
1690 return 0;
1691 }
1692
1693 return -EIO;
1694}
1695
d5c21b88
IM		 1696/*
1697 * Send SCP message to DSP
1698 */
01ef7dbf
IM		 1699static int dspio_send_scp_message(struct hda_codec *codec,
1700 unsigned char *send_buf,
1701 unsigned int send_buf_size,
1702 unsigned char *return_buf,
1703 unsigned int return_buf_size,
1704 unsigned int *bytes_returned)
1705{
1706 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1707 int status = -1;
1708 unsigned int scp_send_size = 0;
1709 unsigned int total_size;
1710 bool waiting_for_resp = false;
1711 unsigned int header;
1712 struct scp_msg *ret_msg;
1713 unsigned int resp_src_id, resp_target_id;
1714 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1715
1716 if (bytes_returned)
1717 *bytes_returned = 0;
1718
1719 /* get scp header from buffer */
1720 header = *((unsigned int *)send_buf);
1721 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1722 &device_flag, NULL, NULL, &data_size);
1723 scp_send_size = data_size + 1;
1724 total_size = (scp_send_size * 4);
1725
1726 if (send_buf_size < total_size)
1727 return -EINVAL;
1728
1729 if (get_flag || device_flag) {
1730 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1731 return -EINVAL;
1732
1733 spec->wait_scp_header = *((unsigned int *)send_buf);
1734
1735 /* swap source id with target id */
1736 resp_target_id = src_id;
1737 resp_src_id = target_id;
1738 spec->wait_scp_header &= 0xffff0000;
1739 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1740 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1741 spec->wait_scp = 1;
1742 waiting_for_resp = true;
1743 }
1744
1745 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1746 scp_send_size);
1747 if (status < 0) {
1748 spec->wait_scp = 0;
1749 return status;
1750 }
1751
1752 if (waiting_for_resp) {
6d67530e 1753 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1754 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1755 do {
1756 msleep(20);
6d67530e 1757 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1758 waiting_for_resp = false;
6d67530e 1759 if (!spec->wait_scp) {
01ef7dbf
IM		 1760 ret_msg = (struct scp_msg *)return_buf;
1761 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1762 memcpy(&ret_msg->data, spec->scp_resp_data,
1763 spec->wait_num_data);
1764 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1765 status = 0;
1766 } else {
1767 status = -EIO;
1768 }
1769 spec->wait_scp = 0;
1770 }
1771
1772 return status;
1773}
1774
d5c21b88
IM		 1775/**
1776 * Prepare and send the SCP message to DSP
1777 * @codec: the HDA codec
1778 * @mod_id: ID of the DSP module to send the command
1779 * @req: ID of request to send to the DSP module
1780 * @dir: SET or GET
1781 * @data: pointer to the data to send with the request, request specific
1782 * @len: length of the data, in bytes
1783 * @reply: point to the buffer to hold data returned for a reply
1784 * @reply_len: length of the reply buffer returned from GET
1785 *
1786 * Returns zero or a negative error code.
1787 */
01ef7dbf 1788static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1789 int mod_id, int src_id, int req, int dir, const void *data,
1790 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1791{
1792 int status = 0;
1793 struct scp_msg scp_send, scp_reply;
1794 unsigned int ret_bytes, send_size, ret_size;
1795 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1796 unsigned int reply_data_size;
1797
1798 memset(&scp_send, 0, sizeof(scp_send));
1799 memset(&scp_reply, 0, sizeof(scp_reply));
1800
1801 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1802 return -EINVAL;
1803
1804 if (dir == SCP_GET && reply == NULL) {
4e76a883 1805 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1806 return -EINVAL;
1807 }
1808
1809 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1810 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1811 return -EINVAL;
1812 }
1813
447fd8e9 1814 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1815 0, 0, 0, len/sizeof(unsigned int));
1816 if (data != NULL && len > 0) {
1817 len = min((unsigned int)(sizeof(scp_send.data)), len);
1818 memcpy(scp_send.data, data, len);
1819 }
1820
1821 ret_bytes = 0;
1822 send_size = sizeof(unsigned int) + len;
1823 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1824 send_size, (unsigned char *)&scp_reply,
1825 sizeof(scp_reply), &ret_bytes);
1826
1827 if (status < 0) {
4e76a883 1828 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1829 return status;
1830 }
1831
1832 /* extract send and reply headers members */
1833 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1834 NULL, NULL, NULL, NULL, NULL);
1835 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1836 &reply_resp_flag, &reply_error_flag,
1837 &reply_data_size);
1838
1839 if (!send_get_flag)
1840 return 0;
1841
1842 if (reply_resp_flag && !reply_error_flag) {
1843 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1844 / sizeof(unsigned int);
1845
1846 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1847 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1848 return -EINVAL;
1849 } else if (ret_size != reply_data_size) {
4e76a883 1850 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1851 return -EINVAL;
46a049da
AB		 1852 } else if (!reply) {
1853 codec_dbg(codec, "NULL reply\n");
1854 return -EINVAL;
01ef7dbf
IM		 1855 } else {
1856 *reply_len = ret_size*sizeof(unsigned int);
1857 memcpy(reply, scp_reply.data, *reply_len);
1858 }
1859 } else {
4e76a883 1860 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1861 return -EIO;
1862 }
1863
1864 return status;
1865}
1866
5aaca44d
IM		 1867/*
1868 * Set DSP parameters
1869 */
1870static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 1871 int src_id, int req, const void *data, unsigned int len)
5aaca44d 1872{
447fd8e9
CM		 1873 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1874 NULL);
5aaca44d
IM		 1875}
1876
1877static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 1878 int req, const unsigned int data)
5aaca44d 1879{
447fd8e9
CM		 1880 return dspio_set_param(codec, mod_id, 0x20, req, &data,
1881 sizeof(unsigned int));
1882}
1883
1884static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1885 int req, const unsigned int data)
1886{
1887 return dspio_set_param(codec, mod_id, 0x00, req, &data,
1888 sizeof(unsigned int));
5aaca44d
IM		 1889}
1890
d5c21b88
IM		 1891/*
1892 * Allocate a DSP DMA channel via an SCP message
1893 */
01ef7dbf
IM		 1894static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1895{
1896 int status = 0;
1897 unsigned int size = sizeof(dma_chan);
1898
4e76a883 1899 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 1900 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1901 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1902 dma_chan, &size);
01ef7dbf
IM		 1903
1904 if (status < 0) {
4e76a883 1905 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1906 return status;
1907 }
1908
1909 if ((*dma_chan + 1) == 0) {
4e76a883 1910 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1911 return -EBUSY;
1912 }
1913
4e76a883
TI		 1914 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1915 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1916
1917 return status;
1918}
1919
d5c21b88
IM		 1920/*
1921 * Free a DSP DMA via an SCP message
1922 */
01ef7dbf
IM		 1923static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1924{
1925 int status = 0;
1926 unsigned int dummy = 0;
1927
4e76a883
TI		 1928 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1929 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 1930
447fd8e9
CM		 1931 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1932 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1933 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 1934
1935 if (status < 0) {
4e76a883 1936 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1937 return status;
1938 }
1939
4e76a883 1940 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1941
1942 return status;
1943}
1944
1945/*
d5c21b88 1946 * (Re)start the DSP
01ef7dbf
IM		 1947 */
1948static int dsp_set_run_state(struct hda_codec *codec)
1949{
1950 unsigned int dbg_ctrl_reg;
1951 unsigned int halt_state;
1952 int err;
1953
1954 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1955 if (err < 0)
1956 return err;
1957
1958 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1959 DSP_DBGCNTL_STATE_LOBIT;
1960
1961 if (halt_state != 0) {
1962 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1963 DSP_DBGCNTL_SS_MASK);
1964 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1965 dbg_ctrl_reg);
1966 if (err < 0)
1967 return err;
1968
1969 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1970 DSP_DBGCNTL_EXEC_MASK;
1971 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1972 dbg_ctrl_reg);
1973 if (err < 0)
1974 return err;
1975 }
1976
1977 return 0;
1978}
1979
d5c21b88
IM		 1980/*
1981 * Reset the DSP
1982 */
01ef7dbf
IM		 1983static int dsp_reset(struct hda_codec *codec)
1984{
1985 unsigned int res;
1986 int retry = 20;
1987
4e76a883 1988 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1989 do {
1990 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1991 retry--;
1992 } while (res == -EIO && retry);
1993
1994 if (!retry) {
4e76a883 1995 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1996 return -EIO;
1997 }
1998
1999 return 0;
2000}
2001
d5c21b88
IM		 2002/*
2003 * Convert chip address to DSP address
2004 */
01ef7dbf
IM		 2005static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2006 bool *code, bool *yram)
2007{
2008 *code = *yram = false;
2009
2010 if (UC_RANGE(chip_addx, 1)) {
2011 *code = true;
2012 return UC_OFF(chip_addx);
2013 } else if (X_RANGE_ALL(chip_addx, 1)) {
2014 return X_OFF(chip_addx);
2015 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2016 *yram = true;
2017 return Y_OFF(chip_addx);
2018 }
2019
4a8b89f9 2020 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2021}
2022
d5c21b88
IM		 2023/*
2024 * Check if the DSP DMA is active
2025 */
01ef7dbf
IM		 2026static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2027{
2028 unsigned int dma_chnlstart_reg;
2029
2030 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2031
2032 return ((dma_chnlstart_reg & (1 <<
2033 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2034}
2035
2036static int dsp_dma_setup_common(struct hda_codec *codec,
2037 unsigned int chip_addx,
2038 unsigned int dma_chan,
2039 unsigned int port_map_mask,
2040 bool ovly)
2041{
2042 int status = 0;
2043 unsigned int chnl_prop;
2044 unsigned int dsp_addx;
2045 unsigned int active;
2046 bool code, yram;
2047
4e76a883 2048 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2049
2050 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2051 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2052 return -EINVAL;
2053 }
2054
2055 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2056 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2057 return -EBUSY;
2058 }
2059
2060 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2061
2062 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2063 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2064 return -ENXIO;
2065 }
2066
2067 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2068 active = 0;
2069
4e76a883 2070 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2071
2072 if (ovly) {
2073 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2074 &chnl_prop);
2075
2076 if (status < 0) {
4e76a883 2077 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2078 return status;
2079 }
4e76a883 2080 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2081 }
2082
2083 if (!code)
2084 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2085 else
2086 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2087
2088 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2089
2090 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2091 if (status < 0) {
4e76a883 2092 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2093 return status;
2094 }
4e76a883 2095 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2096
2097 if (ovly) {
2098 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2099 &active);
2100
2101 if (status < 0) {
4e76a883 2102 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2103 return status;
2104 }
4e76a883 2105 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2106 }
2107
2108 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2109 DSPDMAC_ACTIVE_AAR_MASK;
2110
2111 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2112 if (status < 0) {
4e76a883 2113 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2114 return status;
2115 }
2116
4e76a883 2117 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2118
2119 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2120 port_map_mask);
2121 if (status < 0) {
4e76a883 2122 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2123 return status;
2124 }
4e76a883 2125 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2126
2127 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2128 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2129 if (status < 0) {
4e76a883 2130 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2131 return status;
2132 }
4e76a883 2133 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2134
4e76a883 2135 codec_dbg(codec,
01ef7dbf
IM		 2136 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2137 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2138 chip_addx, dsp_addx, dma_chan,
2139 port_map_mask, chnl_prop, active);
2140
4e76a883 2141 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2142
2143 return 0;
2144}
2145
d5c21b88
IM		 2146/*
2147 * Setup the DSP DMA per-transfer-specific registers
2148 */
01ef7dbf
IM		 2149static int dsp_dma_setup(struct hda_codec *codec,
2150 unsigned int chip_addx,
2151 unsigned int count,
2152 unsigned int dma_chan)
2153{
2154 int status = 0;
2155 bool code, yram;
2156 unsigned int dsp_addx;
2157 unsigned int addr_field;
2158 unsigned int incr_field;
2159 unsigned int base_cnt;
2160 unsigned int cur_cnt;
2161 unsigned int dma_cfg = 0;
2162 unsigned int adr_ofs = 0;
2163 unsigned int xfr_cnt = 0;
2164 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2165 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2166
4e76a883 2167 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2168
2169 if (count > max_dma_count) {
4e76a883 2170 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2171 return -EINVAL;
2172 }
2173
2174 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2175 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2176 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2177 return -ENXIO;
2178 }
2179
4e76a883 2180 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2181
2182 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2183 incr_field = 0;
2184
2185 if (!code) {
2186 addr_field <<= 1;
2187 if (yram)
2188 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2189
2190 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2191 }
2192
2193 dma_cfg = addr_field + incr_field;
2194 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2195 dma_cfg);
2196 if (status < 0) {
4e76a883 2197 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2198 return status;
2199 }
4e76a883 2200 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2201
2202 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2203 (code ? 0 : 1));
2204
2205 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2206 adr_ofs);
2207 if (status < 0) {
4e76a883 2208 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2209 return status;
2210 }
4e76a883 2211 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2212
2213 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2214
2215 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2216
2217 xfr_cnt = base_cnt | cur_cnt;
2218
2219 status = chipio_write(codec,
2220 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2221 if (status < 0) {
4e76a883 2222 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2223 return status;
2224 }
4e76a883 2225 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2226
4e76a883 2227 codec_dbg(codec,
01ef7dbf
IM		 2228 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2229 "ADROFS=0x%x, XFRCNT=0x%x\n",
2230 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2231
4e76a883 2232 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2233
2234 return 0;
2235}
2236
d5c21b88
IM		 2237/*
2238 * Start the DSP DMA
2239 */
01ef7dbf
IM		 2240static int dsp_dma_start(struct hda_codec *codec,
2241 unsigned int dma_chan, bool ovly)
2242{
2243 unsigned int reg = 0;
2244 int status = 0;
2245
4e76a883 2246 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2247
2248 if (ovly) {
2249 status = chipio_read(codec,
2250 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2251
2252 if (status < 0) {
4e76a883 2253 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2254 return status;
2255 }
4e76a883 2256 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2257
2258 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2259 DSPDMAC_CHNLSTART_DIS_MASK);
2260 }
2261
2262 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2263 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2264 if (status < 0) {
4e76a883 2265 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2266 return status;
2267 }
4e76a883 2268 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2269
2270 return status;
2271}
2272
d5c21b88
IM		 2273/*
2274 * Stop the DSP DMA
2275 */
01ef7dbf
IM		 2276static int dsp_dma_stop(struct hda_codec *codec,
2277 unsigned int dma_chan, bool ovly)
2278{
2279 unsigned int reg = 0;
2280 int status = 0;
2281
4e76a883 2282 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2283
2284 if (ovly) {
2285 status = chipio_read(codec,
2286 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2287
2288 if (status < 0) {
4e76a883 2289 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2290 return status;
2291 }
4e76a883 2292 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2293 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2294 DSPDMAC_CHNLSTART_DIS_MASK);
2295 }
2296
2297 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2298 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2299 if (status < 0) {
4e76a883 2300 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2301 return status;
2302 }
4e76a883 2303 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2304
2305 return status;
2306}
2307
d5c21b88
IM		 2308/**
2309 * Allocate router ports
2310 *
2311 * @codec: the HDA codec
2312 * @num_chans: number of channels in the stream
2313 * @ports_per_channel: number of ports per channel
2314 * @start_device: start device
2315 * @port_map: pointer to the port list to hold the allocated ports
2316 *
2317 * Returns zero or a negative error code.
2318 */
01ef7dbf
IM		 2319static int dsp_allocate_router_ports(struct hda_codec *codec,
2320 unsigned int num_chans,
2321 unsigned int ports_per_channel,
2322 unsigned int start_device,
2323 unsigned int *port_map)
2324{
2325 int status = 0;
2326 int res;
2327 u8 val;
2328
2329 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2330 if (status < 0)
2331 return status;
2332
2333 val = start_device << 6;
2334 val |= (ports_per_channel - 1) << 4;
2335 val |= num_chans - 1;
2336
2337 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2338 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2339 val);
2340
2341 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2342 VENDOR_CHIPIO_PORT_ALLOC_SET,
2343 MEM_CONNID_DSP);
2344
2345 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2346 if (status < 0)
2347 return status;
2348
2349 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2350 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2351
2352 *port_map = res;
2353
2354 return (res < 0) ? res : 0;
2355}
2356
d5c21b88
IM		 2357/*
2358 * Free router ports
2359 */
01ef7dbf
IM		 2360static int dsp_free_router_ports(struct hda_codec *codec)
2361{
2362 int status = 0;
2363
2364 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2365 if (status < 0)
2366 return status;
2367
2368 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2369 VENDOR_CHIPIO_PORT_FREE_SET,
2370 MEM_CONNID_DSP);
2371
2372 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2373
2374 return status;
2375}
2376
d5c21b88
IM		 2377/*
2378 * Allocate DSP ports for the download stream
2379 */
01ef7dbf
IM		 2380static int dsp_allocate_ports(struct hda_codec *codec,
2381 unsigned int num_chans,
2382 unsigned int rate_multi, unsigned int *port_map)
2383{
2384 int status;
2385
4e76a883 2386 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2387
2388 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2389 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2390 return -EINVAL;
2391 }
2392
2393 status = dsp_allocate_router_ports(codec, num_chans,
2394 rate_multi, 0, port_map);
2395
4e76a883 2396 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2397
2398 return status;
2399}
2400
01ef7dbf
IM		 2401static int dsp_allocate_ports_format(struct hda_codec *codec,
2402 const unsigned short fmt,
2403 unsigned int *port_map)
2404{
2405 int status;
2406 unsigned int num_chans;
2407
2408 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2409 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2410 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2411
2412 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2413 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2414 return -EINVAL;
2415 }
2416
2417 num_chans = get_hdafmt_chs(fmt) + 1;
2418
2419 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2420
2421 return status;
2422}
2423
d5c21b88
IM		 2424/*
2425 * free DSP ports
2426 */
2427static int dsp_free_ports(struct hda_codec *codec)
2428{
2429 int status;
2430
4e76a883 2431 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2432
2433 status = dsp_free_router_ports(codec);
2434 if (status < 0) {
4e76a883 2435 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2436 return status;
2437 }
4e76a883 2438 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2439
2440 return status;
2441}
2442
01ef7dbf
IM		 2443/*
2444 * HDA DMA engine stuffs for DSP code download
2445 */
2446struct dma_engine {
2447 struct hda_codec *codec;
2448 unsigned short m_converter_format;
2449 struct snd_dma_buffer *dmab;
2450 unsigned int buf_size;
2451};
2452
2453
2454enum dma_state {
2455 DMA_STATE_STOP = 0,
2456 DMA_STATE_RUN = 1
2457};
2458
6194b99d 2459static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2460 unsigned int sample_rate,
2461 unsigned short channels,
01ef7dbf
IM		 2462 unsigned short *hda_format)
2463{
2464 unsigned int format_val;
2465
b7d023e1
TI		 2466 format_val = snd_hdac_calc_stream_format(sample_rate,
2467 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2468
2469 if (hda_format)
2470 *hda_format = (unsigned short)format_val;
2471
2472 return 0;
2473}
2474
d5c21b88
IM		 2475/*
2476 * Reset DMA for DSP download
2477 */
01ef7dbf
IM		 2478static int dma_reset(struct dma_engine *dma)
2479{
2480 struct hda_codec *codec = dma->codec;
2481 struct ca0132_spec *spec = codec->spec;
2482 int status;
2483
b3667bd7 2484 if (dma->dmab->area)
01ef7dbf
IM		 2485 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2486
2487 status = snd_hda_codec_load_dsp_prepare(codec,
2488 dma->m_converter_format,
2489 dma->buf_size,
2490 dma->dmab);
2491 if (status < 0)
2492 return status;
2493 spec->dsp_stream_id = status;
2494 return 0;
2495}
2496
2497static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2498{
01ef7dbf
IM		 2499 bool cmd;
2500
01ef7dbf
IM		 2501 switch (state) {
2502 case DMA_STATE_STOP:
2503 cmd = false;
2504 break;
2505 case DMA_STATE_RUN:
2506 cmd = true;
2507 break;
2508 default:
c41999a2
DH		 2509 return 0;
2510 }
01ef7dbf
IM		 2511
2512 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2513 return 0;
95c6e9cb
IM		 2514}
2515
01ef7dbf
IM		 2516static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2517{
2518 return dma->dmab->bytes;
2519}
95c6e9cb 2520
01ef7dbf
IM		 2521static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2522{
2523 return dma->dmab->area;
2524}
95c6e9cb 2525
01ef7dbf
IM		 2526static int dma_xfer(struct dma_engine *dma,
2527 const unsigned int *data,
2528 unsigned int count)
2529{
2530 memcpy(dma->dmab->area, data, count);
2531 return 0;
2532}
95c6e9cb 2533
01ef7dbf
IM		 2534static void dma_get_converter_format(
2535 struct dma_engine *dma,
2536 unsigned short *format)
2537{
2538 if (format)
2539 *format = dma->m_converter_format;
2540}
95c6e9cb 2541
01ef7dbf 2542static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2543{
01ef7dbf 2544 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2545
01ef7dbf 2546 return spec->dsp_stream_id;
95c6e9cb
IM		 2547}
2548
01ef7dbf
IM		 2549struct dsp_image_seg {
2550 u32 magic;
2551 u32 chip_addr;
2552 u32 count;
2553 u32 data[0];
2554};
2555
2556static const u32 g_magic_value = 0x4c46584d;
2557static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2558
2559static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2560{
01ef7dbf
IM		 2561 return p->magic == g_magic_value;
2562}
95c6e9cb 2563
01ef7dbf
IM		 2564static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2565{
2566 return g_chip_addr_magic_value == p->chip_addr;
2567}
95c6e9cb 2568
01ef7dbf
IM		 2569static bool is_last(const struct dsp_image_seg *p)
2570{
2571 return p->count == 0;
2572}
95c6e9cb 2573
01ef7dbf
IM		 2574static size_t dsp_sizeof(const struct dsp_image_seg *p)
2575{
2576 return sizeof(*p) + p->count*sizeof(u32);
2577}
2578
2579static const struct dsp_image_seg *get_next_seg_ptr(
2580 const struct dsp_image_seg *p)
2581{
2582 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2583}
2584
2585/*
01ef7dbf 2586 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2587 */
8ae3124b 2588#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2589
d5c21b88
IM		 2590/*
2591 * Program a list of address/data pairs via the ChipIO widget.
2592 * The segment data is in the format of successive pairs of words.
2593 * These are repeated as indicated by the segment's count field.
2594 */
01ef7dbf
IM		 2595static int dspxfr_hci_write(struct hda_codec *codec,
2596 const struct dsp_image_seg *fls)
95c6e9cb 2597{
01ef7dbf
IM		 2598 int status;
2599 const u32 *data;
2600 unsigned int count;
95c6e9cb 2601
01ef7dbf 2602 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2603 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2604 return -EINVAL;
95c6e9cb
IM		 2605 }
2606
01ef7dbf
IM		 2607 count = fls->count;
2608 data = (u32 *)(fls->data);
2609 while (count >= 2) {
2610 status = chipio_write(codec, data[0], data[1]);
2611 if (status < 0) {
4e76a883 2612 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2613 return status;
2614 }
2615 count -= 2;
2616 data += 2;
2617 }
2618 return 0;
95c6e9cb
IM		 2619}
2620
d5c21b88
IM		 2621/**
2622 * Write a block of data into DSP code or data RAM using pre-allocated
2623 * DMA engine.
2624 *
2625 * @codec: the HDA codec
2626 * @fls: pointer to a fast load image
2627 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2628 * no relocation
2629 * @dma_engine: pointer to DMA engine to be used for DSP download
2630 * @dma_chan: The number of DMA channels used for DSP download
2631 * @port_map_mask: port mapping
2632 * @ovly: TRUE if overlay format is required
2633 *
2634 * Returns zero or a negative error code.
2635 */
01ef7dbf
IM		 2636static int dspxfr_one_seg(struct hda_codec *codec,
2637 const struct dsp_image_seg *fls,
2638 unsigned int reloc,
2639 struct dma_engine *dma_engine,
2640 unsigned int dma_chan,
2641 unsigned int port_map_mask,
2642 bool ovly)
95c6e9cb 2643{
406261ce 2644 int status = 0;
01ef7dbf
IM		 2645 bool comm_dma_setup_done = false;
2646 const unsigned int *data;
2647 unsigned int chip_addx;
2648 unsigned int words_to_write;
2649 unsigned int buffer_size_words;
2650 unsigned char *buffer_addx;
2651 unsigned short hda_format;
2652 unsigned int sample_rate_div;
2653 unsigned int sample_rate_mul;
2654 unsigned int num_chans;
2655 unsigned int hda_frame_size_words;
2656 unsigned int remainder_words;
2657 const u32 *data_remainder;
2658 u32 chip_addx_remainder;
2659 unsigned int run_size_words;
2660 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2661 unsigned long timeout;
2662 bool dma_active;
01ef7dbf
IM		 2663
2664 if (fls == NULL)
2665 return -EINVAL;
2666 if (is_hci_prog_list_seg(fls)) {
2667 hci_write = fls;
2668 fls = get_next_seg_ptr(fls);
2669 }
95c6e9cb 2670
01ef7dbf 2671 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2672 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2673 return dspxfr_hci_write(codec, hci_write);
2674 }
95c6e9cb 2675
01ef7dbf 2676 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2677 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2678 return -EINVAL;
95c6e9cb
IM		 2679 }
2680
01ef7dbf
IM		 2681 data = fls->data;
2682 chip_addx = fls->chip_addr,
2683 words_to_write = fls->count;
2684
2685 if (!words_to_write)
2686 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2687 if (reloc)
2688 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2689
2690 if (!UC_RANGE(chip_addx, words_to_write) &&
2691 !X_RANGE_ALL(chip_addx, words_to_write) &&
2692 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2693 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2694 return -EINVAL;
95c6e9cb
IM		 2695 }
2696
01ef7dbf
IM		 2697 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2698 sizeof(u32);
2699
2700 buffer_addx = dma_get_buffer_addr(dma_engine);
2701
2702 if (buffer_addx == NULL) {
4e76a883 2703 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2704 return -EINVAL;
2705 }
2706
2707 dma_get_converter_format(dma_engine, &hda_format);
2708 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2709 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2710 num_chans = get_hdafmt_chs(hda_format) + 1;
2711
2712 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2713 (num_chans * sample_rate_mul / sample_rate_div));
2714
3bc085a1 2715 if (hda_frame_size_words == 0) {
4e76a883 2716 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2717 return -EINVAL;
2718 }
2719
01ef7dbf
IM		 2720 buffer_size_words = min(buffer_size_words,
2721 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2722 65536 : 32768));
2723 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2724 codec_dbg(codec,
01ef7dbf
IM		 2725 "chpadr=0x%08x frmsz=%u nchan=%u "
2726 "rate_mul=%u div=%u bufsz=%u\n",
2727 chip_addx, hda_frame_size_words, num_chans,
2728 sample_rate_mul, sample_rate_div, buffer_size_words);
2729
3bc085a1 2730 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2731 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2732 return -EINVAL;
2733 }
2734
2735 remainder_words = words_to_write % hda_frame_size_words;
2736 data_remainder = data;
2737 chip_addx_remainder = chip_addx;
2738
2739 data += remainder_words;
2740 chip_addx += remainder_words*sizeof(u32);
2741 words_to_write -= remainder_words;
2742
2743 while (words_to_write != 0) {
2744 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2745 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2746 words_to_write, run_size_words, remainder_words);
2747 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2748 if (!comm_dma_setup_done) {
2749 status = dsp_dma_stop(codec, dma_chan, ovly);
2750 if (status < 0)
425a7880 2751 return status;
01ef7dbf
IM		 2752 status = dsp_dma_setup_common(codec, chip_addx,
2753 dma_chan, port_map_mask, ovly);
2754 if (status < 0)
2755 return status;
2756 comm_dma_setup_done = true;
2757 }
2758
2759 status = dsp_dma_setup(codec, chip_addx,
2760 run_size_words, dma_chan);
2761 if (status < 0)
2762 return status;
2763 status = dsp_dma_start(codec, dma_chan, ovly);
2764 if (status < 0)
2765 return status;
2766 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2767 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2768 return -EIO;
2769 }
2770 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2771 if (status < 0)
2772 return status;
2773 if (remainder_words != 0) {
2774 status = chipio_write_multiple(codec,
2775 chip_addx_remainder,
2776 data_remainder,
2777 remainder_words);
b3667bd7
TI		 2778 if (status < 0)
2779 return status;
01ef7dbf
IM		 2780 remainder_words = 0;
2781 }
2782 if (hci_write) {
2783 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2784 if (status < 0)
2785 return status;
01ef7dbf
IM		 2786 hci_write = NULL;
2787 }
6d67530e
IM		 2788
2789 timeout = jiffies + msecs_to_jiffies(2000);
2790 do {
2791 dma_active = dsp_is_dma_active(codec, dma_chan);
2792 if (!dma_active)
01ef7dbf 2793 break;
6d67530e
IM		 2794 msleep(20);
2795 } while (time_before(jiffies, timeout));
2796 if (dma_active)
2797 break;
2798
4e76a883 2799 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2800 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2801 status = dma_reset(dma_engine);
01ef7dbf
IM		 2802
2803 if (status < 0)
2804 return status;
2805
2806 data += run_size_words;
2807 chip_addx += run_size_words*sizeof(u32);
2808 words_to_write -= run_size_words;
2809 }
2810
2811 if (remainder_words != 0) {
2812 status = chipio_write_multiple(codec, chip_addx_remainder,
2813 data_remainder, remainder_words);
2814 }
2815
2816 return status;
95c6e9cb
IM		 2817}
2818
d5c21b88
IM		 2819/**
2820 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2821 *
2822 * @codec: the HDA codec
2823 * @fls_data: pointer to a fast load image
2824 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2825 * no relocation
e97249dd 2826 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2827 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2828 * @ovly: TRUE if overlay format is required
2829 *
2830 * Returns zero or a negative error code.
2831 */
01ef7dbf
IM		 2832static int dspxfr_image(struct hda_codec *codec,
2833 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2834 unsigned int reloc,
2835 unsigned int sample_rate,
2836 unsigned short channels,
01ef7dbf 2837 bool ovly)
95c6e9cb
IM		 2838{
2839 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2840 int status;
2841 unsigned short hda_format = 0;
2842 unsigned int response;
2843 unsigned char stream_id = 0;
2844 struct dma_engine *dma_engine;
2845 unsigned int dma_chan;
2846 unsigned int port_map_mask;
2847
2848 if (fls_data == NULL)
2849 return -EINVAL;
2850
2851 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2852 if (!dma_engine)
2853 return -ENOMEM;
95c6e9cb 2854
01ef7dbf
IM		 2855 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2856 if (!dma_engine->dmab) {
549e8292
TI		 2857 kfree(dma_engine);
2858 return -ENOMEM;
01ef7dbf 2859 }
95c6e9cb 2860
01ef7dbf 2861 dma_engine->codec = codec;
6194b99d 2862 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2863 dma_engine->m_converter_format = hda_format;
2864 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2865 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2866
8ae3124b 2867 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2868
2869 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2870 hda_format, &response);
2871
2872 if (status < 0) {
4e76a883 2873 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2874 goto exit;
2875 }
2876
2877 status = snd_hda_codec_load_dsp_prepare(codec,
2878 dma_engine->m_converter_format,
2879 dma_engine->buf_size,
2880 dma_engine->dmab);
2881 if (status < 0)
95c6e9cb 2882 goto exit;
01ef7dbf
IM		 2883 spec->dsp_stream_id = status;
2884
2885 if (ovly) {
2886 status = dspio_alloc_dma_chan(codec, &dma_chan);
2887 if (status < 0) {
4e76a883 2888 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2889 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2890 goto exit;
2891 }
2892 }
95c6e9cb 2893
01ef7dbf
IM		 2894 port_map_mask = 0;
2895 status = dsp_allocate_ports_format(codec, hda_format,
2896 &port_map_mask);
2897 if (status < 0) {
4e76a883 2898 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2899 goto exit;
2900 }
2901
2902 stream_id = dma_get_stream_id(dma_engine);
2903 status = codec_set_converter_stream_channel(codec,
2904 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2905 if (status < 0) {
4e76a883 2906 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2907 goto exit;
2908 }
2909
2910 while ((fls_data != NULL) && !is_last(fls_data)) {
2911 if (!is_valid(fls_data)) {
4e76a883 2912 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2913 status = -EINVAL;
2914 goto exit;
2915 }
2916 status = dspxfr_one_seg(codec, fls_data, reloc,
2917 dma_engine, dma_chan,
2918 port_map_mask, ovly);
2919 if (status < 0)
2920 break;
2921
2922 if (is_hci_prog_list_seg(fls_data))
2923 fls_data = get_next_seg_ptr(fls_data);
2924
2925 if ((fls_data != NULL) && !is_last(fls_data))
2926 fls_data = get_next_seg_ptr(fls_data);
2927 }
2928
2929 if (port_map_mask != 0)
2930 status = dsp_free_ports(codec);
2931
2932 if (status < 0)
95c6e9cb
IM		 2933 goto exit;
2934
01ef7dbf
IM		 2935 status = codec_set_converter_stream_channel(codec,
2936 WIDGET_CHIP_CTRL, 0, 0, &response);
2937
95c6e9cb 2938exit:
01ef7dbf
IM		 2939 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2940 dspio_free_dma_chan(codec, dma_chan);
2941
b3667bd7 2942 if (dma_engine->dmab->area)
01ef7dbf
IM		 2943 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2944 kfree(dma_engine->dmab);
2945 kfree(dma_engine);
2946
2947 return status;
95c6e9cb
IM		 2948}
2949
2950/*
01ef7dbf 2951 * CA0132 DSP download stuffs.
95c6e9cb 2952 */
01ef7dbf 2953static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2954{
009b8f97 2955 struct ca0132_spec *spec = codec->spec;
4e76a883 2956 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 2957 if (!spec->use_alt_functions) {
2958 /*set DSP speaker to 2.0 configuration*/
2959 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2960 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2961
009b8f97
CM		 2962 /*update write pointer*/
2963 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2964 }
01ef7dbf 2965}
95c6e9cb 2966
d5c21b88 2967/**
e60b2c7f 2968 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2969 *
2970 * @codec: the HDA codec
2971 * @fls: pointer to a fast load image
2972 * @ovly: TRUE if overlay format is required
2973 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2974 * no relocation
2975 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2976 * @router_chans: number of audio router channels to be allocated (0 means use
2977 * internal defaults; max is 32)
2978 *
e60b2c7f
TI		 2979 * Download DSP from a DSP Image Fast Load structure. This structure is a
2980 * linear, non-constant sized element array of structures, each of which
2981 * contain the count of the data to be loaded, the data itself, and the
2982 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2983 * Returns zero or a negative error code.
2984 */
01ef7dbf
IM		 2985static int dspload_image(struct hda_codec *codec,
2986 const struct dsp_image_seg *fls,
2987 bool ovly,
2988 unsigned int reloc,
2989 bool autostart,
2990 int router_chans)
2991{
2992 int status = 0;
e97249dd
IM		 2993 unsigned int sample_rate;
2994 unsigned short channels;
01ef7dbf 2995
4e76a883 2996 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2997 if (router_chans == 0) {
2998 if (!ovly)
2999 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3000 else
3001 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3002 }
95c6e9cb 3003
e97249dd
IM		 3004 sample_rate = 48000;
3005 channels = (unsigned short)router_chans;
01ef7dbf 3006
e97249dd
IM		 3007 while (channels > 16) {
3008 sample_rate *= 2;
3009 channels /= 2;
01ef7dbf
IM		 3010 }
3011
01ef7dbf 3012 do {
4e76a883 3013 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3014 if (!ovly)
3015 status = dsp_reset(codec);
3016
3017 if (status < 0)
3018 break;
3019
4e76a883 3020 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3021 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3022 ovly);
01ef7dbf
IM		 3023
3024 if (status < 0)
3025 break;
3026
4e76a883 3027 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3028 if (autostart && !ovly) {
3029 dspload_post_setup(codec);
3030 status = dsp_set_run_state(codec);
3031 }
3032
4e76a883 3033 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3034 } while (0);
3035
3036 return status;
3037}
3038
f664417e 3039#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3040static bool dspload_is_loaded(struct hda_codec *codec)
3041{
3042 unsigned int data = 0;
3043 int status = 0;
3044
3045 status = chipio_read(codec, 0x40004, &data);
3046 if ((status < 0) || (data != 1))
3047 return false;
3048
3049 return true;
3050}
f664417e
TI		 3051#else
3052#define dspload_is_loaded(codec) false
3053#endif
01ef7dbf
IM		 3054
3055static bool dspload_wait_loaded(struct hda_codec *codec)
3056{
6d67530e 3057 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3058
3059 do {
01ef7dbf 3060 if (dspload_is_loaded(codec)) {
d9684bb5 3061 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3062 return true;
3063 }
6d67530e
IM		 3064 msleep(20);
3065 } while (time_before(jiffies, timeout));
01ef7dbf 3066
d9684bb5 3067 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3068 return false;
95c6e9cb
IM		 3069}
3070
e93ac30a
CM		 3071/*
3072 * Setup GPIO for the other variants of Core3D.
3073 */
3074
a62e4739
CM		 3075/*
3076 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3077 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3078 * The first eight bits are just the number of the pin. So far, I've only seen
3079 * this number go to 7.
3080 */
3081static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3082 bool enable)
3083{
3084 struct ca0132_spec *spec = codec->spec;
3085 unsigned short gpio_data;
3086
3087 gpio_data = gpio_pin & 0xF;
3088 gpio_data |= ((enable << 8) & 0x100);
3089
3090 writew(gpio_data, spec->mem_base + 0x320);
3091}
3092
e93ac30a
CM		 3093/*
3094 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3095 * the card shows as having no GPIO pins.
3096 */
3097static void ca0132_gpio_init(struct hda_codec *codec)
3098{
3099 struct ca0132_spec *spec = codec->spec;
3100
3101 switch (spec->quirk) {
3102 case QUIRK_SBZ:
3103 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3104 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3105 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3106 break;
3107 case QUIRK_R3DI:
3108 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3109 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3110 break;
3111 }
3112
3113}
3114
3115/* Sets the GPIO for audio output. */
3116static void ca0132_gpio_setup(struct hda_codec *codec)
3117{
3118 struct ca0132_spec *spec = codec->spec;
3119
3120 switch (spec->quirk) {
3121 case QUIRK_SBZ:
3122 snd_hda_codec_write(codec, 0x01, 0,
3123 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3124 snd_hda_codec_write(codec, 0x01, 0,
3125 AC_VERB_SET_GPIO_MASK, 0x07);
3126 snd_hda_codec_write(codec, 0x01, 0,
3127 AC_VERB_SET_GPIO_DATA, 0x04);
3128 snd_hda_codec_write(codec, 0x01, 0,
3129 AC_VERB_SET_GPIO_DATA, 0x06);
3130 break;
3131 case QUIRK_R3DI:
3132 snd_hda_codec_write(codec, 0x01, 0,
3133 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3134 snd_hda_codec_write(codec, 0x01, 0,
3135 AC_VERB_SET_GPIO_MASK, 0x1F);
3136 snd_hda_codec_write(codec, 0x01, 0,
3137 AC_VERB_SET_GPIO_DATA, 0x0C);
3138 break;
3139 }
3140}
3141
7e6ed62e
CM		 3142/*
3143 * GPIO control functions for the Recon3D integrated.
3144 */
3145
3146enum r3di_gpio_bit {
3147 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3148 R3DI_MIC_SELECT_BIT = 1,
3149 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3150 R3DI_OUT_SELECT_BIT = 2,
3151 /*
3152 * I dunno what this actually does, but it stays on until the dsp
3153 * is downloaded.
3154 */
3155 R3DI_GPIO_DSP_DOWNLOADING = 3,
3156 /*
3157 * Same as above, no clue what it does, but it comes on after the dsp
3158 * is downloaded.
3159 */
3160 R3DI_GPIO_DSP_DOWNLOADED = 4
3161};
3162
3163enum r3di_mic_select {
3164 /* Set GPIO bit 1 to 0 for rear mic */
3165 R3DI_REAR_MIC = 0,
3166 /* Set GPIO bit 1 to 1 for front microphone*/
3167 R3DI_FRONT_MIC = 1
3168};
3169
3170enum r3di_out_select {
3171 /* Set GPIO bit 2 to 0 for headphone */
3172 R3DI_HEADPHONE_OUT = 0,
3173 /* Set GPIO bit 2 to 1 for speaker */
3174 R3DI_LINE_OUT = 1
3175};
3176enum r3di_dsp_status {
3177 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3178 R3DI_DSP_DOWNLOADING = 0,
3179 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3180 R3DI_DSP_DOWNLOADED = 1
3181};
3182
7cb9d94c
CM		 3183
3184static void r3di_gpio_mic_set(struct hda_codec *codec,
3185 enum r3di_mic_select cur_mic)
3186{
3187 unsigned int cur_gpio;
3188
3189 /* Get the current GPIO Data setup */
3190 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3191
3192 switch (cur_mic) {
3193 case R3DI_REAR_MIC:
3194 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3195 break;
3196 case R3DI_FRONT_MIC:
3197 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3198 break;
3199 }
3200 snd_hda_codec_write(codec, codec->core.afg, 0,
3201 AC_VERB_SET_GPIO_DATA, cur_gpio);
3202}
3203
3204static void r3di_gpio_out_set(struct hda_codec *codec,
3205 enum r3di_out_select cur_out)
3206{
3207 unsigned int cur_gpio;
3208
3209 /* Get the current GPIO Data setup */
3210 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3211
3212 switch (cur_out) {
3213 case R3DI_HEADPHONE_OUT:
3214 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3215 break;
3216 case R3DI_LINE_OUT:
3217 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3218 break;
3219 }
3220 snd_hda_codec_write(codec, codec->core.afg, 0,
3221 AC_VERB_SET_GPIO_DATA, cur_gpio);
3222}
3223
7e6ed62e
CM		 3224static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3225 enum r3di_dsp_status dsp_status)
3226{
3227 unsigned int cur_gpio;
3228
3229 /* Get the current GPIO Data setup */
3230 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3231
3232 switch (dsp_status) {
3233 case R3DI_DSP_DOWNLOADING:
3234 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3235 snd_hda_codec_write(codec, codec->core.afg, 0,
3236 AC_VERB_SET_GPIO_DATA, cur_gpio);
3237 break;
3238 case R3DI_DSP_DOWNLOADED:
3239 /* Set DOWNLOADING bit to 0. */
3240 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3241
3242 snd_hda_codec_write(codec, codec->core.afg, 0,
3243 AC_VERB_SET_GPIO_DATA, cur_gpio);
3244
3245 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3246 break;
3247 }
3248
3249 snd_hda_codec_write(codec, codec->core.afg, 0,
3250 AC_VERB_SET_GPIO_DATA, cur_gpio);
3251}
3252
825315bc
IM		 3253/*
3254 * PCM callbacks
3255 */
95c6e9cb
IM		 3256static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3257 struct hda_codec *codec,
3258 unsigned int stream_tag,
3259 unsigned int format,
3260 struct snd_pcm_substream *substream)
3261{
3262 struct ca0132_spec *spec = codec->spec;
825315bc 3263
28fba950 3264 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3265
3266 return 0;
95c6e9cb
IM		 3267}
3268
3269static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3270 struct hda_codec *codec,
3271 struct snd_pcm_substream *substream)
3272{
3273 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3274
3275 if (spec->dsp_state == DSP_DOWNLOADING)
3276 return 0;
3277
3278 /*If Playback effects are on, allow stream some time to flush
3279 *effects tail*/
3280 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3281 msleep(50);
3282
28fba950 3283 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3284
3285 return 0;
95c6e9cb
IM		 3286}
3287
e8412ca4
DR		 3288static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3289 struct hda_codec *codec,
3290 struct snd_pcm_substream *substream)
3291{
3292 struct ca0132_spec *spec = codec->spec;
3293 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3294 struct snd_pcm_runtime *runtime = substream->runtime;
3295
3296 if (spec->dsp_state != DSP_DOWNLOADED)
3297 return 0;
3298
3299 /* Add latency if playback enhancement and either effect is enabled. */
3300 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3301 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3302 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3303 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3304 }
3305
3306 /* Applying Speaker EQ adds latency as well. */
3307 if (spec->cur_out_type == SPEAKER_OUT)
3308 latency += DSP_SPEAKER_OUT_LATENCY;
3309
3310 return (latency * runtime->rate) / 1000;
3311}
3312
95c6e9cb
IM		 3313/*
3314 * Digital out
3315 */
27ebeb0b
TI		 3316static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3317 struct hda_codec *codec,
3318 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3319{
3320 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3321 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3322}
3323
27ebeb0b 3324static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3325 struct hda_codec *codec,
3326 unsigned int stream_tag,
3327 unsigned int format,
3328 struct snd_pcm_substream *substream)
3329{
3330 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3331 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3332 stream_tag, format, substream);
95c6e9cb
IM		 3333}
3334
27ebeb0b 3335static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3336 struct hda_codec *codec,
95c6e9cb
IM		 3337 struct snd_pcm_substream *substream)
3338{
3339 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3340 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3341}
3342
27ebeb0b
TI		 3343static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3344 struct hda_codec *codec,
3345 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3346{
3347 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3348 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3349}
3350
825315bc
IM		 3351/*
3352 * Analog capture
3353 */
3354static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3355 struct hda_codec *codec,
3356 unsigned int stream_tag,
3357 unsigned int format,
3358 struct snd_pcm_substream *substream)
3359{
13c12dbe 3360 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3361 stream_tag, 0, format);
825315bc
IM		 3362
3363 return 0;
3364}
3365
3366static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3367 struct hda_codec *codec,
3368 struct snd_pcm_substream *substream)
3369{
3370 struct ca0132_spec *spec = codec->spec;
3371
3372 if (spec->dsp_state == DSP_DOWNLOADING)
3373 return 0;
3374
28fba950 3375 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3376 return 0;
3377}
3378
e8412ca4
DR		 3379static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3380 struct hda_codec *codec,
3381 struct snd_pcm_substream *substream)
3382{
3383 struct ca0132_spec *spec = codec->spec;
3384 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3385 struct snd_pcm_runtime *runtime = substream->runtime;
3386
3387 if (spec->dsp_state != DSP_DOWNLOADED)
3388 return 0;
3389
3390 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3391 latency += DSP_CRYSTAL_VOICE_LATENCY;
3392
3393 return (latency * runtime->rate) / 1000;
3394}
3395
e90f29e4
IM		 3396/*
3397 * Controls stuffs.
3398 */
3399
3400/*
3401 * Mixer controls helpers.
3402 */
3403#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3404 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3405 .name = xname, \
3406 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3407 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3408 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3409 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3410 .info = ca0132_volume_info, \
3411 .get = ca0132_volume_get, \
3412 .put = ca0132_volume_put, \
3413 .tlv = { .c = ca0132_volume_tlv }, \
3414 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3415
017310fb
CM		 3416/*
3417 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3418 * volume put, which is used for setting the DSP volume. This was done because
3419 * the ca0132 functions were taking too much time and causing lag.
3420 */
3421#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3422 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3423 .name = xname, \
3424 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3425 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3426 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3427 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3428 .info = snd_hda_mixer_amp_volume_info, \
3429 .get = snd_hda_mixer_amp_volume_get, \
3430 .put = ca0132_alt_volume_put, \
3431 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3432 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3433
e90f29e4
IM		 3434#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3435 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3436 .name = xname, \
3437 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3438 .info = snd_hda_mixer_amp_switch_info, \
3439 .get = ca0132_switch_get, \
3440 .put = ca0132_switch_put, \
3441 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3442
3443/* stereo */
3444#define CA0132_CODEC_VOL(xname, nid, dir) \
3445 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3446#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3447 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3448#define CA0132_CODEC_MUTE(xname, nid, dir) \
3449 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3450
017310fb
CM		 3451/* lookup tables */
3452/*
3453 * Lookup table with decibel values for the DSP. When volume is changed in
3454 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3455 * these values have decimal points, probably because the Windows driver
3456 * actually uses floating point. We can't here, so I made a lookup table of
3457 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3458 * DAC's, and 9 is the maximum.
3459 */
3460static const unsigned int float_vol_db_lookup[] = {
34610xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
34620xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
34630xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
34640xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
34650xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
34660xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
34670xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
34680xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
34690xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
34700xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
34710xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
34720xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
34730xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
34740xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
34750xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
34760x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
34770x40C00000, 0x40E00000, 0x41000000, 0x41100000
3478};
3479
47cdf76e
CM		 3480/*
3481 * This table counts from float 0 to 1 in increments of .01, which is
3482 * useful for a few different sliders.
3483 */
3484static const unsigned int float_zero_to_one_lookup[] = {
34850x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
34860x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
34870x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
34880x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
34890x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
34900x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
34910x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
34920x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
34930x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
34940x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
34950x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
34960x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
34970x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
34980x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
34990x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
35000x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
35010x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3502};
3503
3504/*
3505 * This table counts from float 10 to 1000, which is the range of the x-bass
3506 * crossover slider in Windows.
3507 */
3508static const unsigned int float_xbass_xover_lookup[] = {
35090x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
35100x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
35110x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
35120x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
35130x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
35140x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
35150x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
35160x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
35170x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
35180x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
35190x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
35200x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
35210x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
35220x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
35230x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
35240x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
35250x44728000, 0x44750000, 0x44778000, 0x447A0000
3526};
3527
4091fb95 3528/* The following are for tuning of products */
44f0c978
IM		 3529#ifdef ENABLE_TUNING_CONTROLS
3530
3531static unsigned int voice_focus_vals_lookup[] = {
35320x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
35330x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
35340x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
35350x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
35360x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
35370x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
35380x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
35390x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
35400x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
35410x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
35420x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
35430x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
35440x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
35450x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
35460x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
35470x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
35480x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
35490x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
35500x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
35510x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
35520x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
35530x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
35540x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
35550x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
35560x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
35570x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
35580x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3559};
3560
3561static unsigned int mic_svm_vals_lookup[] = {
35620x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
35630x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
35640x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
35650x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
35660x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
35670x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
35680x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
35690x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
35700x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
35710x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
35720x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
35730x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
35740x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
35750x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
35760x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
35770x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
35780x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3579};
3580
3581static unsigned int equalizer_vals_lookup[] = {
35820xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
35830xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
35840xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
35850xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
35860x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
35870x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
35880x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
35890x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
35900x41C00000
3591};
3592
3593static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3594 unsigned int *lookup, int idx)
3595{
3596 int i = 0;
3597
3598 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3599 if (nid == ca0132_tuning_ctls[i].nid)
3600 break;
3601
3602 snd_hda_power_up(codec);
447fd8e9 3603 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3604 ca0132_tuning_ctls[i].req,
3605 &(lookup[idx]), sizeof(unsigned int));
3606 snd_hda_power_down(codec);
3607
3608 return 1;
3609}
3610
3611static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3612 struct snd_ctl_elem_value *ucontrol)
3613{
3614 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3615 struct ca0132_spec *spec = codec->spec;
3616 hda_nid_t nid = get_amp_nid(kcontrol);
3617 long *valp = ucontrol->value.integer.value;
3618 int idx = nid - TUNING_CTL_START_NID;
3619
3620 *valp = spec->cur_ctl_vals[idx];
3621 return 0;
3622}
3623
3624static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3625 struct snd_ctl_elem_info *uinfo)
3626{
3627 int chs = get_amp_channels(kcontrol);
3628 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3629 uinfo->count = chs == 3 ? 2 : 1;
3630 uinfo->value.integer.min = 20;
3631 uinfo->value.integer.max = 180;
3632 uinfo->value.integer.step = 1;
3633
3634 return 0;
3635}
3636
3637static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3638 struct snd_ctl_elem_value *ucontrol)
3639{
3640 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3641 struct ca0132_spec *spec = codec->spec;
3642 hda_nid_t nid = get_amp_nid(kcontrol);
3643 long *valp = ucontrol->value.integer.value;
3644 int idx;
3645
3646 idx = nid - TUNING_CTL_START_NID;
3647 /* any change? */
3648 if (spec->cur_ctl_vals[idx] == *valp)
3649 return 0;
3650
3651 spec->cur_ctl_vals[idx] = *valp;
3652
3653 idx = *valp - 20;
3654 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3655
3656 return 1;
3657}
3658
3659static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3660 struct snd_ctl_elem_info *uinfo)
3661{
3662 int chs = get_amp_channels(kcontrol);
3663 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3664 uinfo->count = chs == 3 ? 2 : 1;
3665 uinfo->value.integer.min = 0;
3666 uinfo->value.integer.max = 100;
3667 uinfo->value.integer.step = 1;
3668
3669 return 0;
3670}
3671
3672static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3673 struct snd_ctl_elem_value *ucontrol)
3674{
3675 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3676 struct ca0132_spec *spec = codec->spec;
3677 hda_nid_t nid = get_amp_nid(kcontrol);
3678 long *valp = ucontrol->value.integer.value;
3679 int idx;
3680
3681 idx = nid - TUNING_CTL_START_NID;
3682 /* any change? */
3683 if (spec->cur_ctl_vals[idx] == *valp)
3684 return 0;
3685
3686 spec->cur_ctl_vals[idx] = *valp;
3687
3688 idx = *valp;
3689 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3690
3691 return 0;
3692}
3693
3694static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3695 struct snd_ctl_elem_info *uinfo)
3696{
3697 int chs = get_amp_channels(kcontrol);
3698 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3699 uinfo->count = chs == 3 ? 2 : 1;
3700 uinfo->value.integer.min = 0;
3701 uinfo->value.integer.max = 48;
3702 uinfo->value.integer.step = 1;
3703
3704 return 0;
3705}
3706
3707static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3708 struct snd_ctl_elem_value *ucontrol)
3709{
3710 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3711 struct ca0132_spec *spec = codec->spec;
3712 hda_nid_t nid = get_amp_nid(kcontrol);
3713 long *valp = ucontrol->value.integer.value;
3714 int idx;
3715
3716 idx = nid - TUNING_CTL_START_NID;
3717 /* any change? */
3718 if (spec->cur_ctl_vals[idx] == *valp)
3719 return 0;
3720
3721 spec->cur_ctl_vals[idx] = *valp;
3722
3723 idx = *valp;
3724 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3725
3726 return 1;
3727}
3728
8e142e9e
TS		 3729static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3730static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3731
3732static int add_tuning_control(struct hda_codec *codec,
3733 hda_nid_t pnid, hda_nid_t nid,
3734 const char *name, int dir)
3735{
975cc02a 3736 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3737 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3738 struct snd_kcontrol_new knew =
3739 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3740
3741 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3742 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3743 knew.tlv.c = 0;
3744 knew.tlv.p = 0;
3745 switch (pnid) {
3746 case VOICE_FOCUS:
3747 knew.info = voice_focus_ctl_info;
3748 knew.get = tuning_ctl_get;
3749 knew.put = voice_focus_ctl_put;
3750 knew.tlv.p = voice_focus_db_scale;
3751 break;
3752 case MIC_SVM:
3753 knew.info = mic_svm_ctl_info;
3754 knew.get = tuning_ctl_get;
3755 knew.put = mic_svm_ctl_put;
3756 break;
3757 case EQUALIZER:
3758 knew.info = equalizer_ctl_info;
3759 knew.get = tuning_ctl_get;
3760 knew.put = equalizer_ctl_put;
3761 knew.tlv.p = eq_db_scale;
3762 break;
3763 default:
3764 return 0;
3765 }
3766 knew.private_value =
3767 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3768 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3769 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3770}
3771
3772static int add_tuning_ctls(struct hda_codec *codec)
3773{
3774 int i;
3775 int err;
3776
3777 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3778 err = add_tuning_control(codec,
3779 ca0132_tuning_ctls[i].parent_nid,
3780 ca0132_tuning_ctls[i].nid,
3781 ca0132_tuning_ctls[i].name,
3782 ca0132_tuning_ctls[i].direct);
3783 if (err < 0)
3784 return err;
3785 }
3786
3787 return 0;
3788}
3789
3790static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3791{
3792 struct ca0132_spec *spec = codec->spec;
3793 int i;
3794
3795 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3796 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3797 /* SVM level defaults to 0.74. */
3798 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3799
3800 /* EQ defaults to 0dB. */
3801 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3802 spec->cur_ctl_vals[i] = 24;
3803}
3804#endif /*ENABLE_TUNING_CONTROLS*/
3805
5aaca44d
IM		 3806/*
3807 * Select the active output.
3808 * If autodetect is enabled, output will be selected based on jack detection.
3809 * If jack inserted, headphone will be selected, else built-in speakers
3810 * If autodetect is disabled, output will be selected based on selection.
3811 */
3812static int ca0132_select_out(struct hda_codec *codec)
3813{
3814 struct ca0132_spec *spec = codec->spec;
3815 unsigned int pin_ctl;
3816 int jack_present;
3817 int auto_jack;
3818 unsigned int tmp;
3819 int err;
3820
4e76a883 3821 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3822
664c7155 3823 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3824
3825 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3826
3827 if (auto_jack)
fe14f39e 3828 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3829 else
3830 jack_present =
3831 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3832
3833 if (jack_present)
3834 spec->cur_out_type = HEADPHONE_OUT;
3835 else
3836 spec->cur_out_type = SPEAKER_OUT;
3837
3838 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3839 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3840 /*speaker out config*/
3841 tmp = FLOAT_ONE;
3842 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3843 if (err < 0)
3844 goto exit;
3845 /*enable speaker EQ*/
3846 tmp = FLOAT_ONE;
3847 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3848 if (err < 0)
3849 goto exit;
3850
3851 /* Setup EAPD */
3852 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3853 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3854 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3855 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3856 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3857 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3858 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3859 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3860
3861 /* disable headphone node */
3862 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3863 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3864 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3865 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3866 /* enable speaker node */
3867 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 3868 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3869 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3870 pin_ctl | PIN_OUT);
5aaca44d 3871 } else {
4e76a883 3872 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3873 /*headphone out config*/
3874 tmp = FLOAT_ZERO;
3875 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3876 if (err < 0)
3877 goto exit;
3878 /*disable speaker EQ*/
3879 tmp = FLOAT_ZERO;
3880 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3881 if (err < 0)
3882 goto exit;
3883
3884 /* Setup EAPD */
3885 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3886 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3887 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3888 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3889 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3890 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3891 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3892 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3893
3894 /* disable speaker*/
3895 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3896 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3897 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3898 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3899 /* enable headphone*/
3900 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3901 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3902 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3903 pin_ctl | PIN_HP);
5aaca44d
IM		 3904 }
3905
3906exit:
664c7155 3907 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3908
3909 return err < 0 ? err : 0;
3910}
3911
7cb9d94c
CM		 3912/*
3913 * This function behaves similarly to the ca0132_select_out funciton above,
3914 * except with a few differences. It adds the ability to select the current
3915 * output with an enumerated control "output source" if the auto detect
3916 * mute switch is set to off. If the auto detect mute switch is enabled, it
3917 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3918 * It also adds the ability to auto-detect the front headphone port. The only
3919 * way to select surround is to disable auto detect, and set Surround with the
3920 * enumerated control.
3921 */
3922static int ca0132_alt_select_out(struct hda_codec *codec)
3923{
3924 struct ca0132_spec *spec = codec->spec;
3925 unsigned int pin_ctl;
3926 int jack_present;
3927 int auto_jack;
3928 unsigned int i;
3929 unsigned int tmp;
3930 int err;
3931 /* Default Headphone is rear headphone */
3932 hda_nid_t headphone_nid = spec->out_pins[1];
3933
3934 codec_dbg(codec, "%s\n", __func__);
3935
3936 snd_hda_power_up_pm(codec);
3937
3938 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3939
3940 /*
3941 * If headphone rear or front is plugged in, set to headphone.
3942 * If neither is plugged in, set to rear line out. Only if
3943 * hp/speaker auto detect is enabled.
3944 */
3945 if (auto_jack) {
3946 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3947 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3948
3949 if (jack_present)
3950 spec->cur_out_type = HEADPHONE_OUT;
3951 else
3952 spec->cur_out_type = SPEAKER_OUT;
3953 } else
3954 spec->cur_out_type = spec->out_enum_val;
3955
3956 /* Begin DSP output switch */
3957 tmp = FLOAT_ONE;
3958 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3959 if (err < 0)
3960 goto exit;
3961
3962 switch (spec->cur_out_type) {
3963 case SPEAKER_OUT:
3964 codec_dbg(codec, "%s speaker\n", __func__);
3965 /*speaker out config*/
3966 switch (spec->quirk) {
3967 case QUIRK_SBZ:
a62e4739
CM		 3968 ca0132_mmio_gpio_set(codec, 7, false);
3969 ca0132_mmio_gpio_set(codec, 4, true);
3970 ca0132_mmio_gpio_set(codec, 1, true);
7cb9d94c
CM		 3971 chipio_set_control_param(codec, 0x0D, 0x18);
3972 break;
3973 case QUIRK_R3DI:
3974 chipio_set_control_param(codec, 0x0D, 0x24);
3975 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3976 break;
3977 }
3978
3979 /* disable headphone node */
3980 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3981 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3982 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3983 pin_ctl & ~PIN_HP);
3984 /* enable line-out node */
3985 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3986 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3987 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3988 pin_ctl | PIN_OUT);
3989 /* Enable EAPD */
3990 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3991 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
3992
3993 /* If PlayEnhancement is enabled, set different source */
3994 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3995 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
3996 else
3997 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
3998 break;
3999 case HEADPHONE_OUT:
4000 codec_dbg(codec, "%s hp\n", __func__);
4001 /* Headphone out config*/
4002 switch (spec->quirk) {
4003 case QUIRK_SBZ:
a62e4739
CM		 4004 ca0132_mmio_gpio_set(codec, 7, true);
4005 ca0132_mmio_gpio_set(codec, 4, true);
4006 ca0132_mmio_gpio_set(codec, 1, false);
7cb9d94c
CM		 4007 chipio_set_control_param(codec, 0x0D, 0x12);
4008 break;
4009 case QUIRK_R3DI:
4010 chipio_set_control_param(codec, 0x0D, 0x21);
4011 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4012 break;
4013 }
4014
4015 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4016 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4017
4018 /* disable speaker*/
4019 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4020 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4021 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4022 pin_ctl & ~PIN_HP);
4023
4024 /* enable headphone, either front or rear */
4025
4026 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4027 headphone_nid = spec->out_pins[2];
4028 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4029 headphone_nid = spec->out_pins[1];
4030
4031 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4032 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4033 snd_hda_set_pin_ctl(codec, headphone_nid,
4034 pin_ctl | PIN_HP);
4035
4036 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4037 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4038 else
4039 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4040 break;
4041 case SURROUND_OUT:
4042 codec_dbg(codec, "%s surround\n", __func__);
4043 /* Surround out config*/
4044 switch (spec->quirk) {
4045 case QUIRK_SBZ:
a62e4739
CM		 4046 ca0132_mmio_gpio_set(codec, 7, false);
4047 ca0132_mmio_gpio_set(codec, 4, true);
4048 ca0132_mmio_gpio_set(codec, 1, true);
7cb9d94c
CM		 4049 chipio_set_control_param(codec, 0x0D, 0x18);
4050 break;
4051 case QUIRK_R3DI:
4052 chipio_set_control_param(codec, 0x0D, 0x24);
4053 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4054 break;
4055 }
4056 /* enable line out node */
4057 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4058 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4059 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4060 pin_ctl | PIN_OUT);
4061 /* Disable headphone out */
4062 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4063 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4064 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4065 pin_ctl & ~PIN_HP);
4066 /* Enable EAPD on line out */
4067 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4068 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4069 /* enable center/lfe out node */
4070 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4071 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4072 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4073 pin_ctl | PIN_OUT);
4074 /* Now set rear surround node as out. */
4075 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4076 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4077 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4078 pin_ctl | PIN_OUT);
4079
4080 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4081 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4082 else
4083 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4084 break;
4085 }
4086
4087 /* run through the output dsp commands for line-out */
4088 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4089 err = dspio_set_uint_param(codec,
4090 alt_out_presets[spec->cur_out_type].mids[i],
4091 alt_out_presets[spec->cur_out_type].reqs[i],
4092 alt_out_presets[spec->cur_out_type].vals[i]);
4093
4094 if (err < 0)
4095 goto exit;
4096 }
4097
4098exit:
4099 snd_hda_power_down_pm(codec);
4100
4101 return err < 0 ? err : 0;
4102}
4103
993884f6
CCC		 4104static void ca0132_unsol_hp_delayed(struct work_struct *work)
4105{
4106 struct ca0132_spec *spec = container_of(
4107 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4108 struct hda_jack_tbl *jack;
4109
7cb9d94c
CM		 4110 if (spec->use_alt_functions)
4111 ca0132_alt_select_out(spec->codec);
4112 else
4113 ca0132_select_out(spec->codec);
4114
d5c016b5 4115 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4116 if (jack) {
4117 jack->block_report = 0;
4118 snd_hda_jack_report_sync(spec->codec);
4119 }
993884f6
CCC		 4120}
4121
5aaca44d
IM		 4122static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4123static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4124static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
e0026d03
CM		 4125static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4126static int stop_mic1(struct hda_codec *codec);
4127static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4128static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4129
4130/*
4131 * Select the active VIP source
4132 */
4133static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4134{
4135 struct ca0132_spec *spec = codec->spec;
4136 unsigned int tmp;
4137
e8f1bd5d 4138 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4139 return 0;
4140
4141 /* if CrystalVoice if off, vipsource should be 0 */
4142 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4143 (val == 0)) {
4144 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4145 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4146 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4147 if (spec->cur_mic_type == DIGITAL_MIC)
4148 tmp = FLOAT_TWO;
4149 else
4150 tmp = FLOAT_ONE;
4151 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4152 tmp = FLOAT_ZERO;
4153 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4154 } else {
4155 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4156 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4157 if (spec->cur_mic_type == DIGITAL_MIC)
4158 tmp = FLOAT_TWO;
4159 else
4160 tmp = FLOAT_ONE;
4161 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4162 tmp = FLOAT_ONE;
4163 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4164 msleep(20);
4165 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4166 }
4167
4168 return 1;
4169}
4170
e0026d03
CM		 4171static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4172{
4173 struct ca0132_spec *spec = codec->spec;
4174 unsigned int tmp;
4175
4176 if (spec->dsp_state != DSP_DOWNLOADED)
4177 return 0;
4178
4179 codec_dbg(codec, "%s\n", __func__);
4180
4181 chipio_set_stream_control(codec, 0x03, 0);
4182 chipio_set_stream_control(codec, 0x04, 0);
4183
4184 /* if CrystalVoice is off, vipsource should be 0 */
4185 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4186 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4187 codec_dbg(codec, "%s: off.", __func__);
4188 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4189
4190 tmp = FLOAT_ZERO;
4191 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4192
4193 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4194 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4195 if (spec->quirk == QUIRK_R3DI)
4196 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4197
4198
4199 if (spec->in_enum_val == REAR_LINE_IN)
4200 tmp = FLOAT_ZERO;
4201 else {
4202 if (spec->quirk == QUIRK_SBZ)
4203 tmp = FLOAT_THREE;
4204 else
4205 tmp = FLOAT_ONE;
4206 }
4207
4208 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4209
4210 } else {
4211 codec_dbg(codec, "%s: on.", __func__);
4212 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4213 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4214 if (spec->quirk == QUIRK_R3DI)
4215 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4216
4217 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4218 tmp = FLOAT_TWO;
4219 else
4220 tmp = FLOAT_ONE;
4221 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4222
4223 tmp = FLOAT_ONE;
4224 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4225
4226 msleep(20);
4227 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4228 }
4229
4230 chipio_set_stream_control(codec, 0x03, 1);
4231 chipio_set_stream_control(codec, 0x04, 1);
4232
4233 return 1;
4234}
4235
5aaca44d
IM		 4236/*
4237 * Select the active microphone.
4238 * If autodetect is enabled, mic will be selected based on jack detection.
4239 * If jack inserted, ext.mic will be selected, else built-in mic
4240 * If autodetect is disabled, mic will be selected based on selection.
4241 */
4242static int ca0132_select_mic(struct hda_codec *codec)
4243{
4244 struct ca0132_spec *spec = codec->spec;
4245 int jack_present;
4246 int auto_jack;
4247
4e76a883 4248 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4249
664c7155 4250 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4251
4252 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4253
4254 if (auto_jack)
fe14f39e 4255 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4256 else
4257 jack_present =
4258 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4259
4260 if (jack_present)
4261 spec->cur_mic_type = LINE_MIC_IN;
4262 else
4263 spec->cur_mic_type = DIGITAL_MIC;
4264
4265 if (spec->cur_mic_type == DIGITAL_MIC) {
4266 /* enable digital Mic */
4267 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4268 ca0132_set_dmic(codec, 1);
4269 ca0132_mic_boost_set(codec, 0);
4270 /* set voice focus */
4271 ca0132_effects_set(codec, VOICE_FOCUS,
4272 spec->effects_switch
4273 [VOICE_FOCUS - EFFECT_START_NID]);
4274 } else {
4275 /* disable digital Mic */
4276 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4277 ca0132_set_dmic(codec, 0);
4278 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4279 /* disable voice focus */
4280 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4281 }
4282
664c7155 4283 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4284
4285 return 0;
4286}
4287
7cb9d94c
CM		 4288/*
4289 * Select the active input.
4290 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4291 * The front mic has no jack-detection, so the only way to switch to it
4292 * is to do it manually in alsamixer.
4293 */
4294static int ca0132_alt_select_in(struct hda_codec *codec)
4295{
4296 struct ca0132_spec *spec = codec->spec;
4297 unsigned int tmp;
4298
4299 codec_dbg(codec, "%s\n", __func__);
4300
4301 snd_hda_power_up_pm(codec);
4302
4303 chipio_set_stream_control(codec, 0x03, 0);
4304 chipio_set_stream_control(codec, 0x04, 0);
4305
4306 spec->cur_mic_type = spec->in_enum_val;
4307
4308 switch (spec->cur_mic_type) {
4309 case REAR_MIC:
4310 switch (spec->quirk) {
4311 case QUIRK_SBZ:
a62e4739 4312 ca0132_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4313 tmp = FLOAT_THREE;
4314 break;
4315 case QUIRK_R3DI:
4316 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4317 tmp = FLOAT_ONE;
4318 break;
4319 default:
4320 tmp = FLOAT_ONE;
4321 break;
4322 }
4323
4324 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4325 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4326 if (spec->quirk == QUIRK_R3DI)
4327 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4328
4329 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4330
4331 chipio_set_stream_control(codec, 0x03, 1);
4332 chipio_set_stream_control(codec, 0x04, 1);
4333
4334 if (spec->quirk == QUIRK_SBZ) {
4335 chipio_write(codec, 0x18B098, 0x0000000C);
4336 chipio_write(codec, 0x18B09C, 0x0000000C);
4337 }
47cdf76e 4338 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4339 break;
4340 case REAR_LINE_IN:
4341 ca0132_mic_boost_set(codec, 0);
4342 switch (spec->quirk) {
4343 case QUIRK_SBZ:
a62e4739 4344 ca0132_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4345 break;
4346 case QUIRK_R3DI:
4347 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4348 break;
4349 }
4350
4351 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4352 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4353 if (spec->quirk == QUIRK_R3DI)
4354 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4355
4356 tmp = FLOAT_ZERO;
4357 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4358
4359 if (spec->quirk == QUIRK_SBZ) {
4360 chipio_write(codec, 0x18B098, 0x00000000);
4361 chipio_write(codec, 0x18B09C, 0x00000000);
4362 }
4363
4364 chipio_set_stream_control(codec, 0x03, 1);
4365 chipio_set_stream_control(codec, 0x04, 1);
4366 break;
4367 case FRONT_MIC:
4368 switch (spec->quirk) {
4369 case QUIRK_SBZ:
a62e4739
CM		 4370 ca0132_mmio_gpio_set(codec, 0, true);
4371 ca0132_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4372 tmp = FLOAT_THREE;
4373 break;
4374 case QUIRK_R3DI:
4375 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4376 tmp = FLOAT_ONE;
4377 break;
4378 default:
4379 tmp = FLOAT_ONE;
4380 break;
4381 }
4382
4383 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4384 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4385 if (spec->quirk == QUIRK_R3DI)
4386 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4387
4388 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4389
4390 chipio_set_stream_control(codec, 0x03, 1);
4391 chipio_set_stream_control(codec, 0x04, 1);
4392
4393 if (spec->quirk == QUIRK_SBZ) {
4394 chipio_write(codec, 0x18B098, 0x0000000C);
4395 chipio_write(codec, 0x18B09C, 0x000000CC);
4396 }
47cdf76e 4397 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4398 break;
4399 }
e0026d03 4400 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4401
4402 snd_hda_power_down_pm(codec);
4403 return 0;
4404
4405}
4406
a7e76271
IM		 4407/*
4408 * Check if VNODE settings take effect immediately.
4409 */
4410static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4411 hda_nid_t vnid,
4412 hda_nid_t *shared_nid)
4413{
4414 struct ca0132_spec *spec = codec->spec;
4415 hda_nid_t nid;
a7e76271
IM		 4416
4417 switch (vnid) {
4418 case VNID_SPK:
4419 nid = spec->shared_out_nid;
a7e76271
IM		 4420 break;
4421 case VNID_MIC:
4422 nid = spec->shared_mic_nid;
a7e76271
IM		 4423 break;
4424 default:
9a0869f4 4425 return false;
a7e76271
IM		 4426 }
4427
9a0869f4 4428 if (shared_nid)
a7e76271
IM		 4429 *shared_nid = nid;
4430
9a0869f4 4431 return true;
a7e76271
IM		 4432}
4433
4434/*
4435* The following functions are control change helpers.
4436* They return 0 if no changed. Return 1 if changed.
4437*/
4438static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4439{
4440 struct ca0132_spec *spec = codec->spec;
4441 unsigned int tmp;
4442
4443 /* based on CrystalVoice state to enable VoiceFX. */
4444 if (enable) {
4445 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4446 FLOAT_ONE : FLOAT_ZERO;
4447 } else {
4448 tmp = FLOAT_ZERO;
4449 }
4450
4451 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4452 ca0132_voicefx.reqs[0], tmp);
4453
4454 return 1;
4455}
4456
5aaca44d
IM		 4457/*
4458 * Set the effects parameters
4459 */
4460static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4461{
4462 struct ca0132_spec *spec = codec->spec;
009b8f97 4463 unsigned int on, tmp;
5aaca44d
IM		 4464 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4465 int err = 0;
4466 int idx = nid - EFFECT_START_NID;
4467
4468 if ((idx < 0) || (idx >= num_fx))
4469 return 0; /* no changed */
4470
4471 /* for out effect, qualify with PE */
4472 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4473 /* if PE if off, turn off out effects. */
4474 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4475 val = 0;
4476 }
4477
4478 /* for in effect, qualify with CrystalVoice */
4479 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4480 /* if CrystalVoice if off, turn off in effects. */
4481 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4482 val = 0;
4483
4484 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4485 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4486 val = 0;
009b8f97
CM		 4487
4488 /* If Voice Focus on SBZ, set to two channel. */
7cb9d94c
CM		 4489 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4490 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4491 if (spec->effects_switch[CRYSTAL_VOICE -
4492 EFFECT_START_NID]) {
4493
4494 if (spec->effects_switch[VOICE_FOCUS -
4495 EFFECT_START_NID]) {
4496 tmp = FLOAT_TWO;
4497 val = 1;
4498 } else
4499 tmp = FLOAT_ONE;
4500
4501 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4502 }
4503 }
4504 /*
4505 * For SBZ noise reduction, there's an extra command
4506 * to module ID 0x47. No clue why.
4507 */
7cb9d94c
CM		 4508 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4509 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4510 if (spec->effects_switch[CRYSTAL_VOICE -
4511 EFFECT_START_NID]) {
4512 if (spec->effects_switch[NOISE_REDUCTION -
4513 EFFECT_START_NID])
4514 tmp = FLOAT_ONE;
4515 else
4516 tmp = FLOAT_ZERO;
4517 } else
4518 tmp = FLOAT_ZERO;
4519
4520 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4521 }
7cb9d94c
CM		 4522
4523 /* If rear line in disable effects. */
4524 if (spec->use_alt_functions &&
4525 spec->in_enum_val == REAR_LINE_IN)
4526 val = 0;
5aaca44d
IM		 4527 }
4528
4e76a883 4529 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4530 nid, val);
4531
4532 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4533 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4534 ca0132_effects[idx].reqs[0], on);
4535
4536 if (err < 0)
4537 return 0; /* no changed */
4538
4539 return 1;
4540}
4541
a7e76271
IM		 4542/*
4543 * Turn on/off Playback Enhancements
4544 */
4545static int ca0132_pe_switch_set(struct hda_codec *codec)
4546{
4547 struct ca0132_spec *spec = codec->spec;
4548 hda_nid_t nid;
4549 int i, ret = 0;
4550
4e76a883 4551 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4552 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4553
7cb9d94c
CM		 4554 if (spec->use_alt_functions)
4555 ca0132_alt_select_out(codec);
4556
a7e76271
IM		 4557 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4558 nid = OUT_EFFECT_START_NID;
4559 /* PE affects all out effects */
4560 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4561 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4562
4563 return ret;
4564}
4565
5aaca44d
IM		 4566/* Check if Mic1 is streaming, if so, stop streaming */
4567static int stop_mic1(struct hda_codec *codec)
4568{
4569 struct ca0132_spec *spec = codec->spec;
4570 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4571 AC_VERB_GET_CONV, 0);
4572 if (oldval != 0)
4573 snd_hda_codec_write(codec, spec->adcs[0], 0,
4574 AC_VERB_SET_CHANNEL_STREAMID,
4575 0);
4576 return oldval;
4577}
4578
4579/* Resume Mic1 streaming if it was stopped. */
4580static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4581{
4582 struct ca0132_spec *spec = codec->spec;
4583 /* Restore the previous stream and channel */
4584 if (oldval != 0)
4585 snd_hda_codec_write(codec, spec->adcs[0], 0,
4586 AC_VERB_SET_CHANNEL_STREAMID,
4587 oldval);
4588}
4589
4590/*
a7e76271 4591 * Turn on/off CrystalVoice
5aaca44d 4592 */
a7e76271
IM		 4593static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4594{
4595 struct ca0132_spec *spec = codec->spec;
4596 hda_nid_t nid;
4597 int i, ret = 0;
4598 unsigned int oldval;
4599
4e76a883 4600 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4601 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4602
4603 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4604 nid = IN_EFFECT_START_NID;
4605 /* CrystalVoice affects all in effects */
4606 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4607 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4608
4609 /* including VoiceFX */
4610 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4611
4612 /* set correct vipsource */
4613 oldval = stop_mic1(codec);
e0026d03
CM		 4614 if (spec->use_alt_functions)
4615 ret |= ca0132_alt_set_vipsource(codec, 1);
4616 else
4617 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 4618 resume_mic1(codec, oldval);
4619 return ret;
4620}
4621
5aaca44d
IM		 4622static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4623{
4624 struct ca0132_spec *spec = codec->spec;
4625 int ret = 0;
4626
4627 if (val) /* on */
4628 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4629 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4630 else /* off */
4631 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4632 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4633
4634 return ret;
4635}
4636
47cdf76e
CM		 4637static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4638{
4639 struct ca0132_spec *spec = codec->spec;
4640 int ret = 0;
4641
4642 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4643 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4644 return ret;
4645}
4646
a7e76271
IM		 4647static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4648 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 4649{
a7e76271
IM		 4650 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4651 hda_nid_t nid = get_amp_nid(kcontrol);
4652 hda_nid_t shared_nid = 0;
4653 bool effective;
4654 int ret = 0;
95c6e9cb 4655 struct ca0132_spec *spec = codec->spec;
a7e76271 4656 int auto_jack;
95c6e9cb 4657
a7e76271
IM		 4658 if (nid == VNID_HP_SEL) {
4659 auto_jack =
4660 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 4661 if (!auto_jack) {
4662 if (spec->use_alt_functions)
4663 ca0132_alt_select_out(codec);
4664 else
4665 ca0132_select_out(codec);
4666 }
a7e76271
IM		 4667 return 1;
4668 }
95c6e9cb 4669
a7e76271
IM		 4670 if (nid == VNID_AMIC1_SEL) {
4671 auto_jack =
4672 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4673 if (!auto_jack)
4674 ca0132_select_mic(codec);
4675 return 1;
4676 }
95c6e9cb 4677
a7e76271 4678 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 4679 if (spec->use_alt_functions)
4680 ca0132_alt_select_out(codec);
4681 else
4682 ca0132_select_out(codec);
a7e76271
IM		 4683 return 1;
4684 }
95c6e9cb 4685
a7e76271
IM		 4686 if (nid == VNID_AMIC1_ASEL) {
4687 ca0132_select_mic(codec);
4688 return 1;
95c6e9cb 4689 }
a7e76271
IM		 4690
4691 /* if effective conditions, then update hw immediately. */
4692 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4693 if (effective) {
4694 int dir = get_amp_direction(kcontrol);
4695 int ch = get_amp_channels(kcontrol);
4696 unsigned long pval;
4697
4698 mutex_lock(&codec->control_mutex);
4699 pval = kcontrol->private_value;
4700 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4701 0, dir);
4702 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4703 kcontrol->private_value = pval;
4704 mutex_unlock(&codec->control_mutex);
95c6e9cb 4705 }
95c6e9cb 4706
a7e76271 4707 return ret;
95c6e9cb 4708}
a7e76271 4709/* End of control change helpers. */
47cdf76e
CM		 4710/*
4711 * Below I've added controls to mess with the effect levels, I've only enabled
4712 * them on the Sound Blaster Z, but they would probably also work on the
4713 * Chromebook. I figured they were probably tuned specifically for it, and left
4714 * out for a reason.
4715 */
4716
4717/* Sets DSP effect level from the sliders above the controls */
4718static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4719 const unsigned int *lookup, int idx)
4720{
4721 int i = 0;
4722 unsigned int y;
4723 /*
4724 * For X_BASS, req 2 is actually crossover freq instead of
4725 * effect level
4726 */
4727 if (nid == X_BASS)
4728 y = 2;
4729 else
4730 y = 1;
4731
4732 snd_hda_power_up(codec);
4733 if (nid == XBASS_XOVER) {
4734 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4735 if (ca0132_effects[i].nid == X_BASS)
4736 break;
4737
4738 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4739 ca0132_effects[i].reqs[1],
4740 &(lookup[idx - 1]), sizeof(unsigned int));
4741 } else {
4742 /* Find the actual effect structure */
4743 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4744 if (nid == ca0132_effects[i].nid)
4745 break;
4746
4747 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4748 ca0132_effects[i].reqs[y],
4749 &(lookup[idx]), sizeof(unsigned int));
4750 }
4751
4752 snd_hda_power_down(codec);
4753
4754 return 0;
4755}
4756
4757static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4758 struct snd_ctl_elem_value *ucontrol)
4759{
4760 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4761 struct ca0132_spec *spec = codec->spec;
4762 long *valp = ucontrol->value.integer.value;
4763
4764 *valp = spec->xbass_xover_freq;
4765 return 0;
4766}
4767
4768static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4769 struct snd_ctl_elem_value *ucontrol)
4770{
4771 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4772 struct ca0132_spec *spec = codec->spec;
4773 hda_nid_t nid = get_amp_nid(kcontrol);
4774 long *valp = ucontrol->value.integer.value;
4775 int idx = nid - OUT_EFFECT_START_NID;
4776
4777 *valp = spec->fx_ctl_val[idx];
4778 return 0;
4779}
4780
4781/*
4782 * The X-bass crossover starts at 10hz, so the min is 1. The
4783 * frequency is set in multiples of 10.
4784 */
4785static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4786 struct snd_ctl_elem_info *uinfo)
4787{
4788 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4789 uinfo->count = 1;
4790 uinfo->value.integer.min = 1;
4791 uinfo->value.integer.max = 100;
4792 uinfo->value.integer.step = 1;
4793
4794 return 0;
4795}
4796
4797static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4798 struct snd_ctl_elem_info *uinfo)
4799{
4800 int chs = get_amp_channels(kcontrol);
4801
4802 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4803 uinfo->count = chs == 3 ? 2 : 1;
4804 uinfo->value.integer.min = 0;
4805 uinfo->value.integer.max = 100;
4806 uinfo->value.integer.step = 1;
4807
4808 return 0;
4809}
4810
4811static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4812 struct snd_ctl_elem_value *ucontrol)
4813{
4814 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4815 struct ca0132_spec *spec = codec->spec;
4816 hda_nid_t nid = get_amp_nid(kcontrol);
4817 long *valp = ucontrol->value.integer.value;
4818 int idx;
4819
4820 /* any change? */
4821 if (spec->xbass_xover_freq == *valp)
4822 return 0;
4823
4824 spec->xbass_xover_freq = *valp;
4825
4826 idx = *valp;
4827 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4828
4829 return 0;
4830}
4831
4832static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4833 struct snd_ctl_elem_value *ucontrol)
4834{
4835 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4836 struct ca0132_spec *spec = codec->spec;
4837 hda_nid_t nid = get_amp_nid(kcontrol);
4838 long *valp = ucontrol->value.integer.value;
4839 int idx;
4840
4841 idx = nid - EFFECT_START_NID;
4842 /* any change? */
4843 if (spec->fx_ctl_val[idx] == *valp)
4844 return 0;
4845
4846 spec->fx_ctl_val[idx] = *valp;
4847
4848 idx = *valp;
4849 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4850
4851 return 0;
4852}
4853
4854
4855/*
4856 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4857 * only has off or full 30 dB, and didn't like making a volume slider that has
4858 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4859 */
4860#define MIC_BOOST_NUM_OF_STEPS 4
4861#define MIC_BOOST_ENUM_MAX_STRLEN 10
4862
4863static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4864 struct snd_ctl_elem_info *uinfo)
4865{
4866 char *sfx = "dB";
4867 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4868
4869 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4870 uinfo->count = 1;
4871 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
4872 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
4873 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
4874 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
4875 strcpy(uinfo->value.enumerated.name, namestr);
4876 return 0;
4877}
4878
4879static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
4880 struct snd_ctl_elem_value *ucontrol)
4881{
4882 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4883 struct ca0132_spec *spec = codec->spec;
4884
4885 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
4886 return 0;
4887}
4888
4889static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
4890 struct snd_ctl_elem_value *ucontrol)
4891{
4892 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4893 struct ca0132_spec *spec = codec->spec;
4894 int sel = ucontrol->value.enumerated.item[0];
4895 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
4896
4897 if (sel >= items)
4898 return 0;
4899
4900 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
4901 sel);
4902
4903 spec->mic_boost_enum_val = sel;
4904
4905 if (spec->in_enum_val != REAR_LINE_IN)
4906 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4907
4908 return 1;
4909}
4910
95c6e9cb 4911
7cb9d94c
CM		 4912/*
4913 * Input Select Control for alternative ca0132 codecs. This exists because
4914 * front microphone has no auto-detect, and we need a way to set the rear
4915 * as line-in
4916 */
4917static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4918 struct snd_ctl_elem_info *uinfo)
4919{
4920 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4921 uinfo->count = 1;
4922 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4923 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4924 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4925 strcpy(uinfo->value.enumerated.name,
4926 in_src_str[uinfo->value.enumerated.item]);
4927 return 0;
4928}
4929
4930static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4931 struct snd_ctl_elem_value *ucontrol)
4932{
4933 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4934 struct ca0132_spec *spec = codec->spec;
4935
4936 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4937 return 0;
4938}
4939
4940static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4941 struct snd_ctl_elem_value *ucontrol)
4942{
4943 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4944 struct ca0132_spec *spec = codec->spec;
4945 int sel = ucontrol->value.enumerated.item[0];
4946 unsigned int items = IN_SRC_NUM_OF_INPUTS;
4947
4948 if (sel >= items)
4949 return 0;
4950
4951 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4952 sel, in_src_str[sel]);
4953
4954 spec->in_enum_val = sel;
4955
4956 ca0132_alt_select_in(codec);
4957
4958 return 1;
4959}
4960
4961/* Sound Blaster Z Output Select Control */
4962static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
4963 struct snd_ctl_elem_info *uinfo)
4964{
4965 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4966 uinfo->count = 1;
4967 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
4968 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
4969 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
4970 strcpy(uinfo->value.enumerated.name,
4971 alt_out_presets[uinfo->value.enumerated.item].name);
4972 return 0;
4973}
4974
4975static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
4976 struct snd_ctl_elem_value *ucontrol)
4977{
4978 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4979 struct ca0132_spec *spec = codec->spec;
4980
4981 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
4982 return 0;
4983}
4984
4985static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
4986 struct snd_ctl_elem_value *ucontrol)
4987{
4988 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4989 struct ca0132_spec *spec = codec->spec;
4990 int sel = ucontrol->value.enumerated.item[0];
4991 unsigned int items = NUM_OF_OUTPUTS;
4992 unsigned int auto_jack;
4993
4994 if (sel >= items)
4995 return 0;
4996
4997 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
4998 sel, alt_out_presets[sel].name);
4999
5000 spec->out_enum_val = sel;
5001
5002 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5003
5004 if (!auto_jack)
5005 ca0132_alt_select_out(codec);
5006
5007 return 1;
5008}
5009
47cdf76e
CM		 5010/*
5011 * Smart Volume output setting control. Three different settings, Normal,
5012 * which takes the value from the smart volume slider. The two others, loud
5013 * and night, disregard the slider value and have uneditable values.
5014 */
5015#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5016static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5017
5018static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5019 struct snd_ctl_elem_info *uinfo)
5020{
5021 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5022 uinfo->count = 1;
5023 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5024 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5025 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5026 strcpy(uinfo->value.enumerated.name,
5027 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5028 return 0;
5029}
5030
5031static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5032 struct snd_ctl_elem_value *ucontrol)
5033{
5034 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5035 struct ca0132_spec *spec = codec->spec;
5036
5037 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5038 return 0;
5039}
5040
5041static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5042 struct snd_ctl_elem_value *ucontrol)
5043{
5044 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5045 struct ca0132_spec *spec = codec->spec;
5046 int sel = ucontrol->value.enumerated.item[0];
5047 unsigned int items = NUM_OF_SVM_SETTINGS;
5048 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5049 unsigned int tmp;
5050
5051 if (sel >= items)
5052 return 0;
5053
5054 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5055 sel, out_svm_set_enum_str[sel]);
5056
5057 spec->smart_volume_setting = sel;
5058
5059 switch (sel) {
5060 case 0:
5061 tmp = FLOAT_ZERO;
5062 break;
5063 case 1:
5064 tmp = FLOAT_ONE;
5065 break;
5066 case 2:
5067 tmp = FLOAT_TWO;
5068 break;
5069 default:
5070 tmp = FLOAT_ZERO;
5071 break;
5072 }
5073 /* Req 2 is the Smart Volume Setting req. */
5074 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5075 ca0132_effects[idx].reqs[2], tmp);
5076 return 1;
5077}
5078
5079/* Sound Blaster Z EQ preset controls */
5080static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5081 struct snd_ctl_elem_info *uinfo)
5082{
c5f13d75 5083 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5084
5085 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5086 uinfo->count = 1;
5087 uinfo->value.enumerated.items = items;
5088 if (uinfo->value.enumerated.item >= items)
5089 uinfo->value.enumerated.item = items - 1;
5090 strcpy(uinfo->value.enumerated.name,
5091 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5092 return 0;
5093}
5094
5095static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5096 struct snd_ctl_elem_value *ucontrol)
5097{
5098 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5099 struct ca0132_spec *spec = codec->spec;
5100
5101 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5102 return 0;
5103}
5104
5105static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5106 struct snd_ctl_elem_value *ucontrol)
5107{
5108 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5109 struct ca0132_spec *spec = codec->spec;
5110 int i, err = 0;
5111 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5112 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5113
5114 if (sel >= items)
5115 return 0;
5116
5117 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5118 ca0132_alt_eq_presets[sel].name);
5119 /*
5120 * Idx 0 is default.
5121 * Default needs to qualify with CrystalVoice state.
5122 */
5123 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5124 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5125 ca0132_alt_eq_enum.reqs[i],
5126 ca0132_alt_eq_presets[sel].vals[i]);
5127 if (err < 0)
5128 break;
5129 }
5130
5131 if (err >= 0)
5132 spec->eq_preset_val = sel;
5133
5134 return 1;
5135}
5136
a7e76271
IM		 5137static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5138 struct snd_ctl_elem_info *uinfo)
5139{
a9291f46 5140 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5141
5142 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5143 uinfo->count = 1;
5144 uinfo->value.enumerated.items = items;
5145 if (uinfo->value.enumerated.item >= items)
5146 uinfo->value.enumerated.item = items - 1;
5147 strcpy(uinfo->value.enumerated.name,
5148 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5149 return 0;
5150}
95c6e9cb 5151
a7e76271 5152static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5153 struct snd_ctl_elem_value *ucontrol)
5154{
5155 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5156 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5157
a7e76271 5158 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5159 return 0;
5160}
5161
a7e76271 5162static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5163 struct snd_ctl_elem_value *ucontrol)
5164{
5165 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5166 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5167 int i, err = 0;
5168 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5169
a9291f46 5170 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5171 return 0;
5172
4e76a883 5173 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5174 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5175
a7e76271
IM		 5176 /*
5177 * Idx 0 is default.
5178 * Default needs to qualify with CrystalVoice state.
5179 */
5180 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5181 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5182 ca0132_voicefx.reqs[i],
5183 ca0132_voicefx_presets[sel].vals[i]);
5184 if (err < 0)
5185 break;
5186 }
95c6e9cb 5187
a7e76271
IM		 5188 if (err >= 0) {
5189 spec->voicefx_val = sel;
5190 /* enable voice fx */
5191 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5192 }
95c6e9cb 5193
a7e76271 5194 return 1;
95c6e9cb
IM		 5195}
5196
a7e76271
IM		 5197static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5198 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5199{
5200 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5201 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5202 hda_nid_t nid = get_amp_nid(kcontrol);
5203 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5204 long *valp = ucontrol->value.integer.value;
5205
a7e76271
IM		 5206 /* vnode */
5207 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5208 if (ch & 1) {
5209 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5210 valp++;
5211 }
5212 if (ch & 2) {
5213 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5214 valp++;
5215 }
5216 return 0;
5217 }
5218
5219 /* effects, include PE and CrystalVoice */
5220 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5221 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5222 return 0;
5223 }
5224
5225 /* mic boost */
5226 if (nid == spec->input_pins[0]) {
5227 *valp = spec->cur_mic_boost;
5228 return 0;
5229 }
5230
95c6e9cb
IM		 5231 return 0;
5232}
5233
a7e76271
IM		 5234static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5235 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5236{
5237 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5238 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5239 hda_nid_t nid = get_amp_nid(kcontrol);
5240 int ch = get_amp_channels(kcontrol);
95c6e9cb 5241 long *valp = ucontrol->value.integer.value;
a7e76271 5242 int changed = 1;
95c6e9cb 5243
4e76a883 5244 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5245 nid, *valp);
95c6e9cb
IM		 5246
5247 snd_hda_power_up(codec);
a7e76271
IM		 5248 /* vnode */
5249 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5250 if (ch & 1) {
5251 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5252 valp++;
5253 }
5254 if (ch & 2) {
5255 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5256 valp++;
5257 }
5258 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5259 goto exit;
5260 }
95c6e9cb 5261
a7e76271
IM		 5262 /* PE */
5263 if (nid == PLAY_ENHANCEMENT) {
5264 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5265 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5266 goto exit;
a7e76271 5267 }
95c6e9cb 5268
a7e76271
IM		 5269 /* CrystalVoice */
5270 if (nid == CRYSTAL_VOICE) {
5271 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5272 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5273 goto exit;
a7e76271 5274 }
95c6e9cb 5275
a7e76271
IM		 5276 /* out and in effects */
5277 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5278 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5279 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5280 changed = ca0132_effects_set(codec, nid, *valp);
5281 goto exit;
5282 }
5283
5284 /* mic boost */
5285 if (nid == spec->input_pins[0]) {
5286 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 5287 if (spec->use_alt_functions) {
5288 if (spec->in_enum_val != REAR_LINE_IN)
5289 changed = ca0132_mic_boost_set(codec, *valp);
5290 } else {
5291 /* Mic boost does not apply to Digital Mic */
5292 if (spec->cur_mic_type != DIGITAL_MIC)
5293 changed = ca0132_mic_boost_set(codec, *valp);
5294 }
a7e76271 5295
a7e76271
IM		 5296 goto exit;
5297 }
95c6e9cb 5298
a7e76271 5299exit:
95c6e9cb 5300 snd_hda_power_down(codec);
a7e76271 5301 return changed;
95c6e9cb
IM		 5302}
5303
a7e76271
IM		 5304/*
5305 * Volume related
5306 */
017310fb
CM		 5307/*
5308 * Sets the internal DSP decibel level to match the DAC for output, and the
5309 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5310 * all alternative codecs set DSP playback volume.
5311 */
5312static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5313{
5314 struct ca0132_spec *spec = codec->spec;
5315 unsigned int dsp_dir;
5316 unsigned int lookup_val;
5317
5318 if (nid == VNID_SPK)
5319 dsp_dir = DSP_VOL_OUT;
5320 else
5321 dsp_dir = DSP_VOL_IN;
5322
5323 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5324
5325 dspio_set_uint_param(codec,
5326 ca0132_alt_vol_ctls[dsp_dir].mid,
5327 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5328 float_vol_db_lookup[lookup_val]);
5329
5330 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5331
5332 dspio_set_uint_param(codec,
5333 ca0132_alt_vol_ctls[dsp_dir].mid,
5334 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5335 float_vol_db_lookup[lookup_val]);
5336
5337 dspio_set_uint_param(codec,
5338 ca0132_alt_vol_ctls[dsp_dir].mid,
5339 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5340}
5341
a7e76271
IM		 5342static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5343 struct snd_ctl_elem_info *uinfo)
5344{
5345 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5346 struct ca0132_spec *spec = codec->spec;
5347 hda_nid_t nid = get_amp_nid(kcontrol);
5348 int ch = get_amp_channels(kcontrol);
5349 int dir = get_amp_direction(kcontrol);
5350 unsigned long pval;
5351 int err;
5352
5353 switch (nid) {
5354 case VNID_SPK:
5355 /* follow shared_out info */
5356 nid = spec->shared_out_nid;
5357 mutex_lock(&codec->control_mutex);
5358 pval = kcontrol->private_value;
5359 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5360 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5361 kcontrol->private_value = pval;
5362 mutex_unlock(&codec->control_mutex);
5363 break;
5364 case VNID_MIC:
5365 /* follow shared_mic info */
5366 nid = spec->shared_mic_nid;
5367 mutex_lock(&codec->control_mutex);
5368 pval = kcontrol->private_value;
5369 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5370 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5371 kcontrol->private_value = pval;
5372 mutex_unlock(&codec->control_mutex);
5373 break;
5374 default:
5375 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5376 }
5377 return err;
5378}
5379
5380static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5381 struct snd_ctl_elem_value *ucontrol)
5382{
5383 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5384 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5385 hda_nid_t nid = get_amp_nid(kcontrol);
5386 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5387 long *valp = ucontrol->value.integer.value;
5388
a7e76271
IM		 5389 /* store the left and right volume */
5390 if (ch & 1) {
5391 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5392 valp++;
5393 }
5394 if (ch & 2) {
5395 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5396 valp++;
5397 }
95c6e9cb
IM		 5398 return 0;
5399}
5400
a7e76271 5401static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5402 struct snd_ctl_elem_value *ucontrol)
5403{
5404 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5405 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5406 hda_nid_t nid = get_amp_nid(kcontrol);
5407 int ch = get_amp_channels(kcontrol);
95c6e9cb 5408 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5409 hda_nid_t shared_nid = 0;
5410 bool effective;
5411 int changed = 1;
5412
5413 /* store the left and right volume */
5414 if (ch & 1) {
5415 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5416 valp++;
5417 }
5418 if (ch & 2) {
5419 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5420 valp++;
5421 }
95c6e9cb 5422
a7e76271
IM		 5423 /* if effective conditions, then update hw immediately. */
5424 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5425 if (effective) {
5426 int dir = get_amp_direction(kcontrol);
5427 unsigned long pval;
5428
5429 snd_hda_power_up(codec);
5430 mutex_lock(&codec->control_mutex);
5431 pval = kcontrol->private_value;
5432 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5433 0, dir);
5434 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5435 kcontrol->private_value = pval;
5436 mutex_unlock(&codec->control_mutex);
5437 snd_hda_power_down(codec);
5438 }
95c6e9cb 5439
a7e76271 5440 return changed;
95c6e9cb
IM		 5441}
5442
017310fb
CM		 5443/*
5444 * This function is the same as the one above, because using an if statement
5445 * inside of the above volume control for the DSP volume would cause too much
5446 * lag. This is a lot more smooth.
5447 */
5448static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5449 struct snd_ctl_elem_value *ucontrol)
5450{
5451 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5452 struct ca0132_spec *spec = codec->spec;
5453 hda_nid_t nid = get_amp_nid(kcontrol);
5454 int ch = get_amp_channels(kcontrol);
5455 long *valp = ucontrol->value.integer.value;
5456 hda_nid_t vnid = 0;
5457 int changed = 1;
5458
5459 switch (nid) {
5460 case 0x02:
5461 vnid = VNID_SPK;
5462 break;
5463 case 0x07:
5464 vnid = VNID_MIC;
5465 break;
5466 }
5467
5468 /* store the left and right volume */
5469 if (ch & 1) {
5470 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5471 valp++;
5472 }
5473 if (ch & 2) {
5474 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5475 valp++;
5476 }
5477
5478 snd_hda_power_up(codec);
5479 ca0132_alt_dsp_volume_put(codec, vnid);
5480 mutex_lock(&codec->control_mutex);
5481 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5482 mutex_unlock(&codec->control_mutex);
5483 snd_hda_power_down(codec);
5484
5485 return changed;
5486}
5487
a7e76271
IM		 5488static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5489 unsigned int size, unsigned int __user *tlv)
95c6e9cb 5490{
a7e76271
IM		 5491 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5492 struct ca0132_spec *spec = codec->spec;
5493 hda_nid_t nid = get_amp_nid(kcontrol);
5494 int ch = get_amp_channels(kcontrol);
5495 int dir = get_amp_direction(kcontrol);
5496 unsigned long pval;
5497 int err;
5498
5499 switch (nid) {
5500 case VNID_SPK:
5501 /* follow shared_out tlv */
5502 nid = spec->shared_out_nid;
5503 mutex_lock(&codec->control_mutex);
5504 pval = kcontrol->private_value;
5505 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5506 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5507 kcontrol->private_value = pval;
5508 mutex_unlock(&codec->control_mutex);
5509 break;
5510 case VNID_MIC:
5511 /* follow shared_mic tlv */
5512 nid = spec->shared_mic_nid;
5513 mutex_lock(&codec->control_mutex);
5514 pval = kcontrol->private_value;
5515 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5516 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5517 kcontrol->private_value = pval;
5518 mutex_unlock(&codec->control_mutex);
5519 break;
5520 default:
5521 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5522 }
5523 return err;
95c6e9cb
IM		 5524}
5525
47cdf76e
CM		 5526/* Add volume slider control for effect level */
5527static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5528 const char *pfx, int dir)
5529{
47cdf76e
CM		 5530 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5531 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5532 struct snd_kcontrol_new knew =
5533 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5534
0cc1aa71 5535 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 5536
bb86124c 5537 knew.tlv.c = NULL;
47cdf76e
CM		 5538
5539 switch (nid) {
5540 case XBASS_XOVER:
5541 knew.info = ca0132_alt_xbass_xover_slider_info;
5542 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5543 knew.put = ca0132_alt_xbass_xover_slider_put;
5544 break;
5545 default:
5546 knew.info = ca0132_alt_effect_slider_info;
5547 knew.get = ca0132_alt_slider_ctl_get;
5548 knew.put = ca0132_alt_effect_slider_put;
5549 knew.private_value =
5550 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5551 break;
5552 }
5553
5554 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5555}
5556
5557/*
5558 * Added FX: prefix for the alternative codecs, because otherwise the surround
5559 * effect would conflict with the Surround sound volume control. Also seems more
5560 * clear as to what the switches do. Left alone for others.
5561 */
a7e76271
IM		 5562static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5563 const char *pfx, int dir)
95c6e9cb 5564{
47cdf76e 5565 struct ca0132_spec *spec = codec->spec;
975cc02a 5566 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 5567 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 5568 struct snd_kcontrol_new knew =
a7e76271 5569 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 5570 /* If using alt_controls, add FX: prefix. But, don't add FX:
5571 * prefix to OutFX or InFX enable controls.
5572 */
5573 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 5574 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 5575 else
5576 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5577
95c6e9cb
IM		 5578 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5579}
5580
a7e76271 5581static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 5582{
5583 struct snd_kcontrol_new knew =
a7e76271
IM		 5584 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5585 VOICEFX, 1, 0, HDA_INPUT);
5586 knew.info = ca0132_voicefx_info;
5587 knew.get = ca0132_voicefx_get;
5588 knew.put = ca0132_voicefx_put;
5589 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 5590}
5591
47cdf76e
CM		 5592/* Create the EQ Preset control */
5593static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5594{
5595 struct snd_kcontrol_new knew =
5596 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5597 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5598 knew.info = ca0132_alt_eq_preset_info;
5599 knew.get = ca0132_alt_eq_preset_get;
5600 knew.put = ca0132_alt_eq_preset_put;
5601 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5602 snd_ctl_new1(&knew, codec));
5603}
5604
5605/*
5606 * Add enumerated control for the three different settings of the smart volume
5607 * output effect. Normal just uses the slider value, and loud and night are
5608 * their own things that ignore that value.
5609 */
5610static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5611{
5612 struct snd_kcontrol_new knew =
5613 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5614 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5615 knew.info = ca0132_alt_svm_setting_info;
5616 knew.get = ca0132_alt_svm_setting_get;
5617 knew.put = ca0132_alt_svm_setting_put;
5618 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5619 snd_ctl_new1(&knew, codec));
5620
5621}
5622
7cb9d94c
CM		 5623/*
5624 * Create an Output Select enumerated control for codecs with surround
5625 * out capabilities.
5626 */
5627static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5628{
5629 struct snd_kcontrol_new knew =
5630 HDA_CODEC_MUTE_MONO("Output Select",
5631 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5632 knew.info = ca0132_alt_output_select_get_info;
5633 knew.get = ca0132_alt_output_select_get;
5634 knew.put = ca0132_alt_output_select_put;
5635 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5636 snd_ctl_new1(&knew, codec));
5637}
5638
5639/*
5640 * Create an Input Source enumerated control for the alternate ca0132 codecs
5641 * because the front microphone has no auto-detect, and Line-in has to be set
5642 * somehow.
5643 */
5644static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5645{
5646 struct snd_kcontrol_new knew =
5647 HDA_CODEC_MUTE_MONO("Input Source",
5648 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5649 knew.info = ca0132_alt_input_source_info;
5650 knew.get = ca0132_alt_input_source_get;
5651 knew.put = ca0132_alt_input_source_put;
5652 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5653 snd_ctl_new1(&knew, codec));
5654}
5655
47cdf76e
CM		 5656/*
5657 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5658 * more control than the original mic boost, which is either full 30dB or off.
5659 */
5660static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5661{
5662 struct snd_kcontrol_new knew =
5663 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5664 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5665 knew.info = ca0132_alt_mic_boost_info;
5666 knew.get = ca0132_alt_mic_boost_get;
5667 knew.put = ca0132_alt_mic_boost_put;
5668 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5669 snd_ctl_new1(&knew, codec));
5670
5671}
5672
5673/*
5674 * Need to create slave controls for the alternate codecs that have surround
5675 * capabilities.
5676 */
5677static const char * const ca0132_alt_slave_pfxs[] = {
5678 "Front", "Surround", "Center", "LFE", NULL,
5679};
5680
5681/*
5682 * Also need special channel map, because the default one is incorrect.
5683 * I think this has to do with the pin for rear surround being 0x11,
5684 * and the center/lfe being 0x10. Usually the pin order is the opposite.
5685 */
9c4a665e 5686static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 5687 { .channels = 2,
5688 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5689 { .channels = 4,
5690 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5691 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5692 { .channels = 6,
5693 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5694 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5695 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5696 { }
5697};
5698
5699/* Add the correct chmap for streams with 6 channels. */
5700static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5701{
5702 int err = 0;
5703 struct hda_pcm *pcm;
5704
5705 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5706 struct hda_pcm_stream *hinfo =
5707 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5708 struct snd_pcm_chmap *chmap;
5709 const struct snd_pcm_chmap_elem *elem;
5710
5711 elem = ca0132_alt_chmaps;
5712 if (hinfo->channels_max == 6) {
5713 err = snd_pcm_add_chmap_ctls(pcm->pcm,
5714 SNDRV_PCM_STREAM_PLAYBACK,
5715 elem, hinfo->channels_max, 0, &chmap);
5716 if (err < 0)
5717 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5718 }
5719 }
5720}
5721
a7e76271
IM		 5722/*
5723 * When changing Node IDs for Mixer Controls below, make sure to update
5724 * Node IDs in ca0132_config() as well.
5725 */
b0eaa072 5726static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 5727 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5728 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5729 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5730 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5731 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5732 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5733 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5734 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5735 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5736 0x12, 1, HDA_INPUT),
5737 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5738 VNID_HP_SEL, 1, HDA_OUTPUT),
5739 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5740 VNID_AMIC1_SEL, 1, HDA_INPUT),
5741 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5742 VNID_HP_ASEL, 1, HDA_OUTPUT),
5743 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5744 VNID_AMIC1_ASEL, 1, HDA_INPUT),
5745 { } /* end */
5746};
5747
017310fb
CM		 5748/*
5749 * SBZ specific control mixer. Removes auto-detect for mic, and adds surround
5750 * controls. Also sets both the Front Playback and Capture Volume controls to
5751 * alt so they set the DSP's decibel level.
5752 */
b0eaa072 5753static const struct snd_kcontrol_new sbz_mixer[] = {
017310fb
CM		 5754 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5755 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5756 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5757 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5758 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5759 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5760 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5761 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5762 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5763 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5764 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5765 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5766 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5767 VNID_HP_ASEL, 1, HDA_OUTPUT),
5768 { } /* end */
5769};
5770
5771/*
5772 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5773 * because it doesn't set decibel levels for the DSP for capture.
5774 */
b0eaa072 5775static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 5776 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5777 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5778 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5779 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5780 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5781 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5782 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5783 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5784 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5785 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5786 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5787 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5788 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5789 VNID_HP_ASEL, 1, HDA_OUTPUT),
5790 { } /* end */
5791};
5792
e90f29e4
IM		 5793static int ca0132_build_controls(struct hda_codec *codec)
5794{
5795 struct ca0132_spec *spec = codec->spec;
47cdf76e 5796 int i, num_fx, num_sliders;
e90f29e4
IM		 5797 int err = 0;
5798
5799 /* Add Mixer controls */
5800 for (i = 0; i < spec->num_mixers; i++) {
5801 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5802 if (err < 0)
5803 return err;
5804 }
47cdf76e
CM		 5805 /* Setup vmaster with surround slaves for desktop ca0132 devices */
5806 if (spec->use_alt_functions) {
5807 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5808 spec->tlv);
5809 snd_hda_add_vmaster(codec, "Master Playback Volume",
5810 spec->tlv, ca0132_alt_slave_pfxs,
5811 "Playback Volume");
5812 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5813 NULL, ca0132_alt_slave_pfxs,
5814 "Playback Switch",
5815 true, &spec->vmaster_mute.sw_kctl);
5816
5817 }
e90f29e4
IM		 5818
5819 /* Add in and out effects controls.
5820 * VoiceFX, PE and CrystalVoice are added separately.
5821 */
5822 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5823 for (i = 0; i < num_fx; i++) {
47cdf76e
CM		 5824 /* SBZ breaks if Echo Cancellation is used */
5825 if (spec->quirk == QUIRK_SBZ) {
5826 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5827 OUT_EFFECTS_COUNT))
5828 continue;
5829 }
5830
e90f29e4
IM		 5831 err = add_fx_switch(codec, ca0132_effects[i].nid,
5832 ca0132_effects[i].name,
5833 ca0132_effects[i].direct);
5834 if (err < 0)
5835 return err;
5836 }
47cdf76e
CM		 5837 /*
5838 * If codec has use_alt_controls set to true, add effect level sliders,
5839 * EQ presets, and Smart Volume presets. Also, change names to add FX
5840 * prefix, and change PlayEnhancement and CrystalVoice to match.
5841 */
5842 if (spec->use_alt_controls) {
5843 ca0132_alt_add_svm_enum(codec);
5844 add_ca0132_alt_eq_presets(codec);
5845 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5846 "Enable OutFX", 0);
5847 if (err < 0)
5848 return err;
e90f29e4 5849
47cdf76e
CM		 5850 err = add_fx_switch(codec, CRYSTAL_VOICE,
5851 "Enable InFX", 1);
5852 if (err < 0)
5853 return err;
e90f29e4 5854
47cdf76e
CM		 5855 num_sliders = OUT_EFFECTS_COUNT - 1;
5856 for (i = 0; i < num_sliders; i++) {
5857 err = ca0132_alt_add_effect_slider(codec,
5858 ca0132_effects[i].nid,
5859 ca0132_effects[i].name,
5860 ca0132_effects[i].direct);
5861 if (err < 0)
5862 return err;
5863 }
5864
5865 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5866 "X-Bass Crossover", EFX_DIR_OUT);
5867
5868 if (err < 0)
5869 return err;
5870 } else {
5871 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5872 "PlayEnhancement", 0);
5873 if (err < 0)
5874 return err;
e90f29e4 5875
47cdf76e
CM		 5876 err = add_fx_switch(codec, CRYSTAL_VOICE,
5877 "CrystalVoice", 1);
5878 if (err < 0)
5879 return err;
5880 }
e90f29e4
IM		 5881 add_voicefx(codec);
5882
7cb9d94c
CM		 5883 /*
5884 * If the codec uses alt_functions, you need the enumerated controls
5885 * to select the new outputs and inputs, plus add the new mic boost
5886 * setting control.
5887 */
5888 if (spec->use_alt_functions) {
5889 ca0132_alt_add_output_enum(codec);
5890 ca0132_alt_add_input_enum(codec);
47cdf76e 5891 ca0132_alt_add_mic_boost_enum(codec);
7cb9d94c 5892 }
e90f29e4
IM		 5893#ifdef ENABLE_TUNING_CONTROLS
5894 add_tuning_ctls(codec);
5895#endif
5896
5897 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
5898 if (err < 0)
5899 return err;
5900
5901 if (spec->dig_out) {
5902 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
5903 spec->dig_out);
5904 if (err < 0)
5905 return err;
5906 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
5907 if (err < 0)
5908 return err;
5909 /* spec->multiout.share_spdif = 1; */
5910 }
5911
5912 if (spec->dig_in) {
5913 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
5914 if (err < 0)
5915 return err;
5916 }
47cdf76e
CM		 5917
5918 if (spec->use_alt_functions)
5919 ca0132_alt_add_chmap_ctls(codec);
5920
e90f29e4
IM		 5921 return 0;
5922}
5923
a7e76271 5924/*
e90f29e4 5925 * PCM
a7e76271 5926 */
071f1344 5927static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 5928 .substreams = 1,
5929 .channels_min = 2,
825315bc 5930 .channels_max = 6,
a7e76271 5931 .ops = {
a7e76271 5932 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 5933 .cleanup = ca0132_playback_pcm_cleanup,
5934 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 5935 },
5936};
5937
071f1344 5938static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 5939 .substreams = 1,
5940 .channels_min = 2,
5941 .channels_max = 2,
825315bc
IM		 5942 .ops = {
5943 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 5944 .cleanup = ca0132_capture_pcm_cleanup,
5945 .get_delay = ca0132_capture_pcm_delay,
825315bc 5946 },
a7e76271
IM		 5947};
5948
071f1344 5949static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 5950 .substreams = 1,
5951 .channels_min = 2,
5952 .channels_max = 2,
5953 .ops = {
5954 .open = ca0132_dig_playback_pcm_open,
5955 .close = ca0132_dig_playback_pcm_close,
5956 .prepare = ca0132_dig_playback_pcm_prepare,
5957 .cleanup = ca0132_dig_playback_pcm_cleanup
5958 },
5959};
5960
071f1344 5961static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 5962 .substreams = 1,
5963 .channels_min = 2,
5964 .channels_max = 2,
5965};
5966
5967static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 5968{
5969 struct ca0132_spec *spec = codec->spec;
bbbc7e85 5970 struct hda_pcm *info;
a7e76271 5971
bbbc7e85
TI		 5972 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
5973 if (!info)
5974 return -ENOMEM;
47cdf76e
CM		 5975 if (spec->use_alt_functions) {
5976 info->own_chmap = true;
5977 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
5978 = ca0132_alt_chmaps;
5979 }
a7e76271
IM		 5980 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
5981 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
5982 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
5983 spec->multiout.max_channels;
5984 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 5985 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 5986 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 5987
009b8f97 5988 /* With the DSP enabled, desktops don't use this ADC. */
5f8ddc6e 5989 if (!spec->use_alt_functions) {
009b8f97
CM		 5990 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
5991 if (!info)
5992 return -ENOMEM;
5993 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
5994 ca0132_pcm_analog_capture;
5995 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
5996 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
5997 }
825315bc 5998
bbbc7e85
TI		 5999 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6000 if (!info)
6001 return -ENOMEM;
825315bc
IM		 6002 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6003 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6004 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6005
a7e76271
IM		 6006 if (!spec->dig_out && !spec->dig_in)
6007 return 0;
6008
bbbc7e85
TI		 6009 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6010 if (!info)
6011 return -ENOMEM;
a7e76271
IM		 6012 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6013 if (spec->dig_out) {
6014 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6015 ca0132_pcm_digital_playback;
6016 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6017 }
6018 if (spec->dig_in) {
6019 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6020 ca0132_pcm_digital_capture;
6021 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6022 }
95c6e9cb 6023
a7e76271 6024 return 0;
95c6e9cb
IM		 6025}
6026
441aa6a0
IM		 6027static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6028{
6029 if (pin) {
a0c041cb 6030 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6031 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6032 snd_hda_codec_write(codec, pin, 0,
6033 AC_VERB_SET_AMP_GAIN_MUTE,
6034 AMP_OUT_UNMUTE);
6035 }
6036 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6037 snd_hda_codec_write(codec, dac, 0,
6038 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6039}
6040
6041static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6042{
6043 if (pin) {
a0c041cb 6044 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6045 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6046 snd_hda_codec_write(codec, pin, 0,
6047 AC_VERB_SET_AMP_GAIN_MUTE,
6048 AMP_IN_UNMUTE(0));
6049 }
6050 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6051 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6052 AMP_IN_UNMUTE(0));
6053
6054 /* init to 0 dB and unmute. */
6055 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6056 HDA_AMP_VOLMASK, 0x5a);
6057 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6058 HDA_AMP_MUTE, 0);
6059 }
6060}
6061
5aaca44d
IM		 6062static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6063{
6064 unsigned int caps;
6065
6066 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6067 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6068 snd_hda_override_amp_caps(codec, nid, dir, caps);
6069}
6070
6071/*
6072 * Switch between Digital built-in mic and analog mic.
6073 */
6074static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6075{
6076 struct ca0132_spec *spec = codec->spec;
6077 unsigned int tmp;
6078 u8 val;
6079 unsigned int oldval;
6080
4e76a883 6081 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6082
6083 oldval = stop_mic1(codec);
6084 ca0132_set_vipsource(codec, 0);
6085 if (enable) {
6086 /* set DMic input as 2-ch */
6087 tmp = FLOAT_TWO;
6088 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6089
6090 val = spec->dmic_ctl;
6091 val |= 0x80;
6092 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6093 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6094
6095 if (!(spec->dmic_ctl & 0x20))
6096 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6097 } else {
6098 /* set AMic input as mono */
6099 tmp = FLOAT_ONE;
6100 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6101
6102 val = spec->dmic_ctl;
6103 /* clear bit7 and bit5 to disable dmic */
6104 val &= 0x5f;
6105 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6106 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6107
6108 if (!(spec->dmic_ctl & 0x20))
6109 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6110 }
6111 ca0132_set_vipsource(codec, 1);
6112 resume_mic1(codec, oldval);
6113}
6114
6115/*
6116 * Initialization for Digital Mic.
6117 */
6118static void ca0132_init_dmic(struct hda_codec *codec)
6119{
6120 struct ca0132_spec *spec = codec->spec;
6121 u8 val;
6122
6123 /* Setup Digital Mic here, but don't enable.
6124 * Enable based on jack detect.
6125 */
6126
6127 /* MCLK uses MPIO1, set to enable.
6128 * Bit 2-0: MPIO select
6129 * Bit 3: set to disable
6130 * Bit 7-4: reserved
6131 */
6132 val = 0x01;
6133 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6134 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6135
6136 /* Data1 uses MPIO3. Data2 not use
6137 * Bit 2-0: Data1 MPIO select
6138 * Bit 3: set disable Data1
6139 * Bit 6-4: Data2 MPIO select
6140 * Bit 7: set disable Data2
6141 */
6142 val = 0x83;
6143 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6144 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6145
6146 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6147 * Bit 3-0: Channel mask
6148 * Bit 4: set for 48KHz, clear for 32KHz
6149 * Bit 5: mode
6150 * Bit 6: set to select Data2, clear for Data1
6151 * Bit 7: set to enable DMic, clear for AMic
6152 */
a57a46b9
AB		 6153 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6154 val = 0x33;
6155 else
6156 val = 0x23;
5aaca44d
IM		 6157 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6158 spec->dmic_ctl = val;
6159 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6160 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6161}
6162
6163/*
6164 * Initialization for Analog Mic 2
6165 */
6166static void ca0132_init_analog_mic2(struct hda_codec *codec)
6167{
6168 struct ca0132_spec *spec = codec->spec;
6169
6170 mutex_lock(&spec->chipio_mutex);
6171 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6172 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6173 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6174 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6175 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6176 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6177 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6178 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6179 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6180 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6181 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6182 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6183 mutex_unlock(&spec->chipio_mutex);
6184}
6185
6186static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6187{
6188 struct ca0132_spec *spec = codec->spec;
6189 int i;
5aaca44d 6190
4e76a883 6191 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6192 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6193
6194 for (i = 0; i < spec->multiout.num_dacs; i++)
6195 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6196
6197 for (i = 0; i < spec->num_outputs; i++)
6198 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6199
6200 for (i = 0; i < spec->num_inputs; i++) {
6201 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6202 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6203 }
6204}
6205
7e6ed62e
CM		 6206/*
6207 * Recon3Di r3di_setup_defaults sub functions.
6208 */
6209
447fd8e9
CM		 6210static void r3di_dsp_scp_startup(struct hda_codec *codec)
6211{
6212 unsigned int tmp;
6213
6214 tmp = 0x00000000;
6215 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6216
6217 tmp = 0x00000001;
6218 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6219
6220 tmp = 0x00000004;
6221 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6222
6223 tmp = 0x00000005;
6224 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6225
6226 tmp = 0x00000000;
6227 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6228
6229}
6230
7e6ed62e
CM		 6231static void r3di_dsp_initial_mic_setup(struct hda_codec *codec)
6232{
6233 unsigned int tmp;
6234
6235 /* Mic 1 Setup */
6236 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6237 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6238 /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6239 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6240 tmp = FLOAT_ONE;
6241 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6242
6243 /* Mic 2 Setup, even though it isn't connected on SBZ */
6244 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6245 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6246 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6247 tmp = FLOAT_ZERO;
6248 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6249}
6250
38ba69ff
CM		 6251/*
6252 * Initialize Sound Blaster Z analog microphones.
6253 */
6254static void sbz_init_analog_mics(struct hda_codec *codec)
6255{
6256 unsigned int tmp;
6257
6258 /* Mic 1 Setup */
6259 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6260 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6261 tmp = FLOAT_THREE;
6262 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6263
6264 /* Mic 2 Setup, even though it isn't connected on SBZ */
6265 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6266 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6267 tmp = FLOAT_ZERO;
6268 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6269
6270}
6271
6272/*
6273 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6274 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6275 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6276 * having an updated DAC, which changes the destination to that DAC.
6277 */
6278static void sbz_connect_streams(struct hda_codec *codec)
6279{
6280 struct ca0132_spec *spec = codec->spec;
6281
6282 mutex_lock(&spec->chipio_mutex);
6283
6284 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6285
6286 chipio_set_stream_channels(codec, 0x0C, 6);
6287 chipio_set_stream_control(codec, 0x0C, 1);
6288
6289 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6290 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6291
6292 /* Setup stream 0x14 with it's source and destination points */
6293 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6294 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6295 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6296 chipio_set_stream_channels(codec, 0x14, 2);
6297 chipio_set_stream_control(codec, 0x14, 1);
6298
6299 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6300
6301 mutex_unlock(&spec->chipio_mutex);
6302
6303}
6304
6305/*
6306 * Write data through ChipIO to setup proper stream destinations.
6307 * Not sure how it exactly works, but it seems to direct data
6308 * to different destinations. Example is f8 to c0, e0 to c0.
6309 * All I know is, if you don't set these, you get no sound.
6310 */
6311static void sbz_chipio_startup_data(struct hda_codec *codec)
6312{
6313 struct ca0132_spec *spec = codec->spec;
6314
6315 mutex_lock(&spec->chipio_mutex);
6316 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6317
6318 /* These control audio output */
6319 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6320 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6321 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6322 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6323 /* Signal to update I think */
6324 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6325
6326 chipio_set_stream_channels(codec, 0x0C, 6);
6327 chipio_set_stream_control(codec, 0x0C, 1);
6328 /* No clue what these control */
6329 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6330 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6331 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6332 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6333 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6334 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6335 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6336 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6337 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6338 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6339 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6340 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6341
6342 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6343
6344 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6345 mutex_unlock(&spec->chipio_mutex);
6346}
6347
447fd8e9
CM		 6348/*
6349 * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6350 * without a 0x20 source like normal.
6351 */
6352static void sbz_dsp_scp_startup(struct hda_codec *codec)
6353{
6354 unsigned int tmp;
6355
6356 tmp = 0x00000003;
6357 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6358
6359 tmp = 0x00000000;
6360 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6361
6362 tmp = 0x00000001;
6363 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6364
6365 tmp = 0x00000004;
6366 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6367
6368 tmp = 0x00000005;
6369 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6370
6371 tmp = 0x00000000;
6372 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6373
6374}
6375
38ba69ff
CM		 6376static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
6377{
6378 unsigned int tmp;
6379
6380 chipio_set_stream_control(codec, 0x03, 0);
6381 chipio_set_stream_control(codec, 0x04, 0);
6382
6383 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6384 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6385
6386 tmp = FLOAT_THREE;
6387 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6388
6389 chipio_set_stream_control(codec, 0x03, 1);
6390 chipio_set_stream_control(codec, 0x04, 1);
6391
6392 chipio_write(codec, 0x18b098, 0x0000000c);
6393 chipio_write(codec, 0x18b09C, 0x0000000c);
6394}
6395
5aaca44d
IM		 6396/*
6397 * Setup default parameters for DSP
6398 */
6399static void ca0132_setup_defaults(struct hda_codec *codec)
6400{
e8f1bd5d 6401 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 6402 unsigned int tmp;
6403 int num_fx;
6404 int idx, i;
6405
e8f1bd5d 6406 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 6407 return;
6408
6409 /* out, in effects + voicefx */
6410 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6411 for (idx = 0; idx < num_fx; idx++) {
6412 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6413 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6414 ca0132_effects[idx].reqs[i],
6415 ca0132_effects[idx].def_vals[i]);
6416 }
6417 }
6418
6419 /*remove DSP headroom*/
6420 tmp = FLOAT_ZERO;
6421 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6422
6423 /*set speaker EQ bypass attenuation*/
6424 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6425
6426 /* set AMic1 and AMic2 as mono mic */
6427 tmp = FLOAT_ONE;
6428 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6429 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6430
6431 /* set AMic1 as CrystalVoice input */
6432 tmp = FLOAT_ONE;
6433 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6434
6435 /* set WUH source */
6436 tmp = FLOAT_TWO;
6437 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6438}
6439
7e6ed62e
CM		 6440/*
6441 * Setup default parameters for Recon3Di DSP.
6442 */
6443
6444static void r3di_setup_defaults(struct hda_codec *codec)
6445{
6446 struct ca0132_spec *spec = codec->spec;
6447 unsigned int tmp;
6448 int num_fx;
6449 int idx, i;
6450
6451 if (spec->dsp_state != DSP_DOWNLOADED)
6452 return;
6453
447fd8e9 6454 r3di_dsp_scp_startup(codec);
7e6ed62e
CM		 6455
6456 r3di_dsp_initial_mic_setup(codec);
6457
6458 /*remove DSP headroom*/
6459 tmp = FLOAT_ZERO;
6460 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6461
6462 /* set WUH source */
6463 tmp = FLOAT_TWO;
6464 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6465 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6466
6467 /* Set speaker source? */
6468 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6469
6470 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6471
6472 /* Setup effect defaults */
6473 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6474 for (idx = 0; idx < num_fx; idx++) {
6475 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6476 dspio_set_uint_param(codec,
6477 ca0132_effects[idx].mid,
6478 ca0132_effects[idx].reqs[i],
6479 ca0132_effects[idx].def_vals[i]);
6480 }
6481 }
6482
6483}
6484
38ba69ff
CM		 6485/*
6486 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6487 * than the Chromebook setup.
6488 */
6489static void sbz_setup_defaults(struct hda_codec *codec)
6490{
6491 struct ca0132_spec *spec = codec->spec;
6492 unsigned int tmp, stream_format;
6493 int num_fx;
6494 int idx, i;
6495
6496 if (spec->dsp_state != DSP_DOWNLOADED)
6497 return;
6498
447fd8e9 6499 sbz_dsp_scp_startup(codec);
38ba69ff
CM		 6500
6501 sbz_init_analog_mics(codec);
6502
6503 sbz_connect_streams(codec);
6504
6505 sbz_chipio_startup_data(codec);
6506
6507 chipio_set_stream_control(codec, 0x03, 1);
6508 chipio_set_stream_control(codec, 0x04, 1);
6509
6510 /*
6511 * Sets internal input loopback to off, used to have a switch to
6512 * enable input loopback, but turned out to be way too buggy.
6513 */
6514 tmp = FLOAT_ONE;
6515 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6516 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6517
6518 /*remove DSP headroom*/
6519 tmp = FLOAT_ZERO;
6520 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6521
6522 /* set WUH source */
6523 tmp = FLOAT_TWO;
6524 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6525 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6526
6527 /* Set speaker source? */
6528 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6529
6530 sbz_dsp_initial_mic_setup(codec);
6531
6532
6533 /* out, in effects + voicefx */
6534 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6535 for (idx = 0; idx < num_fx; idx++) {
6536 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6537 dspio_set_uint_param(codec,
6538 ca0132_effects[idx].mid,
6539 ca0132_effects[idx].reqs[i],
6540 ca0132_effects[idx].def_vals[i]);
6541 }
6542 }
6543
6544 /*
6545 * Have to make a stream to bind the sound output to, otherwise
6546 * you'll get dead audio. Before I did this, it would bind to an
6547 * audio input, and would never work
6548 */
6549 stream_format = snd_hdac_calc_stream_format(48000, 2,
6550 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6551
6552 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6553 0, stream_format);
6554
6555 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6556
6557 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6558 0, stream_format);
6559
6560 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6561}
6562
5aaca44d
IM		 6563/*
6564 * Initialization of flags in chip
6565 */
6566static void ca0132_init_flags(struct hda_codec *codec)
6567{
009b8f97
CM		 6568 struct ca0132_spec *spec = codec->spec;
6569
6570 if (spec->use_alt_functions) {
6571 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6572 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6573 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6574 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6575 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6576 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6577 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6578 chipio_set_control_flag(codec,
6579 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6580 chipio_set_control_flag(codec,
6581 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6582 } else {
6583 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6584 chipio_set_control_flag(codec,
6585 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6586 chipio_set_control_flag(codec,
6587 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6588 chipio_set_control_flag(codec,
6589 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6590 chipio_set_control_flag(codec,
6591 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6592 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6593 }
5aaca44d
IM		 6594}
6595
6596/*
6597 * Initialization of parameters in chip
6598 */
6599static void ca0132_init_params(struct hda_codec *codec)
6600{
009b8f97
CM		 6601 struct ca0132_spec *spec = codec->spec;
6602
6603 if (spec->use_alt_functions) {
6604 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6605 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6606 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6607 chipio_set_control_param(codec, 0, 0);
6608 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6609 }
6610
5aaca44d
IM		 6611 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6612 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6613}
95c6e9cb 6614
e90f29e4
IM		 6615static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6616{
6617 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6618 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6619 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6620 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6621 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6622 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6623
406261ce
IM		 6624 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6625 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 6626 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6627}
6628
6629static bool ca0132_download_dsp_images(struct hda_codec *codec)
6630{
6631 bool dsp_loaded = false;
8a19bcee 6632 struct ca0132_spec *spec = codec->spec;
e90f29e4 6633 const struct dsp_image_seg *dsp_os_image;
15e4ba66 6634 const struct firmware *fw_entry;
8a19bcee
CM		 6635 /*
6636 * Alternate firmwares for different variants. The Recon3Di apparently
6637 * can use the default firmware, but I'll leave the option in case
6638 * it needs it again.
6639 */
6640 switch (spec->quirk) {
6641 case QUIRK_SBZ:
6642 if (request_firmware(&fw_entry, SBZ_EFX_FILE,
6643 codec->card->dev) != 0) {
6644 codec_dbg(codec, "SBZ alt firmware not detected. ");
6645 spec->alt_firmware_present = false;
6646 } else {
6647 codec_dbg(codec, "Sound Blaster Z firmware selected.");
6648 spec->alt_firmware_present = true;
6649 }
6650 break;
6651 case QUIRK_R3DI:
6652 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6653 codec->card->dev) != 0) {
6654 codec_dbg(codec, "Recon3Di alt firmware not detected.");
6655 spec->alt_firmware_present = false;
6656 } else {
6657 codec_dbg(codec, "Recon3Di firmware selected.");
6658 spec->alt_firmware_present = true;
6659 }
6660 break;
6661 default:
6662 spec->alt_firmware_present = false;
6663 break;
6664 }
6665 /*
6666 * Use default ctefx.bin if no alt firmware is detected, or if none
6667 * exists for your particular codec.
6668 */
6669 if (!spec->alt_firmware_present) {
6670 codec_dbg(codec, "Default firmware selected.");
6671 if (request_firmware(&fw_entry, EFX_FILE,
6672 codec->card->dev) != 0)
6673 return false;
6674 }
e90f29e4 6675
15e4ba66 6676 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 6677 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 6678 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 6679 goto exit_download;
6680 }
6681
e90f29e4
IM		 6682 dsp_loaded = dspload_wait_loaded(codec);
6683
d1d28500 6684exit_download:
15e4ba66
TI		 6685 release_firmware(fw_entry);
6686
e90f29e4
IM		 6687 return dsp_loaded;
6688}
6689
6690static void ca0132_download_dsp(struct hda_codec *codec)
6691{
6692 struct ca0132_spec *spec = codec->spec;
6693
9a0869f4
TI		 6694#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6695 return; /* NOP */
6696#endif
e90f29e4 6697
e24aa0a4
TI		 6698 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6699 return; /* don't retry failures */
6700
b714a710 6701 chipio_enable_clocks(codec);
e93ac30a
CM		 6702 if (spec->dsp_state != DSP_DOWNLOADED) {
6703 spec->dsp_state = DSP_DOWNLOADING;
6704
6705 if (!ca0132_download_dsp_images(codec))
6706 spec->dsp_state = DSP_DOWNLOAD_FAILED;
6707 else
6708 spec->dsp_state = DSP_DOWNLOADED;
6709 }
e90f29e4 6710
009b8f97
CM		 6711 /* For codecs using alt functions, this is already done earlier */
6712 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 6713 ca0132_set_dsp_msr(codec, true);
6714}
6715
f8fb1170
TI		 6716static void ca0132_process_dsp_response(struct hda_codec *codec,
6717 struct hda_jack_callback *callback)
e90f29e4
IM		 6718{
6719 struct ca0132_spec *spec = codec->spec;
6720
4e76a883 6721 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 6722 if (spec->wait_scp) {
6723 if (dspio_get_response_data(codec) >= 0)
6724 spec->wait_scp = 0;
6725 }
6726
6727 dspio_clear_response_queue(codec);
6728}
6729
f8fb1170 6730static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 6731{
993884f6 6732 struct ca0132_spec *spec = codec->spec;
2ebab40e 6733 struct hda_jack_tbl *tbl;
e90f29e4 6734
f8fb1170
TI		 6735 /* Delay enabling the HP amp, to let the mic-detection
6736 * state machine run.
6737 */
6738 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 6739 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 6740 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6741 if (tbl)
6742 tbl->block_report = 1;
f8fb1170
TI		 6743}
6744
6745static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6746{
a1b7f016
CM		 6747 struct ca0132_spec *spec = codec->spec;
6748
6749 if (spec->use_alt_functions)
6750 ca0132_alt_select_in(codec);
6751 else
6752 ca0132_select_mic(codec);
f8fb1170
TI		 6753}
6754
6755static void ca0132_init_unsol(struct hda_codec *codec)
6756{
d5c016b5
GM		 6757 struct ca0132_spec *spec = codec->spec;
6758 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6759 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 6760 amic_callback);
6761 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6762 ca0132_process_dsp_response);
63177afc 6763 /* Front headphone jack detection */
009b8f97 6764 if (spec->use_alt_functions)
63177afc
CM		 6765 snd_hda_jack_detect_enable_callback(codec,
6766 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 6767}
6768
5aaca44d
IM		 6769/*
6770 * Verbs tables.
6771 */
6772
6773/* Sends before DSP download. */
6774static struct hda_verb ca0132_base_init_verbs[] = {
6775 /*enable ct extension*/
6776 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 6777 {}
6778};
6779
6780/* Send at exit. */
6781static struct hda_verb ca0132_base_exit_verbs[] = {
6782 /*set afg to D3*/
6783 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
6784 /*disable ct extension*/
6785 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6786 {}
6787};
6788
8a19bcee 6789/* Other verbs tables. Sends after DSP download. */
e93ac30a 6790
5aaca44d
IM		 6791static struct hda_verb ca0132_init_verbs0[] = {
6792 /* chip init verbs */
6793 {0x15, 0x70D, 0xF0},
6794 {0x15, 0x70E, 0xFE},
6795 {0x15, 0x707, 0x75},
6796 {0x15, 0x707, 0xD3},
6797 {0x15, 0x707, 0x09},
6798 {0x15, 0x707, 0x53},
6799 {0x15, 0x707, 0xD4},
6800 {0x15, 0x707, 0xEF},
6801 {0x15, 0x707, 0x75},
6802 {0x15, 0x707, 0xD3},
6803 {0x15, 0x707, 0x09},
6804 {0x15, 0x707, 0x02},
6805 {0x15, 0x707, 0x37},
6806 {0x15, 0x707, 0x78},
6807 {0x15, 0x53C, 0xCE},
6808 {0x15, 0x575, 0xC9},
6809 {0x15, 0x53D, 0xCE},
6810 {0x15, 0x5B7, 0xC9},
6811 {0x15, 0x70D, 0xE8},
6812 {0x15, 0x70E, 0xFE},
6813 {0x15, 0x707, 0x02},
6814 {0x15, 0x707, 0x68},
6815 {0x15, 0x707, 0x62},
6816 {0x15, 0x53A, 0xCE},
6817 {0x15, 0x546, 0xC9},
6818 {0x15, 0x53B, 0xCE},
6819 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 6820 {}
6821};
6822
6823/* Extra init verbs for SBZ */
6824static struct hda_verb sbz_init_verbs[] = {
6825 {0x15, 0x70D, 0x20},
6826 {0x15, 0x70E, 0x19},
6827 {0x15, 0x707, 0x00},
6828 {0x15, 0x539, 0xCE},
6829 {0x15, 0x546, 0xC9},
6830 {0x15, 0x70D, 0xB7},
6831 {0x15, 0x70E, 0x09},
6832 {0x15, 0x707, 0x10},
6833 {0x15, 0x70D, 0xAF},
6834 {0x15, 0x70E, 0x09},
6835 {0x15, 0x707, 0x01},
6836 {0x15, 0x707, 0x05},
6837 {0x15, 0x70D, 0x73},
6838 {0x15, 0x70E, 0x09},
6839 {0x15, 0x707, 0x14},
6840 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 6841 {}
6842};
6843
95c6e9cb
IM		 6844static void ca0132_init_chip(struct hda_codec *codec)
6845{
6846 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 6847 int num_fx;
6848 int i;
6849 unsigned int on;
95c6e9cb
IM		 6850
6851 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 6852
6853 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 6854 if (!spec->use_alt_functions)
6855 spec->cur_mic_type = DIGITAL_MIC;
6856 else
6857 spec->cur_mic_type = REAR_MIC;
6858
5aaca44d
IM		 6859 spec->cur_mic_boost = 0;
6860
6861 for (i = 0; i < VNODES_COUNT; i++) {
6862 spec->vnode_lvol[i] = 0x5a;
6863 spec->vnode_rvol[i] = 0x5a;
6864 spec->vnode_lswitch[i] = 0;
6865 spec->vnode_rswitch[i] = 0;
6866 }
6867
6868 /*
6869 * Default states for effects are in ca0132_effects[].
6870 */
6871 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6872 for (i = 0; i < num_fx; i++) {
6873 on = (unsigned int)ca0132_effects[i].reqs[0];
6874 spec->effects_switch[i] = on ? 1 : 0;
6875 }
47cdf76e
CM		 6876 /*
6877 * Sets defaults for the effect slider controls, only for alternative
6878 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6879 */
6880 if (spec->use_alt_controls) {
6881 spec->xbass_xover_freq = 8;
6882 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6883 spec->fx_ctl_val[i] = effect_slider_defaults[i];
6884 }
5aaca44d
IM		 6885
6886 spec->voicefx_val = 0;
6887 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6888 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
6889
44f0c978
IM		 6890#ifdef ENABLE_TUNING_CONTROLS
6891 ca0132_init_tuning_defaults(codec);
6892#endif
95c6e9cb
IM		 6893}
6894
2e48b2b7
CM		 6895/*
6896 * Recon3Di exit specific commands.
6897 */
6898/* prevents popping noise on shutdown */
6899static void r3di_gpio_shutdown(struct hda_codec *codec)
6900{
6901 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
6902}
6903
6904/*
6905 * Sound Blaster Z exit specific commands.
6906 */
6907static void sbz_region2_exit(struct hda_codec *codec)
6908{
6909 struct ca0132_spec *spec = codec->spec;
6910 unsigned int i;
6911
6912 for (i = 0; i < 4; i++)
6913 writeb(0x0, spec->mem_base + 0x100);
6914 for (i = 0; i < 8; i++)
6915 writeb(0xb3, spec->mem_base + 0x304);
a62e4739
CM		 6916
6917 ca0132_mmio_gpio_set(codec, 0, false);
6918 ca0132_mmio_gpio_set(codec, 1, false);
6919 ca0132_mmio_gpio_set(codec, 4, true);
6920 ca0132_mmio_gpio_set(codec, 5, false);
6921 ca0132_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 6922}
6923
6924static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6925{
6926 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6927 unsigned int i;
6928
6929 snd_hda_codec_write(codec, 0x11, 0,
6930 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6931
6932 for (i = 0; i < 5; i++)
6933 snd_hda_codec_write(codec, pins[i], 0,
6934 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6935}
6936
6937static void sbz_clear_unsolicited(struct hda_codec *codec)
6938{
6939 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6940 unsigned int i;
6941
6942 for (i = 0; i < 7; i++) {
6943 snd_hda_codec_write(codec, pins[i], 0,
6944 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6945 }
6946}
6947
6948/* On shutdown, sends commands in sets of three */
6949static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
6950 int mask, int data)
6951{
6952 if (dir >= 0)
6953 snd_hda_codec_write(codec, 0x01, 0,
6954 AC_VERB_SET_GPIO_DIRECTION, dir);
6955 if (mask >= 0)
6956 snd_hda_codec_write(codec, 0x01, 0,
6957 AC_VERB_SET_GPIO_MASK, mask);
6958
6959 if (data >= 0)
6960 snd_hda_codec_write(codec, 0x01, 0,
6961 AC_VERB_SET_GPIO_DATA, data);
6962}
6963
6964static void sbz_exit_chip(struct hda_codec *codec)
6965{
009b8f97
CM		 6966 chipio_set_stream_control(codec, 0x03, 0);
6967 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 6968
6969 /* Mess with GPIO */
6970 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
6971 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
6972 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
6973
009b8f97
CM		 6974 chipio_set_stream_control(codec, 0x14, 0);
6975 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 6976
6977 chipio_set_conn_rate(codec, 0x41, SR_192_000);
6978 chipio_set_conn_rate(codec, 0x91, SR_192_000);
6979
6980 chipio_write(codec, 0x18a020, 0x00000083);
6981
6982 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
6983 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
6984 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
6985
009b8f97 6986 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 6987
6988 chipio_set_control_param(codec, 0x0D, 0x24);
6989
6990 sbz_clear_unsolicited(codec);
6991 sbz_set_pin_ctl_default(codec);
6992
6993 snd_hda_codec_write(codec, 0x0B, 0,
6994 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
6995
6996 if (dspload_is_loaded(codec))
6997 dsp_reset(codec);
6998
6999 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7000 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x00);
7001
7002 sbz_region2_exit(codec);
7003}
7004
95c6e9cb
IM		 7005static void ca0132_exit_chip(struct hda_codec *codec)
7006{
7007 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7008
7009 if (dspload_is_loaded(codec))
7010 dsp_reset(codec);
95c6e9cb
IM		 7011}
7012
38ba69ff
CM		 7013/*
7014 * This fixes a problem that was hard to reproduce. Very rarely, I would
7015 * boot up, and there would be no sound, but the DSP indicated it had loaded
7016 * properly. I did a few memory dumps to see if anything was different, and
7017 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7018 * checks if those areas are uninitialized, and if they are, it'll attempt to
7019 * reload the card 3 times. Usually it fixes by the second.
7020 */
7021static void sbz_dsp_startup_check(struct hda_codec *codec)
7022{
7023 struct ca0132_spec *spec = codec->spec;
7024 unsigned int dsp_data_check[4];
7025 unsigned int cur_address = 0x390;
7026 unsigned int i;
7027 unsigned int failure = 0;
7028 unsigned int reload = 3;
7029
7030 if (spec->startup_check_entered)
7031 return;
7032
7033 spec->startup_check_entered = true;
7034
7035 for (i = 0; i < 4; i++) {
7036 chipio_read(codec, cur_address, &dsp_data_check[i]);
7037 cur_address += 0x4;
7038 }
7039 for (i = 0; i < 4; i++) {
7040 if (dsp_data_check[i] == 0xa1a2a3a4)
7041 failure = 1;
7042 }
7043
7044 codec_dbg(codec, "Startup Check: %d ", failure);
7045 if (failure)
7046 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7047 /*
7048 * While the failure condition is true, and we haven't reached our
7049 * three reload limit, continue trying to reload the driver and
7050 * fix the issue.
7051 */
7052 while (failure && (reload != 0)) {
7053 codec_info(codec, "Reloading... Tries left: %d", reload);
7054 sbz_exit_chip(codec);
7055 spec->dsp_state = DSP_DOWNLOAD_INIT;
7056 codec->patch_ops.init(codec);
7057 failure = 0;
7058 for (i = 0; i < 4; i++) {
7059 chipio_read(codec, cur_address, &dsp_data_check[i]);
7060 cur_address += 0x4;
7061 }
7062 for (i = 0; i < 4; i++) {
7063 if (dsp_data_check[i] == 0xa1a2a3a4)
7064 failure = 1;
7065 }
7066 reload--;
7067 }
7068
7069 if (!failure && reload < 3)
7070 codec_info(codec, "DSP fixed.");
7071
7072 if (!failure)
7073 return;
7074
7075 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7076}
7077
e93ac30a
CM		 7078/*
7079 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7080 * extra precision for decibel values. If you had the dB value in floating point
7081 * you would take the value after the decimal point, multiply by 64, and divide
7082 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7083 * implement fixed point or floating point dB volumes. For now, I'll set them
7084 * to 0 just incase a value has lingered from a boot into Windows.
7085 */
7086static void ca0132_alt_vol_setup(struct hda_codec *codec)
7087{
7088 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7089 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7090 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7091 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7092 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7093 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7094 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7095 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7096}
7097
7098/*
7099 * Extra commands that don't really fit anywhere else.
7100 */
7101static void sbz_pre_dsp_setup(struct hda_codec *codec)
7102{
7103 struct ca0132_spec *spec = codec->spec;
7104
7105 writel(0x00820680, spec->mem_base + 0x01C);
7106 writel(0x00820680, spec->mem_base + 0x01C);
7107
7108 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7109 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7110 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7111 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7112
7113 chipio_write(codec, 0x18b0a4, 0x000000c2);
7114
7115 snd_hda_codec_write(codec, 0x11, 0,
7116 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7117}
7118
7119/*
7120 * Extra commands that don't really fit anywhere else.
7121 */
7122static void r3di_pre_dsp_setup(struct hda_codec *codec)
7123{
7124 chipio_write(codec, 0x18b0a4, 0x000000c2);
7125
7126 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7127 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7128 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7129 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7130 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7131 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7132
7133 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7134 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7135 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7136 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7137 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7138 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7139 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7140 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7141
7142 snd_hda_codec_write(codec, 0x11, 0,
7143 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7144}
7145
7146
7147/*
7148 * These are sent before the DSP is downloaded. Not sure
7149 * what they do, or if they're necessary. Could possibly
7150 * be removed. Figure they're better to leave in.
7151 */
7152static void sbz_region2_startup(struct hda_codec *codec)
7153{
7154 struct ca0132_spec *spec = codec->spec;
7155
7156 writel(0x00000000, spec->mem_base + 0x400);
7157 writel(0x00000000, spec->mem_base + 0x408);
7158 writel(0x00000000, spec->mem_base + 0x40C);
7159 writel(0x00880680, spec->mem_base + 0x01C);
7160 writel(0x00000083, spec->mem_base + 0xC0C);
7161 writel(0x00000030, spec->mem_base + 0xC00);
7162 writel(0x00000000, spec->mem_base + 0xC04);
7163 writel(0x00000003, spec->mem_base + 0xC0C);
7164 writel(0x00000003, spec->mem_base + 0xC0C);
7165 writel(0x00000003, spec->mem_base + 0xC0C);
7166 writel(0x00000003, spec->mem_base + 0xC0C);
7167 writel(0x000000C1, spec->mem_base + 0xC08);
7168 writel(0x000000F1, spec->mem_base + 0xC08);
7169 writel(0x00000001, spec->mem_base + 0xC08);
7170 writel(0x000000C7, spec->mem_base + 0xC08);
7171 writel(0x000000C1, spec->mem_base + 0xC08);
7172 writel(0x00000080, spec->mem_base + 0xC04);
7173}
7174
7175/*
7176 * Extra init functions for alternative ca0132 codecs. Done
7177 * here so they don't clutter up the main ca0132_init function
7178 * anymore than they have to.
7179 */
7180static void ca0132_alt_init(struct hda_codec *codec)
7181{
7182 struct ca0132_spec *spec = codec->spec;
7183
7184 ca0132_alt_vol_setup(codec);
7185
7186 switch (spec->quirk) {
7187 case QUIRK_SBZ:
7188 codec_dbg(codec, "SBZ alt_init");
7189 ca0132_gpio_init(codec);
7190 sbz_pre_dsp_setup(codec);
7191 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7192 snd_hda_sequence_write(codec, spec->sbz_init_verbs);
7193 break;
7194 case QUIRK_R3DI:
7195 codec_dbg(codec, "R3DI alt_init");
7196 ca0132_gpio_init(codec);
7197 ca0132_gpio_setup(codec);
7e6ed62e 7198 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 7199 r3di_pre_dsp_setup(codec);
7200 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7201 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7202 break;
7203 }
7204}
7205
95c6e9cb
IM		 7206static int ca0132_init(struct hda_codec *codec)
7207{
7208 struct ca0132_spec *spec = codec->spec;
7209 struct auto_pin_cfg *cfg = &spec->autocfg;
7210 int i;
e93ac30a
CM		 7211 bool dsp_loaded;
7212
7213 /*
7214 * If the DSP is already downloaded, and init has been entered again,
7215 * there's only two reasons for it. One, the codec has awaken from a
7216 * suspended state, and in that case dspload_is_loaded will return
7217 * false, and the init will be ran again. The other reason it gets
7218 * re entered is on startup for some reason it triggers a suspend and
7219 * resume state. In this case, it will check if the DSP is downloaded,
7220 * and not run the init function again. For codecs using alt_functions,
7221 * it will check if the DSP is loaded properly.
7222 */
7223 if (spec->dsp_state == DSP_DOWNLOADED) {
7224 dsp_loaded = dspload_is_loaded(codec);
7225 if (!dsp_loaded) {
7226 spec->dsp_reload = true;
7227 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 7228 } else {
7229 if (spec->quirk == QUIRK_SBZ)
7230 sbz_dsp_startup_check(codec);
e93ac30a 7231 return 0;
38ba69ff 7232 }
e93ac30a 7233 }
95c6e9cb 7234
e24aa0a4
TI		 7235 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7236 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 7237 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 7238
e93ac30a
CM		 7239 if (spec->quirk == QUIRK_SBZ)
7240 sbz_region2_startup(codec);
7241
664c7155 7242 snd_hda_power_up_pm(codec);
5aaca44d 7243
f8fb1170 7244 ca0132_init_unsol(codec);
5aaca44d
IM		 7245 ca0132_init_params(codec);
7246 ca0132_init_flags(codec);
7e6ed62e 7247
5aaca44d 7248 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 7249
365c7f25 7250 if (spec->use_alt_functions)
e93ac30a
CM		 7251 ca0132_alt_init(codec);
7252
01ef7dbf 7253 ca0132_download_dsp(codec);
7e6ed62e 7254
5aaca44d 7255 ca0132_refresh_widget_caps(codec);
e93ac30a 7256
7e6ed62e
CM		 7257 switch (spec->quirk) {
7258 case QUIRK_R3DI:
7259 r3di_setup_defaults(codec);
7260 break;
126b75e0 7261 case QUIRK_SBZ:
d97420d2 7262 sbz_setup_defaults(codec);
126b75e0
AB		 7263 break;
7264 default:
38ba69ff
CM		 7265 ca0132_setup_defaults(codec);
7266 ca0132_init_analog_mic2(codec);
7267 ca0132_init_dmic(codec);
7e6ed62e 7268 break;
38ba69ff 7269 }
5aaca44d
IM		 7270
7271 for (i = 0; i < spec->num_outputs; i++)
7272 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 7273
95c6e9cb
IM		 7274 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7275
7276 for (i = 0; i < spec->num_inputs; i++)
7277 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7278
7279 init_input(codec, cfg->dig_in_pin, spec->dig_in);
7280
009b8f97 7281 if (!spec->use_alt_functions) {
e93ac30a
CM		 7282 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7283 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7284 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7285 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7286 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7287 }
7288
7cb9d94c 7289 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 7290 ca0132_gpio_setup(codec);
7291
d5c016b5 7292 snd_hda_sequence_write(codec, spec->spec_init_verbs);
d97420d2 7293 if (spec->use_alt_functions) {
7cb9d94c
CM		 7294 ca0132_alt_select_out(codec);
7295 ca0132_alt_select_in(codec);
d97420d2 7296 } else {
7cb9d94c
CM		 7297 ca0132_select_out(codec);
7298 ca0132_select_mic(codec);
7cb9d94c 7299 }
5aaca44d 7300
a73d511c
IM		 7301 snd_hda_jack_report_sync(codec);
7302
e93ac30a
CM		 7303 /*
7304 * Re set the PlayEnhancement switch on a resume event, because the
7305 * controls will not be reloaded.
7306 */
7307 if (spec->dsp_reload) {
7308 spec->dsp_reload = false;
7309 ca0132_pe_switch_set(codec);
7310 }
7311
664c7155 7312 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 7313
7314 return 0;
7315}
7316
95c6e9cb
IM		 7317static void ca0132_free(struct hda_codec *codec)
7318{
5aaca44d
IM		 7319 struct ca0132_spec *spec = codec->spec;
7320
993884f6 7321 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 7322 snd_hda_power_up(codec);
2e48b2b7
CM		 7323 switch (spec->quirk) {
7324 case QUIRK_SBZ:
7325 sbz_exit_chip(codec);
7326 break;
7327 case QUIRK_R3DI:
7328 r3di_gpio_shutdown(codec);
7329 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7330 ca0132_exit_chip(codec);
7331 break;
7332 default:
7333 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7334 ca0132_exit_chip(codec);
7335 break;
7336 }
5aaca44d 7337 snd_hda_power_down(codec);
aa31704f
CM		 7338 if (spec->mem_base)
7339 iounmap(spec->mem_base);
d5c016b5 7340 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 7341 kfree(codec->spec);
7342}
7343
2e48b2b7
CM		 7344static void ca0132_reboot_notify(struct hda_codec *codec)
7345{
7346 codec->patch_ops.free(codec);
7347}
7348
071f1344 7349static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 7350 .build_controls = ca0132_build_controls,
7351 .build_pcms = ca0132_build_pcms,
7352 .init = ca0132_init,
7353 .free = ca0132_free,
f8fb1170 7354 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 7355 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 7356};
7357
441aa6a0
IM		 7358static void ca0132_config(struct hda_codec *codec)
7359{
7360 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 7361
7362 spec->dacs[0] = 0x2;
7363 spec->dacs[1] = 0x3;
7364 spec->dacs[2] = 0x4;
7365
7366 spec->multiout.dac_nids = spec->dacs;
7367 spec->multiout.num_dacs = 3;
441aa6a0 7368
009b8f97 7369 if (!spec->use_alt_functions)
63177afc
CM		 7370 spec->multiout.max_channels = 2;
7371 else
7372 spec->multiout.max_channels = 6;
7373
7374 switch (spec->quirk) {
7375 case QUIRK_ALIENWARE:
d5c016b5 7376 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 7377 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7378
7379 spec->num_outputs = 2;
7380 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 7381 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 7382 spec->shared_out_nid = 0x2;
7383 spec->unsol_tag_hp = 0x0f;
7384
7385 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7386 spec->adcs[1] = 0x8; /* analog mic2 */
7387 spec->adcs[2] = 0xa; /* what u hear */
7388
7389 spec->num_inputs = 3;
7390 spec->input_pins[0] = 0x12;
7391 spec->input_pins[1] = 0x11;
7392 spec->input_pins[2] = 0x13;
7393 spec->shared_mic_nid = 0x7;
7394 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 7395 break;
7396 case QUIRK_SBZ:
7397 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7398 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7399
7400 spec->num_outputs = 2;
7401 spec->out_pins[0] = 0x0B; /* Line out */
7402 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7403 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7404 spec->out_pins[3] = 0x11; /* Rear surround */
7405 spec->shared_out_nid = 0x2;
7406 spec->unsol_tag_hp = spec->out_pins[1];
7407 spec->unsol_tag_front_hp = spec->out_pins[2];
7408
7409 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7410 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7411 spec->adcs[2] = 0xa; /* what u hear */
7412
7413 spec->num_inputs = 2;
7414 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7415 spec->input_pins[1] = 0x13; /* What U Hear */
7416 spec->shared_mic_nid = 0x7;
7417 spec->unsol_tag_amic1 = spec->input_pins[0];
7418
7419 /* SPDIF I/O */
7420 spec->dig_out = 0x05;
7421 spec->multiout.dig_out_nid = spec->dig_out;
63177afc 7422 spec->dig_in = 0x09;
63177afc
CM		 7423 break;
7424 case QUIRK_R3DI:
7425 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7426 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7427
7428 spec->num_outputs = 2;
7429 spec->out_pins[0] = 0x0B; /* Line out */
7430 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7431 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7432 spec->out_pins[3] = 0x11; /* Rear surround */
7433 spec->shared_out_nid = 0x2;
7434 spec->unsol_tag_hp = spec->out_pins[1];
7435 spec->unsol_tag_front_hp = spec->out_pins[2];
7436
7437 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7438 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7439 spec->adcs[2] = 0x0a; /* what u hear */
7440
7441 spec->num_inputs = 2;
7442 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7443 spec->input_pins[1] = 0x13; /* What U Hear */
7444 spec->shared_mic_nid = 0x7;
7445 spec->unsol_tag_amic1 = spec->input_pins[0];
7446
7447 /* SPDIF I/O */
7448 spec->dig_out = 0x05;
7449 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 7450 break;
7451 default:
fe14f39e
TI		 7452 spec->num_outputs = 2;
7453 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 7454 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 7455 spec->shared_out_nid = 0x2;
7456 spec->unsol_tag_hp = spec->out_pins[1];
7457
7458 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7459 spec->adcs[1] = 0x8; /* analog mic2 */
7460 spec->adcs[2] = 0xa; /* what u hear */
7461
7462 spec->num_inputs = 3;
7463 spec->input_pins[0] = 0x12;
7464 spec->input_pins[1] = 0x11;
7465 spec->input_pins[2] = 0x13;
7466 spec->shared_mic_nid = 0x7;
7467 spec->unsol_tag_amic1 = spec->input_pins[0];
7468
7469 /* SPDIF I/O */
7470 spec->dig_out = 0x05;
7471 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 7472 spec->dig_in = 0x09;
63177afc 7473 break;
d5c016b5 7474 }
441aa6a0
IM		 7475}
7476
d5c016b5
GM		 7477static int ca0132_prepare_verbs(struct hda_codec *codec)
7478{
7479/* Verbs + terminator (an empty element) */
a3d90d67 7480#define NUM_SPEC_VERBS 2
d5c016b5
GM		 7481 struct ca0132_spec *spec = codec->spec;
7482
7483 spec->chip_init_verbs = ca0132_init_verbs0;
e93ac30a
CM		 7484 if (spec->quirk == QUIRK_SBZ)
7485 spec->sbz_init_verbs = sbz_init_verbs;
6396bb22
KC		 7486 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7487 sizeof(struct hda_verb),
7488 GFP_KERNEL);
d5c016b5
GM		 7489 if (!spec->spec_init_verbs)
7490 return -ENOMEM;
7491
d5c016b5 7492 /* config EAPD */
a3d90d67
AB		 7493 spec->spec_init_verbs[0].nid = 0x0b;
7494 spec->spec_init_verbs[0].param = 0x78D;
7495 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 7496
7497 /* Previously commented configuration */
7498 /*
a3d90d67
AB		 7499 spec->spec_init_verbs[2].nid = 0x0b;
7500 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
7501 spec->spec_init_verbs[2].verb = 0x02;
7502
7503 spec->spec_init_verbs[3].nid = 0x10;
7504 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 7505 spec->spec_init_verbs[3].verb = 0x02;
7506
7507 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 7508 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 7509 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 7510 */
7511
7512 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7513 return 0;
7514}
7515
95c6e9cb
IM		 7516static int patch_ca0132(struct hda_codec *codec)
7517{
7518 struct ca0132_spec *spec;
a73d511c 7519 int err;
d5c016b5 7520 const struct snd_pci_quirk *quirk;
95c6e9cb 7521
4e76a883 7522 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 7523
7524 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7525 if (!spec)
7526 return -ENOMEM;
7527 codec->spec = spec;
993884f6 7528 spec->codec = codec;
95c6e9cb 7529
225068ab
TI		 7530 codec->patch_ops = ca0132_patch_ops;
7531 codec->pcm_format_first = 1;
7532 codec->no_sticky_stream = 1;
7533
d5c016b5
GM		 7534 /* Detect codec quirk */
7535 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7536 if (quirk)
7537 spec->quirk = quirk->value;
7538 else
7539 spec->quirk = QUIRK_NONE;
7540
aa31704f
CM		 7541 /* Setup BAR Region 2 for Sound Blaster Z */
7542 if (spec->quirk == QUIRK_SBZ) {
7543 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7544 if (spec->mem_base == NULL) {
7545 codec_warn(codec, "pci_iomap failed!");
7546 codec_info(codec, "perhaps this is not an SBZ?");
7547 spec->quirk = QUIRK_NONE;
7548 }
7549 }
009b8f97 7550
e24aa0a4 7551 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 7552 spec->num_mixers = 1;
017310fb
CM		 7553
7554 /* Set which mixers each quirk uses. */
7555 switch (spec->quirk) {
7556 case QUIRK_SBZ:
7557 spec->mixers[0] = sbz_mixer;
7558 snd_hda_codec_set_name(codec, "Sound Blaster Z");
7559 break;
7560 case QUIRK_R3DI:
7561 spec->mixers[0] = r3di_mixer;
7562 snd_hda_codec_set_name(codec, "Recon3Di");
7563 break;
7564 default:
7565 spec->mixers[0] = ca0132_mixer;
7566 break;
7567 }
a7e76271 7568
47cdf76e 7569 /* Setup whether or not to use alt functions/controls */
009b8f97
CM		 7570 switch (spec->quirk) {
7571 case QUIRK_SBZ:
7572 case QUIRK_R3DI:
47cdf76e 7573 spec->use_alt_controls = true;
009b8f97
CM		 7574 spec->use_alt_functions = true;
7575 break;
7576 default:
47cdf76e 7577 spec->use_alt_controls = false;
009b8f97
CM		 7578 spec->use_alt_functions = false;
7579 break;
7580 }
7581
5aaca44d
IM		 7582 spec->base_init_verbs = ca0132_base_init_verbs;
7583 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 7584
993884f6
CCC		 7585 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7586
95c6e9cb
IM		 7587 ca0132_init_chip(codec);
7588
7589 ca0132_config(codec);
7590
d5c016b5
GM		 7591 err = ca0132_prepare_verbs(codec);
7592 if (err < 0)
cc91ceaf 7593 goto error;
d5c016b5 7594
a73d511c
IM		 7595 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7596 if (err < 0)
cc91ceaf 7597 goto error;
a73d511c 7598
95c6e9cb 7599 return 0;
cc91ceaf
TI		 7600
7601 error:
7602 ca0132_free(codec);
7603 return err;
95c6e9cb
IM		 7604}
7605
7606/*
7607 * patch entries
7608 */
b9a94a9c
TI		 7609static struct hda_device_id snd_hda_id_ca0132[] = {
7610 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 7611 {} /* terminator */
7612};
b9a94a9c 7613MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 7614
7615MODULE_LICENSE("GPL");
406261ce 7616MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 7617
d8a766a1 7618static struct hda_codec_driver ca0132_driver = {
b9a94a9c 7619 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 7620};
7621
d8a766a1 7622module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)