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ALSA: hda/ca0132 - Add quirk ID and enum for Recon3D
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb
IM		 34#include <sound/core.h>
35#include "hda_codec.h"
36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
38ba69ff 52#define FLOAT_THREE 0x40400000
7cb9d94c 53#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 54#define FLOAT_MINUS_5 0xc0a00000
55
ef6b2ead
IM		 56#define UNSOL_TAG_DSP 0x16
57
4aa3bb0c
IM		 58#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
ef6b2ead
IM		 66#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 68
95c6e9cb
IM		 69#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
4aa3bb0c
IM		 72#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
01ef7dbf 83#define EFX_FILE "ctefx.bin"
8a19bcee
CM		 84#define SBZ_EFX_FILE "ctefx-sbz.bin"
85#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 86
24f3cede 87#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 88MODULE_FIRMWARE(EFX_FILE);
8a19bcee
CM		 89MODULE_FIRMWARE(SBZ_EFX_FILE);
90MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 91#endif
01ef7dbf 92
3a03f83b 93static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 94
7cb9d94c 95#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 96enum {
97 SPEAKER_OUT,
7cb9d94c
CM		 98 HEADPHONE_OUT,
99 SURROUND_OUT
ef6b2ead
IM		 100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
7cb9d94c 107/* Strings for Input Source Enum Control */
3a03f83b 108static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
ef6b2ead
IM		 116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
7cb9d94c
CM		 149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
155 MIC_BOOST_ENUM
ef6b2ead
IM		 156#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
157};
158
159/* Effects values size*/
160#define EFFECT_VALS_MAX_COUNT 12
161
47cdf76e
CM		 162/*
163 * Default values for the effect slider controls, they are in order of their
164 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
165 * X-bass.
166 */
167static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
168/* Amount of effect level sliders for ca0132_alt controls. */
169#define EFFECT_LEVEL_SLIDERS 5
170
e8412ca4
DR		 171/* Latency introduced by DSP blocks in milliseconds. */
172#define DSP_CAPTURE_INIT_LATENCY 0
173#define DSP_CRYSTAL_VOICE_LATENCY 124
174#define DSP_PLAYBACK_INIT_LATENCY 13
175#define DSP_PLAY_ENHANCEMENT_LATENCY 30
176#define DSP_SPEAKER_OUT_LATENCY 7
177
ef6b2ead 178struct ct_effect {
975cc02a 179 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 180 hda_nid_t nid;
181 int mid; /*effect module ID*/
182 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
183 int direct; /* 0:output; 1:input*/
184 int params; /* number of default non-on/off params */
185 /*effect default values, 1st is on/off. */
186 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
187};
188
189#define EFX_DIR_OUT 0
190#define EFX_DIR_IN 1
191
862154bb 192static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 193 { .name = "Surround",
194 .nid = SURROUND,
195 .mid = 0x96,
196 .reqs = {0, 1},
197 .direct = EFX_DIR_OUT,
198 .params = 1,
199 .def_vals = {0x3F800000, 0x3F2B851F}
200 },
201 { .name = "Crystalizer",
202 .nid = CRYSTALIZER,
203 .mid = 0x96,
204 .reqs = {7, 8},
205 .direct = EFX_DIR_OUT,
206 .params = 1,
207 .def_vals = {0x3F800000, 0x3F266666}
208 },
209 { .name = "Dialog Plus",
210 .nid = DIALOG_PLUS,
211 .mid = 0x96,
212 .reqs = {2, 3},
213 .direct = EFX_DIR_OUT,
214 .params = 1,
215 .def_vals = {0x00000000, 0x3F000000}
216 },
217 { .name = "Smart Volume",
218 .nid = SMART_VOLUME,
219 .mid = 0x96,
220 .reqs = {4, 5, 6},
221 .direct = EFX_DIR_OUT,
222 .params = 2,
223 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
224 },
225 { .name = "X-Bass",
226 .nid = X_BASS,
227 .mid = 0x96,
228 .reqs = {24, 23, 25},
229 .direct = EFX_DIR_OUT,
230 .params = 2,
231 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
232 },
233 { .name = "Equalizer",
234 .nid = EQUALIZER,
235 .mid = 0x96,
236 .reqs = {9, 10, 11, 12, 13, 14,
237 15, 16, 17, 18, 19, 20},
238 .direct = EFX_DIR_OUT,
239 .params = 11,
240 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
241 0x00000000, 0x00000000, 0x00000000, 0x00000000,
242 0x00000000, 0x00000000, 0x00000000, 0x00000000}
243 },
244 { .name = "Echo Cancellation",
245 .nid = ECHO_CANCELLATION,
246 .mid = 0x95,
247 .reqs = {0, 1, 2, 3},
248 .direct = EFX_DIR_IN,
249 .params = 3,
250 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
251 },
252 { .name = "Voice Focus",
253 .nid = VOICE_FOCUS,
254 .mid = 0x95,
255 .reqs = {6, 7, 8, 9},
256 .direct = EFX_DIR_IN,
257 .params = 3,
258 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
259 },
260 { .name = "Mic SVM",
261 .nid = MIC_SVM,
262 .mid = 0x95,
263 .reqs = {44, 45},
264 .direct = EFX_DIR_IN,
265 .params = 1,
266 .def_vals = {0x00000000, 0x3F3D70A4}
267 },
268 { .name = "Noise Reduction",
269 .nid = NOISE_REDUCTION,
270 .mid = 0x95,
271 .reqs = {4, 5},
272 .direct = EFX_DIR_IN,
273 .params = 1,
274 .def_vals = {0x3F800000, 0x3F000000}
275 },
276 { .name = "VoiceFX",
277 .nid = VOICEFX,
278 .mid = 0x95,
279 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
280 .direct = EFX_DIR_IN,
281 .params = 8,
282 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
283 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
284 0x00000000}
285 }
286};
287
288/* Tuning controls */
289#ifdef ENABLE_TUNING_CONTROLS
290
291enum {
292#define TUNING_CTL_START_NID 0xC0
293 WEDGE_ANGLE = TUNING_CTL_START_NID,
294 SVM_LEVEL,
295 EQUALIZER_BAND_0,
296 EQUALIZER_BAND_1,
297 EQUALIZER_BAND_2,
298 EQUALIZER_BAND_3,
299 EQUALIZER_BAND_4,
300 EQUALIZER_BAND_5,
301 EQUALIZER_BAND_6,
302 EQUALIZER_BAND_7,
303 EQUALIZER_BAND_8,
304 EQUALIZER_BAND_9,
305 TUNING_CTL_END_NID
306#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
307};
308
309struct ct_tuning_ctl {
975cc02a 310 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 311 hda_nid_t parent_nid;
312 hda_nid_t nid;
313 int mid; /*effect module ID*/
314 int req; /*effect module request*/
315 int direct; /* 0:output; 1:input*/
316 unsigned int def_val;/*effect default values*/
317};
318
862154bb 319static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 320 { .name = "Wedge Angle",
321 .parent_nid = VOICE_FOCUS,
322 .nid = WEDGE_ANGLE,
323 .mid = 0x95,
324 .req = 8,
325 .direct = EFX_DIR_IN,
326 .def_val = 0x41F00000
327 },
328 { .name = "SVM Level",
329 .parent_nid = MIC_SVM,
330 .nid = SVM_LEVEL,
331 .mid = 0x95,
332 .req = 45,
333 .direct = EFX_DIR_IN,
334 .def_val = 0x3F3D70A4
335 },
336 { .name = "EQ Band0",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_0,
339 .mid = 0x96,
340 .req = 11,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
343 },
344 { .name = "EQ Band1",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_1,
347 .mid = 0x96,
348 .req = 12,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
351 },
352 { .name = "EQ Band2",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_2,
355 .mid = 0x96,
356 .req = 13,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
359 },
360 { .name = "EQ Band3",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_3,
363 .mid = 0x96,
364 .req = 14,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
367 },
368 { .name = "EQ Band4",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_4,
371 .mid = 0x96,
372 .req = 15,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
375 },
376 { .name = "EQ Band5",
377 .parent_nid = EQUALIZER,
378 .nid = EQUALIZER_BAND_5,
379 .mid = 0x96,
380 .req = 16,
381 .direct = EFX_DIR_OUT,
382 .def_val = 0x00000000
383 },
384 { .name = "EQ Band6",
385 .parent_nid = EQUALIZER,
386 .nid = EQUALIZER_BAND_6,
387 .mid = 0x96,
388 .req = 17,
389 .direct = EFX_DIR_OUT,
390 .def_val = 0x00000000
391 },
392 { .name = "EQ Band7",
393 .parent_nid = EQUALIZER,
394 .nid = EQUALIZER_BAND_7,
395 .mid = 0x96,
396 .req = 18,
397 .direct = EFX_DIR_OUT,
398 .def_val = 0x00000000
399 },
400 { .name = "EQ Band8",
401 .parent_nid = EQUALIZER,
402 .nid = EQUALIZER_BAND_8,
403 .mid = 0x96,
404 .req = 19,
405 .direct = EFX_DIR_OUT,
406 .def_val = 0x00000000
407 },
408 { .name = "EQ Band9",
409 .parent_nid = EQUALIZER,
410 .nid = EQUALIZER_BAND_9,
411 .mid = 0x96,
412 .req = 20,
413 .direct = EFX_DIR_OUT,
414 .def_val = 0x00000000
415 }
416};
417#endif
418
419/* Voice FX Presets */
420#define VOICEFX_MAX_PARAM_COUNT 9
421
422struct ct_voicefx {
423 char *name;
424 hda_nid_t nid;
425 int mid;
426 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
427};
428
429struct ct_voicefx_preset {
430 char *name; /*preset name*/
431 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
432};
433
862154bb 434static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 435 .name = "VoiceFX Capture Switch",
436 .nid = VOICEFX,
437 .mid = 0x95,
438 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
439};
440
862154bb 441static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 442 { .name = "Neutral",
443 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
444 0x44FA0000, 0x3F800000, 0x3F800000,
445 0x3F800000, 0x00000000, 0x00000000 }
446 },
447 { .name = "Female2Male",
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3F19999A, 0x3F866666,
450 0x3F800000, 0x00000000, 0x00000000 }
451 },
452 { .name = "Male2Female",
453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
454 0x450AC000, 0x4017AE14, 0x3F6B851F,
455 0x3F800000, 0x00000000, 0x00000000 }
456 },
457 { .name = "ScrappyKid",
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x40400000, 0x3F28F5C3,
460 0x3F800000, 0x00000000, 0x00000000 }
461 },
462 { .name = "Elderly",
463 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
464 0x44E10000, 0x3FB33333, 0x3FB9999A,
465 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 },
467 { .name = "Orc",
468 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
469 0x45098000, 0x3F266666, 0x3FC00000,
470 0x3F800000, 0x00000000, 0x00000000 }
471 },
472 { .name = "Elf",
473 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
474 0x45193000, 0x3F8E147B, 0x3F75C28F,
475 0x3F800000, 0x00000000, 0x00000000 }
476 },
477 { .name = "Dwarf",
478 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
479 0x45007000, 0x3F451EB8, 0x3F7851EC,
480 0x3F800000, 0x00000000, 0x00000000 }
481 },
482 { .name = "AlienBrute",
483 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
484 0x451F6000, 0x3F266666, 0x3FA7D945,
485 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 },
487 { .name = "Robot",
488 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
489 0x44FA0000, 0x3FB2718B, 0x3F800000,
490 0xBC07010E, 0x00000000, 0x00000000 }
491 },
492 { .name = "Marine",
493 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
494 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
495 0x3F0A3D71, 0x00000000, 0x00000000 }
496 },
497 { .name = "Emo",
498 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
499 0x44FA0000, 0x3F800000, 0x3F800000,
500 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 },
502 { .name = "DeepVoice",
503 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
504 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
505 0x3F800000, 0x00000000, 0x00000000 }
506 },
507 { .name = "Munchkin",
508 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
509 0x44FA0000, 0x3F800000, 0x3F1A043C,
510 0x3F800000, 0x00000000, 0x00000000 }
511 }
512};
513
47cdf76e
CM		 514/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
515
516#define EQ_PRESET_MAX_PARAM_COUNT 11
517
518struct ct_eq {
519 char *name;
520 hda_nid_t nid;
521 int mid;
522 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
523};
524
525struct ct_eq_preset {
526 char *name; /*preset name*/
527 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
528};
529
862154bb 530static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 531 .name = "FX: Equalizer Preset Switch",
532 .nid = EQ_PRESET_ENUM,
533 .mid = 0x96,
534 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
535};
536
537
862154bb 538static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 539 { .name = "Flat",
540 .vals = { 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000, 0x00000000,
542 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000 }
544 },
545 { .name = "Acoustic",
546 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
547 0x40000000, 0x00000000, 0x00000000,
548 0x00000000, 0x00000000, 0x40000000,
549 0x40000000, 0x40000000 }
550 },
551 { .name = "Classical",
552 .vals = { 0x00000000, 0x00000000, 0x40C00000,
553 0x40C00000, 0x40466666, 0x00000000,
554 0x00000000, 0x00000000, 0x00000000,
555 0x40466666, 0x40466666 }
556 },
557 { .name = "Country",
558 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
559 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
560 0x00000000, 0x00000000, 0x40000000,
561 0x40466666, 0x40800000 }
562 },
563 { .name = "Dance",
564 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
565 0x40466666, 0x40866666, 0xBF99999A,
566 0xBF99999A, 0x00000000, 0x00000000,
567 0x40800000, 0x40800000 }
568 },
569 { .name = "Jazz",
570 .vals = { 0x00000000, 0x00000000, 0x00000000,
571 0x3F8CCCCD, 0x40800000, 0x40800000,
572 0x40800000, 0x00000000, 0x3F8CCCCD,
573 0x40466666, 0x40466666 }
574 },
575 { .name = "New Age",
576 .vals = { 0x00000000, 0x00000000, 0x40000000,
577 0x40000000, 0x00000000, 0x00000000,
578 0x00000000, 0x3F8CCCCD, 0x40000000,
579 0x40000000, 0x40000000 }
580 },
581 { .name = "Pop",
582 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
583 0x40000000, 0x40000000, 0x00000000,
584 0xBF99999A, 0xBF99999A, 0x00000000,
585 0x40466666, 0x40C00000 }
586 },
587 { .name = "Rock",
588 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
589 0x3F8CCCCD, 0x40000000, 0xBF99999A,
590 0xBF99999A, 0x00000000, 0x00000000,
591 0x40800000, 0x40800000 }
592 },
593 { .name = "Vocal",
594 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
595 0xBF99999A, 0x00000000, 0x40466666,
596 0x40800000, 0x40466666, 0x00000000,
597 0x00000000, 0x3F8CCCCD }
598 }
599};
600
7cb9d94c
CM		 601/* DSP command sequences for ca0132_alt_select_out */
602#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
603struct ca0132_alt_out_set {
604 char *name; /*preset name*/
605 unsigned char commands;
606 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
607 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
608 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
609};
610
611static const struct ca0132_alt_out_set alt_out_presets[] = {
612 { .name = "Line Out",
613 .commands = 7,
614 .mids = { 0x96, 0x96, 0x96, 0x8F,
615 0x96, 0x96, 0x96 },
616 .reqs = { 0x19, 0x17, 0x18, 0x01,
617 0x1F, 0x15, 0x3A },
618 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
619 0x00000000, 0x00000000, 0x00000000,
620 0x00000000 }
621 },
622 { .name = "Headphone",
623 .commands = 7,
624 .mids = { 0x96, 0x96, 0x96, 0x8F,
625 0x96, 0x96, 0x96 },
626 .reqs = { 0x19, 0x17, 0x18, 0x01,
627 0x1F, 0x15, 0x3A },
628 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
629 0x00000000, 0x00000000, 0x00000000,
630 0x00000000 }
631 },
632 { .name = "Surround",
633 .commands = 8,
634 .mids = { 0x96, 0x8F, 0x96, 0x96,
635 0x96, 0x96, 0x96, 0x96 },
636 .reqs = { 0x18, 0x01, 0x1F, 0x15,
637 0x3A, 0x1A, 0x1B, 0x1C },
638 .vals = { 0x00000000, 0x00000000, 0x00000000,
639 0x00000000, 0x00000000, 0x00000000,
640 0x00000000, 0x00000000 }
641 }
642};
643
017310fb
CM		 644/*
645 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
646 * and I don't know what the third req is, but it's always zero. I assume it's
647 * some sort of update or set command to tell the DSP there's new volume info.
648 */
649#define DSP_VOL_OUT 0
650#define DSP_VOL_IN 1
651
652struct ct_dsp_volume_ctl {
653 hda_nid_t vnid;
654 int mid; /* module ID*/
655 unsigned int reqs[3]; /* scp req ID */
656};
657
862154bb 658static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 659 { .vnid = VNID_SPK,
660 .mid = 0x32,
661 .reqs = {3, 4, 2}
662 },
663 { .vnid = VNID_MIC,
664 .mid = 0x37,
665 .reqs = {2, 3, 1}
666 }
667};
668
95c6e9cb
IM		 669enum hda_cmd_vendor_io {
670 /* for DspIO node */
671 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
672 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
673
674 VENDOR_DSPIO_STATUS = 0xF01,
675 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
676 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
677 VENDOR_DSPIO_DSP_INIT = 0x703,
678 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
679 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
680
681 /* for ChipIO node */
682 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
683 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
684 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
685 VENDOR_CHIPIO_DATA_LOW = 0x300,
686 VENDOR_CHIPIO_DATA_HIGH = 0x400,
687
688 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
689 VENDOR_CHIPIO_STATUS = 0xF01,
690 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
691 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
692
4aa3bb0c
IM		 693 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
694 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
695
95c6e9cb 696 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 697 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 698
699 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
700 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
701 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
702 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
703 VENDOR_CHIPIO_FLAG_SET = 0x70F,
704 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 705 VENDOR_CHIPIO_PARAM_SET = 0x710,
706 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 707
708 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
709 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
710 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
711 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
712
4aa3bb0c
IM		 713 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
714 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
715 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
716 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
717
718 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
719 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
720 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
721 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
722 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
723 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
724
725 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 726};
727
728/*
729 * Control flag IDs
730 */
731enum control_flag_id {
732 /* Connection manager stream setup is bypassed/enabled */
733 CONTROL_FLAG_C_MGR = 0,
734 /* DSP DMA is bypassed/enabled */
735 CONTROL_FLAG_DMA = 1,
736 /* 8051 'idle' mode is disabled/enabled */
737 CONTROL_FLAG_IDLE_ENABLE = 2,
738 /* Tracker for the SPDIF-in path is bypassed/enabled */
739 CONTROL_FLAG_TRACKER = 3,
740 /* DigitalOut to Spdif2Out connection is disabled/enabled */
741 CONTROL_FLAG_SPDIF2OUT = 4,
742 /* Digital Microphone is disabled/enabled */
743 CONTROL_FLAG_DMIC = 5,
744 /* ADC_B rate is 48 kHz/96 kHz */
745 CONTROL_FLAG_ADC_B_96KHZ = 6,
746 /* ADC_C rate is 48 kHz/96 kHz */
747 CONTROL_FLAG_ADC_C_96KHZ = 7,
748 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
749 CONTROL_FLAG_DAC_96KHZ = 8,
750 /* DSP rate is 48 kHz/96 kHz */
751 CONTROL_FLAG_DSP_96KHZ = 9,
752 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
753 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
754 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
755 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
756 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
757 CONTROL_FLAG_DECODE_LOOP = 12,
758 /* De-emphasis filter on DAC-1 disabled/enabled */
759 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
760 /* De-emphasis filter on DAC-2 disabled/enabled */
761 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
762 /* De-emphasis filter on DAC-3 disabled/enabled */
763 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
764 /* High-pass filter on ADC_B disabled/enabled */
765 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
766 /* High-pass filter on ADC_C disabled/enabled */
767 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
768 /* Common mode on Port_A disabled/enabled */
769 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
770 /* Common mode on Port_D disabled/enabled */
771 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
772 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
773 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
774 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 775 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 776 /* ASI rate is 48kHz/96kHz */
777 CONTROL_FLAG_ASI_96KHZ = 22,
778 /* DAC power settings able to control attached ports no/yes */
779 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
780 /* Clock Stop OK reporting is disabled/enabled */
781 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
782 /* Number of control flags */
783 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
784};
785
786/*
787 * Control parameter IDs
788 */
4aa3bb0c 789enum control_param_id {
ef6b2ead
IM		 790 /* 0: None, 1: Mic1In*/
791 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 792 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
793 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 794 /* Port A output stage gain setting to use when 16 Ohm output
795 * impedance is selected*/
796 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
797 /* Port D output stage gain setting to use when 16 Ohm output
798 * impedance is selected*/
799 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 800
801 /* Stream Control */
802
803 /* Select stream with the given ID */
804 CONTROL_PARAM_STREAM_ID = 24,
805 /* Source connection point for the selected stream */
806 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
807 /* Destination connection point for the selected stream */
808 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
809 /* Number of audio channels in the selected stream */
810 CONTROL_PARAM_STREAMS_CHANNELS = 27,
811 /*Enable control for the selected stream */
812 CONTROL_PARAM_STREAM_CONTROL = 28,
813
814 /* Connection Point Control */
815
816 /* Select connection point with the given ID */
817 CONTROL_PARAM_CONN_POINT_ID = 29,
818 /* Connection point sample rate */
819 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
820
821 /* Node Control */
822
823 /* Select HDA node with the given ID */
824 CONTROL_PARAM_NODE_ID = 31
825};
826
827/*
828 * Dsp Io Status codes
829 */
830enum hda_vendor_status_dspio {
831 /* Success */
832 VENDOR_STATUS_DSPIO_OK = 0x00,
833 /* Busy, unable to accept new command, the host must retry */
834 VENDOR_STATUS_DSPIO_BUSY = 0x01,
835 /* SCP command queue is full */
836 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
837 /* SCP response queue is empty */
838 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
839};
840
841/*
842 * Chip Io Status codes
843 */
844enum hda_vendor_status_chipio {
845 /* Success */
846 VENDOR_STATUS_CHIPIO_OK = 0x00,
847 /* Busy, unable to accept new command, the host must retry */
848 VENDOR_STATUS_CHIPIO_BUSY = 0x01
849};
850
851/*
852 * CA0132 sample rate
853 */
854enum ca0132_sample_rate {
855 SR_6_000 = 0x00,
856 SR_8_000 = 0x01,
857 SR_9_600 = 0x02,
858 SR_11_025 = 0x03,
859 SR_16_000 = 0x04,
860 SR_22_050 = 0x05,
861 SR_24_000 = 0x06,
862 SR_32_000 = 0x07,
863 SR_44_100 = 0x08,
864 SR_48_000 = 0x09,
865 SR_88_200 = 0x0A,
866 SR_96_000 = 0x0B,
867 SR_144_000 = 0x0C,
868 SR_176_400 = 0x0D,
869 SR_192_000 = 0x0E,
870 SR_384_000 = 0x0F,
871
872 SR_COUNT = 0x10,
873
874 SR_RATE_UNKNOWN = 0x1F
875};
876
01ef7dbf
IM		 877enum dsp_download_state {
878 DSP_DOWNLOAD_FAILED = -1,
879 DSP_DOWNLOAD_INIT = 0,
880 DSP_DOWNLOADING = 1,
881 DSP_DOWNLOADED = 2
882};
883
01ef7dbf
IM		 884/* retrieve parameters from hda format */
885#define get_hdafmt_chs(fmt) (fmt & 0xf)
886#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
887#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
888#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
889
890/*
891 * CA0132 specific
892 */
893
894struct ca0132_spec {
b0eaa072 895 const struct snd_kcontrol_new *mixers[5];
a7e76271 896 unsigned int num_mixers;
5aaca44d
IM		 897 const struct hda_verb *base_init_verbs;
898 const struct hda_verb *base_exit_verbs;
d5c016b5 899 const struct hda_verb *chip_init_verbs;
e93ac30a 900 const struct hda_verb *sbz_init_verbs;
d5c016b5 901 struct hda_verb *spec_init_verbs;
01ef7dbf 902 struct auto_pin_cfg autocfg;
5aaca44d
IM		 903
904 /* Nodes configurations */
01ef7dbf
IM		 905 struct hda_multi_out multiout;
906 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
907 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 908 unsigned int num_outputs;
01ef7dbf
IM		 909 hda_nid_t input_pins[AUTO_PIN_LAST];
910 hda_nid_t adcs[AUTO_PIN_LAST];
911 hda_nid_t dig_out;
912 hda_nid_t dig_in;
913 unsigned int num_inputs;
a7e76271
IM		 914 hda_nid_t shared_mic_nid;
915 hda_nid_t shared_out_nid;
d5c016b5 916 hda_nid_t unsol_tag_hp;
63177afc 917 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 918 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 919
920 /* chip access */
921 struct mutex chipio_mutex; /* chip access mutex */
922 u32 curr_chip_addx;
923
924 /* DSP download related */
925 enum dsp_download_state dsp_state;
926 unsigned int dsp_stream_id;
927 unsigned int wait_scp;
928 unsigned int wait_scp_header;
929 unsigned int wait_num_data;
930 unsigned int scp_resp_header;
931 unsigned int scp_resp_data[4];
932 unsigned int scp_resp_count;
8a19bcee 933 bool alt_firmware_present;
38ba69ff 934 bool startup_check_entered;
e93ac30a 935 bool dsp_reload;
5aaca44d
IM		 936
937 /* mixer and effects related */
938 unsigned char dmic_ctl;
939 int cur_out_type;
940 int cur_mic_type;
941 long vnode_lvol[VNODES_COUNT];
942 long vnode_rvol[VNODES_COUNT];
943 long vnode_lswitch[VNODES_COUNT];
944 long vnode_rswitch[VNODES_COUNT];
945 long effects_switch[EFFECTS_COUNT];
946 long voicefx_val;
947 long cur_mic_boost;
7cb9d94c
CM		 948 /* ca0132_alt control related values */
949 unsigned char in_enum_val;
950 unsigned char out_enum_val;
47cdf76e
CM		 951 unsigned char mic_boost_enum_val;
952 unsigned char smart_volume_setting;
953 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
954 long xbass_xover_freq;
955 long eq_preset_val;
956 unsigned int tlv[4];
957 struct hda_vmaster_mute_hook vmaster_mute;
958
44f0c978 959
993884f6
CCC		 960 struct hda_codec *codec;
961 struct delayed_work unsol_hp_work;
d5c016b5 962 int quirk;
993884f6 963
44f0c978
IM		 964#ifdef ENABLE_TUNING_CONTROLS
965 long cur_ctl_vals[TUNING_CTLS_COUNT];
966#endif
aa31704f
CM		 967 /*
968 * Sound Blaster Z PCI region 2 iomem, used for input and output
969 * switching, and other unknown commands.
970 */
971 void __iomem *mem_base;
009b8f97
CM		 972
973 /*
974 * Whether or not to use the alt functions like alt_select_out,
975 * alt_select_in, etc. Only used on desktop codecs for now, because of
976 * surround sound support.
977 */
978 bool use_alt_functions;
47cdf76e
CM		 979
980 /*
981 * Whether or not to use alt controls: volume effect sliders, EQ
982 * presets, smart volume presets, and new control names with FX prefix.
983 * Renames PlayEnhancement and CrystalVoice too.
984 */
985 bool use_alt_controls;
01ef7dbf
IM		 986};
987
d5c016b5
GM		 988/*
989 * CA0132 quirks table
990 */
991enum {
992 QUIRK_NONE,
993 QUIRK_ALIENWARE,
a57a46b9 994 QUIRK_ALIENWARE_M17XR4,
8a19bcee
CM		 995 QUIRK_SBZ,
996 QUIRK_R3DI,
8f8c523c 997 QUIRK_R3D,
d5c016b5
GM		 998};
999
fe14f39e
TI		 1000static const struct hda_pintbl alienware_pincfgs[] = {
1001 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1002 { 0x0c, 0x411111f0 }, /* N/A */
1003 { 0x0d, 0x411111f0 }, /* N/A */
1004 { 0x0e, 0x411111f0 }, /* N/A */
1005 { 0x0f, 0x0321101f }, /* HP */
1006 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1007 { 0x11, 0x03a11021 }, /* Mic */
1008 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1009 { 0x13, 0x411111f0 }, /* N/A */
1010 { 0x18, 0x411111f0 }, /* N/A */
1011 {}
1012};
1013
63177afc
CM		 1014/* Sound Blaster Z pin configs taken from Windows Driver */
1015static const struct hda_pintbl sbz_pincfgs[] = {
1016 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1017 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1018 { 0x0d, 0x014510f0 }, /* Digital Out */
1019 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1020 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1021 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1022 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1023 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1024 { 0x13, 0x908700f0 }, /* What U Hear In*/
1025 { 0x18, 0x50d000f0 }, /* N/A */
1026 {}
1027};
1028
1029/* Recon3D integrated pin configs taken from Windows Driver */
1030static const struct hda_pintbl r3di_pincfgs[] = {
1031 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1032 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1033 { 0x0d, 0x014510f0 }, /* Digital Out */
1034 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1035 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1036 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1037 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1038 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1039 { 0x13, 0x908700f0 }, /* What U Hear In*/
1040 { 0x18, 0x500000f0 }, /* N/A */
1041 {}
1042};
1043
d5c016b5 1044static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1045 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1046 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1047 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1048 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1049 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1050 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1051 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1052 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1053 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
8f8c523c 1054 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
d5c016b5
GM		 1055 {}
1056};
1057
01ef7dbf
IM		 1058/*
1059 * CA0132 codec access
1060 */
399ae725 1061static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1062 unsigned int verb, unsigned int parm, unsigned int *res)
1063{
1064 unsigned int response;
1065 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1066 *res = response;
1067
1068 return ((response == -1) ? -1 : 0);
1069}
1070
1071static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1072 unsigned short converter_format, unsigned int *res)
1073{
1074 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1075 converter_format & 0xffff, res);
1076}
1077
1078static int codec_set_converter_stream_channel(struct hda_codec *codec,
1079 hda_nid_t nid, unsigned char stream,
1080 unsigned char channel, unsigned int *res)
1081{
1082 unsigned char converter_stream_channel = 0;
1083
1084 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1085 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1086 converter_stream_channel, res);
1087}
1088
1089/* Chip access helper function */
1090static int chipio_send(struct hda_codec *codec,
1091 unsigned int reg,
1092 unsigned int data)
1093{
1094 unsigned int res;
6d67530e 1095 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1096
1097 /* send bits of data specified by reg */
1098 do {
1099 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1100 reg, data);
1101 if (res == VENDOR_STATUS_CHIPIO_OK)
1102 return 0;
6d67530e
IM		 1103 msleep(20);
1104 } while (time_before(jiffies, timeout));
1105
01ef7dbf
IM		 1106 return -EIO;
1107}
1108
1109/*
1110 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1111 */
1112static int chipio_write_address(struct hda_codec *codec,
1113 unsigned int chip_addx)
1114{
4861af80 1115 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1116 int res;
1117
4861af80
IM		 1118 if (spec->curr_chip_addx == chip_addx)
1119 return 0;
1120
01ef7dbf
IM		 1121 /* send low 16 bits of the address */
1122 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1123 chip_addx & 0xffff);
1124
1125 if (res != -EIO) {
1126 /* send high 16 bits of the address */
1127 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1128 chip_addx >> 16);
1129 }
1130
d1600401 1131 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1132
4861af80 1133 return res;
01ef7dbf
IM		 1134}
1135
1136/*
1137 * Write data through the vendor widget -- NOT protected by the Mutex!
1138 */
01ef7dbf
IM		 1139static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1140{
5aaca44d 1141 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1142 int res;
1143
1144 /* send low 16 bits of the data */
1145 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1146
1147 if (res != -EIO) {
1148 /* send high 16 bits of the data */
1149 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1150 data >> 16);
1151 }
1152
5aaca44d
IM		 1153 /*If no error encountered, automatically increment the address
1154 as per chip behaviour*/
1155 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1156 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1157 return res;
1158}
1159
d5c21b88
IM		 1160/*
1161 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1162 */
01ef7dbf
IM		 1163static int chipio_write_data_multiple(struct hda_codec *codec,
1164 const u32 *data,
1165 unsigned int count)
1166{
1167 int status = 0;
1168
1169 if (data == NULL) {
4e76a883 1170 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1171 return -EINVAL;
1172 }
1173
1174 while ((count-- != 0) && (status == 0))
1175 status = chipio_write_data(codec, *data++);
1176
1177 return status;
1178}
1179
1180
1181/*
1182 * Read data through the vendor widget -- NOT protected by the Mutex!
1183 */
1184static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1185{
5aaca44d 1186 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1187 int res;
1188
1189 /* post read */
1190 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1191
1192 if (res != -EIO) {
1193 /* read status */
1194 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1195 }
1196
1197 if (res != -EIO) {
1198 /* read data */
1199 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1200 VENDOR_CHIPIO_HIC_READ_DATA,
1201 0);
1202 }
1203
5aaca44d
IM		 1204 /*If no error encountered, automatically increment the address
1205 as per chip behaviour*/
1206 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1207 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1208 return res;
1209}
1210
1211/*
1212 * Write given value to the given address through the chip I/O widget.
1213 * protected by the Mutex
1214 */
1215static int chipio_write(struct hda_codec *codec,
1216 unsigned int chip_addx, const unsigned int data)
1217{
1218 struct ca0132_spec *spec = codec->spec;
1219 int err;
1220
1221 mutex_lock(&spec->chipio_mutex);
1222
1223 /* write the address, and if successful proceed to write data */
1224 err = chipio_write_address(codec, chip_addx);
1225 if (err < 0)
1226 goto exit;
1227
1228 err = chipio_write_data(codec, data);
1229 if (err < 0)
1230 goto exit;
1231
1232exit:
1233 mutex_unlock(&spec->chipio_mutex);
1234 return err;
1235}
1236
38ba69ff
CM		 1237/*
1238 * Write given value to the given address through the chip I/O widget.
1239 * not protected by the Mutex
1240 */
1241static int chipio_write_no_mutex(struct hda_codec *codec,
1242 unsigned int chip_addx, const unsigned int data)
1243{
1244 int err;
1245
1246
1247 /* write the address, and if successful proceed to write data */
1248 err = chipio_write_address(codec, chip_addx);
1249 if (err < 0)
1250 goto exit;
1251
1252 err = chipio_write_data(codec, data);
1253 if (err < 0)
1254 goto exit;
1255
1256exit:
1257 return err;
1258}
1259
d5c21b88
IM		 1260/*
1261 * Write multiple values to the given address through the chip I/O widget.
1262 * protected by the Mutex
1263 */
01ef7dbf
IM		 1264static int chipio_write_multiple(struct hda_codec *codec,
1265 u32 chip_addx,
1266 const u32 *data,
1267 unsigned int count)
1268{
1269 struct ca0132_spec *spec = codec->spec;
1270 int status;
1271
1272 mutex_lock(&spec->chipio_mutex);
4861af80 1273 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1274 if (status < 0)
1275 goto error;
1276
1277 status = chipio_write_data_multiple(codec, data, count);
1278error:
1279 mutex_unlock(&spec->chipio_mutex);
1280
1281 return status;
1282}
1283
1284/*
1285 * Read the given address through the chip I/O widget
1286 * protected by the Mutex
1287 */
1288static int chipio_read(struct hda_codec *codec,
1289 unsigned int chip_addx, unsigned int *data)
1290{
1291 struct ca0132_spec *spec = codec->spec;
1292 int err;
1293
1294 mutex_lock(&spec->chipio_mutex);
1295
1296 /* write the address, and if successful proceed to write data */
1297 err = chipio_write_address(codec, chip_addx);
1298 if (err < 0)
1299 goto exit;
1300
1301 err = chipio_read_data(codec, data);
1302 if (err < 0)
1303 goto exit;
1304
1305exit:
1306 mutex_unlock(&spec->chipio_mutex);
1307 return err;
1308}
1309
d5c21b88
IM		 1310/*
1311 * Set chip control flags through the chip I/O widget.
1312 */
01ef7dbf
IM		 1313static void chipio_set_control_flag(struct hda_codec *codec,
1314 enum control_flag_id flag_id,
1315 bool flag_state)
1316{
1317 unsigned int val;
1318 unsigned int flag_bit;
1319
1320 flag_bit = (flag_state ? 1 : 0);
1321 val = (flag_bit << 7) | (flag_id);
1322 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1323 VENDOR_CHIPIO_FLAG_SET, val);
1324}
1325
d5c21b88
IM		 1326/*
1327 * Set chip parameters through the chip I/O widget.
1328 */
01ef7dbf
IM		 1329static void chipio_set_control_param(struct hda_codec *codec,
1330 enum control_param_id param_id, int param_val)
1331{
1332 struct ca0132_spec *spec = codec->spec;
1333 int val;
1334
1335 if ((param_id < 32) && (param_val < 8)) {
1336 val = (param_val << 5) | (param_id);
1337 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1338 VENDOR_CHIPIO_PARAM_SET, val);
1339 } else {
1340 mutex_lock(&spec->chipio_mutex);
1341 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1342 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1343 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1344 param_id);
1345 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1346 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1347 param_val);
1348 }
1349 mutex_unlock(&spec->chipio_mutex);
1350 }
1351}
1352
009b8f97
CM		 1353/*
1354 * Set chip parameters through the chip I/O widget. NO MUTEX.
1355 */
1356static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1357 enum control_param_id param_id, int param_val)
1358{
1359 int val;
1360
1361 if ((param_id < 32) && (param_val < 8)) {
1362 val = (param_val << 5) | (param_id);
1363 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1364 VENDOR_CHIPIO_PARAM_SET, val);
1365 } else {
1366 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1367 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1368 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1369 param_id);
1370 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1371 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1372 param_val);
1373 }
1374 }
1375}
38ba69ff
CM		 1376/*
1377 * Connect stream to a source point, and then connect
1378 * that source point to a destination point.
1379 */
1380static void chipio_set_stream_source_dest(struct hda_codec *codec,
1381 int streamid, int source_point, int dest_point)
1382{
1383 chipio_set_control_param_no_mutex(codec,
1384 CONTROL_PARAM_STREAM_ID, streamid);
1385 chipio_set_control_param_no_mutex(codec,
1386 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1387 chipio_set_control_param_no_mutex(codec,
1388 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1389}
1390
1391/*
1392 * Set number of channels in the selected stream.
1393 */
1394static void chipio_set_stream_channels(struct hda_codec *codec,
1395 int streamid, unsigned int channels)
1396{
1397 chipio_set_control_param_no_mutex(codec,
1398 CONTROL_PARAM_STREAM_ID, streamid);
1399 chipio_set_control_param_no_mutex(codec,
1400 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1401}
009b8f97
CM		 1402
1403/*
1404 * Enable/Disable audio stream.
1405 */
1406static void chipio_set_stream_control(struct hda_codec *codec,
1407 int streamid, int enable)
1408{
1409 chipio_set_control_param_no_mutex(codec,
1410 CONTROL_PARAM_STREAM_ID, streamid);
1411 chipio_set_control_param_no_mutex(codec,
1412 CONTROL_PARAM_STREAM_CONTROL, enable);
1413}
1414
38ba69ff
CM		 1415
1416/*
1417 * Set sampling rate of the connection point. NO MUTEX.
1418 */
1419static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1420 int connid, enum ca0132_sample_rate rate)
1421{
1422 chipio_set_control_param_no_mutex(codec,
1423 CONTROL_PARAM_CONN_POINT_ID, connid);
1424 chipio_set_control_param_no_mutex(codec,
1425 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1426}
1427
d5c21b88
IM		 1428/*
1429 * Set sampling rate of the connection point.
1430 */
01ef7dbf
IM		 1431static void chipio_set_conn_rate(struct hda_codec *codec,
1432 int connid, enum ca0132_sample_rate rate)
1433{
1434 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1435 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1436 rate);
1437}
1438
d5c21b88
IM		 1439/*
1440 * Enable clocks.
1441 */
01ef7dbf
IM		 1442static void chipio_enable_clocks(struct hda_codec *codec)
1443{
1444 struct ca0132_spec *spec = codec->spec;
1445
1446 mutex_lock(&spec->chipio_mutex);
1447 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1448 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1449 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1450 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1451 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1452 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1453 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1454 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1455 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1456 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1457 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1458 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1459 mutex_unlock(&spec->chipio_mutex);
1460}
1461
1462/*
1463 * CA0132 DSP IO stuffs
1464 */
1465static int dspio_send(struct hda_codec *codec, unsigned int reg,
1466 unsigned int data)
1467{
b645d796 1468 int res;
6d67530e 1469 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1470
1471 /* send bits of data specified by reg to dsp */
1472 do {
1473 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1474 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1475 return res;
6d67530e
IM		 1476 msleep(20);
1477 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1478
1479 return -EIO;
1480}
1481
d5c21b88
IM		 1482/*
1483 * Wait for DSP to be ready for commands
1484 */
01ef7dbf
IM		 1485static void dspio_write_wait(struct hda_codec *codec)
1486{
4861af80
IM		 1487 int status;
1488 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1489
01ef7dbf 1490 do {
4861af80
IM		 1491 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1492 VENDOR_DSPIO_STATUS, 0);
1493 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1494 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1495 break;
1496 msleep(1);
1497 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1498}
1499
d5c21b88
IM		 1500/*
1501 * Write SCP data to DSP
1502 */
01ef7dbf
IM		 1503static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1504{
1505 struct ca0132_spec *spec = codec->spec;
1506 int status;
1507
1508 dspio_write_wait(codec);
1509
1510 mutex_lock(&spec->chipio_mutex);
1511 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1512 scp_data & 0xffff);
1513 if (status < 0)
1514 goto error;
1515
1516 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1517 scp_data >> 16);
1518 if (status < 0)
1519 goto error;
1520
1521 /* OK, now check if the write itself has executed*/
1522 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1523 VENDOR_DSPIO_STATUS, 0);
1524error:
1525 mutex_unlock(&spec->chipio_mutex);
1526
1527 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1528 -EIO : 0;
1529}
1530
d5c21b88
IM		 1531/*
1532 * Write multiple SCP data to DSP
1533 */
01ef7dbf
IM		 1534static int dspio_write_multiple(struct hda_codec *codec,
1535 unsigned int *buffer, unsigned int size)
1536{
1537 int status = 0;
1538 unsigned int count;
1539
a16fbb85 1540 if (buffer == NULL)
01ef7dbf
IM		 1541 return -EINVAL;
1542
1543 count = 0;
1544 while (count < size) {
1545 status = dspio_write(codec, *buffer++);
1546 if (status != 0)
1547 break;
1548 count++;
1549 }
1550
1551 return status;
1552}
1553
a73d511c
IM		 1554static int dspio_read(struct hda_codec *codec, unsigned int *data)
1555{
1556 int status;
1557
1558 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1559 if (status == -EIO)
1560 return status;
1561
1562 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1563 if (status == -EIO ||
1564 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1565 return -EIO;
1566
1567 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1568 VENDOR_DSPIO_SCP_READ_DATA, 0);
1569
1570 return 0;
1571}
1572
1573static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1574 unsigned int *buf_size, unsigned int size_count)
1575{
1576 int status = 0;
1577 unsigned int size = *buf_size;
1578 unsigned int count;
1579 unsigned int skip_count;
1580 unsigned int dummy;
1581
a16fbb85 1582 if (buffer == NULL)
a73d511c
IM		 1583 return -1;
1584
1585 count = 0;
1586 while (count < size && count < size_count) {
1587 status = dspio_read(codec, buffer++);
1588 if (status != 0)
1589 break;
1590 count++;
1591 }
1592
1593 skip_count = count;
1594 if (status == 0) {
1595 while (skip_count < size) {
1596 status = dspio_read(codec, &dummy);
1597 if (status != 0)
1598 break;
1599 skip_count++;
1600 }
1601 }
1602 *buf_size = count;
1603
1604 return status;
1605}
1606
d5c21b88
IM		 1607/*
1608 * Construct the SCP header using corresponding fields
1609 */
01ef7dbf
IM		 1610static inline unsigned int
1611make_scp_header(unsigned int target_id, unsigned int source_id,
1612 unsigned int get_flag, unsigned int req,
1613 unsigned int device_flag, unsigned int resp_flag,
1614 unsigned int error_flag, unsigned int data_size)
1615{
1616 unsigned int header = 0;
1617
1618 header = (data_size & 0x1f) << 27;
1619 header |= (error_flag & 0x01) << 26;
1620 header |= (resp_flag & 0x01) << 25;
1621 header |= (device_flag & 0x01) << 24;
1622 header |= (req & 0x7f) << 17;
1623 header |= (get_flag & 0x01) << 16;
1624 header |= (source_id & 0xff) << 8;
1625 header |= target_id & 0xff;
1626
1627 return header;
1628}
1629
d5c21b88
IM		 1630/*
1631 * Extract corresponding fields from SCP header
1632 */
01ef7dbf
IM		 1633static inline void
1634extract_scp_header(unsigned int header,
1635 unsigned int *target_id, unsigned int *source_id,
1636 unsigned int *get_flag, unsigned int *req,
1637 unsigned int *device_flag, unsigned int *resp_flag,
1638 unsigned int *error_flag, unsigned int *data_size)
1639{
1640 if (data_size)
1641 *data_size = (header >> 27) & 0x1f;
1642 if (error_flag)
1643 *error_flag = (header >> 26) & 0x01;
1644 if (resp_flag)
1645 *resp_flag = (header >> 25) & 0x01;
1646 if (device_flag)
1647 *device_flag = (header >> 24) & 0x01;
1648 if (req)
1649 *req = (header >> 17) & 0x7f;
1650 if (get_flag)
1651 *get_flag = (header >> 16) & 0x01;
1652 if (source_id)
1653 *source_id = (header >> 8) & 0xff;
1654 if (target_id)
1655 *target_id = header & 0xff;
1656}
1657
1658#define SCP_MAX_DATA_WORDS (16)
1659
1660/* Structure to contain any SCP message */
1661struct scp_msg {
1662 unsigned int hdr;
1663 unsigned int data[SCP_MAX_DATA_WORDS];
1664};
1665
a73d511c
IM		 1666static void dspio_clear_response_queue(struct hda_codec *codec)
1667{
1668 unsigned int dummy = 0;
1669 int status = -1;
1670
1671 /* clear all from the response queue */
1672 do {
1673 status = dspio_read(codec, &dummy);
1674 } while (status == 0);
1675}
1676
1677static int dspio_get_response_data(struct hda_codec *codec)
1678{
1679 struct ca0132_spec *spec = codec->spec;
1680 unsigned int data = 0;
1681 unsigned int count;
1682
1683 if (dspio_read(codec, &data) < 0)
1684 return -EIO;
1685
1686 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1687 spec->scp_resp_header = data;
1688 spec->scp_resp_count = data >> 27;
1689 count = spec->wait_num_data;
1690 dspio_read_multiple(codec, spec->scp_resp_data,
1691 &spec->scp_resp_count, count);
1692 return 0;
1693 }
1694
1695 return -EIO;
1696}
1697
d5c21b88
IM		 1698/*
1699 * Send SCP message to DSP
1700 */
01ef7dbf
IM		 1701static int dspio_send_scp_message(struct hda_codec *codec,
1702 unsigned char *send_buf,
1703 unsigned int send_buf_size,
1704 unsigned char *return_buf,
1705 unsigned int return_buf_size,
1706 unsigned int *bytes_returned)
1707{
1708 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1709 int status = -1;
1710 unsigned int scp_send_size = 0;
1711 unsigned int total_size;
1712 bool waiting_for_resp = false;
1713 unsigned int header;
1714 struct scp_msg *ret_msg;
1715 unsigned int resp_src_id, resp_target_id;
1716 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1717
1718 if (bytes_returned)
1719 *bytes_returned = 0;
1720
1721 /* get scp header from buffer */
1722 header = *((unsigned int *)send_buf);
1723 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1724 &device_flag, NULL, NULL, &data_size);
1725 scp_send_size = data_size + 1;
1726 total_size = (scp_send_size * 4);
1727
1728 if (send_buf_size < total_size)
1729 return -EINVAL;
1730
1731 if (get_flag || device_flag) {
1732 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1733 return -EINVAL;
1734
1735 spec->wait_scp_header = *((unsigned int *)send_buf);
1736
1737 /* swap source id with target id */
1738 resp_target_id = src_id;
1739 resp_src_id = target_id;
1740 spec->wait_scp_header &= 0xffff0000;
1741 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1742 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1743 spec->wait_scp = 1;
1744 waiting_for_resp = true;
1745 }
1746
1747 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1748 scp_send_size);
1749 if (status < 0) {
1750 spec->wait_scp = 0;
1751 return status;
1752 }
1753
1754 if (waiting_for_resp) {
6d67530e 1755 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1756 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1757 do {
1758 msleep(20);
6d67530e 1759 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1760 waiting_for_resp = false;
6d67530e 1761 if (!spec->wait_scp) {
01ef7dbf
IM		 1762 ret_msg = (struct scp_msg *)return_buf;
1763 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1764 memcpy(&ret_msg->data, spec->scp_resp_data,
1765 spec->wait_num_data);
1766 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1767 status = 0;
1768 } else {
1769 status = -EIO;
1770 }
1771 spec->wait_scp = 0;
1772 }
1773
1774 return status;
1775}
1776
d5c21b88
IM		 1777/**
1778 * Prepare and send the SCP message to DSP
1779 * @codec: the HDA codec
1780 * @mod_id: ID of the DSP module to send the command
1781 * @req: ID of request to send to the DSP module
1782 * @dir: SET or GET
1783 * @data: pointer to the data to send with the request, request specific
1784 * @len: length of the data, in bytes
1785 * @reply: point to the buffer to hold data returned for a reply
1786 * @reply_len: length of the reply buffer returned from GET
1787 *
1788 * Returns zero or a negative error code.
1789 */
01ef7dbf 1790static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1791 int mod_id, int src_id, int req, int dir, const void *data,
1792 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1793{
1794 int status = 0;
1795 struct scp_msg scp_send, scp_reply;
1796 unsigned int ret_bytes, send_size, ret_size;
1797 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1798 unsigned int reply_data_size;
1799
1800 memset(&scp_send, 0, sizeof(scp_send));
1801 memset(&scp_reply, 0, sizeof(scp_reply));
1802
1803 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1804 return -EINVAL;
1805
1806 if (dir == SCP_GET && reply == NULL) {
4e76a883 1807 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1808 return -EINVAL;
1809 }
1810
1811 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1812 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1813 return -EINVAL;
1814 }
1815
447fd8e9 1816 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1817 0, 0, 0, len/sizeof(unsigned int));
1818 if (data != NULL && len > 0) {
1819 len = min((unsigned int)(sizeof(scp_send.data)), len);
1820 memcpy(scp_send.data, data, len);
1821 }
1822
1823 ret_bytes = 0;
1824 send_size = sizeof(unsigned int) + len;
1825 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1826 send_size, (unsigned char *)&scp_reply,
1827 sizeof(scp_reply), &ret_bytes);
1828
1829 if (status < 0) {
4e76a883 1830 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1831 return status;
1832 }
1833
1834 /* extract send and reply headers members */
1835 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1836 NULL, NULL, NULL, NULL, NULL);
1837 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1838 &reply_resp_flag, &reply_error_flag,
1839 &reply_data_size);
1840
1841 if (!send_get_flag)
1842 return 0;
1843
1844 if (reply_resp_flag && !reply_error_flag) {
1845 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1846 / sizeof(unsigned int);
1847
1848 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1849 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1850 return -EINVAL;
1851 } else if (ret_size != reply_data_size) {
4e76a883 1852 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1853 return -EINVAL;
46a049da
AB		 1854 } else if (!reply) {
1855 codec_dbg(codec, "NULL reply\n");
1856 return -EINVAL;
01ef7dbf
IM		 1857 } else {
1858 *reply_len = ret_size*sizeof(unsigned int);
1859 memcpy(reply, scp_reply.data, *reply_len);
1860 }
1861 } else {
4e76a883 1862 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1863 return -EIO;
1864 }
1865
1866 return status;
1867}
1868
5aaca44d
IM		 1869/*
1870 * Set DSP parameters
1871 */
1872static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 1873 int src_id, int req, const void *data, unsigned int len)
5aaca44d 1874{
447fd8e9
CM		 1875 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1876 NULL);
5aaca44d
IM		 1877}
1878
1879static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 1880 int req, const unsigned int data)
5aaca44d 1881{
447fd8e9
CM		 1882 return dspio_set_param(codec, mod_id, 0x20, req, &data,
1883 sizeof(unsigned int));
1884}
1885
1886static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1887 int req, const unsigned int data)
1888{
1889 return dspio_set_param(codec, mod_id, 0x00, req, &data,
1890 sizeof(unsigned int));
5aaca44d
IM		 1891}
1892
d5c21b88
IM		 1893/*
1894 * Allocate a DSP DMA channel via an SCP message
1895 */
01ef7dbf
IM		 1896static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1897{
1898 int status = 0;
1899 unsigned int size = sizeof(dma_chan);
1900
4e76a883 1901 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 1902 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1903 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1904 dma_chan, &size);
01ef7dbf
IM		 1905
1906 if (status < 0) {
4e76a883 1907 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1908 return status;
1909 }
1910
1911 if ((*dma_chan + 1) == 0) {
4e76a883 1912 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1913 return -EBUSY;
1914 }
1915
4e76a883
TI		 1916 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1917 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1918
1919 return status;
1920}
1921
d5c21b88
IM		 1922/*
1923 * Free a DSP DMA via an SCP message
1924 */
01ef7dbf
IM		 1925static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1926{
1927 int status = 0;
1928 unsigned int dummy = 0;
1929
4e76a883
TI		 1930 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1931 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 1932
447fd8e9
CM		 1933 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1934 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1935 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 1936
1937 if (status < 0) {
4e76a883 1938 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1939 return status;
1940 }
1941
4e76a883 1942 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1943
1944 return status;
1945}
1946
1947/*
d5c21b88 1948 * (Re)start the DSP
01ef7dbf
IM		 1949 */
1950static int dsp_set_run_state(struct hda_codec *codec)
1951{
1952 unsigned int dbg_ctrl_reg;
1953 unsigned int halt_state;
1954 int err;
1955
1956 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1957 if (err < 0)
1958 return err;
1959
1960 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1961 DSP_DBGCNTL_STATE_LOBIT;
1962
1963 if (halt_state != 0) {
1964 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1965 DSP_DBGCNTL_SS_MASK);
1966 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1967 dbg_ctrl_reg);
1968 if (err < 0)
1969 return err;
1970
1971 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1972 DSP_DBGCNTL_EXEC_MASK;
1973 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1974 dbg_ctrl_reg);
1975 if (err < 0)
1976 return err;
1977 }
1978
1979 return 0;
1980}
1981
d5c21b88
IM		 1982/*
1983 * Reset the DSP
1984 */
01ef7dbf
IM		 1985static int dsp_reset(struct hda_codec *codec)
1986{
1987 unsigned int res;
1988 int retry = 20;
1989
4e76a883 1990 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1991 do {
1992 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1993 retry--;
1994 } while (res == -EIO && retry);
1995
1996 if (!retry) {
4e76a883 1997 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1998 return -EIO;
1999 }
2000
2001 return 0;
2002}
2003
d5c21b88
IM		 2004/*
2005 * Convert chip address to DSP address
2006 */
01ef7dbf
IM		 2007static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2008 bool *code, bool *yram)
2009{
2010 *code = *yram = false;
2011
2012 if (UC_RANGE(chip_addx, 1)) {
2013 *code = true;
2014 return UC_OFF(chip_addx);
2015 } else if (X_RANGE_ALL(chip_addx, 1)) {
2016 return X_OFF(chip_addx);
2017 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2018 *yram = true;
2019 return Y_OFF(chip_addx);
2020 }
2021
4a8b89f9 2022 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2023}
2024
d5c21b88
IM		 2025/*
2026 * Check if the DSP DMA is active
2027 */
01ef7dbf
IM		 2028static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2029{
2030 unsigned int dma_chnlstart_reg;
2031
2032 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2033
2034 return ((dma_chnlstart_reg & (1 <<
2035 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2036}
2037
2038static int dsp_dma_setup_common(struct hda_codec *codec,
2039 unsigned int chip_addx,
2040 unsigned int dma_chan,
2041 unsigned int port_map_mask,
2042 bool ovly)
2043{
2044 int status = 0;
2045 unsigned int chnl_prop;
2046 unsigned int dsp_addx;
2047 unsigned int active;
2048 bool code, yram;
2049
4e76a883 2050 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2051
2052 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2053 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2054 return -EINVAL;
2055 }
2056
2057 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2058 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2059 return -EBUSY;
2060 }
2061
2062 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2063
2064 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2065 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2066 return -ENXIO;
2067 }
2068
2069 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2070 active = 0;
2071
4e76a883 2072 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2073
2074 if (ovly) {
2075 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2076 &chnl_prop);
2077
2078 if (status < 0) {
4e76a883 2079 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2080 return status;
2081 }
4e76a883 2082 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2083 }
2084
2085 if (!code)
2086 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2087 else
2088 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2089
2090 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2091
2092 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2093 if (status < 0) {
4e76a883 2094 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2095 return status;
2096 }
4e76a883 2097 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2098
2099 if (ovly) {
2100 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2101 &active);
2102
2103 if (status < 0) {
4e76a883 2104 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2105 return status;
2106 }
4e76a883 2107 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2108 }
2109
2110 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2111 DSPDMAC_ACTIVE_AAR_MASK;
2112
2113 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2114 if (status < 0) {
4e76a883 2115 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2116 return status;
2117 }
2118
4e76a883 2119 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2120
2121 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2122 port_map_mask);
2123 if (status < 0) {
4e76a883 2124 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2125 return status;
2126 }
4e76a883 2127 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2128
2129 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2130 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2131 if (status < 0) {
4e76a883 2132 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2133 return status;
2134 }
4e76a883 2135 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2136
4e76a883 2137 codec_dbg(codec,
01ef7dbf
IM		 2138 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2139 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2140 chip_addx, dsp_addx, dma_chan,
2141 port_map_mask, chnl_prop, active);
2142
4e76a883 2143 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2144
2145 return 0;
2146}
2147
d5c21b88
IM		 2148/*
2149 * Setup the DSP DMA per-transfer-specific registers
2150 */
01ef7dbf
IM		 2151static int dsp_dma_setup(struct hda_codec *codec,
2152 unsigned int chip_addx,
2153 unsigned int count,
2154 unsigned int dma_chan)
2155{
2156 int status = 0;
2157 bool code, yram;
2158 unsigned int dsp_addx;
2159 unsigned int addr_field;
2160 unsigned int incr_field;
2161 unsigned int base_cnt;
2162 unsigned int cur_cnt;
2163 unsigned int dma_cfg = 0;
2164 unsigned int adr_ofs = 0;
2165 unsigned int xfr_cnt = 0;
2166 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2167 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2168
4e76a883 2169 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2170
2171 if (count > max_dma_count) {
4e76a883 2172 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2173 return -EINVAL;
2174 }
2175
2176 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2177 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2178 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2179 return -ENXIO;
2180 }
2181
4e76a883 2182 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2183
2184 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2185 incr_field = 0;
2186
2187 if (!code) {
2188 addr_field <<= 1;
2189 if (yram)
2190 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2191
2192 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2193 }
2194
2195 dma_cfg = addr_field + incr_field;
2196 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2197 dma_cfg);
2198 if (status < 0) {
4e76a883 2199 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2200 return status;
2201 }
4e76a883 2202 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2203
2204 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2205 (code ? 0 : 1));
2206
2207 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2208 adr_ofs);
2209 if (status < 0) {
4e76a883 2210 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2211 return status;
2212 }
4e76a883 2213 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2214
2215 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2216
2217 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2218
2219 xfr_cnt = base_cnt | cur_cnt;
2220
2221 status = chipio_write(codec,
2222 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2223 if (status < 0) {
4e76a883 2224 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2225 return status;
2226 }
4e76a883 2227 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2228
4e76a883 2229 codec_dbg(codec,
01ef7dbf
IM		 2230 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2231 "ADROFS=0x%x, XFRCNT=0x%x\n",
2232 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2233
4e76a883 2234 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2235
2236 return 0;
2237}
2238
d5c21b88
IM		 2239/*
2240 * Start the DSP DMA
2241 */
01ef7dbf
IM		 2242static int dsp_dma_start(struct hda_codec *codec,
2243 unsigned int dma_chan, bool ovly)
2244{
2245 unsigned int reg = 0;
2246 int status = 0;
2247
4e76a883 2248 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2249
2250 if (ovly) {
2251 status = chipio_read(codec,
2252 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2253
2254 if (status < 0) {
4e76a883 2255 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2256 return status;
2257 }
4e76a883 2258 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2259
2260 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2261 DSPDMAC_CHNLSTART_DIS_MASK);
2262 }
2263
2264 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2265 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2266 if (status < 0) {
4e76a883 2267 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2268 return status;
2269 }
4e76a883 2270 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2271
2272 return status;
2273}
2274
d5c21b88
IM		 2275/*
2276 * Stop the DSP DMA
2277 */
01ef7dbf
IM		 2278static int dsp_dma_stop(struct hda_codec *codec,
2279 unsigned int dma_chan, bool ovly)
2280{
2281 unsigned int reg = 0;
2282 int status = 0;
2283
4e76a883 2284 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2285
2286 if (ovly) {
2287 status = chipio_read(codec,
2288 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2289
2290 if (status < 0) {
4e76a883 2291 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2292 return status;
2293 }
4e76a883 2294 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2295 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2296 DSPDMAC_CHNLSTART_DIS_MASK);
2297 }
2298
2299 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2300 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2301 if (status < 0) {
4e76a883 2302 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2303 return status;
2304 }
4e76a883 2305 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2306
2307 return status;
2308}
2309
d5c21b88
IM		 2310/**
2311 * Allocate router ports
2312 *
2313 * @codec: the HDA codec
2314 * @num_chans: number of channels in the stream
2315 * @ports_per_channel: number of ports per channel
2316 * @start_device: start device
2317 * @port_map: pointer to the port list to hold the allocated ports
2318 *
2319 * Returns zero or a negative error code.
2320 */
01ef7dbf
IM		 2321static int dsp_allocate_router_ports(struct hda_codec *codec,
2322 unsigned int num_chans,
2323 unsigned int ports_per_channel,
2324 unsigned int start_device,
2325 unsigned int *port_map)
2326{
2327 int status = 0;
2328 int res;
2329 u8 val;
2330
2331 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2332 if (status < 0)
2333 return status;
2334
2335 val = start_device << 6;
2336 val |= (ports_per_channel - 1) << 4;
2337 val |= num_chans - 1;
2338
2339 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2340 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2341 val);
2342
2343 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2344 VENDOR_CHIPIO_PORT_ALLOC_SET,
2345 MEM_CONNID_DSP);
2346
2347 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2348 if (status < 0)
2349 return status;
2350
2351 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2352 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2353
2354 *port_map = res;
2355
2356 return (res < 0) ? res : 0;
2357}
2358
d5c21b88
IM		 2359/*
2360 * Free router ports
2361 */
01ef7dbf
IM		 2362static int dsp_free_router_ports(struct hda_codec *codec)
2363{
2364 int status = 0;
2365
2366 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2367 if (status < 0)
2368 return status;
2369
2370 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2371 VENDOR_CHIPIO_PORT_FREE_SET,
2372 MEM_CONNID_DSP);
2373
2374 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2375
2376 return status;
2377}
2378
d5c21b88
IM		 2379/*
2380 * Allocate DSP ports for the download stream
2381 */
01ef7dbf
IM		 2382static int dsp_allocate_ports(struct hda_codec *codec,
2383 unsigned int num_chans,
2384 unsigned int rate_multi, unsigned int *port_map)
2385{
2386 int status;
2387
4e76a883 2388 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2389
2390 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2391 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2392 return -EINVAL;
2393 }
2394
2395 status = dsp_allocate_router_ports(codec, num_chans,
2396 rate_multi, 0, port_map);
2397
4e76a883 2398 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2399
2400 return status;
2401}
2402
01ef7dbf
IM		 2403static int dsp_allocate_ports_format(struct hda_codec *codec,
2404 const unsigned short fmt,
2405 unsigned int *port_map)
2406{
2407 int status;
2408 unsigned int num_chans;
2409
2410 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2411 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2412 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2413
2414 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2415 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2416 return -EINVAL;
2417 }
2418
2419 num_chans = get_hdafmt_chs(fmt) + 1;
2420
2421 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2422
2423 return status;
2424}
2425
d5c21b88
IM		 2426/*
2427 * free DSP ports
2428 */
2429static int dsp_free_ports(struct hda_codec *codec)
2430{
2431 int status;
2432
4e76a883 2433 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2434
2435 status = dsp_free_router_ports(codec);
2436 if (status < 0) {
4e76a883 2437 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2438 return status;
2439 }
4e76a883 2440 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2441
2442 return status;
2443}
2444
01ef7dbf
IM		 2445/*
2446 * HDA DMA engine stuffs for DSP code download
2447 */
2448struct dma_engine {
2449 struct hda_codec *codec;
2450 unsigned short m_converter_format;
2451 struct snd_dma_buffer *dmab;
2452 unsigned int buf_size;
2453};
2454
2455
2456enum dma_state {
2457 DMA_STATE_STOP = 0,
2458 DMA_STATE_RUN = 1
2459};
2460
6194b99d 2461static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2462 unsigned int sample_rate,
2463 unsigned short channels,
01ef7dbf
IM		 2464 unsigned short *hda_format)
2465{
2466 unsigned int format_val;
2467
b7d023e1
TI		 2468 format_val = snd_hdac_calc_stream_format(sample_rate,
2469 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2470
2471 if (hda_format)
2472 *hda_format = (unsigned short)format_val;
2473
2474 return 0;
2475}
2476
d5c21b88
IM		 2477/*
2478 * Reset DMA for DSP download
2479 */
01ef7dbf
IM		 2480static int dma_reset(struct dma_engine *dma)
2481{
2482 struct hda_codec *codec = dma->codec;
2483 struct ca0132_spec *spec = codec->spec;
2484 int status;
2485
b3667bd7 2486 if (dma->dmab->area)
01ef7dbf
IM		 2487 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2488
2489 status = snd_hda_codec_load_dsp_prepare(codec,
2490 dma->m_converter_format,
2491 dma->buf_size,
2492 dma->dmab);
2493 if (status < 0)
2494 return status;
2495 spec->dsp_stream_id = status;
2496 return 0;
2497}
2498
2499static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2500{
01ef7dbf
IM		 2501 bool cmd;
2502
01ef7dbf
IM		 2503 switch (state) {
2504 case DMA_STATE_STOP:
2505 cmd = false;
2506 break;
2507 case DMA_STATE_RUN:
2508 cmd = true;
2509 break;
2510 default:
c41999a2
DH		 2511 return 0;
2512 }
01ef7dbf
IM		 2513
2514 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2515 return 0;
95c6e9cb
IM		 2516}
2517
01ef7dbf
IM		 2518static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2519{
2520 return dma->dmab->bytes;
2521}
95c6e9cb 2522
01ef7dbf
IM		 2523static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2524{
2525 return dma->dmab->area;
2526}
95c6e9cb 2527
01ef7dbf
IM		 2528static int dma_xfer(struct dma_engine *dma,
2529 const unsigned int *data,
2530 unsigned int count)
2531{
2532 memcpy(dma->dmab->area, data, count);
2533 return 0;
2534}
95c6e9cb 2535
01ef7dbf
IM		 2536static void dma_get_converter_format(
2537 struct dma_engine *dma,
2538 unsigned short *format)
2539{
2540 if (format)
2541 *format = dma->m_converter_format;
2542}
95c6e9cb 2543
01ef7dbf 2544static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2545{
01ef7dbf 2546 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2547
01ef7dbf 2548 return spec->dsp_stream_id;
95c6e9cb
IM		 2549}
2550
01ef7dbf
IM		 2551struct dsp_image_seg {
2552 u32 magic;
2553 u32 chip_addr;
2554 u32 count;
2555 u32 data[0];
2556};
2557
2558static const u32 g_magic_value = 0x4c46584d;
2559static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2560
2561static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2562{
01ef7dbf
IM		 2563 return p->magic == g_magic_value;
2564}
95c6e9cb 2565
01ef7dbf
IM		 2566static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2567{
2568 return g_chip_addr_magic_value == p->chip_addr;
2569}
95c6e9cb 2570
01ef7dbf
IM		 2571static bool is_last(const struct dsp_image_seg *p)
2572{
2573 return p->count == 0;
2574}
95c6e9cb 2575
01ef7dbf
IM		 2576static size_t dsp_sizeof(const struct dsp_image_seg *p)
2577{
2578 return sizeof(*p) + p->count*sizeof(u32);
2579}
2580
2581static const struct dsp_image_seg *get_next_seg_ptr(
2582 const struct dsp_image_seg *p)
2583{
2584 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2585}
2586
2587/*
01ef7dbf 2588 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2589 */
8ae3124b 2590#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2591
d5c21b88
IM		 2592/*
2593 * Program a list of address/data pairs via the ChipIO widget.
2594 * The segment data is in the format of successive pairs of words.
2595 * These are repeated as indicated by the segment's count field.
2596 */
01ef7dbf
IM		 2597static int dspxfr_hci_write(struct hda_codec *codec,
2598 const struct dsp_image_seg *fls)
95c6e9cb 2599{
01ef7dbf
IM		 2600 int status;
2601 const u32 *data;
2602 unsigned int count;
95c6e9cb 2603
01ef7dbf 2604 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2605 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2606 return -EINVAL;
95c6e9cb
IM		 2607 }
2608
01ef7dbf
IM		 2609 count = fls->count;
2610 data = (u32 *)(fls->data);
2611 while (count >= 2) {
2612 status = chipio_write(codec, data[0], data[1]);
2613 if (status < 0) {
4e76a883 2614 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2615 return status;
2616 }
2617 count -= 2;
2618 data += 2;
2619 }
2620 return 0;
95c6e9cb
IM		 2621}
2622
d5c21b88
IM		 2623/**
2624 * Write a block of data into DSP code or data RAM using pre-allocated
2625 * DMA engine.
2626 *
2627 * @codec: the HDA codec
2628 * @fls: pointer to a fast load image
2629 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2630 * no relocation
2631 * @dma_engine: pointer to DMA engine to be used for DSP download
2632 * @dma_chan: The number of DMA channels used for DSP download
2633 * @port_map_mask: port mapping
2634 * @ovly: TRUE if overlay format is required
2635 *
2636 * Returns zero or a negative error code.
2637 */
01ef7dbf
IM		 2638static int dspxfr_one_seg(struct hda_codec *codec,
2639 const struct dsp_image_seg *fls,
2640 unsigned int reloc,
2641 struct dma_engine *dma_engine,
2642 unsigned int dma_chan,
2643 unsigned int port_map_mask,
2644 bool ovly)
95c6e9cb 2645{
406261ce 2646 int status = 0;
01ef7dbf
IM		 2647 bool comm_dma_setup_done = false;
2648 const unsigned int *data;
2649 unsigned int chip_addx;
2650 unsigned int words_to_write;
2651 unsigned int buffer_size_words;
2652 unsigned char *buffer_addx;
2653 unsigned short hda_format;
2654 unsigned int sample_rate_div;
2655 unsigned int sample_rate_mul;
2656 unsigned int num_chans;
2657 unsigned int hda_frame_size_words;
2658 unsigned int remainder_words;
2659 const u32 *data_remainder;
2660 u32 chip_addx_remainder;
2661 unsigned int run_size_words;
2662 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2663 unsigned long timeout;
2664 bool dma_active;
01ef7dbf
IM		 2665
2666 if (fls == NULL)
2667 return -EINVAL;
2668 if (is_hci_prog_list_seg(fls)) {
2669 hci_write = fls;
2670 fls = get_next_seg_ptr(fls);
2671 }
95c6e9cb 2672
01ef7dbf 2673 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2674 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2675 return dspxfr_hci_write(codec, hci_write);
2676 }
95c6e9cb 2677
01ef7dbf 2678 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2679 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2680 return -EINVAL;
95c6e9cb
IM		 2681 }
2682
01ef7dbf
IM		 2683 data = fls->data;
2684 chip_addx = fls->chip_addr,
2685 words_to_write = fls->count;
2686
2687 if (!words_to_write)
2688 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2689 if (reloc)
2690 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2691
2692 if (!UC_RANGE(chip_addx, words_to_write) &&
2693 !X_RANGE_ALL(chip_addx, words_to_write) &&
2694 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2695 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2696 return -EINVAL;
95c6e9cb
IM		 2697 }
2698
01ef7dbf
IM		 2699 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2700 sizeof(u32);
2701
2702 buffer_addx = dma_get_buffer_addr(dma_engine);
2703
2704 if (buffer_addx == NULL) {
4e76a883 2705 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2706 return -EINVAL;
2707 }
2708
2709 dma_get_converter_format(dma_engine, &hda_format);
2710 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2711 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2712 num_chans = get_hdafmt_chs(hda_format) + 1;
2713
2714 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2715 (num_chans * sample_rate_mul / sample_rate_div));
2716
3bc085a1 2717 if (hda_frame_size_words == 0) {
4e76a883 2718 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2719 return -EINVAL;
2720 }
2721
01ef7dbf
IM		 2722 buffer_size_words = min(buffer_size_words,
2723 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2724 65536 : 32768));
2725 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2726 codec_dbg(codec,
01ef7dbf
IM		 2727 "chpadr=0x%08x frmsz=%u nchan=%u "
2728 "rate_mul=%u div=%u bufsz=%u\n",
2729 chip_addx, hda_frame_size_words, num_chans,
2730 sample_rate_mul, sample_rate_div, buffer_size_words);
2731
3bc085a1 2732 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2733 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2734 return -EINVAL;
2735 }
2736
2737 remainder_words = words_to_write % hda_frame_size_words;
2738 data_remainder = data;
2739 chip_addx_remainder = chip_addx;
2740
2741 data += remainder_words;
2742 chip_addx += remainder_words*sizeof(u32);
2743 words_to_write -= remainder_words;
2744
2745 while (words_to_write != 0) {
2746 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2747 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2748 words_to_write, run_size_words, remainder_words);
2749 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2750 if (!comm_dma_setup_done) {
2751 status = dsp_dma_stop(codec, dma_chan, ovly);
2752 if (status < 0)
425a7880 2753 return status;
01ef7dbf
IM		 2754 status = dsp_dma_setup_common(codec, chip_addx,
2755 dma_chan, port_map_mask, ovly);
2756 if (status < 0)
2757 return status;
2758 comm_dma_setup_done = true;
2759 }
2760
2761 status = dsp_dma_setup(codec, chip_addx,
2762 run_size_words, dma_chan);
2763 if (status < 0)
2764 return status;
2765 status = dsp_dma_start(codec, dma_chan, ovly);
2766 if (status < 0)
2767 return status;
2768 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2769 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2770 return -EIO;
2771 }
2772 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2773 if (status < 0)
2774 return status;
2775 if (remainder_words != 0) {
2776 status = chipio_write_multiple(codec,
2777 chip_addx_remainder,
2778 data_remainder,
2779 remainder_words);
b3667bd7
TI		 2780 if (status < 0)
2781 return status;
01ef7dbf
IM		 2782 remainder_words = 0;
2783 }
2784 if (hci_write) {
2785 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2786 if (status < 0)
2787 return status;
01ef7dbf
IM		 2788 hci_write = NULL;
2789 }
6d67530e
IM		 2790
2791 timeout = jiffies + msecs_to_jiffies(2000);
2792 do {
2793 dma_active = dsp_is_dma_active(codec, dma_chan);
2794 if (!dma_active)
01ef7dbf 2795 break;
6d67530e
IM		 2796 msleep(20);
2797 } while (time_before(jiffies, timeout));
2798 if (dma_active)
2799 break;
2800
4e76a883 2801 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2802 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2803 status = dma_reset(dma_engine);
01ef7dbf
IM		 2804
2805 if (status < 0)
2806 return status;
2807
2808 data += run_size_words;
2809 chip_addx += run_size_words*sizeof(u32);
2810 words_to_write -= run_size_words;
2811 }
2812
2813 if (remainder_words != 0) {
2814 status = chipio_write_multiple(codec, chip_addx_remainder,
2815 data_remainder, remainder_words);
2816 }
2817
2818 return status;
95c6e9cb
IM		 2819}
2820
d5c21b88
IM		 2821/**
2822 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2823 *
2824 * @codec: the HDA codec
2825 * @fls_data: pointer to a fast load image
2826 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2827 * no relocation
e97249dd 2828 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2829 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2830 * @ovly: TRUE if overlay format is required
2831 *
2832 * Returns zero or a negative error code.
2833 */
01ef7dbf
IM		 2834static int dspxfr_image(struct hda_codec *codec,
2835 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2836 unsigned int reloc,
2837 unsigned int sample_rate,
2838 unsigned short channels,
01ef7dbf 2839 bool ovly)
95c6e9cb
IM		 2840{
2841 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2842 int status;
2843 unsigned short hda_format = 0;
2844 unsigned int response;
2845 unsigned char stream_id = 0;
2846 struct dma_engine *dma_engine;
2847 unsigned int dma_chan;
2848 unsigned int port_map_mask;
2849
2850 if (fls_data == NULL)
2851 return -EINVAL;
2852
2853 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2854 if (!dma_engine)
2855 return -ENOMEM;
95c6e9cb 2856
01ef7dbf
IM		 2857 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2858 if (!dma_engine->dmab) {
549e8292
TI		 2859 kfree(dma_engine);
2860 return -ENOMEM;
01ef7dbf 2861 }
95c6e9cb 2862
01ef7dbf 2863 dma_engine->codec = codec;
6194b99d 2864 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2865 dma_engine->m_converter_format = hda_format;
2866 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2867 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2868
8ae3124b 2869 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2870
2871 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2872 hda_format, &response);
2873
2874 if (status < 0) {
4e76a883 2875 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2876 goto exit;
2877 }
2878
2879 status = snd_hda_codec_load_dsp_prepare(codec,
2880 dma_engine->m_converter_format,
2881 dma_engine->buf_size,
2882 dma_engine->dmab);
2883 if (status < 0)
95c6e9cb 2884 goto exit;
01ef7dbf
IM		 2885 spec->dsp_stream_id = status;
2886
2887 if (ovly) {
2888 status = dspio_alloc_dma_chan(codec, &dma_chan);
2889 if (status < 0) {
4e76a883 2890 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2891 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2892 goto exit;
2893 }
2894 }
95c6e9cb 2895
01ef7dbf
IM		 2896 port_map_mask = 0;
2897 status = dsp_allocate_ports_format(codec, hda_format,
2898 &port_map_mask);
2899 if (status < 0) {
4e76a883 2900 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2901 goto exit;
2902 }
2903
2904 stream_id = dma_get_stream_id(dma_engine);
2905 status = codec_set_converter_stream_channel(codec,
2906 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2907 if (status < 0) {
4e76a883 2908 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2909 goto exit;
2910 }
2911
2912 while ((fls_data != NULL) && !is_last(fls_data)) {
2913 if (!is_valid(fls_data)) {
4e76a883 2914 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2915 status = -EINVAL;
2916 goto exit;
2917 }
2918 status = dspxfr_one_seg(codec, fls_data, reloc,
2919 dma_engine, dma_chan,
2920 port_map_mask, ovly);
2921 if (status < 0)
2922 break;
2923
2924 if (is_hci_prog_list_seg(fls_data))
2925 fls_data = get_next_seg_ptr(fls_data);
2926
2927 if ((fls_data != NULL) && !is_last(fls_data))
2928 fls_data = get_next_seg_ptr(fls_data);
2929 }
2930
2931 if (port_map_mask != 0)
2932 status = dsp_free_ports(codec);
2933
2934 if (status < 0)
95c6e9cb
IM		 2935 goto exit;
2936
01ef7dbf
IM		 2937 status = codec_set_converter_stream_channel(codec,
2938 WIDGET_CHIP_CTRL, 0, 0, &response);
2939
95c6e9cb 2940exit:
01ef7dbf
IM		 2941 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2942 dspio_free_dma_chan(codec, dma_chan);
2943
b3667bd7 2944 if (dma_engine->dmab->area)
01ef7dbf
IM		 2945 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2946 kfree(dma_engine->dmab);
2947 kfree(dma_engine);
2948
2949 return status;
95c6e9cb
IM		 2950}
2951
2952/*
01ef7dbf 2953 * CA0132 DSP download stuffs.
95c6e9cb 2954 */
01ef7dbf 2955static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2956{
009b8f97 2957 struct ca0132_spec *spec = codec->spec;
4e76a883 2958 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 2959 if (!spec->use_alt_functions) {
2960 /*set DSP speaker to 2.0 configuration*/
2961 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2962 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2963
009b8f97
CM		 2964 /*update write pointer*/
2965 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2966 }
01ef7dbf 2967}
95c6e9cb 2968
d5c21b88 2969/**
e60b2c7f 2970 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2971 *
2972 * @codec: the HDA codec
2973 * @fls: pointer to a fast load image
2974 * @ovly: TRUE if overlay format is required
2975 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2976 * no relocation
2977 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2978 * @router_chans: number of audio router channels to be allocated (0 means use
2979 * internal defaults; max is 32)
2980 *
e60b2c7f
TI		 2981 * Download DSP from a DSP Image Fast Load structure. This structure is a
2982 * linear, non-constant sized element array of structures, each of which
2983 * contain the count of the data to be loaded, the data itself, and the
2984 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2985 * Returns zero or a negative error code.
2986 */
01ef7dbf
IM		 2987static int dspload_image(struct hda_codec *codec,
2988 const struct dsp_image_seg *fls,
2989 bool ovly,
2990 unsigned int reloc,
2991 bool autostart,
2992 int router_chans)
2993{
2994 int status = 0;
e97249dd
IM		 2995 unsigned int sample_rate;
2996 unsigned short channels;
01ef7dbf 2997
4e76a883 2998 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2999 if (router_chans == 0) {
3000 if (!ovly)
3001 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3002 else
3003 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3004 }
95c6e9cb 3005
e97249dd
IM		 3006 sample_rate = 48000;
3007 channels = (unsigned short)router_chans;
01ef7dbf 3008
e97249dd
IM		 3009 while (channels > 16) {
3010 sample_rate *= 2;
3011 channels /= 2;
01ef7dbf
IM		 3012 }
3013
01ef7dbf 3014 do {
4e76a883 3015 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3016 if (!ovly)
3017 status = dsp_reset(codec);
3018
3019 if (status < 0)
3020 break;
3021
4e76a883 3022 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3023 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3024 ovly);
01ef7dbf
IM		 3025
3026 if (status < 0)
3027 break;
3028
4e76a883 3029 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3030 if (autostart && !ovly) {
3031 dspload_post_setup(codec);
3032 status = dsp_set_run_state(codec);
3033 }
3034
4e76a883 3035 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3036 } while (0);
3037
3038 return status;
3039}
3040
f664417e 3041#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3042static bool dspload_is_loaded(struct hda_codec *codec)
3043{
3044 unsigned int data = 0;
3045 int status = 0;
3046
3047 status = chipio_read(codec, 0x40004, &data);
3048 if ((status < 0) || (data != 1))
3049 return false;
3050
3051 return true;
3052}
f664417e
TI		 3053#else
3054#define dspload_is_loaded(codec) false
3055#endif
01ef7dbf
IM		 3056
3057static bool dspload_wait_loaded(struct hda_codec *codec)
3058{
6d67530e 3059 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3060
3061 do {
01ef7dbf 3062 if (dspload_is_loaded(codec)) {
d9684bb5 3063 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3064 return true;
3065 }
6d67530e
IM		 3066 msleep(20);
3067 } while (time_before(jiffies, timeout));
01ef7dbf 3068
d9684bb5 3069 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3070 return false;
95c6e9cb
IM		 3071}
3072
e93ac30a
CM		 3073/*
3074 * Setup GPIO for the other variants of Core3D.
3075 */
3076
a62e4739
CM		 3077/*
3078 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3079 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3080 * The first eight bits are just the number of the pin. So far, I've only seen
3081 * this number go to 7.
3082 */
3083static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3084 bool enable)
3085{
3086 struct ca0132_spec *spec = codec->spec;
3087 unsigned short gpio_data;
3088
3089 gpio_data = gpio_pin & 0xF;
3090 gpio_data |= ((enable << 8) & 0x100);
3091
3092 writew(gpio_data, spec->mem_base + 0x320);
3093}
3094
e93ac30a
CM		 3095/*
3096 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3097 * the card shows as having no GPIO pins.
3098 */
3099static void ca0132_gpio_init(struct hda_codec *codec)
3100{
3101 struct ca0132_spec *spec = codec->spec;
3102
3103 switch (spec->quirk) {
3104 case QUIRK_SBZ:
3105 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3106 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3107 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3108 break;
3109 case QUIRK_R3DI:
3110 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3111 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3112 break;
3113 }
3114
3115}
3116
3117/* Sets the GPIO for audio output. */
3118static void ca0132_gpio_setup(struct hda_codec *codec)
3119{
3120 struct ca0132_spec *spec = codec->spec;
3121
3122 switch (spec->quirk) {
3123 case QUIRK_SBZ:
3124 snd_hda_codec_write(codec, 0x01, 0,
3125 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3126 snd_hda_codec_write(codec, 0x01, 0,
3127 AC_VERB_SET_GPIO_MASK, 0x07);
3128 snd_hda_codec_write(codec, 0x01, 0,
3129 AC_VERB_SET_GPIO_DATA, 0x04);
3130 snd_hda_codec_write(codec, 0x01, 0,
3131 AC_VERB_SET_GPIO_DATA, 0x06);
3132 break;
3133 case QUIRK_R3DI:
3134 snd_hda_codec_write(codec, 0x01, 0,
3135 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3136 snd_hda_codec_write(codec, 0x01, 0,
3137 AC_VERB_SET_GPIO_MASK, 0x1F);
3138 snd_hda_codec_write(codec, 0x01, 0,
3139 AC_VERB_SET_GPIO_DATA, 0x0C);
3140 break;
3141 }
3142}
3143
7e6ed62e
CM		 3144/*
3145 * GPIO control functions for the Recon3D integrated.
3146 */
3147
3148enum r3di_gpio_bit {
3149 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3150 R3DI_MIC_SELECT_BIT = 1,
3151 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3152 R3DI_OUT_SELECT_BIT = 2,
3153 /*
3154 * I dunno what this actually does, but it stays on until the dsp
3155 * is downloaded.
3156 */
3157 R3DI_GPIO_DSP_DOWNLOADING = 3,
3158 /*
3159 * Same as above, no clue what it does, but it comes on after the dsp
3160 * is downloaded.
3161 */
3162 R3DI_GPIO_DSP_DOWNLOADED = 4
3163};
3164
3165enum r3di_mic_select {
3166 /* Set GPIO bit 1 to 0 for rear mic */
3167 R3DI_REAR_MIC = 0,
3168 /* Set GPIO bit 1 to 1 for front microphone*/
3169 R3DI_FRONT_MIC = 1
3170};
3171
3172enum r3di_out_select {
3173 /* Set GPIO bit 2 to 0 for headphone */
3174 R3DI_HEADPHONE_OUT = 0,
3175 /* Set GPIO bit 2 to 1 for speaker */
3176 R3DI_LINE_OUT = 1
3177};
3178enum r3di_dsp_status {
3179 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3180 R3DI_DSP_DOWNLOADING = 0,
3181 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3182 R3DI_DSP_DOWNLOADED = 1
3183};
3184
7cb9d94c
CM		 3185
3186static void r3di_gpio_mic_set(struct hda_codec *codec,
3187 enum r3di_mic_select cur_mic)
3188{
3189 unsigned int cur_gpio;
3190
3191 /* Get the current GPIO Data setup */
3192 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3193
3194 switch (cur_mic) {
3195 case R3DI_REAR_MIC:
3196 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3197 break;
3198 case R3DI_FRONT_MIC:
3199 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3200 break;
3201 }
3202 snd_hda_codec_write(codec, codec->core.afg, 0,
3203 AC_VERB_SET_GPIO_DATA, cur_gpio);
3204}
3205
3206static void r3di_gpio_out_set(struct hda_codec *codec,
3207 enum r3di_out_select cur_out)
3208{
3209 unsigned int cur_gpio;
3210
3211 /* Get the current GPIO Data setup */
3212 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3213
3214 switch (cur_out) {
3215 case R3DI_HEADPHONE_OUT:
3216 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3217 break;
3218 case R3DI_LINE_OUT:
3219 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3220 break;
3221 }
3222 snd_hda_codec_write(codec, codec->core.afg, 0,
3223 AC_VERB_SET_GPIO_DATA, cur_gpio);
3224}
3225
7e6ed62e
CM		 3226static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3227 enum r3di_dsp_status dsp_status)
3228{
3229 unsigned int cur_gpio;
3230
3231 /* Get the current GPIO Data setup */
3232 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3233
3234 switch (dsp_status) {
3235 case R3DI_DSP_DOWNLOADING:
3236 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3237 snd_hda_codec_write(codec, codec->core.afg, 0,
3238 AC_VERB_SET_GPIO_DATA, cur_gpio);
3239 break;
3240 case R3DI_DSP_DOWNLOADED:
3241 /* Set DOWNLOADING bit to 0. */
3242 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3243
3244 snd_hda_codec_write(codec, codec->core.afg, 0,
3245 AC_VERB_SET_GPIO_DATA, cur_gpio);
3246
3247 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3248 break;
3249 }
3250
3251 snd_hda_codec_write(codec, codec->core.afg, 0,
3252 AC_VERB_SET_GPIO_DATA, cur_gpio);
3253}
3254
825315bc
IM		 3255/*
3256 * PCM callbacks
3257 */
95c6e9cb
IM		 3258static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3259 struct hda_codec *codec,
3260 unsigned int stream_tag,
3261 unsigned int format,
3262 struct snd_pcm_substream *substream)
3263{
3264 struct ca0132_spec *spec = codec->spec;
825315bc 3265
28fba950 3266 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3267
3268 return 0;
95c6e9cb
IM		 3269}
3270
3271static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3272 struct hda_codec *codec,
3273 struct snd_pcm_substream *substream)
3274{
3275 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3276
3277 if (spec->dsp_state == DSP_DOWNLOADING)
3278 return 0;
3279
3280 /*If Playback effects are on, allow stream some time to flush
3281 *effects tail*/
3282 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3283 msleep(50);
3284
28fba950 3285 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3286
3287 return 0;
95c6e9cb
IM		 3288}
3289
e8412ca4
DR		 3290static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3291 struct hda_codec *codec,
3292 struct snd_pcm_substream *substream)
3293{
3294 struct ca0132_spec *spec = codec->spec;
3295 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3296 struct snd_pcm_runtime *runtime = substream->runtime;
3297
3298 if (spec->dsp_state != DSP_DOWNLOADED)
3299 return 0;
3300
3301 /* Add latency if playback enhancement and either effect is enabled. */
3302 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3303 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3304 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3305 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3306 }
3307
3308 /* Applying Speaker EQ adds latency as well. */
3309 if (spec->cur_out_type == SPEAKER_OUT)
3310 latency += DSP_SPEAKER_OUT_LATENCY;
3311
3312 return (latency * runtime->rate) / 1000;
3313}
3314
95c6e9cb
IM		 3315/*
3316 * Digital out
3317 */
27ebeb0b
TI		 3318static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3319 struct hda_codec *codec,
3320 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3321{
3322 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3323 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3324}
3325
27ebeb0b 3326static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3327 struct hda_codec *codec,
3328 unsigned int stream_tag,
3329 unsigned int format,
3330 struct snd_pcm_substream *substream)
3331{
3332 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3333 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3334 stream_tag, format, substream);
95c6e9cb
IM		 3335}
3336
27ebeb0b 3337static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3338 struct hda_codec *codec,
95c6e9cb
IM		 3339 struct snd_pcm_substream *substream)
3340{
3341 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3342 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3343}
3344
27ebeb0b
TI		 3345static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3346 struct hda_codec *codec,
3347 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3348{
3349 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3350 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3351}
3352
825315bc
IM		 3353/*
3354 * Analog capture
3355 */
3356static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3357 struct hda_codec *codec,
3358 unsigned int stream_tag,
3359 unsigned int format,
3360 struct snd_pcm_substream *substream)
3361{
13c12dbe 3362 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3363 stream_tag, 0, format);
825315bc
IM		 3364
3365 return 0;
3366}
3367
3368static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3369 struct hda_codec *codec,
3370 struct snd_pcm_substream *substream)
3371{
3372 struct ca0132_spec *spec = codec->spec;
3373
3374 if (spec->dsp_state == DSP_DOWNLOADING)
3375 return 0;
3376
28fba950 3377 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3378 return 0;
3379}
3380
e8412ca4
DR		 3381static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3382 struct hda_codec *codec,
3383 struct snd_pcm_substream *substream)
3384{
3385 struct ca0132_spec *spec = codec->spec;
3386 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3387 struct snd_pcm_runtime *runtime = substream->runtime;
3388
3389 if (spec->dsp_state != DSP_DOWNLOADED)
3390 return 0;
3391
3392 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3393 latency += DSP_CRYSTAL_VOICE_LATENCY;
3394
3395 return (latency * runtime->rate) / 1000;
3396}
3397
e90f29e4
IM		 3398/*
3399 * Controls stuffs.
3400 */
3401
3402/*
3403 * Mixer controls helpers.
3404 */
3405#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3406 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3407 .name = xname, \
3408 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3409 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3410 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3411 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3412 .info = ca0132_volume_info, \
3413 .get = ca0132_volume_get, \
3414 .put = ca0132_volume_put, \
3415 .tlv = { .c = ca0132_volume_tlv }, \
3416 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3417
017310fb
CM		 3418/*
3419 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3420 * volume put, which is used for setting the DSP volume. This was done because
3421 * the ca0132 functions were taking too much time and causing lag.
3422 */
3423#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3424 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3425 .name = xname, \
3426 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3427 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3428 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3429 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3430 .info = snd_hda_mixer_amp_volume_info, \
3431 .get = snd_hda_mixer_amp_volume_get, \
3432 .put = ca0132_alt_volume_put, \
3433 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3434 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3435
e90f29e4
IM		 3436#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3437 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3438 .name = xname, \
3439 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3440 .info = snd_hda_mixer_amp_switch_info, \
3441 .get = ca0132_switch_get, \
3442 .put = ca0132_switch_put, \
3443 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3444
3445/* stereo */
3446#define CA0132_CODEC_VOL(xname, nid, dir) \
3447 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3448#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3449 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3450#define CA0132_CODEC_MUTE(xname, nid, dir) \
3451 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3452
017310fb
CM		 3453/* lookup tables */
3454/*
3455 * Lookup table with decibel values for the DSP. When volume is changed in
3456 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3457 * these values have decimal points, probably because the Windows driver
3458 * actually uses floating point. We can't here, so I made a lookup table of
3459 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3460 * DAC's, and 9 is the maximum.
3461 */
3462static const unsigned int float_vol_db_lookup[] = {
34630xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
34640xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
34650xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
34660xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
34670xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
34680xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
34690xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
34700xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
34710xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
34720xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
34730xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
34740xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
34750xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
34760xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
34770xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
34780x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
34790x40C00000, 0x40E00000, 0x41000000, 0x41100000
3480};
3481
47cdf76e
CM		 3482/*
3483 * This table counts from float 0 to 1 in increments of .01, which is
3484 * useful for a few different sliders.
3485 */
3486static const unsigned int float_zero_to_one_lookup[] = {
34870x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
34880x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
34890x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
34900x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
34910x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
34920x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
34930x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
34940x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
34950x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
34960x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
34970x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
34980x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
34990x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
35000x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
35010x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
35020x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
35030x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3504};
3505
3506/*
3507 * This table counts from float 10 to 1000, which is the range of the x-bass
3508 * crossover slider in Windows.
3509 */
3510static const unsigned int float_xbass_xover_lookup[] = {
35110x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
35120x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
35130x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
35140x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
35150x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
35160x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
35170x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
35180x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
35190x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
35200x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
35210x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
35220x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
35230x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
35240x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
35250x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
35260x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
35270x44728000, 0x44750000, 0x44778000, 0x447A0000
3528};
3529
4091fb95 3530/* The following are for tuning of products */
44f0c978
IM		 3531#ifdef ENABLE_TUNING_CONTROLS
3532
3533static unsigned int voice_focus_vals_lookup[] = {
35340x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
35350x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
35360x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
35370x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
35380x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
35390x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
35400x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
35410x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
35420x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
35430x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
35440x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
35450x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
35460x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
35470x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
35480x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
35490x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
35500x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
35510x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
35520x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
35530x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
35540x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
35550x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
35560x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
35570x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
35580x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
35590x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
35600x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3561};
3562
3563static unsigned int mic_svm_vals_lookup[] = {
35640x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
35650x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
35660x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
35670x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
35680x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
35690x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
35700x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
35710x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
35720x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
35730x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
35740x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
35750x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
35760x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
35770x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
35780x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
35790x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
35800x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3581};
3582
3583static unsigned int equalizer_vals_lookup[] = {
35840xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
35850xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
35860xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
35870xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
35880x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
35890x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
35900x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
35910x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
35920x41C00000
3593};
3594
3595static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3596 unsigned int *lookup, int idx)
3597{
3598 int i = 0;
3599
3600 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3601 if (nid == ca0132_tuning_ctls[i].nid)
3602 break;
3603
3604 snd_hda_power_up(codec);
447fd8e9 3605 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3606 ca0132_tuning_ctls[i].req,
3607 &(lookup[idx]), sizeof(unsigned int));
3608 snd_hda_power_down(codec);
3609
3610 return 1;
3611}
3612
3613static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3614 struct snd_ctl_elem_value *ucontrol)
3615{
3616 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3617 struct ca0132_spec *spec = codec->spec;
3618 hda_nid_t nid = get_amp_nid(kcontrol);
3619 long *valp = ucontrol->value.integer.value;
3620 int idx = nid - TUNING_CTL_START_NID;
3621
3622 *valp = spec->cur_ctl_vals[idx];
3623 return 0;
3624}
3625
3626static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3627 struct snd_ctl_elem_info *uinfo)
3628{
3629 int chs = get_amp_channels(kcontrol);
3630 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3631 uinfo->count = chs == 3 ? 2 : 1;
3632 uinfo->value.integer.min = 20;
3633 uinfo->value.integer.max = 180;
3634 uinfo->value.integer.step = 1;
3635
3636 return 0;
3637}
3638
3639static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3640 struct snd_ctl_elem_value *ucontrol)
3641{
3642 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3643 struct ca0132_spec *spec = codec->spec;
3644 hda_nid_t nid = get_amp_nid(kcontrol);
3645 long *valp = ucontrol->value.integer.value;
3646 int idx;
3647
3648 idx = nid - TUNING_CTL_START_NID;
3649 /* any change? */
3650 if (spec->cur_ctl_vals[idx] == *valp)
3651 return 0;
3652
3653 spec->cur_ctl_vals[idx] = *valp;
3654
3655 idx = *valp - 20;
3656 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3657
3658 return 1;
3659}
3660
3661static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3662 struct snd_ctl_elem_info *uinfo)
3663{
3664 int chs = get_amp_channels(kcontrol);
3665 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3666 uinfo->count = chs == 3 ? 2 : 1;
3667 uinfo->value.integer.min = 0;
3668 uinfo->value.integer.max = 100;
3669 uinfo->value.integer.step = 1;
3670
3671 return 0;
3672}
3673
3674static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3675 struct snd_ctl_elem_value *ucontrol)
3676{
3677 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3678 struct ca0132_spec *spec = codec->spec;
3679 hda_nid_t nid = get_amp_nid(kcontrol);
3680 long *valp = ucontrol->value.integer.value;
3681 int idx;
3682
3683 idx = nid - TUNING_CTL_START_NID;
3684 /* any change? */
3685 if (spec->cur_ctl_vals[idx] == *valp)
3686 return 0;
3687
3688 spec->cur_ctl_vals[idx] = *valp;
3689
3690 idx = *valp;
3691 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3692
3693 return 0;
3694}
3695
3696static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3697 struct snd_ctl_elem_info *uinfo)
3698{
3699 int chs = get_amp_channels(kcontrol);
3700 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3701 uinfo->count = chs == 3 ? 2 : 1;
3702 uinfo->value.integer.min = 0;
3703 uinfo->value.integer.max = 48;
3704 uinfo->value.integer.step = 1;
3705
3706 return 0;
3707}
3708
3709static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3710 struct snd_ctl_elem_value *ucontrol)
3711{
3712 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3713 struct ca0132_spec *spec = codec->spec;
3714 hda_nid_t nid = get_amp_nid(kcontrol);
3715 long *valp = ucontrol->value.integer.value;
3716 int idx;
3717
3718 idx = nid - TUNING_CTL_START_NID;
3719 /* any change? */
3720 if (spec->cur_ctl_vals[idx] == *valp)
3721 return 0;
3722
3723 spec->cur_ctl_vals[idx] = *valp;
3724
3725 idx = *valp;
3726 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3727
3728 return 1;
3729}
3730
8e142e9e
TS		 3731static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3732static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3733
3734static int add_tuning_control(struct hda_codec *codec,
3735 hda_nid_t pnid, hda_nid_t nid,
3736 const char *name, int dir)
3737{
975cc02a 3738 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3739 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3740 struct snd_kcontrol_new knew =
3741 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3742
3743 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3744 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3745 knew.tlv.c = 0;
3746 knew.tlv.p = 0;
3747 switch (pnid) {
3748 case VOICE_FOCUS:
3749 knew.info = voice_focus_ctl_info;
3750 knew.get = tuning_ctl_get;
3751 knew.put = voice_focus_ctl_put;
3752 knew.tlv.p = voice_focus_db_scale;
3753 break;
3754 case MIC_SVM:
3755 knew.info = mic_svm_ctl_info;
3756 knew.get = tuning_ctl_get;
3757 knew.put = mic_svm_ctl_put;
3758 break;
3759 case EQUALIZER:
3760 knew.info = equalizer_ctl_info;
3761 knew.get = tuning_ctl_get;
3762 knew.put = equalizer_ctl_put;
3763 knew.tlv.p = eq_db_scale;
3764 break;
3765 default:
3766 return 0;
3767 }
3768 knew.private_value =
3769 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3770 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3771 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3772}
3773
3774static int add_tuning_ctls(struct hda_codec *codec)
3775{
3776 int i;
3777 int err;
3778
3779 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3780 err = add_tuning_control(codec,
3781 ca0132_tuning_ctls[i].parent_nid,
3782 ca0132_tuning_ctls[i].nid,
3783 ca0132_tuning_ctls[i].name,
3784 ca0132_tuning_ctls[i].direct);
3785 if (err < 0)
3786 return err;
3787 }
3788
3789 return 0;
3790}
3791
3792static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3793{
3794 struct ca0132_spec *spec = codec->spec;
3795 int i;
3796
3797 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3798 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3799 /* SVM level defaults to 0.74. */
3800 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3801
3802 /* EQ defaults to 0dB. */
3803 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3804 spec->cur_ctl_vals[i] = 24;
3805}
3806#endif /*ENABLE_TUNING_CONTROLS*/
3807
5aaca44d
IM		 3808/*
3809 * Select the active output.
3810 * If autodetect is enabled, output will be selected based on jack detection.
3811 * If jack inserted, headphone will be selected, else built-in speakers
3812 * If autodetect is disabled, output will be selected based on selection.
3813 */
3814static int ca0132_select_out(struct hda_codec *codec)
3815{
3816 struct ca0132_spec *spec = codec->spec;
3817 unsigned int pin_ctl;
3818 int jack_present;
3819 int auto_jack;
3820 unsigned int tmp;
3821 int err;
3822
4e76a883 3823 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3824
664c7155 3825 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3826
3827 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3828
3829 if (auto_jack)
fe14f39e 3830 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3831 else
3832 jack_present =
3833 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3834
3835 if (jack_present)
3836 spec->cur_out_type = HEADPHONE_OUT;
3837 else
3838 spec->cur_out_type = SPEAKER_OUT;
3839
3840 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3841 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3842 /*speaker out config*/
3843 tmp = FLOAT_ONE;
3844 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3845 if (err < 0)
3846 goto exit;
3847 /*enable speaker EQ*/
3848 tmp = FLOAT_ONE;
3849 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3850 if (err < 0)
3851 goto exit;
3852
3853 /* Setup EAPD */
3854 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3855 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3856 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3857 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3858 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3859 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3860 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3861 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3862
3863 /* disable headphone node */
3864 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3865 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3866 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3867 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3868 /* enable speaker node */
3869 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 3870 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3871 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3872 pin_ctl | PIN_OUT);
5aaca44d 3873 } else {
4e76a883 3874 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3875 /*headphone out config*/
3876 tmp = FLOAT_ZERO;
3877 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3878 if (err < 0)
3879 goto exit;
3880 /*disable speaker EQ*/
3881 tmp = FLOAT_ZERO;
3882 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3883 if (err < 0)
3884 goto exit;
3885
3886 /* Setup EAPD */
3887 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3888 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3889 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3890 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3891 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3892 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3893 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3894 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3895
3896 /* disable speaker*/
3897 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3898 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3899 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3900 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3901 /* enable headphone*/
3902 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3903 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3904 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3905 pin_ctl | PIN_HP);
5aaca44d
IM		 3906 }
3907
3908exit:
664c7155 3909 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3910
3911 return err < 0 ? err : 0;
3912}
3913
7cb9d94c
CM		 3914/*
3915 * This function behaves similarly to the ca0132_select_out funciton above,
3916 * except with a few differences. It adds the ability to select the current
3917 * output with an enumerated control "output source" if the auto detect
3918 * mute switch is set to off. If the auto detect mute switch is enabled, it
3919 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3920 * It also adds the ability to auto-detect the front headphone port. The only
3921 * way to select surround is to disable auto detect, and set Surround with the
3922 * enumerated control.
3923 */
3924static int ca0132_alt_select_out(struct hda_codec *codec)
3925{
3926 struct ca0132_spec *spec = codec->spec;
3927 unsigned int pin_ctl;
3928 int jack_present;
3929 int auto_jack;
3930 unsigned int i;
3931 unsigned int tmp;
3932 int err;
3933 /* Default Headphone is rear headphone */
3934 hda_nid_t headphone_nid = spec->out_pins[1];
3935
3936 codec_dbg(codec, "%s\n", __func__);
3937
3938 snd_hda_power_up_pm(codec);
3939
3940 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3941
3942 /*
3943 * If headphone rear or front is plugged in, set to headphone.
3944 * If neither is plugged in, set to rear line out. Only if
3945 * hp/speaker auto detect is enabled.
3946 */
3947 if (auto_jack) {
3948 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3949 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3950
3951 if (jack_present)
3952 spec->cur_out_type = HEADPHONE_OUT;
3953 else
3954 spec->cur_out_type = SPEAKER_OUT;
3955 } else
3956 spec->cur_out_type = spec->out_enum_val;
3957
3958 /* Begin DSP output switch */
3959 tmp = FLOAT_ONE;
3960 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3961 if (err < 0)
3962 goto exit;
3963
3964 switch (spec->cur_out_type) {
3965 case SPEAKER_OUT:
3966 codec_dbg(codec, "%s speaker\n", __func__);
3967 /*speaker out config*/
3968 switch (spec->quirk) {
3969 case QUIRK_SBZ:
a62e4739
CM		 3970 ca0132_mmio_gpio_set(codec, 7, false);
3971 ca0132_mmio_gpio_set(codec, 4, true);
3972 ca0132_mmio_gpio_set(codec, 1, true);
7cb9d94c
CM		 3973 chipio_set_control_param(codec, 0x0D, 0x18);
3974 break;
3975 case QUIRK_R3DI:
3976 chipio_set_control_param(codec, 0x0D, 0x24);
3977 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3978 break;
3979 }
3980
3981 /* disable headphone node */
3982 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3983 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3984 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3985 pin_ctl & ~PIN_HP);
3986 /* enable line-out node */
3987 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3988 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3989 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3990 pin_ctl | PIN_OUT);
3991 /* Enable EAPD */
3992 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3993 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
3994
3995 /* If PlayEnhancement is enabled, set different source */
3996 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3997 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
3998 else
3999 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4000 break;
4001 case HEADPHONE_OUT:
4002 codec_dbg(codec, "%s hp\n", __func__);
4003 /* Headphone out config*/
4004 switch (spec->quirk) {
4005 case QUIRK_SBZ:
a62e4739
CM		 4006 ca0132_mmio_gpio_set(codec, 7, true);
4007 ca0132_mmio_gpio_set(codec, 4, true);
4008 ca0132_mmio_gpio_set(codec, 1, false);
7cb9d94c
CM		 4009 chipio_set_control_param(codec, 0x0D, 0x12);
4010 break;
4011 case QUIRK_R3DI:
4012 chipio_set_control_param(codec, 0x0D, 0x21);
4013 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4014 break;
4015 }
4016
4017 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4018 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4019
4020 /* disable speaker*/
4021 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4022 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4023 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4024 pin_ctl & ~PIN_HP);
4025
4026 /* enable headphone, either front or rear */
4027
4028 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4029 headphone_nid = spec->out_pins[2];
4030 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4031 headphone_nid = spec->out_pins[1];
4032
4033 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4034 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4035 snd_hda_set_pin_ctl(codec, headphone_nid,
4036 pin_ctl | PIN_HP);
4037
4038 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4039 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4040 else
4041 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4042 break;
4043 case SURROUND_OUT:
4044 codec_dbg(codec, "%s surround\n", __func__);
4045 /* Surround out config*/
4046 switch (spec->quirk) {
4047 case QUIRK_SBZ:
a62e4739
CM		 4048 ca0132_mmio_gpio_set(codec, 7, false);
4049 ca0132_mmio_gpio_set(codec, 4, true);
4050 ca0132_mmio_gpio_set(codec, 1, true);
7cb9d94c
CM		 4051 chipio_set_control_param(codec, 0x0D, 0x18);
4052 break;
4053 case QUIRK_R3DI:
4054 chipio_set_control_param(codec, 0x0D, 0x24);
4055 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4056 break;
4057 }
4058 /* enable line out node */
4059 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4060 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4061 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4062 pin_ctl | PIN_OUT);
4063 /* Disable headphone out */
4064 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4065 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4066 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4067 pin_ctl & ~PIN_HP);
4068 /* Enable EAPD on line out */
4069 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4070 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4071 /* enable center/lfe out node */
4072 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4073 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4074 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4075 pin_ctl | PIN_OUT);
4076 /* Now set rear surround node as out. */
4077 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4078 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4079 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4080 pin_ctl | PIN_OUT);
4081
4082 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4083 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4084 else
4085 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4086 break;
4087 }
4088
4089 /* run through the output dsp commands for line-out */
4090 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4091 err = dspio_set_uint_param(codec,
4092 alt_out_presets[spec->cur_out_type].mids[i],
4093 alt_out_presets[spec->cur_out_type].reqs[i],
4094 alt_out_presets[spec->cur_out_type].vals[i]);
4095
4096 if (err < 0)
4097 goto exit;
4098 }
4099
4100exit:
4101 snd_hda_power_down_pm(codec);
4102
4103 return err < 0 ? err : 0;
4104}
4105
993884f6
CCC		 4106static void ca0132_unsol_hp_delayed(struct work_struct *work)
4107{
4108 struct ca0132_spec *spec = container_of(
4109 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4110 struct hda_jack_tbl *jack;
4111
7cb9d94c
CM		 4112 if (spec->use_alt_functions)
4113 ca0132_alt_select_out(spec->codec);
4114 else
4115 ca0132_select_out(spec->codec);
4116
d5c016b5 4117 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4118 if (jack) {
4119 jack->block_report = 0;
4120 snd_hda_jack_report_sync(spec->codec);
4121 }
993884f6
CCC		 4122}
4123
5aaca44d
IM		 4124static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4125static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4126static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
e0026d03
CM		 4127static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4128static int stop_mic1(struct hda_codec *codec);
4129static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4130static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4131
4132/*
4133 * Select the active VIP source
4134 */
4135static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4136{
4137 struct ca0132_spec *spec = codec->spec;
4138 unsigned int tmp;
4139
e8f1bd5d 4140 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4141 return 0;
4142
4143 /* if CrystalVoice if off, vipsource should be 0 */
4144 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4145 (val == 0)) {
4146 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4147 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4148 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4149 if (spec->cur_mic_type == DIGITAL_MIC)
4150 tmp = FLOAT_TWO;
4151 else
4152 tmp = FLOAT_ONE;
4153 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4154 tmp = FLOAT_ZERO;
4155 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4156 } else {
4157 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4158 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4159 if (spec->cur_mic_type == DIGITAL_MIC)
4160 tmp = FLOAT_TWO;
4161 else
4162 tmp = FLOAT_ONE;
4163 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4164 tmp = FLOAT_ONE;
4165 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4166 msleep(20);
4167 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4168 }
4169
4170 return 1;
4171}
4172
e0026d03
CM		 4173static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4174{
4175 struct ca0132_spec *spec = codec->spec;
4176 unsigned int tmp;
4177
4178 if (spec->dsp_state != DSP_DOWNLOADED)
4179 return 0;
4180
4181 codec_dbg(codec, "%s\n", __func__);
4182
4183 chipio_set_stream_control(codec, 0x03, 0);
4184 chipio_set_stream_control(codec, 0x04, 0);
4185
4186 /* if CrystalVoice is off, vipsource should be 0 */
4187 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4188 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4189 codec_dbg(codec, "%s: off.", __func__);
4190 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4191
4192 tmp = FLOAT_ZERO;
4193 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4194
4195 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4196 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4197 if (spec->quirk == QUIRK_R3DI)
4198 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4199
4200
4201 if (spec->in_enum_val == REAR_LINE_IN)
4202 tmp = FLOAT_ZERO;
4203 else {
4204 if (spec->quirk == QUIRK_SBZ)
4205 tmp = FLOAT_THREE;
4206 else
4207 tmp = FLOAT_ONE;
4208 }
4209
4210 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4211
4212 } else {
4213 codec_dbg(codec, "%s: on.", __func__);
4214 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4215 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4216 if (spec->quirk == QUIRK_R3DI)
4217 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4218
4219 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4220 tmp = FLOAT_TWO;
4221 else
4222 tmp = FLOAT_ONE;
4223 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4224
4225 tmp = FLOAT_ONE;
4226 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4227
4228 msleep(20);
4229 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4230 }
4231
4232 chipio_set_stream_control(codec, 0x03, 1);
4233 chipio_set_stream_control(codec, 0x04, 1);
4234
4235 return 1;
4236}
4237
5aaca44d
IM		 4238/*
4239 * Select the active microphone.
4240 * If autodetect is enabled, mic will be selected based on jack detection.
4241 * If jack inserted, ext.mic will be selected, else built-in mic
4242 * If autodetect is disabled, mic will be selected based on selection.
4243 */
4244static int ca0132_select_mic(struct hda_codec *codec)
4245{
4246 struct ca0132_spec *spec = codec->spec;
4247 int jack_present;
4248 int auto_jack;
4249
4e76a883 4250 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4251
664c7155 4252 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4253
4254 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4255
4256 if (auto_jack)
fe14f39e 4257 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4258 else
4259 jack_present =
4260 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4261
4262 if (jack_present)
4263 spec->cur_mic_type = LINE_MIC_IN;
4264 else
4265 spec->cur_mic_type = DIGITAL_MIC;
4266
4267 if (spec->cur_mic_type == DIGITAL_MIC) {
4268 /* enable digital Mic */
4269 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4270 ca0132_set_dmic(codec, 1);
4271 ca0132_mic_boost_set(codec, 0);
4272 /* set voice focus */
4273 ca0132_effects_set(codec, VOICE_FOCUS,
4274 spec->effects_switch
4275 [VOICE_FOCUS - EFFECT_START_NID]);
4276 } else {
4277 /* disable digital Mic */
4278 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4279 ca0132_set_dmic(codec, 0);
4280 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4281 /* disable voice focus */
4282 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4283 }
4284
664c7155 4285 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4286
4287 return 0;
4288}
4289
7cb9d94c
CM		 4290/*
4291 * Select the active input.
4292 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4293 * The front mic has no jack-detection, so the only way to switch to it
4294 * is to do it manually in alsamixer.
4295 */
4296static int ca0132_alt_select_in(struct hda_codec *codec)
4297{
4298 struct ca0132_spec *spec = codec->spec;
4299 unsigned int tmp;
4300
4301 codec_dbg(codec, "%s\n", __func__);
4302
4303 snd_hda_power_up_pm(codec);
4304
4305 chipio_set_stream_control(codec, 0x03, 0);
4306 chipio_set_stream_control(codec, 0x04, 0);
4307
4308 spec->cur_mic_type = spec->in_enum_val;
4309
4310 switch (spec->cur_mic_type) {
4311 case REAR_MIC:
4312 switch (spec->quirk) {
4313 case QUIRK_SBZ:
a62e4739 4314 ca0132_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4315 tmp = FLOAT_THREE;
4316 break;
4317 case QUIRK_R3DI:
4318 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4319 tmp = FLOAT_ONE;
4320 break;
4321 default:
4322 tmp = FLOAT_ONE;
4323 break;
4324 }
4325
4326 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4327 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4328 if (spec->quirk == QUIRK_R3DI)
4329 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4330
4331 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4332
4333 chipio_set_stream_control(codec, 0x03, 1);
4334 chipio_set_stream_control(codec, 0x04, 1);
4335
4336 if (spec->quirk == QUIRK_SBZ) {
4337 chipio_write(codec, 0x18B098, 0x0000000C);
4338 chipio_write(codec, 0x18B09C, 0x0000000C);
4339 }
47cdf76e 4340 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4341 break;
4342 case REAR_LINE_IN:
4343 ca0132_mic_boost_set(codec, 0);
4344 switch (spec->quirk) {
4345 case QUIRK_SBZ:
a62e4739 4346 ca0132_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4347 break;
4348 case QUIRK_R3DI:
4349 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4350 break;
4351 }
4352
4353 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4354 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4355 if (spec->quirk == QUIRK_R3DI)
4356 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4357
4358 tmp = FLOAT_ZERO;
4359 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4360
4361 if (spec->quirk == QUIRK_SBZ) {
4362 chipio_write(codec, 0x18B098, 0x00000000);
4363 chipio_write(codec, 0x18B09C, 0x00000000);
4364 }
4365
4366 chipio_set_stream_control(codec, 0x03, 1);
4367 chipio_set_stream_control(codec, 0x04, 1);
4368 break;
4369 case FRONT_MIC:
4370 switch (spec->quirk) {
4371 case QUIRK_SBZ:
a62e4739
CM		 4372 ca0132_mmio_gpio_set(codec, 0, true);
4373 ca0132_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4374 tmp = FLOAT_THREE;
4375 break;
4376 case QUIRK_R3DI:
4377 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4378 tmp = FLOAT_ONE;
4379 break;
4380 default:
4381 tmp = FLOAT_ONE;
4382 break;
4383 }
4384
4385 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4386 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4387 if (spec->quirk == QUIRK_R3DI)
4388 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4389
4390 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4391
4392 chipio_set_stream_control(codec, 0x03, 1);
4393 chipio_set_stream_control(codec, 0x04, 1);
4394
4395 if (spec->quirk == QUIRK_SBZ) {
4396 chipio_write(codec, 0x18B098, 0x0000000C);
4397 chipio_write(codec, 0x18B09C, 0x000000CC);
4398 }
47cdf76e 4399 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4400 break;
4401 }
e0026d03 4402 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4403
4404 snd_hda_power_down_pm(codec);
4405 return 0;
4406
4407}
4408
a7e76271
IM		 4409/*
4410 * Check if VNODE settings take effect immediately.
4411 */
4412static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4413 hda_nid_t vnid,
4414 hda_nid_t *shared_nid)
4415{
4416 struct ca0132_spec *spec = codec->spec;
4417 hda_nid_t nid;
a7e76271
IM		 4418
4419 switch (vnid) {
4420 case VNID_SPK:
4421 nid = spec->shared_out_nid;
a7e76271
IM		 4422 break;
4423 case VNID_MIC:
4424 nid = spec->shared_mic_nid;
a7e76271
IM		 4425 break;
4426 default:
9a0869f4 4427 return false;
a7e76271
IM		 4428 }
4429
9a0869f4 4430 if (shared_nid)
a7e76271
IM		 4431 *shared_nid = nid;
4432
9a0869f4 4433 return true;
a7e76271
IM		 4434}
4435
4436/*
4437* The following functions are control change helpers.
4438* They return 0 if no changed. Return 1 if changed.
4439*/
4440static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4441{
4442 struct ca0132_spec *spec = codec->spec;
4443 unsigned int tmp;
4444
4445 /* based on CrystalVoice state to enable VoiceFX. */
4446 if (enable) {
4447 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4448 FLOAT_ONE : FLOAT_ZERO;
4449 } else {
4450 tmp = FLOAT_ZERO;
4451 }
4452
4453 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4454 ca0132_voicefx.reqs[0], tmp);
4455
4456 return 1;
4457}
4458
5aaca44d
IM		 4459/*
4460 * Set the effects parameters
4461 */
4462static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4463{
4464 struct ca0132_spec *spec = codec->spec;
009b8f97 4465 unsigned int on, tmp;
5aaca44d
IM		 4466 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4467 int err = 0;
4468 int idx = nid - EFFECT_START_NID;
4469
4470 if ((idx < 0) || (idx >= num_fx))
4471 return 0; /* no changed */
4472
4473 /* for out effect, qualify with PE */
4474 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4475 /* if PE if off, turn off out effects. */
4476 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4477 val = 0;
4478 }
4479
4480 /* for in effect, qualify with CrystalVoice */
4481 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4482 /* if CrystalVoice if off, turn off in effects. */
4483 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4484 val = 0;
4485
4486 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4487 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4488 val = 0;
009b8f97
CM		 4489
4490 /* If Voice Focus on SBZ, set to two channel. */
7cb9d94c
CM		 4491 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4492 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4493 if (spec->effects_switch[CRYSTAL_VOICE -
4494 EFFECT_START_NID]) {
4495
4496 if (spec->effects_switch[VOICE_FOCUS -
4497 EFFECT_START_NID]) {
4498 tmp = FLOAT_TWO;
4499 val = 1;
4500 } else
4501 tmp = FLOAT_ONE;
4502
4503 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4504 }
4505 }
4506 /*
4507 * For SBZ noise reduction, there's an extra command
4508 * to module ID 0x47. No clue why.
4509 */
7cb9d94c
CM		 4510 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4511 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4512 if (spec->effects_switch[CRYSTAL_VOICE -
4513 EFFECT_START_NID]) {
4514 if (spec->effects_switch[NOISE_REDUCTION -
4515 EFFECT_START_NID])
4516 tmp = FLOAT_ONE;
4517 else
4518 tmp = FLOAT_ZERO;
4519 } else
4520 tmp = FLOAT_ZERO;
4521
4522 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4523 }
7cb9d94c
CM		 4524
4525 /* If rear line in disable effects. */
4526 if (spec->use_alt_functions &&
4527 spec->in_enum_val == REAR_LINE_IN)
4528 val = 0;
5aaca44d
IM		 4529 }
4530
4e76a883 4531 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4532 nid, val);
4533
4534 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4535 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4536 ca0132_effects[idx].reqs[0], on);
4537
4538 if (err < 0)
4539 return 0; /* no changed */
4540
4541 return 1;
4542}
4543
a7e76271
IM		 4544/*
4545 * Turn on/off Playback Enhancements
4546 */
4547static int ca0132_pe_switch_set(struct hda_codec *codec)
4548{
4549 struct ca0132_spec *spec = codec->spec;
4550 hda_nid_t nid;
4551 int i, ret = 0;
4552
4e76a883 4553 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4554 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4555
7cb9d94c
CM		 4556 if (spec->use_alt_functions)
4557 ca0132_alt_select_out(codec);
4558
a7e76271
IM		 4559 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4560 nid = OUT_EFFECT_START_NID;
4561 /* PE affects all out effects */
4562 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4563 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4564
4565 return ret;
4566}
4567
5aaca44d
IM		 4568/* Check if Mic1 is streaming, if so, stop streaming */
4569static int stop_mic1(struct hda_codec *codec)
4570{
4571 struct ca0132_spec *spec = codec->spec;
4572 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4573 AC_VERB_GET_CONV, 0);
4574 if (oldval != 0)
4575 snd_hda_codec_write(codec, spec->adcs[0], 0,
4576 AC_VERB_SET_CHANNEL_STREAMID,
4577 0);
4578 return oldval;
4579}
4580
4581/* Resume Mic1 streaming if it was stopped. */
4582static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4583{
4584 struct ca0132_spec *spec = codec->spec;
4585 /* Restore the previous stream and channel */
4586 if (oldval != 0)
4587 snd_hda_codec_write(codec, spec->adcs[0], 0,
4588 AC_VERB_SET_CHANNEL_STREAMID,
4589 oldval);
4590}
4591
4592/*
a7e76271 4593 * Turn on/off CrystalVoice
5aaca44d 4594 */
a7e76271
IM		 4595static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4596{
4597 struct ca0132_spec *spec = codec->spec;
4598 hda_nid_t nid;
4599 int i, ret = 0;
4600 unsigned int oldval;
4601
4e76a883 4602 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4603 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4604
4605 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4606 nid = IN_EFFECT_START_NID;
4607 /* CrystalVoice affects all in effects */
4608 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4609 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4610
4611 /* including VoiceFX */
4612 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4613
4614 /* set correct vipsource */
4615 oldval = stop_mic1(codec);
e0026d03
CM		 4616 if (spec->use_alt_functions)
4617 ret |= ca0132_alt_set_vipsource(codec, 1);
4618 else
4619 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 4620 resume_mic1(codec, oldval);
4621 return ret;
4622}
4623
5aaca44d
IM		 4624static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4625{
4626 struct ca0132_spec *spec = codec->spec;
4627 int ret = 0;
4628
4629 if (val) /* on */
4630 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4631 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4632 else /* off */
4633 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4634 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4635
4636 return ret;
4637}
4638
47cdf76e
CM		 4639static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4640{
4641 struct ca0132_spec *spec = codec->spec;
4642 int ret = 0;
4643
4644 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4645 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4646 return ret;
4647}
4648
a7e76271
IM		 4649static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4650 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 4651{
a7e76271
IM		 4652 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4653 hda_nid_t nid = get_amp_nid(kcontrol);
4654 hda_nid_t shared_nid = 0;
4655 bool effective;
4656 int ret = 0;
95c6e9cb 4657 struct ca0132_spec *spec = codec->spec;
a7e76271 4658 int auto_jack;
95c6e9cb 4659
a7e76271
IM		 4660 if (nid == VNID_HP_SEL) {
4661 auto_jack =
4662 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 4663 if (!auto_jack) {
4664 if (spec->use_alt_functions)
4665 ca0132_alt_select_out(codec);
4666 else
4667 ca0132_select_out(codec);
4668 }
a7e76271
IM		 4669 return 1;
4670 }
95c6e9cb 4671
a7e76271
IM		 4672 if (nid == VNID_AMIC1_SEL) {
4673 auto_jack =
4674 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4675 if (!auto_jack)
4676 ca0132_select_mic(codec);
4677 return 1;
4678 }
95c6e9cb 4679
a7e76271 4680 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 4681 if (spec->use_alt_functions)
4682 ca0132_alt_select_out(codec);
4683 else
4684 ca0132_select_out(codec);
a7e76271
IM		 4685 return 1;
4686 }
95c6e9cb 4687
a7e76271
IM		 4688 if (nid == VNID_AMIC1_ASEL) {
4689 ca0132_select_mic(codec);
4690 return 1;
95c6e9cb 4691 }
a7e76271
IM		 4692
4693 /* if effective conditions, then update hw immediately. */
4694 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4695 if (effective) {
4696 int dir = get_amp_direction(kcontrol);
4697 int ch = get_amp_channels(kcontrol);
4698 unsigned long pval;
4699
4700 mutex_lock(&codec->control_mutex);
4701 pval = kcontrol->private_value;
4702 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4703 0, dir);
4704 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4705 kcontrol->private_value = pval;
4706 mutex_unlock(&codec->control_mutex);
95c6e9cb 4707 }
95c6e9cb 4708
a7e76271 4709 return ret;
95c6e9cb 4710}
a7e76271 4711/* End of control change helpers. */
47cdf76e
CM		 4712/*
4713 * Below I've added controls to mess with the effect levels, I've only enabled
4714 * them on the Sound Blaster Z, but they would probably also work on the
4715 * Chromebook. I figured they were probably tuned specifically for it, and left
4716 * out for a reason.
4717 */
4718
4719/* Sets DSP effect level from the sliders above the controls */
4720static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4721 const unsigned int *lookup, int idx)
4722{
4723 int i = 0;
4724 unsigned int y;
4725 /*
4726 * For X_BASS, req 2 is actually crossover freq instead of
4727 * effect level
4728 */
4729 if (nid == X_BASS)
4730 y = 2;
4731 else
4732 y = 1;
4733
4734 snd_hda_power_up(codec);
4735 if (nid == XBASS_XOVER) {
4736 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4737 if (ca0132_effects[i].nid == X_BASS)
4738 break;
4739
4740 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4741 ca0132_effects[i].reqs[1],
4742 &(lookup[idx - 1]), sizeof(unsigned int));
4743 } else {
4744 /* Find the actual effect structure */
4745 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4746 if (nid == ca0132_effects[i].nid)
4747 break;
4748
4749 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4750 ca0132_effects[i].reqs[y],
4751 &(lookup[idx]), sizeof(unsigned int));
4752 }
4753
4754 snd_hda_power_down(codec);
4755
4756 return 0;
4757}
4758
4759static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4760 struct snd_ctl_elem_value *ucontrol)
4761{
4762 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4763 struct ca0132_spec *spec = codec->spec;
4764 long *valp = ucontrol->value.integer.value;
4765
4766 *valp = spec->xbass_xover_freq;
4767 return 0;
4768}
4769
4770static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4771 struct snd_ctl_elem_value *ucontrol)
4772{
4773 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4774 struct ca0132_spec *spec = codec->spec;
4775 hda_nid_t nid = get_amp_nid(kcontrol);
4776 long *valp = ucontrol->value.integer.value;
4777 int idx = nid - OUT_EFFECT_START_NID;
4778
4779 *valp = spec->fx_ctl_val[idx];
4780 return 0;
4781}
4782
4783/*
4784 * The X-bass crossover starts at 10hz, so the min is 1. The
4785 * frequency is set in multiples of 10.
4786 */
4787static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4788 struct snd_ctl_elem_info *uinfo)
4789{
4790 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4791 uinfo->count = 1;
4792 uinfo->value.integer.min = 1;
4793 uinfo->value.integer.max = 100;
4794 uinfo->value.integer.step = 1;
4795
4796 return 0;
4797}
4798
4799static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4800 struct snd_ctl_elem_info *uinfo)
4801{
4802 int chs = get_amp_channels(kcontrol);
4803
4804 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4805 uinfo->count = chs == 3 ? 2 : 1;
4806 uinfo->value.integer.min = 0;
4807 uinfo->value.integer.max = 100;
4808 uinfo->value.integer.step = 1;
4809
4810 return 0;
4811}
4812
4813static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4814 struct snd_ctl_elem_value *ucontrol)
4815{
4816 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4817 struct ca0132_spec *spec = codec->spec;
4818 hda_nid_t nid = get_amp_nid(kcontrol);
4819 long *valp = ucontrol->value.integer.value;
4820 int idx;
4821
4822 /* any change? */
4823 if (spec->xbass_xover_freq == *valp)
4824 return 0;
4825
4826 spec->xbass_xover_freq = *valp;
4827
4828 idx = *valp;
4829 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4830
4831 return 0;
4832}
4833
4834static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4835 struct snd_ctl_elem_value *ucontrol)
4836{
4837 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4838 struct ca0132_spec *spec = codec->spec;
4839 hda_nid_t nid = get_amp_nid(kcontrol);
4840 long *valp = ucontrol->value.integer.value;
4841 int idx;
4842
4843 idx = nid - EFFECT_START_NID;
4844 /* any change? */
4845 if (spec->fx_ctl_val[idx] == *valp)
4846 return 0;
4847
4848 spec->fx_ctl_val[idx] = *valp;
4849
4850 idx = *valp;
4851 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4852
4853 return 0;
4854}
4855
4856
4857/*
4858 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4859 * only has off or full 30 dB, and didn't like making a volume slider that has
4860 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4861 */
4862#define MIC_BOOST_NUM_OF_STEPS 4
4863#define MIC_BOOST_ENUM_MAX_STRLEN 10
4864
4865static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4866 struct snd_ctl_elem_info *uinfo)
4867{
4868 char *sfx = "dB";
4869 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4870
4871 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4872 uinfo->count = 1;
4873 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
4874 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
4875 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
4876 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
4877 strcpy(uinfo->value.enumerated.name, namestr);
4878 return 0;
4879}
4880
4881static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
4882 struct snd_ctl_elem_value *ucontrol)
4883{
4884 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4885 struct ca0132_spec *spec = codec->spec;
4886
4887 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
4888 return 0;
4889}
4890
4891static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
4892 struct snd_ctl_elem_value *ucontrol)
4893{
4894 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4895 struct ca0132_spec *spec = codec->spec;
4896 int sel = ucontrol->value.enumerated.item[0];
4897 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
4898
4899 if (sel >= items)
4900 return 0;
4901
4902 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
4903 sel);
4904
4905 spec->mic_boost_enum_val = sel;
4906
4907 if (spec->in_enum_val != REAR_LINE_IN)
4908 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4909
4910 return 1;
4911}
4912
95c6e9cb 4913
7cb9d94c
CM		 4914/*
4915 * Input Select Control for alternative ca0132 codecs. This exists because
4916 * front microphone has no auto-detect, and we need a way to set the rear
4917 * as line-in
4918 */
4919static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4920 struct snd_ctl_elem_info *uinfo)
4921{
4922 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4923 uinfo->count = 1;
4924 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4925 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4926 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4927 strcpy(uinfo->value.enumerated.name,
4928 in_src_str[uinfo->value.enumerated.item]);
4929 return 0;
4930}
4931
4932static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4933 struct snd_ctl_elem_value *ucontrol)
4934{
4935 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4936 struct ca0132_spec *spec = codec->spec;
4937
4938 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4939 return 0;
4940}
4941
4942static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4943 struct snd_ctl_elem_value *ucontrol)
4944{
4945 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4946 struct ca0132_spec *spec = codec->spec;
4947 int sel = ucontrol->value.enumerated.item[0];
4948 unsigned int items = IN_SRC_NUM_OF_INPUTS;
4949
4950 if (sel >= items)
4951 return 0;
4952
4953 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4954 sel, in_src_str[sel]);
4955
4956 spec->in_enum_val = sel;
4957
4958 ca0132_alt_select_in(codec);
4959
4960 return 1;
4961}
4962
4963/* Sound Blaster Z Output Select Control */
4964static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
4965 struct snd_ctl_elem_info *uinfo)
4966{
4967 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4968 uinfo->count = 1;
4969 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
4970 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
4971 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
4972 strcpy(uinfo->value.enumerated.name,
4973 alt_out_presets[uinfo->value.enumerated.item].name);
4974 return 0;
4975}
4976
4977static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
4978 struct snd_ctl_elem_value *ucontrol)
4979{
4980 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4981 struct ca0132_spec *spec = codec->spec;
4982
4983 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
4984 return 0;
4985}
4986
4987static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
4988 struct snd_ctl_elem_value *ucontrol)
4989{
4990 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4991 struct ca0132_spec *spec = codec->spec;
4992 int sel = ucontrol->value.enumerated.item[0];
4993 unsigned int items = NUM_OF_OUTPUTS;
4994 unsigned int auto_jack;
4995
4996 if (sel >= items)
4997 return 0;
4998
4999 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5000 sel, alt_out_presets[sel].name);
5001
5002 spec->out_enum_val = sel;
5003
5004 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5005
5006 if (!auto_jack)
5007 ca0132_alt_select_out(codec);
5008
5009 return 1;
5010}
5011
47cdf76e
CM		 5012/*
5013 * Smart Volume output setting control. Three different settings, Normal,
5014 * which takes the value from the smart volume slider. The two others, loud
5015 * and night, disregard the slider value and have uneditable values.
5016 */
5017#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5018static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5019
5020static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5021 struct snd_ctl_elem_info *uinfo)
5022{
5023 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5024 uinfo->count = 1;
5025 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5026 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5027 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5028 strcpy(uinfo->value.enumerated.name,
5029 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5030 return 0;
5031}
5032
5033static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5034 struct snd_ctl_elem_value *ucontrol)
5035{
5036 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5037 struct ca0132_spec *spec = codec->spec;
5038
5039 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5040 return 0;
5041}
5042
5043static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5044 struct snd_ctl_elem_value *ucontrol)
5045{
5046 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5047 struct ca0132_spec *spec = codec->spec;
5048 int sel = ucontrol->value.enumerated.item[0];
5049 unsigned int items = NUM_OF_SVM_SETTINGS;
5050 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5051 unsigned int tmp;
5052
5053 if (sel >= items)
5054 return 0;
5055
5056 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5057 sel, out_svm_set_enum_str[sel]);
5058
5059 spec->smart_volume_setting = sel;
5060
5061 switch (sel) {
5062 case 0:
5063 tmp = FLOAT_ZERO;
5064 break;
5065 case 1:
5066 tmp = FLOAT_ONE;
5067 break;
5068 case 2:
5069 tmp = FLOAT_TWO;
5070 break;
5071 default:
5072 tmp = FLOAT_ZERO;
5073 break;
5074 }
5075 /* Req 2 is the Smart Volume Setting req. */
5076 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5077 ca0132_effects[idx].reqs[2], tmp);
5078 return 1;
5079}
5080
5081/* Sound Blaster Z EQ preset controls */
5082static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5083 struct snd_ctl_elem_info *uinfo)
5084{
c5f13d75 5085 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5086
5087 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5088 uinfo->count = 1;
5089 uinfo->value.enumerated.items = items;
5090 if (uinfo->value.enumerated.item >= items)
5091 uinfo->value.enumerated.item = items - 1;
5092 strcpy(uinfo->value.enumerated.name,
5093 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5094 return 0;
5095}
5096
5097static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5098 struct snd_ctl_elem_value *ucontrol)
5099{
5100 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5101 struct ca0132_spec *spec = codec->spec;
5102
5103 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5104 return 0;
5105}
5106
5107static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5108 struct snd_ctl_elem_value *ucontrol)
5109{
5110 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5111 struct ca0132_spec *spec = codec->spec;
5112 int i, err = 0;
5113 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5114 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5115
5116 if (sel >= items)
5117 return 0;
5118
5119 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5120 ca0132_alt_eq_presets[sel].name);
5121 /*
5122 * Idx 0 is default.
5123 * Default needs to qualify with CrystalVoice state.
5124 */
5125 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5126 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5127 ca0132_alt_eq_enum.reqs[i],
5128 ca0132_alt_eq_presets[sel].vals[i]);
5129 if (err < 0)
5130 break;
5131 }
5132
5133 if (err >= 0)
5134 spec->eq_preset_val = sel;
5135
5136 return 1;
5137}
5138
a7e76271
IM		 5139static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5140 struct snd_ctl_elem_info *uinfo)
5141{
a9291f46 5142 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5143
5144 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5145 uinfo->count = 1;
5146 uinfo->value.enumerated.items = items;
5147 if (uinfo->value.enumerated.item >= items)
5148 uinfo->value.enumerated.item = items - 1;
5149 strcpy(uinfo->value.enumerated.name,
5150 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5151 return 0;
5152}
95c6e9cb 5153
a7e76271 5154static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5155 struct snd_ctl_elem_value *ucontrol)
5156{
5157 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5158 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5159
a7e76271 5160 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5161 return 0;
5162}
5163
a7e76271 5164static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5165 struct snd_ctl_elem_value *ucontrol)
5166{
5167 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5168 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5169 int i, err = 0;
5170 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5171
a9291f46 5172 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5173 return 0;
5174
4e76a883 5175 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5176 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5177
a7e76271
IM		 5178 /*
5179 * Idx 0 is default.
5180 * Default needs to qualify with CrystalVoice state.
5181 */
5182 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5183 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5184 ca0132_voicefx.reqs[i],
5185 ca0132_voicefx_presets[sel].vals[i]);
5186 if (err < 0)
5187 break;
5188 }
95c6e9cb 5189
a7e76271
IM		 5190 if (err >= 0) {
5191 spec->voicefx_val = sel;
5192 /* enable voice fx */
5193 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5194 }
95c6e9cb 5195
a7e76271 5196 return 1;
95c6e9cb
IM		 5197}
5198
a7e76271
IM		 5199static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5200 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5201{
5202 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5203 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5204 hda_nid_t nid = get_amp_nid(kcontrol);
5205 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5206 long *valp = ucontrol->value.integer.value;
5207
a7e76271
IM		 5208 /* vnode */
5209 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5210 if (ch & 1) {
5211 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5212 valp++;
5213 }
5214 if (ch & 2) {
5215 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5216 valp++;
5217 }
5218 return 0;
5219 }
5220
5221 /* effects, include PE and CrystalVoice */
5222 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5223 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5224 return 0;
5225 }
5226
5227 /* mic boost */
5228 if (nid == spec->input_pins[0]) {
5229 *valp = spec->cur_mic_boost;
5230 return 0;
5231 }
5232
95c6e9cb
IM		 5233 return 0;
5234}
5235
a7e76271
IM		 5236static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5237 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5238{
5239 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5240 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5241 hda_nid_t nid = get_amp_nid(kcontrol);
5242 int ch = get_amp_channels(kcontrol);
95c6e9cb 5243 long *valp = ucontrol->value.integer.value;
a7e76271 5244 int changed = 1;
95c6e9cb 5245
4e76a883 5246 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5247 nid, *valp);
95c6e9cb
IM		 5248
5249 snd_hda_power_up(codec);
a7e76271
IM		 5250 /* vnode */
5251 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5252 if (ch & 1) {
5253 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5254 valp++;
5255 }
5256 if (ch & 2) {
5257 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5258 valp++;
5259 }
5260 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5261 goto exit;
5262 }
95c6e9cb 5263
a7e76271
IM		 5264 /* PE */
5265 if (nid == PLAY_ENHANCEMENT) {
5266 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5267 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5268 goto exit;
a7e76271 5269 }
95c6e9cb 5270
a7e76271
IM		 5271 /* CrystalVoice */
5272 if (nid == CRYSTAL_VOICE) {
5273 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5274 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5275 goto exit;
a7e76271 5276 }
95c6e9cb 5277
a7e76271
IM		 5278 /* out and in effects */
5279 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5280 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5281 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5282 changed = ca0132_effects_set(codec, nid, *valp);
5283 goto exit;
5284 }
5285
5286 /* mic boost */
5287 if (nid == spec->input_pins[0]) {
5288 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 5289 if (spec->use_alt_functions) {
5290 if (spec->in_enum_val != REAR_LINE_IN)
5291 changed = ca0132_mic_boost_set(codec, *valp);
5292 } else {
5293 /* Mic boost does not apply to Digital Mic */
5294 if (spec->cur_mic_type != DIGITAL_MIC)
5295 changed = ca0132_mic_boost_set(codec, *valp);
5296 }
a7e76271 5297
a7e76271
IM		 5298 goto exit;
5299 }
95c6e9cb 5300
a7e76271 5301exit:
95c6e9cb 5302 snd_hda_power_down(codec);
a7e76271 5303 return changed;
95c6e9cb
IM		 5304}
5305
a7e76271
IM		 5306/*
5307 * Volume related
5308 */
017310fb
CM		 5309/*
5310 * Sets the internal DSP decibel level to match the DAC for output, and the
5311 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5312 * all alternative codecs set DSP playback volume.
5313 */
5314static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5315{
5316 struct ca0132_spec *spec = codec->spec;
5317 unsigned int dsp_dir;
5318 unsigned int lookup_val;
5319
5320 if (nid == VNID_SPK)
5321 dsp_dir = DSP_VOL_OUT;
5322 else
5323 dsp_dir = DSP_VOL_IN;
5324
5325 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5326
5327 dspio_set_uint_param(codec,
5328 ca0132_alt_vol_ctls[dsp_dir].mid,
5329 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5330 float_vol_db_lookup[lookup_val]);
5331
5332 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5333
5334 dspio_set_uint_param(codec,
5335 ca0132_alt_vol_ctls[dsp_dir].mid,
5336 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5337 float_vol_db_lookup[lookup_val]);
5338
5339 dspio_set_uint_param(codec,
5340 ca0132_alt_vol_ctls[dsp_dir].mid,
5341 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5342}
5343
a7e76271
IM		 5344static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5345 struct snd_ctl_elem_info *uinfo)
5346{
5347 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5348 struct ca0132_spec *spec = codec->spec;
5349 hda_nid_t nid = get_amp_nid(kcontrol);
5350 int ch = get_amp_channels(kcontrol);
5351 int dir = get_amp_direction(kcontrol);
5352 unsigned long pval;
5353 int err;
5354
5355 switch (nid) {
5356 case VNID_SPK:
5357 /* follow shared_out info */
5358 nid = spec->shared_out_nid;
5359 mutex_lock(&codec->control_mutex);
5360 pval = kcontrol->private_value;
5361 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5362 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5363 kcontrol->private_value = pval;
5364 mutex_unlock(&codec->control_mutex);
5365 break;
5366 case VNID_MIC:
5367 /* follow shared_mic info */
5368 nid = spec->shared_mic_nid;
5369 mutex_lock(&codec->control_mutex);
5370 pval = kcontrol->private_value;
5371 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5372 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5373 kcontrol->private_value = pval;
5374 mutex_unlock(&codec->control_mutex);
5375 break;
5376 default:
5377 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5378 }
5379 return err;
5380}
5381
5382static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5383 struct snd_ctl_elem_value *ucontrol)
5384{
5385 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5386 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5387 hda_nid_t nid = get_amp_nid(kcontrol);
5388 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5389 long *valp = ucontrol->value.integer.value;
5390
a7e76271
IM		 5391 /* store the left and right volume */
5392 if (ch & 1) {
5393 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5394 valp++;
5395 }
5396 if (ch & 2) {
5397 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5398 valp++;
5399 }
95c6e9cb
IM		 5400 return 0;
5401}
5402
a7e76271 5403static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5404 struct snd_ctl_elem_value *ucontrol)
5405{
5406 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5407 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5408 hda_nid_t nid = get_amp_nid(kcontrol);
5409 int ch = get_amp_channels(kcontrol);
95c6e9cb 5410 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5411 hda_nid_t shared_nid = 0;
5412 bool effective;
5413 int changed = 1;
5414
5415 /* store the left and right volume */
5416 if (ch & 1) {
5417 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5418 valp++;
5419 }
5420 if (ch & 2) {
5421 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5422 valp++;
5423 }
95c6e9cb 5424
a7e76271
IM		 5425 /* if effective conditions, then update hw immediately. */
5426 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5427 if (effective) {
5428 int dir = get_amp_direction(kcontrol);
5429 unsigned long pval;
5430
5431 snd_hda_power_up(codec);
5432 mutex_lock(&codec->control_mutex);
5433 pval = kcontrol->private_value;
5434 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5435 0, dir);
5436 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5437 kcontrol->private_value = pval;
5438 mutex_unlock(&codec->control_mutex);
5439 snd_hda_power_down(codec);
5440 }
95c6e9cb 5441
a7e76271 5442 return changed;
95c6e9cb
IM		 5443}
5444
017310fb
CM		 5445/*
5446 * This function is the same as the one above, because using an if statement
5447 * inside of the above volume control for the DSP volume would cause too much
5448 * lag. This is a lot more smooth.
5449 */
5450static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5451 struct snd_ctl_elem_value *ucontrol)
5452{
5453 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5454 struct ca0132_spec *spec = codec->spec;
5455 hda_nid_t nid = get_amp_nid(kcontrol);
5456 int ch = get_amp_channels(kcontrol);
5457 long *valp = ucontrol->value.integer.value;
5458 hda_nid_t vnid = 0;
5459 int changed = 1;
5460
5461 switch (nid) {
5462 case 0x02:
5463 vnid = VNID_SPK;
5464 break;
5465 case 0x07:
5466 vnid = VNID_MIC;
5467 break;
5468 }
5469
5470 /* store the left and right volume */
5471 if (ch & 1) {
5472 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5473 valp++;
5474 }
5475 if (ch & 2) {
5476 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5477 valp++;
5478 }
5479
5480 snd_hda_power_up(codec);
5481 ca0132_alt_dsp_volume_put(codec, vnid);
5482 mutex_lock(&codec->control_mutex);
5483 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5484 mutex_unlock(&codec->control_mutex);
5485 snd_hda_power_down(codec);
5486
5487 return changed;
5488}
5489
a7e76271
IM		 5490static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5491 unsigned int size, unsigned int __user *tlv)
95c6e9cb 5492{
a7e76271
IM		 5493 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5494 struct ca0132_spec *spec = codec->spec;
5495 hda_nid_t nid = get_amp_nid(kcontrol);
5496 int ch = get_amp_channels(kcontrol);
5497 int dir = get_amp_direction(kcontrol);
5498 unsigned long pval;
5499 int err;
5500
5501 switch (nid) {
5502 case VNID_SPK:
5503 /* follow shared_out tlv */
5504 nid = spec->shared_out_nid;
5505 mutex_lock(&codec->control_mutex);
5506 pval = kcontrol->private_value;
5507 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5508 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5509 kcontrol->private_value = pval;
5510 mutex_unlock(&codec->control_mutex);
5511 break;
5512 case VNID_MIC:
5513 /* follow shared_mic tlv */
5514 nid = spec->shared_mic_nid;
5515 mutex_lock(&codec->control_mutex);
5516 pval = kcontrol->private_value;
5517 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5518 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5519 kcontrol->private_value = pval;
5520 mutex_unlock(&codec->control_mutex);
5521 break;
5522 default:
5523 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5524 }
5525 return err;
95c6e9cb
IM		 5526}
5527
47cdf76e
CM		 5528/* Add volume slider control for effect level */
5529static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5530 const char *pfx, int dir)
5531{
47cdf76e
CM		 5532 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5533 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5534 struct snd_kcontrol_new knew =
5535 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5536
0cc1aa71 5537 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 5538
bb86124c 5539 knew.tlv.c = NULL;
47cdf76e
CM		 5540
5541 switch (nid) {
5542 case XBASS_XOVER:
5543 knew.info = ca0132_alt_xbass_xover_slider_info;
5544 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5545 knew.put = ca0132_alt_xbass_xover_slider_put;
5546 break;
5547 default:
5548 knew.info = ca0132_alt_effect_slider_info;
5549 knew.get = ca0132_alt_slider_ctl_get;
5550 knew.put = ca0132_alt_effect_slider_put;
5551 knew.private_value =
5552 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5553 break;
5554 }
5555
5556 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5557}
5558
5559/*
5560 * Added FX: prefix for the alternative codecs, because otherwise the surround
5561 * effect would conflict with the Surround sound volume control. Also seems more
5562 * clear as to what the switches do. Left alone for others.
5563 */
a7e76271
IM		 5564static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5565 const char *pfx, int dir)
95c6e9cb 5566{
47cdf76e 5567 struct ca0132_spec *spec = codec->spec;
975cc02a 5568 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 5569 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 5570 struct snd_kcontrol_new knew =
a7e76271 5571 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 5572 /* If using alt_controls, add FX: prefix. But, don't add FX:
5573 * prefix to OutFX or InFX enable controls.
5574 */
5575 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 5576 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 5577 else
5578 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5579
95c6e9cb
IM		 5580 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5581}
5582
a7e76271 5583static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 5584{
5585 struct snd_kcontrol_new knew =
a7e76271
IM		 5586 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5587 VOICEFX, 1, 0, HDA_INPUT);
5588 knew.info = ca0132_voicefx_info;
5589 knew.get = ca0132_voicefx_get;
5590 knew.put = ca0132_voicefx_put;
5591 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 5592}
5593
47cdf76e
CM		 5594/* Create the EQ Preset control */
5595static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5596{
5597 struct snd_kcontrol_new knew =
5598 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5599 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5600 knew.info = ca0132_alt_eq_preset_info;
5601 knew.get = ca0132_alt_eq_preset_get;
5602 knew.put = ca0132_alt_eq_preset_put;
5603 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5604 snd_ctl_new1(&knew, codec));
5605}
5606
5607/*
5608 * Add enumerated control for the three different settings of the smart volume
5609 * output effect. Normal just uses the slider value, and loud and night are
5610 * their own things that ignore that value.
5611 */
5612static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5613{
5614 struct snd_kcontrol_new knew =
5615 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5616 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5617 knew.info = ca0132_alt_svm_setting_info;
5618 knew.get = ca0132_alt_svm_setting_get;
5619 knew.put = ca0132_alt_svm_setting_put;
5620 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5621 snd_ctl_new1(&knew, codec));
5622
5623}
5624
7cb9d94c
CM		 5625/*
5626 * Create an Output Select enumerated control for codecs with surround
5627 * out capabilities.
5628 */
5629static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5630{
5631 struct snd_kcontrol_new knew =
5632 HDA_CODEC_MUTE_MONO("Output Select",
5633 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5634 knew.info = ca0132_alt_output_select_get_info;
5635 knew.get = ca0132_alt_output_select_get;
5636 knew.put = ca0132_alt_output_select_put;
5637 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5638 snd_ctl_new1(&knew, codec));
5639}
5640
5641/*
5642 * Create an Input Source enumerated control for the alternate ca0132 codecs
5643 * because the front microphone has no auto-detect, and Line-in has to be set
5644 * somehow.
5645 */
5646static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5647{
5648 struct snd_kcontrol_new knew =
5649 HDA_CODEC_MUTE_MONO("Input Source",
5650 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5651 knew.info = ca0132_alt_input_source_info;
5652 knew.get = ca0132_alt_input_source_get;
5653 knew.put = ca0132_alt_input_source_put;
5654 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5655 snd_ctl_new1(&knew, codec));
5656}
5657
47cdf76e
CM		 5658/*
5659 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5660 * more control than the original mic boost, which is either full 30dB or off.
5661 */
5662static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5663{
5664 struct snd_kcontrol_new knew =
5665 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5666 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5667 knew.info = ca0132_alt_mic_boost_info;
5668 knew.get = ca0132_alt_mic_boost_get;
5669 knew.put = ca0132_alt_mic_boost_put;
5670 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5671 snd_ctl_new1(&knew, codec));
5672
5673}
5674
5675/*
5676 * Need to create slave controls for the alternate codecs that have surround
5677 * capabilities.
5678 */
5679static const char * const ca0132_alt_slave_pfxs[] = {
5680 "Front", "Surround", "Center", "LFE", NULL,
5681};
5682
5683/*
5684 * Also need special channel map, because the default one is incorrect.
5685 * I think this has to do with the pin for rear surround being 0x11,
5686 * and the center/lfe being 0x10. Usually the pin order is the opposite.
5687 */
9c4a665e 5688static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 5689 { .channels = 2,
5690 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5691 { .channels = 4,
5692 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5693 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5694 { .channels = 6,
5695 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5696 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5697 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5698 { }
5699};
5700
5701/* Add the correct chmap for streams with 6 channels. */
5702static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5703{
5704 int err = 0;
5705 struct hda_pcm *pcm;
5706
5707 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5708 struct hda_pcm_stream *hinfo =
5709 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5710 struct snd_pcm_chmap *chmap;
5711 const struct snd_pcm_chmap_elem *elem;
5712
5713 elem = ca0132_alt_chmaps;
5714 if (hinfo->channels_max == 6) {
5715 err = snd_pcm_add_chmap_ctls(pcm->pcm,
5716 SNDRV_PCM_STREAM_PLAYBACK,
5717 elem, hinfo->channels_max, 0, &chmap);
5718 if (err < 0)
5719 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5720 }
5721 }
5722}
5723
a7e76271
IM		 5724/*
5725 * When changing Node IDs for Mixer Controls below, make sure to update
5726 * Node IDs in ca0132_config() as well.
5727 */
b0eaa072 5728static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 5729 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5730 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5731 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5732 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5733 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5734 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5735 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5736 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5737 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5738 0x12, 1, HDA_INPUT),
5739 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5740 VNID_HP_SEL, 1, HDA_OUTPUT),
5741 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5742 VNID_AMIC1_SEL, 1, HDA_INPUT),
5743 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5744 VNID_HP_ASEL, 1, HDA_OUTPUT),
5745 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5746 VNID_AMIC1_ASEL, 1, HDA_INPUT),
5747 { } /* end */
5748};
5749
017310fb
CM		 5750/*
5751 * SBZ specific control mixer. Removes auto-detect for mic, and adds surround
5752 * controls. Also sets both the Front Playback and Capture Volume controls to
5753 * alt so they set the DSP's decibel level.
5754 */
b0eaa072 5755static const struct snd_kcontrol_new sbz_mixer[] = {
017310fb
CM		 5756 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5757 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5758 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5759 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5760 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5761 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5762 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5763 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5764 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5765 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5766 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5767 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5768 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5769 VNID_HP_ASEL, 1, HDA_OUTPUT),
5770 { } /* end */
5771};
5772
5773/*
5774 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5775 * because it doesn't set decibel levels for the DSP for capture.
5776 */
b0eaa072 5777static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 5778 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5779 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5780 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5781 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5782 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5783 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5784 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5785 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5786 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5787 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5788 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5789 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5790 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5791 VNID_HP_ASEL, 1, HDA_OUTPUT),
5792 { } /* end */
5793};
5794
e90f29e4
IM		 5795static int ca0132_build_controls(struct hda_codec *codec)
5796{
5797 struct ca0132_spec *spec = codec->spec;
47cdf76e 5798 int i, num_fx, num_sliders;
e90f29e4
IM		 5799 int err = 0;
5800
5801 /* Add Mixer controls */
5802 for (i = 0; i < spec->num_mixers; i++) {
5803 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5804 if (err < 0)
5805 return err;
5806 }
47cdf76e
CM		 5807 /* Setup vmaster with surround slaves for desktop ca0132 devices */
5808 if (spec->use_alt_functions) {
5809 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5810 spec->tlv);
5811 snd_hda_add_vmaster(codec, "Master Playback Volume",
5812 spec->tlv, ca0132_alt_slave_pfxs,
5813 "Playback Volume");
5814 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5815 NULL, ca0132_alt_slave_pfxs,
5816 "Playback Switch",
5817 true, &spec->vmaster_mute.sw_kctl);
5818
5819 }
e90f29e4
IM		 5820
5821 /* Add in and out effects controls.
5822 * VoiceFX, PE and CrystalVoice are added separately.
5823 */
5824 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5825 for (i = 0; i < num_fx; i++) {
47cdf76e
CM		 5826 /* SBZ breaks if Echo Cancellation is used */
5827 if (spec->quirk == QUIRK_SBZ) {
5828 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5829 OUT_EFFECTS_COUNT))
5830 continue;
5831 }
5832
e90f29e4
IM		 5833 err = add_fx_switch(codec, ca0132_effects[i].nid,
5834 ca0132_effects[i].name,
5835 ca0132_effects[i].direct);
5836 if (err < 0)
5837 return err;
5838 }
47cdf76e
CM		 5839 /*
5840 * If codec has use_alt_controls set to true, add effect level sliders,
5841 * EQ presets, and Smart Volume presets. Also, change names to add FX
5842 * prefix, and change PlayEnhancement and CrystalVoice to match.
5843 */
5844 if (spec->use_alt_controls) {
5845 ca0132_alt_add_svm_enum(codec);
5846 add_ca0132_alt_eq_presets(codec);
5847 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5848 "Enable OutFX", 0);
5849 if (err < 0)
5850 return err;
e90f29e4 5851
47cdf76e
CM		 5852 err = add_fx_switch(codec, CRYSTAL_VOICE,
5853 "Enable InFX", 1);
5854 if (err < 0)
5855 return err;
e90f29e4 5856
47cdf76e
CM		 5857 num_sliders = OUT_EFFECTS_COUNT - 1;
5858 for (i = 0; i < num_sliders; i++) {
5859 err = ca0132_alt_add_effect_slider(codec,
5860 ca0132_effects[i].nid,
5861 ca0132_effects[i].name,
5862 ca0132_effects[i].direct);
5863 if (err < 0)
5864 return err;
5865 }
5866
5867 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5868 "X-Bass Crossover", EFX_DIR_OUT);
5869
5870 if (err < 0)
5871 return err;
5872 } else {
5873 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5874 "PlayEnhancement", 0);
5875 if (err < 0)
5876 return err;
e90f29e4 5877
47cdf76e
CM		 5878 err = add_fx_switch(codec, CRYSTAL_VOICE,
5879 "CrystalVoice", 1);
5880 if (err < 0)
5881 return err;
5882 }
e90f29e4
IM		 5883 add_voicefx(codec);
5884
7cb9d94c
CM		 5885 /*
5886 * If the codec uses alt_functions, you need the enumerated controls
5887 * to select the new outputs and inputs, plus add the new mic boost
5888 * setting control.
5889 */
5890 if (spec->use_alt_functions) {
5891 ca0132_alt_add_output_enum(codec);
5892 ca0132_alt_add_input_enum(codec);
47cdf76e 5893 ca0132_alt_add_mic_boost_enum(codec);
7cb9d94c 5894 }
e90f29e4
IM		 5895#ifdef ENABLE_TUNING_CONTROLS
5896 add_tuning_ctls(codec);
5897#endif
5898
5899 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
5900 if (err < 0)
5901 return err;
5902
5903 if (spec->dig_out) {
5904 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
5905 spec->dig_out);
5906 if (err < 0)
5907 return err;
5908 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
5909 if (err < 0)
5910 return err;
5911 /* spec->multiout.share_spdif = 1; */
5912 }
5913
5914 if (spec->dig_in) {
5915 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
5916 if (err < 0)
5917 return err;
5918 }
47cdf76e
CM		 5919
5920 if (spec->use_alt_functions)
5921 ca0132_alt_add_chmap_ctls(codec);
5922
e90f29e4
IM		 5923 return 0;
5924}
5925
a7e76271 5926/*
e90f29e4 5927 * PCM
a7e76271 5928 */
071f1344 5929static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 5930 .substreams = 1,
5931 .channels_min = 2,
825315bc 5932 .channels_max = 6,
a7e76271 5933 .ops = {
a7e76271 5934 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 5935 .cleanup = ca0132_playback_pcm_cleanup,
5936 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 5937 },
5938};
5939
071f1344 5940static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 5941 .substreams = 1,
5942 .channels_min = 2,
5943 .channels_max = 2,
825315bc
IM		 5944 .ops = {
5945 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 5946 .cleanup = ca0132_capture_pcm_cleanup,
5947 .get_delay = ca0132_capture_pcm_delay,
825315bc 5948 },
a7e76271
IM		 5949};
5950
071f1344 5951static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 5952 .substreams = 1,
5953 .channels_min = 2,
5954 .channels_max = 2,
5955 .ops = {
5956 .open = ca0132_dig_playback_pcm_open,
5957 .close = ca0132_dig_playback_pcm_close,
5958 .prepare = ca0132_dig_playback_pcm_prepare,
5959 .cleanup = ca0132_dig_playback_pcm_cleanup
5960 },
5961};
5962
071f1344 5963static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 5964 .substreams = 1,
5965 .channels_min = 2,
5966 .channels_max = 2,
5967};
5968
5969static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 5970{
5971 struct ca0132_spec *spec = codec->spec;
bbbc7e85 5972 struct hda_pcm *info;
a7e76271 5973
bbbc7e85
TI		 5974 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
5975 if (!info)
5976 return -ENOMEM;
47cdf76e
CM		 5977 if (spec->use_alt_functions) {
5978 info->own_chmap = true;
5979 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
5980 = ca0132_alt_chmaps;
5981 }
a7e76271
IM		 5982 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
5983 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
5984 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
5985 spec->multiout.max_channels;
5986 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 5987 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 5988 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 5989
009b8f97 5990 /* With the DSP enabled, desktops don't use this ADC. */
5f8ddc6e 5991 if (!spec->use_alt_functions) {
009b8f97
CM		 5992 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
5993 if (!info)
5994 return -ENOMEM;
5995 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
5996 ca0132_pcm_analog_capture;
5997 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
5998 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
5999 }
825315bc 6000
bbbc7e85
TI		 6001 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6002 if (!info)
6003 return -ENOMEM;
825315bc
IM		 6004 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6005 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6006 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6007
a7e76271
IM		 6008 if (!spec->dig_out && !spec->dig_in)
6009 return 0;
6010
bbbc7e85
TI		 6011 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6012 if (!info)
6013 return -ENOMEM;
a7e76271
IM		 6014 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6015 if (spec->dig_out) {
6016 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6017 ca0132_pcm_digital_playback;
6018 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6019 }
6020 if (spec->dig_in) {
6021 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6022 ca0132_pcm_digital_capture;
6023 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6024 }
95c6e9cb 6025
a7e76271 6026 return 0;
95c6e9cb
IM		 6027}
6028
441aa6a0
IM		 6029static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6030{
6031 if (pin) {
a0c041cb 6032 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6033 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6034 snd_hda_codec_write(codec, pin, 0,
6035 AC_VERB_SET_AMP_GAIN_MUTE,
6036 AMP_OUT_UNMUTE);
6037 }
6038 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6039 snd_hda_codec_write(codec, dac, 0,
6040 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6041}
6042
6043static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6044{
6045 if (pin) {
a0c041cb 6046 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6047 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6048 snd_hda_codec_write(codec, pin, 0,
6049 AC_VERB_SET_AMP_GAIN_MUTE,
6050 AMP_IN_UNMUTE(0));
6051 }
6052 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6053 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6054 AMP_IN_UNMUTE(0));
6055
6056 /* init to 0 dB and unmute. */
6057 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6058 HDA_AMP_VOLMASK, 0x5a);
6059 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6060 HDA_AMP_MUTE, 0);
6061 }
6062}
6063
5aaca44d
IM		 6064static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6065{
6066 unsigned int caps;
6067
6068 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6069 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6070 snd_hda_override_amp_caps(codec, nid, dir, caps);
6071}
6072
6073/*
6074 * Switch between Digital built-in mic and analog mic.
6075 */
6076static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6077{
6078 struct ca0132_spec *spec = codec->spec;
6079 unsigned int tmp;
6080 u8 val;
6081 unsigned int oldval;
6082
4e76a883 6083 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6084
6085 oldval = stop_mic1(codec);
6086 ca0132_set_vipsource(codec, 0);
6087 if (enable) {
6088 /* set DMic input as 2-ch */
6089 tmp = FLOAT_TWO;
6090 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6091
6092 val = spec->dmic_ctl;
6093 val |= 0x80;
6094 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6095 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6096
6097 if (!(spec->dmic_ctl & 0x20))
6098 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6099 } else {
6100 /* set AMic input as mono */
6101 tmp = FLOAT_ONE;
6102 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6103
6104 val = spec->dmic_ctl;
6105 /* clear bit7 and bit5 to disable dmic */
6106 val &= 0x5f;
6107 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6108 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6109
6110 if (!(spec->dmic_ctl & 0x20))
6111 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6112 }
6113 ca0132_set_vipsource(codec, 1);
6114 resume_mic1(codec, oldval);
6115}
6116
6117/*
6118 * Initialization for Digital Mic.
6119 */
6120static void ca0132_init_dmic(struct hda_codec *codec)
6121{
6122 struct ca0132_spec *spec = codec->spec;
6123 u8 val;
6124
6125 /* Setup Digital Mic here, but don't enable.
6126 * Enable based on jack detect.
6127 */
6128
6129 /* MCLK uses MPIO1, set to enable.
6130 * Bit 2-0: MPIO select
6131 * Bit 3: set to disable
6132 * Bit 7-4: reserved
6133 */
6134 val = 0x01;
6135 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6136 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6137
6138 /* Data1 uses MPIO3. Data2 not use
6139 * Bit 2-0: Data1 MPIO select
6140 * Bit 3: set disable Data1
6141 * Bit 6-4: Data2 MPIO select
6142 * Bit 7: set disable Data2
6143 */
6144 val = 0x83;
6145 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6146 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6147
6148 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6149 * Bit 3-0: Channel mask
6150 * Bit 4: set for 48KHz, clear for 32KHz
6151 * Bit 5: mode
6152 * Bit 6: set to select Data2, clear for Data1
6153 * Bit 7: set to enable DMic, clear for AMic
6154 */
a57a46b9
AB		 6155 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6156 val = 0x33;
6157 else
6158 val = 0x23;
5aaca44d
IM		 6159 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6160 spec->dmic_ctl = val;
6161 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6162 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6163}
6164
6165/*
6166 * Initialization for Analog Mic 2
6167 */
6168static void ca0132_init_analog_mic2(struct hda_codec *codec)
6169{
6170 struct ca0132_spec *spec = codec->spec;
6171
6172 mutex_lock(&spec->chipio_mutex);
6173 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6174 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6175 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6176 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6177 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6178 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6179 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6180 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6181 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6182 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6183 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6184 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6185 mutex_unlock(&spec->chipio_mutex);
6186}
6187
6188static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6189{
6190 struct ca0132_spec *spec = codec->spec;
6191 int i;
5aaca44d 6192
4e76a883 6193 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6194 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6195
6196 for (i = 0; i < spec->multiout.num_dacs; i++)
6197 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6198
6199 for (i = 0; i < spec->num_outputs; i++)
6200 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6201
6202 for (i = 0; i < spec->num_inputs; i++) {
6203 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6204 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6205 }
6206}
6207
7e6ed62e
CM		 6208/*
6209 * Recon3Di r3di_setup_defaults sub functions.
6210 */
6211
447fd8e9
CM		 6212static void r3di_dsp_scp_startup(struct hda_codec *codec)
6213{
6214 unsigned int tmp;
6215
6216 tmp = 0x00000000;
6217 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6218
6219 tmp = 0x00000001;
6220 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6221
6222 tmp = 0x00000004;
6223 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6224
6225 tmp = 0x00000005;
6226 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6227
6228 tmp = 0x00000000;
6229 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6230
6231}
6232
7e6ed62e
CM		 6233static void r3di_dsp_initial_mic_setup(struct hda_codec *codec)
6234{
6235 unsigned int tmp;
6236
6237 /* Mic 1 Setup */
6238 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6239 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6240 /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6241 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6242 tmp = FLOAT_ONE;
6243 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6244
6245 /* Mic 2 Setup, even though it isn't connected on SBZ */
6246 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6247 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6248 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6249 tmp = FLOAT_ZERO;
6250 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6251}
6252
38ba69ff
CM		 6253/*
6254 * Initialize Sound Blaster Z analog microphones.
6255 */
6256static void sbz_init_analog_mics(struct hda_codec *codec)
6257{
6258 unsigned int tmp;
6259
6260 /* Mic 1 Setup */
6261 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6262 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6263 tmp = FLOAT_THREE;
6264 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6265
6266 /* Mic 2 Setup, even though it isn't connected on SBZ */
6267 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6268 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6269 tmp = FLOAT_ZERO;
6270 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6271
6272}
6273
6274/*
6275 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6276 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6277 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6278 * having an updated DAC, which changes the destination to that DAC.
6279 */
6280static void sbz_connect_streams(struct hda_codec *codec)
6281{
6282 struct ca0132_spec *spec = codec->spec;
6283
6284 mutex_lock(&spec->chipio_mutex);
6285
6286 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6287
6288 chipio_set_stream_channels(codec, 0x0C, 6);
6289 chipio_set_stream_control(codec, 0x0C, 1);
6290
6291 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6292 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6293
6294 /* Setup stream 0x14 with it's source and destination points */
6295 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6296 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6297 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6298 chipio_set_stream_channels(codec, 0x14, 2);
6299 chipio_set_stream_control(codec, 0x14, 1);
6300
6301 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6302
6303 mutex_unlock(&spec->chipio_mutex);
6304
6305}
6306
6307/*
6308 * Write data through ChipIO to setup proper stream destinations.
6309 * Not sure how it exactly works, but it seems to direct data
6310 * to different destinations. Example is f8 to c0, e0 to c0.
6311 * All I know is, if you don't set these, you get no sound.
6312 */
6313static void sbz_chipio_startup_data(struct hda_codec *codec)
6314{
6315 struct ca0132_spec *spec = codec->spec;
6316
6317 mutex_lock(&spec->chipio_mutex);
6318 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6319
6320 /* These control audio output */
6321 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6322 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6323 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6324 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6325 /* Signal to update I think */
6326 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6327
6328 chipio_set_stream_channels(codec, 0x0C, 6);
6329 chipio_set_stream_control(codec, 0x0C, 1);
6330 /* No clue what these control */
6331 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6332 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6333 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6334 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6335 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6336 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6337 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6338 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6339 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6340 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6341 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6342 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6343
6344 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6345
6346 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6347 mutex_unlock(&spec->chipio_mutex);
6348}
6349
447fd8e9
CM		 6350/*
6351 * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6352 * without a 0x20 source like normal.
6353 */
6354static void sbz_dsp_scp_startup(struct hda_codec *codec)
6355{
6356 unsigned int tmp;
6357
6358 tmp = 0x00000003;
6359 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6360
6361 tmp = 0x00000000;
6362 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6363
6364 tmp = 0x00000001;
6365 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6366
6367 tmp = 0x00000004;
6368 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6369
6370 tmp = 0x00000005;
6371 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6372
6373 tmp = 0x00000000;
6374 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6375
6376}
6377
38ba69ff
CM		 6378static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
6379{
6380 unsigned int tmp;
6381
6382 chipio_set_stream_control(codec, 0x03, 0);
6383 chipio_set_stream_control(codec, 0x04, 0);
6384
6385 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6386 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6387
6388 tmp = FLOAT_THREE;
6389 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6390
6391 chipio_set_stream_control(codec, 0x03, 1);
6392 chipio_set_stream_control(codec, 0x04, 1);
6393
6394 chipio_write(codec, 0x18b098, 0x0000000c);
6395 chipio_write(codec, 0x18b09C, 0x0000000c);
6396}
6397
5aaca44d
IM		 6398/*
6399 * Setup default parameters for DSP
6400 */
6401static void ca0132_setup_defaults(struct hda_codec *codec)
6402{
e8f1bd5d 6403 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 6404 unsigned int tmp;
6405 int num_fx;
6406 int idx, i;
6407
e8f1bd5d 6408 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 6409 return;
6410
6411 /* out, in effects + voicefx */
6412 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6413 for (idx = 0; idx < num_fx; idx++) {
6414 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6415 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6416 ca0132_effects[idx].reqs[i],
6417 ca0132_effects[idx].def_vals[i]);
6418 }
6419 }
6420
6421 /*remove DSP headroom*/
6422 tmp = FLOAT_ZERO;
6423 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6424
6425 /*set speaker EQ bypass attenuation*/
6426 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6427
6428 /* set AMic1 and AMic2 as mono mic */
6429 tmp = FLOAT_ONE;
6430 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6431 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6432
6433 /* set AMic1 as CrystalVoice input */
6434 tmp = FLOAT_ONE;
6435 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6436
6437 /* set WUH source */
6438 tmp = FLOAT_TWO;
6439 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6440}
6441
7e6ed62e
CM		 6442/*
6443 * Setup default parameters for Recon3Di DSP.
6444 */
6445
6446static void r3di_setup_defaults(struct hda_codec *codec)
6447{
6448 struct ca0132_spec *spec = codec->spec;
6449 unsigned int tmp;
6450 int num_fx;
6451 int idx, i;
6452
6453 if (spec->dsp_state != DSP_DOWNLOADED)
6454 return;
6455
447fd8e9 6456 r3di_dsp_scp_startup(codec);
7e6ed62e
CM		 6457
6458 r3di_dsp_initial_mic_setup(codec);
6459
6460 /*remove DSP headroom*/
6461 tmp = FLOAT_ZERO;
6462 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6463
6464 /* set WUH source */
6465 tmp = FLOAT_TWO;
6466 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6467 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6468
6469 /* Set speaker source? */
6470 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6471
6472 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6473
6474 /* Setup effect defaults */
6475 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6476 for (idx = 0; idx < num_fx; idx++) {
6477 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6478 dspio_set_uint_param(codec,
6479 ca0132_effects[idx].mid,
6480 ca0132_effects[idx].reqs[i],
6481 ca0132_effects[idx].def_vals[i]);
6482 }
6483 }
6484
6485}
6486
38ba69ff
CM		 6487/*
6488 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6489 * than the Chromebook setup.
6490 */
6491static void sbz_setup_defaults(struct hda_codec *codec)
6492{
6493 struct ca0132_spec *spec = codec->spec;
6494 unsigned int tmp, stream_format;
6495 int num_fx;
6496 int idx, i;
6497
6498 if (spec->dsp_state != DSP_DOWNLOADED)
6499 return;
6500
447fd8e9 6501 sbz_dsp_scp_startup(codec);
38ba69ff
CM		 6502
6503 sbz_init_analog_mics(codec);
6504
6505 sbz_connect_streams(codec);
6506
6507 sbz_chipio_startup_data(codec);
6508
6509 chipio_set_stream_control(codec, 0x03, 1);
6510 chipio_set_stream_control(codec, 0x04, 1);
6511
6512 /*
6513 * Sets internal input loopback to off, used to have a switch to
6514 * enable input loopback, but turned out to be way too buggy.
6515 */
6516 tmp = FLOAT_ONE;
6517 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6518 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6519
6520 /*remove DSP headroom*/
6521 tmp = FLOAT_ZERO;
6522 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6523
6524 /* set WUH source */
6525 tmp = FLOAT_TWO;
6526 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6527 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6528
6529 /* Set speaker source? */
6530 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6531
6532 sbz_dsp_initial_mic_setup(codec);
6533
6534
6535 /* out, in effects + voicefx */
6536 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6537 for (idx = 0; idx < num_fx; idx++) {
6538 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6539 dspio_set_uint_param(codec,
6540 ca0132_effects[idx].mid,
6541 ca0132_effects[idx].reqs[i],
6542 ca0132_effects[idx].def_vals[i]);
6543 }
6544 }
6545
6546 /*
6547 * Have to make a stream to bind the sound output to, otherwise
6548 * you'll get dead audio. Before I did this, it would bind to an
6549 * audio input, and would never work
6550 */
6551 stream_format = snd_hdac_calc_stream_format(48000, 2,
6552 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6553
6554 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6555 0, stream_format);
6556
6557 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6558
6559 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6560 0, stream_format);
6561
6562 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6563}
6564
5aaca44d
IM		 6565/*
6566 * Initialization of flags in chip
6567 */
6568static void ca0132_init_flags(struct hda_codec *codec)
6569{
009b8f97
CM		 6570 struct ca0132_spec *spec = codec->spec;
6571
6572 if (spec->use_alt_functions) {
6573 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6574 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6575 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6576 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6577 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6578 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6579 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6580 chipio_set_control_flag(codec,
6581 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6582 chipio_set_control_flag(codec,
6583 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6584 } else {
6585 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6586 chipio_set_control_flag(codec,
6587 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6588 chipio_set_control_flag(codec,
6589 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6590 chipio_set_control_flag(codec,
6591 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6592 chipio_set_control_flag(codec,
6593 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6594 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6595 }
5aaca44d
IM		 6596}
6597
6598/*
6599 * Initialization of parameters in chip
6600 */
6601static void ca0132_init_params(struct hda_codec *codec)
6602{
009b8f97
CM		 6603 struct ca0132_spec *spec = codec->spec;
6604
6605 if (spec->use_alt_functions) {
6606 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6607 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6608 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6609 chipio_set_control_param(codec, 0, 0);
6610 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6611 }
6612
5aaca44d
IM		 6613 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6614 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6615}
95c6e9cb 6616
e90f29e4
IM		 6617static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6618{
6619 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6620 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6621 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6622 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6623 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6624 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6625
406261ce
IM		 6626 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6627 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 6628 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6629}
6630
6631static bool ca0132_download_dsp_images(struct hda_codec *codec)
6632{
6633 bool dsp_loaded = false;
8a19bcee 6634 struct ca0132_spec *spec = codec->spec;
e90f29e4 6635 const struct dsp_image_seg *dsp_os_image;
15e4ba66 6636 const struct firmware *fw_entry;
8a19bcee
CM		 6637 /*
6638 * Alternate firmwares for different variants. The Recon3Di apparently
6639 * can use the default firmware, but I'll leave the option in case
6640 * it needs it again.
6641 */
6642 switch (spec->quirk) {
6643 case QUIRK_SBZ:
6644 if (request_firmware(&fw_entry, SBZ_EFX_FILE,
6645 codec->card->dev) != 0) {
6646 codec_dbg(codec, "SBZ alt firmware not detected. ");
6647 spec->alt_firmware_present = false;
6648 } else {
6649 codec_dbg(codec, "Sound Blaster Z firmware selected.");
6650 spec->alt_firmware_present = true;
6651 }
6652 break;
6653 case QUIRK_R3DI:
6654 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6655 codec->card->dev) != 0) {
6656 codec_dbg(codec, "Recon3Di alt firmware not detected.");
6657 spec->alt_firmware_present = false;
6658 } else {
6659 codec_dbg(codec, "Recon3Di firmware selected.");
6660 spec->alt_firmware_present = true;
6661 }
6662 break;
6663 default:
6664 spec->alt_firmware_present = false;
6665 break;
6666 }
6667 /*
6668 * Use default ctefx.bin if no alt firmware is detected, or if none
6669 * exists for your particular codec.
6670 */
6671 if (!spec->alt_firmware_present) {
6672 codec_dbg(codec, "Default firmware selected.");
6673 if (request_firmware(&fw_entry, EFX_FILE,
6674 codec->card->dev) != 0)
6675 return false;
6676 }
e90f29e4 6677
15e4ba66 6678 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 6679 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 6680 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 6681 goto exit_download;
6682 }
6683
e90f29e4
IM		 6684 dsp_loaded = dspload_wait_loaded(codec);
6685
d1d28500 6686exit_download:
15e4ba66
TI		 6687 release_firmware(fw_entry);
6688
e90f29e4
IM		 6689 return dsp_loaded;
6690}
6691
6692static void ca0132_download_dsp(struct hda_codec *codec)
6693{
6694 struct ca0132_spec *spec = codec->spec;
6695
9a0869f4
TI		 6696#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6697 return; /* NOP */
6698#endif
e90f29e4 6699
e24aa0a4
TI		 6700 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6701 return; /* don't retry failures */
6702
b714a710 6703 chipio_enable_clocks(codec);
e93ac30a
CM		 6704 if (spec->dsp_state != DSP_DOWNLOADED) {
6705 spec->dsp_state = DSP_DOWNLOADING;
6706
6707 if (!ca0132_download_dsp_images(codec))
6708 spec->dsp_state = DSP_DOWNLOAD_FAILED;
6709 else
6710 spec->dsp_state = DSP_DOWNLOADED;
6711 }
e90f29e4 6712
009b8f97
CM		 6713 /* For codecs using alt functions, this is already done earlier */
6714 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 6715 ca0132_set_dsp_msr(codec, true);
6716}
6717
f8fb1170
TI		 6718static void ca0132_process_dsp_response(struct hda_codec *codec,
6719 struct hda_jack_callback *callback)
e90f29e4
IM		 6720{
6721 struct ca0132_spec *spec = codec->spec;
6722
4e76a883 6723 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 6724 if (spec->wait_scp) {
6725 if (dspio_get_response_data(codec) >= 0)
6726 spec->wait_scp = 0;
6727 }
6728
6729 dspio_clear_response_queue(codec);
6730}
6731
f8fb1170 6732static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 6733{
993884f6 6734 struct ca0132_spec *spec = codec->spec;
2ebab40e 6735 struct hda_jack_tbl *tbl;
e90f29e4 6736
f8fb1170
TI		 6737 /* Delay enabling the HP amp, to let the mic-detection
6738 * state machine run.
6739 */
6740 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 6741 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 6742 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6743 if (tbl)
6744 tbl->block_report = 1;
f8fb1170
TI		 6745}
6746
6747static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6748{
a1b7f016
CM		 6749 struct ca0132_spec *spec = codec->spec;
6750
6751 if (spec->use_alt_functions)
6752 ca0132_alt_select_in(codec);
6753 else
6754 ca0132_select_mic(codec);
f8fb1170
TI		 6755}
6756
6757static void ca0132_init_unsol(struct hda_codec *codec)
6758{
d5c016b5
GM		 6759 struct ca0132_spec *spec = codec->spec;
6760 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6761 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 6762 amic_callback);
6763 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6764 ca0132_process_dsp_response);
63177afc 6765 /* Front headphone jack detection */
009b8f97 6766 if (spec->use_alt_functions)
63177afc
CM		 6767 snd_hda_jack_detect_enable_callback(codec,
6768 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 6769}
6770
5aaca44d
IM		 6771/*
6772 * Verbs tables.
6773 */
6774
6775/* Sends before DSP download. */
6776static struct hda_verb ca0132_base_init_verbs[] = {
6777 /*enable ct extension*/
6778 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 6779 {}
6780};
6781
6782/* Send at exit. */
6783static struct hda_verb ca0132_base_exit_verbs[] = {
6784 /*set afg to D3*/
6785 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
6786 /*disable ct extension*/
6787 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6788 {}
6789};
6790
8a19bcee 6791/* Other verbs tables. Sends after DSP download. */
e93ac30a 6792
5aaca44d
IM		 6793static struct hda_verb ca0132_init_verbs0[] = {
6794 /* chip init verbs */
6795 {0x15, 0x70D, 0xF0},
6796 {0x15, 0x70E, 0xFE},
6797 {0x15, 0x707, 0x75},
6798 {0x15, 0x707, 0xD3},
6799 {0x15, 0x707, 0x09},
6800 {0x15, 0x707, 0x53},
6801 {0x15, 0x707, 0xD4},
6802 {0x15, 0x707, 0xEF},
6803 {0x15, 0x707, 0x75},
6804 {0x15, 0x707, 0xD3},
6805 {0x15, 0x707, 0x09},
6806 {0x15, 0x707, 0x02},
6807 {0x15, 0x707, 0x37},
6808 {0x15, 0x707, 0x78},
6809 {0x15, 0x53C, 0xCE},
6810 {0x15, 0x575, 0xC9},
6811 {0x15, 0x53D, 0xCE},
6812 {0x15, 0x5B7, 0xC9},
6813 {0x15, 0x70D, 0xE8},
6814 {0x15, 0x70E, 0xFE},
6815 {0x15, 0x707, 0x02},
6816 {0x15, 0x707, 0x68},
6817 {0x15, 0x707, 0x62},
6818 {0x15, 0x53A, 0xCE},
6819 {0x15, 0x546, 0xC9},
6820 {0x15, 0x53B, 0xCE},
6821 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 6822 {}
6823};
6824
6825/* Extra init verbs for SBZ */
6826static struct hda_verb sbz_init_verbs[] = {
6827 {0x15, 0x70D, 0x20},
6828 {0x15, 0x70E, 0x19},
6829 {0x15, 0x707, 0x00},
6830 {0x15, 0x539, 0xCE},
6831 {0x15, 0x546, 0xC9},
6832 {0x15, 0x70D, 0xB7},
6833 {0x15, 0x70E, 0x09},
6834 {0x15, 0x707, 0x10},
6835 {0x15, 0x70D, 0xAF},
6836 {0x15, 0x70E, 0x09},
6837 {0x15, 0x707, 0x01},
6838 {0x15, 0x707, 0x05},
6839 {0x15, 0x70D, 0x73},
6840 {0x15, 0x70E, 0x09},
6841 {0x15, 0x707, 0x14},
6842 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 6843 {}
6844};
6845
95c6e9cb
IM		 6846static void ca0132_init_chip(struct hda_codec *codec)
6847{
6848 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 6849 int num_fx;
6850 int i;
6851 unsigned int on;
95c6e9cb
IM		 6852
6853 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 6854
6855 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 6856 if (!spec->use_alt_functions)
6857 spec->cur_mic_type = DIGITAL_MIC;
6858 else
6859 spec->cur_mic_type = REAR_MIC;
6860
5aaca44d
IM		 6861 spec->cur_mic_boost = 0;
6862
6863 for (i = 0; i < VNODES_COUNT; i++) {
6864 spec->vnode_lvol[i] = 0x5a;
6865 spec->vnode_rvol[i] = 0x5a;
6866 spec->vnode_lswitch[i] = 0;
6867 spec->vnode_rswitch[i] = 0;
6868 }
6869
6870 /*
6871 * Default states for effects are in ca0132_effects[].
6872 */
6873 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6874 for (i = 0; i < num_fx; i++) {
6875 on = (unsigned int)ca0132_effects[i].reqs[0];
6876 spec->effects_switch[i] = on ? 1 : 0;
6877 }
47cdf76e
CM		 6878 /*
6879 * Sets defaults for the effect slider controls, only for alternative
6880 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6881 */
6882 if (spec->use_alt_controls) {
6883 spec->xbass_xover_freq = 8;
6884 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6885 spec->fx_ctl_val[i] = effect_slider_defaults[i];
6886 }
5aaca44d
IM		 6887
6888 spec->voicefx_val = 0;
6889 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6890 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
6891
44f0c978
IM		 6892#ifdef ENABLE_TUNING_CONTROLS
6893 ca0132_init_tuning_defaults(codec);
6894#endif
95c6e9cb
IM		 6895}
6896
2e48b2b7
CM		 6897/*
6898 * Recon3Di exit specific commands.
6899 */
6900/* prevents popping noise on shutdown */
6901static void r3di_gpio_shutdown(struct hda_codec *codec)
6902{
6903 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
6904}
6905
6906/*
6907 * Sound Blaster Z exit specific commands.
6908 */
6909static void sbz_region2_exit(struct hda_codec *codec)
6910{
6911 struct ca0132_spec *spec = codec->spec;
6912 unsigned int i;
6913
6914 for (i = 0; i < 4; i++)
6915 writeb(0x0, spec->mem_base + 0x100);
6916 for (i = 0; i < 8; i++)
6917 writeb(0xb3, spec->mem_base + 0x304);
a62e4739
CM		 6918
6919 ca0132_mmio_gpio_set(codec, 0, false);
6920 ca0132_mmio_gpio_set(codec, 1, false);
6921 ca0132_mmio_gpio_set(codec, 4, true);
6922 ca0132_mmio_gpio_set(codec, 5, false);
6923 ca0132_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 6924}
6925
6926static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6927{
6928 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6929 unsigned int i;
6930
6931 snd_hda_codec_write(codec, 0x11, 0,
6932 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6933
6934 for (i = 0; i < 5; i++)
6935 snd_hda_codec_write(codec, pins[i], 0,
6936 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6937}
6938
6939static void sbz_clear_unsolicited(struct hda_codec *codec)
6940{
6941 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6942 unsigned int i;
6943
6944 for (i = 0; i < 7; i++) {
6945 snd_hda_codec_write(codec, pins[i], 0,
6946 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6947 }
6948}
6949
6950/* On shutdown, sends commands in sets of three */
6951static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
6952 int mask, int data)
6953{
6954 if (dir >= 0)
6955 snd_hda_codec_write(codec, 0x01, 0,
6956 AC_VERB_SET_GPIO_DIRECTION, dir);
6957 if (mask >= 0)
6958 snd_hda_codec_write(codec, 0x01, 0,
6959 AC_VERB_SET_GPIO_MASK, mask);
6960
6961 if (data >= 0)
6962 snd_hda_codec_write(codec, 0x01, 0,
6963 AC_VERB_SET_GPIO_DATA, data);
6964}
6965
6966static void sbz_exit_chip(struct hda_codec *codec)
6967{
009b8f97
CM		 6968 chipio_set_stream_control(codec, 0x03, 0);
6969 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 6970
6971 /* Mess with GPIO */
6972 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
6973 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
6974 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
6975
009b8f97
CM		 6976 chipio_set_stream_control(codec, 0x14, 0);
6977 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 6978
6979 chipio_set_conn_rate(codec, 0x41, SR_192_000);
6980 chipio_set_conn_rate(codec, 0x91, SR_192_000);
6981
6982 chipio_write(codec, 0x18a020, 0x00000083);
6983
6984 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
6985 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
6986 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
6987
009b8f97 6988 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 6989
6990 chipio_set_control_param(codec, 0x0D, 0x24);
6991
6992 sbz_clear_unsolicited(codec);
6993 sbz_set_pin_ctl_default(codec);
6994
6995 snd_hda_codec_write(codec, 0x0B, 0,
6996 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
6997
6998 if (dspload_is_loaded(codec))
6999 dsp_reset(codec);
7000
7001 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7002 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x00);
7003
7004 sbz_region2_exit(codec);
7005}
7006
95c6e9cb
IM		 7007static void ca0132_exit_chip(struct hda_codec *codec)
7008{
7009 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7010
7011 if (dspload_is_loaded(codec))
7012 dsp_reset(codec);
95c6e9cb
IM		 7013}
7014
38ba69ff
CM		 7015/*
7016 * This fixes a problem that was hard to reproduce. Very rarely, I would
7017 * boot up, and there would be no sound, but the DSP indicated it had loaded
7018 * properly. I did a few memory dumps to see if anything was different, and
7019 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7020 * checks if those areas are uninitialized, and if they are, it'll attempt to
7021 * reload the card 3 times. Usually it fixes by the second.
7022 */
7023static void sbz_dsp_startup_check(struct hda_codec *codec)
7024{
7025 struct ca0132_spec *spec = codec->spec;
7026 unsigned int dsp_data_check[4];
7027 unsigned int cur_address = 0x390;
7028 unsigned int i;
7029 unsigned int failure = 0;
7030 unsigned int reload = 3;
7031
7032 if (spec->startup_check_entered)
7033 return;
7034
7035 spec->startup_check_entered = true;
7036
7037 for (i = 0; i < 4; i++) {
7038 chipio_read(codec, cur_address, &dsp_data_check[i]);
7039 cur_address += 0x4;
7040 }
7041 for (i = 0; i < 4; i++) {
7042 if (dsp_data_check[i] == 0xa1a2a3a4)
7043 failure = 1;
7044 }
7045
7046 codec_dbg(codec, "Startup Check: %d ", failure);
7047 if (failure)
7048 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7049 /*
7050 * While the failure condition is true, and we haven't reached our
7051 * three reload limit, continue trying to reload the driver and
7052 * fix the issue.
7053 */
7054 while (failure && (reload != 0)) {
7055 codec_info(codec, "Reloading... Tries left: %d", reload);
7056 sbz_exit_chip(codec);
7057 spec->dsp_state = DSP_DOWNLOAD_INIT;
7058 codec->patch_ops.init(codec);
7059 failure = 0;
7060 for (i = 0; i < 4; i++) {
7061 chipio_read(codec, cur_address, &dsp_data_check[i]);
7062 cur_address += 0x4;
7063 }
7064 for (i = 0; i < 4; i++) {
7065 if (dsp_data_check[i] == 0xa1a2a3a4)
7066 failure = 1;
7067 }
7068 reload--;
7069 }
7070
7071 if (!failure && reload < 3)
7072 codec_info(codec, "DSP fixed.");
7073
7074 if (!failure)
7075 return;
7076
7077 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7078}
7079
e93ac30a
CM		 7080/*
7081 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7082 * extra precision for decibel values. If you had the dB value in floating point
7083 * you would take the value after the decimal point, multiply by 64, and divide
7084 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7085 * implement fixed point or floating point dB volumes. For now, I'll set them
7086 * to 0 just incase a value has lingered from a boot into Windows.
7087 */
7088static void ca0132_alt_vol_setup(struct hda_codec *codec)
7089{
7090 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7091 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7092 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7093 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7094 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7095 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7096 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7097 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7098}
7099
7100/*
7101 * Extra commands that don't really fit anywhere else.
7102 */
7103static void sbz_pre_dsp_setup(struct hda_codec *codec)
7104{
7105 struct ca0132_spec *spec = codec->spec;
7106
7107 writel(0x00820680, spec->mem_base + 0x01C);
7108 writel(0x00820680, spec->mem_base + 0x01C);
7109
7110 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7111 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7112 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7113 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7114
7115 chipio_write(codec, 0x18b0a4, 0x000000c2);
7116
7117 snd_hda_codec_write(codec, 0x11, 0,
7118 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7119}
7120
7121/*
7122 * Extra commands that don't really fit anywhere else.
7123 */
7124static void r3di_pre_dsp_setup(struct hda_codec *codec)
7125{
7126 chipio_write(codec, 0x18b0a4, 0x000000c2);
7127
7128 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7129 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7130 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7131 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7132 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7133 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7134
7135 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7136 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7137 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7138 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7139 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7140 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7141 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7142 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7143
7144 snd_hda_codec_write(codec, 0x11, 0,
7145 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7146}
7147
7148
7149/*
7150 * These are sent before the DSP is downloaded. Not sure
7151 * what they do, or if they're necessary. Could possibly
7152 * be removed. Figure they're better to leave in.
7153 */
7154static void sbz_region2_startup(struct hda_codec *codec)
7155{
7156 struct ca0132_spec *spec = codec->spec;
7157
7158 writel(0x00000000, spec->mem_base + 0x400);
7159 writel(0x00000000, spec->mem_base + 0x408);
7160 writel(0x00000000, spec->mem_base + 0x40C);
7161 writel(0x00880680, spec->mem_base + 0x01C);
7162 writel(0x00000083, spec->mem_base + 0xC0C);
7163 writel(0x00000030, spec->mem_base + 0xC00);
7164 writel(0x00000000, spec->mem_base + 0xC04);
7165 writel(0x00000003, spec->mem_base + 0xC0C);
7166 writel(0x00000003, spec->mem_base + 0xC0C);
7167 writel(0x00000003, spec->mem_base + 0xC0C);
7168 writel(0x00000003, spec->mem_base + 0xC0C);
7169 writel(0x000000C1, spec->mem_base + 0xC08);
7170 writel(0x000000F1, spec->mem_base + 0xC08);
7171 writel(0x00000001, spec->mem_base + 0xC08);
7172 writel(0x000000C7, spec->mem_base + 0xC08);
7173 writel(0x000000C1, spec->mem_base + 0xC08);
7174 writel(0x00000080, spec->mem_base + 0xC04);
7175}
7176
7177/*
7178 * Extra init functions for alternative ca0132 codecs. Done
7179 * here so they don't clutter up the main ca0132_init function
7180 * anymore than they have to.
7181 */
7182static void ca0132_alt_init(struct hda_codec *codec)
7183{
7184 struct ca0132_spec *spec = codec->spec;
7185
7186 ca0132_alt_vol_setup(codec);
7187
7188 switch (spec->quirk) {
7189 case QUIRK_SBZ:
7190 codec_dbg(codec, "SBZ alt_init");
7191 ca0132_gpio_init(codec);
7192 sbz_pre_dsp_setup(codec);
7193 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7194 snd_hda_sequence_write(codec, spec->sbz_init_verbs);
7195 break;
7196 case QUIRK_R3DI:
7197 codec_dbg(codec, "R3DI alt_init");
7198 ca0132_gpio_init(codec);
7199 ca0132_gpio_setup(codec);
7e6ed62e 7200 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 7201 r3di_pre_dsp_setup(codec);
7202 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7203 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7204 break;
7205 }
7206}
7207
95c6e9cb
IM		 7208static int ca0132_init(struct hda_codec *codec)
7209{
7210 struct ca0132_spec *spec = codec->spec;
7211 struct auto_pin_cfg *cfg = &spec->autocfg;
7212 int i;
e93ac30a
CM		 7213 bool dsp_loaded;
7214
7215 /*
7216 * If the DSP is already downloaded, and init has been entered again,
7217 * there's only two reasons for it. One, the codec has awaken from a
7218 * suspended state, and in that case dspload_is_loaded will return
7219 * false, and the init will be ran again. The other reason it gets
7220 * re entered is on startup for some reason it triggers a suspend and
7221 * resume state. In this case, it will check if the DSP is downloaded,
7222 * and not run the init function again. For codecs using alt_functions,
7223 * it will check if the DSP is loaded properly.
7224 */
7225 if (spec->dsp_state == DSP_DOWNLOADED) {
7226 dsp_loaded = dspload_is_loaded(codec);
7227 if (!dsp_loaded) {
7228 spec->dsp_reload = true;
7229 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 7230 } else {
7231 if (spec->quirk == QUIRK_SBZ)
7232 sbz_dsp_startup_check(codec);
e93ac30a 7233 return 0;
38ba69ff 7234 }
e93ac30a 7235 }
95c6e9cb 7236
e24aa0a4
TI		 7237 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7238 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 7239 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 7240
e93ac30a
CM		 7241 if (spec->quirk == QUIRK_SBZ)
7242 sbz_region2_startup(codec);
7243
664c7155 7244 snd_hda_power_up_pm(codec);
5aaca44d 7245
f8fb1170 7246 ca0132_init_unsol(codec);
5aaca44d
IM		 7247 ca0132_init_params(codec);
7248 ca0132_init_flags(codec);
7e6ed62e 7249
5aaca44d 7250 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 7251
365c7f25 7252 if (spec->use_alt_functions)
e93ac30a
CM		 7253 ca0132_alt_init(codec);
7254
01ef7dbf 7255 ca0132_download_dsp(codec);
7e6ed62e 7256
5aaca44d 7257 ca0132_refresh_widget_caps(codec);
e93ac30a 7258
7e6ed62e
CM		 7259 switch (spec->quirk) {
7260 case QUIRK_R3DI:
7261 r3di_setup_defaults(codec);
7262 break;
126b75e0 7263 case QUIRK_SBZ:
d97420d2 7264 sbz_setup_defaults(codec);
126b75e0
AB		 7265 break;
7266 default:
38ba69ff
CM		 7267 ca0132_setup_defaults(codec);
7268 ca0132_init_analog_mic2(codec);
7269 ca0132_init_dmic(codec);
7e6ed62e 7270 break;
38ba69ff 7271 }
5aaca44d
IM		 7272
7273 for (i = 0; i < spec->num_outputs; i++)
7274 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 7275
95c6e9cb
IM		 7276 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7277
7278 for (i = 0; i < spec->num_inputs; i++)
7279 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7280
7281 init_input(codec, cfg->dig_in_pin, spec->dig_in);
7282
009b8f97 7283 if (!spec->use_alt_functions) {
e93ac30a
CM		 7284 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7285 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7286 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7287 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7288 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7289 }
7290
7cb9d94c 7291 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 7292 ca0132_gpio_setup(codec);
7293
d5c016b5 7294 snd_hda_sequence_write(codec, spec->spec_init_verbs);
d97420d2 7295 if (spec->use_alt_functions) {
7cb9d94c
CM		 7296 ca0132_alt_select_out(codec);
7297 ca0132_alt_select_in(codec);
d97420d2 7298 } else {
7cb9d94c
CM		 7299 ca0132_select_out(codec);
7300 ca0132_select_mic(codec);
7cb9d94c 7301 }
5aaca44d 7302
a73d511c
IM		 7303 snd_hda_jack_report_sync(codec);
7304
e93ac30a
CM		 7305 /*
7306 * Re set the PlayEnhancement switch on a resume event, because the
7307 * controls will not be reloaded.
7308 */
7309 if (spec->dsp_reload) {
7310 spec->dsp_reload = false;
7311 ca0132_pe_switch_set(codec);
7312 }
7313
664c7155 7314 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 7315
7316 return 0;
7317}
7318
95c6e9cb
IM		 7319static void ca0132_free(struct hda_codec *codec)
7320{
5aaca44d
IM		 7321 struct ca0132_spec *spec = codec->spec;
7322
993884f6 7323 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 7324 snd_hda_power_up(codec);
2e48b2b7
CM		 7325 switch (spec->quirk) {
7326 case QUIRK_SBZ:
7327 sbz_exit_chip(codec);
7328 break;
7329 case QUIRK_R3DI:
7330 r3di_gpio_shutdown(codec);
7331 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7332 ca0132_exit_chip(codec);
7333 break;
7334 default:
7335 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7336 ca0132_exit_chip(codec);
7337 break;
7338 }
5aaca44d 7339 snd_hda_power_down(codec);
aa31704f
CM		 7340 if (spec->mem_base)
7341 iounmap(spec->mem_base);
d5c016b5 7342 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 7343 kfree(codec->spec);
7344}
7345
2e48b2b7
CM		 7346static void ca0132_reboot_notify(struct hda_codec *codec)
7347{
7348 codec->patch_ops.free(codec);
7349}
7350
071f1344 7351static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 7352 .build_controls = ca0132_build_controls,
7353 .build_pcms = ca0132_build_pcms,
7354 .init = ca0132_init,
7355 .free = ca0132_free,
f8fb1170 7356 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 7357 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 7358};
7359
441aa6a0
IM		 7360static void ca0132_config(struct hda_codec *codec)
7361{
7362 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 7363
7364 spec->dacs[0] = 0x2;
7365 spec->dacs[1] = 0x3;
7366 spec->dacs[2] = 0x4;
7367
7368 spec->multiout.dac_nids = spec->dacs;
7369 spec->multiout.num_dacs = 3;
441aa6a0 7370
009b8f97 7371 if (!spec->use_alt_functions)
63177afc
CM		 7372 spec->multiout.max_channels = 2;
7373 else
7374 spec->multiout.max_channels = 6;
7375
7376 switch (spec->quirk) {
7377 case QUIRK_ALIENWARE:
d5c016b5 7378 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 7379 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7380
7381 spec->num_outputs = 2;
7382 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 7383 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 7384 spec->shared_out_nid = 0x2;
7385 spec->unsol_tag_hp = 0x0f;
7386
7387 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7388 spec->adcs[1] = 0x8; /* analog mic2 */
7389 spec->adcs[2] = 0xa; /* what u hear */
7390
7391 spec->num_inputs = 3;
7392 spec->input_pins[0] = 0x12;
7393 spec->input_pins[1] = 0x11;
7394 spec->input_pins[2] = 0x13;
7395 spec->shared_mic_nid = 0x7;
7396 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 7397 break;
7398 case QUIRK_SBZ:
7399 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7400 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7401
7402 spec->num_outputs = 2;
7403 spec->out_pins[0] = 0x0B; /* Line out */
7404 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7405 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7406 spec->out_pins[3] = 0x11; /* Rear surround */
7407 spec->shared_out_nid = 0x2;
7408 spec->unsol_tag_hp = spec->out_pins[1];
7409 spec->unsol_tag_front_hp = spec->out_pins[2];
7410
7411 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7412 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7413 spec->adcs[2] = 0xa; /* what u hear */
7414
7415 spec->num_inputs = 2;
7416 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7417 spec->input_pins[1] = 0x13; /* What U Hear */
7418 spec->shared_mic_nid = 0x7;
7419 spec->unsol_tag_amic1 = spec->input_pins[0];
7420
7421 /* SPDIF I/O */
7422 spec->dig_out = 0x05;
7423 spec->multiout.dig_out_nid = spec->dig_out;
63177afc 7424 spec->dig_in = 0x09;
63177afc
CM		 7425 break;
7426 case QUIRK_R3DI:
7427 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7428 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7429
7430 spec->num_outputs = 2;
7431 spec->out_pins[0] = 0x0B; /* Line out */
7432 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7433 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7434 spec->out_pins[3] = 0x11; /* Rear surround */
7435 spec->shared_out_nid = 0x2;
7436 spec->unsol_tag_hp = spec->out_pins[1];
7437 spec->unsol_tag_front_hp = spec->out_pins[2];
7438
7439 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7440 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7441 spec->adcs[2] = 0x0a; /* what u hear */
7442
7443 spec->num_inputs = 2;
7444 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7445 spec->input_pins[1] = 0x13; /* What U Hear */
7446 spec->shared_mic_nid = 0x7;
7447 spec->unsol_tag_amic1 = spec->input_pins[0];
7448
7449 /* SPDIF I/O */
7450 spec->dig_out = 0x05;
7451 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 7452 break;
7453 default:
fe14f39e
TI		 7454 spec->num_outputs = 2;
7455 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 7456 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 7457 spec->shared_out_nid = 0x2;
7458 spec->unsol_tag_hp = spec->out_pins[1];
7459
7460 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7461 spec->adcs[1] = 0x8; /* analog mic2 */
7462 spec->adcs[2] = 0xa; /* what u hear */
7463
7464 spec->num_inputs = 3;
7465 spec->input_pins[0] = 0x12;
7466 spec->input_pins[1] = 0x11;
7467 spec->input_pins[2] = 0x13;
7468 spec->shared_mic_nid = 0x7;
7469 spec->unsol_tag_amic1 = spec->input_pins[0];
7470
7471 /* SPDIF I/O */
7472 spec->dig_out = 0x05;
7473 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 7474 spec->dig_in = 0x09;
63177afc 7475 break;
d5c016b5 7476 }
441aa6a0
IM		 7477}
7478
d5c016b5
GM		 7479static int ca0132_prepare_verbs(struct hda_codec *codec)
7480{
7481/* Verbs + terminator (an empty element) */
a3d90d67 7482#define NUM_SPEC_VERBS 2
d5c016b5
GM		 7483 struct ca0132_spec *spec = codec->spec;
7484
7485 spec->chip_init_verbs = ca0132_init_verbs0;
e93ac30a
CM		 7486 if (spec->quirk == QUIRK_SBZ)
7487 spec->sbz_init_verbs = sbz_init_verbs;
6396bb22
KC		 7488 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7489 sizeof(struct hda_verb),
7490 GFP_KERNEL);
d5c016b5
GM		 7491 if (!spec->spec_init_verbs)
7492 return -ENOMEM;
7493
d5c016b5 7494 /* config EAPD */
a3d90d67
AB		 7495 spec->spec_init_verbs[0].nid = 0x0b;
7496 spec->spec_init_verbs[0].param = 0x78D;
7497 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 7498
7499 /* Previously commented configuration */
7500 /*
a3d90d67
AB		 7501 spec->spec_init_verbs[2].nid = 0x0b;
7502 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
7503 spec->spec_init_verbs[2].verb = 0x02;
7504
7505 spec->spec_init_verbs[3].nid = 0x10;
7506 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 7507 spec->spec_init_verbs[3].verb = 0x02;
7508
7509 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 7510 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 7511 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 7512 */
7513
7514 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7515 return 0;
7516}
7517
95c6e9cb
IM		 7518static int patch_ca0132(struct hda_codec *codec)
7519{
7520 struct ca0132_spec *spec;
a73d511c 7521 int err;
d5c016b5 7522 const struct snd_pci_quirk *quirk;
95c6e9cb 7523
4e76a883 7524 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 7525
7526 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7527 if (!spec)
7528 return -ENOMEM;
7529 codec->spec = spec;
993884f6 7530 spec->codec = codec;
95c6e9cb 7531
225068ab
TI		 7532 codec->patch_ops = ca0132_patch_ops;
7533 codec->pcm_format_first = 1;
7534 codec->no_sticky_stream = 1;
7535
d5c016b5
GM		 7536 /* Detect codec quirk */
7537 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7538 if (quirk)
7539 spec->quirk = quirk->value;
7540 else
7541 spec->quirk = QUIRK_NONE;
7542
aa31704f
CM		 7543 /* Setup BAR Region 2 for Sound Blaster Z */
7544 if (spec->quirk == QUIRK_SBZ) {
7545 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7546 if (spec->mem_base == NULL) {
7547 codec_warn(codec, "pci_iomap failed!");
7548 codec_info(codec, "perhaps this is not an SBZ?");
7549 spec->quirk = QUIRK_NONE;
7550 }
7551 }
009b8f97 7552
e24aa0a4 7553 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 7554 spec->num_mixers = 1;
017310fb
CM		 7555
7556 /* Set which mixers each quirk uses. */
7557 switch (spec->quirk) {
7558 case QUIRK_SBZ:
7559 spec->mixers[0] = sbz_mixer;
7560 snd_hda_codec_set_name(codec, "Sound Blaster Z");
7561 break;
7562 case QUIRK_R3DI:
7563 spec->mixers[0] = r3di_mixer;
7564 snd_hda_codec_set_name(codec, "Recon3Di");
7565 break;
7566 default:
7567 spec->mixers[0] = ca0132_mixer;
7568 break;
7569 }
a7e76271 7570
47cdf76e 7571 /* Setup whether or not to use alt functions/controls */
009b8f97
CM		 7572 switch (spec->quirk) {
7573 case QUIRK_SBZ:
7574 case QUIRK_R3DI:
47cdf76e 7575 spec->use_alt_controls = true;
009b8f97
CM		 7576 spec->use_alt_functions = true;
7577 break;
7578 default:
47cdf76e 7579 spec->use_alt_controls = false;
009b8f97
CM		 7580 spec->use_alt_functions = false;
7581 break;
7582 }
7583
5aaca44d
IM		 7584 spec->base_init_verbs = ca0132_base_init_verbs;
7585 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 7586
993884f6
CCC		 7587 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7588
95c6e9cb
IM		 7589 ca0132_init_chip(codec);
7590
7591 ca0132_config(codec);
7592
d5c016b5
GM		 7593 err = ca0132_prepare_verbs(codec);
7594 if (err < 0)
cc91ceaf 7595 goto error;
d5c016b5 7596
a73d511c
IM		 7597 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7598 if (err < 0)
cc91ceaf 7599 goto error;
a73d511c 7600
95c6e9cb 7601 return 0;
cc91ceaf
TI		 7602
7603 error:
7604 ca0132_free(codec);
7605 return err;
95c6e9cb
IM		 7606}
7607
7608/*
7609 * patch entries
7610 */
b9a94a9c
TI		 7611static struct hda_device_id snd_hda_id_ca0132[] = {
7612 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 7613 {} /* terminator */
7614};
b9a94a9c 7615MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 7616
7617MODULE_LICENSE("GPL");
406261ce 7618MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 7619
d8a766a1 7620static struct hda_codec_driver ca0132_driver = {
b9a94a9c 7621 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 7622};
7623
d8a766a1 7624module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)