projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda_intel: Add Device IDs for Intel Wellsburg PCH
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/pci.h>
28#include <linux/mutex.h>
da155d5b 29#include <linux/module.h>
4aa3bb0c 30#include <linux/firmware.h>
95c6e9cb
IM		 31#include <sound/core.h>
32#include "hda_codec.h"
33#include "hda_local.h"
128bc4ba 34#include "hda_auto_parser.h"
5aaca44d 35#include "hda_jack.h"
95c6e9cb 36
bcd109c0
IM		 37#include "ca0132_regs.h"
38
ef6b2ead
IM		 39/* Enable this to see controls for tuning purpose. */
40/*#define ENABLE_TUNING_CONTROLS*/
41
42#define FLOAT_ZERO 0x00000000
43#define FLOAT_ONE 0x3f800000
44#define FLOAT_TWO 0x40000000
45#define FLOAT_MINUS_5 0xc0a00000
46
47#define UNSOL_TAG_HP 0x10
48#define UNSOL_TAG_AMIC1 0x12
49#define UNSOL_TAG_DSP 0x16
50
4aa3bb0c
IM		 51#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
52#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
53
54#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
55#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
56#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
57
58#define MASTERCONTROL 0x80
ef6b2ead
IM		 59#define MASTERCONTROL_ALLOC_DMA_CHAN 10
60#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 61
95c6e9cb
IM		 62#define WIDGET_CHIP_CTRL 0x15
63#define WIDGET_DSP_CTRL 0x16
64
4aa3bb0c
IM		 65#define MEM_CONNID_MICIN1 3
66#define MEM_CONNID_MICIN2 5
67#define MEM_CONNID_MICOUT1 12
68#define MEM_CONNID_MICOUT2 14
69#define MEM_CONNID_WUH 10
70#define MEM_CONNID_DSP 16
71#define MEM_CONNID_DMIC 100
72
73#define SCP_SET 0
74#define SCP_GET 1
75
01ef7dbf
IM		 76#define EFX_FILE "ctefx.bin"
77
24f3cede 78#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 79MODULE_FIRMWARE(EFX_FILE);
7a527ede 80#endif
01ef7dbf 81
ef6b2ead
IM		 82static char *dirstr[2] = { "Playback", "Capture" };
83
84enum {
85 SPEAKER_OUT,
86 HEADPHONE_OUT
87};
88
89enum {
90 DIGITAL_MIC,
91 LINE_MIC_IN
92};
93
94enum {
95#define VNODE_START_NID 0x80
96 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
97 VNID_MIC,
98 VNID_HP_SEL,
99 VNID_AMIC1_SEL,
100 VNID_HP_ASEL,
101 VNID_AMIC1_ASEL,
102 VNODE_END_NID,
103#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
104
105#define EFFECT_START_NID 0x90
106#define OUT_EFFECT_START_NID EFFECT_START_NID
107 SURROUND = OUT_EFFECT_START_NID,
108 CRYSTALIZER,
109 DIALOG_PLUS,
110 SMART_VOLUME,
111 X_BASS,
112 EQUALIZER,
113 OUT_EFFECT_END_NID,
114#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
115
116#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
117 ECHO_CANCELLATION = IN_EFFECT_START_NID,
118 VOICE_FOCUS,
119 MIC_SVM,
120 NOISE_REDUCTION,
121 IN_EFFECT_END_NID,
122#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
123
124 VOICEFX = IN_EFFECT_END_NID,
125 PLAY_ENHANCEMENT,
126 CRYSTAL_VOICE,
127 EFFECT_END_NID
128#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
129};
130
131/* Effects values size*/
132#define EFFECT_VALS_MAX_COUNT 12
133
134struct ct_effect {
135 char name[44];
136 hda_nid_t nid;
137 int mid; /*effect module ID*/
138 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
139 int direct; /* 0:output; 1:input*/
140 int params; /* number of default non-on/off params */
141 /*effect default values, 1st is on/off. */
142 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
143};
144
145#define EFX_DIR_OUT 0
146#define EFX_DIR_IN 1
147
148static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
149 { .name = "Surround",
150 .nid = SURROUND,
151 .mid = 0x96,
152 .reqs = {0, 1},
153 .direct = EFX_DIR_OUT,
154 .params = 1,
155 .def_vals = {0x3F800000, 0x3F2B851F}
156 },
157 { .name = "Crystalizer",
158 .nid = CRYSTALIZER,
159 .mid = 0x96,
160 .reqs = {7, 8},
161 .direct = EFX_DIR_OUT,
162 .params = 1,
163 .def_vals = {0x3F800000, 0x3F266666}
164 },
165 { .name = "Dialog Plus",
166 .nid = DIALOG_PLUS,
167 .mid = 0x96,
168 .reqs = {2, 3},
169 .direct = EFX_DIR_OUT,
170 .params = 1,
171 .def_vals = {0x00000000, 0x3F000000}
172 },
173 { .name = "Smart Volume",
174 .nid = SMART_VOLUME,
175 .mid = 0x96,
176 .reqs = {4, 5, 6},
177 .direct = EFX_DIR_OUT,
178 .params = 2,
179 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
180 },
181 { .name = "X-Bass",
182 .nid = X_BASS,
183 .mid = 0x96,
184 .reqs = {24, 23, 25},
185 .direct = EFX_DIR_OUT,
186 .params = 2,
187 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
188 },
189 { .name = "Equalizer",
190 .nid = EQUALIZER,
191 .mid = 0x96,
192 .reqs = {9, 10, 11, 12, 13, 14,
193 15, 16, 17, 18, 19, 20},
194 .direct = EFX_DIR_OUT,
195 .params = 11,
196 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
197 0x00000000, 0x00000000, 0x00000000, 0x00000000,
198 0x00000000, 0x00000000, 0x00000000, 0x00000000}
199 },
200 { .name = "Echo Cancellation",
201 .nid = ECHO_CANCELLATION,
202 .mid = 0x95,
203 .reqs = {0, 1, 2, 3},
204 .direct = EFX_DIR_IN,
205 .params = 3,
206 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
207 },
208 { .name = "Voice Focus",
209 .nid = VOICE_FOCUS,
210 .mid = 0x95,
211 .reqs = {6, 7, 8, 9},
212 .direct = EFX_DIR_IN,
213 .params = 3,
214 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
215 },
216 { .name = "Mic SVM",
217 .nid = MIC_SVM,
218 .mid = 0x95,
219 .reqs = {44, 45},
220 .direct = EFX_DIR_IN,
221 .params = 1,
222 .def_vals = {0x00000000, 0x3F3D70A4}
223 },
224 { .name = "Noise Reduction",
225 .nid = NOISE_REDUCTION,
226 .mid = 0x95,
227 .reqs = {4, 5},
228 .direct = EFX_DIR_IN,
229 .params = 1,
230 .def_vals = {0x3F800000, 0x3F000000}
231 },
232 { .name = "VoiceFX",
233 .nid = VOICEFX,
234 .mid = 0x95,
235 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
236 .direct = EFX_DIR_IN,
237 .params = 8,
238 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
239 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
240 0x00000000}
241 }
242};
243
244/* Tuning controls */
245#ifdef ENABLE_TUNING_CONTROLS
246
247enum {
248#define TUNING_CTL_START_NID 0xC0
249 WEDGE_ANGLE = TUNING_CTL_START_NID,
250 SVM_LEVEL,
251 EQUALIZER_BAND_0,
252 EQUALIZER_BAND_1,
253 EQUALIZER_BAND_2,
254 EQUALIZER_BAND_3,
255 EQUALIZER_BAND_4,
256 EQUALIZER_BAND_5,
257 EQUALIZER_BAND_6,
258 EQUALIZER_BAND_7,
259 EQUALIZER_BAND_8,
260 EQUALIZER_BAND_9,
261 TUNING_CTL_END_NID
262#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
263};
264
265struct ct_tuning_ctl {
266 char name[44];
267 hda_nid_t parent_nid;
268 hda_nid_t nid;
269 int mid; /*effect module ID*/
270 int req; /*effect module request*/
271 int direct; /* 0:output; 1:input*/
272 unsigned int def_val;/*effect default values*/
273};
274
275static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
276 { .name = "Wedge Angle",
277 .parent_nid = VOICE_FOCUS,
278 .nid = WEDGE_ANGLE,
279 .mid = 0x95,
280 .req = 8,
281 .direct = EFX_DIR_IN,
282 .def_val = 0x41F00000
283 },
284 { .name = "SVM Level",
285 .parent_nid = MIC_SVM,
286 .nid = SVM_LEVEL,
287 .mid = 0x95,
288 .req = 45,
289 .direct = EFX_DIR_IN,
290 .def_val = 0x3F3D70A4
291 },
292 { .name = "EQ Band0",
293 .parent_nid = EQUALIZER,
294 .nid = EQUALIZER_BAND_0,
295 .mid = 0x96,
296 .req = 11,
297 .direct = EFX_DIR_OUT,
298 .def_val = 0x00000000
299 },
300 { .name = "EQ Band1",
301 .parent_nid = EQUALIZER,
302 .nid = EQUALIZER_BAND_1,
303 .mid = 0x96,
304 .req = 12,
305 .direct = EFX_DIR_OUT,
306 .def_val = 0x00000000
307 },
308 { .name = "EQ Band2",
309 .parent_nid = EQUALIZER,
310 .nid = EQUALIZER_BAND_2,
311 .mid = 0x96,
312 .req = 13,
313 .direct = EFX_DIR_OUT,
314 .def_val = 0x00000000
315 },
316 { .name = "EQ Band3",
317 .parent_nid = EQUALIZER,
318 .nid = EQUALIZER_BAND_3,
319 .mid = 0x96,
320 .req = 14,
321 .direct = EFX_DIR_OUT,
322 .def_val = 0x00000000
323 },
324 { .name = "EQ Band4",
325 .parent_nid = EQUALIZER,
326 .nid = EQUALIZER_BAND_4,
327 .mid = 0x96,
328 .req = 15,
329 .direct = EFX_DIR_OUT,
330 .def_val = 0x00000000
331 },
332 { .name = "EQ Band5",
333 .parent_nid = EQUALIZER,
334 .nid = EQUALIZER_BAND_5,
335 .mid = 0x96,
336 .req = 16,
337 .direct = EFX_DIR_OUT,
338 .def_val = 0x00000000
339 },
340 { .name = "EQ Band6",
341 .parent_nid = EQUALIZER,
342 .nid = EQUALIZER_BAND_6,
343 .mid = 0x96,
344 .req = 17,
345 .direct = EFX_DIR_OUT,
346 .def_val = 0x00000000
347 },
348 { .name = "EQ Band7",
349 .parent_nid = EQUALIZER,
350 .nid = EQUALIZER_BAND_7,
351 .mid = 0x96,
352 .req = 18,
353 .direct = EFX_DIR_OUT,
354 .def_val = 0x00000000
355 },
356 { .name = "EQ Band8",
357 .parent_nid = EQUALIZER,
358 .nid = EQUALIZER_BAND_8,
359 .mid = 0x96,
360 .req = 19,
361 .direct = EFX_DIR_OUT,
362 .def_val = 0x00000000
363 },
364 { .name = "EQ Band9",
365 .parent_nid = EQUALIZER,
366 .nid = EQUALIZER_BAND_9,
367 .mid = 0x96,
368 .req = 20,
369 .direct = EFX_DIR_OUT,
370 .def_val = 0x00000000
371 }
372};
373#endif
374
375/* Voice FX Presets */
376#define VOICEFX_MAX_PARAM_COUNT 9
377
378struct ct_voicefx {
379 char *name;
380 hda_nid_t nid;
381 int mid;
382 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
383};
384
385struct ct_voicefx_preset {
386 char *name; /*preset name*/
387 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
388};
389
ccd7bd3d 390static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 391 .name = "VoiceFX Capture Switch",
392 .nid = VOICEFX,
393 .mid = 0x95,
394 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
395};
396
ccd7bd3d 397static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 398 { .name = "Neutral",
399 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
400 0x44FA0000, 0x3F800000, 0x3F800000,
401 0x3F800000, 0x00000000, 0x00000000 }
402 },
403 { .name = "Female2Male",
404 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
405 0x44FA0000, 0x3F19999A, 0x3F866666,
406 0x3F800000, 0x00000000, 0x00000000 }
407 },
408 { .name = "Male2Female",
409 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
410 0x450AC000, 0x4017AE14, 0x3F6B851F,
411 0x3F800000, 0x00000000, 0x00000000 }
412 },
413 { .name = "ScrappyKid",
414 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
415 0x44FA0000, 0x40400000, 0x3F28F5C3,
416 0x3F800000, 0x00000000, 0x00000000 }
417 },
418 { .name = "Elderly",
419 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
420 0x44E10000, 0x3FB33333, 0x3FB9999A,
421 0x3F800000, 0x3E3A2E43, 0x00000000 }
422 },
423 { .name = "Orc",
424 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
425 0x45098000, 0x3F266666, 0x3FC00000,
426 0x3F800000, 0x00000000, 0x00000000 }
427 },
428 { .name = "Elf",
429 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
430 0x45193000, 0x3F8E147B, 0x3F75C28F,
431 0x3F800000, 0x00000000, 0x00000000 }
432 },
433 { .name = "Dwarf",
434 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
435 0x45007000, 0x3F451EB8, 0x3F7851EC,
436 0x3F800000, 0x00000000, 0x00000000 }
437 },
438 { .name = "AlienBrute",
439 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
440 0x451F6000, 0x3F266666, 0x3FA7D945,
441 0x3F800000, 0x3CF5C28F, 0x00000000 }
442 },
443 { .name = "Robot",
444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
445 0x44FA0000, 0x3FB2718B, 0x3F800000,
446 0xBC07010E, 0x00000000, 0x00000000 }
447 },
448 { .name = "Marine",
449 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
450 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
451 0x3F0A3D71, 0x00000000, 0x00000000 }
452 },
453 { .name = "Emo",
454 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
455 0x44FA0000, 0x3F800000, 0x3F800000,
456 0x3E4CCCCD, 0x00000000, 0x00000000 }
457 },
458 { .name = "DeepVoice",
459 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
460 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
461 0x3F800000, 0x00000000, 0x00000000 }
462 },
463 { .name = "Munchkin",
464 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
465 0x44FA0000, 0x3F800000, 0x3F1A043C,
466 0x3F800000, 0x00000000, 0x00000000 }
467 }
468};
469
95c6e9cb
IM		 470enum hda_cmd_vendor_io {
471 /* for DspIO node */
472 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
473 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
474
475 VENDOR_DSPIO_STATUS = 0xF01,
476 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
477 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
478 VENDOR_DSPIO_DSP_INIT = 0x703,
479 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
480 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
481
482 /* for ChipIO node */
483 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
484 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
485 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
486 VENDOR_CHIPIO_DATA_LOW = 0x300,
487 VENDOR_CHIPIO_DATA_HIGH = 0x400,
488
489 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
490 VENDOR_CHIPIO_STATUS = 0xF01,
491 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
492 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
493
4aa3bb0c
IM		 494 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
495 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
496
95c6e9cb 497 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 498 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 499
500 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
501 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
502 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
503 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
504 VENDOR_CHIPIO_FLAG_SET = 0x70F,
505 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 506 VENDOR_CHIPIO_PARAM_SET = 0x710,
507 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 508
509 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
510 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
511 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
512 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
513
4aa3bb0c
IM		 514 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
515 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
516 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
517 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
518
519 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
520 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
521 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
522 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
523 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
524 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
525
526 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 527};
528
529/*
530 * Control flag IDs
531 */
532enum control_flag_id {
533 /* Connection manager stream setup is bypassed/enabled */
534 CONTROL_FLAG_C_MGR = 0,
535 /* DSP DMA is bypassed/enabled */
536 CONTROL_FLAG_DMA = 1,
537 /* 8051 'idle' mode is disabled/enabled */
538 CONTROL_FLAG_IDLE_ENABLE = 2,
539 /* Tracker for the SPDIF-in path is bypassed/enabled */
540 CONTROL_FLAG_TRACKER = 3,
541 /* DigitalOut to Spdif2Out connection is disabled/enabled */
542 CONTROL_FLAG_SPDIF2OUT = 4,
543 /* Digital Microphone is disabled/enabled */
544 CONTROL_FLAG_DMIC = 5,
545 /* ADC_B rate is 48 kHz/96 kHz */
546 CONTROL_FLAG_ADC_B_96KHZ = 6,
547 /* ADC_C rate is 48 kHz/96 kHz */
548 CONTROL_FLAG_ADC_C_96KHZ = 7,
549 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
550 CONTROL_FLAG_DAC_96KHZ = 8,
551 /* DSP rate is 48 kHz/96 kHz */
552 CONTROL_FLAG_DSP_96KHZ = 9,
553 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
554 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
555 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
556 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
557 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
558 CONTROL_FLAG_DECODE_LOOP = 12,
559 /* De-emphasis filter on DAC-1 disabled/enabled */
560 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
561 /* De-emphasis filter on DAC-2 disabled/enabled */
562 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
563 /* De-emphasis filter on DAC-3 disabled/enabled */
564 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
565 /* High-pass filter on ADC_B disabled/enabled */
566 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
567 /* High-pass filter on ADC_C disabled/enabled */
568 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
569 /* Common mode on Port_A disabled/enabled */
570 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
571 /* Common mode on Port_D disabled/enabled */
572 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
573 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
574 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
575 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 576 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 577 /* ASI rate is 48kHz/96kHz */
578 CONTROL_FLAG_ASI_96KHZ = 22,
579 /* DAC power settings able to control attached ports no/yes */
580 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
581 /* Clock Stop OK reporting is disabled/enabled */
582 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
583 /* Number of control flags */
584 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
585};
586
587/*
588 * Control parameter IDs
589 */
4aa3bb0c 590enum control_param_id {
ef6b2ead
IM		 591 /* 0: None, 1: Mic1In*/
592 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 593 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
594 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 595 /* Port A output stage gain setting to use when 16 Ohm output
596 * impedance is selected*/
597 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
598 /* Port D output stage gain setting to use when 16 Ohm output
599 * impedance is selected*/
600 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 601
602 /* Stream Control */
603
604 /* Select stream with the given ID */
605 CONTROL_PARAM_STREAM_ID = 24,
606 /* Source connection point for the selected stream */
607 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
608 /* Destination connection point for the selected stream */
609 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
610 /* Number of audio channels in the selected stream */
611 CONTROL_PARAM_STREAMS_CHANNELS = 27,
612 /*Enable control for the selected stream */
613 CONTROL_PARAM_STREAM_CONTROL = 28,
614
615 /* Connection Point Control */
616
617 /* Select connection point with the given ID */
618 CONTROL_PARAM_CONN_POINT_ID = 29,
619 /* Connection point sample rate */
620 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
621
622 /* Node Control */
623
624 /* Select HDA node with the given ID */
625 CONTROL_PARAM_NODE_ID = 31
626};
627
628/*
629 * Dsp Io Status codes
630 */
631enum hda_vendor_status_dspio {
632 /* Success */
633 VENDOR_STATUS_DSPIO_OK = 0x00,
634 /* Busy, unable to accept new command, the host must retry */
635 VENDOR_STATUS_DSPIO_BUSY = 0x01,
636 /* SCP command queue is full */
637 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
638 /* SCP response queue is empty */
639 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
640};
641
642/*
643 * Chip Io Status codes
644 */
645enum hda_vendor_status_chipio {
646 /* Success */
647 VENDOR_STATUS_CHIPIO_OK = 0x00,
648 /* Busy, unable to accept new command, the host must retry */
649 VENDOR_STATUS_CHIPIO_BUSY = 0x01
650};
651
652/*
653 * CA0132 sample rate
654 */
655enum ca0132_sample_rate {
656 SR_6_000 = 0x00,
657 SR_8_000 = 0x01,
658 SR_9_600 = 0x02,
659 SR_11_025 = 0x03,
660 SR_16_000 = 0x04,
661 SR_22_050 = 0x05,
662 SR_24_000 = 0x06,
663 SR_32_000 = 0x07,
664 SR_44_100 = 0x08,
665 SR_48_000 = 0x09,
666 SR_88_200 = 0x0A,
667 SR_96_000 = 0x0B,
668 SR_144_000 = 0x0C,
669 SR_176_400 = 0x0D,
670 SR_192_000 = 0x0E,
671 SR_384_000 = 0x0F,
672
673 SR_COUNT = 0x10,
674
675 SR_RATE_UNKNOWN = 0x1F
676};
677
01ef7dbf
IM		 678enum dsp_download_state {
679 DSP_DOWNLOAD_FAILED = -1,
680 DSP_DOWNLOAD_INIT = 0,
681 DSP_DOWNLOADING = 1,
682 DSP_DOWNLOADED = 2
683};
684
01ef7dbf
IM		 685/* retrieve parameters from hda format */
686#define get_hdafmt_chs(fmt) (fmt & 0xf)
687#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
688#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
689#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
690
691/*
692 * CA0132 specific
693 */
694
695struct ca0132_spec {
a7e76271
IM		 696 struct snd_kcontrol_new *mixers[5];
697 unsigned int num_mixers;
5aaca44d
IM		 698 const struct hda_verb *base_init_verbs;
699 const struct hda_verb *base_exit_verbs;
700 const struct hda_verb *init_verbs[5];
701 unsigned int num_init_verbs; /* exclude base init verbs */
01ef7dbf 702 struct auto_pin_cfg autocfg;
5aaca44d
IM		 703
704 /* Nodes configurations */
01ef7dbf
IM		 705 struct hda_multi_out multiout;
706 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
707 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 708 unsigned int num_outputs;
01ef7dbf
IM		 709 hda_nid_t input_pins[AUTO_PIN_LAST];
710 hda_nid_t adcs[AUTO_PIN_LAST];
711 hda_nid_t dig_out;
712 hda_nid_t dig_in;
713 unsigned int num_inputs;
a7e76271
IM		 714 hda_nid_t shared_mic_nid;
715 hda_nid_t shared_out_nid;
5aaca44d 716 struct hda_pcm pcm_rec[5]; /* PCM information */
01ef7dbf
IM		 717
718 /* chip access */
719 struct mutex chipio_mutex; /* chip access mutex */
720 u32 curr_chip_addx;
721
722 /* DSP download related */
723 enum dsp_download_state dsp_state;
724 unsigned int dsp_stream_id;
725 unsigned int wait_scp;
726 unsigned int wait_scp_header;
727 unsigned int wait_num_data;
728 unsigned int scp_resp_header;
729 unsigned int scp_resp_data[4];
730 unsigned int scp_resp_count;
5aaca44d
IM		 731
732 /* mixer and effects related */
733 unsigned char dmic_ctl;
734 int cur_out_type;
735 int cur_mic_type;
736 long vnode_lvol[VNODES_COUNT];
737 long vnode_rvol[VNODES_COUNT];
738 long vnode_lswitch[VNODES_COUNT];
739 long vnode_rswitch[VNODES_COUNT];
740 long effects_switch[EFFECTS_COUNT];
741 long voicefx_val;
742 long cur_mic_boost;
44f0c978
IM		 743
744#ifdef ENABLE_TUNING_CONTROLS
745 long cur_ctl_vals[TUNING_CTLS_COUNT];
746#endif
01ef7dbf
IM		 747};
748
749/*
750 * CA0132 codec access
751 */
752unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
753 unsigned int verb, unsigned int parm, unsigned int *res)
754{
755 unsigned int response;
756 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
757 *res = response;
758
759 return ((response == -1) ? -1 : 0);
760}
761
762static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
763 unsigned short converter_format, unsigned int *res)
764{
765 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
766 converter_format & 0xffff, res);
767}
768
769static int codec_set_converter_stream_channel(struct hda_codec *codec,
770 hda_nid_t nid, unsigned char stream,
771 unsigned char channel, unsigned int *res)
772{
773 unsigned char converter_stream_channel = 0;
774
775 converter_stream_channel = (stream << 4) | (channel & 0x0f);
776 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
777 converter_stream_channel, res);
778}
779
780/* Chip access helper function */
781static int chipio_send(struct hda_codec *codec,
782 unsigned int reg,
783 unsigned int data)
784{
785 unsigned int res;
786 int retry = 50;
787
788 /* send bits of data specified by reg */
789 do {
790 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
791 reg, data);
792 if (res == VENDOR_STATUS_CHIPIO_OK)
793 return 0;
794 } while (--retry);
795 return -EIO;
796}
797
798/*
799 * Write chip address through the vendor widget -- NOT protected by the Mutex!
800 */
801static int chipio_write_address(struct hda_codec *codec,
802 unsigned int chip_addx)
803{
4861af80 804 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 805 int res;
806
4861af80
IM		 807 if (spec->curr_chip_addx == chip_addx)
808 return 0;
809
01ef7dbf
IM		 810 /* send low 16 bits of the address */
811 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
812 chip_addx & 0xffff);
813
814 if (res != -EIO) {
815 /* send high 16 bits of the address */
816 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
817 chip_addx >> 16);
818 }
819
4861af80 820 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
01ef7dbf 821
4861af80 822 return res;
01ef7dbf
IM		 823}
824
825/*
826 * Write data through the vendor widget -- NOT protected by the Mutex!
827 */
01ef7dbf
IM		 828static int chipio_write_data(struct hda_codec *codec, unsigned int data)
829{
5aaca44d 830 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 831 int res;
832
833 /* send low 16 bits of the data */
834 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
835
836 if (res != -EIO) {
837 /* send high 16 bits of the data */
838 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
839 data >> 16);
840 }
841
5aaca44d
IM		 842 /*If no error encountered, automatically increment the address
843 as per chip behaviour*/
844 spec->curr_chip_addx = (res != -EIO) ?
845 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 846 return res;
847}
848
d5c21b88
IM		 849/*
850 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
851 */
01ef7dbf
IM		 852static int chipio_write_data_multiple(struct hda_codec *codec,
853 const u32 *data,
854 unsigned int count)
855{
856 int status = 0;
857
858 if (data == NULL) {
859 snd_printdd(KERN_ERR "chipio_write_data null ptr");
860 return -EINVAL;
861 }
862
863 while ((count-- != 0) && (status == 0))
864 status = chipio_write_data(codec, *data++);
865
866 return status;
867}
868
869
870/*
871 * Read data through the vendor widget -- NOT protected by the Mutex!
872 */
873static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
874{
5aaca44d 875 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 876 int res;
877
878 /* post read */
879 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
880
881 if (res != -EIO) {
882 /* read status */
883 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
884 }
885
886 if (res != -EIO) {
887 /* read data */
888 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
889 VENDOR_CHIPIO_HIC_READ_DATA,
890 0);
891 }
892
5aaca44d
IM		 893 /*If no error encountered, automatically increment the address
894 as per chip behaviour*/
895 spec->curr_chip_addx = (res != -EIO) ?
896 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 897 return res;
898}
899
900/*
901 * Write given value to the given address through the chip I/O widget.
902 * protected by the Mutex
903 */
904static int chipio_write(struct hda_codec *codec,
905 unsigned int chip_addx, const unsigned int data)
906{
907 struct ca0132_spec *spec = codec->spec;
908 int err;
909
910 mutex_lock(&spec->chipio_mutex);
911
912 /* write the address, and if successful proceed to write data */
913 err = chipio_write_address(codec, chip_addx);
914 if (err < 0)
915 goto exit;
916
917 err = chipio_write_data(codec, data);
918 if (err < 0)
919 goto exit;
920
921exit:
922 mutex_unlock(&spec->chipio_mutex);
923 return err;
924}
925
d5c21b88
IM		 926/*
927 * Write multiple values to the given address through the chip I/O widget.
928 * protected by the Mutex
929 */
01ef7dbf
IM		 930static int chipio_write_multiple(struct hda_codec *codec,
931 u32 chip_addx,
932 const u32 *data,
933 unsigned int count)
934{
935 struct ca0132_spec *spec = codec->spec;
936 int status;
937
938 mutex_lock(&spec->chipio_mutex);
4861af80 939 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 940 if (status < 0)
941 goto error;
942
943 status = chipio_write_data_multiple(codec, data, count);
944error:
945 mutex_unlock(&spec->chipio_mutex);
946
947 return status;
948}
949
950/*
951 * Read the given address through the chip I/O widget
952 * protected by the Mutex
953 */
954static int chipio_read(struct hda_codec *codec,
955 unsigned int chip_addx, unsigned int *data)
956{
957 struct ca0132_spec *spec = codec->spec;
958 int err;
959
960 mutex_lock(&spec->chipio_mutex);
961
962 /* write the address, and if successful proceed to write data */
963 err = chipio_write_address(codec, chip_addx);
964 if (err < 0)
965 goto exit;
966
967 err = chipio_read_data(codec, data);
968 if (err < 0)
969 goto exit;
970
971exit:
972 mutex_unlock(&spec->chipio_mutex);
973 return err;
974}
975
d5c21b88
IM		 976/*
977 * Set chip control flags through the chip I/O widget.
978 */
01ef7dbf
IM		 979static void chipio_set_control_flag(struct hda_codec *codec,
980 enum control_flag_id flag_id,
981 bool flag_state)
982{
983 unsigned int val;
984 unsigned int flag_bit;
985
986 flag_bit = (flag_state ? 1 : 0);
987 val = (flag_bit << 7) | (flag_id);
988 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
989 VENDOR_CHIPIO_FLAG_SET, val);
990}
991
d5c21b88
IM		 992/*
993 * Set chip parameters through the chip I/O widget.
994 */
01ef7dbf
IM		 995static void chipio_set_control_param(struct hda_codec *codec,
996 enum control_param_id param_id, int param_val)
997{
998 struct ca0132_spec *spec = codec->spec;
999 int val;
1000
1001 if ((param_id < 32) && (param_val < 8)) {
1002 val = (param_val << 5) | (param_id);
1003 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1004 VENDOR_CHIPIO_PARAM_SET, val);
1005 } else {
1006 mutex_lock(&spec->chipio_mutex);
1007 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1008 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1009 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1010 param_id);
1011 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1012 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1013 param_val);
1014 }
1015 mutex_unlock(&spec->chipio_mutex);
1016 }
1017}
1018
d5c21b88
IM		 1019/*
1020 * Set sampling rate of the connection point.
1021 */
01ef7dbf
IM		 1022static void chipio_set_conn_rate(struct hda_codec *codec,
1023 int connid, enum ca0132_sample_rate rate)
1024{
1025 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1026 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1027 rate);
1028}
1029
d5c21b88
IM		 1030/*
1031 * Enable clocks.
1032 */
01ef7dbf
IM		 1033static void chipio_enable_clocks(struct hda_codec *codec)
1034{
1035 struct ca0132_spec *spec = codec->spec;
1036
1037 mutex_lock(&spec->chipio_mutex);
1038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1039 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1041 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1043 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1044 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1045 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1046 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1047 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1048 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1049 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1050 mutex_unlock(&spec->chipio_mutex);
1051}
1052
1053/*
1054 * CA0132 DSP IO stuffs
1055 */
1056static int dspio_send(struct hda_codec *codec, unsigned int reg,
1057 unsigned int data)
1058{
b645d796 1059 int res;
01ef7dbf
IM		 1060 int retry = 50;
1061
1062 /* send bits of data specified by reg to dsp */
1063 do {
1064 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1065 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1066 return res;
1067 } while (--retry);
1068
1069 return -EIO;
1070}
1071
d5c21b88
IM		 1072/*
1073 * Wait for DSP to be ready for commands
1074 */
01ef7dbf
IM		 1075static void dspio_write_wait(struct hda_codec *codec)
1076{
4861af80
IM		 1077 int status;
1078 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1079
01ef7dbf 1080 do {
4861af80
IM		 1081 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1082 VENDOR_DSPIO_STATUS, 0);
1083 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1084 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1085 break;
1086 msleep(1);
1087 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1088}
1089
d5c21b88
IM		 1090/*
1091 * Write SCP data to DSP
1092 */
01ef7dbf
IM		 1093static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1094{
1095 struct ca0132_spec *spec = codec->spec;
1096 int status;
1097
1098 dspio_write_wait(codec);
1099
1100 mutex_lock(&spec->chipio_mutex);
1101 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1102 scp_data & 0xffff);
1103 if (status < 0)
1104 goto error;
1105
1106 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1107 scp_data >> 16);
1108 if (status < 0)
1109 goto error;
1110
1111 /* OK, now check if the write itself has executed*/
1112 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1113 VENDOR_DSPIO_STATUS, 0);
1114error:
1115 mutex_unlock(&spec->chipio_mutex);
1116
1117 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1118 -EIO : 0;
1119}
1120
d5c21b88
IM		 1121/*
1122 * Write multiple SCP data to DSP
1123 */
01ef7dbf
IM		 1124static int dspio_write_multiple(struct hda_codec *codec,
1125 unsigned int *buffer, unsigned int size)
1126{
1127 int status = 0;
1128 unsigned int count;
1129
1130 if ((buffer == NULL))
1131 return -EINVAL;
1132
1133 count = 0;
1134 while (count < size) {
1135 status = dspio_write(codec, *buffer++);
1136 if (status != 0)
1137 break;
1138 count++;
1139 }
1140
1141 return status;
1142}
1143
a73d511c
IM		 1144static int dspio_read(struct hda_codec *codec, unsigned int *data)
1145{
1146 int status;
1147
1148 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1149 if (status == -EIO)
1150 return status;
1151
1152 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1153 if (status == -EIO ||
1154 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1155 return -EIO;
1156
1157 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1158 VENDOR_DSPIO_SCP_READ_DATA, 0);
1159
1160 return 0;
1161}
1162
1163static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1164 unsigned int *buf_size, unsigned int size_count)
1165{
1166 int status = 0;
1167 unsigned int size = *buf_size;
1168 unsigned int count;
1169 unsigned int skip_count;
1170 unsigned int dummy;
1171
1172 if ((buffer == NULL))
1173 return -1;
1174
1175 count = 0;
1176 while (count < size && count < size_count) {
1177 status = dspio_read(codec, buffer++);
1178 if (status != 0)
1179 break;
1180 count++;
1181 }
1182
1183 skip_count = count;
1184 if (status == 0) {
1185 while (skip_count < size) {
1186 status = dspio_read(codec, &dummy);
1187 if (status != 0)
1188 break;
1189 skip_count++;
1190 }
1191 }
1192 *buf_size = count;
1193
1194 return status;
1195}
1196
d5c21b88
IM		 1197/*
1198 * Construct the SCP header using corresponding fields
1199 */
01ef7dbf
IM		 1200static inline unsigned int
1201make_scp_header(unsigned int target_id, unsigned int source_id,
1202 unsigned int get_flag, unsigned int req,
1203 unsigned int device_flag, unsigned int resp_flag,
1204 unsigned int error_flag, unsigned int data_size)
1205{
1206 unsigned int header = 0;
1207
1208 header = (data_size & 0x1f) << 27;
1209 header |= (error_flag & 0x01) << 26;
1210 header |= (resp_flag & 0x01) << 25;
1211 header |= (device_flag & 0x01) << 24;
1212 header |= (req & 0x7f) << 17;
1213 header |= (get_flag & 0x01) << 16;
1214 header |= (source_id & 0xff) << 8;
1215 header |= target_id & 0xff;
1216
1217 return header;
1218}
1219
d5c21b88
IM		 1220/*
1221 * Extract corresponding fields from SCP header
1222 */
01ef7dbf
IM		 1223static inline void
1224extract_scp_header(unsigned int header,
1225 unsigned int *target_id, unsigned int *source_id,
1226 unsigned int *get_flag, unsigned int *req,
1227 unsigned int *device_flag, unsigned int *resp_flag,
1228 unsigned int *error_flag, unsigned int *data_size)
1229{
1230 if (data_size)
1231 *data_size = (header >> 27) & 0x1f;
1232 if (error_flag)
1233 *error_flag = (header >> 26) & 0x01;
1234 if (resp_flag)
1235 *resp_flag = (header >> 25) & 0x01;
1236 if (device_flag)
1237 *device_flag = (header >> 24) & 0x01;
1238 if (req)
1239 *req = (header >> 17) & 0x7f;
1240 if (get_flag)
1241 *get_flag = (header >> 16) & 0x01;
1242 if (source_id)
1243 *source_id = (header >> 8) & 0xff;
1244 if (target_id)
1245 *target_id = header & 0xff;
1246}
1247
1248#define SCP_MAX_DATA_WORDS (16)
1249
1250/* Structure to contain any SCP message */
1251struct scp_msg {
1252 unsigned int hdr;
1253 unsigned int data[SCP_MAX_DATA_WORDS];
1254};
1255
a73d511c
IM		 1256static void dspio_clear_response_queue(struct hda_codec *codec)
1257{
1258 unsigned int dummy = 0;
1259 int status = -1;
1260
1261 /* clear all from the response queue */
1262 do {
1263 status = dspio_read(codec, &dummy);
1264 } while (status == 0);
1265}
1266
1267static int dspio_get_response_data(struct hda_codec *codec)
1268{
1269 struct ca0132_spec *spec = codec->spec;
1270 unsigned int data = 0;
1271 unsigned int count;
1272
1273 if (dspio_read(codec, &data) < 0)
1274 return -EIO;
1275
1276 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1277 spec->scp_resp_header = data;
1278 spec->scp_resp_count = data >> 27;
1279 count = spec->wait_num_data;
1280 dspio_read_multiple(codec, spec->scp_resp_data,
1281 &spec->scp_resp_count, count);
1282 return 0;
1283 }
1284
1285 return -EIO;
1286}
1287
d5c21b88
IM		 1288/*
1289 * Send SCP message to DSP
1290 */
01ef7dbf
IM		 1291static int dspio_send_scp_message(struct hda_codec *codec,
1292 unsigned char *send_buf,
1293 unsigned int send_buf_size,
1294 unsigned char *return_buf,
1295 unsigned int return_buf_size,
1296 unsigned int *bytes_returned)
1297{
1298 struct ca0132_spec *spec = codec->spec;
1299 int retry;
1300 int status = -1;
1301 unsigned int scp_send_size = 0;
1302 unsigned int total_size;
1303 bool waiting_for_resp = false;
1304 unsigned int header;
1305 struct scp_msg *ret_msg;
1306 unsigned int resp_src_id, resp_target_id;
1307 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1308
1309 if (bytes_returned)
1310 *bytes_returned = 0;
1311
1312 /* get scp header from buffer */
1313 header = *((unsigned int *)send_buf);
1314 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1315 &device_flag, NULL, NULL, &data_size);
1316 scp_send_size = data_size + 1;
1317 total_size = (scp_send_size * 4);
1318
1319 if (send_buf_size < total_size)
1320 return -EINVAL;
1321
1322 if (get_flag || device_flag) {
1323 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1324 return -EINVAL;
1325
1326 spec->wait_scp_header = *((unsigned int *)send_buf);
1327
1328 /* swap source id with target id */
1329 resp_target_id = src_id;
1330 resp_src_id = target_id;
1331 spec->wait_scp_header &= 0xffff0000;
1332 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1333 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1334 spec->wait_scp = 1;
1335 waiting_for_resp = true;
1336 }
1337
1338 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1339 scp_send_size);
1340 if (status < 0) {
1341 spec->wait_scp = 0;
1342 return status;
1343 }
1344
1345 if (waiting_for_resp) {
1346 memset(return_buf, 0, return_buf_size);
1347 retry = 50;
1348 do {
1349 msleep(20);
1350 } while (spec->wait_scp && (--retry != 0));
1351 waiting_for_resp = false;
1352 if (retry != 0) {
1353 ret_msg = (struct scp_msg *)return_buf;
1354 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1355 memcpy(&ret_msg->data, spec->scp_resp_data,
1356 spec->wait_num_data);
1357 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1358 status = 0;
1359 } else {
1360 status = -EIO;
1361 }
1362 spec->wait_scp = 0;
1363 }
1364
1365 return status;
1366}
1367
d5c21b88
IM		 1368/**
1369 * Prepare and send the SCP message to DSP
1370 * @codec: the HDA codec
1371 * @mod_id: ID of the DSP module to send the command
1372 * @req: ID of request to send to the DSP module
1373 * @dir: SET or GET
1374 * @data: pointer to the data to send with the request, request specific
1375 * @len: length of the data, in bytes
1376 * @reply: point to the buffer to hold data returned for a reply
1377 * @reply_len: length of the reply buffer returned from GET
1378 *
1379 * Returns zero or a negative error code.
1380 */
01ef7dbf
IM		 1381static int dspio_scp(struct hda_codec *codec,
1382 int mod_id, int req, int dir, void *data, unsigned int len,
1383 void *reply, unsigned int *reply_len)
1384{
1385 int status = 0;
1386 struct scp_msg scp_send, scp_reply;
1387 unsigned int ret_bytes, send_size, ret_size;
1388 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1389 unsigned int reply_data_size;
1390
1391 memset(&scp_send, 0, sizeof(scp_send));
1392 memset(&scp_reply, 0, sizeof(scp_reply));
1393
1394 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1395 return -EINVAL;
1396
1397 if (dir == SCP_GET && reply == NULL) {
1398 snd_printdd(KERN_ERR "dspio_scp get but has no buffer");
1399 return -EINVAL;
1400 }
1401
1402 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1403 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms");
1404 return -EINVAL;
1405 }
1406
1407 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1408 0, 0, 0, len/sizeof(unsigned int));
1409 if (data != NULL && len > 0) {
1410 len = min((unsigned int)(sizeof(scp_send.data)), len);
1411 memcpy(scp_send.data, data, len);
1412 }
1413
1414 ret_bytes = 0;
1415 send_size = sizeof(unsigned int) + len;
1416 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1417 send_size, (unsigned char *)&scp_reply,
1418 sizeof(scp_reply), &ret_bytes);
1419
1420 if (status < 0) {
1421 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed");
1422 return status;
1423 }
1424
1425 /* extract send and reply headers members */
1426 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1427 NULL, NULL, NULL, NULL, NULL);
1428 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1429 &reply_resp_flag, &reply_error_flag,
1430 &reply_data_size);
1431
1432 if (!send_get_flag)
1433 return 0;
1434
1435 if (reply_resp_flag && !reply_error_flag) {
1436 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1437 / sizeof(unsigned int);
1438
1439 if (*reply_len < ret_size*sizeof(unsigned int)) {
1440 snd_printdd(KERN_ERR "reply too long for buf");
1441 return -EINVAL;
1442 } else if (ret_size != reply_data_size) {
1443 snd_printdd(KERN_ERR "RetLen and HdrLen .NE.");
1444 return -EINVAL;
1445 } else {
1446 *reply_len = ret_size*sizeof(unsigned int);
1447 memcpy(reply, scp_reply.data, *reply_len);
1448 }
1449 } else {
1450 snd_printdd(KERN_ERR "reply ill-formed or errflag set");
1451 return -EIO;
1452 }
1453
1454 return status;
1455}
1456
5aaca44d
IM		 1457/*
1458 * Set DSP parameters
1459 */
1460static int dspio_set_param(struct hda_codec *codec, int mod_id,
1461 int req, void *data, unsigned int len)
1462{
1463 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1464}
1465
1466static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1467 int req, unsigned int data)
1468{
1469 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1470}
1471
d5c21b88
IM		 1472/*
1473 * Allocate a DSP DMA channel via an SCP message
1474 */
01ef7dbf
IM		 1475static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1476{
1477 int status = 0;
1478 unsigned int size = sizeof(dma_chan);
1479
1480 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin");
1481 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1482 SCP_GET, NULL, 0, dma_chan, &size);
1483
1484 if (status < 0) {
1485 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed");
1486 return status;
1487 }
1488
1489 if ((*dma_chan + 1) == 0) {
1490 snd_printdd(KERN_INFO "no free dma channels to allocate");
1491 return -EBUSY;
1492 }
1493
1494 snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1495 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete");
1496
1497 return status;
1498}
1499
d5c21b88
IM		 1500/*
1501 * Free a DSP DMA via an SCP message
1502 */
01ef7dbf
IM		 1503static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1504{
1505 int status = 0;
1506 unsigned int dummy = 0;
1507
1508 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin");
1509 snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan);
1510
1511 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1512 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1513
1514 if (status < 0) {
1515 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed");
1516 return status;
1517 }
1518
1519 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete");
1520
1521 return status;
1522}
1523
1524/*
d5c21b88 1525 * (Re)start the DSP
01ef7dbf
IM		 1526 */
1527static int dsp_set_run_state(struct hda_codec *codec)
1528{
1529 unsigned int dbg_ctrl_reg;
1530 unsigned int halt_state;
1531 int err;
1532
1533 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1534 if (err < 0)
1535 return err;
1536
1537 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1538 DSP_DBGCNTL_STATE_LOBIT;
1539
1540 if (halt_state != 0) {
1541 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1542 DSP_DBGCNTL_SS_MASK);
1543 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1544 dbg_ctrl_reg);
1545 if (err < 0)
1546 return err;
1547
1548 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1549 DSP_DBGCNTL_EXEC_MASK;
1550 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1551 dbg_ctrl_reg);
1552 if (err < 0)
1553 return err;
1554 }
1555
1556 return 0;
1557}
1558
d5c21b88
IM		 1559/*
1560 * Reset the DSP
1561 */
01ef7dbf
IM		 1562static int dsp_reset(struct hda_codec *codec)
1563{
1564 unsigned int res;
1565 int retry = 20;
1566
1567 snd_printdd("dsp_reset\n");
1568 do {
1569 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1570 retry--;
1571 } while (res == -EIO && retry);
1572
1573 if (!retry) {
1574 snd_printdd("dsp_reset timeout\n");
1575 return -EIO;
1576 }
1577
1578 return 0;
1579}
1580
d5c21b88
IM		 1581/*
1582 * Convert chip address to DSP address
1583 */
01ef7dbf
IM		 1584static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1585 bool *code, bool *yram)
1586{
1587 *code = *yram = false;
1588
1589 if (UC_RANGE(chip_addx, 1)) {
1590 *code = true;
1591 return UC_OFF(chip_addx);
1592 } else if (X_RANGE_ALL(chip_addx, 1)) {
1593 return X_OFF(chip_addx);
1594 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1595 *yram = true;
1596 return Y_OFF(chip_addx);
1597 }
1598
1599 return (unsigned int)INVALID_CHIP_ADDRESS;
1600}
1601
d5c21b88
IM		 1602/*
1603 * Check if the DSP DMA is active
1604 */
01ef7dbf
IM		 1605static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1606{
1607 unsigned int dma_chnlstart_reg;
1608
1609 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1610
1611 return ((dma_chnlstart_reg & (1 <<
1612 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1613}
1614
1615static int dsp_dma_setup_common(struct hda_codec *codec,
1616 unsigned int chip_addx,
1617 unsigned int dma_chan,
1618 unsigned int port_map_mask,
1619 bool ovly)
1620{
1621 int status = 0;
1622 unsigned int chnl_prop;
1623 unsigned int dsp_addx;
1624 unsigned int active;
1625 bool code, yram;
1626
1627 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------");
1628
1629 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1630 snd_printdd(KERN_ERR "dma chan num invalid");
1631 return -EINVAL;
1632 }
1633
1634 if (dsp_is_dma_active(codec, dma_chan)) {
1635 snd_printdd(KERN_ERR "dma already active");
1636 return -EBUSY;
1637 }
1638
1639 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1640
1641 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1642 snd_printdd(KERN_ERR "invalid chip addr");
1643 return -ENXIO;
1644 }
1645
1646 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1647 active = 0;
1648
1649 snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm");
1650
1651 if (ovly) {
1652 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1653 &chnl_prop);
1654
1655 if (status < 0) {
1656 snd_printdd(KERN_ERR "read CHNLPROP Reg fail");
1657 return status;
1658 }
1659 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP");
1660 }
1661
1662 if (!code)
1663 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1664 else
1665 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1666
1667 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1668
1669 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1670 if (status < 0) {
1671 snd_printdd(KERN_ERR "write CHNLPROP Reg fail");
1672 return status;
1673 }
1674 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP");
1675
1676 if (ovly) {
1677 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1678 &active);
1679
1680 if (status < 0) {
1681 snd_printdd(KERN_ERR "read ACTIVE Reg fail");
1682 return status;
1683 }
1684 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE");
1685 }
1686
1687 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1688 DSPDMAC_ACTIVE_AAR_MASK;
1689
1690 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1691 if (status < 0) {
1692 snd_printdd(KERN_ERR "write ACTIVE Reg fail");
1693 return status;
1694 }
1695
1696 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE");
1697
1698 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1699 port_map_mask);
1700 if (status < 0) {
1701 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail");
1702 return status;
1703 }
1704 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL");
1705
1706 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1707 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1708 if (status < 0) {
1709 snd_printdd(KERN_ERR "write IRQCNT Reg fail");
1710 return status;
1711 }
1712 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT");
1713
1714 snd_printdd(
1715 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1716 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1717 chip_addx, dsp_addx, dma_chan,
1718 port_map_mask, chnl_prop, active);
1719
1720 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------");
1721
1722 return 0;
1723}
1724
d5c21b88
IM		 1725/*
1726 * Setup the DSP DMA per-transfer-specific registers
1727 */
01ef7dbf
IM		 1728static int dsp_dma_setup(struct hda_codec *codec,
1729 unsigned int chip_addx,
1730 unsigned int count,
1731 unsigned int dma_chan)
1732{
1733 int status = 0;
1734 bool code, yram;
1735 unsigned int dsp_addx;
1736 unsigned int addr_field;
1737 unsigned int incr_field;
1738 unsigned int base_cnt;
1739 unsigned int cur_cnt;
1740 unsigned int dma_cfg = 0;
1741 unsigned int adr_ofs = 0;
1742 unsigned int xfr_cnt = 0;
1743 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1744 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1745
1746 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------");
1747
1748 if (count > max_dma_count) {
1749 snd_printdd(KERN_ERR "count too big");
1750 return -EINVAL;
1751 }
1752
1753 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1754 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1755 snd_printdd(KERN_ERR "invalid chip addr");
1756 return -ENXIO;
1757 }
1758
1759 snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm");
1760
1761 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1762 incr_field = 0;
1763
1764 if (!code) {
1765 addr_field <<= 1;
1766 if (yram)
1767 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1768
1769 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1770 }
1771
1772 dma_cfg = addr_field + incr_field;
1773 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1774 dma_cfg);
1775 if (status < 0) {
1776 snd_printdd(KERN_ERR "write DMACFG Reg fail");
1777 return status;
1778 }
1779 snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG");
1780
1781 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1782 (code ? 0 : 1));
1783
1784 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1785 adr_ofs);
1786 if (status < 0) {
1787 snd_printdd(KERN_ERR "write DSPADROFS Reg fail");
1788 return status;
1789 }
1790 snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS");
1791
1792 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1793
1794 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1795
1796 xfr_cnt = base_cnt | cur_cnt;
1797
1798 status = chipio_write(codec,
1799 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1800 if (status < 0) {
1801 snd_printdd(KERN_ERR "write XFRCNT Reg fail");
1802 return status;
1803 }
1804 snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT");
1805
1806 snd_printdd(
1807 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1808 "ADROFS=0x%x, XFRCNT=0x%x\n",
1809 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1810
1811 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------");
1812
1813 return 0;
1814}
1815
d5c21b88
IM		 1816/*
1817 * Start the DSP DMA
1818 */
01ef7dbf
IM		 1819static int dsp_dma_start(struct hda_codec *codec,
1820 unsigned int dma_chan, bool ovly)
1821{
1822 unsigned int reg = 0;
1823 int status = 0;
1824
1825 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------");
1826
1827 if (ovly) {
1828 status = chipio_read(codec,
1829 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1830
1831 if (status < 0) {
1832 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1833 return status;
1834 }
1835 snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART");
1836
1837 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1838 DSPDMAC_CHNLSTART_DIS_MASK);
1839 }
1840
1841 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1842 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1843 if (status < 0) {
1844 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1845 return status;
1846 }
1847 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------");
1848
1849 return status;
1850}
1851
d5c21b88
IM		 1852/*
1853 * Stop the DSP DMA
1854 */
01ef7dbf
IM		 1855static int dsp_dma_stop(struct hda_codec *codec,
1856 unsigned int dma_chan, bool ovly)
1857{
1858 unsigned int reg = 0;
1859 int status = 0;
1860
1861 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------");
1862
1863 if (ovly) {
1864 status = chipio_read(codec,
1865 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1866
1867 if (status < 0) {
1868 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1869 return status;
1870 }
1871 snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART");
1872 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1873 DSPDMAC_CHNLSTART_DIS_MASK);
1874 }
1875
1876 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1877 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1878 if (status < 0) {
1879 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1880 return status;
1881 }
1882 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------");
1883
1884 return status;
1885}
1886
d5c21b88
IM		 1887/**
1888 * Allocate router ports
1889 *
1890 * @codec: the HDA codec
1891 * @num_chans: number of channels in the stream
1892 * @ports_per_channel: number of ports per channel
1893 * @start_device: start device
1894 * @port_map: pointer to the port list to hold the allocated ports
1895 *
1896 * Returns zero or a negative error code.
1897 */
01ef7dbf
IM		 1898static int dsp_allocate_router_ports(struct hda_codec *codec,
1899 unsigned int num_chans,
1900 unsigned int ports_per_channel,
1901 unsigned int start_device,
1902 unsigned int *port_map)
1903{
1904 int status = 0;
1905 int res;
1906 u8 val;
1907
1908 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1909 if (status < 0)
1910 return status;
1911
1912 val = start_device << 6;
1913 val |= (ports_per_channel - 1) << 4;
1914 val |= num_chans - 1;
1915
1916 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1917 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1918 val);
1919
1920 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1921 VENDOR_CHIPIO_PORT_ALLOC_SET,
1922 MEM_CONNID_DSP);
1923
1924 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1925 if (status < 0)
1926 return status;
1927
1928 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1929 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1930
1931 *port_map = res;
1932
1933 return (res < 0) ? res : 0;
1934}
1935
d5c21b88
IM		 1936/*
1937 * Free router ports
1938 */
01ef7dbf
IM		 1939static int dsp_free_router_ports(struct hda_codec *codec)
1940{
1941 int status = 0;
1942
1943 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1944 if (status < 0)
1945 return status;
1946
1947 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1948 VENDOR_CHIPIO_PORT_FREE_SET,
1949 MEM_CONNID_DSP);
1950
1951 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1952
1953 return status;
1954}
1955
d5c21b88
IM		 1956/*
1957 * Allocate DSP ports for the download stream
1958 */
01ef7dbf
IM		 1959static int dsp_allocate_ports(struct hda_codec *codec,
1960 unsigned int num_chans,
1961 unsigned int rate_multi, unsigned int *port_map)
1962{
1963 int status;
1964
1965 snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin");
1966
1967 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1968 snd_printdd(KERN_ERR "bad rate multiple");
1969 return -EINVAL;
1970 }
1971
1972 status = dsp_allocate_router_ports(codec, num_chans,
1973 rate_multi, 0, port_map);
1974
1975 snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete");
1976
1977 return status;
1978}
1979
01ef7dbf
IM		 1980static int dsp_allocate_ports_format(struct hda_codec *codec,
1981 const unsigned short fmt,
1982 unsigned int *port_map)
1983{
1984 int status;
1985 unsigned int num_chans;
1986
1987 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1988 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1989 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
1990
1991 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1992 snd_printdd(KERN_ERR "bad rate multiple");
1993 return -EINVAL;
1994 }
1995
1996 num_chans = get_hdafmt_chs(fmt) + 1;
1997
1998 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
1999
2000 return status;
2001}
2002
d5c21b88
IM		 2003/*
2004 * free DSP ports
2005 */
2006static int dsp_free_ports(struct hda_codec *codec)
2007{
2008 int status;
2009
2010 snd_printdd(KERN_INFO " dsp_free_ports() -- begin");
2011
2012 status = dsp_free_router_ports(codec);
2013 if (status < 0) {
2014 snd_printdd(KERN_ERR "free router ports fail");
2015 return status;
2016 }
2017 snd_printdd(KERN_INFO " dsp_free_ports() -- complete");
2018
2019 return status;
2020}
2021
01ef7dbf
IM		 2022/*
2023 * HDA DMA engine stuffs for DSP code download
2024 */
2025struct dma_engine {
2026 struct hda_codec *codec;
2027 unsigned short m_converter_format;
2028 struct snd_dma_buffer *dmab;
2029 unsigned int buf_size;
2030};
2031
2032
2033enum dma_state {
2034 DMA_STATE_STOP = 0,
2035 DMA_STATE_RUN = 1
2036};
2037
2038static int dma_convert_to_hda_format(
e97249dd
IM		 2039 unsigned int sample_rate,
2040 unsigned short channels,
01ef7dbf
IM		 2041 unsigned short *hda_format)
2042{
2043 unsigned int format_val;
2044
2045 format_val = snd_hda_calc_stream_format(
e97249dd
IM		 2046 sample_rate,
2047 channels,
01ef7dbf 2048 SNDRV_PCM_FORMAT_S32_LE,
e97249dd 2049 32, 0);
01ef7dbf
IM		 2050
2051 if (hda_format)
2052 *hda_format = (unsigned short)format_val;
2053
2054 return 0;
2055}
2056
d5c21b88
IM		 2057/*
2058 * Reset DMA for DSP download
2059 */
01ef7dbf
IM		 2060static int dma_reset(struct dma_engine *dma)
2061{
2062 struct hda_codec *codec = dma->codec;
2063 struct ca0132_spec *spec = codec->spec;
2064 int status;
2065
2066 if (dma->dmab)
2067 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2068
2069 status = snd_hda_codec_load_dsp_prepare(codec,
2070 dma->m_converter_format,
2071 dma->buf_size,
2072 dma->dmab);
2073 if (status < 0)
2074 return status;
2075 spec->dsp_stream_id = status;
2076 return 0;
2077}
2078
2079static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2080{
01ef7dbf
IM		 2081 bool cmd;
2082
2083 snd_printdd("dma_set_state state=%d\n", state);
2084
2085 switch (state) {
2086 case DMA_STATE_STOP:
2087 cmd = false;
2088 break;
2089 case DMA_STATE_RUN:
2090 cmd = true;
2091 break;
2092 default:
c41999a2
DH		 2093 return 0;
2094 }
01ef7dbf
IM		 2095
2096 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2097 return 0;
95c6e9cb
IM		 2098}
2099
01ef7dbf
IM		 2100static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2101{
2102 return dma->dmab->bytes;
2103}
95c6e9cb 2104
01ef7dbf
IM		 2105static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2106{
2107 return dma->dmab->area;
2108}
95c6e9cb 2109
01ef7dbf
IM		 2110static int dma_xfer(struct dma_engine *dma,
2111 const unsigned int *data,
2112 unsigned int count)
2113{
2114 memcpy(dma->dmab->area, data, count);
2115 return 0;
2116}
95c6e9cb 2117
01ef7dbf
IM		 2118static void dma_get_converter_format(
2119 struct dma_engine *dma,
2120 unsigned short *format)
2121{
2122 if (format)
2123 *format = dma->m_converter_format;
2124}
95c6e9cb 2125
01ef7dbf 2126static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2127{
01ef7dbf 2128 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2129
01ef7dbf 2130 return spec->dsp_stream_id;
95c6e9cb
IM		 2131}
2132
01ef7dbf
IM		 2133struct dsp_image_seg {
2134 u32 magic;
2135 u32 chip_addr;
2136 u32 count;
2137 u32 data[0];
2138};
2139
2140static const u32 g_magic_value = 0x4c46584d;
2141static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2142
2143static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2144{
01ef7dbf
IM		 2145 return p->magic == g_magic_value;
2146}
95c6e9cb 2147
01ef7dbf
IM		 2148static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2149{
2150 return g_chip_addr_magic_value == p->chip_addr;
2151}
95c6e9cb 2152
01ef7dbf
IM		 2153static bool is_last(const struct dsp_image_seg *p)
2154{
2155 return p->count == 0;
2156}
95c6e9cb 2157
01ef7dbf
IM		 2158static size_t dsp_sizeof(const struct dsp_image_seg *p)
2159{
2160 return sizeof(*p) + p->count*sizeof(u32);
2161}
2162
2163static const struct dsp_image_seg *get_next_seg_ptr(
2164 const struct dsp_image_seg *p)
2165{
2166 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2167}
2168
2169/*
01ef7dbf 2170 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2171 */
8ae3124b 2172#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2173
d5c21b88
IM		 2174/*
2175 * Program a list of address/data pairs via the ChipIO widget.
2176 * The segment data is in the format of successive pairs of words.
2177 * These are repeated as indicated by the segment's count field.
2178 */
01ef7dbf
IM		 2179static int dspxfr_hci_write(struct hda_codec *codec,
2180 const struct dsp_image_seg *fls)
95c6e9cb 2181{
01ef7dbf
IM		 2182 int status;
2183 const u32 *data;
2184 unsigned int count;
95c6e9cb 2185
01ef7dbf
IM		 2186 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2187 snd_printdd(KERN_ERR "hci_write invalid params");
2188 return -EINVAL;
95c6e9cb
IM		 2189 }
2190
01ef7dbf
IM		 2191 count = fls->count;
2192 data = (u32 *)(fls->data);
2193 while (count >= 2) {
2194 status = chipio_write(codec, data[0], data[1]);
2195 if (status < 0) {
2196 snd_printdd(KERN_ERR "hci_write chipio failed");
2197 return status;
2198 }
2199 count -= 2;
2200 data += 2;
2201 }
2202 return 0;
95c6e9cb
IM		 2203}
2204
d5c21b88
IM		 2205/**
2206 * Write a block of data into DSP code or data RAM using pre-allocated
2207 * DMA engine.
2208 *
2209 * @codec: the HDA codec
2210 * @fls: pointer to a fast load image
2211 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2212 * no relocation
2213 * @dma_engine: pointer to DMA engine to be used for DSP download
2214 * @dma_chan: The number of DMA channels used for DSP download
2215 * @port_map_mask: port mapping
2216 * @ovly: TRUE if overlay format is required
2217 *
2218 * Returns zero or a negative error code.
2219 */
01ef7dbf
IM		 2220static int dspxfr_one_seg(struct hda_codec *codec,
2221 const struct dsp_image_seg *fls,
2222 unsigned int reloc,
2223 struct dma_engine *dma_engine,
2224 unsigned int dma_chan,
2225 unsigned int port_map_mask,
2226 bool ovly)
95c6e9cb 2227{
406261ce 2228 int status = 0;
01ef7dbf
IM		 2229 bool comm_dma_setup_done = false;
2230 const unsigned int *data;
2231 unsigned int chip_addx;
2232 unsigned int words_to_write;
2233 unsigned int buffer_size_words;
2234 unsigned char *buffer_addx;
2235 unsigned short hda_format;
2236 unsigned int sample_rate_div;
2237 unsigned int sample_rate_mul;
2238 unsigned int num_chans;
2239 unsigned int hda_frame_size_words;
2240 unsigned int remainder_words;
2241 const u32 *data_remainder;
2242 u32 chip_addx_remainder;
2243 unsigned int run_size_words;
2244 const struct dsp_image_seg *hci_write = NULL;
2245 int retry;
2246
2247 if (fls == NULL)
2248 return -EINVAL;
2249 if (is_hci_prog_list_seg(fls)) {
2250 hci_write = fls;
2251 fls = get_next_seg_ptr(fls);
2252 }
95c6e9cb 2253
01ef7dbf
IM		 2254 if (hci_write && (!fls || is_last(fls))) {
2255 snd_printdd("hci_write\n");
2256 return dspxfr_hci_write(codec, hci_write);
2257 }
95c6e9cb 2258
01ef7dbf
IM		 2259 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2260 snd_printdd("Invalid Params\n");
2261 return -EINVAL;
95c6e9cb
IM		 2262 }
2263
01ef7dbf
IM		 2264 data = fls->data;
2265 chip_addx = fls->chip_addr,
2266 words_to_write = fls->count;
2267
2268 if (!words_to_write)
2269 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2270 if (reloc)
2271 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2272
2273 if (!UC_RANGE(chip_addx, words_to_write) &&
2274 !X_RANGE_ALL(chip_addx, words_to_write) &&
2275 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2276 snd_printdd("Invalid chip_addx Params\n");
2277 return -EINVAL;
95c6e9cb
IM		 2278 }
2279
01ef7dbf
IM		 2280 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2281 sizeof(u32);
2282
2283 buffer_addx = dma_get_buffer_addr(dma_engine);
2284
2285 if (buffer_addx == NULL) {
2286 snd_printdd(KERN_ERR "dma_engine buffer NULL\n");
2287 return -EINVAL;
2288 }
2289
2290 dma_get_converter_format(dma_engine, &hda_format);
2291 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2292 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2293 num_chans = get_hdafmt_chs(hda_format) + 1;
2294
2295 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2296 (num_chans * sample_rate_mul / sample_rate_div));
2297
2298 buffer_size_words = min(buffer_size_words,
2299 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2300 65536 : 32768));
2301 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2302 snd_printdd(
2303 "chpadr=0x%08x frmsz=%u nchan=%u "
2304 "rate_mul=%u div=%u bufsz=%u\n",
2305 chip_addx, hda_frame_size_words, num_chans,
2306 sample_rate_mul, sample_rate_div, buffer_size_words);
2307
2308 if ((buffer_addx == NULL) || (hda_frame_size_words == 0) ||
2309 (buffer_size_words < hda_frame_size_words)) {
2310 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n");
2311 return -EINVAL;
2312 }
2313
2314 remainder_words = words_to_write % hda_frame_size_words;
2315 data_remainder = data;
2316 chip_addx_remainder = chip_addx;
2317
2318 data += remainder_words;
2319 chip_addx += remainder_words*sizeof(u32);
2320 words_to_write -= remainder_words;
2321
2322 while (words_to_write != 0) {
2323 run_size_words = min(buffer_size_words, words_to_write);
2324 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2325 words_to_write, run_size_words, remainder_words);
2326 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2327 if (!comm_dma_setup_done) {
2328 status = dsp_dma_stop(codec, dma_chan, ovly);
2329 if (status < 0)
425a7880 2330 return status;
01ef7dbf
IM		 2331 status = dsp_dma_setup_common(codec, chip_addx,
2332 dma_chan, port_map_mask, ovly);
2333 if (status < 0)
2334 return status;
2335 comm_dma_setup_done = true;
2336 }
2337
2338 status = dsp_dma_setup(codec, chip_addx,
2339 run_size_words, dma_chan);
2340 if (status < 0)
2341 return status;
2342 status = dsp_dma_start(codec, dma_chan, ovly);
2343 if (status < 0)
2344 return status;
2345 if (!dsp_is_dma_active(codec, dma_chan)) {
2346 snd_printdd(KERN_ERR "dspxfr:DMA did not start");
2347 return -EIO;
2348 }
2349 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2350 if (status < 0)
2351 return status;
2352 if (remainder_words != 0) {
2353 status = chipio_write_multiple(codec,
2354 chip_addx_remainder,
2355 data_remainder,
2356 remainder_words);
2357 remainder_words = 0;
2358 }
2359 if (hci_write) {
2360 status = dspxfr_hci_write(codec, hci_write);
2361 hci_write = NULL;
2362 }
2363 retry = 5000;
2364 while (dsp_is_dma_active(codec, dma_chan)) {
2365 if (--retry <= 0)
2366 break;
2367 }
2368 snd_printdd(KERN_INFO "+++++ DMA complete");
2369 dma_set_state(dma_engine, DMA_STATE_STOP);
2370 dma_reset(dma_engine);
2371
2372 if (status < 0)
2373 return status;
2374
2375 data += run_size_words;
2376 chip_addx += run_size_words*sizeof(u32);
2377 words_to_write -= run_size_words;
2378 }
2379
2380 if (remainder_words != 0) {
2381 status = chipio_write_multiple(codec, chip_addx_remainder,
2382 data_remainder, remainder_words);
2383 }
2384
2385 return status;
95c6e9cb
IM		 2386}
2387
d5c21b88
IM		 2388/**
2389 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2390 *
2391 * @codec: the HDA codec
2392 * @fls_data: pointer to a fast load image
2393 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2394 * no relocation
e97249dd
IM		 2395 * @sample_rate: sampling rate of the stream used for DSP download
2396 * @number_channels: channels of the stream used for DSP download
d5c21b88
IM		 2397 * @ovly: TRUE if overlay format is required
2398 *
2399 * Returns zero or a negative error code.
2400 */
01ef7dbf
IM		 2401static int dspxfr_image(struct hda_codec *codec,
2402 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2403 unsigned int reloc,
2404 unsigned int sample_rate,
2405 unsigned short channels,
01ef7dbf 2406 bool ovly)
95c6e9cb
IM		 2407{
2408 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2409 int status;
2410 unsigned short hda_format = 0;
2411 unsigned int response;
2412 unsigned char stream_id = 0;
2413 struct dma_engine *dma_engine;
2414 unsigned int dma_chan;
2415 unsigned int port_map_mask;
2416
2417 if (fls_data == NULL)
2418 return -EINVAL;
2419
2420 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2421 if (!dma_engine)
2422 return -ENOMEM;
95c6e9cb 2423
01ef7dbf
IM		 2424 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2425 if (!dma_engine->dmab) {
549e8292
TI		 2426 kfree(dma_engine);
2427 return -ENOMEM;
01ef7dbf 2428 }
95c6e9cb 2429
01ef7dbf 2430 dma_engine->codec = codec;
e97249dd 2431 dma_convert_to_hda_format(sample_rate, channels, &hda_format);
01ef7dbf
IM		 2432 dma_engine->m_converter_format = hda_format;
2433 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2434 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2435
8ae3124b 2436 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2437
2438 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2439 hda_format, &response);
2440
2441 if (status < 0) {
2442 snd_printdd(KERN_ERR "set converter format fail");
2443 goto exit;
2444 }
2445
2446 status = snd_hda_codec_load_dsp_prepare(codec,
2447 dma_engine->m_converter_format,
2448 dma_engine->buf_size,
2449 dma_engine->dmab);
2450 if (status < 0)
95c6e9cb 2451 goto exit;
01ef7dbf
IM		 2452 spec->dsp_stream_id = status;
2453
2454 if (ovly) {
2455 status = dspio_alloc_dma_chan(codec, &dma_chan);
2456 if (status < 0) {
2457 snd_printdd(KERN_ERR "alloc dmachan fail");
8ae3124b 2458 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2459 goto exit;
2460 }
2461 }
95c6e9cb 2462
01ef7dbf
IM		 2463 port_map_mask = 0;
2464 status = dsp_allocate_ports_format(codec, hda_format,
2465 &port_map_mask);
2466 if (status < 0) {
2467 snd_printdd(KERN_ERR "alloc ports fail");
2468 goto exit;
2469 }
2470
2471 stream_id = dma_get_stream_id(dma_engine);
2472 status = codec_set_converter_stream_channel(codec,
2473 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2474 if (status < 0) {
2475 snd_printdd(KERN_ERR "set stream chan fail");
2476 goto exit;
2477 }
2478
2479 while ((fls_data != NULL) && !is_last(fls_data)) {
2480 if (!is_valid(fls_data)) {
2481 snd_printdd(KERN_ERR "FLS check fail");
2482 status = -EINVAL;
2483 goto exit;
2484 }
2485 status = dspxfr_one_seg(codec, fls_data, reloc,
2486 dma_engine, dma_chan,
2487 port_map_mask, ovly);
2488 if (status < 0)
2489 break;
2490
2491 if (is_hci_prog_list_seg(fls_data))
2492 fls_data = get_next_seg_ptr(fls_data);
2493
2494 if ((fls_data != NULL) && !is_last(fls_data))
2495 fls_data = get_next_seg_ptr(fls_data);
2496 }
2497
2498 if (port_map_mask != 0)
2499 status = dsp_free_ports(codec);
2500
2501 if (status < 0)
95c6e9cb
IM		 2502 goto exit;
2503
01ef7dbf
IM		 2504 status = codec_set_converter_stream_channel(codec,
2505 WIDGET_CHIP_CTRL, 0, 0, &response);
2506
95c6e9cb 2507exit:
01ef7dbf
IM		 2508 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2509 dspio_free_dma_chan(codec, dma_chan);
2510
2511 if (dma_engine->dmab)
2512 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2513 kfree(dma_engine->dmab);
2514 kfree(dma_engine);
2515
2516 return status;
95c6e9cb
IM		 2517}
2518
2519/*
01ef7dbf 2520 * CA0132 DSP download stuffs.
95c6e9cb 2521 */
01ef7dbf 2522static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2523{
01ef7dbf 2524 snd_printdd(KERN_INFO "---- dspload_post_setup ------");
95c6e9cb 2525
01ef7dbf
IM		 2526 /*set DSP speaker to 2.0 configuration*/
2527 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2528 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2529
01ef7dbf
IM		 2530 /*update write pointer*/
2531 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2532}
95c6e9cb 2533
d5c21b88
IM		 2534/**
2535 * Download DSP from a DSP Image Fast Load structure. This structure is a
2536 * linear, non-constant sized element array of structures, each of which
2537 * contain the count of the data to be loaded, the data itself, and the
2538 * corresponding starting chip address of the starting data location.
2539 *
2540 * @codec: the HDA codec
2541 * @fls: pointer to a fast load image
2542 * @ovly: TRUE if overlay format is required
2543 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2544 * no relocation
2545 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2546 * @router_chans: number of audio router channels to be allocated (0 means use
2547 * internal defaults; max is 32)
2548 *
2549 * Returns zero or a negative error code.
2550 */
01ef7dbf
IM		 2551static int dspload_image(struct hda_codec *codec,
2552 const struct dsp_image_seg *fls,
2553 bool ovly,
2554 unsigned int reloc,
2555 bool autostart,
2556 int router_chans)
2557{
2558 int status = 0;
e97249dd
IM		 2559 unsigned int sample_rate;
2560 unsigned short channels;
01ef7dbf
IM		 2561
2562 snd_printdd(KERN_INFO "---- dspload_image begin ------");
2563 if (router_chans == 0) {
2564 if (!ovly)
2565 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2566 else
2567 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2568 }
95c6e9cb 2569
e97249dd
IM		 2570 sample_rate = 48000;
2571 channels = (unsigned short)router_chans;
01ef7dbf 2572
e97249dd
IM		 2573 while (channels > 16) {
2574 sample_rate *= 2;
2575 channels /= 2;
01ef7dbf
IM		 2576 }
2577
01ef7dbf
IM		 2578 do {
2579 snd_printdd(KERN_INFO "Ready to program DMA");
2580 if (!ovly)
2581 status = dsp_reset(codec);
2582
2583 if (status < 0)
2584 break;
2585
2586 snd_printdd(KERN_INFO "dsp_reset() complete");
e97249dd
IM		 2587 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2588 ovly);
01ef7dbf
IM		 2589
2590 if (status < 0)
2591 break;
2592
2593 snd_printdd(KERN_INFO "dspxfr_image() complete");
2594 if (autostart && !ovly) {
2595 dspload_post_setup(codec);
2596 status = dsp_set_run_state(codec);
2597 }
2598
2599 snd_printdd(KERN_INFO "LOAD FINISHED");
2600 } while (0);
2601
2602 return status;
2603}
2604
2605static bool dspload_is_loaded(struct hda_codec *codec)
2606{
2607 unsigned int data = 0;
2608 int status = 0;
2609
2610 status = chipio_read(codec, 0x40004, &data);
2611 if ((status < 0) || (data != 1))
2612 return false;
2613
2614 return true;
2615}
2616
2617static bool dspload_wait_loaded(struct hda_codec *codec)
2618{
2619 int retry = 100;
2620
2621 do {
2622 msleep(20);
2623 if (dspload_is_loaded(codec)) {
2624 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2625 return true;
2626 }
2627 } while (--retry);
2628
2629 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2630 return false;
95c6e9cb
IM		 2631}
2632
2633/*
825315bc 2634 * PCM stuffs
95c6e9cb 2635 */
825315bc
IM		 2636static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
2637 u32 stream_tag,
2638 int channel_id, int format)
95c6e9cb 2639{
825315bc
IM		 2640 unsigned int oldval, newval;
2641
2642 if (!nid)
2643 return;
2644
2645 snd_printdd(
2646 "ca0132_setup_stream: NID=0x%x, stream=0x%x, "
2647 "channel=%d, format=0x%x\n",
2648 nid, stream_tag, channel_id, format);
2649
2650 /* update the format-id if changed */
2651 oldval = snd_hda_codec_read(codec, nid, 0,
2652 AC_VERB_GET_STREAM_FORMAT,
2653 0);
2654 if (oldval != format) {
2655 msleep(20);
2656 snd_hda_codec_write(codec, nid, 0,
2657 AC_VERB_SET_STREAM_FORMAT,
2658 format);
2659 }
2660
2661 oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2662 newval = (stream_tag << 4) | channel_id;
2663 if (oldval != newval) {
2664 snd_hda_codec_write(codec, nid, 0,
2665 AC_VERB_SET_CHANNEL_STREAMID,
2666 newval);
2667 }
2668}
2669
2670static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
2671{
2672 unsigned int val;
2673
2674 if (!nid)
2675 return;
2676
2677 snd_printdd(KERN_INFO "ca0132_cleanup_stream: NID=0x%x\n", nid);
2678
2679 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2680 if (!val)
2681 return;
2682
2683 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
2684 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
95c6e9cb
IM		 2685}
2686
825315bc
IM		 2687/*
2688 * PCM callbacks
2689 */
95c6e9cb
IM		 2690static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2691 struct hda_codec *codec,
2692 unsigned int stream_tag,
2693 unsigned int format,
2694 struct snd_pcm_substream *substream)
2695{
2696 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2697
2698 ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2699
2700 return 0;
95c6e9cb
IM		 2701}
2702
2703static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2704 struct hda_codec *codec,
2705 struct snd_pcm_substream *substream)
2706{
2707 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2708
2709 if (spec->dsp_state == DSP_DOWNLOADING)
2710 return 0;
2711
2712 /*If Playback effects are on, allow stream some time to flush
2713 *effects tail*/
2714 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2715 msleep(50);
2716
2717 ca0132_cleanup_stream(codec, spec->dacs[0]);
2718
2719 return 0;
95c6e9cb
IM		 2720}
2721
2722/*
2723 * Digital out
2724 */
27ebeb0b
TI		 2725static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2726 struct hda_codec *codec,
2727 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2728{
2729 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2730 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2731}
2732
27ebeb0b 2733static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2734 struct hda_codec *codec,
2735 unsigned int stream_tag,
2736 unsigned int format,
2737 struct snd_pcm_substream *substream)
2738{
2739 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2740 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2741 stream_tag, format, substream);
95c6e9cb
IM		 2742}
2743
27ebeb0b 2744static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2745 struct hda_codec *codec,
95c6e9cb
IM		 2746 struct snd_pcm_substream *substream)
2747{
2748 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2749 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2750}
2751
27ebeb0b
TI		 2752static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2753 struct hda_codec *codec,
2754 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2755{
2756 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2757 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2758}
2759
825315bc
IM		 2760/*
2761 * Analog capture
2762 */
2763static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2764 struct hda_codec *codec,
2765 unsigned int stream_tag,
2766 unsigned int format,
2767 struct snd_pcm_substream *substream)
2768{
2769 struct ca0132_spec *spec = codec->spec;
2770
2771 ca0132_setup_stream(codec, spec->adcs[substream->number],
2772 stream_tag, 0, format);
2773
2774 return 0;
2775}
2776
2777static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2778 struct hda_codec *codec,
2779 struct snd_pcm_substream *substream)
2780{
2781 struct ca0132_spec *spec = codec->spec;
2782
2783 if (spec->dsp_state == DSP_DOWNLOADING)
2784 return 0;
2785
2786 ca0132_cleanup_stream(codec, hinfo->nid);
2787 return 0;
2788}
2789
e90f29e4
IM		 2790/*
2791 * Controls stuffs.
2792 */
2793
2794/*
2795 * Mixer controls helpers.
2796 */
2797#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2798 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2799 .name = xname, \
2800 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2801 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2802 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2803 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2804 .info = ca0132_volume_info, \
2805 .get = ca0132_volume_get, \
2806 .put = ca0132_volume_put, \
2807 .tlv = { .c = ca0132_volume_tlv }, \
2808 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2809
2810#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2811 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2812 .name = xname, \
2813 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2814 .info = snd_hda_mixer_amp_switch_info, \
2815 .get = ca0132_switch_get, \
2816 .put = ca0132_switch_put, \
2817 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2818
2819/* stereo */
2820#define CA0132_CODEC_VOL(xname, nid, dir) \
2821 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2822#define CA0132_CODEC_MUTE(xname, nid, dir) \
2823 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2824
44f0c978
IM		 2825/* The followings are for tuning of products */
2826#ifdef ENABLE_TUNING_CONTROLS
2827
2828static unsigned int voice_focus_vals_lookup[] = {
28290x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
28300x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
28310x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
28320x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
28330x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
28340x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
28350x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
28360x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
28370x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
28380x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
28390x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
28400x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
28410x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
28420x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
28430x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
28440x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
28450x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
28460x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
28470x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
28480x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
28490x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
28500x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
28510x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
28520x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
28530x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
28540x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
28550x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2856};
2857
2858static unsigned int mic_svm_vals_lookup[] = {
28590x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
28600x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
28610x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
28620x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
28630x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
28640x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
28650x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
28660x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
28670x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
28680x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
28690x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
28700x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
28710x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
28720x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
28730x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
28740x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
28750x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2876};
2877
2878static unsigned int equalizer_vals_lookup[] = {
28790xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
28800xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
28810xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
28820xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
28830x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
28840x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
28850x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
28860x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
28870x41C00000
2888};
2889
2890static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2891 unsigned int *lookup, int idx)
2892{
2893 int i = 0;
2894
2895 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2896 if (nid == ca0132_tuning_ctls[i].nid)
2897 break;
2898
2899 snd_hda_power_up(codec);
2900 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2901 ca0132_tuning_ctls[i].req,
2902 &(lookup[idx]), sizeof(unsigned int));
2903 snd_hda_power_down(codec);
2904
2905 return 1;
2906}
2907
2908static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2909 struct snd_ctl_elem_value *ucontrol)
2910{
2911 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2912 struct ca0132_spec *spec = codec->spec;
2913 hda_nid_t nid = get_amp_nid(kcontrol);
2914 long *valp = ucontrol->value.integer.value;
2915 int idx = nid - TUNING_CTL_START_NID;
2916
2917 *valp = spec->cur_ctl_vals[idx];
2918 return 0;
2919}
2920
2921static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2922 struct snd_ctl_elem_info *uinfo)
2923{
2924 int chs = get_amp_channels(kcontrol);
2925 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2926 uinfo->count = chs == 3 ? 2 : 1;
2927 uinfo->value.integer.min = 20;
2928 uinfo->value.integer.max = 180;
2929 uinfo->value.integer.step = 1;
2930
2931 return 0;
2932}
2933
2934static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2935 struct snd_ctl_elem_value *ucontrol)
2936{
2937 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2938 struct ca0132_spec *spec = codec->spec;
2939 hda_nid_t nid = get_amp_nid(kcontrol);
2940 long *valp = ucontrol->value.integer.value;
2941 int idx;
2942
2943 idx = nid - TUNING_CTL_START_NID;
2944 /* any change? */
2945 if (spec->cur_ctl_vals[idx] == *valp)
2946 return 0;
2947
2948 spec->cur_ctl_vals[idx] = *valp;
2949
2950 idx = *valp - 20;
2951 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2952
2953 return 1;
2954}
2955
2956static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2957 struct snd_ctl_elem_info *uinfo)
2958{
2959 int chs = get_amp_channels(kcontrol);
2960 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2961 uinfo->count = chs == 3 ? 2 : 1;
2962 uinfo->value.integer.min = 0;
2963 uinfo->value.integer.max = 100;
2964 uinfo->value.integer.step = 1;
2965
2966 return 0;
2967}
2968
2969static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2970 struct snd_ctl_elem_value *ucontrol)
2971{
2972 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2973 struct ca0132_spec *spec = codec->spec;
2974 hda_nid_t nid = get_amp_nid(kcontrol);
2975 long *valp = ucontrol->value.integer.value;
2976 int idx;
2977
2978 idx = nid - TUNING_CTL_START_NID;
2979 /* any change? */
2980 if (spec->cur_ctl_vals[idx] == *valp)
2981 return 0;
2982
2983 spec->cur_ctl_vals[idx] = *valp;
2984
2985 idx = *valp;
2986 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
2987
2988 return 0;
2989}
2990
2991static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
2992 struct snd_ctl_elem_info *uinfo)
2993{
2994 int chs = get_amp_channels(kcontrol);
2995 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2996 uinfo->count = chs == 3 ? 2 : 1;
2997 uinfo->value.integer.min = 0;
2998 uinfo->value.integer.max = 48;
2999 uinfo->value.integer.step = 1;
3000
3001 return 0;
3002}
3003
3004static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3005 struct snd_ctl_elem_value *ucontrol)
3006{
3007 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3008 struct ca0132_spec *spec = codec->spec;
3009 hda_nid_t nid = get_amp_nid(kcontrol);
3010 long *valp = ucontrol->value.integer.value;
3011 int idx;
3012
3013 idx = nid - TUNING_CTL_START_NID;
3014 /* any change? */
3015 if (spec->cur_ctl_vals[idx] == *valp)
3016 return 0;
3017
3018 spec->cur_ctl_vals[idx] = *valp;
3019
3020 idx = *valp;
3021 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3022
3023 return 1;
3024}
3025
3026static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3027static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3028
3029static int add_tuning_control(struct hda_codec *codec,
3030 hda_nid_t pnid, hda_nid_t nid,
3031 const char *name, int dir)
3032{
3033 char namestr[44];
3034 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3035 struct snd_kcontrol_new knew =
3036 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3037
3038 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3039 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3040 knew.tlv.c = 0;
3041 knew.tlv.p = 0;
3042 switch (pnid) {
3043 case VOICE_FOCUS:
3044 knew.info = voice_focus_ctl_info;
3045 knew.get = tuning_ctl_get;
3046 knew.put = voice_focus_ctl_put;
3047 knew.tlv.p = voice_focus_db_scale;
3048 break;
3049 case MIC_SVM:
3050 knew.info = mic_svm_ctl_info;
3051 knew.get = tuning_ctl_get;
3052 knew.put = mic_svm_ctl_put;
3053 break;
3054 case EQUALIZER:
3055 knew.info = equalizer_ctl_info;
3056 knew.get = tuning_ctl_get;
3057 knew.put = equalizer_ctl_put;
3058 knew.tlv.p = eq_db_scale;
3059 break;
3060 default:
3061 return 0;
3062 }
3063 knew.private_value =
3064 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3065 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3066 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3067}
3068
3069static int add_tuning_ctls(struct hda_codec *codec)
3070{
3071 int i;
3072 int err;
3073
3074 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3075 err = add_tuning_control(codec,
3076 ca0132_tuning_ctls[i].parent_nid,
3077 ca0132_tuning_ctls[i].nid,
3078 ca0132_tuning_ctls[i].name,
3079 ca0132_tuning_ctls[i].direct);
3080 if (err < 0)
3081 return err;
3082 }
3083
3084 return 0;
3085}
3086
3087static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3088{
3089 struct ca0132_spec *spec = codec->spec;
3090 int i;
3091
3092 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3093 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3094 /* SVM level defaults to 0.74. */
3095 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3096
3097 /* EQ defaults to 0dB. */
3098 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3099 spec->cur_ctl_vals[i] = 24;
3100}
3101#endif /*ENABLE_TUNING_CONTROLS*/
3102
5aaca44d
IM		 3103/*
3104 * Select the active output.
3105 * If autodetect is enabled, output will be selected based on jack detection.
3106 * If jack inserted, headphone will be selected, else built-in speakers
3107 * If autodetect is disabled, output will be selected based on selection.
3108 */
3109static int ca0132_select_out(struct hda_codec *codec)
3110{
3111 struct ca0132_spec *spec = codec->spec;
3112 unsigned int pin_ctl;
3113 int jack_present;
3114 int auto_jack;
3115 unsigned int tmp;
3116 int err;
3117
3118 snd_printdd(KERN_INFO "ca0132_select_out\n");
3119
3120 snd_hda_power_up(codec);
3121
3122 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3123
3124 if (auto_jack)
3125 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3126 else
3127 jack_present =
3128 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3129
3130 if (jack_present)
3131 spec->cur_out_type = HEADPHONE_OUT;
3132 else
3133 spec->cur_out_type = SPEAKER_OUT;
3134
3135 if (spec->cur_out_type == SPEAKER_OUT) {
3136 snd_printdd(KERN_INFO "ca0132_select_out speaker\n");
3137 /*speaker out config*/
3138 tmp = FLOAT_ONE;
3139 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3140 if (err < 0)
3141 goto exit;
3142 /*enable speaker EQ*/
3143 tmp = FLOAT_ONE;
3144 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3145 if (err < 0)
3146 goto exit;
3147
3148 /* Setup EAPD */
3149 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3150 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3151 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3152 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3153 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3154 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3155 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3156 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3157
3158 /* disable headphone node */
3159 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3160 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3161 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3162 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3163 /* enable speaker node */
3164 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3165 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3166 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3167 pin_ctl | PIN_OUT);
5aaca44d
IM		 3168 } else {
3169 snd_printdd(KERN_INFO "ca0132_select_out hp\n");
3170 /*headphone out config*/
3171 tmp = FLOAT_ZERO;
3172 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3173 if (err < 0)
3174 goto exit;
3175 /*disable speaker EQ*/
3176 tmp = FLOAT_ZERO;
3177 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3178 if (err < 0)
3179 goto exit;
3180
3181 /* Setup EAPD */
3182 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3183 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3184 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3185 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3186 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3187 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3188 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3189 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3190
3191 /* disable speaker*/
3192 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3193 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3194 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3195 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3196 /* enable headphone*/
3197 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3198 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3199 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3200 pin_ctl | PIN_HP);
5aaca44d
IM		 3201 }
3202
3203exit:
3204 snd_hda_power_down(codec);
3205
3206 return err < 0 ? err : 0;
3207}
3208
3209static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3210static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3211static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3212
3213/*
3214 * Select the active VIP source
3215 */
3216static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3217{
3218 struct ca0132_spec *spec = codec->spec;
3219 unsigned int tmp;
3220
3221 if (!dspload_is_loaded(codec))
3222 return 0;
3223
3224 /* if CrystalVoice if off, vipsource should be 0 */
3225 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3226 (val == 0)) {
3227 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3228 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3229 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3230 if (spec->cur_mic_type == DIGITAL_MIC)
3231 tmp = FLOAT_TWO;
3232 else
3233 tmp = FLOAT_ONE;
3234 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3235 tmp = FLOAT_ZERO;
3236 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3237 } else {
3238 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3239 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3240 if (spec->cur_mic_type == DIGITAL_MIC)
3241 tmp = FLOAT_TWO;
3242 else
3243 tmp = FLOAT_ONE;
3244 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3245 tmp = FLOAT_ONE;
3246 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3247 msleep(20);
3248 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3249 }
3250
3251 return 1;
3252}
3253
3254/*
3255 * Select the active microphone.
3256 * If autodetect is enabled, mic will be selected based on jack detection.
3257 * If jack inserted, ext.mic will be selected, else built-in mic
3258 * If autodetect is disabled, mic will be selected based on selection.
3259 */
3260static int ca0132_select_mic(struct hda_codec *codec)
3261{
3262 struct ca0132_spec *spec = codec->spec;
3263 int jack_present;
3264 int auto_jack;
3265
3266 snd_printdd(KERN_INFO "ca0132_select_mic\n");
3267
3268 snd_hda_power_up(codec);
3269
3270 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3271
3272 if (auto_jack)
3273 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3274 else
3275 jack_present =
3276 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3277
3278 if (jack_present)
3279 spec->cur_mic_type = LINE_MIC_IN;
3280 else
3281 spec->cur_mic_type = DIGITAL_MIC;
3282
3283 if (spec->cur_mic_type == DIGITAL_MIC) {
3284 /* enable digital Mic */
3285 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3286 ca0132_set_dmic(codec, 1);
3287 ca0132_mic_boost_set(codec, 0);
3288 /* set voice focus */
3289 ca0132_effects_set(codec, VOICE_FOCUS,
3290 spec->effects_switch
3291 [VOICE_FOCUS - EFFECT_START_NID]);
3292 } else {
3293 /* disable digital Mic */
3294 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3295 ca0132_set_dmic(codec, 0);
3296 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3297 /* disable voice focus */
3298 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3299 }
3300
3301 snd_hda_power_down(codec);
3302
3303 return 0;
3304}
3305
a7e76271
IM		 3306/*
3307 * Check if VNODE settings take effect immediately.
3308 */
3309static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3310 hda_nid_t vnid,
3311 hda_nid_t *shared_nid)
3312{
3313 struct ca0132_spec *spec = codec->spec;
3314 hda_nid_t nid;
a7e76271
IM		 3315
3316 switch (vnid) {
3317 case VNID_SPK:
3318 nid = spec->shared_out_nid;
a7e76271
IM		 3319 break;
3320 case VNID_MIC:
3321 nid = spec->shared_mic_nid;
a7e76271
IM		 3322 break;
3323 default:
9a0869f4 3324 return false;
a7e76271
IM		 3325 }
3326
9a0869f4 3327 if (shared_nid)
a7e76271
IM		 3328 *shared_nid = nid;
3329
9a0869f4 3330 return true;
a7e76271
IM		 3331}
3332
3333/*
3334* The following functions are control change helpers.
3335* They return 0 if no changed. Return 1 if changed.
3336*/
3337static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3338{
3339 struct ca0132_spec *spec = codec->spec;
3340 unsigned int tmp;
3341
3342 /* based on CrystalVoice state to enable VoiceFX. */
3343 if (enable) {
3344 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3345 FLOAT_ONE : FLOAT_ZERO;
3346 } else {
3347 tmp = FLOAT_ZERO;
3348 }
3349
3350 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3351 ca0132_voicefx.reqs[0], tmp);
3352
3353 return 1;
3354}
3355
5aaca44d
IM		 3356/*
3357 * Set the effects parameters
3358 */
3359static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3360{
3361 struct ca0132_spec *spec = codec->spec;
3362 unsigned int on;
3363 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3364 int err = 0;
3365 int idx = nid - EFFECT_START_NID;
3366
3367 if ((idx < 0) || (idx >= num_fx))
3368 return 0; /* no changed */
3369
3370 /* for out effect, qualify with PE */
3371 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3372 /* if PE if off, turn off out effects. */
3373 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3374 val = 0;
3375 }
3376
3377 /* for in effect, qualify with CrystalVoice */
3378 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3379 /* if CrystalVoice if off, turn off in effects. */
3380 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3381 val = 0;
3382
3383 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3384 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3385 val = 0;
3386 }
3387
dea500c7 3388 snd_printdd(KERN_INFO "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 3389 nid, val);
3390
3391 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3392 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3393 ca0132_effects[idx].reqs[0], on);
3394
3395 if (err < 0)
3396 return 0; /* no changed */
3397
3398 return 1;
3399}
3400
a7e76271
IM		 3401/*
3402 * Turn on/off Playback Enhancements
3403 */
3404static int ca0132_pe_switch_set(struct hda_codec *codec)
3405{
3406 struct ca0132_spec *spec = codec->spec;
3407 hda_nid_t nid;
3408 int i, ret = 0;
3409
3410 snd_printdd(KERN_INFO "ca0132_pe_switch_set: val=%ld\n",
3411 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3412
3413 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3414 nid = OUT_EFFECT_START_NID;
3415 /* PE affects all out effects */
3416 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3417 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3418
3419 return ret;
3420}
3421
5aaca44d
IM		 3422/* Check if Mic1 is streaming, if so, stop streaming */
3423static int stop_mic1(struct hda_codec *codec)
3424{
3425 struct ca0132_spec *spec = codec->spec;
3426 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3427 AC_VERB_GET_CONV, 0);
3428 if (oldval != 0)
3429 snd_hda_codec_write(codec, spec->adcs[0], 0,
3430 AC_VERB_SET_CHANNEL_STREAMID,
3431 0);
3432 return oldval;
3433}
3434
3435/* Resume Mic1 streaming if it was stopped. */
3436static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3437{
3438 struct ca0132_spec *spec = codec->spec;
3439 /* Restore the previous stream and channel */
3440 if (oldval != 0)
3441 snd_hda_codec_write(codec, spec->adcs[0], 0,
3442 AC_VERB_SET_CHANNEL_STREAMID,
3443 oldval);
3444}
3445
3446/*
a7e76271 3447 * Turn on/off CrystalVoice
5aaca44d 3448 */
a7e76271
IM		 3449static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3450{
3451 struct ca0132_spec *spec = codec->spec;
3452 hda_nid_t nid;
3453 int i, ret = 0;
3454 unsigned int oldval;
3455
3456 snd_printdd(KERN_INFO "ca0132_cvoice_switch_set: val=%ld\n",
3457 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3458
3459 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3460 nid = IN_EFFECT_START_NID;
3461 /* CrystalVoice affects all in effects */
3462 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3463 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3464
3465 /* including VoiceFX */
3466 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3467
3468 /* set correct vipsource */
3469 oldval = stop_mic1(codec);
3470 ret |= ca0132_set_vipsource(codec, 1);
3471 resume_mic1(codec, oldval);
3472 return ret;
3473}
3474
5aaca44d
IM		 3475static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3476{
3477 struct ca0132_spec *spec = codec->spec;
3478 int ret = 0;
3479
3480 if (val) /* on */
3481 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3482 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3483 else /* off */
3484 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3485 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3486
3487 return ret;
3488}
3489
a7e76271
IM		 3490static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3491 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3492{
a7e76271
IM		 3493 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3494 hda_nid_t nid = get_amp_nid(kcontrol);
3495 hda_nid_t shared_nid = 0;
3496 bool effective;
3497 int ret = 0;
95c6e9cb 3498 struct ca0132_spec *spec = codec->spec;
a7e76271 3499 int auto_jack;
95c6e9cb 3500
a7e76271
IM		 3501 if (nid == VNID_HP_SEL) {
3502 auto_jack =
3503 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3504 if (!auto_jack)
3505 ca0132_select_out(codec);
3506 return 1;
3507 }
95c6e9cb 3508
a7e76271
IM		 3509 if (nid == VNID_AMIC1_SEL) {
3510 auto_jack =
3511 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3512 if (!auto_jack)
3513 ca0132_select_mic(codec);
3514 return 1;
3515 }
95c6e9cb 3516
a7e76271
IM		 3517 if (nid == VNID_HP_ASEL) {
3518 ca0132_select_out(codec);
3519 return 1;
3520 }
95c6e9cb 3521
a7e76271
IM		 3522 if (nid == VNID_AMIC1_ASEL) {
3523 ca0132_select_mic(codec);
3524 return 1;
95c6e9cb 3525 }
a7e76271
IM		 3526
3527 /* if effective conditions, then update hw immediately. */
3528 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3529 if (effective) {
3530 int dir = get_amp_direction(kcontrol);
3531 int ch = get_amp_channels(kcontrol);
3532 unsigned long pval;
3533
3534 mutex_lock(&codec->control_mutex);
3535 pval = kcontrol->private_value;
3536 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3537 0, dir);
3538 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3539 kcontrol->private_value = pval;
3540 mutex_unlock(&codec->control_mutex);
95c6e9cb 3541 }
95c6e9cb 3542
a7e76271 3543 return ret;
95c6e9cb 3544}
a7e76271 3545/* End of control change helpers. */
95c6e9cb 3546
a7e76271
IM		 3547static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3548 struct snd_ctl_elem_info *uinfo)
3549{
3550 unsigned int items = sizeof(ca0132_voicefx_presets)
3551 / sizeof(struct ct_voicefx_preset);
3552
3553 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3554 uinfo->count = 1;
3555 uinfo->value.enumerated.items = items;
3556 if (uinfo->value.enumerated.item >= items)
3557 uinfo->value.enumerated.item = items - 1;
3558 strcpy(uinfo->value.enumerated.name,
3559 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3560 return 0;
3561}
95c6e9cb 3562
a7e76271 3563static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3564 struct snd_ctl_elem_value *ucontrol)
3565{
3566 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3567 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3568
a7e76271 3569 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3570 return 0;
3571}
3572
a7e76271 3573static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3574 struct snd_ctl_elem_value *ucontrol)
3575{
3576 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3577 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3578 int i, err = 0;
3579 int sel = ucontrol->value.enumerated.item[0];
3580 unsigned int items = sizeof(ca0132_voicefx_presets)
3581 / sizeof(struct ct_voicefx_preset);
95c6e9cb 3582
a7e76271 3583 if (sel >= items)
95c6e9cb
IM		 3584 return 0;
3585
a7e76271
IM		 3586 snd_printdd(KERN_INFO "ca0132_voicefx_put: sel=%d, preset=%s\n",
3587 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3588
a7e76271
IM		 3589 /*
3590 * Idx 0 is default.
3591 * Default needs to qualify with CrystalVoice state.
3592 */
3593 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3594 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3595 ca0132_voicefx.reqs[i],
3596 ca0132_voicefx_presets[sel].vals[i]);
3597 if (err < 0)
3598 break;
3599 }
95c6e9cb 3600
a7e76271
IM		 3601 if (err >= 0) {
3602 spec->voicefx_val = sel;
3603 /* enable voice fx */
3604 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3605 }
95c6e9cb 3606
a7e76271 3607 return 1;
95c6e9cb
IM		 3608}
3609
a7e76271
IM		 3610static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3611 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3612{
3613 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3614 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3615 hda_nid_t nid = get_amp_nid(kcontrol);
3616 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3617 long *valp = ucontrol->value.integer.value;
3618
a7e76271
IM		 3619 /* vnode */
3620 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3621 if (ch & 1) {
3622 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3623 valp++;
3624 }
3625 if (ch & 2) {
3626 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3627 valp++;
3628 }
3629 return 0;
3630 }
3631
3632 /* effects, include PE and CrystalVoice */
3633 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3634 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3635 return 0;
3636 }
3637
3638 /* mic boost */
3639 if (nid == spec->input_pins[0]) {
3640 *valp = spec->cur_mic_boost;
3641 return 0;
3642 }
3643
95c6e9cb
IM		 3644 return 0;
3645}
3646
a7e76271
IM		 3647static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3648 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3649{
3650 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3651 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3652 hda_nid_t nid = get_amp_nid(kcontrol);
3653 int ch = get_amp_channels(kcontrol);
95c6e9cb 3654 long *valp = ucontrol->value.integer.value;
a7e76271 3655 int changed = 1;
95c6e9cb 3656
a7e76271
IM		 3657 snd_printdd(KERN_INFO "ca0132_switch_put: nid=0x%x, val=%ld\n",
3658 nid, *valp);
95c6e9cb
IM		 3659
3660 snd_hda_power_up(codec);
a7e76271
IM		 3661 /* vnode */
3662 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3663 if (ch & 1) {
3664 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3665 valp++;
3666 }
3667 if (ch & 2) {
3668 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3669 valp++;
3670 }
3671 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3672 goto exit;
3673 }
95c6e9cb 3674
a7e76271
IM		 3675 /* PE */
3676 if (nid == PLAY_ENHANCEMENT) {
3677 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3678 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3679 goto exit;
a7e76271 3680 }
95c6e9cb 3681
a7e76271
IM		 3682 /* CrystalVoice */
3683 if (nid == CRYSTAL_VOICE) {
3684 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3685 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3686 goto exit;
a7e76271 3687 }
95c6e9cb 3688
a7e76271
IM		 3689 /* out and in effects */
3690 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3691 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3692 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3693 changed = ca0132_effects_set(codec, nid, *valp);
3694 goto exit;
3695 }
3696
3697 /* mic boost */
3698 if (nid == spec->input_pins[0]) {
3699 spec->cur_mic_boost = *valp;
3700
3701 /* Mic boost does not apply to Digital Mic */
3702 if (spec->cur_mic_type != DIGITAL_MIC)
3703 changed = ca0132_mic_boost_set(codec, *valp);
3704 goto exit;
3705 }
95c6e9cb 3706
a7e76271 3707exit:
95c6e9cb 3708 snd_hda_power_down(codec);
a7e76271 3709 return changed;
95c6e9cb
IM		 3710}
3711
a7e76271
IM		 3712/*
3713 * Volume related
3714 */
3715static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3716 struct snd_ctl_elem_info *uinfo)
3717{
3718 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3719 struct ca0132_spec *spec = codec->spec;
3720 hda_nid_t nid = get_amp_nid(kcontrol);
3721 int ch = get_amp_channels(kcontrol);
3722 int dir = get_amp_direction(kcontrol);
3723 unsigned long pval;
3724 int err;
3725
3726 switch (nid) {
3727 case VNID_SPK:
3728 /* follow shared_out info */
3729 nid = spec->shared_out_nid;
3730 mutex_lock(&codec->control_mutex);
3731 pval = kcontrol->private_value;
3732 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3733 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3734 kcontrol->private_value = pval;
3735 mutex_unlock(&codec->control_mutex);
3736 break;
3737 case VNID_MIC:
3738 /* follow shared_mic info */
3739 nid = spec->shared_mic_nid;
3740 mutex_lock(&codec->control_mutex);
3741 pval = kcontrol->private_value;
3742 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3743 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3744 kcontrol->private_value = pval;
3745 mutex_unlock(&codec->control_mutex);
3746 break;
3747 default:
3748 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3749 }
3750 return err;
3751}
3752
3753static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3754 struct snd_ctl_elem_value *ucontrol)
3755{
3756 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3757 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3758 hda_nid_t nid = get_amp_nid(kcontrol);
3759 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3760 long *valp = ucontrol->value.integer.value;
3761
a7e76271
IM		 3762 /* store the left and right volume */
3763 if (ch & 1) {
3764 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3765 valp++;
3766 }
3767 if (ch & 2) {
3768 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3769 valp++;
3770 }
95c6e9cb
IM		 3771 return 0;
3772}
3773
a7e76271 3774static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3775 struct snd_ctl_elem_value *ucontrol)
3776{
3777 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3778 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3779 hda_nid_t nid = get_amp_nid(kcontrol);
3780 int ch = get_amp_channels(kcontrol);
95c6e9cb 3781 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3782 hda_nid_t shared_nid = 0;
3783 bool effective;
3784 int changed = 1;
3785
3786 /* store the left and right volume */
3787 if (ch & 1) {
3788 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3789 valp++;
3790 }
3791 if (ch & 2) {
3792 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3793 valp++;
3794 }
95c6e9cb 3795
a7e76271
IM		 3796 /* if effective conditions, then update hw immediately. */
3797 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3798 if (effective) {
3799 int dir = get_amp_direction(kcontrol);
3800 unsigned long pval;
3801
3802 snd_hda_power_up(codec);
3803 mutex_lock(&codec->control_mutex);
3804 pval = kcontrol->private_value;
3805 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3806 0, dir);
3807 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3808 kcontrol->private_value = pval;
3809 mutex_unlock(&codec->control_mutex);
3810 snd_hda_power_down(codec);
3811 }
95c6e9cb 3812
a7e76271 3813 return changed;
95c6e9cb
IM		 3814}
3815
a7e76271
IM		 3816static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3817 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3818{
a7e76271
IM		 3819 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3820 struct ca0132_spec *spec = codec->spec;
3821 hda_nid_t nid = get_amp_nid(kcontrol);
3822 int ch = get_amp_channels(kcontrol);
3823 int dir = get_amp_direction(kcontrol);
3824 unsigned long pval;
3825 int err;
3826
3827 switch (nid) {
3828 case VNID_SPK:
3829 /* follow shared_out tlv */
3830 nid = spec->shared_out_nid;
3831 mutex_lock(&codec->control_mutex);
3832 pval = kcontrol->private_value;
3833 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3834 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3835 kcontrol->private_value = pval;
3836 mutex_unlock(&codec->control_mutex);
3837 break;
3838 case VNID_MIC:
3839 /* follow shared_mic tlv */
3840 nid = spec->shared_mic_nid;
3841 mutex_lock(&codec->control_mutex);
3842 pval = kcontrol->private_value;
3843 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3844 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3845 kcontrol->private_value = pval;
3846 mutex_unlock(&codec->control_mutex);
3847 break;
3848 default:
3849 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3850 }
3851 return err;
95c6e9cb
IM		 3852}
3853
a7e76271
IM		 3854static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3855 const char *pfx, int dir)
95c6e9cb 3856{
a7e76271
IM		 3857 char namestr[44];
3858 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3859 struct snd_kcontrol_new knew =
a7e76271
IM		 3860 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3861 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3862 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3863}
3864
a7e76271 3865static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3866{
3867 struct snd_kcontrol_new knew =
a7e76271
IM		 3868 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3869 VOICEFX, 1, 0, HDA_INPUT);
3870 knew.info = ca0132_voicefx_info;
3871 knew.get = ca0132_voicefx_get;
3872 knew.put = ca0132_voicefx_put;
3873 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3874}
3875
a7e76271
IM		 3876/*
3877 * When changing Node IDs for Mixer Controls below, make sure to update
3878 * Node IDs in ca0132_config() as well.
3879 */
3880static struct snd_kcontrol_new ca0132_mixer[] = {
3881 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3882 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3883 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3884 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3885 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3886 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3887 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3888 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3889 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3890 0x12, 1, HDA_INPUT),
3891 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3892 VNID_HP_SEL, 1, HDA_OUTPUT),
3893 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3894 VNID_AMIC1_SEL, 1, HDA_INPUT),
3895 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3896 VNID_HP_ASEL, 1, HDA_OUTPUT),
3897 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3898 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3899 { } /* end */
3900};
3901
e90f29e4
IM		 3902static int ca0132_build_controls(struct hda_codec *codec)
3903{
3904 struct ca0132_spec *spec = codec->spec;
3905 int i, num_fx;
3906 int err = 0;
3907
3908 /* Add Mixer controls */
3909 for (i = 0; i < spec->num_mixers; i++) {
3910 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3911 if (err < 0)
3912 return err;
3913 }
3914
3915 /* Add in and out effects controls.
3916 * VoiceFX, PE and CrystalVoice are added separately.
3917 */
3918 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3919 for (i = 0; i < num_fx; i++) {
3920 err = add_fx_switch(codec, ca0132_effects[i].nid,
3921 ca0132_effects[i].name,
3922 ca0132_effects[i].direct);
3923 if (err < 0)
3924 return err;
3925 }
3926
3927 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3928 if (err < 0)
3929 return err;
3930
3931 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3932 if (err < 0)
3933 return err;
3934
3935 add_voicefx(codec);
3936
3937#ifdef ENABLE_TUNING_CONTROLS
3938 add_tuning_ctls(codec);
3939#endif
3940
3941 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3942 if (err < 0)
3943 return err;
3944
3945 if (spec->dig_out) {
3946 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3947 spec->dig_out);
3948 if (err < 0)
3949 return err;
3950 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
3951 if (err < 0)
3952 return err;
3953 /* spec->multiout.share_spdif = 1; */
3954 }
3955
3956 if (spec->dig_in) {
3957 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
3958 if (err < 0)
3959 return err;
3960 }
3961 return 0;
3962}
3963
a7e76271 3964/*
e90f29e4 3965 * PCM
a7e76271
IM		 3966 */
3967static struct hda_pcm_stream ca0132_pcm_analog_playback = {
3968 .substreams = 1,
3969 .channels_min = 2,
825315bc 3970 .channels_max = 6,
a7e76271 3971 .ops = {
a7e76271
IM		 3972 .prepare = ca0132_playback_pcm_prepare,
3973 .cleanup = ca0132_playback_pcm_cleanup
3974 },
3975};
3976
3977static struct hda_pcm_stream ca0132_pcm_analog_capture = {
3978 .substreams = 1,
3979 .channels_min = 2,
3980 .channels_max = 2,
825315bc
IM		 3981 .ops = {
3982 .prepare = ca0132_capture_pcm_prepare,
3983 .cleanup = ca0132_capture_pcm_cleanup
3984 },
a7e76271
IM		 3985};
3986
3987static struct hda_pcm_stream ca0132_pcm_digital_playback = {
3988 .substreams = 1,
3989 .channels_min = 2,
3990 .channels_max = 2,
3991 .ops = {
3992 .open = ca0132_dig_playback_pcm_open,
3993 .close = ca0132_dig_playback_pcm_close,
3994 .prepare = ca0132_dig_playback_pcm_prepare,
3995 .cleanup = ca0132_dig_playback_pcm_cleanup
3996 },
3997};
3998
3999static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4000 .substreams = 1,
4001 .channels_min = 2,
4002 .channels_max = 2,
4003};
4004
4005static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4006{
4007 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 4008 struct hda_pcm *info = spec->pcm_rec;
4009
4010 codec->pcm_info = info;
4011 codec->num_pcms = 0;
4012
4013 info->name = "CA0132 Analog";
4014 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4015 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4016 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4017 spec->multiout.max_channels;
4018 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4019 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271
IM		 4020 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4021 codec->num_pcms++;
4022
825315bc
IM		 4023 info++;
4024 info->name = "CA0132 Analog Mic-In2";
4025 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4026 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4027 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4028 codec->num_pcms++;
4029
4030 info++;
4031 info->name = "CA0132 What U Hear";
4032 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4033 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4034 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4035 codec->num_pcms++;
4036
a7e76271
IM		 4037 if (!spec->dig_out && !spec->dig_in)
4038 return 0;
4039
4040 info++;
4041 info->name = "CA0132 Digital";
4042 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4043 if (spec->dig_out) {
4044 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4045 ca0132_pcm_digital_playback;
4046 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4047 }
4048 if (spec->dig_in) {
4049 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4050 ca0132_pcm_digital_capture;
4051 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4052 }
4053 codec->num_pcms++;
95c6e9cb 4054
a7e76271 4055 return 0;
95c6e9cb
IM		 4056}
4057
441aa6a0
IM		 4058static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4059{
4060 if (pin) {
a0c041cb 4061 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 4062 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4063 snd_hda_codec_write(codec, pin, 0,
4064 AC_VERB_SET_AMP_GAIN_MUTE,
4065 AMP_OUT_UNMUTE);
4066 }
4067 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4068 snd_hda_codec_write(codec, dac, 0,
4069 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4070}
4071
4072static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4073{
4074 if (pin) {
a0c041cb 4075 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 4076 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4077 snd_hda_codec_write(codec, pin, 0,
4078 AC_VERB_SET_AMP_GAIN_MUTE,
4079 AMP_IN_UNMUTE(0));
4080 }
4081 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4082 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4083 AMP_IN_UNMUTE(0));
4084
4085 /* init to 0 dB and unmute. */
4086 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4087 HDA_AMP_VOLMASK, 0x5a);
4088 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4089 HDA_AMP_MUTE, 0);
4090 }
4091}
4092
a73d511c
IM		 4093static void ca0132_init_unsol(struct hda_codec *codec)
4094{
4095 snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP);
4096 snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1);
4097}
4098
5aaca44d
IM		 4099static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4100{
4101 unsigned int caps;
4102
4103 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4104 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4105 snd_hda_override_amp_caps(codec, nid, dir, caps);
4106}
4107
4108/*
4109 * Switch between Digital built-in mic and analog mic.
4110 */
4111static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4112{
4113 struct ca0132_spec *spec = codec->spec;
4114 unsigned int tmp;
4115 u8 val;
4116 unsigned int oldval;
4117
4118 snd_printdd(KERN_INFO "ca0132_set_dmic: enable=%d\n", enable);
4119
4120 oldval = stop_mic1(codec);
4121 ca0132_set_vipsource(codec, 0);
4122 if (enable) {
4123 /* set DMic input as 2-ch */
4124 tmp = FLOAT_TWO;
4125 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4126
4127 val = spec->dmic_ctl;
4128 val |= 0x80;
4129 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4130 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4131
4132 if (!(spec->dmic_ctl & 0x20))
4133 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4134 } else {
4135 /* set AMic input as mono */
4136 tmp = FLOAT_ONE;
4137 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4138
4139 val = spec->dmic_ctl;
4140 /* clear bit7 and bit5 to disable dmic */
4141 val &= 0x5f;
4142 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4143 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4144
4145 if (!(spec->dmic_ctl & 0x20))
4146 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4147 }
4148 ca0132_set_vipsource(codec, 1);
4149 resume_mic1(codec, oldval);
4150}
4151
4152/*
4153 * Initialization for Digital Mic.
4154 */
4155static void ca0132_init_dmic(struct hda_codec *codec)
4156{
4157 struct ca0132_spec *spec = codec->spec;
4158 u8 val;
4159
4160 /* Setup Digital Mic here, but don't enable.
4161 * Enable based on jack detect.
4162 */
4163
4164 /* MCLK uses MPIO1, set to enable.
4165 * Bit 2-0: MPIO select
4166 * Bit 3: set to disable
4167 * Bit 7-4: reserved
4168 */
4169 val = 0x01;
4170 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4171 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4172
4173 /* Data1 uses MPIO3. Data2 not use
4174 * Bit 2-0: Data1 MPIO select
4175 * Bit 3: set disable Data1
4176 * Bit 6-4: Data2 MPIO select
4177 * Bit 7: set disable Data2
4178 */
4179 val = 0x83;
4180 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4181 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4182
4183 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4184 * Bit 3-0: Channel mask
4185 * Bit 4: set for 48KHz, clear for 32KHz
4186 * Bit 5: mode
4187 * Bit 6: set to select Data2, clear for Data1
4188 * Bit 7: set to enable DMic, clear for AMic
4189 */
4190 val = 0x23;
4191 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4192 spec->dmic_ctl = val;
4193 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4194 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4195}
4196
4197/*
4198 * Initialization for Analog Mic 2
4199 */
4200static void ca0132_init_analog_mic2(struct hda_codec *codec)
4201{
4202 struct ca0132_spec *spec = codec->spec;
4203
4204 mutex_lock(&spec->chipio_mutex);
4205 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4206 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4207 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4208 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4209 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4210 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4211 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4212 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4213 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4214 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4215 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4216 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4217 mutex_unlock(&spec->chipio_mutex);
4218}
4219
4220static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4221{
4222 struct ca0132_spec *spec = codec->spec;
4223 int i;
4224 hda_nid_t nid;
4225
4226 snd_printdd(KERN_INFO "ca0132_refresh_widget_caps.\n");
4227 nid = codec->start_nid;
4228 for (i = 0; i < codec->num_nodes; i++, nid++)
4229 codec->wcaps[i] = snd_hda_param_read(codec, nid,
4230 AC_PAR_AUDIO_WIDGET_CAP);
4231
4232 for (i = 0; i < spec->multiout.num_dacs; i++)
4233 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4234
4235 for (i = 0; i < spec->num_outputs; i++)
4236 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4237
4238 for (i = 0; i < spec->num_inputs; i++) {
4239 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4240 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4241 }
4242}
4243
4244/*
4245 * Setup default parameters for DSP
4246 */
4247static void ca0132_setup_defaults(struct hda_codec *codec)
4248{
4249 unsigned int tmp;
4250 int num_fx;
4251 int idx, i;
4252
4253 if (!dspload_is_loaded(codec))
4254 return;
4255
4256 /* out, in effects + voicefx */
4257 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4258 for (idx = 0; idx < num_fx; idx++) {
4259 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4260 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4261 ca0132_effects[idx].reqs[i],
4262 ca0132_effects[idx].def_vals[i]);
4263 }
4264 }
4265
4266 /*remove DSP headroom*/
4267 tmp = FLOAT_ZERO;
4268 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4269
4270 /*set speaker EQ bypass attenuation*/
4271 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4272
4273 /* set AMic1 and AMic2 as mono mic */
4274 tmp = FLOAT_ONE;
4275 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4276 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4277
4278 /* set AMic1 as CrystalVoice input */
4279 tmp = FLOAT_ONE;
4280 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4281
4282 /* set WUH source */
4283 tmp = FLOAT_TWO;
4284 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4285}
4286
4287/*
4288 * Initialization of flags in chip
4289 */
4290static void ca0132_init_flags(struct hda_codec *codec)
4291{
4292 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4293 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4294 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4295 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4296 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4297 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4298}
4299
4300/*
4301 * Initialization of parameters in chip
4302 */
4303static void ca0132_init_params(struct hda_codec *codec)
4304{
4305 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4306 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4307}
95c6e9cb 4308
e90f29e4
IM		 4309static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4310{
4311 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4312 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4313 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4314 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4315 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4316 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4317
406261ce
IM		 4318 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4319 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 4320 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4321}
4322
4323static bool ca0132_download_dsp_images(struct hda_codec *codec)
4324{
4325 bool dsp_loaded = false;
4326 const struct dsp_image_seg *dsp_os_image;
15e4ba66 4327 const struct firmware *fw_entry;
e90f29e4 4328
15e4ba66 4329 if (request_firmware(&fw_entry, EFX_FILE, codec->bus->card->dev) != 0)
e90f29e4
IM		 4330 return false;
4331
15e4ba66 4332 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
e90f29e4
IM		 4333 dspload_image(codec, dsp_os_image, 0, 0, true, 0);
4334 dsp_loaded = dspload_wait_loaded(codec);
4335
15e4ba66
TI		 4336 release_firmware(fw_entry);
4337
4338
e90f29e4
IM		 4339 return dsp_loaded;
4340}
4341
4342static void ca0132_download_dsp(struct hda_codec *codec)
4343{
4344 struct ca0132_spec *spec = codec->spec;
4345
9a0869f4
TI		 4346#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4347 return; /* NOP */
4348#endif
e90f29e4
IM		 4349 spec->dsp_state = DSP_DOWNLOAD_INIT;
4350
4351 if (spec->dsp_state == DSP_DOWNLOAD_INIT) {
4352 chipio_enable_clocks(codec);
4353 spec->dsp_state = DSP_DOWNLOADING;
4354 if (!ca0132_download_dsp_images(codec))
4355 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4356 else
4357 spec->dsp_state = DSP_DOWNLOADED;
4358 }
4359
4360 if (spec->dsp_state == DSP_DOWNLOADED)
4361 ca0132_set_dsp_msr(codec, true);
4362}
4363
e90f29e4
IM		 4364static void ca0132_process_dsp_response(struct hda_codec *codec)
4365{
4366 struct ca0132_spec *spec = codec->spec;
4367
4368 snd_printdd(KERN_INFO "ca0132_process_dsp_response\n");
4369 if (spec->wait_scp) {
4370 if (dspio_get_response_data(codec) >= 0)
4371 spec->wait_scp = 0;
4372 }
4373
4374 dspio_clear_response_queue(codec);
4375}
4376
4377static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res)
4378{
4379 snd_printdd(KERN_INFO "ca0132_unsol_event: 0x%x\n", res);
4380
4381
4382 if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) {
4383 ca0132_process_dsp_response(codec);
4384 } else {
4385 res = snd_hda_jack_get_action(codec,
4386 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f);
4387
4388 snd_printdd(KERN_INFO "snd_hda_jack_get_action: 0x%x\n", res);
4389
4390 switch (res) {
4391 case UNSOL_TAG_HP:
4392 ca0132_select_out(codec);
4393 snd_hda_jack_report_sync(codec);
4394 break;
4395 case UNSOL_TAG_AMIC1:
4396 ca0132_select_mic(codec);
4397 snd_hda_jack_report_sync(codec);
4398 break;
4399 default:
4400 break;
4401 }
4402 }
4403}
4404
5aaca44d
IM		 4405/*
4406 * Verbs tables.
4407 */
4408
4409/* Sends before DSP download. */
4410static struct hda_verb ca0132_base_init_verbs[] = {
4411 /*enable ct extension*/
4412 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4413 /*enable DSP node unsol, needed for DSP download*/
4414 {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
4415 {}
4416};
4417
4418/* Send at exit. */
4419static struct hda_verb ca0132_base_exit_verbs[] = {
4420 /*set afg to D3*/
4421 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4422 /*disable ct extension*/
4423 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4424 {}
4425};
4426
4427/* Other verbs tables. Sends after DSP download. */
4428static struct hda_verb ca0132_init_verbs0[] = {
4429 /* chip init verbs */
4430 {0x15, 0x70D, 0xF0},
4431 {0x15, 0x70E, 0xFE},
4432 {0x15, 0x707, 0x75},
4433 {0x15, 0x707, 0xD3},
4434 {0x15, 0x707, 0x09},
4435 {0x15, 0x707, 0x53},
4436 {0x15, 0x707, 0xD4},
4437 {0x15, 0x707, 0xEF},
4438 {0x15, 0x707, 0x75},
4439 {0x15, 0x707, 0xD3},
4440 {0x15, 0x707, 0x09},
4441 {0x15, 0x707, 0x02},
4442 {0x15, 0x707, 0x37},
4443 {0x15, 0x707, 0x78},
4444 {0x15, 0x53C, 0xCE},
4445 {0x15, 0x575, 0xC9},
4446 {0x15, 0x53D, 0xCE},
4447 {0x15, 0x5B7, 0xC9},
4448 {0x15, 0x70D, 0xE8},
4449 {0x15, 0x70E, 0xFE},
4450 {0x15, 0x707, 0x02},
4451 {0x15, 0x707, 0x68},
4452 {0x15, 0x707, 0x62},
4453 {0x15, 0x53A, 0xCE},
4454 {0x15, 0x546, 0xC9},
4455 {0x15, 0x53B, 0xCE},
4456 {0x15, 0x5E8, 0xC9},
4457 {0x15, 0x717, 0x0D},
4458 {0x15, 0x718, 0x20},
4459 {}
4460};
4461
4462static struct hda_verb ca0132_init_verbs1[] = {
4463 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4464 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4465 /* config EAPD */
4466 {0x0b, 0x78D, 0x00},
4467 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4468 /*{0x10, 0x78D, 0x02},*/
4469 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4470 {}
4471};
4472
95c6e9cb
IM		 4473static void ca0132_init_chip(struct hda_codec *codec)
4474{
4475 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4476 int num_fx;
4477 int i;
4478 unsigned int on;
95c6e9cb
IM		 4479
4480 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 4481
4482 spec->cur_out_type = SPEAKER_OUT;
4483 spec->cur_mic_type = DIGITAL_MIC;
4484 spec->cur_mic_boost = 0;
4485
4486 for (i = 0; i < VNODES_COUNT; i++) {
4487 spec->vnode_lvol[i] = 0x5a;
4488 spec->vnode_rvol[i] = 0x5a;
4489 spec->vnode_lswitch[i] = 0;
4490 spec->vnode_rswitch[i] = 0;
4491 }
4492
4493 /*
4494 * Default states for effects are in ca0132_effects[].
4495 */
4496 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4497 for (i = 0; i < num_fx; i++) {
4498 on = (unsigned int)ca0132_effects[i].reqs[0];
4499 spec->effects_switch[i] = on ? 1 : 0;
4500 }
4501
4502 spec->voicefx_val = 0;
4503 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4504 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4505
44f0c978
IM		 4506#ifdef ENABLE_TUNING_CONTROLS
4507 ca0132_init_tuning_defaults(codec);
4508#endif
95c6e9cb
IM		 4509}
4510
4511static void ca0132_exit_chip(struct hda_codec *codec)
4512{
4513 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 4514
4515 if (dspload_is_loaded(codec))
4516 dsp_reset(codec);
95c6e9cb
IM		 4517}
4518
4519static int ca0132_init(struct hda_codec *codec)
4520{
4521 struct ca0132_spec *spec = codec->spec;
4522 struct auto_pin_cfg *cfg = &spec->autocfg;
4523 int i;
4524
5aaca44d
IM		 4525 spec->dsp_state = DSP_DOWNLOAD_INIT;
4526 spec->curr_chip_addx = (unsigned int)INVALID_CHIP_ADDRESS;
4527
4528 snd_hda_power_up(codec);
4529
4530 ca0132_init_params(codec);
4531 ca0132_init_flags(codec);
4532 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf 4533 ca0132_download_dsp(codec);
5aaca44d
IM		 4534 ca0132_refresh_widget_caps(codec);
4535 ca0132_setup_defaults(codec);
4536 ca0132_init_analog_mic2(codec);
4537 ca0132_init_dmic(codec);
4538
4539 for (i = 0; i < spec->num_outputs; i++)
4540 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4541
95c6e9cb
IM		 4542 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4543
4544 for (i = 0; i < spec->num_inputs; i++)
4545 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4546
4547 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4548
5aaca44d
IM		 4549 for (i = 0; i < spec->num_init_verbs; i++)
4550 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4551
a73d511c
IM		 4552 ca0132_init_unsol(codec);
4553
5aaca44d
IM		 4554 ca0132_select_out(codec);
4555 ca0132_select_mic(codec);
4556
a73d511c
IM		 4557 snd_hda_jack_report_sync(codec);
4558
5aaca44d 4559 snd_hda_power_down(codec);
95c6e9cb
IM		 4560
4561 return 0;
4562}
4563
95c6e9cb
IM		 4564static void ca0132_free(struct hda_codec *codec)
4565{
5aaca44d
IM		 4566 struct ca0132_spec *spec = codec->spec;
4567
4568 snd_hda_power_up(codec);
4569 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4570 ca0132_exit_chip(codec);
5aaca44d 4571 snd_hda_power_down(codec);
95c6e9cb
IM		 4572 kfree(codec->spec);
4573}
4574
4575static struct hda_codec_ops ca0132_patch_ops = {
4576 .build_controls = ca0132_build_controls,
4577 .build_pcms = ca0132_build_pcms,
4578 .init = ca0132_init,
4579 .free = ca0132_free,
a73d511c 4580 .unsol_event = ca0132_unsol_event,
95c6e9cb
IM		 4581};
4582
441aa6a0
IM		 4583static void ca0132_config(struct hda_codec *codec)
4584{
4585 struct ca0132_spec *spec = codec->spec;
4586 struct auto_pin_cfg *cfg = &spec->autocfg;
4587
4588 spec->dacs[0] = 0x2;
4589 spec->dacs[1] = 0x3;
4590 spec->dacs[2] = 0x4;
4591
4592 spec->multiout.dac_nids = spec->dacs;
4593 spec->multiout.num_dacs = 3;
4594 spec->multiout.max_channels = 2;
4595
4596 spec->num_outputs = 2;
4597 spec->out_pins[0] = 0x0b; /* speaker out */
4598 spec->out_pins[1] = 0x10; /* headphone out */
4599 spec->shared_out_nid = 0x2;
4600
4601 spec->num_inputs = 3;
4602 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4603 spec->adcs[1] = 0x8; /* analog mic2 */
4604 spec->adcs[2] = 0xa; /* what u hear */
4605 spec->shared_mic_nid = 0x7;
4606
4607 spec->input_pins[0] = 0x12;
4608 spec->input_pins[1] = 0x11;
4609 spec->input_pins[2] = 0x13;
4610
4611 /* SPDIF I/O */
4612 spec->dig_out = 0x05;
4613 spec->multiout.dig_out_nid = spec->dig_out;
4614 cfg->dig_out_pins[0] = 0x0c;
4615 cfg->dig_outs = 1;
4616 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4617 spec->dig_in = 0x09;
4618 cfg->dig_in_pin = 0x0e;
4619 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4620}
4621
95c6e9cb
IM		 4622static int patch_ca0132(struct hda_codec *codec)
4623{
4624 struct ca0132_spec *spec;
a73d511c 4625 int err;
95c6e9cb
IM		 4626
4627 snd_printdd("patch_ca0132\n");
4628
4629 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4630 if (!spec)
4631 return -ENOMEM;
4632 codec->spec = spec;
4633
a7e76271
IM		 4634 spec->num_mixers = 1;
4635 spec->mixers[0] = ca0132_mixer;
4636
5aaca44d
IM		 4637 spec->base_init_verbs = ca0132_base_init_verbs;
4638 spec->base_exit_verbs = ca0132_base_exit_verbs;
4639 spec->init_verbs[0] = ca0132_init_verbs0;
4640 spec->init_verbs[1] = ca0132_init_verbs1;
4641 spec->num_init_verbs = 2;
4642
95c6e9cb
IM		 4643 ca0132_init_chip(codec);
4644
4645 ca0132_config(codec);
4646
a73d511c
IM		 4647 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4648 if (err < 0)
4649 return err;
4650
95c6e9cb
IM		 4651 codec->patch_ops = ca0132_patch_ops;
4652
4653 return 0;
4654}
4655
4656/*
4657 * patch entries
4658 */
4659static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4660 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4661 {} /* terminator */
4662};
4663
4664MODULE_ALIAS("snd-hda-codec-id:11020011");
4665
4666MODULE_LICENSE("GPL");
406261ce 4667MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb
IM		 4668
4669static struct hda_codec_preset_list ca0132_list = {
4670 .preset = snd_hda_preset_ca0132,
4671 .owner = THIS_MODULE,
4672};
4673
4674static int __init patch_ca0132_init(void)
4675{
4676 return snd_hda_add_codec_preset(&ca0132_list);
4677}
4678
4679static void __exit patch_ca0132_exit(void)
4680{
4681 snd_hda_delete_codec_preset(&ca0132_list);
4682}
4683
4684module_init(patch_ca0132_init)
4685module_exit(patch_ca0132_exit)
Linux 6.x block layer and io_uring tree(s)