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ALSA: hda/ca0132: add alt_select_in/out for R3Di + SBZ
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb
IM		 34#include <sound/core.h>
35#include "hda_codec.h"
36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
38ba69ff 52#define FLOAT_THREE 0x40400000
7cb9d94c 53#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 54#define FLOAT_MINUS_5 0xc0a00000
55
ef6b2ead
IM		 56#define UNSOL_TAG_DSP 0x16
57
4aa3bb0c
IM		 58#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
ef6b2ead
IM		 66#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 68
95c6e9cb
IM		 69#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
4aa3bb0c
IM		 72#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
01ef7dbf 83#define EFX_FILE "ctefx.bin"
8a19bcee
CM		 84#define SBZ_EFX_FILE "ctefx-sbz.bin"
85#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 86
24f3cede 87#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 88MODULE_FIRMWARE(EFX_FILE);
8a19bcee
CM		 89MODULE_FIRMWARE(SBZ_EFX_FILE);
90MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 91#endif
01ef7dbf 92
8a19bcee 93static const char *dirstr[2] = { "Playback", "Capture" };
ef6b2ead 94
7cb9d94c 95#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 96enum {
97 SPEAKER_OUT,
7cb9d94c
CM		 98 HEADPHONE_OUT,
99 SURROUND_OUT
ef6b2ead
IM		 100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
7cb9d94c
CM		 107/* Strings for Input Source Enum Control */
108static const char *in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
ef6b2ead
IM		 116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
7cb9d94c
CM		 149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
151 INPUT_SOURCE_ENUM
ef6b2ead
IM		 152#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
153};
154
155/* Effects values size*/
156#define EFFECT_VALS_MAX_COUNT 12
157
e8412ca4
DR		 158/* Latency introduced by DSP blocks in milliseconds. */
159#define DSP_CAPTURE_INIT_LATENCY 0
160#define DSP_CRYSTAL_VOICE_LATENCY 124
161#define DSP_PLAYBACK_INIT_LATENCY 13
162#define DSP_PLAY_ENHANCEMENT_LATENCY 30
163#define DSP_SPEAKER_OUT_LATENCY 7
164
ef6b2ead 165struct ct_effect {
975cc02a 166 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 167 hda_nid_t nid;
168 int mid; /*effect module ID*/
169 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
170 int direct; /* 0:output; 1:input*/
171 int params; /* number of default non-on/off params */
172 /*effect default values, 1st is on/off. */
173 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
174};
175
176#define EFX_DIR_OUT 0
177#define EFX_DIR_IN 1
178
179static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
180 { .name = "Surround",
181 .nid = SURROUND,
182 .mid = 0x96,
183 .reqs = {0, 1},
184 .direct = EFX_DIR_OUT,
185 .params = 1,
186 .def_vals = {0x3F800000, 0x3F2B851F}
187 },
188 { .name = "Crystalizer",
189 .nid = CRYSTALIZER,
190 .mid = 0x96,
191 .reqs = {7, 8},
192 .direct = EFX_DIR_OUT,
193 .params = 1,
194 .def_vals = {0x3F800000, 0x3F266666}
195 },
196 { .name = "Dialog Plus",
197 .nid = DIALOG_PLUS,
198 .mid = 0x96,
199 .reqs = {2, 3},
200 .direct = EFX_DIR_OUT,
201 .params = 1,
202 .def_vals = {0x00000000, 0x3F000000}
203 },
204 { .name = "Smart Volume",
205 .nid = SMART_VOLUME,
206 .mid = 0x96,
207 .reqs = {4, 5, 6},
208 .direct = EFX_DIR_OUT,
209 .params = 2,
210 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
211 },
212 { .name = "X-Bass",
213 .nid = X_BASS,
214 .mid = 0x96,
215 .reqs = {24, 23, 25},
216 .direct = EFX_DIR_OUT,
217 .params = 2,
218 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
219 },
220 { .name = "Equalizer",
221 .nid = EQUALIZER,
222 .mid = 0x96,
223 .reqs = {9, 10, 11, 12, 13, 14,
224 15, 16, 17, 18, 19, 20},
225 .direct = EFX_DIR_OUT,
226 .params = 11,
227 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
228 0x00000000, 0x00000000, 0x00000000, 0x00000000,
229 0x00000000, 0x00000000, 0x00000000, 0x00000000}
230 },
231 { .name = "Echo Cancellation",
232 .nid = ECHO_CANCELLATION,
233 .mid = 0x95,
234 .reqs = {0, 1, 2, 3},
235 .direct = EFX_DIR_IN,
236 .params = 3,
237 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
238 },
239 { .name = "Voice Focus",
240 .nid = VOICE_FOCUS,
241 .mid = 0x95,
242 .reqs = {6, 7, 8, 9},
243 .direct = EFX_DIR_IN,
244 .params = 3,
245 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
246 },
247 { .name = "Mic SVM",
248 .nid = MIC_SVM,
249 .mid = 0x95,
250 .reqs = {44, 45},
251 .direct = EFX_DIR_IN,
252 .params = 1,
253 .def_vals = {0x00000000, 0x3F3D70A4}
254 },
255 { .name = "Noise Reduction",
256 .nid = NOISE_REDUCTION,
257 .mid = 0x95,
258 .reqs = {4, 5},
259 .direct = EFX_DIR_IN,
260 .params = 1,
261 .def_vals = {0x3F800000, 0x3F000000}
262 },
263 { .name = "VoiceFX",
264 .nid = VOICEFX,
265 .mid = 0x95,
266 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
267 .direct = EFX_DIR_IN,
268 .params = 8,
269 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
270 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
271 0x00000000}
272 }
273};
274
275/* Tuning controls */
276#ifdef ENABLE_TUNING_CONTROLS
277
278enum {
279#define TUNING_CTL_START_NID 0xC0
280 WEDGE_ANGLE = TUNING_CTL_START_NID,
281 SVM_LEVEL,
282 EQUALIZER_BAND_0,
283 EQUALIZER_BAND_1,
284 EQUALIZER_BAND_2,
285 EQUALIZER_BAND_3,
286 EQUALIZER_BAND_4,
287 EQUALIZER_BAND_5,
288 EQUALIZER_BAND_6,
289 EQUALIZER_BAND_7,
290 EQUALIZER_BAND_8,
291 EQUALIZER_BAND_9,
292 TUNING_CTL_END_NID
293#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
294};
295
296struct ct_tuning_ctl {
975cc02a 297 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 298 hda_nid_t parent_nid;
299 hda_nid_t nid;
300 int mid; /*effect module ID*/
301 int req; /*effect module request*/
302 int direct; /* 0:output; 1:input*/
303 unsigned int def_val;/*effect default values*/
304};
305
306static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
307 { .name = "Wedge Angle",
308 .parent_nid = VOICE_FOCUS,
309 .nid = WEDGE_ANGLE,
310 .mid = 0x95,
311 .req = 8,
312 .direct = EFX_DIR_IN,
313 .def_val = 0x41F00000
314 },
315 { .name = "SVM Level",
316 .parent_nid = MIC_SVM,
317 .nid = SVM_LEVEL,
318 .mid = 0x95,
319 .req = 45,
320 .direct = EFX_DIR_IN,
321 .def_val = 0x3F3D70A4
322 },
323 { .name = "EQ Band0",
324 .parent_nid = EQUALIZER,
325 .nid = EQUALIZER_BAND_0,
326 .mid = 0x96,
327 .req = 11,
328 .direct = EFX_DIR_OUT,
329 .def_val = 0x00000000
330 },
331 { .name = "EQ Band1",
332 .parent_nid = EQUALIZER,
333 .nid = EQUALIZER_BAND_1,
334 .mid = 0x96,
335 .req = 12,
336 .direct = EFX_DIR_OUT,
337 .def_val = 0x00000000
338 },
339 { .name = "EQ Band2",
340 .parent_nid = EQUALIZER,
341 .nid = EQUALIZER_BAND_2,
342 .mid = 0x96,
343 .req = 13,
344 .direct = EFX_DIR_OUT,
345 .def_val = 0x00000000
346 },
347 { .name = "EQ Band3",
348 .parent_nid = EQUALIZER,
349 .nid = EQUALIZER_BAND_3,
350 .mid = 0x96,
351 .req = 14,
352 .direct = EFX_DIR_OUT,
353 .def_val = 0x00000000
354 },
355 { .name = "EQ Band4",
356 .parent_nid = EQUALIZER,
357 .nid = EQUALIZER_BAND_4,
358 .mid = 0x96,
359 .req = 15,
360 .direct = EFX_DIR_OUT,
361 .def_val = 0x00000000
362 },
363 { .name = "EQ Band5",
364 .parent_nid = EQUALIZER,
365 .nid = EQUALIZER_BAND_5,
366 .mid = 0x96,
367 .req = 16,
368 .direct = EFX_DIR_OUT,
369 .def_val = 0x00000000
370 },
371 { .name = "EQ Band6",
372 .parent_nid = EQUALIZER,
373 .nid = EQUALIZER_BAND_6,
374 .mid = 0x96,
375 .req = 17,
376 .direct = EFX_DIR_OUT,
377 .def_val = 0x00000000
378 },
379 { .name = "EQ Band7",
380 .parent_nid = EQUALIZER,
381 .nid = EQUALIZER_BAND_7,
382 .mid = 0x96,
383 .req = 18,
384 .direct = EFX_DIR_OUT,
385 .def_val = 0x00000000
386 },
387 { .name = "EQ Band8",
388 .parent_nid = EQUALIZER,
389 .nid = EQUALIZER_BAND_8,
390 .mid = 0x96,
391 .req = 19,
392 .direct = EFX_DIR_OUT,
393 .def_val = 0x00000000
394 },
395 { .name = "EQ Band9",
396 .parent_nid = EQUALIZER,
397 .nid = EQUALIZER_BAND_9,
398 .mid = 0x96,
399 .req = 20,
400 .direct = EFX_DIR_OUT,
401 .def_val = 0x00000000
402 }
403};
404#endif
405
406/* Voice FX Presets */
407#define VOICEFX_MAX_PARAM_COUNT 9
408
409struct ct_voicefx {
410 char *name;
411 hda_nid_t nid;
412 int mid;
413 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
414};
415
416struct ct_voicefx_preset {
417 char *name; /*preset name*/
418 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
419};
420
ccd7bd3d 421static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 422 .name = "VoiceFX Capture Switch",
423 .nid = VOICEFX,
424 .mid = 0x95,
425 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
426};
427
ccd7bd3d 428static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 429 { .name = "Neutral",
430 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
431 0x44FA0000, 0x3F800000, 0x3F800000,
432 0x3F800000, 0x00000000, 0x00000000 }
433 },
434 { .name = "Female2Male",
435 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
436 0x44FA0000, 0x3F19999A, 0x3F866666,
437 0x3F800000, 0x00000000, 0x00000000 }
438 },
439 { .name = "Male2Female",
440 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
441 0x450AC000, 0x4017AE14, 0x3F6B851F,
442 0x3F800000, 0x00000000, 0x00000000 }
443 },
444 { .name = "ScrappyKid",
445 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
446 0x44FA0000, 0x40400000, 0x3F28F5C3,
447 0x3F800000, 0x00000000, 0x00000000 }
448 },
449 { .name = "Elderly",
450 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
451 0x44E10000, 0x3FB33333, 0x3FB9999A,
452 0x3F800000, 0x3E3A2E43, 0x00000000 }
453 },
454 { .name = "Orc",
455 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
456 0x45098000, 0x3F266666, 0x3FC00000,
457 0x3F800000, 0x00000000, 0x00000000 }
458 },
459 { .name = "Elf",
460 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
461 0x45193000, 0x3F8E147B, 0x3F75C28F,
462 0x3F800000, 0x00000000, 0x00000000 }
463 },
464 { .name = "Dwarf",
465 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
466 0x45007000, 0x3F451EB8, 0x3F7851EC,
467 0x3F800000, 0x00000000, 0x00000000 }
468 },
469 { .name = "AlienBrute",
470 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
471 0x451F6000, 0x3F266666, 0x3FA7D945,
472 0x3F800000, 0x3CF5C28F, 0x00000000 }
473 },
474 { .name = "Robot",
475 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
476 0x44FA0000, 0x3FB2718B, 0x3F800000,
477 0xBC07010E, 0x00000000, 0x00000000 }
478 },
479 { .name = "Marine",
480 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
481 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
482 0x3F0A3D71, 0x00000000, 0x00000000 }
483 },
484 { .name = "Emo",
485 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
486 0x44FA0000, 0x3F800000, 0x3F800000,
487 0x3E4CCCCD, 0x00000000, 0x00000000 }
488 },
489 { .name = "DeepVoice",
490 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
491 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
492 0x3F800000, 0x00000000, 0x00000000 }
493 },
494 { .name = "Munchkin",
495 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
496 0x44FA0000, 0x3F800000, 0x3F1A043C,
497 0x3F800000, 0x00000000, 0x00000000 }
498 }
499};
500
7cb9d94c
CM		 501/* DSP command sequences for ca0132_alt_select_out */
502#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
503struct ca0132_alt_out_set {
504 char *name; /*preset name*/
505 unsigned char commands;
506 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
507 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
508 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
509};
510
511static const struct ca0132_alt_out_set alt_out_presets[] = {
512 { .name = "Line Out",
513 .commands = 7,
514 .mids = { 0x96, 0x96, 0x96, 0x8F,
515 0x96, 0x96, 0x96 },
516 .reqs = { 0x19, 0x17, 0x18, 0x01,
517 0x1F, 0x15, 0x3A },
518 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
519 0x00000000, 0x00000000, 0x00000000,
520 0x00000000 }
521 },
522 { .name = "Headphone",
523 .commands = 7,
524 .mids = { 0x96, 0x96, 0x96, 0x8F,
525 0x96, 0x96, 0x96 },
526 .reqs = { 0x19, 0x17, 0x18, 0x01,
527 0x1F, 0x15, 0x3A },
528 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
529 0x00000000, 0x00000000, 0x00000000,
530 0x00000000 }
531 },
532 { .name = "Surround",
533 .commands = 8,
534 .mids = { 0x96, 0x8F, 0x96, 0x96,
535 0x96, 0x96, 0x96, 0x96 },
536 .reqs = { 0x18, 0x01, 0x1F, 0x15,
537 0x3A, 0x1A, 0x1B, 0x1C },
538 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x00000000,
540 0x00000000, 0x00000000 }
541 }
542};
543
95c6e9cb
IM		 544enum hda_cmd_vendor_io {
545 /* for DspIO node */
546 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
547 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
548
549 VENDOR_DSPIO_STATUS = 0xF01,
550 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
551 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
552 VENDOR_DSPIO_DSP_INIT = 0x703,
553 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
554 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
555
556 /* for ChipIO node */
557 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
558 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
559 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
560 VENDOR_CHIPIO_DATA_LOW = 0x300,
561 VENDOR_CHIPIO_DATA_HIGH = 0x400,
562
563 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
564 VENDOR_CHIPIO_STATUS = 0xF01,
565 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
566 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
567
4aa3bb0c
IM		 568 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
569 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
570
95c6e9cb 571 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 572 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 573
574 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
575 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
576 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
577 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
578 VENDOR_CHIPIO_FLAG_SET = 0x70F,
579 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 580 VENDOR_CHIPIO_PARAM_SET = 0x710,
581 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 582
583 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
584 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
585 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
586 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
587
4aa3bb0c
IM		 588 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
589 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
590 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
591 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
592
593 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
594 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
595 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
596 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
597 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
598 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
599
600 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 601};
602
603/*
604 * Control flag IDs
605 */
606enum control_flag_id {
607 /* Connection manager stream setup is bypassed/enabled */
608 CONTROL_FLAG_C_MGR = 0,
609 /* DSP DMA is bypassed/enabled */
610 CONTROL_FLAG_DMA = 1,
611 /* 8051 'idle' mode is disabled/enabled */
612 CONTROL_FLAG_IDLE_ENABLE = 2,
613 /* Tracker for the SPDIF-in path is bypassed/enabled */
614 CONTROL_FLAG_TRACKER = 3,
615 /* DigitalOut to Spdif2Out connection is disabled/enabled */
616 CONTROL_FLAG_SPDIF2OUT = 4,
617 /* Digital Microphone is disabled/enabled */
618 CONTROL_FLAG_DMIC = 5,
619 /* ADC_B rate is 48 kHz/96 kHz */
620 CONTROL_FLAG_ADC_B_96KHZ = 6,
621 /* ADC_C rate is 48 kHz/96 kHz */
622 CONTROL_FLAG_ADC_C_96KHZ = 7,
623 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
624 CONTROL_FLAG_DAC_96KHZ = 8,
625 /* DSP rate is 48 kHz/96 kHz */
626 CONTROL_FLAG_DSP_96KHZ = 9,
627 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
628 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
629 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
630 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
631 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
632 CONTROL_FLAG_DECODE_LOOP = 12,
633 /* De-emphasis filter on DAC-1 disabled/enabled */
634 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
635 /* De-emphasis filter on DAC-2 disabled/enabled */
636 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
637 /* De-emphasis filter on DAC-3 disabled/enabled */
638 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
639 /* High-pass filter on ADC_B disabled/enabled */
640 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
641 /* High-pass filter on ADC_C disabled/enabled */
642 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
643 /* Common mode on Port_A disabled/enabled */
644 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
645 /* Common mode on Port_D disabled/enabled */
646 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
647 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
648 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
649 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 650 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 651 /* ASI rate is 48kHz/96kHz */
652 CONTROL_FLAG_ASI_96KHZ = 22,
653 /* DAC power settings able to control attached ports no/yes */
654 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
655 /* Clock Stop OK reporting is disabled/enabled */
656 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
657 /* Number of control flags */
658 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
659};
660
661/*
662 * Control parameter IDs
663 */
4aa3bb0c 664enum control_param_id {
ef6b2ead
IM		 665 /* 0: None, 1: Mic1In*/
666 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 667 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
668 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 669 /* Port A output stage gain setting to use when 16 Ohm output
670 * impedance is selected*/
671 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
672 /* Port D output stage gain setting to use when 16 Ohm output
673 * impedance is selected*/
674 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 675
676 /* Stream Control */
677
678 /* Select stream with the given ID */
679 CONTROL_PARAM_STREAM_ID = 24,
680 /* Source connection point for the selected stream */
681 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
682 /* Destination connection point for the selected stream */
683 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
684 /* Number of audio channels in the selected stream */
685 CONTROL_PARAM_STREAMS_CHANNELS = 27,
686 /*Enable control for the selected stream */
687 CONTROL_PARAM_STREAM_CONTROL = 28,
688
689 /* Connection Point Control */
690
691 /* Select connection point with the given ID */
692 CONTROL_PARAM_CONN_POINT_ID = 29,
693 /* Connection point sample rate */
694 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
695
696 /* Node Control */
697
698 /* Select HDA node with the given ID */
699 CONTROL_PARAM_NODE_ID = 31
700};
701
702/*
703 * Dsp Io Status codes
704 */
705enum hda_vendor_status_dspio {
706 /* Success */
707 VENDOR_STATUS_DSPIO_OK = 0x00,
708 /* Busy, unable to accept new command, the host must retry */
709 VENDOR_STATUS_DSPIO_BUSY = 0x01,
710 /* SCP command queue is full */
711 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
712 /* SCP response queue is empty */
713 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
714};
715
716/*
717 * Chip Io Status codes
718 */
719enum hda_vendor_status_chipio {
720 /* Success */
721 VENDOR_STATUS_CHIPIO_OK = 0x00,
722 /* Busy, unable to accept new command, the host must retry */
723 VENDOR_STATUS_CHIPIO_BUSY = 0x01
724};
725
726/*
727 * CA0132 sample rate
728 */
729enum ca0132_sample_rate {
730 SR_6_000 = 0x00,
731 SR_8_000 = 0x01,
732 SR_9_600 = 0x02,
733 SR_11_025 = 0x03,
734 SR_16_000 = 0x04,
735 SR_22_050 = 0x05,
736 SR_24_000 = 0x06,
737 SR_32_000 = 0x07,
738 SR_44_100 = 0x08,
739 SR_48_000 = 0x09,
740 SR_88_200 = 0x0A,
741 SR_96_000 = 0x0B,
742 SR_144_000 = 0x0C,
743 SR_176_400 = 0x0D,
744 SR_192_000 = 0x0E,
745 SR_384_000 = 0x0F,
746
747 SR_COUNT = 0x10,
748
749 SR_RATE_UNKNOWN = 0x1F
750};
751
01ef7dbf
IM		 752enum dsp_download_state {
753 DSP_DOWNLOAD_FAILED = -1,
754 DSP_DOWNLOAD_INIT = 0,
755 DSP_DOWNLOADING = 1,
756 DSP_DOWNLOADED = 2
757};
758
01ef7dbf
IM		 759/* retrieve parameters from hda format */
760#define get_hdafmt_chs(fmt) (fmt & 0xf)
761#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
762#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
763#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
764
765/*
766 * CA0132 specific
767 */
768
769struct ca0132_spec {
a7e76271
IM		 770 struct snd_kcontrol_new *mixers[5];
771 unsigned int num_mixers;
5aaca44d
IM		 772 const struct hda_verb *base_init_verbs;
773 const struct hda_verb *base_exit_verbs;
d5c016b5 774 const struct hda_verb *chip_init_verbs;
e93ac30a 775 const struct hda_verb *sbz_init_verbs;
d5c016b5 776 struct hda_verb *spec_init_verbs;
01ef7dbf 777 struct auto_pin_cfg autocfg;
5aaca44d
IM		 778
779 /* Nodes configurations */
01ef7dbf
IM		 780 struct hda_multi_out multiout;
781 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
782 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 783 unsigned int num_outputs;
01ef7dbf
IM		 784 hda_nid_t input_pins[AUTO_PIN_LAST];
785 hda_nid_t adcs[AUTO_PIN_LAST];
786 hda_nid_t dig_out;
787 hda_nid_t dig_in;
788 unsigned int num_inputs;
a7e76271
IM		 789 hda_nid_t shared_mic_nid;
790 hda_nid_t shared_out_nid;
d5c016b5 791 hda_nid_t unsol_tag_hp;
63177afc 792 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 793 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 794
795 /* chip access */
796 struct mutex chipio_mutex; /* chip access mutex */
797 u32 curr_chip_addx;
798
799 /* DSP download related */
800 enum dsp_download_state dsp_state;
801 unsigned int dsp_stream_id;
802 unsigned int wait_scp;
803 unsigned int wait_scp_header;
804 unsigned int wait_num_data;
805 unsigned int scp_resp_header;
806 unsigned int scp_resp_data[4];
807 unsigned int scp_resp_count;
8a19bcee 808 bool alt_firmware_present;
38ba69ff 809 bool startup_check_entered;
e93ac30a 810 bool dsp_reload;
5aaca44d
IM		 811
812 /* mixer and effects related */
813 unsigned char dmic_ctl;
814 int cur_out_type;
815 int cur_mic_type;
816 long vnode_lvol[VNODES_COUNT];
817 long vnode_rvol[VNODES_COUNT];
818 long vnode_lswitch[VNODES_COUNT];
819 long vnode_rswitch[VNODES_COUNT];
820 long effects_switch[EFFECTS_COUNT];
821 long voicefx_val;
822 long cur_mic_boost;
7cb9d94c
CM		 823 /* ca0132_alt control related values */
824 unsigned char in_enum_val;
825 unsigned char out_enum_val;
44f0c978 826
993884f6
CCC		 827 struct hda_codec *codec;
828 struct delayed_work unsol_hp_work;
d5c016b5 829 int quirk;
993884f6 830
44f0c978
IM		 831#ifdef ENABLE_TUNING_CONTROLS
832 long cur_ctl_vals[TUNING_CTLS_COUNT];
833#endif
aa31704f
CM		 834 /*
835 * Sound Blaster Z PCI region 2 iomem, used for input and output
836 * switching, and other unknown commands.
837 */
838 void __iomem *mem_base;
009b8f97
CM		 839
840 /*
841 * Whether or not to use the alt functions like alt_select_out,
842 * alt_select_in, etc. Only used on desktop codecs for now, because of
843 * surround sound support.
844 */
845 bool use_alt_functions;
01ef7dbf
IM		 846};
847
d5c016b5
GM		 848/*
849 * CA0132 quirks table
850 */
851enum {
852 QUIRK_NONE,
853 QUIRK_ALIENWARE,
8a19bcee
CM		 854 QUIRK_SBZ,
855 QUIRK_R3DI,
d5c016b5
GM		 856};
857
fe14f39e
TI		 858static const struct hda_pintbl alienware_pincfgs[] = {
859 { 0x0b, 0x90170110 }, /* Builtin Speaker */
860 { 0x0c, 0x411111f0 }, /* N/A */
861 { 0x0d, 0x411111f0 }, /* N/A */
862 { 0x0e, 0x411111f0 }, /* N/A */
863 { 0x0f, 0x0321101f }, /* HP */
864 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
865 { 0x11, 0x03a11021 }, /* Mic */
866 { 0x12, 0xd5a30140 }, /* Builtin Mic */
867 { 0x13, 0x411111f0 }, /* N/A */
868 { 0x18, 0x411111f0 }, /* N/A */
869 {}
870};
871
63177afc
CM		 872/* Sound Blaster Z pin configs taken from Windows Driver */
873static const struct hda_pintbl sbz_pincfgs[] = {
874 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
875 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
876 { 0x0d, 0x014510f0 }, /* Digital Out */
877 { 0x0e, 0x01c510f0 }, /* SPDIF In */
878 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
879 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
880 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
881 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
882 { 0x13, 0x908700f0 }, /* What U Hear In*/
883 { 0x18, 0x50d000f0 }, /* N/A */
884 {}
885};
886
887/* Recon3D integrated pin configs taken from Windows Driver */
888static const struct hda_pintbl r3di_pincfgs[] = {
889 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
890 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
891 { 0x0d, 0x014510f0 }, /* Digital Out */
892 { 0x0e, 0x41c520f0 }, /* SPDIF In */
893 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
894 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
895 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
896 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
897 { 0x13, 0x908700f0 }, /* What U Hear In*/
898 { 0x18, 0x500000f0 }, /* N/A */
899 {}
900};
901
d5c016b5 902static const struct snd_pci_quirk ca0132_quirks[] = {
5328e1ea
GM		 903 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
904 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 905 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 906 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
907 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
908 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
909 SND_PCI_QUIRK(0x1458, 0xA036, "Recon3Di", QUIRK_R3DI),
d5c016b5
GM		 910 {}
911};
912
01ef7dbf
IM		 913/*
914 * CA0132 codec access
915 */
399ae725 916static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 917 unsigned int verb, unsigned int parm, unsigned int *res)
918{
919 unsigned int response;
920 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
921 *res = response;
922
923 return ((response == -1) ? -1 : 0);
924}
925
926static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
927 unsigned short converter_format, unsigned int *res)
928{
929 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
930 converter_format & 0xffff, res);
931}
932
933static int codec_set_converter_stream_channel(struct hda_codec *codec,
934 hda_nid_t nid, unsigned char stream,
935 unsigned char channel, unsigned int *res)
936{
937 unsigned char converter_stream_channel = 0;
938
939 converter_stream_channel = (stream << 4) | (channel & 0x0f);
940 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
941 converter_stream_channel, res);
942}
943
944/* Chip access helper function */
945static int chipio_send(struct hda_codec *codec,
946 unsigned int reg,
947 unsigned int data)
948{
949 unsigned int res;
6d67530e 950 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 951
952 /* send bits of data specified by reg */
953 do {
954 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
955 reg, data);
956 if (res == VENDOR_STATUS_CHIPIO_OK)
957 return 0;
6d67530e
IM		 958 msleep(20);
959 } while (time_before(jiffies, timeout));
960
01ef7dbf
IM		 961 return -EIO;
962}
963
964/*
965 * Write chip address through the vendor widget -- NOT protected by the Mutex!
966 */
967static int chipio_write_address(struct hda_codec *codec,
968 unsigned int chip_addx)
969{
4861af80 970 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 971 int res;
972
4861af80
IM		 973 if (spec->curr_chip_addx == chip_addx)
974 return 0;
975
01ef7dbf
IM		 976 /* send low 16 bits of the address */
977 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
978 chip_addx & 0xffff);
979
980 if (res != -EIO) {
981 /* send high 16 bits of the address */
982 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
983 chip_addx >> 16);
984 }
985
d1600401 986 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 987
4861af80 988 return res;
01ef7dbf
IM		 989}
990
991/*
992 * Write data through the vendor widget -- NOT protected by the Mutex!
993 */
01ef7dbf
IM		 994static int chipio_write_data(struct hda_codec *codec, unsigned int data)
995{
5aaca44d 996 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 997 int res;
998
999 /* send low 16 bits of the data */
1000 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1001
1002 if (res != -EIO) {
1003 /* send high 16 bits of the data */
1004 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1005 data >> 16);
1006 }
1007
5aaca44d
IM		 1008 /*If no error encountered, automatically increment the address
1009 as per chip behaviour*/
1010 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1011 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1012 return res;
1013}
1014
d5c21b88
IM		 1015/*
1016 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1017 */
01ef7dbf
IM		 1018static int chipio_write_data_multiple(struct hda_codec *codec,
1019 const u32 *data,
1020 unsigned int count)
1021{
1022 int status = 0;
1023
1024 if (data == NULL) {
4e76a883 1025 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1026 return -EINVAL;
1027 }
1028
1029 while ((count-- != 0) && (status == 0))
1030 status = chipio_write_data(codec, *data++);
1031
1032 return status;
1033}
1034
1035
1036/*
1037 * Read data through the vendor widget -- NOT protected by the Mutex!
1038 */
1039static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1040{
5aaca44d 1041 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1042 int res;
1043
1044 /* post read */
1045 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1046
1047 if (res != -EIO) {
1048 /* read status */
1049 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1050 }
1051
1052 if (res != -EIO) {
1053 /* read data */
1054 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1055 VENDOR_CHIPIO_HIC_READ_DATA,
1056 0);
1057 }
1058
5aaca44d
IM		 1059 /*If no error encountered, automatically increment the address
1060 as per chip behaviour*/
1061 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1062 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1063 return res;
1064}
1065
1066/*
1067 * Write given value to the given address through the chip I/O widget.
1068 * protected by the Mutex
1069 */
1070static int chipio_write(struct hda_codec *codec,
1071 unsigned int chip_addx, const unsigned int data)
1072{
1073 struct ca0132_spec *spec = codec->spec;
1074 int err;
1075
1076 mutex_lock(&spec->chipio_mutex);
1077
1078 /* write the address, and if successful proceed to write data */
1079 err = chipio_write_address(codec, chip_addx);
1080 if (err < 0)
1081 goto exit;
1082
1083 err = chipio_write_data(codec, data);
1084 if (err < 0)
1085 goto exit;
1086
1087exit:
1088 mutex_unlock(&spec->chipio_mutex);
1089 return err;
1090}
1091
38ba69ff
CM		 1092/*
1093 * Write given value to the given address through the chip I/O widget.
1094 * not protected by the Mutex
1095 */
1096static int chipio_write_no_mutex(struct hda_codec *codec,
1097 unsigned int chip_addx, const unsigned int data)
1098{
1099 int err;
1100
1101
1102 /* write the address, and if successful proceed to write data */
1103 err = chipio_write_address(codec, chip_addx);
1104 if (err < 0)
1105 goto exit;
1106
1107 err = chipio_write_data(codec, data);
1108 if (err < 0)
1109 goto exit;
1110
1111exit:
1112 return err;
1113}
1114
d5c21b88
IM		 1115/*
1116 * Write multiple values to the given address through the chip I/O widget.
1117 * protected by the Mutex
1118 */
01ef7dbf
IM		 1119static int chipio_write_multiple(struct hda_codec *codec,
1120 u32 chip_addx,
1121 const u32 *data,
1122 unsigned int count)
1123{
1124 struct ca0132_spec *spec = codec->spec;
1125 int status;
1126
1127 mutex_lock(&spec->chipio_mutex);
4861af80 1128 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1129 if (status < 0)
1130 goto error;
1131
1132 status = chipio_write_data_multiple(codec, data, count);
1133error:
1134 mutex_unlock(&spec->chipio_mutex);
1135
1136 return status;
1137}
1138
1139/*
1140 * Read the given address through the chip I/O widget
1141 * protected by the Mutex
1142 */
1143static int chipio_read(struct hda_codec *codec,
1144 unsigned int chip_addx, unsigned int *data)
1145{
1146 struct ca0132_spec *spec = codec->spec;
1147 int err;
1148
1149 mutex_lock(&spec->chipio_mutex);
1150
1151 /* write the address, and if successful proceed to write data */
1152 err = chipio_write_address(codec, chip_addx);
1153 if (err < 0)
1154 goto exit;
1155
1156 err = chipio_read_data(codec, data);
1157 if (err < 0)
1158 goto exit;
1159
1160exit:
1161 mutex_unlock(&spec->chipio_mutex);
1162 return err;
1163}
1164
d5c21b88
IM		 1165/*
1166 * Set chip control flags through the chip I/O widget.
1167 */
01ef7dbf
IM		 1168static void chipio_set_control_flag(struct hda_codec *codec,
1169 enum control_flag_id flag_id,
1170 bool flag_state)
1171{
1172 unsigned int val;
1173 unsigned int flag_bit;
1174
1175 flag_bit = (flag_state ? 1 : 0);
1176 val = (flag_bit << 7) | (flag_id);
1177 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1178 VENDOR_CHIPIO_FLAG_SET, val);
1179}
1180
d5c21b88
IM		 1181/*
1182 * Set chip parameters through the chip I/O widget.
1183 */
01ef7dbf
IM		 1184static void chipio_set_control_param(struct hda_codec *codec,
1185 enum control_param_id param_id, int param_val)
1186{
1187 struct ca0132_spec *spec = codec->spec;
1188 int val;
1189
1190 if ((param_id < 32) && (param_val < 8)) {
1191 val = (param_val << 5) | (param_id);
1192 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1193 VENDOR_CHIPIO_PARAM_SET, val);
1194 } else {
1195 mutex_lock(&spec->chipio_mutex);
1196 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1197 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1198 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1199 param_id);
1200 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1201 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1202 param_val);
1203 }
1204 mutex_unlock(&spec->chipio_mutex);
1205 }
1206}
1207
009b8f97
CM		 1208/*
1209 * Set chip parameters through the chip I/O widget. NO MUTEX.
1210 */
1211static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1212 enum control_param_id param_id, int param_val)
1213{
1214 int val;
1215
1216 if ((param_id < 32) && (param_val < 8)) {
1217 val = (param_val << 5) | (param_id);
1218 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1219 VENDOR_CHIPIO_PARAM_SET, val);
1220 } else {
1221 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1222 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1223 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1224 param_id);
1225 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1226 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1227 param_val);
1228 }
1229 }
1230}
38ba69ff
CM		 1231/*
1232 * Connect stream to a source point, and then connect
1233 * that source point to a destination point.
1234 */
1235static void chipio_set_stream_source_dest(struct hda_codec *codec,
1236 int streamid, int source_point, int dest_point)
1237{
1238 chipio_set_control_param_no_mutex(codec,
1239 CONTROL_PARAM_STREAM_ID, streamid);
1240 chipio_set_control_param_no_mutex(codec,
1241 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1242 chipio_set_control_param_no_mutex(codec,
1243 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1244}
1245
1246/*
1247 * Set number of channels in the selected stream.
1248 */
1249static void chipio_set_stream_channels(struct hda_codec *codec,
1250 int streamid, unsigned int channels)
1251{
1252 chipio_set_control_param_no_mutex(codec,
1253 CONTROL_PARAM_STREAM_ID, streamid);
1254 chipio_set_control_param_no_mutex(codec,
1255 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1256}
009b8f97
CM		 1257
1258/*
1259 * Enable/Disable audio stream.
1260 */
1261static void chipio_set_stream_control(struct hda_codec *codec,
1262 int streamid, int enable)
1263{
1264 chipio_set_control_param_no_mutex(codec,
1265 CONTROL_PARAM_STREAM_ID, streamid);
1266 chipio_set_control_param_no_mutex(codec,
1267 CONTROL_PARAM_STREAM_CONTROL, enable);
1268}
1269
38ba69ff
CM		 1270
1271/*
1272 * Set sampling rate of the connection point. NO MUTEX.
1273 */
1274static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1275 int connid, enum ca0132_sample_rate rate)
1276{
1277 chipio_set_control_param_no_mutex(codec,
1278 CONTROL_PARAM_CONN_POINT_ID, connid);
1279 chipio_set_control_param_no_mutex(codec,
1280 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1281}
1282
d5c21b88
IM		 1283/*
1284 * Set sampling rate of the connection point.
1285 */
01ef7dbf
IM		 1286static void chipio_set_conn_rate(struct hda_codec *codec,
1287 int connid, enum ca0132_sample_rate rate)
1288{
1289 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1290 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1291 rate);
1292}
1293
d5c21b88
IM		 1294/*
1295 * Enable clocks.
1296 */
01ef7dbf
IM		 1297static void chipio_enable_clocks(struct hda_codec *codec)
1298{
1299 struct ca0132_spec *spec = codec->spec;
1300
1301 mutex_lock(&spec->chipio_mutex);
1302 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1303 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1304 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1305 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1306 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1307 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1308 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1309 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1310 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1311 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1312 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1313 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1314 mutex_unlock(&spec->chipio_mutex);
1315}
1316
1317/*
1318 * CA0132 DSP IO stuffs
1319 */
1320static int dspio_send(struct hda_codec *codec, unsigned int reg,
1321 unsigned int data)
1322{
b645d796 1323 int res;
6d67530e 1324 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1325
1326 /* send bits of data specified by reg to dsp */
1327 do {
1328 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1329 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1330 return res;
6d67530e
IM		 1331 msleep(20);
1332 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1333
1334 return -EIO;
1335}
1336
d5c21b88
IM		 1337/*
1338 * Wait for DSP to be ready for commands
1339 */
01ef7dbf
IM		 1340static void dspio_write_wait(struct hda_codec *codec)
1341{
4861af80
IM		 1342 int status;
1343 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1344
01ef7dbf 1345 do {
4861af80
IM		 1346 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1347 VENDOR_DSPIO_STATUS, 0);
1348 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1349 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1350 break;
1351 msleep(1);
1352 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1353}
1354
d5c21b88
IM		 1355/*
1356 * Write SCP data to DSP
1357 */
01ef7dbf
IM		 1358static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1359{
1360 struct ca0132_spec *spec = codec->spec;
1361 int status;
1362
1363 dspio_write_wait(codec);
1364
1365 mutex_lock(&spec->chipio_mutex);
1366 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1367 scp_data & 0xffff);
1368 if (status < 0)
1369 goto error;
1370
1371 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1372 scp_data >> 16);
1373 if (status < 0)
1374 goto error;
1375
1376 /* OK, now check if the write itself has executed*/
1377 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1378 VENDOR_DSPIO_STATUS, 0);
1379error:
1380 mutex_unlock(&spec->chipio_mutex);
1381
1382 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1383 -EIO : 0;
1384}
1385
d5c21b88
IM		 1386/*
1387 * Write multiple SCP data to DSP
1388 */
01ef7dbf
IM		 1389static int dspio_write_multiple(struct hda_codec *codec,
1390 unsigned int *buffer, unsigned int size)
1391{
1392 int status = 0;
1393 unsigned int count;
1394
a16fbb85 1395 if (buffer == NULL)
01ef7dbf
IM		 1396 return -EINVAL;
1397
1398 count = 0;
1399 while (count < size) {
1400 status = dspio_write(codec, *buffer++);
1401 if (status != 0)
1402 break;
1403 count++;
1404 }
1405
1406 return status;
1407}
1408
a73d511c
IM		 1409static int dspio_read(struct hda_codec *codec, unsigned int *data)
1410{
1411 int status;
1412
1413 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1414 if (status == -EIO)
1415 return status;
1416
1417 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1418 if (status == -EIO ||
1419 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1420 return -EIO;
1421
1422 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1423 VENDOR_DSPIO_SCP_READ_DATA, 0);
1424
1425 return 0;
1426}
1427
1428static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1429 unsigned int *buf_size, unsigned int size_count)
1430{
1431 int status = 0;
1432 unsigned int size = *buf_size;
1433 unsigned int count;
1434 unsigned int skip_count;
1435 unsigned int dummy;
1436
a16fbb85 1437 if (buffer == NULL)
a73d511c
IM		 1438 return -1;
1439
1440 count = 0;
1441 while (count < size && count < size_count) {
1442 status = dspio_read(codec, buffer++);
1443 if (status != 0)
1444 break;
1445 count++;
1446 }
1447
1448 skip_count = count;
1449 if (status == 0) {
1450 while (skip_count < size) {
1451 status = dspio_read(codec, &dummy);
1452 if (status != 0)
1453 break;
1454 skip_count++;
1455 }
1456 }
1457 *buf_size = count;
1458
1459 return status;
1460}
1461
d5c21b88
IM		 1462/*
1463 * Construct the SCP header using corresponding fields
1464 */
01ef7dbf
IM		 1465static inline unsigned int
1466make_scp_header(unsigned int target_id, unsigned int source_id,
1467 unsigned int get_flag, unsigned int req,
1468 unsigned int device_flag, unsigned int resp_flag,
1469 unsigned int error_flag, unsigned int data_size)
1470{
1471 unsigned int header = 0;
1472
1473 header = (data_size & 0x1f) << 27;
1474 header |= (error_flag & 0x01) << 26;
1475 header |= (resp_flag & 0x01) << 25;
1476 header |= (device_flag & 0x01) << 24;
1477 header |= (req & 0x7f) << 17;
1478 header |= (get_flag & 0x01) << 16;
1479 header |= (source_id & 0xff) << 8;
1480 header |= target_id & 0xff;
1481
1482 return header;
1483}
1484
d5c21b88
IM		 1485/*
1486 * Extract corresponding fields from SCP header
1487 */
01ef7dbf
IM		 1488static inline void
1489extract_scp_header(unsigned int header,
1490 unsigned int *target_id, unsigned int *source_id,
1491 unsigned int *get_flag, unsigned int *req,
1492 unsigned int *device_flag, unsigned int *resp_flag,
1493 unsigned int *error_flag, unsigned int *data_size)
1494{
1495 if (data_size)
1496 *data_size = (header >> 27) & 0x1f;
1497 if (error_flag)
1498 *error_flag = (header >> 26) & 0x01;
1499 if (resp_flag)
1500 *resp_flag = (header >> 25) & 0x01;
1501 if (device_flag)
1502 *device_flag = (header >> 24) & 0x01;
1503 if (req)
1504 *req = (header >> 17) & 0x7f;
1505 if (get_flag)
1506 *get_flag = (header >> 16) & 0x01;
1507 if (source_id)
1508 *source_id = (header >> 8) & 0xff;
1509 if (target_id)
1510 *target_id = header & 0xff;
1511}
1512
1513#define SCP_MAX_DATA_WORDS (16)
1514
1515/* Structure to contain any SCP message */
1516struct scp_msg {
1517 unsigned int hdr;
1518 unsigned int data[SCP_MAX_DATA_WORDS];
1519};
1520
a73d511c
IM		 1521static void dspio_clear_response_queue(struct hda_codec *codec)
1522{
1523 unsigned int dummy = 0;
1524 int status = -1;
1525
1526 /* clear all from the response queue */
1527 do {
1528 status = dspio_read(codec, &dummy);
1529 } while (status == 0);
1530}
1531
1532static int dspio_get_response_data(struct hda_codec *codec)
1533{
1534 struct ca0132_spec *spec = codec->spec;
1535 unsigned int data = 0;
1536 unsigned int count;
1537
1538 if (dspio_read(codec, &data) < 0)
1539 return -EIO;
1540
1541 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1542 spec->scp_resp_header = data;
1543 spec->scp_resp_count = data >> 27;
1544 count = spec->wait_num_data;
1545 dspio_read_multiple(codec, spec->scp_resp_data,
1546 &spec->scp_resp_count, count);
1547 return 0;
1548 }
1549
1550 return -EIO;
1551}
1552
d5c21b88
IM		 1553/*
1554 * Send SCP message to DSP
1555 */
01ef7dbf
IM		 1556static int dspio_send_scp_message(struct hda_codec *codec,
1557 unsigned char *send_buf,
1558 unsigned int send_buf_size,
1559 unsigned char *return_buf,
1560 unsigned int return_buf_size,
1561 unsigned int *bytes_returned)
1562{
1563 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1564 int status = -1;
1565 unsigned int scp_send_size = 0;
1566 unsigned int total_size;
1567 bool waiting_for_resp = false;
1568 unsigned int header;
1569 struct scp_msg *ret_msg;
1570 unsigned int resp_src_id, resp_target_id;
1571 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1572
1573 if (bytes_returned)
1574 *bytes_returned = 0;
1575
1576 /* get scp header from buffer */
1577 header = *((unsigned int *)send_buf);
1578 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1579 &device_flag, NULL, NULL, &data_size);
1580 scp_send_size = data_size + 1;
1581 total_size = (scp_send_size * 4);
1582
1583 if (send_buf_size < total_size)
1584 return -EINVAL;
1585
1586 if (get_flag || device_flag) {
1587 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1588 return -EINVAL;
1589
1590 spec->wait_scp_header = *((unsigned int *)send_buf);
1591
1592 /* swap source id with target id */
1593 resp_target_id = src_id;
1594 resp_src_id = target_id;
1595 spec->wait_scp_header &= 0xffff0000;
1596 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1597 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1598 spec->wait_scp = 1;
1599 waiting_for_resp = true;
1600 }
1601
1602 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1603 scp_send_size);
1604 if (status < 0) {
1605 spec->wait_scp = 0;
1606 return status;
1607 }
1608
1609 if (waiting_for_resp) {
6d67530e 1610 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1611 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1612 do {
1613 msleep(20);
6d67530e 1614 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1615 waiting_for_resp = false;
6d67530e 1616 if (!spec->wait_scp) {
01ef7dbf
IM		 1617 ret_msg = (struct scp_msg *)return_buf;
1618 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1619 memcpy(&ret_msg->data, spec->scp_resp_data,
1620 spec->wait_num_data);
1621 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1622 status = 0;
1623 } else {
1624 status = -EIO;
1625 }
1626 spec->wait_scp = 0;
1627 }
1628
1629 return status;
1630}
1631
d5c21b88
IM		 1632/**
1633 * Prepare and send the SCP message to DSP
1634 * @codec: the HDA codec
1635 * @mod_id: ID of the DSP module to send the command
1636 * @req: ID of request to send to the DSP module
1637 * @dir: SET or GET
1638 * @data: pointer to the data to send with the request, request specific
1639 * @len: length of the data, in bytes
1640 * @reply: point to the buffer to hold data returned for a reply
1641 * @reply_len: length of the reply buffer returned from GET
1642 *
1643 * Returns zero or a negative error code.
1644 */
01ef7dbf 1645static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1646 int mod_id, int src_id, int req, int dir, const void *data,
1647 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1648{
1649 int status = 0;
1650 struct scp_msg scp_send, scp_reply;
1651 unsigned int ret_bytes, send_size, ret_size;
1652 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1653 unsigned int reply_data_size;
1654
1655 memset(&scp_send, 0, sizeof(scp_send));
1656 memset(&scp_reply, 0, sizeof(scp_reply));
1657
1658 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1659 return -EINVAL;
1660
1661 if (dir == SCP_GET && reply == NULL) {
4e76a883 1662 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1663 return -EINVAL;
1664 }
1665
1666 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1667 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1668 return -EINVAL;
1669 }
1670
447fd8e9 1671 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1672 0, 0, 0, len/sizeof(unsigned int));
1673 if (data != NULL && len > 0) {
1674 len = min((unsigned int)(sizeof(scp_send.data)), len);
1675 memcpy(scp_send.data, data, len);
1676 }
1677
1678 ret_bytes = 0;
1679 send_size = sizeof(unsigned int) + len;
1680 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1681 send_size, (unsigned char *)&scp_reply,
1682 sizeof(scp_reply), &ret_bytes);
1683
1684 if (status < 0) {
4e76a883 1685 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1686 return status;
1687 }
1688
1689 /* extract send and reply headers members */
1690 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1691 NULL, NULL, NULL, NULL, NULL);
1692 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1693 &reply_resp_flag, &reply_error_flag,
1694 &reply_data_size);
1695
1696 if (!send_get_flag)
1697 return 0;
1698
1699 if (reply_resp_flag && !reply_error_flag) {
1700 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1701 / sizeof(unsigned int);
1702
1703 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1704 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1705 return -EINVAL;
1706 } else if (ret_size != reply_data_size) {
4e76a883 1707 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1708 return -EINVAL;
46a049da
AB		 1709 } else if (!reply) {
1710 codec_dbg(codec, "NULL reply\n");
1711 return -EINVAL;
01ef7dbf
IM		 1712 } else {
1713 *reply_len = ret_size*sizeof(unsigned int);
1714 memcpy(reply, scp_reply.data, *reply_len);
1715 }
1716 } else {
4e76a883 1717 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1718 return -EIO;
1719 }
1720
1721 return status;
1722}
1723
5aaca44d
IM		 1724/*
1725 * Set DSP parameters
1726 */
1727static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 1728 int src_id, int req, const void *data, unsigned int len)
5aaca44d 1729{
447fd8e9
CM		 1730 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1731 NULL);
5aaca44d
IM		 1732}
1733
1734static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 1735 int req, const unsigned int data)
5aaca44d 1736{
447fd8e9
CM		 1737 return dspio_set_param(codec, mod_id, 0x20, req, &data,
1738 sizeof(unsigned int));
1739}
1740
1741static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1742 int req, const unsigned int data)
1743{
1744 return dspio_set_param(codec, mod_id, 0x00, req, &data,
1745 sizeof(unsigned int));
5aaca44d
IM		 1746}
1747
d5c21b88
IM		 1748/*
1749 * Allocate a DSP DMA channel via an SCP message
1750 */
01ef7dbf
IM		 1751static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1752{
1753 int status = 0;
1754 unsigned int size = sizeof(dma_chan);
1755
4e76a883 1756 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 1757 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1758 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1759 dma_chan, &size);
01ef7dbf
IM		 1760
1761 if (status < 0) {
4e76a883 1762 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1763 return status;
1764 }
1765
1766 if ((*dma_chan + 1) == 0) {
4e76a883 1767 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1768 return -EBUSY;
1769 }
1770
4e76a883
TI		 1771 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1772 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1773
1774 return status;
1775}
1776
d5c21b88
IM		 1777/*
1778 * Free a DSP DMA via an SCP message
1779 */
01ef7dbf
IM		 1780static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1781{
1782 int status = 0;
1783 unsigned int dummy = 0;
1784
4e76a883
TI		 1785 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1786 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 1787
447fd8e9
CM		 1788 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1789 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1790 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 1791
1792 if (status < 0) {
4e76a883 1793 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1794 return status;
1795 }
1796
4e76a883 1797 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1798
1799 return status;
1800}
1801
1802/*
d5c21b88 1803 * (Re)start the DSP
01ef7dbf
IM		 1804 */
1805static int dsp_set_run_state(struct hda_codec *codec)
1806{
1807 unsigned int dbg_ctrl_reg;
1808 unsigned int halt_state;
1809 int err;
1810
1811 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1812 if (err < 0)
1813 return err;
1814
1815 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1816 DSP_DBGCNTL_STATE_LOBIT;
1817
1818 if (halt_state != 0) {
1819 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1820 DSP_DBGCNTL_SS_MASK);
1821 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1822 dbg_ctrl_reg);
1823 if (err < 0)
1824 return err;
1825
1826 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1827 DSP_DBGCNTL_EXEC_MASK;
1828 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1829 dbg_ctrl_reg);
1830 if (err < 0)
1831 return err;
1832 }
1833
1834 return 0;
1835}
1836
d5c21b88
IM		 1837/*
1838 * Reset the DSP
1839 */
01ef7dbf
IM		 1840static int dsp_reset(struct hda_codec *codec)
1841{
1842 unsigned int res;
1843 int retry = 20;
1844
4e76a883 1845 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1846 do {
1847 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1848 retry--;
1849 } while (res == -EIO && retry);
1850
1851 if (!retry) {
4e76a883 1852 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1853 return -EIO;
1854 }
1855
1856 return 0;
1857}
1858
d5c21b88
IM		 1859/*
1860 * Convert chip address to DSP address
1861 */
01ef7dbf
IM		 1862static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1863 bool *code, bool *yram)
1864{
1865 *code = *yram = false;
1866
1867 if (UC_RANGE(chip_addx, 1)) {
1868 *code = true;
1869 return UC_OFF(chip_addx);
1870 } else if (X_RANGE_ALL(chip_addx, 1)) {
1871 return X_OFF(chip_addx);
1872 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1873 *yram = true;
1874 return Y_OFF(chip_addx);
1875 }
1876
4a8b89f9 1877 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 1878}
1879
d5c21b88
IM		 1880/*
1881 * Check if the DSP DMA is active
1882 */
01ef7dbf
IM		 1883static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1884{
1885 unsigned int dma_chnlstart_reg;
1886
1887 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1888
1889 return ((dma_chnlstart_reg & (1 <<
1890 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1891}
1892
1893static int dsp_dma_setup_common(struct hda_codec *codec,
1894 unsigned int chip_addx,
1895 unsigned int dma_chan,
1896 unsigned int port_map_mask,
1897 bool ovly)
1898{
1899 int status = 0;
1900 unsigned int chnl_prop;
1901 unsigned int dsp_addx;
1902 unsigned int active;
1903 bool code, yram;
1904
4e76a883 1905 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 1906
1907 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 1908 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 1909 return -EINVAL;
1910 }
1911
1912 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 1913 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 1914 return -EBUSY;
1915 }
1916
1917 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1918
1919 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1920 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1921 return -ENXIO;
1922 }
1923
1924 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1925 active = 0;
1926
4e76a883 1927 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 1928
1929 if (ovly) {
1930 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1931 &chnl_prop);
1932
1933 if (status < 0) {
4e76a883 1934 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 1935 return status;
1936 }
4e76a883 1937 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 1938 }
1939
1940 if (!code)
1941 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1942 else
1943 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1944
1945 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1946
1947 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1948 if (status < 0) {
4e76a883 1949 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 1950 return status;
1951 }
4e76a883 1952 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 1953
1954 if (ovly) {
1955 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1956 &active);
1957
1958 if (status < 0) {
4e76a883 1959 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 1960 return status;
1961 }
4e76a883 1962 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 1963 }
1964
1965 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1966 DSPDMAC_ACTIVE_AAR_MASK;
1967
1968 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1969 if (status < 0) {
4e76a883 1970 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 1971 return status;
1972 }
1973
4e76a883 1974 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 1975
1976 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1977 port_map_mask);
1978 if (status < 0) {
4e76a883 1979 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 1980 return status;
1981 }
4e76a883 1982 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 1983
1984 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1985 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1986 if (status < 0) {
4e76a883 1987 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 1988 return status;
1989 }
4e76a883 1990 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 1991
4e76a883 1992 codec_dbg(codec,
01ef7dbf
IM		 1993 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1994 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1995 chip_addx, dsp_addx, dma_chan,
1996 port_map_mask, chnl_prop, active);
1997
4e76a883 1998 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 1999
2000 return 0;
2001}
2002
d5c21b88
IM		 2003/*
2004 * Setup the DSP DMA per-transfer-specific registers
2005 */
01ef7dbf
IM		 2006static int dsp_dma_setup(struct hda_codec *codec,
2007 unsigned int chip_addx,
2008 unsigned int count,
2009 unsigned int dma_chan)
2010{
2011 int status = 0;
2012 bool code, yram;
2013 unsigned int dsp_addx;
2014 unsigned int addr_field;
2015 unsigned int incr_field;
2016 unsigned int base_cnt;
2017 unsigned int cur_cnt;
2018 unsigned int dma_cfg = 0;
2019 unsigned int adr_ofs = 0;
2020 unsigned int xfr_cnt = 0;
2021 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2022 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2023
4e76a883 2024 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2025
2026 if (count > max_dma_count) {
4e76a883 2027 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2028 return -EINVAL;
2029 }
2030
2031 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2032 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2033 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2034 return -ENXIO;
2035 }
2036
4e76a883 2037 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2038
2039 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2040 incr_field = 0;
2041
2042 if (!code) {
2043 addr_field <<= 1;
2044 if (yram)
2045 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2046
2047 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2048 }
2049
2050 dma_cfg = addr_field + incr_field;
2051 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2052 dma_cfg);
2053 if (status < 0) {
4e76a883 2054 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2055 return status;
2056 }
4e76a883 2057 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2058
2059 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2060 (code ? 0 : 1));
2061
2062 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2063 adr_ofs);
2064 if (status < 0) {
4e76a883 2065 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2066 return status;
2067 }
4e76a883 2068 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2069
2070 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2071
2072 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2073
2074 xfr_cnt = base_cnt | cur_cnt;
2075
2076 status = chipio_write(codec,
2077 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2078 if (status < 0) {
4e76a883 2079 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2080 return status;
2081 }
4e76a883 2082 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2083
4e76a883 2084 codec_dbg(codec,
01ef7dbf
IM		 2085 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2086 "ADROFS=0x%x, XFRCNT=0x%x\n",
2087 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2088
4e76a883 2089 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2090
2091 return 0;
2092}
2093
d5c21b88
IM		 2094/*
2095 * Start the DSP DMA
2096 */
01ef7dbf
IM		 2097static int dsp_dma_start(struct hda_codec *codec,
2098 unsigned int dma_chan, bool ovly)
2099{
2100 unsigned int reg = 0;
2101 int status = 0;
2102
4e76a883 2103 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2104
2105 if (ovly) {
2106 status = chipio_read(codec,
2107 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2108
2109 if (status < 0) {
4e76a883 2110 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2111 return status;
2112 }
4e76a883 2113 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2114
2115 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2116 DSPDMAC_CHNLSTART_DIS_MASK);
2117 }
2118
2119 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2120 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2121 if (status < 0) {
4e76a883 2122 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2123 return status;
2124 }
4e76a883 2125 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2126
2127 return status;
2128}
2129
d5c21b88
IM		 2130/*
2131 * Stop the DSP DMA
2132 */
01ef7dbf
IM		 2133static int dsp_dma_stop(struct hda_codec *codec,
2134 unsigned int dma_chan, bool ovly)
2135{
2136 unsigned int reg = 0;
2137 int status = 0;
2138
4e76a883 2139 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2140
2141 if (ovly) {
2142 status = chipio_read(codec,
2143 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2144
2145 if (status < 0) {
4e76a883 2146 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2147 return status;
2148 }
4e76a883 2149 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2150 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2151 DSPDMAC_CHNLSTART_DIS_MASK);
2152 }
2153
2154 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2155 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2156 if (status < 0) {
4e76a883 2157 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2158 return status;
2159 }
4e76a883 2160 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2161
2162 return status;
2163}
2164
d5c21b88
IM		 2165/**
2166 * Allocate router ports
2167 *
2168 * @codec: the HDA codec
2169 * @num_chans: number of channels in the stream
2170 * @ports_per_channel: number of ports per channel
2171 * @start_device: start device
2172 * @port_map: pointer to the port list to hold the allocated ports
2173 *
2174 * Returns zero or a negative error code.
2175 */
01ef7dbf
IM		 2176static int dsp_allocate_router_ports(struct hda_codec *codec,
2177 unsigned int num_chans,
2178 unsigned int ports_per_channel,
2179 unsigned int start_device,
2180 unsigned int *port_map)
2181{
2182 int status = 0;
2183 int res;
2184 u8 val;
2185
2186 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2187 if (status < 0)
2188 return status;
2189
2190 val = start_device << 6;
2191 val |= (ports_per_channel - 1) << 4;
2192 val |= num_chans - 1;
2193
2194 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2195 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2196 val);
2197
2198 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2199 VENDOR_CHIPIO_PORT_ALLOC_SET,
2200 MEM_CONNID_DSP);
2201
2202 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2203 if (status < 0)
2204 return status;
2205
2206 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2207 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2208
2209 *port_map = res;
2210
2211 return (res < 0) ? res : 0;
2212}
2213
d5c21b88
IM		 2214/*
2215 * Free router ports
2216 */
01ef7dbf
IM		 2217static int dsp_free_router_ports(struct hda_codec *codec)
2218{
2219 int status = 0;
2220
2221 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2222 if (status < 0)
2223 return status;
2224
2225 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2226 VENDOR_CHIPIO_PORT_FREE_SET,
2227 MEM_CONNID_DSP);
2228
2229 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2230
2231 return status;
2232}
2233
d5c21b88
IM		 2234/*
2235 * Allocate DSP ports for the download stream
2236 */
01ef7dbf
IM		 2237static int dsp_allocate_ports(struct hda_codec *codec,
2238 unsigned int num_chans,
2239 unsigned int rate_multi, unsigned int *port_map)
2240{
2241 int status;
2242
4e76a883 2243 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2244
2245 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2246 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2247 return -EINVAL;
2248 }
2249
2250 status = dsp_allocate_router_ports(codec, num_chans,
2251 rate_multi, 0, port_map);
2252
4e76a883 2253 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2254
2255 return status;
2256}
2257
01ef7dbf
IM		 2258static int dsp_allocate_ports_format(struct hda_codec *codec,
2259 const unsigned short fmt,
2260 unsigned int *port_map)
2261{
2262 int status;
2263 unsigned int num_chans;
2264
2265 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2266 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2267 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2268
2269 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2270 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2271 return -EINVAL;
2272 }
2273
2274 num_chans = get_hdafmt_chs(fmt) + 1;
2275
2276 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2277
2278 return status;
2279}
2280
d5c21b88
IM		 2281/*
2282 * free DSP ports
2283 */
2284static int dsp_free_ports(struct hda_codec *codec)
2285{
2286 int status;
2287
4e76a883 2288 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2289
2290 status = dsp_free_router_ports(codec);
2291 if (status < 0) {
4e76a883 2292 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2293 return status;
2294 }
4e76a883 2295 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2296
2297 return status;
2298}
2299
01ef7dbf
IM		 2300/*
2301 * HDA DMA engine stuffs for DSP code download
2302 */
2303struct dma_engine {
2304 struct hda_codec *codec;
2305 unsigned short m_converter_format;
2306 struct snd_dma_buffer *dmab;
2307 unsigned int buf_size;
2308};
2309
2310
2311enum dma_state {
2312 DMA_STATE_STOP = 0,
2313 DMA_STATE_RUN = 1
2314};
2315
6194b99d 2316static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2317 unsigned int sample_rate,
2318 unsigned short channels,
01ef7dbf
IM		 2319 unsigned short *hda_format)
2320{
2321 unsigned int format_val;
2322
b7d023e1
TI		 2323 format_val = snd_hdac_calc_stream_format(sample_rate,
2324 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2325
2326 if (hda_format)
2327 *hda_format = (unsigned short)format_val;
2328
2329 return 0;
2330}
2331
d5c21b88
IM		 2332/*
2333 * Reset DMA for DSP download
2334 */
01ef7dbf
IM		 2335static int dma_reset(struct dma_engine *dma)
2336{
2337 struct hda_codec *codec = dma->codec;
2338 struct ca0132_spec *spec = codec->spec;
2339 int status;
2340
b3667bd7 2341 if (dma->dmab->area)
01ef7dbf
IM		 2342 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2343
2344 status = snd_hda_codec_load_dsp_prepare(codec,
2345 dma->m_converter_format,
2346 dma->buf_size,
2347 dma->dmab);
2348 if (status < 0)
2349 return status;
2350 spec->dsp_stream_id = status;
2351 return 0;
2352}
2353
2354static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2355{
01ef7dbf
IM		 2356 bool cmd;
2357
01ef7dbf
IM		 2358 switch (state) {
2359 case DMA_STATE_STOP:
2360 cmd = false;
2361 break;
2362 case DMA_STATE_RUN:
2363 cmd = true;
2364 break;
2365 default:
c41999a2
DH		 2366 return 0;
2367 }
01ef7dbf
IM		 2368
2369 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2370 return 0;
95c6e9cb
IM		 2371}
2372
01ef7dbf
IM		 2373static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2374{
2375 return dma->dmab->bytes;
2376}
95c6e9cb 2377
01ef7dbf
IM		 2378static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2379{
2380 return dma->dmab->area;
2381}
95c6e9cb 2382
01ef7dbf
IM		 2383static int dma_xfer(struct dma_engine *dma,
2384 const unsigned int *data,
2385 unsigned int count)
2386{
2387 memcpy(dma->dmab->area, data, count);
2388 return 0;
2389}
95c6e9cb 2390
01ef7dbf
IM		 2391static void dma_get_converter_format(
2392 struct dma_engine *dma,
2393 unsigned short *format)
2394{
2395 if (format)
2396 *format = dma->m_converter_format;
2397}
95c6e9cb 2398
01ef7dbf 2399static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2400{
01ef7dbf 2401 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2402
01ef7dbf 2403 return spec->dsp_stream_id;
95c6e9cb
IM		 2404}
2405
01ef7dbf
IM		 2406struct dsp_image_seg {
2407 u32 magic;
2408 u32 chip_addr;
2409 u32 count;
2410 u32 data[0];
2411};
2412
2413static const u32 g_magic_value = 0x4c46584d;
2414static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2415
2416static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2417{
01ef7dbf
IM		 2418 return p->magic == g_magic_value;
2419}
95c6e9cb 2420
01ef7dbf
IM		 2421static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2422{
2423 return g_chip_addr_magic_value == p->chip_addr;
2424}
95c6e9cb 2425
01ef7dbf
IM		 2426static bool is_last(const struct dsp_image_seg *p)
2427{
2428 return p->count == 0;
2429}
95c6e9cb 2430
01ef7dbf
IM		 2431static size_t dsp_sizeof(const struct dsp_image_seg *p)
2432{
2433 return sizeof(*p) + p->count*sizeof(u32);
2434}
2435
2436static const struct dsp_image_seg *get_next_seg_ptr(
2437 const struct dsp_image_seg *p)
2438{
2439 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2440}
2441
2442/*
01ef7dbf 2443 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2444 */
8ae3124b 2445#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2446
d5c21b88
IM		 2447/*
2448 * Program a list of address/data pairs via the ChipIO widget.
2449 * The segment data is in the format of successive pairs of words.
2450 * These are repeated as indicated by the segment's count field.
2451 */
01ef7dbf
IM		 2452static int dspxfr_hci_write(struct hda_codec *codec,
2453 const struct dsp_image_seg *fls)
95c6e9cb 2454{
01ef7dbf
IM		 2455 int status;
2456 const u32 *data;
2457 unsigned int count;
95c6e9cb 2458
01ef7dbf 2459 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2460 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2461 return -EINVAL;
95c6e9cb
IM		 2462 }
2463
01ef7dbf
IM		 2464 count = fls->count;
2465 data = (u32 *)(fls->data);
2466 while (count >= 2) {
2467 status = chipio_write(codec, data[0], data[1]);
2468 if (status < 0) {
4e76a883 2469 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2470 return status;
2471 }
2472 count -= 2;
2473 data += 2;
2474 }
2475 return 0;
95c6e9cb
IM		 2476}
2477
d5c21b88
IM		 2478/**
2479 * Write a block of data into DSP code or data RAM using pre-allocated
2480 * DMA engine.
2481 *
2482 * @codec: the HDA codec
2483 * @fls: pointer to a fast load image
2484 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2485 * no relocation
2486 * @dma_engine: pointer to DMA engine to be used for DSP download
2487 * @dma_chan: The number of DMA channels used for DSP download
2488 * @port_map_mask: port mapping
2489 * @ovly: TRUE if overlay format is required
2490 *
2491 * Returns zero or a negative error code.
2492 */
01ef7dbf
IM		 2493static int dspxfr_one_seg(struct hda_codec *codec,
2494 const struct dsp_image_seg *fls,
2495 unsigned int reloc,
2496 struct dma_engine *dma_engine,
2497 unsigned int dma_chan,
2498 unsigned int port_map_mask,
2499 bool ovly)
95c6e9cb 2500{
406261ce 2501 int status = 0;
01ef7dbf
IM		 2502 bool comm_dma_setup_done = false;
2503 const unsigned int *data;
2504 unsigned int chip_addx;
2505 unsigned int words_to_write;
2506 unsigned int buffer_size_words;
2507 unsigned char *buffer_addx;
2508 unsigned short hda_format;
2509 unsigned int sample_rate_div;
2510 unsigned int sample_rate_mul;
2511 unsigned int num_chans;
2512 unsigned int hda_frame_size_words;
2513 unsigned int remainder_words;
2514 const u32 *data_remainder;
2515 u32 chip_addx_remainder;
2516 unsigned int run_size_words;
2517 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2518 unsigned long timeout;
2519 bool dma_active;
01ef7dbf
IM		 2520
2521 if (fls == NULL)
2522 return -EINVAL;
2523 if (is_hci_prog_list_seg(fls)) {
2524 hci_write = fls;
2525 fls = get_next_seg_ptr(fls);
2526 }
95c6e9cb 2527
01ef7dbf 2528 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2529 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2530 return dspxfr_hci_write(codec, hci_write);
2531 }
95c6e9cb 2532
01ef7dbf 2533 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2534 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2535 return -EINVAL;
95c6e9cb
IM		 2536 }
2537
01ef7dbf
IM		 2538 data = fls->data;
2539 chip_addx = fls->chip_addr,
2540 words_to_write = fls->count;
2541
2542 if (!words_to_write)
2543 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2544 if (reloc)
2545 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2546
2547 if (!UC_RANGE(chip_addx, words_to_write) &&
2548 !X_RANGE_ALL(chip_addx, words_to_write) &&
2549 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2550 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2551 return -EINVAL;
95c6e9cb
IM		 2552 }
2553
01ef7dbf
IM		 2554 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2555 sizeof(u32);
2556
2557 buffer_addx = dma_get_buffer_addr(dma_engine);
2558
2559 if (buffer_addx == NULL) {
4e76a883 2560 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2561 return -EINVAL;
2562 }
2563
2564 dma_get_converter_format(dma_engine, &hda_format);
2565 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2566 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2567 num_chans = get_hdafmt_chs(hda_format) + 1;
2568
2569 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2570 (num_chans * sample_rate_mul / sample_rate_div));
2571
3bc085a1 2572 if (hda_frame_size_words == 0) {
4e76a883 2573 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2574 return -EINVAL;
2575 }
2576
01ef7dbf
IM		 2577 buffer_size_words = min(buffer_size_words,
2578 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2579 65536 : 32768));
2580 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2581 codec_dbg(codec,
01ef7dbf
IM		 2582 "chpadr=0x%08x frmsz=%u nchan=%u "
2583 "rate_mul=%u div=%u bufsz=%u\n",
2584 chip_addx, hda_frame_size_words, num_chans,
2585 sample_rate_mul, sample_rate_div, buffer_size_words);
2586
3bc085a1 2587 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2588 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2589 return -EINVAL;
2590 }
2591
2592 remainder_words = words_to_write % hda_frame_size_words;
2593 data_remainder = data;
2594 chip_addx_remainder = chip_addx;
2595
2596 data += remainder_words;
2597 chip_addx += remainder_words*sizeof(u32);
2598 words_to_write -= remainder_words;
2599
2600 while (words_to_write != 0) {
2601 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2602 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2603 words_to_write, run_size_words, remainder_words);
2604 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2605 if (!comm_dma_setup_done) {
2606 status = dsp_dma_stop(codec, dma_chan, ovly);
2607 if (status < 0)
425a7880 2608 return status;
01ef7dbf
IM		 2609 status = dsp_dma_setup_common(codec, chip_addx,
2610 dma_chan, port_map_mask, ovly);
2611 if (status < 0)
2612 return status;
2613 comm_dma_setup_done = true;
2614 }
2615
2616 status = dsp_dma_setup(codec, chip_addx,
2617 run_size_words, dma_chan);
2618 if (status < 0)
2619 return status;
2620 status = dsp_dma_start(codec, dma_chan, ovly);
2621 if (status < 0)
2622 return status;
2623 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2624 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2625 return -EIO;
2626 }
2627 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2628 if (status < 0)
2629 return status;
2630 if (remainder_words != 0) {
2631 status = chipio_write_multiple(codec,
2632 chip_addx_remainder,
2633 data_remainder,
2634 remainder_words);
b3667bd7
TI		 2635 if (status < 0)
2636 return status;
01ef7dbf
IM		 2637 remainder_words = 0;
2638 }
2639 if (hci_write) {
2640 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2641 if (status < 0)
2642 return status;
01ef7dbf
IM		 2643 hci_write = NULL;
2644 }
6d67530e
IM		 2645
2646 timeout = jiffies + msecs_to_jiffies(2000);
2647 do {
2648 dma_active = dsp_is_dma_active(codec, dma_chan);
2649 if (!dma_active)
01ef7dbf 2650 break;
6d67530e
IM		 2651 msleep(20);
2652 } while (time_before(jiffies, timeout));
2653 if (dma_active)
2654 break;
2655
4e76a883 2656 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2657 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2658 status = dma_reset(dma_engine);
01ef7dbf
IM		 2659
2660 if (status < 0)
2661 return status;
2662
2663 data += run_size_words;
2664 chip_addx += run_size_words*sizeof(u32);
2665 words_to_write -= run_size_words;
2666 }
2667
2668 if (remainder_words != 0) {
2669 status = chipio_write_multiple(codec, chip_addx_remainder,
2670 data_remainder, remainder_words);
2671 }
2672
2673 return status;
95c6e9cb
IM		 2674}
2675
d5c21b88
IM		 2676/**
2677 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2678 *
2679 * @codec: the HDA codec
2680 * @fls_data: pointer to a fast load image
2681 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2682 * no relocation
e97249dd 2683 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2684 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2685 * @ovly: TRUE if overlay format is required
2686 *
2687 * Returns zero or a negative error code.
2688 */
01ef7dbf
IM		 2689static int dspxfr_image(struct hda_codec *codec,
2690 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2691 unsigned int reloc,
2692 unsigned int sample_rate,
2693 unsigned short channels,
01ef7dbf 2694 bool ovly)
95c6e9cb
IM		 2695{
2696 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2697 int status;
2698 unsigned short hda_format = 0;
2699 unsigned int response;
2700 unsigned char stream_id = 0;
2701 struct dma_engine *dma_engine;
2702 unsigned int dma_chan;
2703 unsigned int port_map_mask;
2704
2705 if (fls_data == NULL)
2706 return -EINVAL;
2707
2708 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2709 if (!dma_engine)
2710 return -ENOMEM;
95c6e9cb 2711
01ef7dbf
IM		 2712 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2713 if (!dma_engine->dmab) {
549e8292
TI		 2714 kfree(dma_engine);
2715 return -ENOMEM;
01ef7dbf 2716 }
95c6e9cb 2717
01ef7dbf 2718 dma_engine->codec = codec;
6194b99d 2719 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2720 dma_engine->m_converter_format = hda_format;
2721 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2722 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2723
8ae3124b 2724 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2725
2726 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2727 hda_format, &response);
2728
2729 if (status < 0) {
4e76a883 2730 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2731 goto exit;
2732 }
2733
2734 status = snd_hda_codec_load_dsp_prepare(codec,
2735 dma_engine->m_converter_format,
2736 dma_engine->buf_size,
2737 dma_engine->dmab);
2738 if (status < 0)
95c6e9cb 2739 goto exit;
01ef7dbf
IM		 2740 spec->dsp_stream_id = status;
2741
2742 if (ovly) {
2743 status = dspio_alloc_dma_chan(codec, &dma_chan);
2744 if (status < 0) {
4e76a883 2745 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2746 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2747 goto exit;
2748 }
2749 }
95c6e9cb 2750
01ef7dbf
IM		 2751 port_map_mask = 0;
2752 status = dsp_allocate_ports_format(codec, hda_format,
2753 &port_map_mask);
2754 if (status < 0) {
4e76a883 2755 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2756 goto exit;
2757 }
2758
2759 stream_id = dma_get_stream_id(dma_engine);
2760 status = codec_set_converter_stream_channel(codec,
2761 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2762 if (status < 0) {
4e76a883 2763 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2764 goto exit;
2765 }
2766
2767 while ((fls_data != NULL) && !is_last(fls_data)) {
2768 if (!is_valid(fls_data)) {
4e76a883 2769 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2770 status = -EINVAL;
2771 goto exit;
2772 }
2773 status = dspxfr_one_seg(codec, fls_data, reloc,
2774 dma_engine, dma_chan,
2775 port_map_mask, ovly);
2776 if (status < 0)
2777 break;
2778
2779 if (is_hci_prog_list_seg(fls_data))
2780 fls_data = get_next_seg_ptr(fls_data);
2781
2782 if ((fls_data != NULL) && !is_last(fls_data))
2783 fls_data = get_next_seg_ptr(fls_data);
2784 }
2785
2786 if (port_map_mask != 0)
2787 status = dsp_free_ports(codec);
2788
2789 if (status < 0)
95c6e9cb
IM		 2790 goto exit;
2791
01ef7dbf
IM		 2792 status = codec_set_converter_stream_channel(codec,
2793 WIDGET_CHIP_CTRL, 0, 0, &response);
2794
95c6e9cb 2795exit:
01ef7dbf
IM		 2796 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2797 dspio_free_dma_chan(codec, dma_chan);
2798
b3667bd7 2799 if (dma_engine->dmab->area)
01ef7dbf
IM		 2800 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2801 kfree(dma_engine->dmab);
2802 kfree(dma_engine);
2803
2804 return status;
95c6e9cb
IM		 2805}
2806
2807/*
01ef7dbf 2808 * CA0132 DSP download stuffs.
95c6e9cb 2809 */
01ef7dbf 2810static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2811{
009b8f97 2812 struct ca0132_spec *spec = codec->spec;
4e76a883 2813 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 2814 if (!spec->use_alt_functions) {
2815 /*set DSP speaker to 2.0 configuration*/
2816 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2817 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2818
009b8f97
CM		 2819 /*update write pointer*/
2820 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2821 }
01ef7dbf 2822}
95c6e9cb 2823
d5c21b88 2824/**
e60b2c7f 2825 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2826 *
2827 * @codec: the HDA codec
2828 * @fls: pointer to a fast load image
2829 * @ovly: TRUE if overlay format is required
2830 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2831 * no relocation
2832 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2833 * @router_chans: number of audio router channels to be allocated (0 means use
2834 * internal defaults; max is 32)
2835 *
e60b2c7f
TI		 2836 * Download DSP from a DSP Image Fast Load structure. This structure is a
2837 * linear, non-constant sized element array of structures, each of which
2838 * contain the count of the data to be loaded, the data itself, and the
2839 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2840 * Returns zero or a negative error code.
2841 */
01ef7dbf
IM		 2842static int dspload_image(struct hda_codec *codec,
2843 const struct dsp_image_seg *fls,
2844 bool ovly,
2845 unsigned int reloc,
2846 bool autostart,
2847 int router_chans)
2848{
2849 int status = 0;
e97249dd
IM		 2850 unsigned int sample_rate;
2851 unsigned short channels;
01ef7dbf 2852
4e76a883 2853 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2854 if (router_chans == 0) {
2855 if (!ovly)
2856 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2857 else
2858 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2859 }
95c6e9cb 2860
e97249dd
IM		 2861 sample_rate = 48000;
2862 channels = (unsigned short)router_chans;
01ef7dbf 2863
e97249dd
IM		 2864 while (channels > 16) {
2865 sample_rate *= 2;
2866 channels /= 2;
01ef7dbf
IM		 2867 }
2868
01ef7dbf 2869 do {
4e76a883 2870 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 2871 if (!ovly)
2872 status = dsp_reset(codec);
2873
2874 if (status < 0)
2875 break;
2876
4e76a883 2877 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 2878 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2879 ovly);
01ef7dbf
IM		 2880
2881 if (status < 0)
2882 break;
2883
4e76a883 2884 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 2885 if (autostart && !ovly) {
2886 dspload_post_setup(codec);
2887 status = dsp_set_run_state(codec);
2888 }
2889
4e76a883 2890 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 2891 } while (0);
2892
2893 return status;
2894}
2895
f664417e 2896#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 2897static bool dspload_is_loaded(struct hda_codec *codec)
2898{
2899 unsigned int data = 0;
2900 int status = 0;
2901
2902 status = chipio_read(codec, 0x40004, &data);
2903 if ((status < 0) || (data != 1))
2904 return false;
2905
2906 return true;
2907}
f664417e
TI		 2908#else
2909#define dspload_is_loaded(codec) false
2910#endif
01ef7dbf
IM		 2911
2912static bool dspload_wait_loaded(struct hda_codec *codec)
2913{
6d67530e 2914 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 2915
2916 do {
01ef7dbf 2917 if (dspload_is_loaded(codec)) {
d9684bb5 2918 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 2919 return true;
2920 }
6d67530e
IM		 2921 msleep(20);
2922 } while (time_before(jiffies, timeout));
01ef7dbf 2923
d9684bb5 2924 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 2925 return false;
95c6e9cb
IM		 2926}
2927
e93ac30a
CM		 2928/*
2929 * Setup GPIO for the other variants of Core3D.
2930 */
2931
2932/*
2933 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
2934 * the card shows as having no GPIO pins.
2935 */
2936static void ca0132_gpio_init(struct hda_codec *codec)
2937{
2938 struct ca0132_spec *spec = codec->spec;
2939
2940 switch (spec->quirk) {
2941 case QUIRK_SBZ:
2942 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
2943 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
2944 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
2945 break;
2946 case QUIRK_R3DI:
2947 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
2948 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
2949 break;
2950 }
2951
2952}
2953
2954/* Sets the GPIO for audio output. */
2955static void ca0132_gpio_setup(struct hda_codec *codec)
2956{
2957 struct ca0132_spec *spec = codec->spec;
2958
2959 switch (spec->quirk) {
2960 case QUIRK_SBZ:
2961 snd_hda_codec_write(codec, 0x01, 0,
2962 AC_VERB_SET_GPIO_DIRECTION, 0x07);
2963 snd_hda_codec_write(codec, 0x01, 0,
2964 AC_VERB_SET_GPIO_MASK, 0x07);
2965 snd_hda_codec_write(codec, 0x01, 0,
2966 AC_VERB_SET_GPIO_DATA, 0x04);
2967 snd_hda_codec_write(codec, 0x01, 0,
2968 AC_VERB_SET_GPIO_DATA, 0x06);
2969 break;
2970 case QUIRK_R3DI:
2971 snd_hda_codec_write(codec, 0x01, 0,
2972 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
2973 snd_hda_codec_write(codec, 0x01, 0,
2974 AC_VERB_SET_GPIO_MASK, 0x1F);
2975 snd_hda_codec_write(codec, 0x01, 0,
2976 AC_VERB_SET_GPIO_DATA, 0x0C);
2977 break;
2978 }
2979}
2980
7e6ed62e
CM		 2981/*
2982 * GPIO control functions for the Recon3D integrated.
2983 */
2984
2985enum r3di_gpio_bit {
2986 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
2987 R3DI_MIC_SELECT_BIT = 1,
2988 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
2989 R3DI_OUT_SELECT_BIT = 2,
2990 /*
2991 * I dunno what this actually does, but it stays on until the dsp
2992 * is downloaded.
2993 */
2994 R3DI_GPIO_DSP_DOWNLOADING = 3,
2995 /*
2996 * Same as above, no clue what it does, but it comes on after the dsp
2997 * is downloaded.
2998 */
2999 R3DI_GPIO_DSP_DOWNLOADED = 4
3000};
3001
3002enum r3di_mic_select {
3003 /* Set GPIO bit 1 to 0 for rear mic */
3004 R3DI_REAR_MIC = 0,
3005 /* Set GPIO bit 1 to 1 for front microphone*/
3006 R3DI_FRONT_MIC = 1
3007};
3008
3009enum r3di_out_select {
3010 /* Set GPIO bit 2 to 0 for headphone */
3011 R3DI_HEADPHONE_OUT = 0,
3012 /* Set GPIO bit 2 to 1 for speaker */
3013 R3DI_LINE_OUT = 1
3014};
3015enum r3di_dsp_status {
3016 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3017 R3DI_DSP_DOWNLOADING = 0,
3018 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3019 R3DI_DSP_DOWNLOADED = 1
3020};
3021
7cb9d94c
CM		 3022
3023static void r3di_gpio_mic_set(struct hda_codec *codec,
3024 enum r3di_mic_select cur_mic)
3025{
3026 unsigned int cur_gpio;
3027
3028 /* Get the current GPIO Data setup */
3029 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3030
3031 switch (cur_mic) {
3032 case R3DI_REAR_MIC:
3033 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3034 break;
3035 case R3DI_FRONT_MIC:
3036 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3037 break;
3038 }
3039 snd_hda_codec_write(codec, codec->core.afg, 0,
3040 AC_VERB_SET_GPIO_DATA, cur_gpio);
3041}
3042
3043static void r3di_gpio_out_set(struct hda_codec *codec,
3044 enum r3di_out_select cur_out)
3045{
3046 unsigned int cur_gpio;
3047
3048 /* Get the current GPIO Data setup */
3049 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3050
3051 switch (cur_out) {
3052 case R3DI_HEADPHONE_OUT:
3053 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3054 break;
3055 case R3DI_LINE_OUT:
3056 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3057 break;
3058 }
3059 snd_hda_codec_write(codec, codec->core.afg, 0,
3060 AC_VERB_SET_GPIO_DATA, cur_gpio);
3061}
3062
7e6ed62e
CM		 3063static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3064 enum r3di_dsp_status dsp_status)
3065{
3066 unsigned int cur_gpio;
3067
3068 /* Get the current GPIO Data setup */
3069 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3070
3071 switch (dsp_status) {
3072 case R3DI_DSP_DOWNLOADING:
3073 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3074 snd_hda_codec_write(codec, codec->core.afg, 0,
3075 AC_VERB_SET_GPIO_DATA, cur_gpio);
3076 break;
3077 case R3DI_DSP_DOWNLOADED:
3078 /* Set DOWNLOADING bit to 0. */
3079 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3080
3081 snd_hda_codec_write(codec, codec->core.afg, 0,
3082 AC_VERB_SET_GPIO_DATA, cur_gpio);
3083
3084 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3085 break;
3086 }
3087
3088 snd_hda_codec_write(codec, codec->core.afg, 0,
3089 AC_VERB_SET_GPIO_DATA, cur_gpio);
3090}
3091
825315bc
IM		 3092/*
3093 * PCM callbacks
3094 */
95c6e9cb
IM		 3095static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3096 struct hda_codec *codec,
3097 unsigned int stream_tag,
3098 unsigned int format,
3099 struct snd_pcm_substream *substream)
3100{
3101 struct ca0132_spec *spec = codec->spec;
825315bc 3102
28fba950 3103 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3104
3105 return 0;
95c6e9cb
IM		 3106}
3107
3108static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3109 struct hda_codec *codec,
3110 struct snd_pcm_substream *substream)
3111{
3112 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3113
3114 if (spec->dsp_state == DSP_DOWNLOADING)
3115 return 0;
3116
3117 /*If Playback effects are on, allow stream some time to flush
3118 *effects tail*/
3119 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3120 msleep(50);
3121
28fba950 3122 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3123
3124 return 0;
95c6e9cb
IM		 3125}
3126
e8412ca4
DR		 3127static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3128 struct hda_codec *codec,
3129 struct snd_pcm_substream *substream)
3130{
3131 struct ca0132_spec *spec = codec->spec;
3132 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3133 struct snd_pcm_runtime *runtime = substream->runtime;
3134
3135 if (spec->dsp_state != DSP_DOWNLOADED)
3136 return 0;
3137
3138 /* Add latency if playback enhancement and either effect is enabled. */
3139 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3140 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3141 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3142 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3143 }
3144
3145 /* Applying Speaker EQ adds latency as well. */
3146 if (spec->cur_out_type == SPEAKER_OUT)
3147 latency += DSP_SPEAKER_OUT_LATENCY;
3148
3149 return (latency * runtime->rate) / 1000;
3150}
3151
95c6e9cb
IM		 3152/*
3153 * Digital out
3154 */
27ebeb0b
TI		 3155static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3156 struct hda_codec *codec,
3157 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3158{
3159 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3160 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3161}
3162
27ebeb0b 3163static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3164 struct hda_codec *codec,
3165 unsigned int stream_tag,
3166 unsigned int format,
3167 struct snd_pcm_substream *substream)
3168{
3169 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3170 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3171 stream_tag, format, substream);
95c6e9cb
IM		 3172}
3173
27ebeb0b 3174static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3175 struct hda_codec *codec,
95c6e9cb
IM		 3176 struct snd_pcm_substream *substream)
3177{
3178 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3179 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3180}
3181
27ebeb0b
TI		 3182static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3183 struct hda_codec *codec,
3184 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3185{
3186 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3187 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3188}
3189
825315bc
IM		 3190/*
3191 * Analog capture
3192 */
3193static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3194 struct hda_codec *codec,
3195 unsigned int stream_tag,
3196 unsigned int format,
3197 struct snd_pcm_substream *substream)
3198{
13c12dbe 3199 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3200 stream_tag, 0, format);
825315bc
IM		 3201
3202 return 0;
3203}
3204
3205static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3206 struct hda_codec *codec,
3207 struct snd_pcm_substream *substream)
3208{
3209 struct ca0132_spec *spec = codec->spec;
3210
3211 if (spec->dsp_state == DSP_DOWNLOADING)
3212 return 0;
3213
28fba950 3214 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3215 return 0;
3216}
3217
e8412ca4
DR		 3218static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3219 struct hda_codec *codec,
3220 struct snd_pcm_substream *substream)
3221{
3222 struct ca0132_spec *spec = codec->spec;
3223 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3224 struct snd_pcm_runtime *runtime = substream->runtime;
3225
3226 if (spec->dsp_state != DSP_DOWNLOADED)
3227 return 0;
3228
3229 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3230 latency += DSP_CRYSTAL_VOICE_LATENCY;
3231
3232 return (latency * runtime->rate) / 1000;
3233}
3234
e90f29e4
IM		 3235/*
3236 * Controls stuffs.
3237 */
3238
3239/*
3240 * Mixer controls helpers.
3241 */
3242#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3243 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3244 .name = xname, \
3245 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3246 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3247 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3248 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3249 .info = ca0132_volume_info, \
3250 .get = ca0132_volume_get, \
3251 .put = ca0132_volume_put, \
3252 .tlv = { .c = ca0132_volume_tlv }, \
3253 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3254
3255#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3256 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3257 .name = xname, \
3258 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3259 .info = snd_hda_mixer_amp_switch_info, \
3260 .get = ca0132_switch_get, \
3261 .put = ca0132_switch_put, \
3262 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3263
3264/* stereo */
3265#define CA0132_CODEC_VOL(xname, nid, dir) \
3266 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3267#define CA0132_CODEC_MUTE(xname, nid, dir) \
3268 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3269
4091fb95 3270/* The following are for tuning of products */
44f0c978
IM		 3271#ifdef ENABLE_TUNING_CONTROLS
3272
3273static unsigned int voice_focus_vals_lookup[] = {
32740x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
32750x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
32760x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
32770x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
32780x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
32790x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
32800x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
32810x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
32820x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
32830x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
32840x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
32850x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
32860x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
32870x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
32880x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
32890x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
32900x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
32910x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
32920x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
32930x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
32940x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
32950x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
32960x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
32970x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
32980x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
32990x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
33000x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3301};
3302
3303static unsigned int mic_svm_vals_lookup[] = {
33040x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
33050x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
33060x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
33070x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
33080x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
33090x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
33100x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
33110x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
33120x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
33130x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
33140x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
33150x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
33160x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
33170x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
33180x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
33190x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
33200x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3321};
3322
3323static unsigned int equalizer_vals_lookup[] = {
33240xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
33250xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
33260xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
33270xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
33280x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
33290x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
33300x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
33310x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
33320x41C00000
3333};
3334
3335static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3336 unsigned int *lookup, int idx)
3337{
3338 int i = 0;
3339
3340 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3341 if (nid == ca0132_tuning_ctls[i].nid)
3342 break;
3343
3344 snd_hda_power_up(codec);
447fd8e9 3345 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3346 ca0132_tuning_ctls[i].req,
3347 &(lookup[idx]), sizeof(unsigned int));
3348 snd_hda_power_down(codec);
3349
3350 return 1;
3351}
3352
3353static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3354 struct snd_ctl_elem_value *ucontrol)
3355{
3356 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3357 struct ca0132_spec *spec = codec->spec;
3358 hda_nid_t nid = get_amp_nid(kcontrol);
3359 long *valp = ucontrol->value.integer.value;
3360 int idx = nid - TUNING_CTL_START_NID;
3361
3362 *valp = spec->cur_ctl_vals[idx];
3363 return 0;
3364}
3365
3366static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3367 struct snd_ctl_elem_info *uinfo)
3368{
3369 int chs = get_amp_channels(kcontrol);
3370 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3371 uinfo->count = chs == 3 ? 2 : 1;
3372 uinfo->value.integer.min = 20;
3373 uinfo->value.integer.max = 180;
3374 uinfo->value.integer.step = 1;
3375
3376 return 0;
3377}
3378
3379static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3380 struct snd_ctl_elem_value *ucontrol)
3381{
3382 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3383 struct ca0132_spec *spec = codec->spec;
3384 hda_nid_t nid = get_amp_nid(kcontrol);
3385 long *valp = ucontrol->value.integer.value;
3386 int idx;
3387
3388 idx = nid - TUNING_CTL_START_NID;
3389 /* any change? */
3390 if (spec->cur_ctl_vals[idx] == *valp)
3391 return 0;
3392
3393 spec->cur_ctl_vals[idx] = *valp;
3394
3395 idx = *valp - 20;
3396 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3397
3398 return 1;
3399}
3400
3401static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3402 struct snd_ctl_elem_info *uinfo)
3403{
3404 int chs = get_amp_channels(kcontrol);
3405 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3406 uinfo->count = chs == 3 ? 2 : 1;
3407 uinfo->value.integer.min = 0;
3408 uinfo->value.integer.max = 100;
3409 uinfo->value.integer.step = 1;
3410
3411 return 0;
3412}
3413
3414static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3415 struct snd_ctl_elem_value *ucontrol)
3416{
3417 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3418 struct ca0132_spec *spec = codec->spec;
3419 hda_nid_t nid = get_amp_nid(kcontrol);
3420 long *valp = ucontrol->value.integer.value;
3421 int idx;
3422
3423 idx = nid - TUNING_CTL_START_NID;
3424 /* any change? */
3425 if (spec->cur_ctl_vals[idx] == *valp)
3426 return 0;
3427
3428 spec->cur_ctl_vals[idx] = *valp;
3429
3430 idx = *valp;
3431 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3432
3433 return 0;
3434}
3435
3436static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3437 struct snd_ctl_elem_info *uinfo)
3438{
3439 int chs = get_amp_channels(kcontrol);
3440 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3441 uinfo->count = chs == 3 ? 2 : 1;
3442 uinfo->value.integer.min = 0;
3443 uinfo->value.integer.max = 48;
3444 uinfo->value.integer.step = 1;
3445
3446 return 0;
3447}
3448
3449static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3450 struct snd_ctl_elem_value *ucontrol)
3451{
3452 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3453 struct ca0132_spec *spec = codec->spec;
3454 hda_nid_t nid = get_amp_nid(kcontrol);
3455 long *valp = ucontrol->value.integer.value;
3456 int idx;
3457
3458 idx = nid - TUNING_CTL_START_NID;
3459 /* any change? */
3460 if (spec->cur_ctl_vals[idx] == *valp)
3461 return 0;
3462
3463 spec->cur_ctl_vals[idx] = *valp;
3464
3465 idx = *valp;
3466 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3467
3468 return 1;
3469}
3470
8e142e9e
TS		 3471static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3472static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3473
3474static int add_tuning_control(struct hda_codec *codec,
3475 hda_nid_t pnid, hda_nid_t nid,
3476 const char *name, int dir)
3477{
975cc02a 3478 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3479 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3480 struct snd_kcontrol_new knew =
3481 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3482
3483 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3484 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3485 knew.tlv.c = 0;
3486 knew.tlv.p = 0;
3487 switch (pnid) {
3488 case VOICE_FOCUS:
3489 knew.info = voice_focus_ctl_info;
3490 knew.get = tuning_ctl_get;
3491 knew.put = voice_focus_ctl_put;
3492 knew.tlv.p = voice_focus_db_scale;
3493 break;
3494 case MIC_SVM:
3495 knew.info = mic_svm_ctl_info;
3496 knew.get = tuning_ctl_get;
3497 knew.put = mic_svm_ctl_put;
3498 break;
3499 case EQUALIZER:
3500 knew.info = equalizer_ctl_info;
3501 knew.get = tuning_ctl_get;
3502 knew.put = equalizer_ctl_put;
3503 knew.tlv.p = eq_db_scale;
3504 break;
3505 default:
3506 return 0;
3507 }
3508 knew.private_value =
3509 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3510 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3511 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3512}
3513
3514static int add_tuning_ctls(struct hda_codec *codec)
3515{
3516 int i;
3517 int err;
3518
3519 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3520 err = add_tuning_control(codec,
3521 ca0132_tuning_ctls[i].parent_nid,
3522 ca0132_tuning_ctls[i].nid,
3523 ca0132_tuning_ctls[i].name,
3524 ca0132_tuning_ctls[i].direct);
3525 if (err < 0)
3526 return err;
3527 }
3528
3529 return 0;
3530}
3531
3532static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3533{
3534 struct ca0132_spec *spec = codec->spec;
3535 int i;
3536
3537 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3538 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3539 /* SVM level defaults to 0.74. */
3540 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3541
3542 /* EQ defaults to 0dB. */
3543 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3544 spec->cur_ctl_vals[i] = 24;
3545}
3546#endif /*ENABLE_TUNING_CONTROLS*/
3547
5aaca44d
IM		 3548/*
3549 * Select the active output.
3550 * If autodetect is enabled, output will be selected based on jack detection.
3551 * If jack inserted, headphone will be selected, else built-in speakers
3552 * If autodetect is disabled, output will be selected based on selection.
3553 */
3554static int ca0132_select_out(struct hda_codec *codec)
3555{
3556 struct ca0132_spec *spec = codec->spec;
3557 unsigned int pin_ctl;
3558 int jack_present;
3559 int auto_jack;
3560 unsigned int tmp;
3561 int err;
3562
4e76a883 3563 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3564
664c7155 3565 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3566
3567 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3568
3569 if (auto_jack)
fe14f39e 3570 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3571 else
3572 jack_present =
3573 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3574
3575 if (jack_present)
3576 spec->cur_out_type = HEADPHONE_OUT;
3577 else
3578 spec->cur_out_type = SPEAKER_OUT;
3579
3580 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3581 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3582 /*speaker out config*/
3583 tmp = FLOAT_ONE;
3584 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3585 if (err < 0)
3586 goto exit;
3587 /*enable speaker EQ*/
3588 tmp = FLOAT_ONE;
3589 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3590 if (err < 0)
3591 goto exit;
3592
3593 /* Setup EAPD */
3594 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3595 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3596 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3597 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3598 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3599 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3600 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3601 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3602
3603 /* disable headphone node */
3604 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3605 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3606 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3607 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3608 /* enable speaker node */
3609 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 3610 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3611 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3612 pin_ctl | PIN_OUT);
5aaca44d 3613 } else {
4e76a883 3614 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3615 /*headphone out config*/
3616 tmp = FLOAT_ZERO;
3617 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3618 if (err < 0)
3619 goto exit;
3620 /*disable speaker EQ*/
3621 tmp = FLOAT_ZERO;
3622 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3623 if (err < 0)
3624 goto exit;
3625
3626 /* Setup EAPD */
3627 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3628 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3629 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3630 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3631 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3632 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3633 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3634 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3635
3636 /* disable speaker*/
3637 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3638 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3639 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3640 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3641 /* enable headphone*/
3642 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3643 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3644 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3645 pin_ctl | PIN_HP);
5aaca44d
IM		 3646 }
3647
3648exit:
664c7155 3649 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3650
3651 return err < 0 ? err : 0;
3652}
3653
7cb9d94c
CM		 3654/*
3655 * This function behaves similarly to the ca0132_select_out funciton above,
3656 * except with a few differences. It adds the ability to select the current
3657 * output with an enumerated control "output source" if the auto detect
3658 * mute switch is set to off. If the auto detect mute switch is enabled, it
3659 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3660 * It also adds the ability to auto-detect the front headphone port. The only
3661 * way to select surround is to disable auto detect, and set Surround with the
3662 * enumerated control.
3663 */
3664static int ca0132_alt_select_out(struct hda_codec *codec)
3665{
3666 struct ca0132_spec *spec = codec->spec;
3667 unsigned int pin_ctl;
3668 int jack_present;
3669 int auto_jack;
3670 unsigned int i;
3671 unsigned int tmp;
3672 int err;
3673 /* Default Headphone is rear headphone */
3674 hda_nid_t headphone_nid = spec->out_pins[1];
3675
3676 codec_dbg(codec, "%s\n", __func__);
3677
3678 snd_hda_power_up_pm(codec);
3679
3680 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3681
3682 /*
3683 * If headphone rear or front is plugged in, set to headphone.
3684 * If neither is plugged in, set to rear line out. Only if
3685 * hp/speaker auto detect is enabled.
3686 */
3687 if (auto_jack) {
3688 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3689 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3690
3691 if (jack_present)
3692 spec->cur_out_type = HEADPHONE_OUT;
3693 else
3694 spec->cur_out_type = SPEAKER_OUT;
3695 } else
3696 spec->cur_out_type = spec->out_enum_val;
3697
3698 /* Begin DSP output switch */
3699 tmp = FLOAT_ONE;
3700 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3701 if (err < 0)
3702 goto exit;
3703
3704 switch (spec->cur_out_type) {
3705 case SPEAKER_OUT:
3706 codec_dbg(codec, "%s speaker\n", __func__);
3707 /*speaker out config*/
3708 switch (spec->quirk) {
3709 case QUIRK_SBZ:
3710 writew(0x0007, spec->mem_base + 0x320);
3711 writew(0x0104, spec->mem_base + 0x320);
3712 writew(0x0101, spec->mem_base + 0x320);
3713 chipio_set_control_param(codec, 0x0D, 0x18);
3714 break;
3715 case QUIRK_R3DI:
3716 chipio_set_control_param(codec, 0x0D, 0x24);
3717 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3718 break;
3719 }
3720
3721 /* disable headphone node */
3722 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3723 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3724 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3725 pin_ctl & ~PIN_HP);
3726 /* enable line-out node */
3727 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3728 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3729 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3730 pin_ctl | PIN_OUT);
3731 /* Enable EAPD */
3732 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3733 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
3734
3735 /* If PlayEnhancement is enabled, set different source */
3736 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3737 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
3738 else
3739 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
3740 break;
3741 case HEADPHONE_OUT:
3742 codec_dbg(codec, "%s hp\n", __func__);
3743 /* Headphone out config*/
3744 switch (spec->quirk) {
3745 case QUIRK_SBZ:
3746 writew(0x0107, spec->mem_base + 0x320);
3747 writew(0x0104, spec->mem_base + 0x320);
3748 writew(0x0001, spec->mem_base + 0x320);
3749 chipio_set_control_param(codec, 0x0D, 0x12);
3750 break;
3751 case QUIRK_R3DI:
3752 chipio_set_control_param(codec, 0x0D, 0x21);
3753 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
3754 break;
3755 }
3756
3757 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3758 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3759
3760 /* disable speaker*/
3761 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3762 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3763 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3764 pin_ctl & ~PIN_HP);
3765
3766 /* enable headphone, either front or rear */
3767
3768 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
3769 headphone_nid = spec->out_pins[2];
3770 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
3771 headphone_nid = spec->out_pins[1];
3772
3773 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
3774 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3775 snd_hda_set_pin_ctl(codec, headphone_nid,
3776 pin_ctl | PIN_HP);
3777
3778 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3779 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
3780 else
3781 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
3782 break;
3783 case SURROUND_OUT:
3784 codec_dbg(codec, "%s surround\n", __func__);
3785 /* Surround out config*/
3786 switch (spec->quirk) {
3787 case QUIRK_SBZ:
3788 writew(0x0007, spec->mem_base + 0x320);
3789 writew(0x0104, spec->mem_base + 0x320);
3790 writew(0x0101, spec->mem_base + 0x320);
3791 chipio_set_control_param(codec, 0x0D, 0x18);
3792 break;
3793 case QUIRK_R3DI:
3794 chipio_set_control_param(codec, 0x0D, 0x24);
3795 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3796 break;
3797 }
3798 /* enable line out node */
3799 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3800 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3801 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3802 pin_ctl | PIN_OUT);
3803 /* Disable headphone out */
3804 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3805 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3806 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3807 pin_ctl & ~PIN_HP);
3808 /* Enable EAPD on line out */
3809 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3810 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
3811 /* enable center/lfe out node */
3812 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
3813 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3814 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
3815 pin_ctl | PIN_OUT);
3816 /* Now set rear surround node as out. */
3817 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
3818 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3819 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
3820 pin_ctl | PIN_OUT);
3821
3822 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3823 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
3824 else
3825 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
3826 break;
3827 }
3828
3829 /* run through the output dsp commands for line-out */
3830 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
3831 err = dspio_set_uint_param(codec,
3832 alt_out_presets[spec->cur_out_type].mids[i],
3833 alt_out_presets[spec->cur_out_type].reqs[i],
3834 alt_out_presets[spec->cur_out_type].vals[i]);
3835
3836 if (err < 0)
3837 goto exit;
3838 }
3839
3840exit:
3841 snd_hda_power_down_pm(codec);
3842
3843 return err < 0 ? err : 0;
3844}
3845
993884f6
CCC		 3846static void ca0132_unsol_hp_delayed(struct work_struct *work)
3847{
3848 struct ca0132_spec *spec = container_of(
3849 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 3850 struct hda_jack_tbl *jack;
3851
7cb9d94c
CM		 3852 if (spec->use_alt_functions)
3853 ca0132_alt_select_out(spec->codec);
3854 else
3855 ca0132_select_out(spec->codec);
3856
d5c016b5 3857 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 3858 if (jack) {
3859 jack->block_report = 0;
3860 snd_hda_jack_report_sync(spec->codec);
3861 }
993884f6
CCC		 3862}
3863
5aaca44d
IM		 3864static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3865static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3866static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3867
3868/*
3869 * Select the active VIP source
3870 */
3871static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3872{
3873 struct ca0132_spec *spec = codec->spec;
3874 unsigned int tmp;
3875
e8f1bd5d 3876 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 3877 return 0;
3878
3879 /* if CrystalVoice if off, vipsource should be 0 */
3880 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3881 (val == 0)) {
3882 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3883 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3884 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3885 if (spec->cur_mic_type == DIGITAL_MIC)
3886 tmp = FLOAT_TWO;
3887 else
3888 tmp = FLOAT_ONE;
3889 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3890 tmp = FLOAT_ZERO;
3891 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3892 } else {
3893 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3894 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3895 if (spec->cur_mic_type == DIGITAL_MIC)
3896 tmp = FLOAT_TWO;
3897 else
3898 tmp = FLOAT_ONE;
3899 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3900 tmp = FLOAT_ONE;
3901 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3902 msleep(20);
3903 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3904 }
3905
3906 return 1;
3907}
3908
3909/*
3910 * Select the active microphone.
3911 * If autodetect is enabled, mic will be selected based on jack detection.
3912 * If jack inserted, ext.mic will be selected, else built-in mic
3913 * If autodetect is disabled, mic will be selected based on selection.
3914 */
3915static int ca0132_select_mic(struct hda_codec *codec)
3916{
3917 struct ca0132_spec *spec = codec->spec;
3918 int jack_present;
3919 int auto_jack;
3920
4e76a883 3921 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 3922
664c7155 3923 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3924
3925 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3926
3927 if (auto_jack)
fe14f39e 3928 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 3929 else
3930 jack_present =
3931 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3932
3933 if (jack_present)
3934 spec->cur_mic_type = LINE_MIC_IN;
3935 else
3936 spec->cur_mic_type = DIGITAL_MIC;
3937
3938 if (spec->cur_mic_type == DIGITAL_MIC) {
3939 /* enable digital Mic */
3940 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3941 ca0132_set_dmic(codec, 1);
3942 ca0132_mic_boost_set(codec, 0);
3943 /* set voice focus */
3944 ca0132_effects_set(codec, VOICE_FOCUS,
3945 spec->effects_switch
3946 [VOICE_FOCUS - EFFECT_START_NID]);
3947 } else {
3948 /* disable digital Mic */
3949 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3950 ca0132_set_dmic(codec, 0);
3951 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3952 /* disable voice focus */
3953 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3954 }
3955
664c7155 3956 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3957
3958 return 0;
3959}
3960
7cb9d94c
CM		 3961/*
3962 * Select the active input.
3963 * Mic detection isn't used, because it's kind of pointless on the SBZ.
3964 * The front mic has no jack-detection, so the only way to switch to it
3965 * is to do it manually in alsamixer.
3966 */
3967static int ca0132_alt_select_in(struct hda_codec *codec)
3968{
3969 struct ca0132_spec *spec = codec->spec;
3970 unsigned int tmp;
3971
3972 codec_dbg(codec, "%s\n", __func__);
3973
3974 snd_hda_power_up_pm(codec);
3975
3976 chipio_set_stream_control(codec, 0x03, 0);
3977 chipio_set_stream_control(codec, 0x04, 0);
3978
3979 spec->cur_mic_type = spec->in_enum_val;
3980
3981 switch (spec->cur_mic_type) {
3982 case REAR_MIC:
3983 switch (spec->quirk) {
3984 case QUIRK_SBZ:
3985 writew(0x0000, spec->mem_base + 0x320);
3986 tmp = FLOAT_THREE;
3987 break;
3988 case QUIRK_R3DI:
3989 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
3990 tmp = FLOAT_ONE;
3991 break;
3992 default:
3993 tmp = FLOAT_ONE;
3994 break;
3995 }
3996
3997 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3998 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3999 if (spec->quirk == QUIRK_R3DI)
4000 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4001
4002 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4003
4004 chipio_set_stream_control(codec, 0x03, 1);
4005 chipio_set_stream_control(codec, 0x04, 1);
4006
4007 if (spec->quirk == QUIRK_SBZ) {
4008 chipio_write(codec, 0x18B098, 0x0000000C);
4009 chipio_write(codec, 0x18B09C, 0x0000000C);
4010 }
4011 break;
4012 case REAR_LINE_IN:
4013 ca0132_mic_boost_set(codec, 0);
4014 switch (spec->quirk) {
4015 case QUIRK_SBZ:
4016 writew(0x0000, spec->mem_base + 0x320);
4017 break;
4018 case QUIRK_R3DI:
4019 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4020 break;
4021 }
4022
4023 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4024 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4025 if (spec->quirk == QUIRK_R3DI)
4026 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4027
4028 tmp = FLOAT_ZERO;
4029 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4030
4031 if (spec->quirk == QUIRK_SBZ) {
4032 chipio_write(codec, 0x18B098, 0x00000000);
4033 chipio_write(codec, 0x18B09C, 0x00000000);
4034 }
4035
4036 chipio_set_stream_control(codec, 0x03, 1);
4037 chipio_set_stream_control(codec, 0x04, 1);
4038 break;
4039 case FRONT_MIC:
4040 switch (spec->quirk) {
4041 case QUIRK_SBZ:
4042 writew(0x0100, spec->mem_base + 0x320);
4043 writew(0x0005, spec->mem_base + 0x320);
4044 tmp = FLOAT_THREE;
4045 break;
4046 case QUIRK_R3DI:
4047 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4048 tmp = FLOAT_ONE;
4049 break;
4050 default:
4051 tmp = FLOAT_ONE;
4052 break;
4053 }
4054
4055 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4056 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4057 if (spec->quirk == QUIRK_R3DI)
4058 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4059
4060 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4061
4062 chipio_set_stream_control(codec, 0x03, 1);
4063 chipio_set_stream_control(codec, 0x04, 1);
4064
4065 if (spec->quirk == QUIRK_SBZ) {
4066 chipio_write(codec, 0x18B098, 0x0000000C);
4067 chipio_write(codec, 0x18B09C, 0x000000CC);
4068 }
4069 break;
4070 }
4071
4072 snd_hda_power_down_pm(codec);
4073 return 0;
4074
4075}
4076
a7e76271
IM		 4077/*
4078 * Check if VNODE settings take effect immediately.
4079 */
4080static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4081 hda_nid_t vnid,
4082 hda_nid_t *shared_nid)
4083{
4084 struct ca0132_spec *spec = codec->spec;
4085 hda_nid_t nid;
a7e76271
IM		 4086
4087 switch (vnid) {
4088 case VNID_SPK:
4089 nid = spec->shared_out_nid;
a7e76271
IM		 4090 break;
4091 case VNID_MIC:
4092 nid = spec->shared_mic_nid;
a7e76271
IM		 4093 break;
4094 default:
9a0869f4 4095 return false;
a7e76271
IM		 4096 }
4097
9a0869f4 4098 if (shared_nid)
a7e76271
IM		 4099 *shared_nid = nid;
4100
9a0869f4 4101 return true;
a7e76271
IM		 4102}
4103
4104/*
4105* The following functions are control change helpers.
4106* They return 0 if no changed. Return 1 if changed.
4107*/
4108static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4109{
4110 struct ca0132_spec *spec = codec->spec;
4111 unsigned int tmp;
4112
4113 /* based on CrystalVoice state to enable VoiceFX. */
4114 if (enable) {
4115 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4116 FLOAT_ONE : FLOAT_ZERO;
4117 } else {
4118 tmp = FLOAT_ZERO;
4119 }
4120
4121 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4122 ca0132_voicefx.reqs[0], tmp);
4123
4124 return 1;
4125}
4126
5aaca44d
IM		 4127/*
4128 * Set the effects parameters
4129 */
4130static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4131{
4132 struct ca0132_spec *spec = codec->spec;
009b8f97 4133 unsigned int on, tmp;
5aaca44d
IM		 4134 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4135 int err = 0;
4136 int idx = nid - EFFECT_START_NID;
4137
4138 if ((idx < 0) || (idx >= num_fx))
4139 return 0; /* no changed */
4140
4141 /* for out effect, qualify with PE */
4142 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4143 /* if PE if off, turn off out effects. */
4144 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4145 val = 0;
4146 }
4147
4148 /* for in effect, qualify with CrystalVoice */
4149 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4150 /* if CrystalVoice if off, turn off in effects. */
4151 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4152 val = 0;
4153
4154 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4155 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4156 val = 0;
009b8f97
CM		 4157
4158 /* If Voice Focus on SBZ, set to two channel. */
7cb9d94c
CM		 4159 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4160 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4161 if (spec->effects_switch[CRYSTAL_VOICE -
4162 EFFECT_START_NID]) {
4163
4164 if (spec->effects_switch[VOICE_FOCUS -
4165 EFFECT_START_NID]) {
4166 tmp = FLOAT_TWO;
4167 val = 1;
4168 } else
4169 tmp = FLOAT_ONE;
4170
4171 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4172 }
4173 }
4174 /*
4175 * For SBZ noise reduction, there's an extra command
4176 * to module ID 0x47. No clue why.
4177 */
7cb9d94c
CM		 4178 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4179 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4180 if (spec->effects_switch[CRYSTAL_VOICE -
4181 EFFECT_START_NID]) {
4182 if (spec->effects_switch[NOISE_REDUCTION -
4183 EFFECT_START_NID])
4184 tmp = FLOAT_ONE;
4185 else
4186 tmp = FLOAT_ZERO;
4187 } else
4188 tmp = FLOAT_ZERO;
4189
4190 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4191 }
7cb9d94c
CM		 4192
4193 /* If rear line in disable effects. */
4194 if (spec->use_alt_functions &&
4195 spec->in_enum_val == REAR_LINE_IN)
4196 val = 0;
5aaca44d
IM		 4197 }
4198
4e76a883 4199 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4200 nid, val);
4201
4202 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4203 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4204 ca0132_effects[idx].reqs[0], on);
4205
4206 if (err < 0)
4207 return 0; /* no changed */
4208
4209 return 1;
4210}
4211
a7e76271
IM		 4212/*
4213 * Turn on/off Playback Enhancements
4214 */
4215static int ca0132_pe_switch_set(struct hda_codec *codec)
4216{
4217 struct ca0132_spec *spec = codec->spec;
4218 hda_nid_t nid;
4219 int i, ret = 0;
4220
4e76a883 4221 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4222 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4223
7cb9d94c
CM		 4224 if (spec->use_alt_functions)
4225 ca0132_alt_select_out(codec);
4226
a7e76271
IM		 4227 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4228 nid = OUT_EFFECT_START_NID;
4229 /* PE affects all out effects */
4230 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4231 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4232
4233 return ret;
4234}
4235
5aaca44d
IM		 4236/* Check if Mic1 is streaming, if so, stop streaming */
4237static int stop_mic1(struct hda_codec *codec)
4238{
4239 struct ca0132_spec *spec = codec->spec;
4240 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4241 AC_VERB_GET_CONV, 0);
4242 if (oldval != 0)
4243 snd_hda_codec_write(codec, spec->adcs[0], 0,
4244 AC_VERB_SET_CHANNEL_STREAMID,
4245 0);
4246 return oldval;
4247}
4248
4249/* Resume Mic1 streaming if it was stopped. */
4250static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4251{
4252 struct ca0132_spec *spec = codec->spec;
4253 /* Restore the previous stream and channel */
4254 if (oldval != 0)
4255 snd_hda_codec_write(codec, spec->adcs[0], 0,
4256 AC_VERB_SET_CHANNEL_STREAMID,
4257 oldval);
4258}
4259
4260/*
a7e76271 4261 * Turn on/off CrystalVoice
5aaca44d 4262 */
a7e76271
IM		 4263static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4264{
4265 struct ca0132_spec *spec = codec->spec;
4266 hda_nid_t nid;
4267 int i, ret = 0;
4268 unsigned int oldval;
4269
4e76a883 4270 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4271 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4272
4273 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4274 nid = IN_EFFECT_START_NID;
4275 /* CrystalVoice affects all in effects */
4276 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4277 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4278
4279 /* including VoiceFX */
4280 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4281
4282 /* set correct vipsource */
4283 oldval = stop_mic1(codec);
4284 ret |= ca0132_set_vipsource(codec, 1);
4285 resume_mic1(codec, oldval);
4286 return ret;
4287}
4288
5aaca44d
IM		 4289static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4290{
4291 struct ca0132_spec *spec = codec->spec;
4292 int ret = 0;
4293
4294 if (val) /* on */
4295 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4296 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4297 else /* off */
4298 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4299 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4300
4301 return ret;
4302}
4303
a7e76271
IM		 4304static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4305 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 4306{
a7e76271
IM		 4307 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4308 hda_nid_t nid = get_amp_nid(kcontrol);
4309 hda_nid_t shared_nid = 0;
4310 bool effective;
4311 int ret = 0;
95c6e9cb 4312 struct ca0132_spec *spec = codec->spec;
a7e76271 4313 int auto_jack;
95c6e9cb 4314
a7e76271
IM		 4315 if (nid == VNID_HP_SEL) {
4316 auto_jack =
4317 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 4318 if (!auto_jack) {
4319 if (spec->use_alt_functions)
4320 ca0132_alt_select_out(codec);
4321 else
4322 ca0132_select_out(codec);
4323 }
a7e76271
IM		 4324 return 1;
4325 }
95c6e9cb 4326
a7e76271
IM		 4327 if (nid == VNID_AMIC1_SEL) {
4328 auto_jack =
4329 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4330 if (!auto_jack)
4331 ca0132_select_mic(codec);
4332 return 1;
4333 }
95c6e9cb 4334
a7e76271 4335 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 4336 if (spec->use_alt_functions)
4337 ca0132_alt_select_out(codec);
4338 else
4339 ca0132_select_out(codec);
a7e76271
IM		 4340 return 1;
4341 }
95c6e9cb 4342
a7e76271
IM		 4343 if (nid == VNID_AMIC1_ASEL) {
4344 ca0132_select_mic(codec);
4345 return 1;
95c6e9cb 4346 }
a7e76271
IM		 4347
4348 /* if effective conditions, then update hw immediately. */
4349 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4350 if (effective) {
4351 int dir = get_amp_direction(kcontrol);
4352 int ch = get_amp_channels(kcontrol);
4353 unsigned long pval;
4354
4355 mutex_lock(&codec->control_mutex);
4356 pval = kcontrol->private_value;
4357 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4358 0, dir);
4359 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4360 kcontrol->private_value = pval;
4361 mutex_unlock(&codec->control_mutex);
95c6e9cb 4362 }
95c6e9cb 4363
a7e76271 4364 return ret;
95c6e9cb 4365}
a7e76271 4366/* End of control change helpers. */
95c6e9cb 4367
7cb9d94c
CM		 4368/*
4369 * Input Select Control for alternative ca0132 codecs. This exists because
4370 * front microphone has no auto-detect, and we need a way to set the rear
4371 * as line-in
4372 */
4373static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4374 struct snd_ctl_elem_info *uinfo)
4375{
4376 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4377 uinfo->count = 1;
4378 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4379 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4380 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4381 strcpy(uinfo->value.enumerated.name,
4382 in_src_str[uinfo->value.enumerated.item]);
4383 return 0;
4384}
4385
4386static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4387 struct snd_ctl_elem_value *ucontrol)
4388{
4389 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4390 struct ca0132_spec *spec = codec->spec;
4391
4392 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4393 return 0;
4394}
4395
4396static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4397 struct snd_ctl_elem_value *ucontrol)
4398{
4399 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4400 struct ca0132_spec *spec = codec->spec;
4401 int sel = ucontrol->value.enumerated.item[0];
4402 unsigned int items = IN_SRC_NUM_OF_INPUTS;
4403
4404 if (sel >= items)
4405 return 0;
4406
4407 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4408 sel, in_src_str[sel]);
4409
4410 spec->in_enum_val = sel;
4411
4412 ca0132_alt_select_in(codec);
4413
4414 return 1;
4415}
4416
4417/* Sound Blaster Z Output Select Control */
4418static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
4419 struct snd_ctl_elem_info *uinfo)
4420{
4421 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4422 uinfo->count = 1;
4423 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
4424 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
4425 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
4426 strcpy(uinfo->value.enumerated.name,
4427 alt_out_presets[uinfo->value.enumerated.item].name);
4428 return 0;
4429}
4430
4431static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
4432 struct snd_ctl_elem_value *ucontrol)
4433{
4434 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4435 struct ca0132_spec *spec = codec->spec;
4436
4437 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
4438 return 0;
4439}
4440
4441static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
4442 struct snd_ctl_elem_value *ucontrol)
4443{
4444 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4445 struct ca0132_spec *spec = codec->spec;
4446 int sel = ucontrol->value.enumerated.item[0];
4447 unsigned int items = NUM_OF_OUTPUTS;
4448 unsigned int auto_jack;
4449
4450 if (sel >= items)
4451 return 0;
4452
4453 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
4454 sel, alt_out_presets[sel].name);
4455
4456 spec->out_enum_val = sel;
4457
4458 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4459
4460 if (!auto_jack)
4461 ca0132_alt_select_out(codec);
4462
4463 return 1;
4464}
4465
a7e76271
IM		 4466static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
4467 struct snd_ctl_elem_info *uinfo)
4468{
a9291f46 4469 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 4470
4471 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4472 uinfo->count = 1;
4473 uinfo->value.enumerated.items = items;
4474 if (uinfo->value.enumerated.item >= items)
4475 uinfo->value.enumerated.item = items - 1;
4476 strcpy(uinfo->value.enumerated.name,
4477 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
4478 return 0;
4479}
95c6e9cb 4480
a7e76271 4481static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 4482 struct snd_ctl_elem_value *ucontrol)
4483{
4484 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4485 struct ca0132_spec *spec = codec->spec;
95c6e9cb 4486
a7e76271 4487 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 4488 return 0;
4489}
4490
a7e76271 4491static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 4492 struct snd_ctl_elem_value *ucontrol)
4493{
4494 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4495 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 4496 int i, err = 0;
4497 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 4498
a9291f46 4499 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 4500 return 0;
4501
4e76a883 4502 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 4503 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 4504
a7e76271
IM		 4505 /*
4506 * Idx 0 is default.
4507 * Default needs to qualify with CrystalVoice state.
4508 */
4509 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
4510 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
4511 ca0132_voicefx.reqs[i],
4512 ca0132_voicefx_presets[sel].vals[i]);
4513 if (err < 0)
4514 break;
4515 }
95c6e9cb 4516
a7e76271
IM		 4517 if (err >= 0) {
4518 spec->voicefx_val = sel;
4519 /* enable voice fx */
4520 ca0132_voicefx_set(codec, (sel ? 1 : 0));
4521 }
95c6e9cb 4522
a7e76271 4523 return 1;
95c6e9cb
IM		 4524}
4525
a7e76271
IM		 4526static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
4527 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 4528{
4529 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4530 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 4531 hda_nid_t nid = get_amp_nid(kcontrol);
4532 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 4533 long *valp = ucontrol->value.integer.value;
4534
a7e76271
IM		 4535 /* vnode */
4536 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
4537 if (ch & 1) {
4538 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
4539 valp++;
4540 }
4541 if (ch & 2) {
4542 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
4543 valp++;
4544 }
4545 return 0;
4546 }
4547
4548 /* effects, include PE and CrystalVoice */
4549 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
4550 *valp = spec->effects_switch[nid - EFFECT_START_NID];
4551 return 0;
4552 }
4553
4554 /* mic boost */
4555 if (nid == spec->input_pins[0]) {
4556 *valp = spec->cur_mic_boost;
4557 return 0;
4558 }
4559
95c6e9cb
IM		 4560 return 0;
4561}
4562
a7e76271
IM		 4563static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
4564 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 4565{
4566 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4567 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 4568 hda_nid_t nid = get_amp_nid(kcontrol);
4569 int ch = get_amp_channels(kcontrol);
95c6e9cb 4570 long *valp = ucontrol->value.integer.value;
a7e76271 4571 int changed = 1;
95c6e9cb 4572
4e76a883 4573 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 4574 nid, *valp);
95c6e9cb
IM		 4575
4576 snd_hda_power_up(codec);
a7e76271
IM		 4577 /* vnode */
4578 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
4579 if (ch & 1) {
4580 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
4581 valp++;
4582 }
4583 if (ch & 2) {
4584 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
4585 valp++;
4586 }
4587 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
4588 goto exit;
4589 }
95c6e9cb 4590
a7e76271
IM		 4591 /* PE */
4592 if (nid == PLAY_ENHANCEMENT) {
4593 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
4594 changed = ca0132_pe_switch_set(codec);
b97f6bfd 4595 goto exit;
a7e76271 4596 }
95c6e9cb 4597
a7e76271
IM		 4598 /* CrystalVoice */
4599 if (nid == CRYSTAL_VOICE) {
4600 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
4601 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 4602 goto exit;
a7e76271 4603 }
95c6e9cb 4604
a7e76271
IM		 4605 /* out and in effects */
4606 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
4607 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
4608 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
4609 changed = ca0132_effects_set(codec, nid, *valp);
4610 goto exit;
4611 }
4612
4613 /* mic boost */
4614 if (nid == spec->input_pins[0]) {
4615 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 4616 if (spec->use_alt_functions) {
4617 if (spec->in_enum_val != REAR_LINE_IN)
4618 changed = ca0132_mic_boost_set(codec, *valp);
4619 } else {
4620 /* Mic boost does not apply to Digital Mic */
4621 if (spec->cur_mic_type != DIGITAL_MIC)
4622 changed = ca0132_mic_boost_set(codec, *valp);
4623 }
a7e76271 4624
a7e76271
IM		 4625 goto exit;
4626 }
95c6e9cb 4627
a7e76271 4628exit:
95c6e9cb 4629 snd_hda_power_down(codec);
a7e76271 4630 return changed;
95c6e9cb
IM		 4631}
4632
a7e76271
IM		 4633/*
4634 * Volume related
4635 */
4636static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
4637 struct snd_ctl_elem_info *uinfo)
4638{
4639 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4640 struct ca0132_spec *spec = codec->spec;
4641 hda_nid_t nid = get_amp_nid(kcontrol);
4642 int ch = get_amp_channels(kcontrol);
4643 int dir = get_amp_direction(kcontrol);
4644 unsigned long pval;
4645 int err;
4646
4647 switch (nid) {
4648 case VNID_SPK:
4649 /* follow shared_out info */
4650 nid = spec->shared_out_nid;
4651 mutex_lock(&codec->control_mutex);
4652 pval = kcontrol->private_value;
4653 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
4654 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
4655 kcontrol->private_value = pval;
4656 mutex_unlock(&codec->control_mutex);
4657 break;
4658 case VNID_MIC:
4659 /* follow shared_mic info */
4660 nid = spec->shared_mic_nid;
4661 mutex_lock(&codec->control_mutex);
4662 pval = kcontrol->private_value;
4663 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
4664 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
4665 kcontrol->private_value = pval;
4666 mutex_unlock(&codec->control_mutex);
4667 break;
4668 default:
4669 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
4670 }
4671 return err;
4672}
4673
4674static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 4675 struct snd_ctl_elem_value *ucontrol)
4676{
4677 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4678 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 4679 hda_nid_t nid = get_amp_nid(kcontrol);
4680 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 4681 long *valp = ucontrol->value.integer.value;
4682
a7e76271
IM		 4683 /* store the left and right volume */
4684 if (ch & 1) {
4685 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
4686 valp++;
4687 }
4688 if (ch & 2) {
4689 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
4690 valp++;
4691 }
95c6e9cb
IM		 4692 return 0;
4693}
4694
a7e76271 4695static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 4696 struct snd_ctl_elem_value *ucontrol)
4697{
4698 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4699 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 4700 hda_nid_t nid = get_amp_nid(kcontrol);
4701 int ch = get_amp_channels(kcontrol);
95c6e9cb 4702 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 4703 hda_nid_t shared_nid = 0;
4704 bool effective;
4705 int changed = 1;
4706
4707 /* store the left and right volume */
4708 if (ch & 1) {
4709 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
4710 valp++;
4711 }
4712 if (ch & 2) {
4713 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
4714 valp++;
4715 }
95c6e9cb 4716
a7e76271
IM		 4717 /* if effective conditions, then update hw immediately. */
4718 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4719 if (effective) {
4720 int dir = get_amp_direction(kcontrol);
4721 unsigned long pval;
4722
4723 snd_hda_power_up(codec);
4724 mutex_lock(&codec->control_mutex);
4725 pval = kcontrol->private_value;
4726 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4727 0, dir);
4728 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
4729 kcontrol->private_value = pval;
4730 mutex_unlock(&codec->control_mutex);
4731 snd_hda_power_down(codec);
4732 }
95c6e9cb 4733
a7e76271 4734 return changed;
95c6e9cb
IM		 4735}
4736
a7e76271
IM		 4737static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
4738 unsigned int size, unsigned int __user *tlv)
95c6e9cb 4739{
a7e76271
IM		 4740 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4741 struct ca0132_spec *spec = codec->spec;
4742 hda_nid_t nid = get_amp_nid(kcontrol);
4743 int ch = get_amp_channels(kcontrol);
4744 int dir = get_amp_direction(kcontrol);
4745 unsigned long pval;
4746 int err;
4747
4748 switch (nid) {
4749 case VNID_SPK:
4750 /* follow shared_out tlv */
4751 nid = spec->shared_out_nid;
4752 mutex_lock(&codec->control_mutex);
4753 pval = kcontrol->private_value;
4754 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
4755 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
4756 kcontrol->private_value = pval;
4757 mutex_unlock(&codec->control_mutex);
4758 break;
4759 case VNID_MIC:
4760 /* follow shared_mic tlv */
4761 nid = spec->shared_mic_nid;
4762 mutex_lock(&codec->control_mutex);
4763 pval = kcontrol->private_value;
4764 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
4765 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
4766 kcontrol->private_value = pval;
4767 mutex_unlock(&codec->control_mutex);
4768 break;
4769 default:
4770 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
4771 }
4772 return err;
95c6e9cb
IM		 4773}
4774
a7e76271
IM		 4775static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
4776 const char *pfx, int dir)
95c6e9cb 4777{
975cc02a 4778 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 4779 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 4780 struct snd_kcontrol_new knew =
a7e76271
IM		 4781 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
4782 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 4783 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4784}
4785
a7e76271 4786static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 4787{
4788 struct snd_kcontrol_new knew =
a7e76271
IM		 4789 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
4790 VOICEFX, 1, 0, HDA_INPUT);
4791 knew.info = ca0132_voicefx_info;
4792 knew.get = ca0132_voicefx_get;
4793 knew.put = ca0132_voicefx_put;
4794 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 4795}
4796
7cb9d94c
CM		 4797/*
4798 * Create an Output Select enumerated control for codecs with surround
4799 * out capabilities.
4800 */
4801static int ca0132_alt_add_output_enum(struct hda_codec *codec)
4802{
4803 struct snd_kcontrol_new knew =
4804 HDA_CODEC_MUTE_MONO("Output Select",
4805 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
4806 knew.info = ca0132_alt_output_select_get_info;
4807 knew.get = ca0132_alt_output_select_get;
4808 knew.put = ca0132_alt_output_select_put;
4809 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
4810 snd_ctl_new1(&knew, codec));
4811}
4812
4813/*
4814 * Create an Input Source enumerated control for the alternate ca0132 codecs
4815 * because the front microphone has no auto-detect, and Line-in has to be set
4816 * somehow.
4817 */
4818static int ca0132_alt_add_input_enum(struct hda_codec *codec)
4819{
4820 struct snd_kcontrol_new knew =
4821 HDA_CODEC_MUTE_MONO("Input Source",
4822 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
4823 knew.info = ca0132_alt_input_source_info;
4824 knew.get = ca0132_alt_input_source_get;
4825 knew.put = ca0132_alt_input_source_put;
4826 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
4827 snd_ctl_new1(&knew, codec));
4828}
4829
a7e76271
IM		 4830/*
4831 * When changing Node IDs for Mixer Controls below, make sure to update
4832 * Node IDs in ca0132_config() as well.
4833 */
4834static struct snd_kcontrol_new ca0132_mixer[] = {
4835 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
4836 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
4837 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
4838 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
4839 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
4840 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
4841 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
4842 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
4843 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
4844 0x12, 1, HDA_INPUT),
4845 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
4846 VNID_HP_SEL, 1, HDA_OUTPUT),
4847 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
4848 VNID_AMIC1_SEL, 1, HDA_INPUT),
4849 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
4850 VNID_HP_ASEL, 1, HDA_OUTPUT),
4851 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
4852 VNID_AMIC1_ASEL, 1, HDA_INPUT),
4853 { } /* end */
4854};
4855
e90f29e4
IM		 4856static int ca0132_build_controls(struct hda_codec *codec)
4857{
4858 struct ca0132_spec *spec = codec->spec;
4859 int i, num_fx;
4860 int err = 0;
4861
4862 /* Add Mixer controls */
4863 for (i = 0; i < spec->num_mixers; i++) {
4864 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
4865 if (err < 0)
4866 return err;
4867 }
4868
4869 /* Add in and out effects controls.
4870 * VoiceFX, PE and CrystalVoice are added separately.
4871 */
4872 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4873 for (i = 0; i < num_fx; i++) {
4874 err = add_fx_switch(codec, ca0132_effects[i].nid,
4875 ca0132_effects[i].name,
4876 ca0132_effects[i].direct);
4877 if (err < 0)
4878 return err;
4879 }
4880
4881 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
4882 if (err < 0)
4883 return err;
4884
4885 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
4886 if (err < 0)
4887 return err;
4888
4889 add_voicefx(codec);
4890
7cb9d94c
CM		 4891 /*
4892 * If the codec uses alt_functions, you need the enumerated controls
4893 * to select the new outputs and inputs, plus add the new mic boost
4894 * setting control.
4895 */
4896 if (spec->use_alt_functions) {
4897 ca0132_alt_add_output_enum(codec);
4898 ca0132_alt_add_input_enum(codec);
4899 }
e90f29e4
IM		 4900#ifdef ENABLE_TUNING_CONTROLS
4901 add_tuning_ctls(codec);
4902#endif
4903
4904 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
4905 if (err < 0)
4906 return err;
4907
4908 if (spec->dig_out) {
4909 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4910 spec->dig_out);
4911 if (err < 0)
4912 return err;
4913 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4914 if (err < 0)
4915 return err;
4916 /* spec->multiout.share_spdif = 1; */
4917 }
4918
4919 if (spec->dig_in) {
4920 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4921 if (err < 0)
4922 return err;
4923 }
4924 return 0;
4925}
4926
a7e76271 4927/*
e90f29e4 4928 * PCM
a7e76271 4929 */
071f1344 4930static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 4931 .substreams = 1,
4932 .channels_min = 2,
825315bc 4933 .channels_max = 6,
a7e76271 4934 .ops = {
a7e76271 4935 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 4936 .cleanup = ca0132_playback_pcm_cleanup,
4937 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 4938 },
4939};
4940
071f1344 4941static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 4942 .substreams = 1,
4943 .channels_min = 2,
4944 .channels_max = 2,
825315bc
IM		 4945 .ops = {
4946 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 4947 .cleanup = ca0132_capture_pcm_cleanup,
4948 .get_delay = ca0132_capture_pcm_delay,
825315bc 4949 },
a7e76271
IM		 4950};
4951
071f1344 4952static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 4953 .substreams = 1,
4954 .channels_min = 2,
4955 .channels_max = 2,
4956 .ops = {
4957 .open = ca0132_dig_playback_pcm_open,
4958 .close = ca0132_dig_playback_pcm_close,
4959 .prepare = ca0132_dig_playback_pcm_prepare,
4960 .cleanup = ca0132_dig_playback_pcm_cleanup
4961 },
4962};
4963
071f1344 4964static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 4965 .substreams = 1,
4966 .channels_min = 2,
4967 .channels_max = 2,
4968};
4969
4970static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4971{
4972 struct ca0132_spec *spec = codec->spec;
bbbc7e85 4973 struct hda_pcm *info;
a7e76271 4974
bbbc7e85
TI		 4975 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4976 if (!info)
4977 return -ENOMEM;
a7e76271
IM		 4978 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4979 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4980 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4981 spec->multiout.max_channels;
4982 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4983 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 4984 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 4985
009b8f97
CM		 4986 /* With the DSP enabled, desktops don't use this ADC. */
4987 if (spec->use_alt_functions) {
4988 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4989 if (!info)
4990 return -ENOMEM;
4991 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4992 ca0132_pcm_analog_capture;
4993 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4994 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4995 }
825315bc 4996
bbbc7e85
TI		 4997 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4998 if (!info)
4999 return -ENOMEM;
825315bc
IM		 5000 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
5001 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
5002 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 5003
a7e76271
IM		 5004 if (!spec->dig_out && !spec->dig_in)
5005 return 0;
5006
bbbc7e85
TI		 5007 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
5008 if (!info)
5009 return -ENOMEM;
a7e76271
IM		 5010 info->pcm_type = HDA_PCM_TYPE_SPDIF;
5011 if (spec->dig_out) {
5012 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
5013 ca0132_pcm_digital_playback;
5014 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
5015 }
5016 if (spec->dig_in) {
5017 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
5018 ca0132_pcm_digital_capture;
5019 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
5020 }
95c6e9cb 5021
a7e76271 5022 return 0;
95c6e9cb
IM		 5023}
5024
441aa6a0
IM		 5025static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
5026{
5027 if (pin) {
a0c041cb 5028 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 5029 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
5030 snd_hda_codec_write(codec, pin, 0,
5031 AC_VERB_SET_AMP_GAIN_MUTE,
5032 AMP_OUT_UNMUTE);
5033 }
5034 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
5035 snd_hda_codec_write(codec, dac, 0,
5036 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
5037}
5038
5039static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
5040{
5041 if (pin) {
a0c041cb 5042 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 5043 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
5044 snd_hda_codec_write(codec, pin, 0,
5045 AC_VERB_SET_AMP_GAIN_MUTE,
5046 AMP_IN_UNMUTE(0));
5047 }
5048 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
5049 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
5050 AMP_IN_UNMUTE(0));
5051
5052 /* init to 0 dB and unmute. */
5053 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
5054 HDA_AMP_VOLMASK, 0x5a);
5055 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
5056 HDA_AMP_MUTE, 0);
5057 }
5058}
5059
5aaca44d
IM		 5060static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
5061{
5062 unsigned int caps;
5063
5064 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
5065 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
5066 snd_hda_override_amp_caps(codec, nid, dir, caps);
5067}
5068
5069/*
5070 * Switch between Digital built-in mic and analog mic.
5071 */
5072static void ca0132_set_dmic(struct hda_codec *codec, int enable)
5073{
5074 struct ca0132_spec *spec = codec->spec;
5075 unsigned int tmp;
5076 u8 val;
5077 unsigned int oldval;
5078
4e76a883 5079 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 5080
5081 oldval = stop_mic1(codec);
5082 ca0132_set_vipsource(codec, 0);
5083 if (enable) {
5084 /* set DMic input as 2-ch */
5085 tmp = FLOAT_TWO;
5086 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5087
5088 val = spec->dmic_ctl;
5089 val |= 0x80;
5090 snd_hda_codec_write(codec, spec->input_pins[0], 0,
5091 VENDOR_CHIPIO_DMIC_CTL_SET, val);
5092
5093 if (!(spec->dmic_ctl & 0x20))
5094 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
5095 } else {
5096 /* set AMic input as mono */
5097 tmp = FLOAT_ONE;
5098 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5099
5100 val = spec->dmic_ctl;
5101 /* clear bit7 and bit5 to disable dmic */
5102 val &= 0x5f;
5103 snd_hda_codec_write(codec, spec->input_pins[0], 0,
5104 VENDOR_CHIPIO_DMIC_CTL_SET, val);
5105
5106 if (!(spec->dmic_ctl & 0x20))
5107 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
5108 }
5109 ca0132_set_vipsource(codec, 1);
5110 resume_mic1(codec, oldval);
5111}
5112
5113/*
5114 * Initialization for Digital Mic.
5115 */
5116static void ca0132_init_dmic(struct hda_codec *codec)
5117{
5118 struct ca0132_spec *spec = codec->spec;
5119 u8 val;
5120
5121 /* Setup Digital Mic here, but don't enable.
5122 * Enable based on jack detect.
5123 */
5124
5125 /* MCLK uses MPIO1, set to enable.
5126 * Bit 2-0: MPIO select
5127 * Bit 3: set to disable
5128 * Bit 7-4: reserved
5129 */
5130 val = 0x01;
5131 snd_hda_codec_write(codec, spec->input_pins[0], 0,
5132 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
5133
5134 /* Data1 uses MPIO3. Data2 not use
5135 * Bit 2-0: Data1 MPIO select
5136 * Bit 3: set disable Data1
5137 * Bit 6-4: Data2 MPIO select
5138 * Bit 7: set disable Data2
5139 */
5140 val = 0x83;
5141 snd_hda_codec_write(codec, spec->input_pins[0], 0,
5142 VENDOR_CHIPIO_DMIC_PIN_SET, val);
5143
5144 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
5145 * Bit 3-0: Channel mask
5146 * Bit 4: set for 48KHz, clear for 32KHz
5147 * Bit 5: mode
5148 * Bit 6: set to select Data2, clear for Data1
5149 * Bit 7: set to enable DMic, clear for AMic
5150 */
5151 val = 0x23;
5152 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
5153 spec->dmic_ctl = val;
5154 snd_hda_codec_write(codec, spec->input_pins[0], 0,
5155 VENDOR_CHIPIO_DMIC_CTL_SET, val);
5156}
5157
5158/*
5159 * Initialization for Analog Mic 2
5160 */
5161static void ca0132_init_analog_mic2(struct hda_codec *codec)
5162{
5163 struct ca0132_spec *spec = codec->spec;
5164
5165 mutex_lock(&spec->chipio_mutex);
5166 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
5167 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
5168 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
5169 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
5170 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
5171 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
5172 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
5173 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
5174 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
5175 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
5176 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
5177 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
5178 mutex_unlock(&spec->chipio_mutex);
5179}
5180
5181static void ca0132_refresh_widget_caps(struct hda_codec *codec)
5182{
5183 struct ca0132_spec *spec = codec->spec;
5184 int i;
5aaca44d 5185
4e76a883 5186 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 5187 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 5188
5189 for (i = 0; i < spec->multiout.num_dacs; i++)
5190 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
5191
5192 for (i = 0; i < spec->num_outputs; i++)
5193 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
5194
5195 for (i = 0; i < spec->num_inputs; i++) {
5196 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
5197 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
5198 }
5199}
5200
7e6ed62e
CM		 5201/*
5202 * Recon3Di r3di_setup_defaults sub functions.
5203 */
5204
447fd8e9
CM		 5205static void r3di_dsp_scp_startup(struct hda_codec *codec)
5206{
5207 unsigned int tmp;
5208
5209 tmp = 0x00000000;
5210 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
5211
5212 tmp = 0x00000001;
5213 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
5214
5215 tmp = 0x00000004;
5216 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
5217
5218 tmp = 0x00000005;
5219 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
5220
5221 tmp = 0x00000000;
5222 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
5223
5224}
5225
7e6ed62e
CM		 5226static void r3di_dsp_initial_mic_setup(struct hda_codec *codec)
5227{
5228 unsigned int tmp;
5229
5230 /* Mic 1 Setup */
5231 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5232 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5233 /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
5234 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5235 tmp = FLOAT_ONE;
5236 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5237
5238 /* Mic 2 Setup, even though it isn't connected on SBZ */
5239 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
5240 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
5241 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5242 tmp = FLOAT_ZERO;
5243 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
5244}
5245
38ba69ff
CM		 5246/*
5247 * Initialize Sound Blaster Z analog microphones.
5248 */
5249static void sbz_init_analog_mics(struct hda_codec *codec)
5250{
5251 unsigned int tmp;
5252
5253 /* Mic 1 Setup */
5254 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5255 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5256 tmp = FLOAT_THREE;
5257 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5258
5259 /* Mic 2 Setup, even though it isn't connected on SBZ */
5260 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
5261 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
5262 tmp = FLOAT_ZERO;
5263 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
5264
5265}
5266
5267/*
5268 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
5269 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
5270 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
5271 * having an updated DAC, which changes the destination to that DAC.
5272 */
5273static void sbz_connect_streams(struct hda_codec *codec)
5274{
5275 struct ca0132_spec *spec = codec->spec;
5276
5277 mutex_lock(&spec->chipio_mutex);
5278
5279 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
5280
5281 chipio_set_stream_channels(codec, 0x0C, 6);
5282 chipio_set_stream_control(codec, 0x0C, 1);
5283
5284 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
5285 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
5286
5287 /* Setup stream 0x14 with it's source and destination points */
5288 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
5289 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
5290 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
5291 chipio_set_stream_channels(codec, 0x14, 2);
5292 chipio_set_stream_control(codec, 0x14, 1);
5293
5294 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
5295
5296 mutex_unlock(&spec->chipio_mutex);
5297
5298}
5299
5300/*
5301 * Write data through ChipIO to setup proper stream destinations.
5302 * Not sure how it exactly works, but it seems to direct data
5303 * to different destinations. Example is f8 to c0, e0 to c0.
5304 * All I know is, if you don't set these, you get no sound.
5305 */
5306static void sbz_chipio_startup_data(struct hda_codec *codec)
5307{
5308 struct ca0132_spec *spec = codec->spec;
5309
5310 mutex_lock(&spec->chipio_mutex);
5311 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
5312
5313 /* These control audio output */
5314 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
5315 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
5316 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
5317 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
5318 /* Signal to update I think */
5319 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
5320
5321 chipio_set_stream_channels(codec, 0x0C, 6);
5322 chipio_set_stream_control(codec, 0x0C, 1);
5323 /* No clue what these control */
5324 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
5325 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
5326 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
5327 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
5328 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
5329 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
5330 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
5331 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
5332 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
5333 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
5334 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
5335 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
5336
5337 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
5338
5339 codec_dbg(codec, "Startup Data exited, mutex released.\n");
5340 mutex_unlock(&spec->chipio_mutex);
5341}
5342
447fd8e9
CM		 5343/*
5344 * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
5345 * without a 0x20 source like normal.
5346 */
5347static void sbz_dsp_scp_startup(struct hda_codec *codec)
5348{
5349 unsigned int tmp;
5350
5351 tmp = 0x00000003;
5352 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
5353
5354 tmp = 0x00000000;
5355 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
5356
5357 tmp = 0x00000001;
5358 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
5359
5360 tmp = 0x00000004;
5361 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
5362
5363 tmp = 0x00000005;
5364 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
5365
5366 tmp = 0x00000000;
5367 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
5368
5369}
5370
38ba69ff
CM		 5371static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
5372{
5373 unsigned int tmp;
5374
5375 chipio_set_stream_control(codec, 0x03, 0);
5376 chipio_set_stream_control(codec, 0x04, 0);
5377
5378 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5379 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5380
5381 tmp = FLOAT_THREE;
5382 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5383
5384 chipio_set_stream_control(codec, 0x03, 1);
5385 chipio_set_stream_control(codec, 0x04, 1);
5386
5387 chipio_write(codec, 0x18b098, 0x0000000c);
5388 chipio_write(codec, 0x18b09C, 0x0000000c);
5389}
5390
5aaca44d
IM		 5391/*
5392 * Setup default parameters for DSP
5393 */
5394static void ca0132_setup_defaults(struct hda_codec *codec)
5395{
e8f1bd5d 5396 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 5397 unsigned int tmp;
5398 int num_fx;
5399 int idx, i;
5400
e8f1bd5d 5401 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 5402 return;
5403
5404 /* out, in effects + voicefx */
5405 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
5406 for (idx = 0; idx < num_fx; idx++) {
5407 for (i = 0; i <= ca0132_effects[idx].params; i++) {
5408 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5409 ca0132_effects[idx].reqs[i],
5410 ca0132_effects[idx].def_vals[i]);
5411 }
5412 }
5413
5414 /*remove DSP headroom*/
5415 tmp = FLOAT_ZERO;
5416 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
5417
5418 /*set speaker EQ bypass attenuation*/
5419 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
5420
5421 /* set AMic1 and AMic2 as mono mic */
5422 tmp = FLOAT_ONE;
5423 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5424 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
5425
5426 /* set AMic1 as CrystalVoice input */
5427 tmp = FLOAT_ONE;
5428 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5429
5430 /* set WUH source */
5431 tmp = FLOAT_TWO;
5432 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
5433}
5434
7e6ed62e
CM		 5435/*
5436 * Setup default parameters for Recon3Di DSP.
5437 */
5438
5439static void r3di_setup_defaults(struct hda_codec *codec)
5440{
5441 struct ca0132_spec *spec = codec->spec;
5442 unsigned int tmp;
5443 int num_fx;
5444 int idx, i;
5445
5446 if (spec->dsp_state != DSP_DOWNLOADED)
5447 return;
5448
447fd8e9 5449 r3di_dsp_scp_startup(codec);
7e6ed62e
CM		 5450
5451 r3di_dsp_initial_mic_setup(codec);
5452
5453 /*remove DSP headroom*/
5454 tmp = FLOAT_ZERO;
5455 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
5456
5457 /* set WUH source */
5458 tmp = FLOAT_TWO;
5459 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
5460 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
5461
5462 /* Set speaker source? */
5463 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
5464
5465 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
5466
5467 /* Setup effect defaults */
5468 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
5469 for (idx = 0; idx < num_fx; idx++) {
5470 for (i = 0; i <= ca0132_effects[idx].params; i++) {
5471 dspio_set_uint_param(codec,
5472 ca0132_effects[idx].mid,
5473 ca0132_effects[idx].reqs[i],
5474 ca0132_effects[idx].def_vals[i]);
5475 }
5476 }
5477
5478}
5479
38ba69ff
CM		 5480/*
5481 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
5482 * than the Chromebook setup.
5483 */
5484static void sbz_setup_defaults(struct hda_codec *codec)
5485{
5486 struct ca0132_spec *spec = codec->spec;
5487 unsigned int tmp, stream_format;
5488 int num_fx;
5489 int idx, i;
5490
5491 if (spec->dsp_state != DSP_DOWNLOADED)
5492 return;
5493
447fd8e9 5494 sbz_dsp_scp_startup(codec);
38ba69ff
CM		 5495
5496 sbz_init_analog_mics(codec);
5497
5498 sbz_connect_streams(codec);
5499
5500 sbz_chipio_startup_data(codec);
5501
5502 chipio_set_stream_control(codec, 0x03, 1);
5503 chipio_set_stream_control(codec, 0x04, 1);
5504
5505 /*
5506 * Sets internal input loopback to off, used to have a switch to
5507 * enable input loopback, but turned out to be way too buggy.
5508 */
5509 tmp = FLOAT_ONE;
5510 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
5511 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
5512
5513 /*remove DSP headroom*/
5514 tmp = FLOAT_ZERO;
5515 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
5516
5517 /* set WUH source */
5518 tmp = FLOAT_TWO;
5519 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
5520 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
5521
5522 /* Set speaker source? */
5523 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
5524
5525 sbz_dsp_initial_mic_setup(codec);
5526
5527
5528 /* out, in effects + voicefx */
5529 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
5530 for (idx = 0; idx < num_fx; idx++) {
5531 for (i = 0; i <= ca0132_effects[idx].params; i++) {
5532 dspio_set_uint_param(codec,
5533 ca0132_effects[idx].mid,
5534 ca0132_effects[idx].reqs[i],
5535 ca0132_effects[idx].def_vals[i]);
5536 }
5537 }
5538
5539 /*
5540 * Have to make a stream to bind the sound output to, otherwise
5541 * you'll get dead audio. Before I did this, it would bind to an
5542 * audio input, and would never work
5543 */
5544 stream_format = snd_hdac_calc_stream_format(48000, 2,
5545 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
5546
5547 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
5548 0, stream_format);
5549
5550 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
5551
5552 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
5553 0, stream_format);
5554
5555 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
5556}
5557
5aaca44d
IM		 5558/*
5559 * Initialization of flags in chip
5560 */
5561static void ca0132_init_flags(struct hda_codec *codec)
5562{
009b8f97
CM		 5563 struct ca0132_spec *spec = codec->spec;
5564
5565 if (spec->use_alt_functions) {
5566 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
5567 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
5568 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
5569 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
5570 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
5571 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
5572 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
5573 chipio_set_control_flag(codec,
5574 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
5575 chipio_set_control_flag(codec,
5576 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
5577 } else {
5578 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
5579 chipio_set_control_flag(codec,
5580 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
5581 chipio_set_control_flag(codec,
5582 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
5583 chipio_set_control_flag(codec,
5584 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
5585 chipio_set_control_flag(codec,
5586 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
5587 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
5588 }
5aaca44d
IM		 5589}
5590
5591/*
5592 * Initialization of parameters in chip
5593 */
5594static void ca0132_init_params(struct hda_codec *codec)
5595{
009b8f97
CM		 5596 struct ca0132_spec *spec = codec->spec;
5597
5598 if (spec->use_alt_functions) {
5599 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
5600 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
5601 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
5602 chipio_set_control_param(codec, 0, 0);
5603 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
5604 }
5605
5aaca44d
IM		 5606 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
5607 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
5608}
95c6e9cb 5609
e90f29e4
IM		 5610static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
5611{
5612 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
5613 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
5614 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
5615 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
5616 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
5617 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
5618
406261ce
IM		 5619 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5620 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 5621 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
5622}
5623
5624static bool ca0132_download_dsp_images(struct hda_codec *codec)
5625{
5626 bool dsp_loaded = false;
8a19bcee 5627 struct ca0132_spec *spec = codec->spec;
e90f29e4 5628 const struct dsp_image_seg *dsp_os_image;
15e4ba66 5629 const struct firmware *fw_entry;
8a19bcee
CM		 5630 /*
5631 * Alternate firmwares for different variants. The Recon3Di apparently
5632 * can use the default firmware, but I'll leave the option in case
5633 * it needs it again.
5634 */
5635 switch (spec->quirk) {
5636 case QUIRK_SBZ:
5637 if (request_firmware(&fw_entry, SBZ_EFX_FILE,
5638 codec->card->dev) != 0) {
5639 codec_dbg(codec, "SBZ alt firmware not detected. ");
5640 spec->alt_firmware_present = false;
5641 } else {
5642 codec_dbg(codec, "Sound Blaster Z firmware selected.");
5643 spec->alt_firmware_present = true;
5644 }
5645 break;
5646 case QUIRK_R3DI:
5647 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
5648 codec->card->dev) != 0) {
5649 codec_dbg(codec, "Recon3Di alt firmware not detected.");
5650 spec->alt_firmware_present = false;
5651 } else {
5652 codec_dbg(codec, "Recon3Di firmware selected.");
5653 spec->alt_firmware_present = true;
5654 }
5655 break;
5656 default:
5657 spec->alt_firmware_present = false;
5658 break;
5659 }
5660 /*
5661 * Use default ctefx.bin if no alt firmware is detected, or if none
5662 * exists for your particular codec.
5663 */
5664 if (!spec->alt_firmware_present) {
5665 codec_dbg(codec, "Default firmware selected.");
5666 if (request_firmware(&fw_entry, EFX_FILE,
5667 codec->card->dev) != 0)
5668 return false;
5669 }
e90f29e4 5670
15e4ba66 5671 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 5672 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 5673 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 5674 goto exit_download;
5675 }
5676
e90f29e4
IM		 5677 dsp_loaded = dspload_wait_loaded(codec);
5678
d1d28500 5679exit_download:
15e4ba66
TI		 5680 release_firmware(fw_entry);
5681
e90f29e4
IM		 5682 return dsp_loaded;
5683}
5684
5685static void ca0132_download_dsp(struct hda_codec *codec)
5686{
5687 struct ca0132_spec *spec = codec->spec;
5688
9a0869f4
TI		 5689#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
5690 return; /* NOP */
5691#endif
e90f29e4 5692
e24aa0a4
TI		 5693 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
5694 return; /* don't retry failures */
5695
b714a710 5696 chipio_enable_clocks(codec);
e93ac30a
CM		 5697 if (spec->dsp_state != DSP_DOWNLOADED) {
5698 spec->dsp_state = DSP_DOWNLOADING;
5699
5700 if (!ca0132_download_dsp_images(codec))
5701 spec->dsp_state = DSP_DOWNLOAD_FAILED;
5702 else
5703 spec->dsp_state = DSP_DOWNLOADED;
5704 }
e90f29e4 5705
009b8f97
CM		 5706 /* For codecs using alt functions, this is already done earlier */
5707 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 5708 ca0132_set_dsp_msr(codec, true);
5709}
5710
f8fb1170
TI		 5711static void ca0132_process_dsp_response(struct hda_codec *codec,
5712 struct hda_jack_callback *callback)
e90f29e4
IM		 5713{
5714 struct ca0132_spec *spec = codec->spec;
5715
4e76a883 5716 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 5717 if (spec->wait_scp) {
5718 if (dspio_get_response_data(codec) >= 0)
5719 spec->wait_scp = 0;
5720 }
5721
5722 dspio_clear_response_queue(codec);
5723}
5724
f8fb1170 5725static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 5726{
993884f6 5727 struct ca0132_spec *spec = codec->spec;
2ebab40e 5728 struct hda_jack_tbl *tbl;
e90f29e4 5729
f8fb1170
TI		 5730 /* Delay enabling the HP amp, to let the mic-detection
5731 * state machine run.
5732 */
5733 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 5734 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 5735 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
5736 if (tbl)
5737 tbl->block_report = 1;
f8fb1170
TI		 5738}
5739
5740static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
5741{
5742 ca0132_select_mic(codec);
5743}
5744
5745static void ca0132_init_unsol(struct hda_codec *codec)
5746{
d5c016b5
GM		 5747 struct ca0132_spec *spec = codec->spec;
5748 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
5749 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 5750 amic_callback);
5751 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
5752 ca0132_process_dsp_response);
63177afc 5753 /* Front headphone jack detection */
009b8f97 5754 if (spec->use_alt_functions)
63177afc
CM		 5755 snd_hda_jack_detect_enable_callback(codec,
5756 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 5757}
5758
5aaca44d
IM		 5759/*
5760 * Verbs tables.
5761 */
5762
5763/* Sends before DSP download. */
5764static struct hda_verb ca0132_base_init_verbs[] = {
5765 /*enable ct extension*/
5766 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 5767 {}
5768};
5769
5770/* Send at exit. */
5771static struct hda_verb ca0132_base_exit_verbs[] = {
5772 /*set afg to D3*/
5773 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
5774 /*disable ct extension*/
5775 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
5776 {}
5777};
5778
8a19bcee 5779/* Other verbs tables. Sends after DSP download. */
e93ac30a 5780
5aaca44d
IM		 5781static struct hda_verb ca0132_init_verbs0[] = {
5782 /* chip init verbs */
5783 {0x15, 0x70D, 0xF0},
5784 {0x15, 0x70E, 0xFE},
5785 {0x15, 0x707, 0x75},
5786 {0x15, 0x707, 0xD3},
5787 {0x15, 0x707, 0x09},
5788 {0x15, 0x707, 0x53},
5789 {0x15, 0x707, 0xD4},
5790 {0x15, 0x707, 0xEF},
5791 {0x15, 0x707, 0x75},
5792 {0x15, 0x707, 0xD3},
5793 {0x15, 0x707, 0x09},
5794 {0x15, 0x707, 0x02},
5795 {0x15, 0x707, 0x37},
5796 {0x15, 0x707, 0x78},
5797 {0x15, 0x53C, 0xCE},
5798 {0x15, 0x575, 0xC9},
5799 {0x15, 0x53D, 0xCE},
5800 {0x15, 0x5B7, 0xC9},
5801 {0x15, 0x70D, 0xE8},
5802 {0x15, 0x70E, 0xFE},
5803 {0x15, 0x707, 0x02},
5804 {0x15, 0x707, 0x68},
5805 {0x15, 0x707, 0x62},
5806 {0x15, 0x53A, 0xCE},
5807 {0x15, 0x546, 0xC9},
5808 {0x15, 0x53B, 0xCE},
5809 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 5810 {}
5811};
5812
5813/* Extra init verbs for SBZ */
5814static struct hda_verb sbz_init_verbs[] = {
5815 {0x15, 0x70D, 0x20},
5816 {0x15, 0x70E, 0x19},
5817 {0x15, 0x707, 0x00},
5818 {0x15, 0x539, 0xCE},
5819 {0x15, 0x546, 0xC9},
5820 {0x15, 0x70D, 0xB7},
5821 {0x15, 0x70E, 0x09},
5822 {0x15, 0x707, 0x10},
5823 {0x15, 0x70D, 0xAF},
5824 {0x15, 0x70E, 0x09},
5825 {0x15, 0x707, 0x01},
5826 {0x15, 0x707, 0x05},
5827 {0x15, 0x70D, 0x73},
5828 {0x15, 0x70E, 0x09},
5829 {0x15, 0x707, 0x14},
5830 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 5831 {}
5832};
5833
95c6e9cb
IM		 5834static void ca0132_init_chip(struct hda_codec *codec)
5835{
5836 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 5837 int num_fx;
5838 int i;
5839 unsigned int on;
95c6e9cb
IM		 5840
5841 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 5842
5843 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 5844 if (!spec->use_alt_functions)
5845 spec->cur_mic_type = DIGITAL_MIC;
5846 else
5847 spec->cur_mic_type = REAR_MIC;
5848
5aaca44d
IM		 5849 spec->cur_mic_boost = 0;
5850
5851 for (i = 0; i < VNODES_COUNT; i++) {
5852 spec->vnode_lvol[i] = 0x5a;
5853 spec->vnode_rvol[i] = 0x5a;
5854 spec->vnode_lswitch[i] = 0;
5855 spec->vnode_rswitch[i] = 0;
5856 }
5857
5858 /*
5859 * Default states for effects are in ca0132_effects[].
5860 */
5861 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5862 for (i = 0; i < num_fx; i++) {
5863 on = (unsigned int)ca0132_effects[i].reqs[0];
5864 spec->effects_switch[i] = on ? 1 : 0;
5865 }
5866
5867 spec->voicefx_val = 0;
5868 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
5869 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
5870
44f0c978
IM		 5871#ifdef ENABLE_TUNING_CONTROLS
5872 ca0132_init_tuning_defaults(codec);
5873#endif
95c6e9cb
IM		 5874}
5875
2e48b2b7
CM		 5876/*
5877 * Recon3Di exit specific commands.
5878 */
5879/* prevents popping noise on shutdown */
5880static void r3di_gpio_shutdown(struct hda_codec *codec)
5881{
5882 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
5883}
5884
5885/*
5886 * Sound Blaster Z exit specific commands.
5887 */
5888static void sbz_region2_exit(struct hda_codec *codec)
5889{
5890 struct ca0132_spec *spec = codec->spec;
5891 unsigned int i;
5892
5893 for (i = 0; i < 4; i++)
5894 writeb(0x0, spec->mem_base + 0x100);
5895 for (i = 0; i < 8; i++)
5896 writeb(0xb3, spec->mem_base + 0x304);
5897 /*
5898 * I believe these are GPIO, with the right most hex digit being the
5899 * gpio pin, and the second digit being on or off. We see this more in
5900 * the input/output select functions.
5901 */
5902 writew(0x0000, spec->mem_base + 0x320);
5903 writew(0x0001, spec->mem_base + 0x320);
5904 writew(0x0104, spec->mem_base + 0x320);
5905 writew(0x0005, spec->mem_base + 0x320);
5906 writew(0x0007, spec->mem_base + 0x320);
5907}
5908
5909static void sbz_set_pin_ctl_default(struct hda_codec *codec)
5910{
5911 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
5912 unsigned int i;
5913
5914 snd_hda_codec_write(codec, 0x11, 0,
5915 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
5916
5917 for (i = 0; i < 5; i++)
5918 snd_hda_codec_write(codec, pins[i], 0,
5919 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
5920}
5921
5922static void sbz_clear_unsolicited(struct hda_codec *codec)
5923{
5924 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
5925 unsigned int i;
5926
5927 for (i = 0; i < 7; i++) {
5928 snd_hda_codec_write(codec, pins[i], 0,
5929 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
5930 }
5931}
5932
5933/* On shutdown, sends commands in sets of three */
5934static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
5935 int mask, int data)
5936{
5937 if (dir >= 0)
5938 snd_hda_codec_write(codec, 0x01, 0,
5939 AC_VERB_SET_GPIO_DIRECTION, dir);
5940 if (mask >= 0)
5941 snd_hda_codec_write(codec, 0x01, 0,
5942 AC_VERB_SET_GPIO_MASK, mask);
5943
5944 if (data >= 0)
5945 snd_hda_codec_write(codec, 0x01, 0,
5946 AC_VERB_SET_GPIO_DATA, data);
5947}
5948
5949static void sbz_exit_chip(struct hda_codec *codec)
5950{
009b8f97
CM		 5951 chipio_set_stream_control(codec, 0x03, 0);
5952 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 5953
5954 /* Mess with GPIO */
5955 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
5956 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
5957 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
5958
009b8f97
CM		 5959 chipio_set_stream_control(codec, 0x14, 0);
5960 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 5961
5962 chipio_set_conn_rate(codec, 0x41, SR_192_000);
5963 chipio_set_conn_rate(codec, 0x91, SR_192_000);
5964
5965 chipio_write(codec, 0x18a020, 0x00000083);
5966
5967 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
5968 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
5969 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
5970
009b8f97 5971 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 5972
5973 chipio_set_control_param(codec, 0x0D, 0x24);
5974
5975 sbz_clear_unsolicited(codec);
5976 sbz_set_pin_ctl_default(codec);
5977
5978 snd_hda_codec_write(codec, 0x0B, 0,
5979 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
5980
5981 if (dspload_is_loaded(codec))
5982 dsp_reset(codec);
5983
5984 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
5985 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x00);
5986
5987 sbz_region2_exit(codec);
5988}
5989
95c6e9cb
IM		 5990static void ca0132_exit_chip(struct hda_codec *codec)
5991{
5992 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 5993
5994 if (dspload_is_loaded(codec))
5995 dsp_reset(codec);
95c6e9cb
IM		 5996}
5997
38ba69ff
CM		 5998/*
5999 * This fixes a problem that was hard to reproduce. Very rarely, I would
6000 * boot up, and there would be no sound, but the DSP indicated it had loaded
6001 * properly. I did a few memory dumps to see if anything was different, and
6002 * there were a few areas of memory uninitialized with a1a2a3a4. This function
6003 * checks if those areas are uninitialized, and if they are, it'll attempt to
6004 * reload the card 3 times. Usually it fixes by the second.
6005 */
6006static void sbz_dsp_startup_check(struct hda_codec *codec)
6007{
6008 struct ca0132_spec *spec = codec->spec;
6009 unsigned int dsp_data_check[4];
6010 unsigned int cur_address = 0x390;
6011 unsigned int i;
6012 unsigned int failure = 0;
6013 unsigned int reload = 3;
6014
6015 if (spec->startup_check_entered)
6016 return;
6017
6018 spec->startup_check_entered = true;
6019
6020 for (i = 0; i < 4; i++) {
6021 chipio_read(codec, cur_address, &dsp_data_check[i]);
6022 cur_address += 0x4;
6023 }
6024 for (i = 0; i < 4; i++) {
6025 if (dsp_data_check[i] == 0xa1a2a3a4)
6026 failure = 1;
6027 }
6028
6029 codec_dbg(codec, "Startup Check: %d ", failure);
6030 if (failure)
6031 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
6032 /*
6033 * While the failure condition is true, and we haven't reached our
6034 * three reload limit, continue trying to reload the driver and
6035 * fix the issue.
6036 */
6037 while (failure && (reload != 0)) {
6038 codec_info(codec, "Reloading... Tries left: %d", reload);
6039 sbz_exit_chip(codec);
6040 spec->dsp_state = DSP_DOWNLOAD_INIT;
6041 codec->patch_ops.init(codec);
6042 failure = 0;
6043 for (i = 0; i < 4; i++) {
6044 chipio_read(codec, cur_address, &dsp_data_check[i]);
6045 cur_address += 0x4;
6046 }
6047 for (i = 0; i < 4; i++) {
6048 if (dsp_data_check[i] == 0xa1a2a3a4)
6049 failure = 1;
6050 }
6051 reload--;
6052 }
6053
6054 if (!failure && reload < 3)
6055 codec_info(codec, "DSP fixed.");
6056
6057 if (!failure)
6058 return;
6059
6060 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
6061}
6062
e93ac30a
CM		 6063/*
6064 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
6065 * extra precision for decibel values. If you had the dB value in floating point
6066 * you would take the value after the decimal point, multiply by 64, and divide
6067 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
6068 * implement fixed point or floating point dB volumes. For now, I'll set them
6069 * to 0 just incase a value has lingered from a boot into Windows.
6070 */
6071static void ca0132_alt_vol_setup(struct hda_codec *codec)
6072{
6073 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
6074 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
6075 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
6076 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
6077 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
6078 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
6079 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
6080 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
6081}
6082
6083/*
6084 * Extra commands that don't really fit anywhere else.
6085 */
6086static void sbz_pre_dsp_setup(struct hda_codec *codec)
6087{
6088 struct ca0132_spec *spec = codec->spec;
6089
6090 writel(0x00820680, spec->mem_base + 0x01C);
6091 writel(0x00820680, spec->mem_base + 0x01C);
6092
6093 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
6094 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
6095 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
6096 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
6097
6098 chipio_write(codec, 0x18b0a4, 0x000000c2);
6099
6100 snd_hda_codec_write(codec, 0x11, 0,
6101 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
6102}
6103
6104/*
6105 * Extra commands that don't really fit anywhere else.
6106 */
6107static void r3di_pre_dsp_setup(struct hda_codec *codec)
6108{
6109 chipio_write(codec, 0x18b0a4, 0x000000c2);
6110
6111 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6112 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
6113 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6114 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
6115 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6116 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
6117
6118 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6119 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6120 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6121 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6122 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6123 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6124 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6125 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
6126
6127 snd_hda_codec_write(codec, 0x11, 0,
6128 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
6129}
6130
6131
6132/*
6133 * These are sent before the DSP is downloaded. Not sure
6134 * what they do, or if they're necessary. Could possibly
6135 * be removed. Figure they're better to leave in.
6136 */
6137static void sbz_region2_startup(struct hda_codec *codec)
6138{
6139 struct ca0132_spec *spec = codec->spec;
6140
6141 writel(0x00000000, spec->mem_base + 0x400);
6142 writel(0x00000000, spec->mem_base + 0x408);
6143 writel(0x00000000, spec->mem_base + 0x40C);
6144 writel(0x00880680, spec->mem_base + 0x01C);
6145 writel(0x00000083, spec->mem_base + 0xC0C);
6146 writel(0x00000030, spec->mem_base + 0xC00);
6147 writel(0x00000000, spec->mem_base + 0xC04);
6148 writel(0x00000003, spec->mem_base + 0xC0C);
6149 writel(0x00000003, spec->mem_base + 0xC0C);
6150 writel(0x00000003, spec->mem_base + 0xC0C);
6151 writel(0x00000003, spec->mem_base + 0xC0C);
6152 writel(0x000000C1, spec->mem_base + 0xC08);
6153 writel(0x000000F1, spec->mem_base + 0xC08);
6154 writel(0x00000001, spec->mem_base + 0xC08);
6155 writel(0x000000C7, spec->mem_base + 0xC08);
6156 writel(0x000000C1, spec->mem_base + 0xC08);
6157 writel(0x00000080, spec->mem_base + 0xC04);
6158}
6159
6160/*
6161 * Extra init functions for alternative ca0132 codecs. Done
6162 * here so they don't clutter up the main ca0132_init function
6163 * anymore than they have to.
6164 */
6165static void ca0132_alt_init(struct hda_codec *codec)
6166{
6167 struct ca0132_spec *spec = codec->spec;
6168
6169 ca0132_alt_vol_setup(codec);
6170
6171 switch (spec->quirk) {
6172 case QUIRK_SBZ:
6173 codec_dbg(codec, "SBZ alt_init");
6174 ca0132_gpio_init(codec);
6175 sbz_pre_dsp_setup(codec);
6176 snd_hda_sequence_write(codec, spec->chip_init_verbs);
6177 snd_hda_sequence_write(codec, spec->sbz_init_verbs);
6178 break;
6179 case QUIRK_R3DI:
6180 codec_dbg(codec, "R3DI alt_init");
6181 ca0132_gpio_init(codec);
6182 ca0132_gpio_setup(codec);
7e6ed62e 6183 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 6184 r3di_pre_dsp_setup(codec);
6185 snd_hda_sequence_write(codec, spec->chip_init_verbs);
6186 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
6187 break;
6188 }
6189}
6190
95c6e9cb
IM		 6191static int ca0132_init(struct hda_codec *codec)
6192{
6193 struct ca0132_spec *spec = codec->spec;
6194 struct auto_pin_cfg *cfg = &spec->autocfg;
6195 int i;
e93ac30a
CM		 6196 bool dsp_loaded;
6197
6198 /*
6199 * If the DSP is already downloaded, and init has been entered again,
6200 * there's only two reasons for it. One, the codec has awaken from a
6201 * suspended state, and in that case dspload_is_loaded will return
6202 * false, and the init will be ran again. The other reason it gets
6203 * re entered is on startup for some reason it triggers a suspend and
6204 * resume state. In this case, it will check if the DSP is downloaded,
6205 * and not run the init function again. For codecs using alt_functions,
6206 * it will check if the DSP is loaded properly.
6207 */
6208 if (spec->dsp_state == DSP_DOWNLOADED) {
6209 dsp_loaded = dspload_is_loaded(codec);
6210 if (!dsp_loaded) {
6211 spec->dsp_reload = true;
6212 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 6213 } else {
6214 if (spec->quirk == QUIRK_SBZ)
6215 sbz_dsp_startup_check(codec);
e93ac30a 6216 return 0;
38ba69ff 6217 }
e93ac30a 6218 }
95c6e9cb 6219
e24aa0a4
TI		 6220 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
6221 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 6222 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 6223
e93ac30a
CM		 6224 if (spec->quirk == QUIRK_SBZ)
6225 sbz_region2_startup(codec);
6226
664c7155 6227 snd_hda_power_up_pm(codec);
5aaca44d 6228
f8fb1170 6229 ca0132_init_unsol(codec);
5aaca44d
IM		 6230 ca0132_init_params(codec);
6231 ca0132_init_flags(codec);
7e6ed62e 6232
5aaca44d 6233 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a
CM		 6234
6235 if (spec->quirk != QUIRK_NONE)
6236 ca0132_alt_init(codec);
6237
01ef7dbf 6238 ca0132_download_dsp(codec);
7e6ed62e 6239
5aaca44d 6240 ca0132_refresh_widget_caps(codec);
e93ac30a
CM		 6241
6242 if (spec->quirk == QUIRK_SBZ)
6243 writew(0x0107, spec->mem_base + 0x320);
6244
7e6ed62e
CM		 6245 switch (spec->quirk) {
6246 case QUIRK_R3DI:
6247 r3di_setup_defaults(codec);
6248 break;
6249 case QUIRK_NONE:
6250 case QUIRK_ALIENWARE:
38ba69ff
CM		 6251 ca0132_setup_defaults(codec);
6252 ca0132_init_analog_mic2(codec);
6253 ca0132_init_dmic(codec);
7e6ed62e 6254 break;
38ba69ff 6255 }
5aaca44d
IM		 6256
6257 for (i = 0; i < spec->num_outputs; i++)
6258 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 6259
95c6e9cb
IM		 6260 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
6261
6262 for (i = 0; i < spec->num_inputs; i++)
6263 init_input(codec, spec->input_pins[i], spec->adcs[i]);
6264
6265 init_input(codec, cfg->dig_in_pin, spec->dig_in);
6266
009b8f97 6267 if (!spec->use_alt_functions) {
e93ac30a
CM		 6268 snd_hda_sequence_write(codec, spec->chip_init_verbs);
6269 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6270 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
6271 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6272 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
6273 }
6274
7cb9d94c 6275 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 6276 ca0132_gpio_setup(codec);
6277
d5c016b5 6278 snd_hda_sequence_write(codec, spec->spec_init_verbs);
7cb9d94c
CM		 6279 switch (spec->quirk) {
6280 case QUIRK_SBZ:
6281 sbz_setup_defaults(codec);
6282 ca0132_alt_select_out(codec);
6283 ca0132_alt_select_in(codec);
6284 break;
6285 case QUIRK_R3DI:
6286 ca0132_alt_select_out(codec);
6287 ca0132_alt_select_in(codec);
6288 break;
6289 default:
6290 ca0132_select_out(codec);
6291 ca0132_select_mic(codec);
6292 break;
6293 }
5aaca44d 6294
a73d511c
IM		 6295 snd_hda_jack_report_sync(codec);
6296
e93ac30a
CM		 6297 /*
6298 * Re set the PlayEnhancement switch on a resume event, because the
6299 * controls will not be reloaded.
6300 */
6301 if (spec->dsp_reload) {
6302 spec->dsp_reload = false;
6303 ca0132_pe_switch_set(codec);
6304 }
6305
664c7155 6306 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 6307
6308 return 0;
6309}
6310
95c6e9cb
IM		 6311static void ca0132_free(struct hda_codec *codec)
6312{
5aaca44d
IM		 6313 struct ca0132_spec *spec = codec->spec;
6314
993884f6 6315 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 6316 snd_hda_power_up(codec);
2e48b2b7
CM		 6317 switch (spec->quirk) {
6318 case QUIRK_SBZ:
6319 sbz_exit_chip(codec);
6320 break;
6321 case QUIRK_R3DI:
6322 r3di_gpio_shutdown(codec);
6323 snd_hda_sequence_write(codec, spec->base_exit_verbs);
6324 ca0132_exit_chip(codec);
6325 break;
6326 default:
6327 snd_hda_sequence_write(codec, spec->base_exit_verbs);
6328 ca0132_exit_chip(codec);
6329 break;
6330 }
5aaca44d 6331 snd_hda_power_down(codec);
aa31704f
CM		 6332 if (spec->mem_base)
6333 iounmap(spec->mem_base);
d5c016b5 6334 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 6335 kfree(codec->spec);
6336}
6337
2e48b2b7
CM		 6338static void ca0132_reboot_notify(struct hda_codec *codec)
6339{
6340 codec->patch_ops.free(codec);
6341}
6342
071f1344 6343static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 6344 .build_controls = ca0132_build_controls,
6345 .build_pcms = ca0132_build_pcms,
6346 .init = ca0132_init,
6347 .free = ca0132_free,
f8fb1170 6348 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 6349 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 6350};
6351
441aa6a0
IM		 6352static void ca0132_config(struct hda_codec *codec)
6353{
6354 struct ca0132_spec *spec = codec->spec;
6355 struct auto_pin_cfg *cfg = &spec->autocfg;
6356
6357 spec->dacs[0] = 0x2;
6358 spec->dacs[1] = 0x3;
6359 spec->dacs[2] = 0x4;
6360
6361 spec->multiout.dac_nids = spec->dacs;
6362 spec->multiout.num_dacs = 3;
441aa6a0 6363
009b8f97 6364 if (!spec->use_alt_functions)
63177afc
CM		 6365 spec->multiout.max_channels = 2;
6366 else
6367 spec->multiout.max_channels = 6;
6368
6369 switch (spec->quirk) {
6370 case QUIRK_ALIENWARE:
d5c016b5 6371 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 6372 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
6373
6374 spec->num_outputs = 2;
6375 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 6376 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 6377 spec->shared_out_nid = 0x2;
6378 spec->unsol_tag_hp = 0x0f;
6379
6380 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
6381 spec->adcs[1] = 0x8; /* analog mic2 */
6382 spec->adcs[2] = 0xa; /* what u hear */
6383
6384 spec->num_inputs = 3;
6385 spec->input_pins[0] = 0x12;
6386 spec->input_pins[1] = 0x11;
6387 spec->input_pins[2] = 0x13;
6388 spec->shared_mic_nid = 0x7;
6389 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 6390 break;
6391 case QUIRK_SBZ:
6392 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
6393 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
6394
6395 spec->num_outputs = 2;
6396 spec->out_pins[0] = 0x0B; /* Line out */
6397 spec->out_pins[1] = 0x0F; /* Rear headphone out */
6398 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
6399 spec->out_pins[3] = 0x11; /* Rear surround */
6400 spec->shared_out_nid = 0x2;
6401 spec->unsol_tag_hp = spec->out_pins[1];
6402 spec->unsol_tag_front_hp = spec->out_pins[2];
6403
6404 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
6405 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
6406 spec->adcs[2] = 0xa; /* what u hear */
6407
6408 spec->num_inputs = 2;
6409 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
6410 spec->input_pins[1] = 0x13; /* What U Hear */
6411 spec->shared_mic_nid = 0x7;
6412 spec->unsol_tag_amic1 = spec->input_pins[0];
6413
6414 /* SPDIF I/O */
6415 spec->dig_out = 0x05;
6416 spec->multiout.dig_out_nid = spec->dig_out;
6417 cfg->dig_out_pins[0] = 0x0c;
6418 cfg->dig_outs = 1;
6419 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
6420 spec->dig_in = 0x09;
6421 cfg->dig_in_pin = 0x0e;
6422 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
6423 break;
6424 case QUIRK_R3DI:
6425 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
6426 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
6427
6428 spec->num_outputs = 2;
6429 spec->out_pins[0] = 0x0B; /* Line out */
6430 spec->out_pins[1] = 0x0F; /* Rear headphone out */
6431 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
6432 spec->out_pins[3] = 0x11; /* Rear surround */
6433 spec->shared_out_nid = 0x2;
6434 spec->unsol_tag_hp = spec->out_pins[1];
6435 spec->unsol_tag_front_hp = spec->out_pins[2];
6436
6437 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
6438 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
6439 spec->adcs[2] = 0x0a; /* what u hear */
6440
6441 spec->num_inputs = 2;
6442 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
6443 spec->input_pins[1] = 0x13; /* What U Hear */
6444 spec->shared_mic_nid = 0x7;
6445 spec->unsol_tag_amic1 = spec->input_pins[0];
6446
6447 /* SPDIF I/O */
6448 spec->dig_out = 0x05;
6449 spec->multiout.dig_out_nid = spec->dig_out;
6450 cfg->dig_out_pins[0] = 0x0c;
6451 cfg->dig_outs = 1;
6452 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
6453 break;
6454 default:
fe14f39e
TI		 6455 spec->num_outputs = 2;
6456 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 6457 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 6458 spec->shared_out_nid = 0x2;
6459 spec->unsol_tag_hp = spec->out_pins[1];
6460
6461 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
6462 spec->adcs[1] = 0x8; /* analog mic2 */
6463 spec->adcs[2] = 0xa; /* what u hear */
6464
6465 spec->num_inputs = 3;
6466 spec->input_pins[0] = 0x12;
6467 spec->input_pins[1] = 0x11;
6468 spec->input_pins[2] = 0x13;
6469 spec->shared_mic_nid = 0x7;
6470 spec->unsol_tag_amic1 = spec->input_pins[0];
6471
6472 /* SPDIF I/O */
6473 spec->dig_out = 0x05;
6474 spec->multiout.dig_out_nid = spec->dig_out;
6475 cfg->dig_out_pins[0] = 0x0c;
6476 cfg->dig_outs = 1;
6477 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
6478 spec->dig_in = 0x09;
6479 cfg->dig_in_pin = 0x0e;
6480 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
63177afc 6481 break;
d5c016b5 6482 }
441aa6a0
IM		 6483}
6484
d5c016b5
GM		 6485static int ca0132_prepare_verbs(struct hda_codec *codec)
6486{
6487/* Verbs + terminator (an empty element) */
6488#define NUM_SPEC_VERBS 4
6489 struct ca0132_spec *spec = codec->spec;
6490
6491 spec->chip_init_verbs = ca0132_init_verbs0;
e93ac30a
CM		 6492 if (spec->quirk == QUIRK_SBZ)
6493 spec->sbz_init_verbs = sbz_init_verbs;
d5c016b5
GM		 6494 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
6495 if (!spec->spec_init_verbs)
6496 return -ENOMEM;
6497
6498 /* HP jack autodetection */
6499 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
6500 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
6501 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
6502
6503 /* MIC1 jack autodetection */
6504 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
6505 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
6506 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
6507
6508 /* config EAPD */
6509 spec->spec_init_verbs[2].nid = 0x0b;
6510 spec->spec_init_verbs[2].param = 0x78D;
6511 spec->spec_init_verbs[2].verb = 0x00;
6512
6513 /* Previously commented configuration */
6514 /*
6515 spec->spec_init_verbs[3].nid = 0x0b;
6516 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
6517 spec->spec_init_verbs[3].verb = 0x02;
6518
6519 spec->spec_init_verbs[4].nid = 0x10;
6520 spec->spec_init_verbs[4].param = 0x78D;
6521 spec->spec_init_verbs[4].verb = 0x02;
6522
6523 spec->spec_init_verbs[5].nid = 0x10;
6524 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
6525 spec->spec_init_verbs[5].verb = 0x02;
6526 */
6527
6528 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
6529 return 0;
6530}
6531
95c6e9cb
IM		 6532static int patch_ca0132(struct hda_codec *codec)
6533{
6534 struct ca0132_spec *spec;
a73d511c 6535 int err;
d5c016b5 6536 const struct snd_pci_quirk *quirk;
95c6e9cb 6537
4e76a883 6538 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 6539
6540 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
6541 if (!spec)
6542 return -ENOMEM;
6543 codec->spec = spec;
993884f6 6544 spec->codec = codec;
95c6e9cb 6545
225068ab
TI		 6546 codec->patch_ops = ca0132_patch_ops;
6547 codec->pcm_format_first = 1;
6548 codec->no_sticky_stream = 1;
6549
d5c016b5
GM		 6550 /* Detect codec quirk */
6551 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
6552 if (quirk)
6553 spec->quirk = quirk->value;
6554 else
6555 spec->quirk = QUIRK_NONE;
6556
aa31704f
CM		 6557 /* Setup BAR Region 2 for Sound Blaster Z */
6558 if (spec->quirk == QUIRK_SBZ) {
6559 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
6560 if (spec->mem_base == NULL) {
6561 codec_warn(codec, "pci_iomap failed!");
6562 codec_info(codec, "perhaps this is not an SBZ?");
6563 spec->quirk = QUIRK_NONE;
6564 }
6565 }
009b8f97 6566
e24aa0a4 6567 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271
IM		 6568 spec->num_mixers = 1;
6569 spec->mixers[0] = ca0132_mixer;
6570
009b8f97
CM		 6571 /* Setup whether or not to use alt functions */
6572 switch (spec->quirk) {
6573 case QUIRK_SBZ:
6574 case QUIRK_R3DI:
6575 spec->use_alt_functions = true;
6576 break;
6577 default:
6578 spec->use_alt_functions = false;
6579 break;
6580 }
6581
5aaca44d
IM		 6582 spec->base_init_verbs = ca0132_base_init_verbs;
6583 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 6584
993884f6
CCC		 6585 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
6586
95c6e9cb
IM		 6587 ca0132_init_chip(codec);
6588
6589 ca0132_config(codec);
6590
d5c016b5
GM		 6591 err = ca0132_prepare_verbs(codec);
6592 if (err < 0)
cc91ceaf 6593 goto error;
d5c016b5 6594
a73d511c
IM		 6595 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
6596 if (err < 0)
cc91ceaf 6597 goto error;
a73d511c 6598
95c6e9cb 6599 return 0;
cc91ceaf
TI		 6600
6601 error:
6602 ca0132_free(codec);
6603 return err;
95c6e9cb
IM		 6604}
6605
6606/*
6607 * patch entries
6608 */
b9a94a9c
TI		 6609static struct hda_device_id snd_hda_id_ca0132[] = {
6610 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 6611 {} /* terminator */
6612};
b9a94a9c 6613MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 6614
6615MODULE_LICENSE("GPL");
406261ce 6616MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 6617
d8a766a1 6618static struct hda_codec_driver ca0132_driver = {
b9a94a9c 6619 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 6620};
6621
d8a766a1 6622module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)