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ALSA: hda - Add hdaudio bus modalias support
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
95c6e9cb
IM		 30#include <sound/core.h>
31#include "hda_codec.h"
32#include "hda_local.h"
128bc4ba 33#include "hda_auto_parser.h"
5aaca44d 34#include "hda_jack.h"
95c6e9cb 35
bcd109c0
IM		 36#include "ca0132_regs.h"
37
ef6b2ead
IM		 38/* Enable this to see controls for tuning purpose. */
39/*#define ENABLE_TUNING_CONTROLS*/
40
41#define FLOAT_ZERO 0x00000000
42#define FLOAT_ONE 0x3f800000
43#define FLOAT_TWO 0x40000000
44#define FLOAT_MINUS_5 0xc0a00000
45
ef6b2ead
IM		 46#define UNSOL_TAG_DSP 0x16
47
4aa3bb0c
IM		 48#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
50
51#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
54
55#define MASTERCONTROL 0x80
ef6b2ead
IM		 56#define MASTERCONTROL_ALLOC_DMA_CHAN 10
57#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 58
95c6e9cb
IM		 59#define WIDGET_CHIP_CTRL 0x15
60#define WIDGET_DSP_CTRL 0x16
61
4aa3bb0c
IM		 62#define MEM_CONNID_MICIN1 3
63#define MEM_CONNID_MICIN2 5
64#define MEM_CONNID_MICOUT1 12
65#define MEM_CONNID_MICOUT2 14
66#define MEM_CONNID_WUH 10
67#define MEM_CONNID_DSP 16
68#define MEM_CONNID_DMIC 100
69
70#define SCP_SET 0
71#define SCP_GET 1
72
01ef7dbf
IM		 73#define EFX_FILE "ctefx.bin"
74
24f3cede 75#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 76MODULE_FIRMWARE(EFX_FILE);
7a527ede 77#endif
01ef7dbf 78
ef6b2ead
IM		 79static char *dirstr[2] = { "Playback", "Capture" };
80
81enum {
82 SPEAKER_OUT,
83 HEADPHONE_OUT
84};
85
86enum {
87 DIGITAL_MIC,
88 LINE_MIC_IN
89};
90
91enum {
92#define VNODE_START_NID 0x80
93 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
94 VNID_MIC,
95 VNID_HP_SEL,
96 VNID_AMIC1_SEL,
97 VNID_HP_ASEL,
98 VNID_AMIC1_ASEL,
99 VNODE_END_NID,
100#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
101
102#define EFFECT_START_NID 0x90
103#define OUT_EFFECT_START_NID EFFECT_START_NID
104 SURROUND = OUT_EFFECT_START_NID,
105 CRYSTALIZER,
106 DIALOG_PLUS,
107 SMART_VOLUME,
108 X_BASS,
109 EQUALIZER,
110 OUT_EFFECT_END_NID,
111#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
112
113#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
114 ECHO_CANCELLATION = IN_EFFECT_START_NID,
115 VOICE_FOCUS,
116 MIC_SVM,
117 NOISE_REDUCTION,
118 IN_EFFECT_END_NID,
119#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
120
121 VOICEFX = IN_EFFECT_END_NID,
122 PLAY_ENHANCEMENT,
123 CRYSTAL_VOICE,
124 EFFECT_END_NID
125#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
126};
127
128/* Effects values size*/
129#define EFFECT_VALS_MAX_COUNT 12
130
e8412ca4
DR		 131/* Latency introduced by DSP blocks in milliseconds. */
132#define DSP_CAPTURE_INIT_LATENCY 0
133#define DSP_CRYSTAL_VOICE_LATENCY 124
134#define DSP_PLAYBACK_INIT_LATENCY 13
135#define DSP_PLAY_ENHANCEMENT_LATENCY 30
136#define DSP_SPEAKER_OUT_LATENCY 7
137
ef6b2ead 138struct ct_effect {
975cc02a 139 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 140 hda_nid_t nid;
141 int mid; /*effect module ID*/
142 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
143 int direct; /* 0:output; 1:input*/
144 int params; /* number of default non-on/off params */
145 /*effect default values, 1st is on/off. */
146 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
147};
148
149#define EFX_DIR_OUT 0
150#define EFX_DIR_IN 1
151
152static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
153 { .name = "Surround",
154 .nid = SURROUND,
155 .mid = 0x96,
156 .reqs = {0, 1},
157 .direct = EFX_DIR_OUT,
158 .params = 1,
159 .def_vals = {0x3F800000, 0x3F2B851F}
160 },
161 { .name = "Crystalizer",
162 .nid = CRYSTALIZER,
163 .mid = 0x96,
164 .reqs = {7, 8},
165 .direct = EFX_DIR_OUT,
166 .params = 1,
167 .def_vals = {0x3F800000, 0x3F266666}
168 },
169 { .name = "Dialog Plus",
170 .nid = DIALOG_PLUS,
171 .mid = 0x96,
172 .reqs = {2, 3},
173 .direct = EFX_DIR_OUT,
174 .params = 1,
175 .def_vals = {0x00000000, 0x3F000000}
176 },
177 { .name = "Smart Volume",
178 .nid = SMART_VOLUME,
179 .mid = 0x96,
180 .reqs = {4, 5, 6},
181 .direct = EFX_DIR_OUT,
182 .params = 2,
183 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
184 },
185 { .name = "X-Bass",
186 .nid = X_BASS,
187 .mid = 0x96,
188 .reqs = {24, 23, 25},
189 .direct = EFX_DIR_OUT,
190 .params = 2,
191 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
192 },
193 { .name = "Equalizer",
194 .nid = EQUALIZER,
195 .mid = 0x96,
196 .reqs = {9, 10, 11, 12, 13, 14,
197 15, 16, 17, 18, 19, 20},
198 .direct = EFX_DIR_OUT,
199 .params = 11,
200 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
201 0x00000000, 0x00000000, 0x00000000, 0x00000000,
202 0x00000000, 0x00000000, 0x00000000, 0x00000000}
203 },
204 { .name = "Echo Cancellation",
205 .nid = ECHO_CANCELLATION,
206 .mid = 0x95,
207 .reqs = {0, 1, 2, 3},
208 .direct = EFX_DIR_IN,
209 .params = 3,
210 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
211 },
212 { .name = "Voice Focus",
213 .nid = VOICE_FOCUS,
214 .mid = 0x95,
215 .reqs = {6, 7, 8, 9},
216 .direct = EFX_DIR_IN,
217 .params = 3,
218 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
219 },
220 { .name = "Mic SVM",
221 .nid = MIC_SVM,
222 .mid = 0x95,
223 .reqs = {44, 45},
224 .direct = EFX_DIR_IN,
225 .params = 1,
226 .def_vals = {0x00000000, 0x3F3D70A4}
227 },
228 { .name = "Noise Reduction",
229 .nid = NOISE_REDUCTION,
230 .mid = 0x95,
231 .reqs = {4, 5},
232 .direct = EFX_DIR_IN,
233 .params = 1,
234 .def_vals = {0x3F800000, 0x3F000000}
235 },
236 { .name = "VoiceFX",
237 .nid = VOICEFX,
238 .mid = 0x95,
239 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
240 .direct = EFX_DIR_IN,
241 .params = 8,
242 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
243 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
244 0x00000000}
245 }
246};
247
248/* Tuning controls */
249#ifdef ENABLE_TUNING_CONTROLS
250
251enum {
252#define TUNING_CTL_START_NID 0xC0
253 WEDGE_ANGLE = TUNING_CTL_START_NID,
254 SVM_LEVEL,
255 EQUALIZER_BAND_0,
256 EQUALIZER_BAND_1,
257 EQUALIZER_BAND_2,
258 EQUALIZER_BAND_3,
259 EQUALIZER_BAND_4,
260 EQUALIZER_BAND_5,
261 EQUALIZER_BAND_6,
262 EQUALIZER_BAND_7,
263 EQUALIZER_BAND_8,
264 EQUALIZER_BAND_9,
265 TUNING_CTL_END_NID
266#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
267};
268
269struct ct_tuning_ctl {
975cc02a 270 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 271 hda_nid_t parent_nid;
272 hda_nid_t nid;
273 int mid; /*effect module ID*/
274 int req; /*effect module request*/
275 int direct; /* 0:output; 1:input*/
276 unsigned int def_val;/*effect default values*/
277};
278
279static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
280 { .name = "Wedge Angle",
281 .parent_nid = VOICE_FOCUS,
282 .nid = WEDGE_ANGLE,
283 .mid = 0x95,
284 .req = 8,
285 .direct = EFX_DIR_IN,
286 .def_val = 0x41F00000
287 },
288 { .name = "SVM Level",
289 .parent_nid = MIC_SVM,
290 .nid = SVM_LEVEL,
291 .mid = 0x95,
292 .req = 45,
293 .direct = EFX_DIR_IN,
294 .def_val = 0x3F3D70A4
295 },
296 { .name = "EQ Band0",
297 .parent_nid = EQUALIZER,
298 .nid = EQUALIZER_BAND_0,
299 .mid = 0x96,
300 .req = 11,
301 .direct = EFX_DIR_OUT,
302 .def_val = 0x00000000
303 },
304 { .name = "EQ Band1",
305 .parent_nid = EQUALIZER,
306 .nid = EQUALIZER_BAND_1,
307 .mid = 0x96,
308 .req = 12,
309 .direct = EFX_DIR_OUT,
310 .def_val = 0x00000000
311 },
312 { .name = "EQ Band2",
313 .parent_nid = EQUALIZER,
314 .nid = EQUALIZER_BAND_2,
315 .mid = 0x96,
316 .req = 13,
317 .direct = EFX_DIR_OUT,
318 .def_val = 0x00000000
319 },
320 { .name = "EQ Band3",
321 .parent_nid = EQUALIZER,
322 .nid = EQUALIZER_BAND_3,
323 .mid = 0x96,
324 .req = 14,
325 .direct = EFX_DIR_OUT,
326 .def_val = 0x00000000
327 },
328 { .name = "EQ Band4",
329 .parent_nid = EQUALIZER,
330 .nid = EQUALIZER_BAND_4,
331 .mid = 0x96,
332 .req = 15,
333 .direct = EFX_DIR_OUT,
334 .def_val = 0x00000000
335 },
336 { .name = "EQ Band5",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_5,
339 .mid = 0x96,
340 .req = 16,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
343 },
344 { .name = "EQ Band6",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_6,
347 .mid = 0x96,
348 .req = 17,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
351 },
352 { .name = "EQ Band7",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_7,
355 .mid = 0x96,
356 .req = 18,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
359 },
360 { .name = "EQ Band8",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_8,
363 .mid = 0x96,
364 .req = 19,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
367 },
368 { .name = "EQ Band9",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_9,
371 .mid = 0x96,
372 .req = 20,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
375 }
376};
377#endif
378
379/* Voice FX Presets */
380#define VOICEFX_MAX_PARAM_COUNT 9
381
382struct ct_voicefx {
383 char *name;
384 hda_nid_t nid;
385 int mid;
386 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
387};
388
389struct ct_voicefx_preset {
390 char *name; /*preset name*/
391 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
392};
393
ccd7bd3d 394static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 395 .name = "VoiceFX Capture Switch",
396 .nid = VOICEFX,
397 .mid = 0x95,
398 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
399};
400
ccd7bd3d 401static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 402 { .name = "Neutral",
403 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
404 0x44FA0000, 0x3F800000, 0x3F800000,
405 0x3F800000, 0x00000000, 0x00000000 }
406 },
407 { .name = "Female2Male",
408 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
409 0x44FA0000, 0x3F19999A, 0x3F866666,
410 0x3F800000, 0x00000000, 0x00000000 }
411 },
412 { .name = "Male2Female",
413 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
414 0x450AC000, 0x4017AE14, 0x3F6B851F,
415 0x3F800000, 0x00000000, 0x00000000 }
416 },
417 { .name = "ScrappyKid",
418 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
419 0x44FA0000, 0x40400000, 0x3F28F5C3,
420 0x3F800000, 0x00000000, 0x00000000 }
421 },
422 { .name = "Elderly",
423 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
424 0x44E10000, 0x3FB33333, 0x3FB9999A,
425 0x3F800000, 0x3E3A2E43, 0x00000000 }
426 },
427 { .name = "Orc",
428 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
429 0x45098000, 0x3F266666, 0x3FC00000,
430 0x3F800000, 0x00000000, 0x00000000 }
431 },
432 { .name = "Elf",
433 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
434 0x45193000, 0x3F8E147B, 0x3F75C28F,
435 0x3F800000, 0x00000000, 0x00000000 }
436 },
437 { .name = "Dwarf",
438 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
439 0x45007000, 0x3F451EB8, 0x3F7851EC,
440 0x3F800000, 0x00000000, 0x00000000 }
441 },
442 { .name = "AlienBrute",
443 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
444 0x451F6000, 0x3F266666, 0x3FA7D945,
445 0x3F800000, 0x3CF5C28F, 0x00000000 }
446 },
447 { .name = "Robot",
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3FB2718B, 0x3F800000,
450 0xBC07010E, 0x00000000, 0x00000000 }
451 },
452 { .name = "Marine",
453 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
454 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
455 0x3F0A3D71, 0x00000000, 0x00000000 }
456 },
457 { .name = "Emo",
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x3F800000, 0x3F800000,
460 0x3E4CCCCD, 0x00000000, 0x00000000 }
461 },
462 { .name = "DeepVoice",
463 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
464 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
465 0x3F800000, 0x00000000, 0x00000000 }
466 },
467 { .name = "Munchkin",
468 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
469 0x44FA0000, 0x3F800000, 0x3F1A043C,
470 0x3F800000, 0x00000000, 0x00000000 }
471 }
472};
473
95c6e9cb
IM		 474enum hda_cmd_vendor_io {
475 /* for DspIO node */
476 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
477 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
478
479 VENDOR_DSPIO_STATUS = 0xF01,
480 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
481 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
482 VENDOR_DSPIO_DSP_INIT = 0x703,
483 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
484 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
485
486 /* for ChipIO node */
487 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
488 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
489 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
490 VENDOR_CHIPIO_DATA_LOW = 0x300,
491 VENDOR_CHIPIO_DATA_HIGH = 0x400,
492
493 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
494 VENDOR_CHIPIO_STATUS = 0xF01,
495 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
496 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
497
4aa3bb0c
IM		 498 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
499 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
500
95c6e9cb 501 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 502 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 503
504 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
505 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
506 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
507 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
508 VENDOR_CHIPIO_FLAG_SET = 0x70F,
509 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 510 VENDOR_CHIPIO_PARAM_SET = 0x710,
511 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 512
513 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
514 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
515 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
516 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
517
4aa3bb0c
IM		 518 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
519 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
520 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
521 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
522
523 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
524 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
525 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
526 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
527 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
528 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
529
530 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 531};
532
533/*
534 * Control flag IDs
535 */
536enum control_flag_id {
537 /* Connection manager stream setup is bypassed/enabled */
538 CONTROL_FLAG_C_MGR = 0,
539 /* DSP DMA is bypassed/enabled */
540 CONTROL_FLAG_DMA = 1,
541 /* 8051 'idle' mode is disabled/enabled */
542 CONTROL_FLAG_IDLE_ENABLE = 2,
543 /* Tracker for the SPDIF-in path is bypassed/enabled */
544 CONTROL_FLAG_TRACKER = 3,
545 /* DigitalOut to Spdif2Out connection is disabled/enabled */
546 CONTROL_FLAG_SPDIF2OUT = 4,
547 /* Digital Microphone is disabled/enabled */
548 CONTROL_FLAG_DMIC = 5,
549 /* ADC_B rate is 48 kHz/96 kHz */
550 CONTROL_FLAG_ADC_B_96KHZ = 6,
551 /* ADC_C rate is 48 kHz/96 kHz */
552 CONTROL_FLAG_ADC_C_96KHZ = 7,
553 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
554 CONTROL_FLAG_DAC_96KHZ = 8,
555 /* DSP rate is 48 kHz/96 kHz */
556 CONTROL_FLAG_DSP_96KHZ = 9,
557 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
558 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
559 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
560 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
561 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
562 CONTROL_FLAG_DECODE_LOOP = 12,
563 /* De-emphasis filter on DAC-1 disabled/enabled */
564 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
565 /* De-emphasis filter on DAC-2 disabled/enabled */
566 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
567 /* De-emphasis filter on DAC-3 disabled/enabled */
568 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
569 /* High-pass filter on ADC_B disabled/enabled */
570 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
571 /* High-pass filter on ADC_C disabled/enabled */
572 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
573 /* Common mode on Port_A disabled/enabled */
574 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
575 /* Common mode on Port_D disabled/enabled */
576 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
577 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
578 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
579 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 580 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 581 /* ASI rate is 48kHz/96kHz */
582 CONTROL_FLAG_ASI_96KHZ = 22,
583 /* DAC power settings able to control attached ports no/yes */
584 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
585 /* Clock Stop OK reporting is disabled/enabled */
586 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
587 /* Number of control flags */
588 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
589};
590
591/*
592 * Control parameter IDs
593 */
4aa3bb0c 594enum control_param_id {
ef6b2ead
IM		 595 /* 0: None, 1: Mic1In*/
596 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 597 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
598 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 599 /* Port A output stage gain setting to use when 16 Ohm output
600 * impedance is selected*/
601 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
602 /* Port D output stage gain setting to use when 16 Ohm output
603 * impedance is selected*/
604 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 605
606 /* Stream Control */
607
608 /* Select stream with the given ID */
609 CONTROL_PARAM_STREAM_ID = 24,
610 /* Source connection point for the selected stream */
611 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
612 /* Destination connection point for the selected stream */
613 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
614 /* Number of audio channels in the selected stream */
615 CONTROL_PARAM_STREAMS_CHANNELS = 27,
616 /*Enable control for the selected stream */
617 CONTROL_PARAM_STREAM_CONTROL = 28,
618
619 /* Connection Point Control */
620
621 /* Select connection point with the given ID */
622 CONTROL_PARAM_CONN_POINT_ID = 29,
623 /* Connection point sample rate */
624 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
625
626 /* Node Control */
627
628 /* Select HDA node with the given ID */
629 CONTROL_PARAM_NODE_ID = 31
630};
631
632/*
633 * Dsp Io Status codes
634 */
635enum hda_vendor_status_dspio {
636 /* Success */
637 VENDOR_STATUS_DSPIO_OK = 0x00,
638 /* Busy, unable to accept new command, the host must retry */
639 VENDOR_STATUS_DSPIO_BUSY = 0x01,
640 /* SCP command queue is full */
641 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
642 /* SCP response queue is empty */
643 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
644};
645
646/*
647 * Chip Io Status codes
648 */
649enum hda_vendor_status_chipio {
650 /* Success */
651 VENDOR_STATUS_CHIPIO_OK = 0x00,
652 /* Busy, unable to accept new command, the host must retry */
653 VENDOR_STATUS_CHIPIO_BUSY = 0x01
654};
655
656/*
657 * CA0132 sample rate
658 */
659enum ca0132_sample_rate {
660 SR_6_000 = 0x00,
661 SR_8_000 = 0x01,
662 SR_9_600 = 0x02,
663 SR_11_025 = 0x03,
664 SR_16_000 = 0x04,
665 SR_22_050 = 0x05,
666 SR_24_000 = 0x06,
667 SR_32_000 = 0x07,
668 SR_44_100 = 0x08,
669 SR_48_000 = 0x09,
670 SR_88_200 = 0x0A,
671 SR_96_000 = 0x0B,
672 SR_144_000 = 0x0C,
673 SR_176_400 = 0x0D,
674 SR_192_000 = 0x0E,
675 SR_384_000 = 0x0F,
676
677 SR_COUNT = 0x10,
678
679 SR_RATE_UNKNOWN = 0x1F
680};
681
01ef7dbf
IM		 682enum dsp_download_state {
683 DSP_DOWNLOAD_FAILED = -1,
684 DSP_DOWNLOAD_INIT = 0,
685 DSP_DOWNLOADING = 1,
686 DSP_DOWNLOADED = 2
687};
688
01ef7dbf
IM		 689/* retrieve parameters from hda format */
690#define get_hdafmt_chs(fmt) (fmt & 0xf)
691#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
692#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
693#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
694
695/*
696 * CA0132 specific
697 */
698
699struct ca0132_spec {
a7e76271
IM		 700 struct snd_kcontrol_new *mixers[5];
701 unsigned int num_mixers;
5aaca44d
IM		 702 const struct hda_verb *base_init_verbs;
703 const struct hda_verb *base_exit_verbs;
d5c016b5
GM		 704 const struct hda_verb *chip_init_verbs;
705 struct hda_verb *spec_init_verbs;
01ef7dbf 706 struct auto_pin_cfg autocfg;
5aaca44d
IM		 707
708 /* Nodes configurations */
01ef7dbf
IM		 709 struct hda_multi_out multiout;
710 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
711 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 712 unsigned int num_outputs;
01ef7dbf
IM		 713 hda_nid_t input_pins[AUTO_PIN_LAST];
714 hda_nid_t adcs[AUTO_PIN_LAST];
715 hda_nid_t dig_out;
716 hda_nid_t dig_in;
717 unsigned int num_inputs;
a7e76271
IM		 718 hda_nid_t shared_mic_nid;
719 hda_nid_t shared_out_nid;
d5c016b5
GM		 720 hda_nid_t unsol_tag_hp;
721 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 722
723 /* chip access */
724 struct mutex chipio_mutex; /* chip access mutex */
725 u32 curr_chip_addx;
726
727 /* DSP download related */
728 enum dsp_download_state dsp_state;
729 unsigned int dsp_stream_id;
730 unsigned int wait_scp;
731 unsigned int wait_scp_header;
732 unsigned int wait_num_data;
733 unsigned int scp_resp_header;
734 unsigned int scp_resp_data[4];
735 unsigned int scp_resp_count;
5aaca44d
IM		 736
737 /* mixer and effects related */
738 unsigned char dmic_ctl;
739 int cur_out_type;
740 int cur_mic_type;
741 long vnode_lvol[VNODES_COUNT];
742 long vnode_rvol[VNODES_COUNT];
743 long vnode_lswitch[VNODES_COUNT];
744 long vnode_rswitch[VNODES_COUNT];
745 long effects_switch[EFFECTS_COUNT];
746 long voicefx_val;
747 long cur_mic_boost;
44f0c978 748
993884f6
CCC		 749 struct hda_codec *codec;
750 struct delayed_work unsol_hp_work;
d5c016b5 751 int quirk;
993884f6 752
44f0c978
IM		 753#ifdef ENABLE_TUNING_CONTROLS
754 long cur_ctl_vals[TUNING_CTLS_COUNT];
755#endif
01ef7dbf
IM		 756};
757
d5c016b5
GM		 758/*
759 * CA0132 quirks table
760 */
761enum {
762 QUIRK_NONE,
763 QUIRK_ALIENWARE,
764};
765
fe14f39e
TI		 766static const struct hda_pintbl alienware_pincfgs[] = {
767 { 0x0b, 0x90170110 }, /* Builtin Speaker */
768 { 0x0c, 0x411111f0 }, /* N/A */
769 { 0x0d, 0x411111f0 }, /* N/A */
770 { 0x0e, 0x411111f0 }, /* N/A */
771 { 0x0f, 0x0321101f }, /* HP */
772 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
773 { 0x11, 0x03a11021 }, /* Mic */
774 { 0x12, 0xd5a30140 }, /* Builtin Mic */
775 { 0x13, 0x411111f0 }, /* N/A */
776 { 0x18, 0x411111f0 }, /* N/A */
777 {}
778};
779
d5c016b5
GM		 780static const struct snd_pci_quirk ca0132_quirks[] = {
781 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15", QUIRK_ALIENWARE),
782 {}
783};
784
01ef7dbf
IM		 785/*
786 * CA0132 codec access
787 */
399ae725 788static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 789 unsigned int verb, unsigned int parm, unsigned int *res)
790{
791 unsigned int response;
792 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
793 *res = response;
794
795 return ((response == -1) ? -1 : 0);
796}
797
798static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
799 unsigned short converter_format, unsigned int *res)
800{
801 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
802 converter_format & 0xffff, res);
803}
804
805static int codec_set_converter_stream_channel(struct hda_codec *codec,
806 hda_nid_t nid, unsigned char stream,
807 unsigned char channel, unsigned int *res)
808{
809 unsigned char converter_stream_channel = 0;
810
811 converter_stream_channel = (stream << 4) | (channel & 0x0f);
812 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
813 converter_stream_channel, res);
814}
815
816/* Chip access helper function */
817static int chipio_send(struct hda_codec *codec,
818 unsigned int reg,
819 unsigned int data)
820{
821 unsigned int res;
6d67530e 822 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 823
824 /* send bits of data specified by reg */
825 do {
826 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
827 reg, data);
828 if (res == VENDOR_STATUS_CHIPIO_OK)
829 return 0;
6d67530e
IM		 830 msleep(20);
831 } while (time_before(jiffies, timeout));
832
01ef7dbf
IM		 833 return -EIO;
834}
835
836/*
837 * Write chip address through the vendor widget -- NOT protected by the Mutex!
838 */
839static int chipio_write_address(struct hda_codec *codec,
840 unsigned int chip_addx)
841{
4861af80 842 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 843 int res;
844
4861af80
IM		 845 if (spec->curr_chip_addx == chip_addx)
846 return 0;
847
01ef7dbf
IM		 848 /* send low 16 bits of the address */
849 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
850 chip_addx & 0xffff);
851
852 if (res != -EIO) {
853 /* send high 16 bits of the address */
854 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
855 chip_addx >> 16);
856 }
857
4861af80 858 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
01ef7dbf 859
4861af80 860 return res;
01ef7dbf
IM		 861}
862
863/*
864 * Write data through the vendor widget -- NOT protected by the Mutex!
865 */
01ef7dbf
IM		 866static int chipio_write_data(struct hda_codec *codec, unsigned int data)
867{
5aaca44d 868 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 869 int res;
870
871 /* send low 16 bits of the data */
872 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
873
874 if (res != -EIO) {
875 /* send high 16 bits of the data */
876 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
877 data >> 16);
878 }
879
5aaca44d
IM		 880 /*If no error encountered, automatically increment the address
881 as per chip behaviour*/
882 spec->curr_chip_addx = (res != -EIO) ?
883 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 884 return res;
885}
886
d5c21b88
IM		 887/*
888 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
889 */
01ef7dbf
IM		 890static int chipio_write_data_multiple(struct hda_codec *codec,
891 const u32 *data,
892 unsigned int count)
893{
894 int status = 0;
895
896 if (data == NULL) {
4e76a883 897 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 898 return -EINVAL;
899 }
900
901 while ((count-- != 0) && (status == 0))
902 status = chipio_write_data(codec, *data++);
903
904 return status;
905}
906
907
908/*
909 * Read data through the vendor widget -- NOT protected by the Mutex!
910 */
911static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
912{
5aaca44d 913 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 914 int res;
915
916 /* post read */
917 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
918
919 if (res != -EIO) {
920 /* read status */
921 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
922 }
923
924 if (res != -EIO) {
925 /* read data */
926 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
927 VENDOR_CHIPIO_HIC_READ_DATA,
928 0);
929 }
930
5aaca44d
IM		 931 /*If no error encountered, automatically increment the address
932 as per chip behaviour*/
933 spec->curr_chip_addx = (res != -EIO) ?
934 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 935 return res;
936}
937
938/*
939 * Write given value to the given address through the chip I/O widget.
940 * protected by the Mutex
941 */
942static int chipio_write(struct hda_codec *codec,
943 unsigned int chip_addx, const unsigned int data)
944{
945 struct ca0132_spec *spec = codec->spec;
946 int err;
947
948 mutex_lock(&spec->chipio_mutex);
949
950 /* write the address, and if successful proceed to write data */
951 err = chipio_write_address(codec, chip_addx);
952 if (err < 0)
953 goto exit;
954
955 err = chipio_write_data(codec, data);
956 if (err < 0)
957 goto exit;
958
959exit:
960 mutex_unlock(&spec->chipio_mutex);
961 return err;
962}
963
d5c21b88
IM		 964/*
965 * Write multiple values to the given address through the chip I/O widget.
966 * protected by the Mutex
967 */
01ef7dbf
IM		 968static int chipio_write_multiple(struct hda_codec *codec,
969 u32 chip_addx,
970 const u32 *data,
971 unsigned int count)
972{
973 struct ca0132_spec *spec = codec->spec;
974 int status;
975
976 mutex_lock(&spec->chipio_mutex);
4861af80 977 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 978 if (status < 0)
979 goto error;
980
981 status = chipio_write_data_multiple(codec, data, count);
982error:
983 mutex_unlock(&spec->chipio_mutex);
984
985 return status;
986}
987
988/*
989 * Read the given address through the chip I/O widget
990 * protected by the Mutex
991 */
992static int chipio_read(struct hda_codec *codec,
993 unsigned int chip_addx, unsigned int *data)
994{
995 struct ca0132_spec *spec = codec->spec;
996 int err;
997
998 mutex_lock(&spec->chipio_mutex);
999
1000 /* write the address, and if successful proceed to write data */
1001 err = chipio_write_address(codec, chip_addx);
1002 if (err < 0)
1003 goto exit;
1004
1005 err = chipio_read_data(codec, data);
1006 if (err < 0)
1007 goto exit;
1008
1009exit:
1010 mutex_unlock(&spec->chipio_mutex);
1011 return err;
1012}
1013
d5c21b88
IM		 1014/*
1015 * Set chip control flags through the chip I/O widget.
1016 */
01ef7dbf
IM		 1017static void chipio_set_control_flag(struct hda_codec *codec,
1018 enum control_flag_id flag_id,
1019 bool flag_state)
1020{
1021 unsigned int val;
1022 unsigned int flag_bit;
1023
1024 flag_bit = (flag_state ? 1 : 0);
1025 val = (flag_bit << 7) | (flag_id);
1026 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1027 VENDOR_CHIPIO_FLAG_SET, val);
1028}
1029
d5c21b88
IM		 1030/*
1031 * Set chip parameters through the chip I/O widget.
1032 */
01ef7dbf
IM		 1033static void chipio_set_control_param(struct hda_codec *codec,
1034 enum control_param_id param_id, int param_val)
1035{
1036 struct ca0132_spec *spec = codec->spec;
1037 int val;
1038
1039 if ((param_id < 32) && (param_val < 8)) {
1040 val = (param_val << 5) | (param_id);
1041 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1042 VENDOR_CHIPIO_PARAM_SET, val);
1043 } else {
1044 mutex_lock(&spec->chipio_mutex);
1045 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1046 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1047 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1048 param_id);
1049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1050 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1051 param_val);
1052 }
1053 mutex_unlock(&spec->chipio_mutex);
1054 }
1055}
1056
d5c21b88
IM		 1057/*
1058 * Set sampling rate of the connection point.
1059 */
01ef7dbf
IM		 1060static void chipio_set_conn_rate(struct hda_codec *codec,
1061 int connid, enum ca0132_sample_rate rate)
1062{
1063 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1064 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1065 rate);
1066}
1067
d5c21b88
IM		 1068/*
1069 * Enable clocks.
1070 */
01ef7dbf
IM		 1071static void chipio_enable_clocks(struct hda_codec *codec)
1072{
1073 struct ca0132_spec *spec = codec->spec;
1074
1075 mutex_lock(&spec->chipio_mutex);
1076 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1077 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1078 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1079 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1080 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1081 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1082 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1083 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1084 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1085 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1087 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1088 mutex_unlock(&spec->chipio_mutex);
1089}
1090
1091/*
1092 * CA0132 DSP IO stuffs
1093 */
1094static int dspio_send(struct hda_codec *codec, unsigned int reg,
1095 unsigned int data)
1096{
b645d796 1097 int res;
6d67530e 1098 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1099
1100 /* send bits of data specified by reg to dsp */
1101 do {
1102 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1103 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1104 return res;
6d67530e
IM		 1105 msleep(20);
1106 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1107
1108 return -EIO;
1109}
1110
d5c21b88
IM		 1111/*
1112 * Wait for DSP to be ready for commands
1113 */
01ef7dbf
IM		 1114static void dspio_write_wait(struct hda_codec *codec)
1115{
4861af80
IM		 1116 int status;
1117 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1118
01ef7dbf 1119 do {
4861af80
IM		 1120 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1121 VENDOR_DSPIO_STATUS, 0);
1122 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1123 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1124 break;
1125 msleep(1);
1126 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1127}
1128
d5c21b88
IM		 1129/*
1130 * Write SCP data to DSP
1131 */
01ef7dbf
IM		 1132static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1133{
1134 struct ca0132_spec *spec = codec->spec;
1135 int status;
1136
1137 dspio_write_wait(codec);
1138
1139 mutex_lock(&spec->chipio_mutex);
1140 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1141 scp_data & 0xffff);
1142 if (status < 0)
1143 goto error;
1144
1145 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1146 scp_data >> 16);
1147 if (status < 0)
1148 goto error;
1149
1150 /* OK, now check if the write itself has executed*/
1151 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1152 VENDOR_DSPIO_STATUS, 0);
1153error:
1154 mutex_unlock(&spec->chipio_mutex);
1155
1156 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1157 -EIO : 0;
1158}
1159
d5c21b88
IM		 1160/*
1161 * Write multiple SCP data to DSP
1162 */
01ef7dbf
IM		 1163static int dspio_write_multiple(struct hda_codec *codec,
1164 unsigned int *buffer, unsigned int size)
1165{
1166 int status = 0;
1167 unsigned int count;
1168
1169 if ((buffer == NULL))
1170 return -EINVAL;
1171
1172 count = 0;
1173 while (count < size) {
1174 status = dspio_write(codec, *buffer++);
1175 if (status != 0)
1176 break;
1177 count++;
1178 }
1179
1180 return status;
1181}
1182
a73d511c
IM		 1183static int dspio_read(struct hda_codec *codec, unsigned int *data)
1184{
1185 int status;
1186
1187 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1188 if (status == -EIO)
1189 return status;
1190
1191 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1192 if (status == -EIO ||
1193 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1194 return -EIO;
1195
1196 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1197 VENDOR_DSPIO_SCP_READ_DATA, 0);
1198
1199 return 0;
1200}
1201
1202static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1203 unsigned int *buf_size, unsigned int size_count)
1204{
1205 int status = 0;
1206 unsigned int size = *buf_size;
1207 unsigned int count;
1208 unsigned int skip_count;
1209 unsigned int dummy;
1210
1211 if ((buffer == NULL))
1212 return -1;
1213
1214 count = 0;
1215 while (count < size && count < size_count) {
1216 status = dspio_read(codec, buffer++);
1217 if (status != 0)
1218 break;
1219 count++;
1220 }
1221
1222 skip_count = count;
1223 if (status == 0) {
1224 while (skip_count < size) {
1225 status = dspio_read(codec, &dummy);
1226 if (status != 0)
1227 break;
1228 skip_count++;
1229 }
1230 }
1231 *buf_size = count;
1232
1233 return status;
1234}
1235
d5c21b88
IM		 1236/*
1237 * Construct the SCP header using corresponding fields
1238 */
01ef7dbf
IM		 1239static inline unsigned int
1240make_scp_header(unsigned int target_id, unsigned int source_id,
1241 unsigned int get_flag, unsigned int req,
1242 unsigned int device_flag, unsigned int resp_flag,
1243 unsigned int error_flag, unsigned int data_size)
1244{
1245 unsigned int header = 0;
1246
1247 header = (data_size & 0x1f) << 27;
1248 header |= (error_flag & 0x01) << 26;
1249 header |= (resp_flag & 0x01) << 25;
1250 header |= (device_flag & 0x01) << 24;
1251 header |= (req & 0x7f) << 17;
1252 header |= (get_flag & 0x01) << 16;
1253 header |= (source_id & 0xff) << 8;
1254 header |= target_id & 0xff;
1255
1256 return header;
1257}
1258
d5c21b88
IM		 1259/*
1260 * Extract corresponding fields from SCP header
1261 */
01ef7dbf
IM		 1262static inline void
1263extract_scp_header(unsigned int header,
1264 unsigned int *target_id, unsigned int *source_id,
1265 unsigned int *get_flag, unsigned int *req,
1266 unsigned int *device_flag, unsigned int *resp_flag,
1267 unsigned int *error_flag, unsigned int *data_size)
1268{
1269 if (data_size)
1270 *data_size = (header >> 27) & 0x1f;
1271 if (error_flag)
1272 *error_flag = (header >> 26) & 0x01;
1273 if (resp_flag)
1274 *resp_flag = (header >> 25) & 0x01;
1275 if (device_flag)
1276 *device_flag = (header >> 24) & 0x01;
1277 if (req)
1278 *req = (header >> 17) & 0x7f;
1279 if (get_flag)
1280 *get_flag = (header >> 16) & 0x01;
1281 if (source_id)
1282 *source_id = (header >> 8) & 0xff;
1283 if (target_id)
1284 *target_id = header & 0xff;
1285}
1286
1287#define SCP_MAX_DATA_WORDS (16)
1288
1289/* Structure to contain any SCP message */
1290struct scp_msg {
1291 unsigned int hdr;
1292 unsigned int data[SCP_MAX_DATA_WORDS];
1293};
1294
a73d511c
IM		 1295static void dspio_clear_response_queue(struct hda_codec *codec)
1296{
1297 unsigned int dummy = 0;
1298 int status = -1;
1299
1300 /* clear all from the response queue */
1301 do {
1302 status = dspio_read(codec, &dummy);
1303 } while (status == 0);
1304}
1305
1306static int dspio_get_response_data(struct hda_codec *codec)
1307{
1308 struct ca0132_spec *spec = codec->spec;
1309 unsigned int data = 0;
1310 unsigned int count;
1311
1312 if (dspio_read(codec, &data) < 0)
1313 return -EIO;
1314
1315 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1316 spec->scp_resp_header = data;
1317 spec->scp_resp_count = data >> 27;
1318 count = spec->wait_num_data;
1319 dspio_read_multiple(codec, spec->scp_resp_data,
1320 &spec->scp_resp_count, count);
1321 return 0;
1322 }
1323
1324 return -EIO;
1325}
1326
d5c21b88
IM		 1327/*
1328 * Send SCP message to DSP
1329 */
01ef7dbf
IM		 1330static int dspio_send_scp_message(struct hda_codec *codec,
1331 unsigned char *send_buf,
1332 unsigned int send_buf_size,
1333 unsigned char *return_buf,
1334 unsigned int return_buf_size,
1335 unsigned int *bytes_returned)
1336{
1337 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1338 int status = -1;
1339 unsigned int scp_send_size = 0;
1340 unsigned int total_size;
1341 bool waiting_for_resp = false;
1342 unsigned int header;
1343 struct scp_msg *ret_msg;
1344 unsigned int resp_src_id, resp_target_id;
1345 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1346
1347 if (bytes_returned)
1348 *bytes_returned = 0;
1349
1350 /* get scp header from buffer */
1351 header = *((unsigned int *)send_buf);
1352 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1353 &device_flag, NULL, NULL, &data_size);
1354 scp_send_size = data_size + 1;
1355 total_size = (scp_send_size * 4);
1356
1357 if (send_buf_size < total_size)
1358 return -EINVAL;
1359
1360 if (get_flag || device_flag) {
1361 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1362 return -EINVAL;
1363
1364 spec->wait_scp_header = *((unsigned int *)send_buf);
1365
1366 /* swap source id with target id */
1367 resp_target_id = src_id;
1368 resp_src_id = target_id;
1369 spec->wait_scp_header &= 0xffff0000;
1370 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1371 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1372 spec->wait_scp = 1;
1373 waiting_for_resp = true;
1374 }
1375
1376 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1377 scp_send_size);
1378 if (status < 0) {
1379 spec->wait_scp = 0;
1380 return status;
1381 }
1382
1383 if (waiting_for_resp) {
6d67530e 1384 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1385 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1386 do {
1387 msleep(20);
6d67530e 1388 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1389 waiting_for_resp = false;
6d67530e 1390 if (!spec->wait_scp) {
01ef7dbf
IM		 1391 ret_msg = (struct scp_msg *)return_buf;
1392 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1393 memcpy(&ret_msg->data, spec->scp_resp_data,
1394 spec->wait_num_data);
1395 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1396 status = 0;
1397 } else {
1398 status = -EIO;
1399 }
1400 spec->wait_scp = 0;
1401 }
1402
1403 return status;
1404}
1405
d5c21b88
IM		 1406/**
1407 * Prepare and send the SCP message to DSP
1408 * @codec: the HDA codec
1409 * @mod_id: ID of the DSP module to send the command
1410 * @req: ID of request to send to the DSP module
1411 * @dir: SET or GET
1412 * @data: pointer to the data to send with the request, request specific
1413 * @len: length of the data, in bytes
1414 * @reply: point to the buffer to hold data returned for a reply
1415 * @reply_len: length of the reply buffer returned from GET
1416 *
1417 * Returns zero or a negative error code.
1418 */
01ef7dbf
IM		 1419static int dspio_scp(struct hda_codec *codec,
1420 int mod_id, int req, int dir, void *data, unsigned int len,
1421 void *reply, unsigned int *reply_len)
1422{
1423 int status = 0;
1424 struct scp_msg scp_send, scp_reply;
1425 unsigned int ret_bytes, send_size, ret_size;
1426 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1427 unsigned int reply_data_size;
1428
1429 memset(&scp_send, 0, sizeof(scp_send));
1430 memset(&scp_reply, 0, sizeof(scp_reply));
1431
1432 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1433 return -EINVAL;
1434
1435 if (dir == SCP_GET && reply == NULL) {
4e76a883 1436 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1437 return -EINVAL;
1438 }
1439
1440 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1441 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1442 return -EINVAL;
1443 }
1444
1445 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1446 0, 0, 0, len/sizeof(unsigned int));
1447 if (data != NULL && len > 0) {
1448 len = min((unsigned int)(sizeof(scp_send.data)), len);
1449 memcpy(scp_send.data, data, len);
1450 }
1451
1452 ret_bytes = 0;
1453 send_size = sizeof(unsigned int) + len;
1454 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1455 send_size, (unsigned char *)&scp_reply,
1456 sizeof(scp_reply), &ret_bytes);
1457
1458 if (status < 0) {
4e76a883 1459 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1460 return status;
1461 }
1462
1463 /* extract send and reply headers members */
1464 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1465 NULL, NULL, NULL, NULL, NULL);
1466 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1467 &reply_resp_flag, &reply_error_flag,
1468 &reply_data_size);
1469
1470 if (!send_get_flag)
1471 return 0;
1472
1473 if (reply_resp_flag && !reply_error_flag) {
1474 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1475 / sizeof(unsigned int);
1476
1477 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1478 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1479 return -EINVAL;
1480 } else if (ret_size != reply_data_size) {
4e76a883 1481 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf
IM		 1482 return -EINVAL;
1483 } else {
1484 *reply_len = ret_size*sizeof(unsigned int);
1485 memcpy(reply, scp_reply.data, *reply_len);
1486 }
1487 } else {
4e76a883 1488 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1489 return -EIO;
1490 }
1491
1492 return status;
1493}
1494
5aaca44d
IM		 1495/*
1496 * Set DSP parameters
1497 */
1498static int dspio_set_param(struct hda_codec *codec, int mod_id,
1499 int req, void *data, unsigned int len)
1500{
1501 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1502}
1503
1504static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1505 int req, unsigned int data)
1506{
1507 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1508}
1509
d5c21b88
IM		 1510/*
1511 * Allocate a DSP DMA channel via an SCP message
1512 */
01ef7dbf
IM		 1513static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1514{
1515 int status = 0;
1516 unsigned int size = sizeof(dma_chan);
1517
4e76a883 1518 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
01ef7dbf
IM		 1519 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1520 SCP_GET, NULL, 0, dma_chan, &size);
1521
1522 if (status < 0) {
4e76a883 1523 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1524 return status;
1525 }
1526
1527 if ((*dma_chan + 1) == 0) {
4e76a883 1528 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1529 return -EBUSY;
1530 }
1531
4e76a883
TI		 1532 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1533 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1534
1535 return status;
1536}
1537
d5c21b88
IM		 1538/*
1539 * Free a DSP DMA via an SCP message
1540 */
01ef7dbf
IM		 1541static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1542{
1543 int status = 0;
1544 unsigned int dummy = 0;
1545
4e76a883
TI		 1546 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1547 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf
IM		 1548
1549 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1550 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1551
1552 if (status < 0) {
4e76a883 1553 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1554 return status;
1555 }
1556
4e76a883 1557 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1558
1559 return status;
1560}
1561
1562/*
d5c21b88 1563 * (Re)start the DSP
01ef7dbf
IM		 1564 */
1565static int dsp_set_run_state(struct hda_codec *codec)
1566{
1567 unsigned int dbg_ctrl_reg;
1568 unsigned int halt_state;
1569 int err;
1570
1571 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1572 if (err < 0)
1573 return err;
1574
1575 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1576 DSP_DBGCNTL_STATE_LOBIT;
1577
1578 if (halt_state != 0) {
1579 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1580 DSP_DBGCNTL_SS_MASK);
1581 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1582 dbg_ctrl_reg);
1583 if (err < 0)
1584 return err;
1585
1586 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1587 DSP_DBGCNTL_EXEC_MASK;
1588 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1589 dbg_ctrl_reg);
1590 if (err < 0)
1591 return err;
1592 }
1593
1594 return 0;
1595}
1596
d5c21b88
IM		 1597/*
1598 * Reset the DSP
1599 */
01ef7dbf
IM		 1600static int dsp_reset(struct hda_codec *codec)
1601{
1602 unsigned int res;
1603 int retry = 20;
1604
4e76a883 1605 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1606 do {
1607 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1608 retry--;
1609 } while (res == -EIO && retry);
1610
1611 if (!retry) {
4e76a883 1612 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1613 return -EIO;
1614 }
1615
1616 return 0;
1617}
1618
d5c21b88
IM		 1619/*
1620 * Convert chip address to DSP address
1621 */
01ef7dbf
IM		 1622static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1623 bool *code, bool *yram)
1624{
1625 *code = *yram = false;
1626
1627 if (UC_RANGE(chip_addx, 1)) {
1628 *code = true;
1629 return UC_OFF(chip_addx);
1630 } else if (X_RANGE_ALL(chip_addx, 1)) {
1631 return X_OFF(chip_addx);
1632 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1633 *yram = true;
1634 return Y_OFF(chip_addx);
1635 }
1636
4a8b89f9 1637 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 1638}
1639
d5c21b88
IM		 1640/*
1641 * Check if the DSP DMA is active
1642 */
01ef7dbf
IM		 1643static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1644{
1645 unsigned int dma_chnlstart_reg;
1646
1647 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1648
1649 return ((dma_chnlstart_reg & (1 <<
1650 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1651}
1652
1653static int dsp_dma_setup_common(struct hda_codec *codec,
1654 unsigned int chip_addx,
1655 unsigned int dma_chan,
1656 unsigned int port_map_mask,
1657 bool ovly)
1658{
1659 int status = 0;
1660 unsigned int chnl_prop;
1661 unsigned int dsp_addx;
1662 unsigned int active;
1663 bool code, yram;
1664
4e76a883 1665 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 1666
1667 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 1668 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 1669 return -EINVAL;
1670 }
1671
1672 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 1673 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 1674 return -EBUSY;
1675 }
1676
1677 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1678
1679 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1680 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1681 return -ENXIO;
1682 }
1683
1684 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1685 active = 0;
1686
4e76a883 1687 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 1688
1689 if (ovly) {
1690 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1691 &chnl_prop);
1692
1693 if (status < 0) {
4e76a883 1694 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 1695 return status;
1696 }
4e76a883 1697 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 1698 }
1699
1700 if (!code)
1701 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1702 else
1703 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1704
1705 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1706
1707 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1708 if (status < 0) {
4e76a883 1709 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 1710 return status;
1711 }
4e76a883 1712 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 1713
1714 if (ovly) {
1715 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1716 &active);
1717
1718 if (status < 0) {
4e76a883 1719 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 1720 return status;
1721 }
4e76a883 1722 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 1723 }
1724
1725 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1726 DSPDMAC_ACTIVE_AAR_MASK;
1727
1728 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1729 if (status < 0) {
4e76a883 1730 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 1731 return status;
1732 }
1733
4e76a883 1734 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 1735
1736 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1737 port_map_mask);
1738 if (status < 0) {
4e76a883 1739 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 1740 return status;
1741 }
4e76a883 1742 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 1743
1744 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1745 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1746 if (status < 0) {
4e76a883 1747 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 1748 return status;
1749 }
4e76a883 1750 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 1751
4e76a883 1752 codec_dbg(codec,
01ef7dbf
IM		 1753 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1754 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1755 chip_addx, dsp_addx, dma_chan,
1756 port_map_mask, chnl_prop, active);
1757
4e76a883 1758 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 1759
1760 return 0;
1761}
1762
d5c21b88
IM		 1763/*
1764 * Setup the DSP DMA per-transfer-specific registers
1765 */
01ef7dbf
IM		 1766static int dsp_dma_setup(struct hda_codec *codec,
1767 unsigned int chip_addx,
1768 unsigned int count,
1769 unsigned int dma_chan)
1770{
1771 int status = 0;
1772 bool code, yram;
1773 unsigned int dsp_addx;
1774 unsigned int addr_field;
1775 unsigned int incr_field;
1776 unsigned int base_cnt;
1777 unsigned int cur_cnt;
1778 unsigned int dma_cfg = 0;
1779 unsigned int adr_ofs = 0;
1780 unsigned int xfr_cnt = 0;
1781 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1782 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1783
4e76a883 1784 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 1785
1786 if (count > max_dma_count) {
4e76a883 1787 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 1788 return -EINVAL;
1789 }
1790
1791 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1792 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1793 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1794 return -ENXIO;
1795 }
1796
4e76a883 1797 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 1798
1799 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1800 incr_field = 0;
1801
1802 if (!code) {
1803 addr_field <<= 1;
1804 if (yram)
1805 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1806
1807 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1808 }
1809
1810 dma_cfg = addr_field + incr_field;
1811 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1812 dma_cfg);
1813 if (status < 0) {
4e76a883 1814 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 1815 return status;
1816 }
4e76a883 1817 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 1818
1819 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1820 (code ? 0 : 1));
1821
1822 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1823 adr_ofs);
1824 if (status < 0) {
4e76a883 1825 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 1826 return status;
1827 }
4e76a883 1828 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 1829
1830 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1831
1832 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1833
1834 xfr_cnt = base_cnt | cur_cnt;
1835
1836 status = chipio_write(codec,
1837 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1838 if (status < 0) {
4e76a883 1839 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 1840 return status;
1841 }
4e76a883 1842 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 1843
4e76a883 1844 codec_dbg(codec,
01ef7dbf
IM		 1845 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1846 "ADROFS=0x%x, XFRCNT=0x%x\n",
1847 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1848
4e76a883 1849 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 1850
1851 return 0;
1852}
1853
d5c21b88
IM		 1854/*
1855 * Start the DSP DMA
1856 */
01ef7dbf
IM		 1857static int dsp_dma_start(struct hda_codec *codec,
1858 unsigned int dma_chan, bool ovly)
1859{
1860 unsigned int reg = 0;
1861 int status = 0;
1862
4e76a883 1863 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 1864
1865 if (ovly) {
1866 status = chipio_read(codec,
1867 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1868
1869 if (status < 0) {
4e76a883 1870 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1871 return status;
1872 }
4e76a883 1873 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 1874
1875 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1876 DSPDMAC_CHNLSTART_DIS_MASK);
1877 }
1878
1879 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1880 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1881 if (status < 0) {
4e76a883 1882 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1883 return status;
1884 }
4e76a883 1885 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 1886
1887 return status;
1888}
1889
d5c21b88
IM		 1890/*
1891 * Stop the DSP DMA
1892 */
01ef7dbf
IM		 1893static int dsp_dma_stop(struct hda_codec *codec,
1894 unsigned int dma_chan, bool ovly)
1895{
1896 unsigned int reg = 0;
1897 int status = 0;
1898
4e76a883 1899 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 1900
1901 if (ovly) {
1902 status = chipio_read(codec,
1903 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1904
1905 if (status < 0) {
4e76a883 1906 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1907 return status;
1908 }
4e76a883 1909 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 1910 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1911 DSPDMAC_CHNLSTART_DIS_MASK);
1912 }
1913
1914 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1915 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1916 if (status < 0) {
4e76a883 1917 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1918 return status;
1919 }
4e76a883 1920 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 1921
1922 return status;
1923}
1924
d5c21b88
IM		 1925/**
1926 * Allocate router ports
1927 *
1928 * @codec: the HDA codec
1929 * @num_chans: number of channels in the stream
1930 * @ports_per_channel: number of ports per channel
1931 * @start_device: start device
1932 * @port_map: pointer to the port list to hold the allocated ports
1933 *
1934 * Returns zero or a negative error code.
1935 */
01ef7dbf
IM		 1936static int dsp_allocate_router_ports(struct hda_codec *codec,
1937 unsigned int num_chans,
1938 unsigned int ports_per_channel,
1939 unsigned int start_device,
1940 unsigned int *port_map)
1941{
1942 int status = 0;
1943 int res;
1944 u8 val;
1945
1946 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1947 if (status < 0)
1948 return status;
1949
1950 val = start_device << 6;
1951 val |= (ports_per_channel - 1) << 4;
1952 val |= num_chans - 1;
1953
1954 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1955 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1956 val);
1957
1958 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1959 VENDOR_CHIPIO_PORT_ALLOC_SET,
1960 MEM_CONNID_DSP);
1961
1962 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1963 if (status < 0)
1964 return status;
1965
1966 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1967 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1968
1969 *port_map = res;
1970
1971 return (res < 0) ? res : 0;
1972}
1973
d5c21b88
IM		 1974/*
1975 * Free router ports
1976 */
01ef7dbf
IM		 1977static int dsp_free_router_ports(struct hda_codec *codec)
1978{
1979 int status = 0;
1980
1981 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1982 if (status < 0)
1983 return status;
1984
1985 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1986 VENDOR_CHIPIO_PORT_FREE_SET,
1987 MEM_CONNID_DSP);
1988
1989 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1990
1991 return status;
1992}
1993
d5c21b88
IM		 1994/*
1995 * Allocate DSP ports for the download stream
1996 */
01ef7dbf
IM		 1997static int dsp_allocate_ports(struct hda_codec *codec,
1998 unsigned int num_chans,
1999 unsigned int rate_multi, unsigned int *port_map)
2000{
2001 int status;
2002
4e76a883 2003 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2004
2005 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2006 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2007 return -EINVAL;
2008 }
2009
2010 status = dsp_allocate_router_ports(codec, num_chans,
2011 rate_multi, 0, port_map);
2012
4e76a883 2013 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2014
2015 return status;
2016}
2017
01ef7dbf
IM		 2018static int dsp_allocate_ports_format(struct hda_codec *codec,
2019 const unsigned short fmt,
2020 unsigned int *port_map)
2021{
2022 int status;
2023 unsigned int num_chans;
2024
2025 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2026 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2027 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2028
2029 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2030 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2031 return -EINVAL;
2032 }
2033
2034 num_chans = get_hdafmt_chs(fmt) + 1;
2035
2036 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2037
2038 return status;
2039}
2040
d5c21b88
IM		 2041/*
2042 * free DSP ports
2043 */
2044static int dsp_free_ports(struct hda_codec *codec)
2045{
2046 int status;
2047
4e76a883 2048 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2049
2050 status = dsp_free_router_ports(codec);
2051 if (status < 0) {
4e76a883 2052 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2053 return status;
2054 }
4e76a883 2055 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2056
2057 return status;
2058}
2059
01ef7dbf
IM		 2060/*
2061 * HDA DMA engine stuffs for DSP code download
2062 */
2063struct dma_engine {
2064 struct hda_codec *codec;
2065 unsigned short m_converter_format;
2066 struct snd_dma_buffer *dmab;
2067 unsigned int buf_size;
2068};
2069
2070
2071enum dma_state {
2072 DMA_STATE_STOP = 0,
2073 DMA_STATE_RUN = 1
2074};
2075
6194b99d 2076static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2077 unsigned int sample_rate,
2078 unsigned short channels,
01ef7dbf
IM		 2079 unsigned short *hda_format)
2080{
2081 unsigned int format_val;
2082
b7d023e1
TI		 2083 format_val = snd_hdac_calc_stream_format(sample_rate,
2084 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2085
2086 if (hda_format)
2087 *hda_format = (unsigned short)format_val;
2088
2089 return 0;
2090}
2091
d5c21b88
IM		 2092/*
2093 * Reset DMA for DSP download
2094 */
01ef7dbf
IM		 2095static int dma_reset(struct dma_engine *dma)
2096{
2097 struct hda_codec *codec = dma->codec;
2098 struct ca0132_spec *spec = codec->spec;
2099 int status;
2100
b3667bd7 2101 if (dma->dmab->area)
01ef7dbf
IM		 2102 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2103
2104 status = snd_hda_codec_load_dsp_prepare(codec,
2105 dma->m_converter_format,
2106 dma->buf_size,
2107 dma->dmab);
2108 if (status < 0)
2109 return status;
2110 spec->dsp_stream_id = status;
2111 return 0;
2112}
2113
2114static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2115{
01ef7dbf
IM		 2116 bool cmd;
2117
01ef7dbf
IM		 2118 switch (state) {
2119 case DMA_STATE_STOP:
2120 cmd = false;
2121 break;
2122 case DMA_STATE_RUN:
2123 cmd = true;
2124 break;
2125 default:
c41999a2
DH		 2126 return 0;
2127 }
01ef7dbf
IM		 2128
2129 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2130 return 0;
95c6e9cb
IM		 2131}
2132
01ef7dbf
IM		 2133static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2134{
2135 return dma->dmab->bytes;
2136}
95c6e9cb 2137
01ef7dbf
IM		 2138static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2139{
2140 return dma->dmab->area;
2141}
95c6e9cb 2142
01ef7dbf
IM		 2143static int dma_xfer(struct dma_engine *dma,
2144 const unsigned int *data,
2145 unsigned int count)
2146{
2147 memcpy(dma->dmab->area, data, count);
2148 return 0;
2149}
95c6e9cb 2150
01ef7dbf
IM		 2151static void dma_get_converter_format(
2152 struct dma_engine *dma,
2153 unsigned short *format)
2154{
2155 if (format)
2156 *format = dma->m_converter_format;
2157}
95c6e9cb 2158
01ef7dbf 2159static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2160{
01ef7dbf 2161 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2162
01ef7dbf 2163 return spec->dsp_stream_id;
95c6e9cb
IM		 2164}
2165
01ef7dbf
IM		 2166struct dsp_image_seg {
2167 u32 magic;
2168 u32 chip_addr;
2169 u32 count;
2170 u32 data[0];
2171};
2172
2173static const u32 g_magic_value = 0x4c46584d;
2174static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2175
2176static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2177{
01ef7dbf
IM		 2178 return p->magic == g_magic_value;
2179}
95c6e9cb 2180
01ef7dbf
IM		 2181static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2182{
2183 return g_chip_addr_magic_value == p->chip_addr;
2184}
95c6e9cb 2185
01ef7dbf
IM		 2186static bool is_last(const struct dsp_image_seg *p)
2187{
2188 return p->count == 0;
2189}
95c6e9cb 2190
01ef7dbf
IM		 2191static size_t dsp_sizeof(const struct dsp_image_seg *p)
2192{
2193 return sizeof(*p) + p->count*sizeof(u32);
2194}
2195
2196static const struct dsp_image_seg *get_next_seg_ptr(
2197 const struct dsp_image_seg *p)
2198{
2199 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2200}
2201
2202/*
01ef7dbf 2203 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2204 */
8ae3124b 2205#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2206
d5c21b88
IM		 2207/*
2208 * Program a list of address/data pairs via the ChipIO widget.
2209 * The segment data is in the format of successive pairs of words.
2210 * These are repeated as indicated by the segment's count field.
2211 */
01ef7dbf
IM		 2212static int dspxfr_hci_write(struct hda_codec *codec,
2213 const struct dsp_image_seg *fls)
95c6e9cb 2214{
01ef7dbf
IM		 2215 int status;
2216 const u32 *data;
2217 unsigned int count;
95c6e9cb 2218
01ef7dbf 2219 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2220 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2221 return -EINVAL;
95c6e9cb
IM		 2222 }
2223
01ef7dbf
IM		 2224 count = fls->count;
2225 data = (u32 *)(fls->data);
2226 while (count >= 2) {
2227 status = chipio_write(codec, data[0], data[1]);
2228 if (status < 0) {
4e76a883 2229 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2230 return status;
2231 }
2232 count -= 2;
2233 data += 2;
2234 }
2235 return 0;
95c6e9cb
IM		 2236}
2237
d5c21b88
IM		 2238/**
2239 * Write a block of data into DSP code or data RAM using pre-allocated
2240 * DMA engine.
2241 *
2242 * @codec: the HDA codec
2243 * @fls: pointer to a fast load image
2244 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2245 * no relocation
2246 * @dma_engine: pointer to DMA engine to be used for DSP download
2247 * @dma_chan: The number of DMA channels used for DSP download
2248 * @port_map_mask: port mapping
2249 * @ovly: TRUE if overlay format is required
2250 *
2251 * Returns zero or a negative error code.
2252 */
01ef7dbf
IM		 2253static int dspxfr_one_seg(struct hda_codec *codec,
2254 const struct dsp_image_seg *fls,
2255 unsigned int reloc,
2256 struct dma_engine *dma_engine,
2257 unsigned int dma_chan,
2258 unsigned int port_map_mask,
2259 bool ovly)
95c6e9cb 2260{
406261ce 2261 int status = 0;
01ef7dbf
IM		 2262 bool comm_dma_setup_done = false;
2263 const unsigned int *data;
2264 unsigned int chip_addx;
2265 unsigned int words_to_write;
2266 unsigned int buffer_size_words;
2267 unsigned char *buffer_addx;
2268 unsigned short hda_format;
2269 unsigned int sample_rate_div;
2270 unsigned int sample_rate_mul;
2271 unsigned int num_chans;
2272 unsigned int hda_frame_size_words;
2273 unsigned int remainder_words;
2274 const u32 *data_remainder;
2275 u32 chip_addx_remainder;
2276 unsigned int run_size_words;
2277 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2278 unsigned long timeout;
2279 bool dma_active;
01ef7dbf
IM		 2280
2281 if (fls == NULL)
2282 return -EINVAL;
2283 if (is_hci_prog_list_seg(fls)) {
2284 hci_write = fls;
2285 fls = get_next_seg_ptr(fls);
2286 }
95c6e9cb 2287
01ef7dbf 2288 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2289 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2290 return dspxfr_hci_write(codec, hci_write);
2291 }
95c6e9cb 2292
01ef7dbf 2293 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2294 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2295 return -EINVAL;
95c6e9cb
IM		 2296 }
2297
01ef7dbf
IM		 2298 data = fls->data;
2299 chip_addx = fls->chip_addr,
2300 words_to_write = fls->count;
2301
2302 if (!words_to_write)
2303 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2304 if (reloc)
2305 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2306
2307 if (!UC_RANGE(chip_addx, words_to_write) &&
2308 !X_RANGE_ALL(chip_addx, words_to_write) &&
2309 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2310 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2311 return -EINVAL;
95c6e9cb
IM		 2312 }
2313
01ef7dbf
IM		 2314 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2315 sizeof(u32);
2316
2317 buffer_addx = dma_get_buffer_addr(dma_engine);
2318
2319 if (buffer_addx == NULL) {
4e76a883 2320 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2321 return -EINVAL;
2322 }
2323
2324 dma_get_converter_format(dma_engine, &hda_format);
2325 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2326 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2327 num_chans = get_hdafmt_chs(hda_format) + 1;
2328
2329 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2330 (num_chans * sample_rate_mul / sample_rate_div));
2331
3bc085a1 2332 if (hda_frame_size_words == 0) {
4e76a883 2333 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2334 return -EINVAL;
2335 }
2336
01ef7dbf
IM		 2337 buffer_size_words = min(buffer_size_words,
2338 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2339 65536 : 32768));
2340 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2341 codec_dbg(codec,
01ef7dbf
IM		 2342 "chpadr=0x%08x frmsz=%u nchan=%u "
2343 "rate_mul=%u div=%u bufsz=%u\n",
2344 chip_addx, hda_frame_size_words, num_chans,
2345 sample_rate_mul, sample_rate_div, buffer_size_words);
2346
3bc085a1 2347 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2348 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2349 return -EINVAL;
2350 }
2351
2352 remainder_words = words_to_write % hda_frame_size_words;
2353 data_remainder = data;
2354 chip_addx_remainder = chip_addx;
2355
2356 data += remainder_words;
2357 chip_addx += remainder_words*sizeof(u32);
2358 words_to_write -= remainder_words;
2359
2360 while (words_to_write != 0) {
2361 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2362 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2363 words_to_write, run_size_words, remainder_words);
2364 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2365 if (!comm_dma_setup_done) {
2366 status = dsp_dma_stop(codec, dma_chan, ovly);
2367 if (status < 0)
425a7880 2368 return status;
01ef7dbf
IM		 2369 status = dsp_dma_setup_common(codec, chip_addx,
2370 dma_chan, port_map_mask, ovly);
2371 if (status < 0)
2372 return status;
2373 comm_dma_setup_done = true;
2374 }
2375
2376 status = dsp_dma_setup(codec, chip_addx,
2377 run_size_words, dma_chan);
2378 if (status < 0)
2379 return status;
2380 status = dsp_dma_start(codec, dma_chan, ovly);
2381 if (status < 0)
2382 return status;
2383 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2384 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2385 return -EIO;
2386 }
2387 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2388 if (status < 0)
2389 return status;
2390 if (remainder_words != 0) {
2391 status = chipio_write_multiple(codec,
2392 chip_addx_remainder,
2393 data_remainder,
2394 remainder_words);
b3667bd7
TI		 2395 if (status < 0)
2396 return status;
01ef7dbf
IM		 2397 remainder_words = 0;
2398 }
2399 if (hci_write) {
2400 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2401 if (status < 0)
2402 return status;
01ef7dbf
IM		 2403 hci_write = NULL;
2404 }
6d67530e
IM		 2405
2406 timeout = jiffies + msecs_to_jiffies(2000);
2407 do {
2408 dma_active = dsp_is_dma_active(codec, dma_chan);
2409 if (!dma_active)
01ef7dbf 2410 break;
6d67530e
IM		 2411 msleep(20);
2412 } while (time_before(jiffies, timeout));
2413 if (dma_active)
2414 break;
2415
4e76a883 2416 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2417 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2418 status = dma_reset(dma_engine);
01ef7dbf
IM		 2419
2420 if (status < 0)
2421 return status;
2422
2423 data += run_size_words;
2424 chip_addx += run_size_words*sizeof(u32);
2425 words_to_write -= run_size_words;
2426 }
2427
2428 if (remainder_words != 0) {
2429 status = chipio_write_multiple(codec, chip_addx_remainder,
2430 data_remainder, remainder_words);
2431 }
2432
2433 return status;
95c6e9cb
IM		 2434}
2435
d5c21b88
IM		 2436/**
2437 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2438 *
2439 * @codec: the HDA codec
2440 * @fls_data: pointer to a fast load image
2441 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2442 * no relocation
e97249dd 2443 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2444 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2445 * @ovly: TRUE if overlay format is required
2446 *
2447 * Returns zero or a negative error code.
2448 */
01ef7dbf
IM		 2449static int dspxfr_image(struct hda_codec *codec,
2450 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2451 unsigned int reloc,
2452 unsigned int sample_rate,
2453 unsigned short channels,
01ef7dbf 2454 bool ovly)
95c6e9cb
IM		 2455{
2456 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2457 int status;
2458 unsigned short hda_format = 0;
2459 unsigned int response;
2460 unsigned char stream_id = 0;
2461 struct dma_engine *dma_engine;
2462 unsigned int dma_chan;
2463 unsigned int port_map_mask;
2464
2465 if (fls_data == NULL)
2466 return -EINVAL;
2467
2468 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2469 if (!dma_engine)
2470 return -ENOMEM;
95c6e9cb 2471
01ef7dbf
IM		 2472 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2473 if (!dma_engine->dmab) {
549e8292
TI		 2474 kfree(dma_engine);
2475 return -ENOMEM;
01ef7dbf 2476 }
95c6e9cb 2477
01ef7dbf 2478 dma_engine->codec = codec;
6194b99d 2479 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2480 dma_engine->m_converter_format = hda_format;
2481 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2482 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2483
8ae3124b 2484 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2485
2486 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2487 hda_format, &response);
2488
2489 if (status < 0) {
4e76a883 2490 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2491 goto exit;
2492 }
2493
2494 status = snd_hda_codec_load_dsp_prepare(codec,
2495 dma_engine->m_converter_format,
2496 dma_engine->buf_size,
2497 dma_engine->dmab);
2498 if (status < 0)
95c6e9cb 2499 goto exit;
01ef7dbf
IM		 2500 spec->dsp_stream_id = status;
2501
2502 if (ovly) {
2503 status = dspio_alloc_dma_chan(codec, &dma_chan);
2504 if (status < 0) {
4e76a883 2505 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2506 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2507 goto exit;
2508 }
2509 }
95c6e9cb 2510
01ef7dbf
IM		 2511 port_map_mask = 0;
2512 status = dsp_allocate_ports_format(codec, hda_format,
2513 &port_map_mask);
2514 if (status < 0) {
4e76a883 2515 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2516 goto exit;
2517 }
2518
2519 stream_id = dma_get_stream_id(dma_engine);
2520 status = codec_set_converter_stream_channel(codec,
2521 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2522 if (status < 0) {
4e76a883 2523 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2524 goto exit;
2525 }
2526
2527 while ((fls_data != NULL) && !is_last(fls_data)) {
2528 if (!is_valid(fls_data)) {
4e76a883 2529 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2530 status = -EINVAL;
2531 goto exit;
2532 }
2533 status = dspxfr_one_seg(codec, fls_data, reloc,
2534 dma_engine, dma_chan,
2535 port_map_mask, ovly);
2536 if (status < 0)
2537 break;
2538
2539 if (is_hci_prog_list_seg(fls_data))
2540 fls_data = get_next_seg_ptr(fls_data);
2541
2542 if ((fls_data != NULL) && !is_last(fls_data))
2543 fls_data = get_next_seg_ptr(fls_data);
2544 }
2545
2546 if (port_map_mask != 0)
2547 status = dsp_free_ports(codec);
2548
2549 if (status < 0)
95c6e9cb
IM		 2550 goto exit;
2551
01ef7dbf
IM		 2552 status = codec_set_converter_stream_channel(codec,
2553 WIDGET_CHIP_CTRL, 0, 0, &response);
2554
95c6e9cb 2555exit:
01ef7dbf
IM		 2556 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2557 dspio_free_dma_chan(codec, dma_chan);
2558
b3667bd7 2559 if (dma_engine->dmab->area)
01ef7dbf
IM		 2560 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2561 kfree(dma_engine->dmab);
2562 kfree(dma_engine);
2563
2564 return status;
95c6e9cb
IM		 2565}
2566
2567/*
01ef7dbf 2568 * CA0132 DSP download stuffs.
95c6e9cb 2569 */
01ef7dbf 2570static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2571{
4e76a883 2572 codec_dbg(codec, "---- dspload_post_setup ------\n");
95c6e9cb 2573
01ef7dbf
IM		 2574 /*set DSP speaker to 2.0 configuration*/
2575 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2576 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2577
01ef7dbf
IM		 2578 /*update write pointer*/
2579 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2580}
95c6e9cb 2581
d5c21b88 2582/**
e60b2c7f 2583 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2584 *
2585 * @codec: the HDA codec
2586 * @fls: pointer to a fast load image
2587 * @ovly: TRUE if overlay format is required
2588 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2589 * no relocation
2590 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2591 * @router_chans: number of audio router channels to be allocated (0 means use
2592 * internal defaults; max is 32)
2593 *
e60b2c7f
TI		 2594 * Download DSP from a DSP Image Fast Load structure. This structure is a
2595 * linear, non-constant sized element array of structures, each of which
2596 * contain the count of the data to be loaded, the data itself, and the
2597 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2598 * Returns zero or a negative error code.
2599 */
01ef7dbf
IM		 2600static int dspload_image(struct hda_codec *codec,
2601 const struct dsp_image_seg *fls,
2602 bool ovly,
2603 unsigned int reloc,
2604 bool autostart,
2605 int router_chans)
2606{
2607 int status = 0;
e97249dd
IM		 2608 unsigned int sample_rate;
2609 unsigned short channels;
01ef7dbf 2610
4e76a883 2611 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2612 if (router_chans == 0) {
2613 if (!ovly)
2614 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2615 else
2616 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2617 }
95c6e9cb 2618
e97249dd
IM		 2619 sample_rate = 48000;
2620 channels = (unsigned short)router_chans;
01ef7dbf 2621
e97249dd
IM		 2622 while (channels > 16) {
2623 sample_rate *= 2;
2624 channels /= 2;
01ef7dbf
IM		 2625 }
2626
01ef7dbf 2627 do {
4e76a883 2628 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 2629 if (!ovly)
2630 status = dsp_reset(codec);
2631
2632 if (status < 0)
2633 break;
2634
4e76a883 2635 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 2636 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2637 ovly);
01ef7dbf
IM		 2638
2639 if (status < 0)
2640 break;
2641
4e76a883 2642 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 2643 if (autostart && !ovly) {
2644 dspload_post_setup(codec);
2645 status = dsp_set_run_state(codec);
2646 }
2647
4e76a883 2648 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 2649 } while (0);
2650
2651 return status;
2652}
2653
f664417e 2654#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 2655static bool dspload_is_loaded(struct hda_codec *codec)
2656{
2657 unsigned int data = 0;
2658 int status = 0;
2659
2660 status = chipio_read(codec, 0x40004, &data);
2661 if ((status < 0) || (data != 1))
2662 return false;
2663
2664 return true;
2665}
f664417e
TI		 2666#else
2667#define dspload_is_loaded(codec) false
2668#endif
01ef7dbf
IM		 2669
2670static bool dspload_wait_loaded(struct hda_codec *codec)
2671{
6d67530e 2672 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 2673
2674 do {
01ef7dbf
IM		 2675 if (dspload_is_loaded(codec)) {
2676 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2677 return true;
2678 }
6d67530e
IM		 2679 msleep(20);
2680 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 2681
2682 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2683 return false;
95c6e9cb
IM		 2684}
2685
825315bc
IM		 2686/*
2687 * PCM callbacks
2688 */
95c6e9cb
IM		 2689static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2690 struct hda_codec *codec,
2691 unsigned int stream_tag,
2692 unsigned int format,
2693 struct snd_pcm_substream *substream)
2694{
2695 struct ca0132_spec *spec = codec->spec;
825315bc 2696
28fba950 2697 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 2698
2699 return 0;
95c6e9cb
IM		 2700}
2701
2702static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2703 struct hda_codec *codec,
2704 struct snd_pcm_substream *substream)
2705{
2706 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2707
2708 if (spec->dsp_state == DSP_DOWNLOADING)
2709 return 0;
2710
2711 /*If Playback effects are on, allow stream some time to flush
2712 *effects tail*/
2713 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2714 msleep(50);
2715
28fba950 2716 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 2717
2718 return 0;
95c6e9cb
IM		 2719}
2720
e8412ca4
DR		 2721static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2722 struct hda_codec *codec,
2723 struct snd_pcm_substream *substream)
2724{
2725 struct ca0132_spec *spec = codec->spec;
2726 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2727 struct snd_pcm_runtime *runtime = substream->runtime;
2728
2729 if (spec->dsp_state != DSP_DOWNLOADED)
2730 return 0;
2731
2732 /* Add latency if playback enhancement and either effect is enabled. */
2733 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2734 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2735 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2736 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2737 }
2738
2739 /* Applying Speaker EQ adds latency as well. */
2740 if (spec->cur_out_type == SPEAKER_OUT)
2741 latency += DSP_SPEAKER_OUT_LATENCY;
2742
2743 return (latency * runtime->rate) / 1000;
2744}
2745
95c6e9cb
IM		 2746/*
2747 * Digital out
2748 */
27ebeb0b
TI		 2749static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2750 struct hda_codec *codec,
2751 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2752{
2753 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2754 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2755}
2756
27ebeb0b 2757static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2758 struct hda_codec *codec,
2759 unsigned int stream_tag,
2760 unsigned int format,
2761 struct snd_pcm_substream *substream)
2762{
2763 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2764 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2765 stream_tag, format, substream);
95c6e9cb
IM		 2766}
2767
27ebeb0b 2768static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2769 struct hda_codec *codec,
95c6e9cb
IM		 2770 struct snd_pcm_substream *substream)
2771{
2772 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2773 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2774}
2775
27ebeb0b
TI		 2776static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2777 struct hda_codec *codec,
2778 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2779{
2780 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2781 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2782}
2783
825315bc
IM		 2784/*
2785 * Analog capture
2786 */
2787static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2788 struct hda_codec *codec,
2789 unsigned int stream_tag,
2790 unsigned int format,
2791 struct snd_pcm_substream *substream)
2792{
13c12dbe 2793 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 2794 stream_tag, 0, format);
825315bc
IM		 2795
2796 return 0;
2797}
2798
2799static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2800 struct hda_codec *codec,
2801 struct snd_pcm_substream *substream)
2802{
2803 struct ca0132_spec *spec = codec->spec;
2804
2805 if (spec->dsp_state == DSP_DOWNLOADING)
2806 return 0;
2807
28fba950 2808 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 2809 return 0;
2810}
2811
e8412ca4
DR		 2812static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2813 struct hda_codec *codec,
2814 struct snd_pcm_substream *substream)
2815{
2816 struct ca0132_spec *spec = codec->spec;
2817 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2818 struct snd_pcm_runtime *runtime = substream->runtime;
2819
2820 if (spec->dsp_state != DSP_DOWNLOADED)
2821 return 0;
2822
2823 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2824 latency += DSP_CRYSTAL_VOICE_LATENCY;
2825
2826 return (latency * runtime->rate) / 1000;
2827}
2828
e90f29e4
IM		 2829/*
2830 * Controls stuffs.
2831 */
2832
2833/*
2834 * Mixer controls helpers.
2835 */
2836#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2837 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2838 .name = xname, \
2839 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2840 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2841 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2842 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2843 .info = ca0132_volume_info, \
2844 .get = ca0132_volume_get, \
2845 .put = ca0132_volume_put, \
2846 .tlv = { .c = ca0132_volume_tlv }, \
2847 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2848
2849#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2850 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2851 .name = xname, \
2852 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2853 .info = snd_hda_mixer_amp_switch_info, \
2854 .get = ca0132_switch_get, \
2855 .put = ca0132_switch_put, \
2856 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2857
2858/* stereo */
2859#define CA0132_CODEC_VOL(xname, nid, dir) \
2860 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2861#define CA0132_CODEC_MUTE(xname, nid, dir) \
2862 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2863
44f0c978
IM		 2864/* The followings are for tuning of products */
2865#ifdef ENABLE_TUNING_CONTROLS
2866
2867static unsigned int voice_focus_vals_lookup[] = {
28680x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
28690x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
28700x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
28710x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
28720x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
28730x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
28740x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
28750x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
28760x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
28770x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
28780x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
28790x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
28800x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
28810x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
28820x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
28830x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
28840x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
28850x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
28860x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
28870x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
28880x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
28890x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
28900x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
28910x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
28920x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
28930x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
28940x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2895};
2896
2897static unsigned int mic_svm_vals_lookup[] = {
28980x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
28990x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
29000x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
29010x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
29020x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
29030x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
29040x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
29050x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
29060x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
29070x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
29080x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
29090x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
29100x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
29110x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
29120x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
29130x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
29140x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2915};
2916
2917static unsigned int equalizer_vals_lookup[] = {
29180xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
29190xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
29200xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
29210xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
29220x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
29230x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
29240x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
29250x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
29260x41C00000
2927};
2928
2929static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2930 unsigned int *lookup, int idx)
2931{
2932 int i = 0;
2933
2934 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2935 if (nid == ca0132_tuning_ctls[i].nid)
2936 break;
2937
2938 snd_hda_power_up(codec);
2939 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2940 ca0132_tuning_ctls[i].req,
2941 &(lookup[idx]), sizeof(unsigned int));
2942 snd_hda_power_down(codec);
2943
2944 return 1;
2945}
2946
2947static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2948 struct snd_ctl_elem_value *ucontrol)
2949{
2950 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2951 struct ca0132_spec *spec = codec->spec;
2952 hda_nid_t nid = get_amp_nid(kcontrol);
2953 long *valp = ucontrol->value.integer.value;
2954 int idx = nid - TUNING_CTL_START_NID;
2955
2956 *valp = spec->cur_ctl_vals[idx];
2957 return 0;
2958}
2959
2960static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2961 struct snd_ctl_elem_info *uinfo)
2962{
2963 int chs = get_amp_channels(kcontrol);
2964 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2965 uinfo->count = chs == 3 ? 2 : 1;
2966 uinfo->value.integer.min = 20;
2967 uinfo->value.integer.max = 180;
2968 uinfo->value.integer.step = 1;
2969
2970 return 0;
2971}
2972
2973static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2974 struct snd_ctl_elem_value *ucontrol)
2975{
2976 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2977 struct ca0132_spec *spec = codec->spec;
2978 hda_nid_t nid = get_amp_nid(kcontrol);
2979 long *valp = ucontrol->value.integer.value;
2980 int idx;
2981
2982 idx = nid - TUNING_CTL_START_NID;
2983 /* any change? */
2984 if (spec->cur_ctl_vals[idx] == *valp)
2985 return 0;
2986
2987 spec->cur_ctl_vals[idx] = *valp;
2988
2989 idx = *valp - 20;
2990 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2991
2992 return 1;
2993}
2994
2995static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2996 struct snd_ctl_elem_info *uinfo)
2997{
2998 int chs = get_amp_channels(kcontrol);
2999 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3000 uinfo->count = chs == 3 ? 2 : 1;
3001 uinfo->value.integer.min = 0;
3002 uinfo->value.integer.max = 100;
3003 uinfo->value.integer.step = 1;
3004
3005 return 0;
3006}
3007
3008static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3009 struct snd_ctl_elem_value *ucontrol)
3010{
3011 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3012 struct ca0132_spec *spec = codec->spec;
3013 hda_nid_t nid = get_amp_nid(kcontrol);
3014 long *valp = ucontrol->value.integer.value;
3015 int idx;
3016
3017 idx = nid - TUNING_CTL_START_NID;
3018 /* any change? */
3019 if (spec->cur_ctl_vals[idx] == *valp)
3020 return 0;
3021
3022 spec->cur_ctl_vals[idx] = *valp;
3023
3024 idx = *valp;
3025 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3026
3027 return 0;
3028}
3029
3030static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3031 struct snd_ctl_elem_info *uinfo)
3032{
3033 int chs = get_amp_channels(kcontrol);
3034 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3035 uinfo->count = chs == 3 ? 2 : 1;
3036 uinfo->value.integer.min = 0;
3037 uinfo->value.integer.max = 48;
3038 uinfo->value.integer.step = 1;
3039
3040 return 0;
3041}
3042
3043static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3044 struct snd_ctl_elem_value *ucontrol)
3045{
3046 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3047 struct ca0132_spec *spec = codec->spec;
3048 hda_nid_t nid = get_amp_nid(kcontrol);
3049 long *valp = ucontrol->value.integer.value;
3050 int idx;
3051
3052 idx = nid - TUNING_CTL_START_NID;
3053 /* any change? */
3054 if (spec->cur_ctl_vals[idx] == *valp)
3055 return 0;
3056
3057 spec->cur_ctl_vals[idx] = *valp;
3058
3059 idx = *valp;
3060 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3061
3062 return 1;
3063}
3064
3065static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3066static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3067
3068static int add_tuning_control(struct hda_codec *codec,
3069 hda_nid_t pnid, hda_nid_t nid,
3070 const char *name, int dir)
3071{
975cc02a 3072 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3073 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3074 struct snd_kcontrol_new knew =
3075 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3076
3077 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3078 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3079 knew.tlv.c = 0;
3080 knew.tlv.p = 0;
3081 switch (pnid) {
3082 case VOICE_FOCUS:
3083 knew.info = voice_focus_ctl_info;
3084 knew.get = tuning_ctl_get;
3085 knew.put = voice_focus_ctl_put;
3086 knew.tlv.p = voice_focus_db_scale;
3087 break;
3088 case MIC_SVM:
3089 knew.info = mic_svm_ctl_info;
3090 knew.get = tuning_ctl_get;
3091 knew.put = mic_svm_ctl_put;
3092 break;
3093 case EQUALIZER:
3094 knew.info = equalizer_ctl_info;
3095 knew.get = tuning_ctl_get;
3096 knew.put = equalizer_ctl_put;
3097 knew.tlv.p = eq_db_scale;
3098 break;
3099 default:
3100 return 0;
3101 }
3102 knew.private_value =
3103 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3104 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3105 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3106}
3107
3108static int add_tuning_ctls(struct hda_codec *codec)
3109{
3110 int i;
3111 int err;
3112
3113 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3114 err = add_tuning_control(codec,
3115 ca0132_tuning_ctls[i].parent_nid,
3116 ca0132_tuning_ctls[i].nid,
3117 ca0132_tuning_ctls[i].name,
3118 ca0132_tuning_ctls[i].direct);
3119 if (err < 0)
3120 return err;
3121 }
3122
3123 return 0;
3124}
3125
3126static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3127{
3128 struct ca0132_spec *spec = codec->spec;
3129 int i;
3130
3131 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3132 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3133 /* SVM level defaults to 0.74. */
3134 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3135
3136 /* EQ defaults to 0dB. */
3137 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3138 spec->cur_ctl_vals[i] = 24;
3139}
3140#endif /*ENABLE_TUNING_CONTROLS*/
3141
5aaca44d
IM		 3142/*
3143 * Select the active output.
3144 * If autodetect is enabled, output will be selected based on jack detection.
3145 * If jack inserted, headphone will be selected, else built-in speakers
3146 * If autodetect is disabled, output will be selected based on selection.
3147 */
3148static int ca0132_select_out(struct hda_codec *codec)
3149{
3150 struct ca0132_spec *spec = codec->spec;
3151 unsigned int pin_ctl;
3152 int jack_present;
3153 int auto_jack;
3154 unsigned int tmp;
3155 int err;
3156
4e76a883 3157 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3158
664c7155 3159 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3160
3161 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3162
3163 if (auto_jack)
fe14f39e 3164 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3165 else
3166 jack_present =
3167 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3168
3169 if (jack_present)
3170 spec->cur_out_type = HEADPHONE_OUT;
3171 else
3172 spec->cur_out_type = SPEAKER_OUT;
3173
3174 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3175 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3176 /*speaker out config*/
3177 tmp = FLOAT_ONE;
3178 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3179 if (err < 0)
3180 goto exit;
3181 /*enable speaker EQ*/
3182 tmp = FLOAT_ONE;
3183 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3184 if (err < 0)
3185 goto exit;
3186
3187 /* Setup EAPD */
3188 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3189 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3190 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3191 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3192 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3193 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3194 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3195 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3196
3197 /* disable headphone node */
3198 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3199 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3200 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3201 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3202 /* enable speaker node */
3203 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3204 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3205 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3206 pin_ctl | PIN_OUT);
5aaca44d 3207 } else {
4e76a883 3208 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3209 /*headphone out config*/
3210 tmp = FLOAT_ZERO;
3211 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3212 if (err < 0)
3213 goto exit;
3214 /*disable speaker EQ*/
3215 tmp = FLOAT_ZERO;
3216 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3217 if (err < 0)
3218 goto exit;
3219
3220 /* Setup EAPD */
3221 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3222 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3223 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3224 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3225 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3226 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3227 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3228 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3229
3230 /* disable speaker*/
3231 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3232 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3233 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3234 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3235 /* enable headphone*/
3236 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3237 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3238 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3239 pin_ctl | PIN_HP);
5aaca44d
IM		 3240 }
3241
3242exit:
664c7155 3243 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3244
3245 return err < 0 ? err : 0;
3246}
3247
993884f6
CCC		 3248static void ca0132_unsol_hp_delayed(struct work_struct *work)
3249{
3250 struct ca0132_spec *spec = container_of(
3251 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 3252 struct hda_jack_tbl *jack;
3253
993884f6 3254 ca0132_select_out(spec->codec);
d5c016b5 3255 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 3256 if (jack) {
3257 jack->block_report = 0;
3258 snd_hda_jack_report_sync(spec->codec);
3259 }
993884f6
CCC		 3260}
3261
5aaca44d
IM		 3262static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3263static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3264static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3265
3266/*
3267 * Select the active VIP source
3268 */
3269static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3270{
3271 struct ca0132_spec *spec = codec->spec;
3272 unsigned int tmp;
3273
e8f1bd5d 3274 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 3275 return 0;
3276
3277 /* if CrystalVoice if off, vipsource should be 0 */
3278 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3279 (val == 0)) {
3280 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3281 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3282 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3283 if (spec->cur_mic_type == DIGITAL_MIC)
3284 tmp = FLOAT_TWO;
3285 else
3286 tmp = FLOAT_ONE;
3287 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3288 tmp = FLOAT_ZERO;
3289 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3290 } else {
3291 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3292 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3293 if (spec->cur_mic_type == DIGITAL_MIC)
3294 tmp = FLOAT_TWO;
3295 else
3296 tmp = FLOAT_ONE;
3297 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3298 tmp = FLOAT_ONE;
3299 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3300 msleep(20);
3301 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3302 }
3303
3304 return 1;
3305}
3306
3307/*
3308 * Select the active microphone.
3309 * If autodetect is enabled, mic will be selected based on jack detection.
3310 * If jack inserted, ext.mic will be selected, else built-in mic
3311 * If autodetect is disabled, mic will be selected based on selection.
3312 */
3313static int ca0132_select_mic(struct hda_codec *codec)
3314{
3315 struct ca0132_spec *spec = codec->spec;
3316 int jack_present;
3317 int auto_jack;
3318
4e76a883 3319 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 3320
664c7155 3321 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3322
3323 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3324
3325 if (auto_jack)
fe14f39e 3326 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 3327 else
3328 jack_present =
3329 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3330
3331 if (jack_present)
3332 spec->cur_mic_type = LINE_MIC_IN;
3333 else
3334 spec->cur_mic_type = DIGITAL_MIC;
3335
3336 if (spec->cur_mic_type == DIGITAL_MIC) {
3337 /* enable digital Mic */
3338 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3339 ca0132_set_dmic(codec, 1);
3340 ca0132_mic_boost_set(codec, 0);
3341 /* set voice focus */
3342 ca0132_effects_set(codec, VOICE_FOCUS,
3343 spec->effects_switch
3344 [VOICE_FOCUS - EFFECT_START_NID]);
3345 } else {
3346 /* disable digital Mic */
3347 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3348 ca0132_set_dmic(codec, 0);
3349 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3350 /* disable voice focus */
3351 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3352 }
3353
664c7155 3354 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3355
3356 return 0;
3357}
3358
a7e76271
IM		 3359/*
3360 * Check if VNODE settings take effect immediately.
3361 */
3362static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3363 hda_nid_t vnid,
3364 hda_nid_t *shared_nid)
3365{
3366 struct ca0132_spec *spec = codec->spec;
3367 hda_nid_t nid;
a7e76271
IM		 3368
3369 switch (vnid) {
3370 case VNID_SPK:
3371 nid = spec->shared_out_nid;
a7e76271
IM		 3372 break;
3373 case VNID_MIC:
3374 nid = spec->shared_mic_nid;
a7e76271
IM		 3375 break;
3376 default:
9a0869f4 3377 return false;
a7e76271
IM		 3378 }
3379
9a0869f4 3380 if (shared_nid)
a7e76271
IM		 3381 *shared_nid = nid;
3382
9a0869f4 3383 return true;
a7e76271
IM		 3384}
3385
3386/*
3387* The following functions are control change helpers.
3388* They return 0 if no changed. Return 1 if changed.
3389*/
3390static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3391{
3392 struct ca0132_spec *spec = codec->spec;
3393 unsigned int tmp;
3394
3395 /* based on CrystalVoice state to enable VoiceFX. */
3396 if (enable) {
3397 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3398 FLOAT_ONE : FLOAT_ZERO;
3399 } else {
3400 tmp = FLOAT_ZERO;
3401 }
3402
3403 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3404 ca0132_voicefx.reqs[0], tmp);
3405
3406 return 1;
3407}
3408
5aaca44d
IM		 3409/*
3410 * Set the effects parameters
3411 */
3412static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3413{
3414 struct ca0132_spec *spec = codec->spec;
3415 unsigned int on;
3416 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3417 int err = 0;
3418 int idx = nid - EFFECT_START_NID;
3419
3420 if ((idx < 0) || (idx >= num_fx))
3421 return 0; /* no changed */
3422
3423 /* for out effect, qualify with PE */
3424 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3425 /* if PE if off, turn off out effects. */
3426 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3427 val = 0;
3428 }
3429
3430 /* for in effect, qualify with CrystalVoice */
3431 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3432 /* if CrystalVoice if off, turn off in effects. */
3433 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3434 val = 0;
3435
3436 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3437 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3438 val = 0;
3439 }
3440
4e76a883 3441 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 3442 nid, val);
3443
3444 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3445 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3446 ca0132_effects[idx].reqs[0], on);
3447
3448 if (err < 0)
3449 return 0; /* no changed */
3450
3451 return 1;
3452}
3453
a7e76271
IM		 3454/*
3455 * Turn on/off Playback Enhancements
3456 */
3457static int ca0132_pe_switch_set(struct hda_codec *codec)
3458{
3459 struct ca0132_spec *spec = codec->spec;
3460 hda_nid_t nid;
3461 int i, ret = 0;
3462
4e76a883 3463 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 3464 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3465
3466 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3467 nid = OUT_EFFECT_START_NID;
3468 /* PE affects all out effects */
3469 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3470 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3471
3472 return ret;
3473}
3474
5aaca44d
IM		 3475/* Check if Mic1 is streaming, if so, stop streaming */
3476static int stop_mic1(struct hda_codec *codec)
3477{
3478 struct ca0132_spec *spec = codec->spec;
3479 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3480 AC_VERB_GET_CONV, 0);
3481 if (oldval != 0)
3482 snd_hda_codec_write(codec, spec->adcs[0], 0,
3483 AC_VERB_SET_CHANNEL_STREAMID,
3484 0);
3485 return oldval;
3486}
3487
3488/* Resume Mic1 streaming if it was stopped. */
3489static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3490{
3491 struct ca0132_spec *spec = codec->spec;
3492 /* Restore the previous stream and channel */
3493 if (oldval != 0)
3494 snd_hda_codec_write(codec, spec->adcs[0], 0,
3495 AC_VERB_SET_CHANNEL_STREAMID,
3496 oldval);
3497}
3498
3499/*
a7e76271 3500 * Turn on/off CrystalVoice
5aaca44d 3501 */
a7e76271
IM		 3502static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3503{
3504 struct ca0132_spec *spec = codec->spec;
3505 hda_nid_t nid;
3506 int i, ret = 0;
3507 unsigned int oldval;
3508
4e76a883 3509 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 3510 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3511
3512 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3513 nid = IN_EFFECT_START_NID;
3514 /* CrystalVoice affects all in effects */
3515 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3516 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3517
3518 /* including VoiceFX */
3519 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3520
3521 /* set correct vipsource */
3522 oldval = stop_mic1(codec);
3523 ret |= ca0132_set_vipsource(codec, 1);
3524 resume_mic1(codec, oldval);
3525 return ret;
3526}
3527
5aaca44d
IM		 3528static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3529{
3530 struct ca0132_spec *spec = codec->spec;
3531 int ret = 0;
3532
3533 if (val) /* on */
3534 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3535 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3536 else /* off */
3537 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3538 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3539
3540 return ret;
3541}
3542
a7e76271
IM		 3543static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3544 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3545{
a7e76271
IM		 3546 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3547 hda_nid_t nid = get_amp_nid(kcontrol);
3548 hda_nid_t shared_nid = 0;
3549 bool effective;
3550 int ret = 0;
95c6e9cb 3551 struct ca0132_spec *spec = codec->spec;
a7e76271 3552 int auto_jack;
95c6e9cb 3553
a7e76271
IM		 3554 if (nid == VNID_HP_SEL) {
3555 auto_jack =
3556 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3557 if (!auto_jack)
3558 ca0132_select_out(codec);
3559 return 1;
3560 }
95c6e9cb 3561
a7e76271
IM		 3562 if (nid == VNID_AMIC1_SEL) {
3563 auto_jack =
3564 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3565 if (!auto_jack)
3566 ca0132_select_mic(codec);
3567 return 1;
3568 }
95c6e9cb 3569
a7e76271
IM		 3570 if (nid == VNID_HP_ASEL) {
3571 ca0132_select_out(codec);
3572 return 1;
3573 }
95c6e9cb 3574
a7e76271
IM		 3575 if (nid == VNID_AMIC1_ASEL) {
3576 ca0132_select_mic(codec);
3577 return 1;
95c6e9cb 3578 }
a7e76271
IM		 3579
3580 /* if effective conditions, then update hw immediately. */
3581 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3582 if (effective) {
3583 int dir = get_amp_direction(kcontrol);
3584 int ch = get_amp_channels(kcontrol);
3585 unsigned long pval;
3586
3587 mutex_lock(&codec->control_mutex);
3588 pval = kcontrol->private_value;
3589 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3590 0, dir);
3591 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3592 kcontrol->private_value = pval;
3593 mutex_unlock(&codec->control_mutex);
95c6e9cb 3594 }
95c6e9cb 3595
a7e76271 3596 return ret;
95c6e9cb 3597}
a7e76271 3598/* End of control change helpers. */
95c6e9cb 3599
a7e76271
IM		 3600static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3601 struct snd_ctl_elem_info *uinfo)
3602{
3603 unsigned int items = sizeof(ca0132_voicefx_presets)
3604 / sizeof(struct ct_voicefx_preset);
3605
3606 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3607 uinfo->count = 1;
3608 uinfo->value.enumerated.items = items;
3609 if (uinfo->value.enumerated.item >= items)
3610 uinfo->value.enumerated.item = items - 1;
3611 strcpy(uinfo->value.enumerated.name,
3612 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3613 return 0;
3614}
95c6e9cb 3615
a7e76271 3616static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3617 struct snd_ctl_elem_value *ucontrol)
3618{
3619 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3620 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3621
a7e76271 3622 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3623 return 0;
3624}
3625
a7e76271 3626static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3627 struct snd_ctl_elem_value *ucontrol)
3628{
3629 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3630 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3631 int i, err = 0;
3632 int sel = ucontrol->value.enumerated.item[0];
3633 unsigned int items = sizeof(ca0132_voicefx_presets)
3634 / sizeof(struct ct_voicefx_preset);
95c6e9cb 3635
a7e76271 3636 if (sel >= items)
95c6e9cb
IM		 3637 return 0;
3638
4e76a883 3639 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 3640 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3641
a7e76271
IM		 3642 /*
3643 * Idx 0 is default.
3644 * Default needs to qualify with CrystalVoice state.
3645 */
3646 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3647 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3648 ca0132_voicefx.reqs[i],
3649 ca0132_voicefx_presets[sel].vals[i]);
3650 if (err < 0)
3651 break;
3652 }
95c6e9cb 3653
a7e76271
IM		 3654 if (err >= 0) {
3655 spec->voicefx_val = sel;
3656 /* enable voice fx */
3657 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3658 }
95c6e9cb 3659
a7e76271 3660 return 1;
95c6e9cb
IM		 3661}
3662
a7e76271
IM		 3663static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3664 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3665{
3666 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3667 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3668 hda_nid_t nid = get_amp_nid(kcontrol);
3669 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3670 long *valp = ucontrol->value.integer.value;
3671
a7e76271
IM		 3672 /* vnode */
3673 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3674 if (ch & 1) {
3675 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3676 valp++;
3677 }
3678 if (ch & 2) {
3679 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3680 valp++;
3681 }
3682 return 0;
3683 }
3684
3685 /* effects, include PE and CrystalVoice */
3686 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3687 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3688 return 0;
3689 }
3690
3691 /* mic boost */
3692 if (nid == spec->input_pins[0]) {
3693 *valp = spec->cur_mic_boost;
3694 return 0;
3695 }
3696
95c6e9cb
IM		 3697 return 0;
3698}
3699
a7e76271
IM		 3700static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3701 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3702{
3703 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3704 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3705 hda_nid_t nid = get_amp_nid(kcontrol);
3706 int ch = get_amp_channels(kcontrol);
95c6e9cb 3707 long *valp = ucontrol->value.integer.value;
a7e76271 3708 int changed = 1;
95c6e9cb 3709
4e76a883 3710 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 3711 nid, *valp);
95c6e9cb
IM		 3712
3713 snd_hda_power_up(codec);
a7e76271
IM		 3714 /* vnode */
3715 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3716 if (ch & 1) {
3717 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3718 valp++;
3719 }
3720 if (ch & 2) {
3721 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3722 valp++;
3723 }
3724 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3725 goto exit;
3726 }
95c6e9cb 3727
a7e76271
IM		 3728 /* PE */
3729 if (nid == PLAY_ENHANCEMENT) {
3730 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3731 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3732 goto exit;
a7e76271 3733 }
95c6e9cb 3734
a7e76271
IM		 3735 /* CrystalVoice */
3736 if (nid == CRYSTAL_VOICE) {
3737 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3738 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3739 goto exit;
a7e76271 3740 }
95c6e9cb 3741
a7e76271
IM		 3742 /* out and in effects */
3743 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3744 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3745 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3746 changed = ca0132_effects_set(codec, nid, *valp);
3747 goto exit;
3748 }
3749
3750 /* mic boost */
3751 if (nid == spec->input_pins[0]) {
3752 spec->cur_mic_boost = *valp;
3753
3754 /* Mic boost does not apply to Digital Mic */
3755 if (spec->cur_mic_type != DIGITAL_MIC)
3756 changed = ca0132_mic_boost_set(codec, *valp);
3757 goto exit;
3758 }
95c6e9cb 3759
a7e76271 3760exit:
95c6e9cb 3761 snd_hda_power_down(codec);
a7e76271 3762 return changed;
95c6e9cb
IM		 3763}
3764
a7e76271
IM		 3765/*
3766 * Volume related
3767 */
3768static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3769 struct snd_ctl_elem_info *uinfo)
3770{
3771 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3772 struct ca0132_spec *spec = codec->spec;
3773 hda_nid_t nid = get_amp_nid(kcontrol);
3774 int ch = get_amp_channels(kcontrol);
3775 int dir = get_amp_direction(kcontrol);
3776 unsigned long pval;
3777 int err;
3778
3779 switch (nid) {
3780 case VNID_SPK:
3781 /* follow shared_out info */
3782 nid = spec->shared_out_nid;
3783 mutex_lock(&codec->control_mutex);
3784 pval = kcontrol->private_value;
3785 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3786 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3787 kcontrol->private_value = pval;
3788 mutex_unlock(&codec->control_mutex);
3789 break;
3790 case VNID_MIC:
3791 /* follow shared_mic info */
3792 nid = spec->shared_mic_nid;
3793 mutex_lock(&codec->control_mutex);
3794 pval = kcontrol->private_value;
3795 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3796 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3797 kcontrol->private_value = pval;
3798 mutex_unlock(&codec->control_mutex);
3799 break;
3800 default:
3801 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3802 }
3803 return err;
3804}
3805
3806static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3807 struct snd_ctl_elem_value *ucontrol)
3808{
3809 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3810 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3811 hda_nid_t nid = get_amp_nid(kcontrol);
3812 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3813 long *valp = ucontrol->value.integer.value;
3814
a7e76271
IM		 3815 /* store the left and right volume */
3816 if (ch & 1) {
3817 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3818 valp++;
3819 }
3820 if (ch & 2) {
3821 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3822 valp++;
3823 }
95c6e9cb
IM		 3824 return 0;
3825}
3826
a7e76271 3827static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3828 struct snd_ctl_elem_value *ucontrol)
3829{
3830 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3831 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3832 hda_nid_t nid = get_amp_nid(kcontrol);
3833 int ch = get_amp_channels(kcontrol);
95c6e9cb 3834 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3835 hda_nid_t shared_nid = 0;
3836 bool effective;
3837 int changed = 1;
3838
3839 /* store the left and right volume */
3840 if (ch & 1) {
3841 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3842 valp++;
3843 }
3844 if (ch & 2) {
3845 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3846 valp++;
3847 }
95c6e9cb 3848
a7e76271
IM		 3849 /* if effective conditions, then update hw immediately. */
3850 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3851 if (effective) {
3852 int dir = get_amp_direction(kcontrol);
3853 unsigned long pval;
3854
3855 snd_hda_power_up(codec);
3856 mutex_lock(&codec->control_mutex);
3857 pval = kcontrol->private_value;
3858 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3859 0, dir);
3860 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3861 kcontrol->private_value = pval;
3862 mutex_unlock(&codec->control_mutex);
3863 snd_hda_power_down(codec);
3864 }
95c6e9cb 3865
a7e76271 3866 return changed;
95c6e9cb
IM		 3867}
3868
a7e76271
IM		 3869static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3870 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3871{
a7e76271
IM		 3872 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3873 struct ca0132_spec *spec = codec->spec;
3874 hda_nid_t nid = get_amp_nid(kcontrol);
3875 int ch = get_amp_channels(kcontrol);
3876 int dir = get_amp_direction(kcontrol);
3877 unsigned long pval;
3878 int err;
3879
3880 switch (nid) {
3881 case VNID_SPK:
3882 /* follow shared_out tlv */
3883 nid = spec->shared_out_nid;
3884 mutex_lock(&codec->control_mutex);
3885 pval = kcontrol->private_value;
3886 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3887 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3888 kcontrol->private_value = pval;
3889 mutex_unlock(&codec->control_mutex);
3890 break;
3891 case VNID_MIC:
3892 /* follow shared_mic tlv */
3893 nid = spec->shared_mic_nid;
3894 mutex_lock(&codec->control_mutex);
3895 pval = kcontrol->private_value;
3896 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3897 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3898 kcontrol->private_value = pval;
3899 mutex_unlock(&codec->control_mutex);
3900 break;
3901 default:
3902 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3903 }
3904 return err;
95c6e9cb
IM		 3905}
3906
a7e76271
IM		 3907static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3908 const char *pfx, int dir)
95c6e9cb 3909{
975cc02a 3910 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 3911 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3912 struct snd_kcontrol_new knew =
a7e76271
IM		 3913 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3914 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3915 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3916}
3917
a7e76271 3918static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3919{
3920 struct snd_kcontrol_new knew =
a7e76271
IM		 3921 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3922 VOICEFX, 1, 0, HDA_INPUT);
3923 knew.info = ca0132_voicefx_info;
3924 knew.get = ca0132_voicefx_get;
3925 knew.put = ca0132_voicefx_put;
3926 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3927}
3928
a7e76271
IM		 3929/*
3930 * When changing Node IDs for Mixer Controls below, make sure to update
3931 * Node IDs in ca0132_config() as well.
3932 */
3933static struct snd_kcontrol_new ca0132_mixer[] = {
3934 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3935 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3936 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3937 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3938 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3939 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3940 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3941 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3942 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3943 0x12, 1, HDA_INPUT),
3944 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3945 VNID_HP_SEL, 1, HDA_OUTPUT),
3946 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3947 VNID_AMIC1_SEL, 1, HDA_INPUT),
3948 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3949 VNID_HP_ASEL, 1, HDA_OUTPUT),
3950 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3951 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3952 { } /* end */
3953};
3954
e90f29e4
IM		 3955static int ca0132_build_controls(struct hda_codec *codec)
3956{
3957 struct ca0132_spec *spec = codec->spec;
3958 int i, num_fx;
3959 int err = 0;
3960
3961 /* Add Mixer controls */
3962 for (i = 0; i < spec->num_mixers; i++) {
3963 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3964 if (err < 0)
3965 return err;
3966 }
3967
3968 /* Add in and out effects controls.
3969 * VoiceFX, PE and CrystalVoice are added separately.
3970 */
3971 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3972 for (i = 0; i < num_fx; i++) {
3973 err = add_fx_switch(codec, ca0132_effects[i].nid,
3974 ca0132_effects[i].name,
3975 ca0132_effects[i].direct);
3976 if (err < 0)
3977 return err;
3978 }
3979
3980 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3981 if (err < 0)
3982 return err;
3983
3984 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3985 if (err < 0)
3986 return err;
3987
3988 add_voicefx(codec);
3989
3990#ifdef ENABLE_TUNING_CONTROLS
3991 add_tuning_ctls(codec);
3992#endif
3993
3994 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3995 if (err < 0)
3996 return err;
3997
3998 if (spec->dig_out) {
3999 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4000 spec->dig_out);
4001 if (err < 0)
4002 return err;
4003 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4004 if (err < 0)
4005 return err;
4006 /* spec->multiout.share_spdif = 1; */
4007 }
4008
4009 if (spec->dig_in) {
4010 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4011 if (err < 0)
4012 return err;
4013 }
4014 return 0;
4015}
4016
a7e76271 4017/*
e90f29e4 4018 * PCM
a7e76271
IM		 4019 */
4020static struct hda_pcm_stream ca0132_pcm_analog_playback = {
4021 .substreams = 1,
4022 .channels_min = 2,
825315bc 4023 .channels_max = 6,
a7e76271 4024 .ops = {
a7e76271 4025 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 4026 .cleanup = ca0132_playback_pcm_cleanup,
4027 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 4028 },
4029};
4030
4031static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4032 .substreams = 1,
4033 .channels_min = 2,
4034 .channels_max = 2,
825315bc
IM		 4035 .ops = {
4036 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 4037 .cleanup = ca0132_capture_pcm_cleanup,
4038 .get_delay = ca0132_capture_pcm_delay,
825315bc 4039 },
a7e76271
IM		 4040};
4041
4042static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4043 .substreams = 1,
4044 .channels_min = 2,
4045 .channels_max = 2,
4046 .ops = {
4047 .open = ca0132_dig_playback_pcm_open,
4048 .close = ca0132_dig_playback_pcm_close,
4049 .prepare = ca0132_dig_playback_pcm_prepare,
4050 .cleanup = ca0132_dig_playback_pcm_cleanup
4051 },
4052};
4053
4054static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4055 .substreams = 1,
4056 .channels_min = 2,
4057 .channels_max = 2,
4058};
4059
4060static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4061{
4062 struct ca0132_spec *spec = codec->spec;
bbbc7e85 4063 struct hda_pcm *info;
a7e76271 4064
bbbc7e85
TI		 4065 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4066 if (!info)
4067 return -ENOMEM;
a7e76271
IM		 4068 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4069 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4070 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4071 spec->multiout.max_channels;
4072 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4073 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 4074 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 4075
bbbc7e85
TI		 4076 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4077 if (!info)
4078 return -ENOMEM;
825315bc
IM		 4079 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4080 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4081 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
825315bc 4082
bbbc7e85
TI		 4083 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4084 if (!info)
4085 return -ENOMEM;
825315bc
IM		 4086 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4087 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4088 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 4089
a7e76271
IM		 4090 if (!spec->dig_out && !spec->dig_in)
4091 return 0;
4092
bbbc7e85
TI		 4093 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4094 if (!info)
4095 return -ENOMEM;
a7e76271
IM		 4096 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4097 if (spec->dig_out) {
4098 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4099 ca0132_pcm_digital_playback;
4100 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4101 }
4102 if (spec->dig_in) {
4103 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4104 ca0132_pcm_digital_capture;
4105 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4106 }
95c6e9cb 4107
a7e76271 4108 return 0;
95c6e9cb
IM		 4109}
4110
441aa6a0
IM		 4111static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4112{
4113 if (pin) {
a0c041cb 4114 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 4115 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4116 snd_hda_codec_write(codec, pin, 0,
4117 AC_VERB_SET_AMP_GAIN_MUTE,
4118 AMP_OUT_UNMUTE);
4119 }
4120 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4121 snd_hda_codec_write(codec, dac, 0,
4122 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4123}
4124
4125static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4126{
4127 if (pin) {
a0c041cb 4128 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 4129 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4130 snd_hda_codec_write(codec, pin, 0,
4131 AC_VERB_SET_AMP_GAIN_MUTE,
4132 AMP_IN_UNMUTE(0));
4133 }
4134 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4135 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4136 AMP_IN_UNMUTE(0));
4137
4138 /* init to 0 dB and unmute. */
4139 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4140 HDA_AMP_VOLMASK, 0x5a);
4141 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4142 HDA_AMP_MUTE, 0);
4143 }
4144}
4145
5aaca44d
IM		 4146static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4147{
4148 unsigned int caps;
4149
4150 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4151 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4152 snd_hda_override_amp_caps(codec, nid, dir, caps);
4153}
4154
4155/*
4156 * Switch between Digital built-in mic and analog mic.
4157 */
4158static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4159{
4160 struct ca0132_spec *spec = codec->spec;
4161 unsigned int tmp;
4162 u8 val;
4163 unsigned int oldval;
4164
4e76a883 4165 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 4166
4167 oldval = stop_mic1(codec);
4168 ca0132_set_vipsource(codec, 0);
4169 if (enable) {
4170 /* set DMic input as 2-ch */
4171 tmp = FLOAT_TWO;
4172 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4173
4174 val = spec->dmic_ctl;
4175 val |= 0x80;
4176 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4177 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4178
4179 if (!(spec->dmic_ctl & 0x20))
4180 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4181 } else {
4182 /* set AMic input as mono */
4183 tmp = FLOAT_ONE;
4184 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4185
4186 val = spec->dmic_ctl;
4187 /* clear bit7 and bit5 to disable dmic */
4188 val &= 0x5f;
4189 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4190 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4191
4192 if (!(spec->dmic_ctl & 0x20))
4193 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4194 }
4195 ca0132_set_vipsource(codec, 1);
4196 resume_mic1(codec, oldval);
4197}
4198
4199/*
4200 * Initialization for Digital Mic.
4201 */
4202static void ca0132_init_dmic(struct hda_codec *codec)
4203{
4204 struct ca0132_spec *spec = codec->spec;
4205 u8 val;
4206
4207 /* Setup Digital Mic here, but don't enable.
4208 * Enable based on jack detect.
4209 */
4210
4211 /* MCLK uses MPIO1, set to enable.
4212 * Bit 2-0: MPIO select
4213 * Bit 3: set to disable
4214 * Bit 7-4: reserved
4215 */
4216 val = 0x01;
4217 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4218 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4219
4220 /* Data1 uses MPIO3. Data2 not use
4221 * Bit 2-0: Data1 MPIO select
4222 * Bit 3: set disable Data1
4223 * Bit 6-4: Data2 MPIO select
4224 * Bit 7: set disable Data2
4225 */
4226 val = 0x83;
4227 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4228 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4229
4230 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4231 * Bit 3-0: Channel mask
4232 * Bit 4: set for 48KHz, clear for 32KHz
4233 * Bit 5: mode
4234 * Bit 6: set to select Data2, clear for Data1
4235 * Bit 7: set to enable DMic, clear for AMic
4236 */
4237 val = 0x23;
4238 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4239 spec->dmic_ctl = val;
4240 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4241 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4242}
4243
4244/*
4245 * Initialization for Analog Mic 2
4246 */
4247static void ca0132_init_analog_mic2(struct hda_codec *codec)
4248{
4249 struct ca0132_spec *spec = codec->spec;
4250
4251 mutex_lock(&spec->chipio_mutex);
4252 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4253 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4254 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4255 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4256 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4257 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4258 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4259 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4260 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4261 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4262 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4263 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4264 mutex_unlock(&spec->chipio_mutex);
4265}
4266
4267static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4268{
4269 struct ca0132_spec *spec = codec->spec;
4270 int i;
5aaca44d 4271
4e76a883 4272 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 4273 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 4274
4275 for (i = 0; i < spec->multiout.num_dacs; i++)
4276 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4277
4278 for (i = 0; i < spec->num_outputs; i++)
4279 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4280
4281 for (i = 0; i < spec->num_inputs; i++) {
4282 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4283 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4284 }
4285}
4286
4287/*
4288 * Setup default parameters for DSP
4289 */
4290static void ca0132_setup_defaults(struct hda_codec *codec)
4291{
e8f1bd5d 4292 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4293 unsigned int tmp;
4294 int num_fx;
4295 int idx, i;
4296
e8f1bd5d 4297 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4298 return;
4299
4300 /* out, in effects + voicefx */
4301 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4302 for (idx = 0; idx < num_fx; idx++) {
4303 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4304 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4305 ca0132_effects[idx].reqs[i],
4306 ca0132_effects[idx].def_vals[i]);
4307 }
4308 }
4309
4310 /*remove DSP headroom*/
4311 tmp = FLOAT_ZERO;
4312 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4313
4314 /*set speaker EQ bypass attenuation*/
4315 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4316
4317 /* set AMic1 and AMic2 as mono mic */
4318 tmp = FLOAT_ONE;
4319 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4320 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4321
4322 /* set AMic1 as CrystalVoice input */
4323 tmp = FLOAT_ONE;
4324 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4325
4326 /* set WUH source */
4327 tmp = FLOAT_TWO;
4328 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4329}
4330
4331/*
4332 * Initialization of flags in chip
4333 */
4334static void ca0132_init_flags(struct hda_codec *codec)
4335{
4336 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4337 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4338 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4339 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4340 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4341 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4342}
4343
4344/*
4345 * Initialization of parameters in chip
4346 */
4347static void ca0132_init_params(struct hda_codec *codec)
4348{
4349 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4350 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4351}
95c6e9cb 4352
e90f29e4
IM		 4353static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4354{
4355 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4356 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4357 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4358 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4359 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4360 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4361
406261ce
IM		 4362 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4363 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 4364 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4365}
4366
4367static bool ca0132_download_dsp_images(struct hda_codec *codec)
4368{
4369 bool dsp_loaded = false;
4370 const struct dsp_image_seg *dsp_os_image;
15e4ba66 4371 const struct firmware *fw_entry;
e90f29e4 4372
6efdd851 4373 if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
e90f29e4
IM		 4374 return false;
4375
15e4ba66 4376 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500
DR		 4377 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4378 pr_err("ca0132 dspload_image failed.\n");
4379 goto exit_download;
4380 }
4381
e90f29e4
IM		 4382 dsp_loaded = dspload_wait_loaded(codec);
4383
d1d28500 4384exit_download:
15e4ba66
TI		 4385 release_firmware(fw_entry);
4386
e90f29e4
IM		 4387 return dsp_loaded;
4388}
4389
4390static void ca0132_download_dsp(struct hda_codec *codec)
4391{
4392 struct ca0132_spec *spec = codec->spec;
4393
9a0869f4
TI		 4394#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4395 return; /* NOP */
4396#endif
e90f29e4 4397
e24aa0a4
TI		 4398 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4399 return; /* don't retry failures */
4400
b714a710
DR		 4401 chipio_enable_clocks(codec);
4402 spec->dsp_state = DSP_DOWNLOADING;
4403 if (!ca0132_download_dsp_images(codec))
4404 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4405 else
4406 spec->dsp_state = DSP_DOWNLOADED;
e90f29e4
IM		 4407
4408 if (spec->dsp_state == DSP_DOWNLOADED)
4409 ca0132_set_dsp_msr(codec, true);
4410}
4411
f8fb1170
TI		 4412static void ca0132_process_dsp_response(struct hda_codec *codec,
4413 struct hda_jack_callback *callback)
e90f29e4
IM		 4414{
4415 struct ca0132_spec *spec = codec->spec;
4416
4e76a883 4417 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 4418 if (spec->wait_scp) {
4419 if (dspio_get_response_data(codec) >= 0)
4420 spec->wait_scp = 0;
4421 }
4422
4423 dspio_clear_response_queue(codec);
4424}
4425
f8fb1170 4426static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 4427{
993884f6 4428 struct ca0132_spec *spec = codec->spec;
e90f29e4 4429
f8fb1170
TI		 4430 /* Delay enabling the HP amp, to let the mic-detection
4431 * state machine run.
4432 */
4433 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 4434 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
f8fb1170
TI		 4435 cb->tbl->block_report = 1;
4436}
4437
4438static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4439{
4440 ca0132_select_mic(codec);
4441}
4442
4443static void ca0132_init_unsol(struct hda_codec *codec)
4444{
d5c016b5
GM		 4445 struct ca0132_spec *spec = codec->spec;
4446 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4447 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 4448 amic_callback);
4449 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4450 ca0132_process_dsp_response);
e90f29e4
IM		 4451}
4452
5aaca44d
IM		 4453/*
4454 * Verbs tables.
4455 */
4456
4457/* Sends before DSP download. */
4458static struct hda_verb ca0132_base_init_verbs[] = {
4459 /*enable ct extension*/
4460 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 4461 {}
4462};
4463
4464/* Send at exit. */
4465static struct hda_verb ca0132_base_exit_verbs[] = {
4466 /*set afg to D3*/
4467 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4468 /*disable ct extension*/
4469 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4470 {}
4471};
4472
4473/* Other verbs tables. Sends after DSP download. */
4474static struct hda_verb ca0132_init_verbs0[] = {
4475 /* chip init verbs */
4476 {0x15, 0x70D, 0xF0},
4477 {0x15, 0x70E, 0xFE},
4478 {0x15, 0x707, 0x75},
4479 {0x15, 0x707, 0xD3},
4480 {0x15, 0x707, 0x09},
4481 {0x15, 0x707, 0x53},
4482 {0x15, 0x707, 0xD4},
4483 {0x15, 0x707, 0xEF},
4484 {0x15, 0x707, 0x75},
4485 {0x15, 0x707, 0xD3},
4486 {0x15, 0x707, 0x09},
4487 {0x15, 0x707, 0x02},
4488 {0x15, 0x707, 0x37},
4489 {0x15, 0x707, 0x78},
4490 {0x15, 0x53C, 0xCE},
4491 {0x15, 0x575, 0xC9},
4492 {0x15, 0x53D, 0xCE},
4493 {0x15, 0x5B7, 0xC9},
4494 {0x15, 0x70D, 0xE8},
4495 {0x15, 0x70E, 0xFE},
4496 {0x15, 0x707, 0x02},
4497 {0x15, 0x707, 0x68},
4498 {0x15, 0x707, 0x62},
4499 {0x15, 0x53A, 0xCE},
4500 {0x15, 0x546, 0xC9},
4501 {0x15, 0x53B, 0xCE},
4502 {0x15, 0x5E8, 0xC9},
4503 {0x15, 0x717, 0x0D},
4504 {0x15, 0x718, 0x20},
4505 {}
4506};
4507
95c6e9cb
IM		 4508static void ca0132_init_chip(struct hda_codec *codec)
4509{
4510 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4511 int num_fx;
4512 int i;
4513 unsigned int on;
95c6e9cb
IM		 4514
4515 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 4516
4517 spec->cur_out_type = SPEAKER_OUT;
4518 spec->cur_mic_type = DIGITAL_MIC;
4519 spec->cur_mic_boost = 0;
4520
4521 for (i = 0; i < VNODES_COUNT; i++) {
4522 spec->vnode_lvol[i] = 0x5a;
4523 spec->vnode_rvol[i] = 0x5a;
4524 spec->vnode_lswitch[i] = 0;
4525 spec->vnode_rswitch[i] = 0;
4526 }
4527
4528 /*
4529 * Default states for effects are in ca0132_effects[].
4530 */
4531 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4532 for (i = 0; i < num_fx; i++) {
4533 on = (unsigned int)ca0132_effects[i].reqs[0];
4534 spec->effects_switch[i] = on ? 1 : 0;
4535 }
4536
4537 spec->voicefx_val = 0;
4538 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4539 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4540
44f0c978
IM		 4541#ifdef ENABLE_TUNING_CONTROLS
4542 ca0132_init_tuning_defaults(codec);
4543#endif
95c6e9cb
IM		 4544}
4545
4546static void ca0132_exit_chip(struct hda_codec *codec)
4547{
4548 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 4549
4550 if (dspload_is_loaded(codec))
4551 dsp_reset(codec);
95c6e9cb
IM		 4552}
4553
4554static int ca0132_init(struct hda_codec *codec)
4555{
4556 struct ca0132_spec *spec = codec->spec;
4557 struct auto_pin_cfg *cfg = &spec->autocfg;
4558 int i;
4559
e24aa0a4
TI		 4560 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4561 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 4562 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 4563
664c7155 4564 snd_hda_power_up_pm(codec);
5aaca44d 4565
f8fb1170
TI		 4566 ca0132_init_unsol(codec);
4567
5aaca44d
IM		 4568 ca0132_init_params(codec);
4569 ca0132_init_flags(codec);
4570 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf 4571 ca0132_download_dsp(codec);
5aaca44d
IM		 4572 ca0132_refresh_widget_caps(codec);
4573 ca0132_setup_defaults(codec);
4574 ca0132_init_analog_mic2(codec);
4575 ca0132_init_dmic(codec);
4576
4577 for (i = 0; i < spec->num_outputs; i++)
4578 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4579
95c6e9cb
IM		 4580 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4581
4582 for (i = 0; i < spec->num_inputs; i++)
4583 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4584
4585 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4586
d5c016b5
GM		 4587 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4588 snd_hda_sequence_write(codec, spec->spec_init_verbs);
5aaca44d
IM		 4589
4590 ca0132_select_out(codec);
4591 ca0132_select_mic(codec);
4592
a73d511c
IM		 4593 snd_hda_jack_report_sync(codec);
4594
664c7155 4595 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 4596
4597 return 0;
4598}
4599
95c6e9cb
IM		 4600static void ca0132_free(struct hda_codec *codec)
4601{
5aaca44d
IM		 4602 struct ca0132_spec *spec = codec->spec;
4603
993884f6 4604 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d
IM		 4605 snd_hda_power_up(codec);
4606 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4607 ca0132_exit_chip(codec);
5aaca44d 4608 snd_hda_power_down(codec);
d5c016b5 4609 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 4610 kfree(codec->spec);
4611}
4612
4613static struct hda_codec_ops ca0132_patch_ops = {
4614 .build_controls = ca0132_build_controls,
4615 .build_pcms = ca0132_build_pcms,
4616 .init = ca0132_init,
4617 .free = ca0132_free,
f8fb1170 4618 .unsol_event = snd_hda_jack_unsol_event,
95c6e9cb
IM		 4619};
4620
441aa6a0
IM		 4621static void ca0132_config(struct hda_codec *codec)
4622{
4623 struct ca0132_spec *spec = codec->spec;
4624 struct auto_pin_cfg *cfg = &spec->autocfg;
4625
4626 spec->dacs[0] = 0x2;
4627 spec->dacs[1] = 0x3;
4628 spec->dacs[2] = 0x4;
4629
4630 spec->multiout.dac_nids = spec->dacs;
4631 spec->multiout.num_dacs = 3;
4632 spec->multiout.max_channels = 2;
4633
d5c016b5
GM		 4634 if (spec->quirk == QUIRK_ALIENWARE) {
4635 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 4636 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4637
4638 spec->num_outputs = 2;
4639 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4640 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 4641 spec->shared_out_nid = 0x2;
4642 spec->unsol_tag_hp = 0x0f;
4643
4644 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4645 spec->adcs[1] = 0x8; /* analog mic2 */
4646 spec->adcs[2] = 0xa; /* what u hear */
4647
4648 spec->num_inputs = 3;
4649 spec->input_pins[0] = 0x12;
4650 spec->input_pins[1] = 0x11;
4651 spec->input_pins[2] = 0x13;
4652 spec->shared_mic_nid = 0x7;
4653 spec->unsol_tag_amic1 = 0x11;
4654 } else {
4655 spec->num_outputs = 2;
4656 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4657 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 4658 spec->shared_out_nid = 0x2;
4659 spec->unsol_tag_hp = spec->out_pins[1];
4660
4661 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4662 spec->adcs[1] = 0x8; /* analog mic2 */
4663 spec->adcs[2] = 0xa; /* what u hear */
4664
4665 spec->num_inputs = 3;
4666 spec->input_pins[0] = 0x12;
4667 spec->input_pins[1] = 0x11;
4668 spec->input_pins[2] = 0x13;
4669 spec->shared_mic_nid = 0x7;
4670 spec->unsol_tag_amic1 = spec->input_pins[0];
4671
4672 /* SPDIF I/O */
4673 spec->dig_out = 0x05;
4674 spec->multiout.dig_out_nid = spec->dig_out;
4675 cfg->dig_out_pins[0] = 0x0c;
4676 cfg->dig_outs = 1;
4677 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4678 spec->dig_in = 0x09;
4679 cfg->dig_in_pin = 0x0e;
4680 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
d5c016b5 4681 }
441aa6a0
IM		 4682}
4683
d5c016b5
GM		 4684static int ca0132_prepare_verbs(struct hda_codec *codec)
4685{
4686/* Verbs + terminator (an empty element) */
4687#define NUM_SPEC_VERBS 4
4688 struct ca0132_spec *spec = codec->spec;
4689
4690 spec->chip_init_verbs = ca0132_init_verbs0;
4691 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4692 if (!spec->spec_init_verbs)
4693 return -ENOMEM;
4694
4695 /* HP jack autodetection */
4696 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4697 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4698 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4699
4700 /* MIC1 jack autodetection */
4701 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4702 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4703 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4704
4705 /* config EAPD */
4706 spec->spec_init_verbs[2].nid = 0x0b;
4707 spec->spec_init_verbs[2].param = 0x78D;
4708 spec->spec_init_verbs[2].verb = 0x00;
4709
4710 /* Previously commented configuration */
4711 /*
4712 spec->spec_init_verbs[3].nid = 0x0b;
4713 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4714 spec->spec_init_verbs[3].verb = 0x02;
4715
4716 spec->spec_init_verbs[4].nid = 0x10;
4717 spec->spec_init_verbs[4].param = 0x78D;
4718 spec->spec_init_verbs[4].verb = 0x02;
4719
4720 spec->spec_init_verbs[5].nid = 0x10;
4721 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4722 spec->spec_init_verbs[5].verb = 0x02;
4723 */
4724
4725 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4726 return 0;
4727}
4728
95c6e9cb
IM		 4729static int patch_ca0132(struct hda_codec *codec)
4730{
4731 struct ca0132_spec *spec;
a73d511c 4732 int err;
d5c016b5 4733 const struct snd_pci_quirk *quirk;
95c6e9cb 4734
4e76a883 4735 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 4736
4737 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4738 if (!spec)
4739 return -ENOMEM;
4740 codec->spec = spec;
993884f6 4741 spec->codec = codec;
95c6e9cb 4742
225068ab
TI		 4743 codec->patch_ops = ca0132_patch_ops;
4744 codec->pcm_format_first = 1;
4745 codec->no_sticky_stream = 1;
4746
d5c016b5
GM		 4747 /* Detect codec quirk */
4748 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4749 if (quirk)
4750 spec->quirk = quirk->value;
4751 else
4752 spec->quirk = QUIRK_NONE;
4753
e24aa0a4 4754 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271
IM		 4755 spec->num_mixers = 1;
4756 spec->mixers[0] = ca0132_mixer;
4757
5aaca44d
IM		 4758 spec->base_init_verbs = ca0132_base_init_verbs;
4759 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 4760
993884f6
CCC		 4761 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4762
95c6e9cb
IM		 4763 ca0132_init_chip(codec);
4764
4765 ca0132_config(codec);
4766
d5c016b5
GM		 4767 err = ca0132_prepare_verbs(codec);
4768 if (err < 0)
4769 return err;
4770
a73d511c
IM		 4771 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4772 if (err < 0)
4773 return err;
4774
95c6e9cb
IM		 4775 return 0;
4776}
4777
4778/*
4779 * patch entries
4780 */
4781static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4782 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4783 {} /* terminator */
4784};
4785
4786MODULE_ALIAS("snd-hda-codec-id:11020011");
4787
4788MODULE_LICENSE("GPL");
406261ce 4789MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 4790
d8a766a1 4791static struct hda_codec_driver ca0132_driver = {
95c6e9cb 4792 .preset = snd_hda_preset_ca0132,
95c6e9cb
IM		 4793};
4794
d8a766a1 4795module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)