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ALSA: hda/ca0132 - Add DBpro hda_codec_ops
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb 34#include <sound/core.h>
be57bfff 35#include <sound/hda_codec.h>
95c6e9cb 36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
38ba69ff 52#define FLOAT_THREE 0x40400000
7cb9d94c 53#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 54#define FLOAT_MINUS_5 0xc0a00000
55
ef6b2ead
IM		 56#define UNSOL_TAG_DSP 0x16
57
4aa3bb0c
IM		 58#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
ef6b2ead
IM		 66#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 68
95c6e9cb
IM		 69#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
4aa3bb0c
IM		 72#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
01ef7dbf 83#define EFX_FILE "ctefx.bin"
7a928186 84#define DESKTOP_EFX_FILE "ctefx-desktop.bin"
8a19bcee 85#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 86
24f3cede 87#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 88MODULE_FIRMWARE(EFX_FILE);
7a928186 89MODULE_FIRMWARE(DESKTOP_EFX_FILE);
8a19bcee 90MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 91#endif
01ef7dbf 92
3a03f83b 93static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 94
7cb9d94c 95#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 96enum {
97 SPEAKER_OUT,
7cb9d94c
CM		 98 HEADPHONE_OUT,
99 SURROUND_OUT
ef6b2ead
IM		 100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
7cb9d94c 107/* Strings for Input Source Enum Control */
3a03f83b 108static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
ef6b2ead
IM		 116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
7cb9d94c
CM		 149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
212de2e7
CM		 155 MIC_BOOST_ENUM,
156 AE5_HEADPHONE_GAIN_ENUM,
157 AE5_SOUND_FILTER_ENUM
ef6b2ead
IM		 158#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
159};
160
161/* Effects values size*/
162#define EFFECT_VALS_MAX_COUNT 12
163
47cdf76e
CM		 164/*
165 * Default values for the effect slider controls, they are in order of their
166 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
167 * X-bass.
168 */
169static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
170/* Amount of effect level sliders for ca0132_alt controls. */
171#define EFFECT_LEVEL_SLIDERS 5
172
e8412ca4
DR		 173/* Latency introduced by DSP blocks in milliseconds. */
174#define DSP_CAPTURE_INIT_LATENCY 0
175#define DSP_CRYSTAL_VOICE_LATENCY 124
176#define DSP_PLAYBACK_INIT_LATENCY 13
177#define DSP_PLAY_ENHANCEMENT_LATENCY 30
178#define DSP_SPEAKER_OUT_LATENCY 7
179
ef6b2ead 180struct ct_effect {
975cc02a 181 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 182 hda_nid_t nid;
183 int mid; /*effect module ID*/
184 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
185 int direct; /* 0:output; 1:input*/
186 int params; /* number of default non-on/off params */
187 /*effect default values, 1st is on/off. */
188 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
189};
190
191#define EFX_DIR_OUT 0
192#define EFX_DIR_IN 1
193
862154bb 194static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 195 { .name = "Surround",
196 .nid = SURROUND,
197 .mid = 0x96,
198 .reqs = {0, 1},
199 .direct = EFX_DIR_OUT,
200 .params = 1,
201 .def_vals = {0x3F800000, 0x3F2B851F}
202 },
203 { .name = "Crystalizer",
204 .nid = CRYSTALIZER,
205 .mid = 0x96,
206 .reqs = {7, 8},
207 .direct = EFX_DIR_OUT,
208 .params = 1,
209 .def_vals = {0x3F800000, 0x3F266666}
210 },
211 { .name = "Dialog Plus",
212 .nid = DIALOG_PLUS,
213 .mid = 0x96,
214 .reqs = {2, 3},
215 .direct = EFX_DIR_OUT,
216 .params = 1,
217 .def_vals = {0x00000000, 0x3F000000}
218 },
219 { .name = "Smart Volume",
220 .nid = SMART_VOLUME,
221 .mid = 0x96,
222 .reqs = {4, 5, 6},
223 .direct = EFX_DIR_OUT,
224 .params = 2,
225 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
226 },
227 { .name = "X-Bass",
228 .nid = X_BASS,
229 .mid = 0x96,
230 .reqs = {24, 23, 25},
231 .direct = EFX_DIR_OUT,
232 .params = 2,
233 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
234 },
235 { .name = "Equalizer",
236 .nid = EQUALIZER,
237 .mid = 0x96,
238 .reqs = {9, 10, 11, 12, 13, 14,
239 15, 16, 17, 18, 19, 20},
240 .direct = EFX_DIR_OUT,
241 .params = 11,
242 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
243 0x00000000, 0x00000000, 0x00000000, 0x00000000,
244 0x00000000, 0x00000000, 0x00000000, 0x00000000}
245 },
246 { .name = "Echo Cancellation",
247 .nid = ECHO_CANCELLATION,
248 .mid = 0x95,
249 .reqs = {0, 1, 2, 3},
250 .direct = EFX_DIR_IN,
251 .params = 3,
252 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
253 },
254 { .name = "Voice Focus",
255 .nid = VOICE_FOCUS,
256 .mid = 0x95,
257 .reqs = {6, 7, 8, 9},
258 .direct = EFX_DIR_IN,
259 .params = 3,
260 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
261 },
262 { .name = "Mic SVM",
263 .nid = MIC_SVM,
264 .mid = 0x95,
265 .reqs = {44, 45},
266 .direct = EFX_DIR_IN,
267 .params = 1,
268 .def_vals = {0x00000000, 0x3F3D70A4}
269 },
270 { .name = "Noise Reduction",
271 .nid = NOISE_REDUCTION,
272 .mid = 0x95,
273 .reqs = {4, 5},
274 .direct = EFX_DIR_IN,
275 .params = 1,
276 .def_vals = {0x3F800000, 0x3F000000}
277 },
278 { .name = "VoiceFX",
279 .nid = VOICEFX,
280 .mid = 0x95,
281 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
282 .direct = EFX_DIR_IN,
283 .params = 8,
284 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
285 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
286 0x00000000}
287 }
288};
289
290/* Tuning controls */
291#ifdef ENABLE_TUNING_CONTROLS
292
293enum {
294#define TUNING_CTL_START_NID 0xC0
295 WEDGE_ANGLE = TUNING_CTL_START_NID,
296 SVM_LEVEL,
297 EQUALIZER_BAND_0,
298 EQUALIZER_BAND_1,
299 EQUALIZER_BAND_2,
300 EQUALIZER_BAND_3,
301 EQUALIZER_BAND_4,
302 EQUALIZER_BAND_5,
303 EQUALIZER_BAND_6,
304 EQUALIZER_BAND_7,
305 EQUALIZER_BAND_8,
306 EQUALIZER_BAND_9,
307 TUNING_CTL_END_NID
308#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
309};
310
311struct ct_tuning_ctl {
975cc02a 312 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 313 hda_nid_t parent_nid;
314 hda_nid_t nid;
315 int mid; /*effect module ID*/
316 int req; /*effect module request*/
317 int direct; /* 0:output; 1:input*/
318 unsigned int def_val;/*effect default values*/
319};
320
862154bb 321static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 322 { .name = "Wedge Angle",
323 .parent_nid = VOICE_FOCUS,
324 .nid = WEDGE_ANGLE,
325 .mid = 0x95,
326 .req = 8,
327 .direct = EFX_DIR_IN,
328 .def_val = 0x41F00000
329 },
330 { .name = "SVM Level",
331 .parent_nid = MIC_SVM,
332 .nid = SVM_LEVEL,
333 .mid = 0x95,
334 .req = 45,
335 .direct = EFX_DIR_IN,
336 .def_val = 0x3F3D70A4
337 },
338 { .name = "EQ Band0",
339 .parent_nid = EQUALIZER,
340 .nid = EQUALIZER_BAND_0,
341 .mid = 0x96,
342 .req = 11,
343 .direct = EFX_DIR_OUT,
344 .def_val = 0x00000000
345 },
346 { .name = "EQ Band1",
347 .parent_nid = EQUALIZER,
348 .nid = EQUALIZER_BAND_1,
349 .mid = 0x96,
350 .req = 12,
351 .direct = EFX_DIR_OUT,
352 .def_val = 0x00000000
353 },
354 { .name = "EQ Band2",
355 .parent_nid = EQUALIZER,
356 .nid = EQUALIZER_BAND_2,
357 .mid = 0x96,
358 .req = 13,
359 .direct = EFX_DIR_OUT,
360 .def_val = 0x00000000
361 },
362 { .name = "EQ Band3",
363 .parent_nid = EQUALIZER,
364 .nid = EQUALIZER_BAND_3,
365 .mid = 0x96,
366 .req = 14,
367 .direct = EFX_DIR_OUT,
368 .def_val = 0x00000000
369 },
370 { .name = "EQ Band4",
371 .parent_nid = EQUALIZER,
372 .nid = EQUALIZER_BAND_4,
373 .mid = 0x96,
374 .req = 15,
375 .direct = EFX_DIR_OUT,
376 .def_val = 0x00000000
377 },
378 { .name = "EQ Band5",
379 .parent_nid = EQUALIZER,
380 .nid = EQUALIZER_BAND_5,
381 .mid = 0x96,
382 .req = 16,
383 .direct = EFX_DIR_OUT,
384 .def_val = 0x00000000
385 },
386 { .name = "EQ Band6",
387 .parent_nid = EQUALIZER,
388 .nid = EQUALIZER_BAND_6,
389 .mid = 0x96,
390 .req = 17,
391 .direct = EFX_DIR_OUT,
392 .def_val = 0x00000000
393 },
394 { .name = "EQ Band7",
395 .parent_nid = EQUALIZER,
396 .nid = EQUALIZER_BAND_7,
397 .mid = 0x96,
398 .req = 18,
399 .direct = EFX_DIR_OUT,
400 .def_val = 0x00000000
401 },
402 { .name = "EQ Band8",
403 .parent_nid = EQUALIZER,
404 .nid = EQUALIZER_BAND_8,
405 .mid = 0x96,
406 .req = 19,
407 .direct = EFX_DIR_OUT,
408 .def_val = 0x00000000
409 },
410 { .name = "EQ Band9",
411 .parent_nid = EQUALIZER,
412 .nid = EQUALIZER_BAND_9,
413 .mid = 0x96,
414 .req = 20,
415 .direct = EFX_DIR_OUT,
416 .def_val = 0x00000000
417 }
418};
419#endif
420
421/* Voice FX Presets */
422#define VOICEFX_MAX_PARAM_COUNT 9
423
424struct ct_voicefx {
425 char *name;
426 hda_nid_t nid;
427 int mid;
428 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
429};
430
431struct ct_voicefx_preset {
432 char *name; /*preset name*/
433 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
434};
435
862154bb 436static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 437 .name = "VoiceFX Capture Switch",
438 .nid = VOICEFX,
439 .mid = 0x95,
440 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
441};
442
862154bb 443static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 444 { .name = "Neutral",
445 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
446 0x44FA0000, 0x3F800000, 0x3F800000,
447 0x3F800000, 0x00000000, 0x00000000 }
448 },
449 { .name = "Female2Male",
450 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
451 0x44FA0000, 0x3F19999A, 0x3F866666,
452 0x3F800000, 0x00000000, 0x00000000 }
453 },
454 { .name = "Male2Female",
455 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
456 0x450AC000, 0x4017AE14, 0x3F6B851F,
457 0x3F800000, 0x00000000, 0x00000000 }
458 },
459 { .name = "ScrappyKid",
460 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
461 0x44FA0000, 0x40400000, 0x3F28F5C3,
462 0x3F800000, 0x00000000, 0x00000000 }
463 },
464 { .name = "Elderly",
465 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
466 0x44E10000, 0x3FB33333, 0x3FB9999A,
467 0x3F800000, 0x3E3A2E43, 0x00000000 }
468 },
469 { .name = "Orc",
470 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
471 0x45098000, 0x3F266666, 0x3FC00000,
472 0x3F800000, 0x00000000, 0x00000000 }
473 },
474 { .name = "Elf",
475 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
476 0x45193000, 0x3F8E147B, 0x3F75C28F,
477 0x3F800000, 0x00000000, 0x00000000 }
478 },
479 { .name = "Dwarf",
480 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
481 0x45007000, 0x3F451EB8, 0x3F7851EC,
482 0x3F800000, 0x00000000, 0x00000000 }
483 },
484 { .name = "AlienBrute",
485 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
486 0x451F6000, 0x3F266666, 0x3FA7D945,
487 0x3F800000, 0x3CF5C28F, 0x00000000 }
488 },
489 { .name = "Robot",
490 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
491 0x44FA0000, 0x3FB2718B, 0x3F800000,
492 0xBC07010E, 0x00000000, 0x00000000 }
493 },
494 { .name = "Marine",
495 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
496 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
497 0x3F0A3D71, 0x00000000, 0x00000000 }
498 },
499 { .name = "Emo",
500 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
501 0x44FA0000, 0x3F800000, 0x3F800000,
502 0x3E4CCCCD, 0x00000000, 0x00000000 }
503 },
504 { .name = "DeepVoice",
505 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
506 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
507 0x3F800000, 0x00000000, 0x00000000 }
508 },
509 { .name = "Munchkin",
510 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
511 0x44FA0000, 0x3F800000, 0x3F1A043C,
512 0x3F800000, 0x00000000, 0x00000000 }
513 }
514};
515
47cdf76e
CM		 516/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
517
518#define EQ_PRESET_MAX_PARAM_COUNT 11
519
520struct ct_eq {
521 char *name;
522 hda_nid_t nid;
523 int mid;
524 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
525};
526
527struct ct_eq_preset {
528 char *name; /*preset name*/
529 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
530};
531
862154bb 532static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 533 .name = "FX: Equalizer Preset Switch",
534 .nid = EQ_PRESET_ENUM,
535 .mid = 0x96,
536 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
537};
538
539
862154bb 540static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 541 { .name = "Flat",
542 .vals = { 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000, 0x00000000,
544 0x00000000, 0x00000000, 0x00000000,
545 0x00000000, 0x00000000 }
546 },
547 { .name = "Acoustic",
548 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
549 0x40000000, 0x00000000, 0x00000000,
550 0x00000000, 0x00000000, 0x40000000,
551 0x40000000, 0x40000000 }
552 },
553 { .name = "Classical",
554 .vals = { 0x00000000, 0x00000000, 0x40C00000,
555 0x40C00000, 0x40466666, 0x00000000,
556 0x00000000, 0x00000000, 0x00000000,
557 0x40466666, 0x40466666 }
558 },
559 { .name = "Country",
560 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
561 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
562 0x00000000, 0x00000000, 0x40000000,
563 0x40466666, 0x40800000 }
564 },
565 { .name = "Dance",
566 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
567 0x40466666, 0x40866666, 0xBF99999A,
568 0xBF99999A, 0x00000000, 0x00000000,
569 0x40800000, 0x40800000 }
570 },
571 { .name = "Jazz",
572 .vals = { 0x00000000, 0x00000000, 0x00000000,
573 0x3F8CCCCD, 0x40800000, 0x40800000,
574 0x40800000, 0x00000000, 0x3F8CCCCD,
575 0x40466666, 0x40466666 }
576 },
577 { .name = "New Age",
578 .vals = { 0x00000000, 0x00000000, 0x40000000,
579 0x40000000, 0x00000000, 0x00000000,
580 0x00000000, 0x3F8CCCCD, 0x40000000,
581 0x40000000, 0x40000000 }
582 },
583 { .name = "Pop",
584 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
585 0x40000000, 0x40000000, 0x00000000,
586 0xBF99999A, 0xBF99999A, 0x00000000,
587 0x40466666, 0x40C00000 }
588 },
589 { .name = "Rock",
590 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
591 0x3F8CCCCD, 0x40000000, 0xBF99999A,
592 0xBF99999A, 0x00000000, 0x00000000,
593 0x40800000, 0x40800000 }
594 },
595 { .name = "Vocal",
596 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
597 0xBF99999A, 0x00000000, 0x40466666,
598 0x40800000, 0x40466666, 0x00000000,
599 0x00000000, 0x3F8CCCCD }
600 }
601};
602
7cb9d94c
CM		 603/* DSP command sequences for ca0132_alt_select_out */
604#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
605struct ca0132_alt_out_set {
606 char *name; /*preset name*/
607 unsigned char commands;
608 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
609 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
610 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
611};
612
613static const struct ca0132_alt_out_set alt_out_presets[] = {
614 { .name = "Line Out",
615 .commands = 7,
616 .mids = { 0x96, 0x96, 0x96, 0x8F,
617 0x96, 0x96, 0x96 },
618 .reqs = { 0x19, 0x17, 0x18, 0x01,
619 0x1F, 0x15, 0x3A },
620 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
621 0x00000000, 0x00000000, 0x00000000,
622 0x00000000 }
623 },
624 { .name = "Headphone",
625 .commands = 7,
626 .mids = { 0x96, 0x96, 0x96, 0x8F,
627 0x96, 0x96, 0x96 },
628 .reqs = { 0x19, 0x17, 0x18, 0x01,
629 0x1F, 0x15, 0x3A },
630 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
631 0x00000000, 0x00000000, 0x00000000,
632 0x00000000 }
633 },
634 { .name = "Surround",
635 .commands = 8,
636 .mids = { 0x96, 0x8F, 0x96, 0x96,
637 0x96, 0x96, 0x96, 0x96 },
638 .reqs = { 0x18, 0x01, 0x1F, 0x15,
639 0x3A, 0x1A, 0x1B, 0x1C },
640 .vals = { 0x00000000, 0x00000000, 0x00000000,
641 0x00000000, 0x00000000, 0x00000000,
642 0x00000000, 0x00000000 }
643 }
644};
645
017310fb
CM		 646/*
647 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
648 * and I don't know what the third req is, but it's always zero. I assume it's
649 * some sort of update or set command to tell the DSP there's new volume info.
650 */
651#define DSP_VOL_OUT 0
652#define DSP_VOL_IN 1
653
654struct ct_dsp_volume_ctl {
655 hda_nid_t vnid;
656 int mid; /* module ID*/
657 unsigned int reqs[3]; /* scp req ID */
658};
659
862154bb 660static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 661 { .vnid = VNID_SPK,
662 .mid = 0x32,
663 .reqs = {3, 4, 2}
664 },
665 { .vnid = VNID_MIC,
666 .mid = 0x37,
667 .reqs = {2, 3, 1}
668 }
669};
670
2283c85b
CM		 671/* Values for ca0113_mmio_command_set for selecting output. */
672#define AE5_CA0113_OUT_SET_COMMANDS 6
673struct ae5_ca0113_output_set {
674 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS];
675 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS];
676 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS];
677};
678
679static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = {
680 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
681 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
682 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
683 },
684 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
685 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
686 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 }
687 },
688 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
689 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
690 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
691 }
692};
693
212de2e7
CM		 694/* ae5 ca0113 command sequences to set headphone gain levels. */
695#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
696struct ae5_headphone_gain_set {
697 char *name;
698 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
699};
700
701static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
702 { .name = "Low (16-31",
703 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
704 },
705 { .name = "Medium (32-149",
706 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
707 },
708 { .name = "High (150-600",
709 .vals = { 0xff, 0xff, 0xff, 0x7f }
710 }
711};
712
713struct ae5_filter_set {
714 char *name;
715 unsigned int val;
716};
717
718static const struct ae5_filter_set ae5_filter_presets[] = {
719 { .name = "Slow Roll Off",
720 .val = 0xa0
721 },
722 { .name = "Minimum Phase",
723 .val = 0xc0
724 },
725 { .name = "Fast Roll Off",
726 .val = 0x80
727 }
728};
729
95c6e9cb
IM		 730enum hda_cmd_vendor_io {
731 /* for DspIO node */
732 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
733 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
734
735 VENDOR_DSPIO_STATUS = 0xF01,
736 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
737 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
738 VENDOR_DSPIO_DSP_INIT = 0x703,
739 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
740 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
741
742 /* for ChipIO node */
743 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
744 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
745 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
746 VENDOR_CHIPIO_DATA_LOW = 0x300,
747 VENDOR_CHIPIO_DATA_HIGH = 0x400,
748
bf85a91c
CM		 749 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
750 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
751
95c6e9cb
IM		 752 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
753 VENDOR_CHIPIO_STATUS = 0xF01,
754 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
755 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
756
4aa3bb0c
IM		 757 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
758 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
bf85a91c
CM		 759 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
760 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
761 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
4aa3bb0c 762
95c6e9cb 763 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 764 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 765
766 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
767 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
768 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
769 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
770 VENDOR_CHIPIO_FLAG_SET = 0x70F,
771 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 772 VENDOR_CHIPIO_PARAM_SET = 0x710,
773 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 774
775 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
776 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
777 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
778 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
779
4aa3bb0c
IM		 780 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
781 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
782 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
783 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
784
785 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
786 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
787 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
788 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
789 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
790 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
791
792 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 793};
794
795/*
796 * Control flag IDs
797 */
798enum control_flag_id {
799 /* Connection manager stream setup is bypassed/enabled */
800 CONTROL_FLAG_C_MGR = 0,
801 /* DSP DMA is bypassed/enabled */
802 CONTROL_FLAG_DMA = 1,
803 /* 8051 'idle' mode is disabled/enabled */
804 CONTROL_FLAG_IDLE_ENABLE = 2,
805 /* Tracker for the SPDIF-in path is bypassed/enabled */
806 CONTROL_FLAG_TRACKER = 3,
807 /* DigitalOut to Spdif2Out connection is disabled/enabled */
808 CONTROL_FLAG_SPDIF2OUT = 4,
809 /* Digital Microphone is disabled/enabled */
810 CONTROL_FLAG_DMIC = 5,
811 /* ADC_B rate is 48 kHz/96 kHz */
812 CONTROL_FLAG_ADC_B_96KHZ = 6,
813 /* ADC_C rate is 48 kHz/96 kHz */
814 CONTROL_FLAG_ADC_C_96KHZ = 7,
815 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
816 CONTROL_FLAG_DAC_96KHZ = 8,
817 /* DSP rate is 48 kHz/96 kHz */
818 CONTROL_FLAG_DSP_96KHZ = 9,
819 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
820 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
821 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
822 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
823 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
824 CONTROL_FLAG_DECODE_LOOP = 12,
825 /* De-emphasis filter on DAC-1 disabled/enabled */
826 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
827 /* De-emphasis filter on DAC-2 disabled/enabled */
828 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
829 /* De-emphasis filter on DAC-3 disabled/enabled */
830 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
831 /* High-pass filter on ADC_B disabled/enabled */
832 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
833 /* High-pass filter on ADC_C disabled/enabled */
834 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
835 /* Common mode on Port_A disabled/enabled */
836 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
837 /* Common mode on Port_D disabled/enabled */
838 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
839 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
840 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
841 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 842 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 843 /* ASI rate is 48kHz/96kHz */
844 CONTROL_FLAG_ASI_96KHZ = 22,
845 /* DAC power settings able to control attached ports no/yes */
846 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
847 /* Clock Stop OK reporting is disabled/enabled */
848 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
849 /* Number of control flags */
850 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
851};
852
853/*
854 * Control parameter IDs
855 */
4aa3bb0c 856enum control_param_id {
ef6b2ead
IM		 857 /* 0: None, 1: Mic1In*/
858 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 859 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
860 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 861 /* Port A output stage gain setting to use when 16 Ohm output
862 * impedance is selected*/
863 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
864 /* Port D output stage gain setting to use when 16 Ohm output
865 * impedance is selected*/
866 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb 867
bf85a91c
CM		 868 /*
869 * This control param name was found in the 8051 memory, and makes
870 * sense given the fact the AE-5 uses it and has the ASI flag set.
871 */
872 CONTROL_PARAM_ASI = 23,
873
95c6e9cb
IM		 874 /* Stream Control */
875
876 /* Select stream with the given ID */
877 CONTROL_PARAM_STREAM_ID = 24,
878 /* Source connection point for the selected stream */
879 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
880 /* Destination connection point for the selected stream */
881 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
882 /* Number of audio channels in the selected stream */
883 CONTROL_PARAM_STREAMS_CHANNELS = 27,
884 /*Enable control for the selected stream */
885 CONTROL_PARAM_STREAM_CONTROL = 28,
886
887 /* Connection Point Control */
888
889 /* Select connection point with the given ID */
890 CONTROL_PARAM_CONN_POINT_ID = 29,
891 /* Connection point sample rate */
892 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
893
894 /* Node Control */
895
896 /* Select HDA node with the given ID */
897 CONTROL_PARAM_NODE_ID = 31
898};
899
900/*
901 * Dsp Io Status codes
902 */
903enum hda_vendor_status_dspio {
904 /* Success */
905 VENDOR_STATUS_DSPIO_OK = 0x00,
906 /* Busy, unable to accept new command, the host must retry */
907 VENDOR_STATUS_DSPIO_BUSY = 0x01,
908 /* SCP command queue is full */
909 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
910 /* SCP response queue is empty */
911 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
912};
913
914/*
915 * Chip Io Status codes
916 */
917enum hda_vendor_status_chipio {
918 /* Success */
919 VENDOR_STATUS_CHIPIO_OK = 0x00,
920 /* Busy, unable to accept new command, the host must retry */
921 VENDOR_STATUS_CHIPIO_BUSY = 0x01
922};
923
924/*
925 * CA0132 sample rate
926 */
927enum ca0132_sample_rate {
928 SR_6_000 = 0x00,
929 SR_8_000 = 0x01,
930 SR_9_600 = 0x02,
931 SR_11_025 = 0x03,
932 SR_16_000 = 0x04,
933 SR_22_050 = 0x05,
934 SR_24_000 = 0x06,
935 SR_32_000 = 0x07,
936 SR_44_100 = 0x08,
937 SR_48_000 = 0x09,
938 SR_88_200 = 0x0A,
939 SR_96_000 = 0x0B,
940 SR_144_000 = 0x0C,
941 SR_176_400 = 0x0D,
942 SR_192_000 = 0x0E,
943 SR_384_000 = 0x0F,
944
945 SR_COUNT = 0x10,
946
947 SR_RATE_UNKNOWN = 0x1F
948};
949
01ef7dbf
IM		 950enum dsp_download_state {
951 DSP_DOWNLOAD_FAILED = -1,
952 DSP_DOWNLOAD_INIT = 0,
953 DSP_DOWNLOADING = 1,
954 DSP_DOWNLOADED = 2
955};
956
01ef7dbf
IM		 957/* retrieve parameters from hda format */
958#define get_hdafmt_chs(fmt) (fmt & 0xf)
959#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
960#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
961#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
962
963/*
964 * CA0132 specific
965 */
966
967struct ca0132_spec {
b0eaa072 968 const struct snd_kcontrol_new *mixers[5];
a7e76271 969 unsigned int num_mixers;
5aaca44d
IM		 970 const struct hda_verb *base_init_verbs;
971 const struct hda_verb *base_exit_verbs;
d5c016b5 972 const struct hda_verb *chip_init_verbs;
e42c7c73 973 const struct hda_verb *desktop_init_verbs;
d5c016b5 974 struct hda_verb *spec_init_verbs;
01ef7dbf 975 struct auto_pin_cfg autocfg;
5aaca44d
IM		 976
977 /* Nodes configurations */
01ef7dbf
IM		 978 struct hda_multi_out multiout;
979 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
980 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 981 unsigned int num_outputs;
01ef7dbf
IM		 982 hda_nid_t input_pins[AUTO_PIN_LAST];
983 hda_nid_t adcs[AUTO_PIN_LAST];
984 hda_nid_t dig_out;
985 hda_nid_t dig_in;
986 unsigned int num_inputs;
a7e76271
IM		 987 hda_nid_t shared_mic_nid;
988 hda_nid_t shared_out_nid;
d5c016b5 989 hda_nid_t unsol_tag_hp;
63177afc 990 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 991 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 992
993 /* chip access */
994 struct mutex chipio_mutex; /* chip access mutex */
995 u32 curr_chip_addx;
996
997 /* DSP download related */
998 enum dsp_download_state dsp_state;
999 unsigned int dsp_stream_id;
1000 unsigned int wait_scp;
1001 unsigned int wait_scp_header;
1002 unsigned int wait_num_data;
1003 unsigned int scp_resp_header;
1004 unsigned int scp_resp_data[4];
1005 unsigned int scp_resp_count;
8a19bcee 1006 bool alt_firmware_present;
38ba69ff 1007 bool startup_check_entered;
e93ac30a 1008 bool dsp_reload;
5aaca44d
IM		 1009
1010 /* mixer and effects related */
1011 unsigned char dmic_ctl;
1012 int cur_out_type;
1013 int cur_mic_type;
1014 long vnode_lvol[VNODES_COUNT];
1015 long vnode_rvol[VNODES_COUNT];
1016 long vnode_lswitch[VNODES_COUNT];
1017 long vnode_rswitch[VNODES_COUNT];
1018 long effects_switch[EFFECTS_COUNT];
1019 long voicefx_val;
1020 long cur_mic_boost;
7cb9d94c
CM		 1021 /* ca0132_alt control related values */
1022 unsigned char in_enum_val;
1023 unsigned char out_enum_val;
47cdf76e
CM		 1024 unsigned char mic_boost_enum_val;
1025 unsigned char smart_volume_setting;
1026 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1027 long xbass_xover_freq;
1028 long eq_preset_val;
1029 unsigned int tlv[4];
1030 struct hda_vmaster_mute_hook vmaster_mute;
212de2e7
CM		 1031 /* AE-5 Control values */
1032 unsigned char ae5_headphone_gain_val;
1033 unsigned char ae5_filter_val;
47cdf76e 1034
44f0c978 1035
993884f6
CCC		 1036 struct hda_codec *codec;
1037 struct delayed_work unsol_hp_work;
d5c016b5 1038 int quirk;
993884f6 1039
44f0c978
IM		 1040#ifdef ENABLE_TUNING_CONTROLS
1041 long cur_ctl_vals[TUNING_CTLS_COUNT];
1042#endif
aa31704f 1043 /*
08eca6b1
CM		 1044 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1045 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1046 * things.
aa31704f 1047 */
08eca6b1 1048 bool use_pci_mmio;
aa31704f 1049 void __iomem *mem_base;
009b8f97
CM		 1050
1051 /*
1052 * Whether or not to use the alt functions like alt_select_out,
1053 * alt_select_in, etc. Only used on desktop codecs for now, because of
1054 * surround sound support.
1055 */
1056 bool use_alt_functions;
47cdf76e
CM		 1057
1058 /*
1059 * Whether or not to use alt controls: volume effect sliders, EQ
1060 * presets, smart volume presets, and new control names with FX prefix.
1061 * Renames PlayEnhancement and CrystalVoice too.
1062 */
1063 bool use_alt_controls;
01ef7dbf
IM		 1064};
1065
d5c016b5
GM		 1066/*
1067 * CA0132 quirks table
1068 */
1069enum {
1070 QUIRK_NONE,
1071 QUIRK_ALIENWARE,
a57a46b9 1072 QUIRK_ALIENWARE_M17XR4,
8a19bcee 1073 QUIRK_SBZ,
b29733db
CM		 1074 QUIRK_ZXR,
1075 QUIRK_ZXR_DBPRO,
8a19bcee 1076 QUIRK_R3DI,
8f8c523c 1077 QUIRK_R3D,
f6276463 1078 QUIRK_AE5,
d5c016b5
GM		 1079};
1080
fe14f39e
TI		 1081static const struct hda_pintbl alienware_pincfgs[] = {
1082 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1083 { 0x0c, 0x411111f0 }, /* N/A */
1084 { 0x0d, 0x411111f0 }, /* N/A */
1085 { 0x0e, 0x411111f0 }, /* N/A */
1086 { 0x0f, 0x0321101f }, /* HP */
1087 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1088 { 0x11, 0x03a11021 }, /* Mic */
1089 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1090 { 0x13, 0x411111f0 }, /* N/A */
1091 { 0x18, 0x411111f0 }, /* N/A */
1092 {}
1093};
1094
63177afc
CM		 1095/* Sound Blaster Z pin configs taken from Windows Driver */
1096static const struct hda_pintbl sbz_pincfgs[] = {
1097 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1098 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1099 { 0x0d, 0x014510f0 }, /* Digital Out */
1100 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1101 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1102 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1103 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1104 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1105 { 0x13, 0x908700f0 }, /* What U Hear In*/
1106 { 0x18, 0x50d000f0 }, /* N/A */
1107 {}
1108};
1109
6dcd7244
CM		 1110/* Sound Blaster ZxR pin configs taken from Windows Driver */
1111static const struct hda_pintbl zxr_pincfgs[] = {
1112 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1113 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1114 { 0x0d, 0x014510f0 }, /* Digital Out */
1115 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1116 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1117 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1118 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1119 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1120 { 0x13, 0x908700f0 }, /* What U Hear In*/
1121 { 0x18, 0x50d000f0 }, /* N/A */
1122 {}
1123};
1124
7f73df95
CM		 1125/* Recon3D pin configs taken from Windows Driver */
1126static const struct hda_pintbl r3d_pincfgs[] = {
1127 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1128 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1129 { 0x0d, 0x014510f0 }, /* Digital Out */
1130 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1131 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1132 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1133 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1134 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1135 { 0x13, 0x908700f0 }, /* What U Hear In*/
1136 { 0x18, 0x50d000f0 }, /* N/A */
1137 {}
1138};
1139
d06feaf0
CM		 1140/* Sound Blaster AE-5 pin configs taken from Windows Driver */
1141static const struct hda_pintbl ae5_pincfgs[] = {
1142 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1143 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1144 { 0x0d, 0x014510f0 }, /* Digital Out */
1145 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1146 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1147 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1148 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1149 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1150 { 0x13, 0x908700f0 }, /* What U Hear In*/
1151 { 0x18, 0x50d000f0 }, /* N/A */
1152 {}
1153};
1154
63177afc
CM		 1155/* Recon3D integrated pin configs taken from Windows Driver */
1156static const struct hda_pintbl r3di_pincfgs[] = {
1157 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1158 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1159 { 0x0d, 0x014510f0 }, /* Digital Out */
1160 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1161 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1162 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1163 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1164 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1165 { 0x13, 0x908700f0 }, /* What U Hear In*/
1166 { 0x18, 0x500000f0 }, /* N/A */
1167 {}
1168};
1169
d5c016b5 1170static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1171 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1172 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1173 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1174 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1175 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1176 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1177 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1178 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1179 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
8f8c523c 1180 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
f6276463 1181 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
d5c016b5
GM		 1182 {}
1183};
1184
01ef7dbf
IM		 1185/*
1186 * CA0132 codec access
1187 */
399ae725 1188static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1189 unsigned int verb, unsigned int parm, unsigned int *res)
1190{
1191 unsigned int response;
1192 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1193 *res = response;
1194
1195 return ((response == -1) ? -1 : 0);
1196}
1197
1198static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1199 unsigned short converter_format, unsigned int *res)
1200{
1201 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1202 converter_format & 0xffff, res);
1203}
1204
1205static int codec_set_converter_stream_channel(struct hda_codec *codec,
1206 hda_nid_t nid, unsigned char stream,
1207 unsigned char channel, unsigned int *res)
1208{
1209 unsigned char converter_stream_channel = 0;
1210
1211 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1212 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1213 converter_stream_channel, res);
1214}
1215
1216/* Chip access helper function */
1217static int chipio_send(struct hda_codec *codec,
1218 unsigned int reg,
1219 unsigned int data)
1220{
1221 unsigned int res;
6d67530e 1222 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1223
1224 /* send bits of data specified by reg */
1225 do {
1226 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1227 reg, data);
1228 if (res == VENDOR_STATUS_CHIPIO_OK)
1229 return 0;
6d67530e
IM		 1230 msleep(20);
1231 } while (time_before(jiffies, timeout));
1232
01ef7dbf
IM		 1233 return -EIO;
1234}
1235
1236/*
1237 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1238 */
1239static int chipio_write_address(struct hda_codec *codec,
1240 unsigned int chip_addx)
1241{
4861af80 1242 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1243 int res;
1244
4861af80
IM		 1245 if (spec->curr_chip_addx == chip_addx)
1246 return 0;
1247
01ef7dbf
IM		 1248 /* send low 16 bits of the address */
1249 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1250 chip_addx & 0xffff);
1251
1252 if (res != -EIO) {
1253 /* send high 16 bits of the address */
1254 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1255 chip_addx >> 16);
1256 }
1257
d1600401 1258 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1259
4861af80 1260 return res;
01ef7dbf
IM		 1261}
1262
1263/*
1264 * Write data through the vendor widget -- NOT protected by the Mutex!
1265 */
01ef7dbf
IM		 1266static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1267{
5aaca44d 1268 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1269 int res;
1270
1271 /* send low 16 bits of the data */
1272 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1273
1274 if (res != -EIO) {
1275 /* send high 16 bits of the data */
1276 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1277 data >> 16);
1278 }
1279
5aaca44d
IM		 1280 /*If no error encountered, automatically increment the address
1281 as per chip behaviour*/
1282 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1283 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1284 return res;
1285}
1286
d5c21b88
IM		 1287/*
1288 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1289 */
01ef7dbf
IM		 1290static int chipio_write_data_multiple(struct hda_codec *codec,
1291 const u32 *data,
1292 unsigned int count)
1293{
1294 int status = 0;
1295
1296 if (data == NULL) {
4e76a883 1297 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1298 return -EINVAL;
1299 }
1300
1301 while ((count-- != 0) && (status == 0))
1302 status = chipio_write_data(codec, *data++);
1303
1304 return status;
1305}
1306
1307
1308/*
1309 * Read data through the vendor widget -- NOT protected by the Mutex!
1310 */
1311static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1312{
5aaca44d 1313 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1314 int res;
1315
1316 /* post read */
1317 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1318
1319 if (res != -EIO) {
1320 /* read status */
1321 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1322 }
1323
1324 if (res != -EIO) {
1325 /* read data */
1326 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1327 VENDOR_CHIPIO_HIC_READ_DATA,
1328 0);
1329 }
1330
5aaca44d
IM		 1331 /*If no error encountered, automatically increment the address
1332 as per chip behaviour*/
1333 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1334 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1335 return res;
1336}
1337
1338/*
1339 * Write given value to the given address through the chip I/O widget.
1340 * protected by the Mutex
1341 */
1342static int chipio_write(struct hda_codec *codec,
1343 unsigned int chip_addx, const unsigned int data)
1344{
1345 struct ca0132_spec *spec = codec->spec;
1346 int err;
1347
1348 mutex_lock(&spec->chipio_mutex);
1349
1350 /* write the address, and if successful proceed to write data */
1351 err = chipio_write_address(codec, chip_addx);
1352 if (err < 0)
1353 goto exit;
1354
1355 err = chipio_write_data(codec, data);
1356 if (err < 0)
1357 goto exit;
1358
1359exit:
1360 mutex_unlock(&spec->chipio_mutex);
1361 return err;
1362}
1363
38ba69ff
CM		 1364/*
1365 * Write given value to the given address through the chip I/O widget.
1366 * not protected by the Mutex
1367 */
1368static int chipio_write_no_mutex(struct hda_codec *codec,
1369 unsigned int chip_addx, const unsigned int data)
1370{
1371 int err;
1372
1373
1374 /* write the address, and if successful proceed to write data */
1375 err = chipio_write_address(codec, chip_addx);
1376 if (err < 0)
1377 goto exit;
1378
1379 err = chipio_write_data(codec, data);
1380 if (err < 0)
1381 goto exit;
1382
1383exit:
1384 return err;
1385}
1386
d5c21b88
IM		 1387/*
1388 * Write multiple values to the given address through the chip I/O widget.
1389 * protected by the Mutex
1390 */
01ef7dbf
IM		 1391static int chipio_write_multiple(struct hda_codec *codec,
1392 u32 chip_addx,
1393 const u32 *data,
1394 unsigned int count)
1395{
1396 struct ca0132_spec *spec = codec->spec;
1397 int status;
1398
1399 mutex_lock(&spec->chipio_mutex);
4861af80 1400 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1401 if (status < 0)
1402 goto error;
1403
1404 status = chipio_write_data_multiple(codec, data, count);
1405error:
1406 mutex_unlock(&spec->chipio_mutex);
1407
1408 return status;
1409}
1410
1411/*
1412 * Read the given address through the chip I/O widget
1413 * protected by the Mutex
1414 */
1415static int chipio_read(struct hda_codec *codec,
1416 unsigned int chip_addx, unsigned int *data)
1417{
1418 struct ca0132_spec *spec = codec->spec;
1419 int err;
1420
1421 mutex_lock(&spec->chipio_mutex);
1422
1423 /* write the address, and if successful proceed to write data */
1424 err = chipio_write_address(codec, chip_addx);
1425 if (err < 0)
1426 goto exit;
1427
1428 err = chipio_read_data(codec, data);
1429 if (err < 0)
1430 goto exit;
1431
1432exit:
1433 mutex_unlock(&spec->chipio_mutex);
1434 return err;
1435}
1436
d5c21b88
IM		 1437/*
1438 * Set chip control flags through the chip I/O widget.
1439 */
01ef7dbf
IM		 1440static void chipio_set_control_flag(struct hda_codec *codec,
1441 enum control_flag_id flag_id,
1442 bool flag_state)
1443{
1444 unsigned int val;
1445 unsigned int flag_bit;
1446
1447 flag_bit = (flag_state ? 1 : 0);
1448 val = (flag_bit << 7) | (flag_id);
1449 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1450 VENDOR_CHIPIO_FLAG_SET, val);
1451}
1452
d5c21b88
IM		 1453/*
1454 * Set chip parameters through the chip I/O widget.
1455 */
01ef7dbf
IM		 1456static void chipio_set_control_param(struct hda_codec *codec,
1457 enum control_param_id param_id, int param_val)
1458{
1459 struct ca0132_spec *spec = codec->spec;
1460 int val;
1461
1462 if ((param_id < 32) && (param_val < 8)) {
1463 val = (param_val << 5) | (param_id);
1464 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1465 VENDOR_CHIPIO_PARAM_SET, val);
1466 } else {
1467 mutex_lock(&spec->chipio_mutex);
1468 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1469 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1470 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1471 param_id);
1472 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1473 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1474 param_val);
1475 }
1476 mutex_unlock(&spec->chipio_mutex);
1477 }
1478}
1479
009b8f97
CM		 1480/*
1481 * Set chip parameters through the chip I/O widget. NO MUTEX.
1482 */
1483static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1484 enum control_param_id param_id, int param_val)
1485{
1486 int val;
1487
1488 if ((param_id < 32) && (param_val < 8)) {
1489 val = (param_val << 5) | (param_id);
1490 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1491 VENDOR_CHIPIO_PARAM_SET, val);
1492 } else {
1493 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1494 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1495 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1496 param_id);
1497 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1498 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1499 param_val);
1500 }
1501 }
1502}
38ba69ff
CM		 1503/*
1504 * Connect stream to a source point, and then connect
1505 * that source point to a destination point.
1506 */
1507static void chipio_set_stream_source_dest(struct hda_codec *codec,
1508 int streamid, int source_point, int dest_point)
1509{
1510 chipio_set_control_param_no_mutex(codec,
1511 CONTROL_PARAM_STREAM_ID, streamid);
1512 chipio_set_control_param_no_mutex(codec,
1513 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1514 chipio_set_control_param_no_mutex(codec,
1515 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1516}
1517
1518/*
1519 * Set number of channels in the selected stream.
1520 */
1521static void chipio_set_stream_channels(struct hda_codec *codec,
1522 int streamid, unsigned int channels)
1523{
1524 chipio_set_control_param_no_mutex(codec,
1525 CONTROL_PARAM_STREAM_ID, streamid);
1526 chipio_set_control_param_no_mutex(codec,
1527 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1528}
009b8f97
CM		 1529
1530/*
1531 * Enable/Disable audio stream.
1532 */
1533static void chipio_set_stream_control(struct hda_codec *codec,
1534 int streamid, int enable)
1535{
1536 chipio_set_control_param_no_mutex(codec,
1537 CONTROL_PARAM_STREAM_ID, streamid);
1538 chipio_set_control_param_no_mutex(codec,
1539 CONTROL_PARAM_STREAM_CONTROL, enable);
1540}
1541
38ba69ff
CM		 1542
1543/*
1544 * Set sampling rate of the connection point. NO MUTEX.
1545 */
1546static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1547 int connid, enum ca0132_sample_rate rate)
1548{
1549 chipio_set_control_param_no_mutex(codec,
1550 CONTROL_PARAM_CONN_POINT_ID, connid);
1551 chipio_set_control_param_no_mutex(codec,
1552 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1553}
1554
d5c21b88
IM		 1555/*
1556 * Set sampling rate of the connection point.
1557 */
01ef7dbf
IM		 1558static void chipio_set_conn_rate(struct hda_codec *codec,
1559 int connid, enum ca0132_sample_rate rate)
1560{
1561 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1562 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1563 rate);
1564}
1565
b9b41345
CM		 1566/*
1567 * Writes to the 8051's internal address space directly instead of indirectly,
1568 * giving access to the special function registers located at addresses
1569 * 0x80-0xFF.
1570 */
1571static void chipio_8051_write_direct(struct hda_codec *codec,
1572 unsigned int addr, unsigned int data)
1573{
1574 unsigned int verb;
1575
1576 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1577 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1578}
1579
d5c21b88
IM		 1580/*
1581 * Enable clocks.
1582 */
01ef7dbf
IM		 1583static void chipio_enable_clocks(struct hda_codec *codec)
1584{
1585 struct ca0132_spec *spec = codec->spec;
1586
1587 mutex_lock(&spec->chipio_mutex);
1588 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1589 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1590 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1591 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1592 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1593 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1594 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1595 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1596 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1597 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1598 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1599 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1600 mutex_unlock(&spec->chipio_mutex);
1601}
1602
1603/*
1604 * CA0132 DSP IO stuffs
1605 */
1606static int dspio_send(struct hda_codec *codec, unsigned int reg,
1607 unsigned int data)
1608{
b645d796 1609 int res;
6d67530e 1610 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1611
1612 /* send bits of data specified by reg to dsp */
1613 do {
1614 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1615 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1616 return res;
6d67530e
IM		 1617 msleep(20);
1618 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1619
1620 return -EIO;
1621}
1622
d5c21b88
IM		 1623/*
1624 * Wait for DSP to be ready for commands
1625 */
01ef7dbf
IM		 1626static void dspio_write_wait(struct hda_codec *codec)
1627{
4861af80
IM		 1628 int status;
1629 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1630
01ef7dbf 1631 do {
4861af80
IM		 1632 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1633 VENDOR_DSPIO_STATUS, 0);
1634 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1635 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1636 break;
1637 msleep(1);
1638 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1639}
1640
d5c21b88
IM		 1641/*
1642 * Write SCP data to DSP
1643 */
01ef7dbf
IM		 1644static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1645{
1646 struct ca0132_spec *spec = codec->spec;
1647 int status;
1648
1649 dspio_write_wait(codec);
1650
1651 mutex_lock(&spec->chipio_mutex);
1652 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1653 scp_data & 0xffff);
1654 if (status < 0)
1655 goto error;
1656
1657 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1658 scp_data >> 16);
1659 if (status < 0)
1660 goto error;
1661
1662 /* OK, now check if the write itself has executed*/
1663 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1664 VENDOR_DSPIO_STATUS, 0);
1665error:
1666 mutex_unlock(&spec->chipio_mutex);
1667
1668 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1669 -EIO : 0;
1670}
1671
d5c21b88
IM		 1672/*
1673 * Write multiple SCP data to DSP
1674 */
01ef7dbf
IM		 1675static int dspio_write_multiple(struct hda_codec *codec,
1676 unsigned int *buffer, unsigned int size)
1677{
1678 int status = 0;
1679 unsigned int count;
1680
a16fbb85 1681 if (buffer == NULL)
01ef7dbf
IM		 1682 return -EINVAL;
1683
1684 count = 0;
1685 while (count < size) {
1686 status = dspio_write(codec, *buffer++);
1687 if (status != 0)
1688 break;
1689 count++;
1690 }
1691
1692 return status;
1693}
1694
a73d511c
IM		 1695static int dspio_read(struct hda_codec *codec, unsigned int *data)
1696{
1697 int status;
1698
1699 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1700 if (status == -EIO)
1701 return status;
1702
1703 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1704 if (status == -EIO ||
1705 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1706 return -EIO;
1707
1708 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1709 VENDOR_DSPIO_SCP_READ_DATA, 0);
1710
1711 return 0;
1712}
1713
1714static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1715 unsigned int *buf_size, unsigned int size_count)
1716{
1717 int status = 0;
1718 unsigned int size = *buf_size;
1719 unsigned int count;
1720 unsigned int skip_count;
1721 unsigned int dummy;
1722
a16fbb85 1723 if (buffer == NULL)
a73d511c
IM		 1724 return -1;
1725
1726 count = 0;
1727 while (count < size && count < size_count) {
1728 status = dspio_read(codec, buffer++);
1729 if (status != 0)
1730 break;
1731 count++;
1732 }
1733
1734 skip_count = count;
1735 if (status == 0) {
1736 while (skip_count < size) {
1737 status = dspio_read(codec, &dummy);
1738 if (status != 0)
1739 break;
1740 skip_count++;
1741 }
1742 }
1743 *buf_size = count;
1744
1745 return status;
1746}
1747
d5c21b88
IM		 1748/*
1749 * Construct the SCP header using corresponding fields
1750 */
01ef7dbf
IM		 1751static inline unsigned int
1752make_scp_header(unsigned int target_id, unsigned int source_id,
1753 unsigned int get_flag, unsigned int req,
1754 unsigned int device_flag, unsigned int resp_flag,
1755 unsigned int error_flag, unsigned int data_size)
1756{
1757 unsigned int header = 0;
1758
1759 header = (data_size & 0x1f) << 27;
1760 header |= (error_flag & 0x01) << 26;
1761 header |= (resp_flag & 0x01) << 25;
1762 header |= (device_flag & 0x01) << 24;
1763 header |= (req & 0x7f) << 17;
1764 header |= (get_flag & 0x01) << 16;
1765 header |= (source_id & 0xff) << 8;
1766 header |= target_id & 0xff;
1767
1768 return header;
1769}
1770
d5c21b88
IM		 1771/*
1772 * Extract corresponding fields from SCP header
1773 */
01ef7dbf
IM		 1774static inline void
1775extract_scp_header(unsigned int header,
1776 unsigned int *target_id, unsigned int *source_id,
1777 unsigned int *get_flag, unsigned int *req,
1778 unsigned int *device_flag, unsigned int *resp_flag,
1779 unsigned int *error_flag, unsigned int *data_size)
1780{
1781 if (data_size)
1782 *data_size = (header >> 27) & 0x1f;
1783 if (error_flag)
1784 *error_flag = (header >> 26) & 0x01;
1785 if (resp_flag)
1786 *resp_flag = (header >> 25) & 0x01;
1787 if (device_flag)
1788 *device_flag = (header >> 24) & 0x01;
1789 if (req)
1790 *req = (header >> 17) & 0x7f;
1791 if (get_flag)
1792 *get_flag = (header >> 16) & 0x01;
1793 if (source_id)
1794 *source_id = (header >> 8) & 0xff;
1795 if (target_id)
1796 *target_id = header & 0xff;
1797}
1798
1799#define SCP_MAX_DATA_WORDS (16)
1800
1801/* Structure to contain any SCP message */
1802struct scp_msg {
1803 unsigned int hdr;
1804 unsigned int data[SCP_MAX_DATA_WORDS];
1805};
1806
a73d511c
IM		 1807static void dspio_clear_response_queue(struct hda_codec *codec)
1808{
1809 unsigned int dummy = 0;
1810 int status = -1;
1811
1812 /* clear all from the response queue */
1813 do {
1814 status = dspio_read(codec, &dummy);
1815 } while (status == 0);
1816}
1817
1818static int dspio_get_response_data(struct hda_codec *codec)
1819{
1820 struct ca0132_spec *spec = codec->spec;
1821 unsigned int data = 0;
1822 unsigned int count;
1823
1824 if (dspio_read(codec, &data) < 0)
1825 return -EIO;
1826
1827 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1828 spec->scp_resp_header = data;
1829 spec->scp_resp_count = data >> 27;
1830 count = spec->wait_num_data;
1831 dspio_read_multiple(codec, spec->scp_resp_data,
1832 &spec->scp_resp_count, count);
1833 return 0;
1834 }
1835
1836 return -EIO;
1837}
1838
d5c21b88
IM		 1839/*
1840 * Send SCP message to DSP
1841 */
01ef7dbf
IM		 1842static int dspio_send_scp_message(struct hda_codec *codec,
1843 unsigned char *send_buf,
1844 unsigned int send_buf_size,
1845 unsigned char *return_buf,
1846 unsigned int return_buf_size,
1847 unsigned int *bytes_returned)
1848{
1849 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1850 int status = -1;
1851 unsigned int scp_send_size = 0;
1852 unsigned int total_size;
1853 bool waiting_for_resp = false;
1854 unsigned int header;
1855 struct scp_msg *ret_msg;
1856 unsigned int resp_src_id, resp_target_id;
1857 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1858
1859 if (bytes_returned)
1860 *bytes_returned = 0;
1861
1862 /* get scp header from buffer */
1863 header = *((unsigned int *)send_buf);
1864 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1865 &device_flag, NULL, NULL, &data_size);
1866 scp_send_size = data_size + 1;
1867 total_size = (scp_send_size * 4);
1868
1869 if (send_buf_size < total_size)
1870 return -EINVAL;
1871
1872 if (get_flag || device_flag) {
1873 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1874 return -EINVAL;
1875
1876 spec->wait_scp_header = *((unsigned int *)send_buf);
1877
1878 /* swap source id with target id */
1879 resp_target_id = src_id;
1880 resp_src_id = target_id;
1881 spec->wait_scp_header &= 0xffff0000;
1882 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1883 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1884 spec->wait_scp = 1;
1885 waiting_for_resp = true;
1886 }
1887
1888 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1889 scp_send_size);
1890 if (status < 0) {
1891 spec->wait_scp = 0;
1892 return status;
1893 }
1894
1895 if (waiting_for_resp) {
6d67530e 1896 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1897 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1898 do {
1899 msleep(20);
6d67530e 1900 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1901 waiting_for_resp = false;
6d67530e 1902 if (!spec->wait_scp) {
01ef7dbf
IM		 1903 ret_msg = (struct scp_msg *)return_buf;
1904 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1905 memcpy(&ret_msg->data, spec->scp_resp_data,
1906 spec->wait_num_data);
1907 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1908 status = 0;
1909 } else {
1910 status = -EIO;
1911 }
1912 spec->wait_scp = 0;
1913 }
1914
1915 return status;
1916}
1917
d5c21b88
IM		 1918/**
1919 * Prepare and send the SCP message to DSP
1920 * @codec: the HDA codec
1921 * @mod_id: ID of the DSP module to send the command
1922 * @req: ID of request to send to the DSP module
1923 * @dir: SET or GET
1924 * @data: pointer to the data to send with the request, request specific
1925 * @len: length of the data, in bytes
1926 * @reply: point to the buffer to hold data returned for a reply
1927 * @reply_len: length of the reply buffer returned from GET
1928 *
1929 * Returns zero or a negative error code.
1930 */
01ef7dbf 1931static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1932 int mod_id, int src_id, int req, int dir, const void *data,
1933 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1934{
1935 int status = 0;
1936 struct scp_msg scp_send, scp_reply;
1937 unsigned int ret_bytes, send_size, ret_size;
1938 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1939 unsigned int reply_data_size;
1940
1941 memset(&scp_send, 0, sizeof(scp_send));
1942 memset(&scp_reply, 0, sizeof(scp_reply));
1943
1944 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1945 return -EINVAL;
1946
1947 if (dir == SCP_GET && reply == NULL) {
4e76a883 1948 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1949 return -EINVAL;
1950 }
1951
1952 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1953 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1954 return -EINVAL;
1955 }
1956
447fd8e9 1957 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1958 0, 0, 0, len/sizeof(unsigned int));
1959 if (data != NULL && len > 0) {
1960 len = min((unsigned int)(sizeof(scp_send.data)), len);
1961 memcpy(scp_send.data, data, len);
1962 }
1963
1964 ret_bytes = 0;
1965 send_size = sizeof(unsigned int) + len;
1966 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1967 send_size, (unsigned char *)&scp_reply,
1968 sizeof(scp_reply), &ret_bytes);
1969
1970 if (status < 0) {
4e76a883 1971 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1972 return status;
1973 }
1974
1975 /* extract send and reply headers members */
1976 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1977 NULL, NULL, NULL, NULL, NULL);
1978 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1979 &reply_resp_flag, &reply_error_flag,
1980 &reply_data_size);
1981
1982 if (!send_get_flag)
1983 return 0;
1984
1985 if (reply_resp_flag && !reply_error_flag) {
1986 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1987 / sizeof(unsigned int);
1988
1989 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1990 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1991 return -EINVAL;
1992 } else if (ret_size != reply_data_size) {
4e76a883 1993 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1994 return -EINVAL;
46a049da
AB		 1995 } else if (!reply) {
1996 codec_dbg(codec, "NULL reply\n");
1997 return -EINVAL;
01ef7dbf
IM		 1998 } else {
1999 *reply_len = ret_size*sizeof(unsigned int);
2000 memcpy(reply, scp_reply.data, *reply_len);
2001 }
2002 } else {
4e76a883 2003 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 2004 return -EIO;
2005 }
2006
2007 return status;
2008}
2009
5aaca44d
IM		 2010/*
2011 * Set DSP parameters
2012 */
2013static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 2014 int src_id, int req, const void *data, unsigned int len)
5aaca44d 2015{
447fd8e9
CM		 2016 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2017 NULL);
5aaca44d
IM		 2018}
2019
2020static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 2021 int req, const unsigned int data)
5aaca44d 2022{
447fd8e9
CM		 2023 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2024 sizeof(unsigned int));
2025}
2026
2027static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2028 int req, const unsigned int data)
2029{
2030 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2031 sizeof(unsigned int));
5aaca44d
IM		 2032}
2033
d5c21b88
IM		 2034/*
2035 * Allocate a DSP DMA channel via an SCP message
2036 */
01ef7dbf
IM		 2037static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2038{
2039 int status = 0;
2040 unsigned int size = sizeof(dma_chan);
2041
4e76a883 2042 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 2043 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2044 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2045 dma_chan, &size);
01ef7dbf
IM		 2046
2047 if (status < 0) {
4e76a883 2048 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2049 return status;
2050 }
2051
2052 if ((*dma_chan + 1) == 0) {
4e76a883 2053 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 2054 return -EBUSY;
2055 }
2056
4e76a883
TI		 2057 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2058 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 2059
2060 return status;
2061}
2062
d5c21b88
IM		 2063/*
2064 * Free a DSP DMA via an SCP message
2065 */
01ef7dbf
IM		 2066static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2067{
2068 int status = 0;
2069 unsigned int dummy = 0;
2070
4e76a883
TI		 2071 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2072 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 2073
447fd8e9
CM		 2074 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2075 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2076 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 2077
2078 if (status < 0) {
4e76a883 2079 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2080 return status;
2081 }
2082
4e76a883 2083 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 2084
2085 return status;
2086}
2087
2088/*
d5c21b88 2089 * (Re)start the DSP
01ef7dbf
IM		 2090 */
2091static int dsp_set_run_state(struct hda_codec *codec)
2092{
2093 unsigned int dbg_ctrl_reg;
2094 unsigned int halt_state;
2095 int err;
2096
2097 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2098 if (err < 0)
2099 return err;
2100
2101 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2102 DSP_DBGCNTL_STATE_LOBIT;
2103
2104 if (halt_state != 0) {
2105 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2106 DSP_DBGCNTL_SS_MASK);
2107 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2108 dbg_ctrl_reg);
2109 if (err < 0)
2110 return err;
2111
2112 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2113 DSP_DBGCNTL_EXEC_MASK;
2114 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2115 dbg_ctrl_reg);
2116 if (err < 0)
2117 return err;
2118 }
2119
2120 return 0;
2121}
2122
d5c21b88
IM		 2123/*
2124 * Reset the DSP
2125 */
01ef7dbf
IM		 2126static int dsp_reset(struct hda_codec *codec)
2127{
2128 unsigned int res;
2129 int retry = 20;
2130
4e76a883 2131 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 2132 do {
2133 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2134 retry--;
2135 } while (res == -EIO && retry);
2136
2137 if (!retry) {
4e76a883 2138 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 2139 return -EIO;
2140 }
2141
2142 return 0;
2143}
2144
d5c21b88
IM		 2145/*
2146 * Convert chip address to DSP address
2147 */
01ef7dbf
IM		 2148static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2149 bool *code, bool *yram)
2150{
2151 *code = *yram = false;
2152
2153 if (UC_RANGE(chip_addx, 1)) {
2154 *code = true;
2155 return UC_OFF(chip_addx);
2156 } else if (X_RANGE_ALL(chip_addx, 1)) {
2157 return X_OFF(chip_addx);
2158 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2159 *yram = true;
2160 return Y_OFF(chip_addx);
2161 }
2162
4a8b89f9 2163 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2164}
2165
d5c21b88
IM		 2166/*
2167 * Check if the DSP DMA is active
2168 */
01ef7dbf
IM		 2169static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2170{
2171 unsigned int dma_chnlstart_reg;
2172
2173 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2174
2175 return ((dma_chnlstart_reg & (1 <<
2176 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2177}
2178
2179static int dsp_dma_setup_common(struct hda_codec *codec,
2180 unsigned int chip_addx,
2181 unsigned int dma_chan,
2182 unsigned int port_map_mask,
2183 bool ovly)
2184{
2185 int status = 0;
2186 unsigned int chnl_prop;
2187 unsigned int dsp_addx;
2188 unsigned int active;
2189 bool code, yram;
2190
4e76a883 2191 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2192
2193 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2194 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2195 return -EINVAL;
2196 }
2197
2198 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2199 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2200 return -EBUSY;
2201 }
2202
2203 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2204
2205 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2206 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2207 return -ENXIO;
2208 }
2209
2210 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2211 active = 0;
2212
4e76a883 2213 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2214
2215 if (ovly) {
2216 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2217 &chnl_prop);
2218
2219 if (status < 0) {
4e76a883 2220 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2221 return status;
2222 }
4e76a883 2223 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2224 }
2225
2226 if (!code)
2227 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2228 else
2229 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2230
2231 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2232
2233 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2234 if (status < 0) {
4e76a883 2235 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2236 return status;
2237 }
4e76a883 2238 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2239
2240 if (ovly) {
2241 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2242 &active);
2243
2244 if (status < 0) {
4e76a883 2245 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2246 return status;
2247 }
4e76a883 2248 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2249 }
2250
2251 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2252 DSPDMAC_ACTIVE_AAR_MASK;
2253
2254 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2255 if (status < 0) {
4e76a883 2256 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2257 return status;
2258 }
2259
4e76a883 2260 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2261
2262 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2263 port_map_mask);
2264 if (status < 0) {
4e76a883 2265 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2266 return status;
2267 }
4e76a883 2268 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2269
2270 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2271 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2272 if (status < 0) {
4e76a883 2273 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2274 return status;
2275 }
4e76a883 2276 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2277
4e76a883 2278 codec_dbg(codec,
01ef7dbf
IM		 2279 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2280 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2281 chip_addx, dsp_addx, dma_chan,
2282 port_map_mask, chnl_prop, active);
2283
4e76a883 2284 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2285
2286 return 0;
2287}
2288
d5c21b88
IM		 2289/*
2290 * Setup the DSP DMA per-transfer-specific registers
2291 */
01ef7dbf
IM		 2292static int dsp_dma_setup(struct hda_codec *codec,
2293 unsigned int chip_addx,
2294 unsigned int count,
2295 unsigned int dma_chan)
2296{
2297 int status = 0;
2298 bool code, yram;
2299 unsigned int dsp_addx;
2300 unsigned int addr_field;
2301 unsigned int incr_field;
2302 unsigned int base_cnt;
2303 unsigned int cur_cnt;
2304 unsigned int dma_cfg = 0;
2305 unsigned int adr_ofs = 0;
2306 unsigned int xfr_cnt = 0;
2307 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2308 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2309
4e76a883 2310 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2311
2312 if (count > max_dma_count) {
4e76a883 2313 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2314 return -EINVAL;
2315 }
2316
2317 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2318 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2319 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2320 return -ENXIO;
2321 }
2322
4e76a883 2323 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2324
2325 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2326 incr_field = 0;
2327
2328 if (!code) {
2329 addr_field <<= 1;
2330 if (yram)
2331 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2332
2333 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2334 }
2335
2336 dma_cfg = addr_field + incr_field;
2337 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2338 dma_cfg);
2339 if (status < 0) {
4e76a883 2340 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2341 return status;
2342 }
4e76a883 2343 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2344
2345 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2346 (code ? 0 : 1));
2347
2348 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2349 adr_ofs);
2350 if (status < 0) {
4e76a883 2351 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2352 return status;
2353 }
4e76a883 2354 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2355
2356 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2357
2358 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2359
2360 xfr_cnt = base_cnt | cur_cnt;
2361
2362 status = chipio_write(codec,
2363 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2364 if (status < 0) {
4e76a883 2365 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2366 return status;
2367 }
4e76a883 2368 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2369
4e76a883 2370 codec_dbg(codec,
01ef7dbf
IM		 2371 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2372 "ADROFS=0x%x, XFRCNT=0x%x\n",
2373 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2374
4e76a883 2375 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2376
2377 return 0;
2378}
2379
d5c21b88
IM		 2380/*
2381 * Start the DSP DMA
2382 */
01ef7dbf
IM		 2383static int dsp_dma_start(struct hda_codec *codec,
2384 unsigned int dma_chan, bool ovly)
2385{
2386 unsigned int reg = 0;
2387 int status = 0;
2388
4e76a883 2389 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2390
2391 if (ovly) {
2392 status = chipio_read(codec,
2393 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2394
2395 if (status < 0) {
4e76a883 2396 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2397 return status;
2398 }
4e76a883 2399 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2400
2401 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2402 DSPDMAC_CHNLSTART_DIS_MASK);
2403 }
2404
2405 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2406 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2407 if (status < 0) {
4e76a883 2408 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2409 return status;
2410 }
4e76a883 2411 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2412
2413 return status;
2414}
2415
d5c21b88
IM		 2416/*
2417 * Stop the DSP DMA
2418 */
01ef7dbf
IM		 2419static int dsp_dma_stop(struct hda_codec *codec,
2420 unsigned int dma_chan, bool ovly)
2421{
2422 unsigned int reg = 0;
2423 int status = 0;
2424
4e76a883 2425 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2426
2427 if (ovly) {
2428 status = chipio_read(codec,
2429 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2430
2431 if (status < 0) {
4e76a883 2432 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2433 return status;
2434 }
4e76a883 2435 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2436 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2437 DSPDMAC_CHNLSTART_DIS_MASK);
2438 }
2439
2440 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2441 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2442 if (status < 0) {
4e76a883 2443 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2444 return status;
2445 }
4e76a883 2446 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2447
2448 return status;
2449}
2450
d5c21b88
IM		 2451/**
2452 * Allocate router ports
2453 *
2454 * @codec: the HDA codec
2455 * @num_chans: number of channels in the stream
2456 * @ports_per_channel: number of ports per channel
2457 * @start_device: start device
2458 * @port_map: pointer to the port list to hold the allocated ports
2459 *
2460 * Returns zero or a negative error code.
2461 */
01ef7dbf
IM		 2462static int dsp_allocate_router_ports(struct hda_codec *codec,
2463 unsigned int num_chans,
2464 unsigned int ports_per_channel,
2465 unsigned int start_device,
2466 unsigned int *port_map)
2467{
2468 int status = 0;
2469 int res;
2470 u8 val;
2471
2472 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2473 if (status < 0)
2474 return status;
2475
2476 val = start_device << 6;
2477 val |= (ports_per_channel - 1) << 4;
2478 val |= num_chans - 1;
2479
2480 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2481 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2482 val);
2483
2484 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2485 VENDOR_CHIPIO_PORT_ALLOC_SET,
2486 MEM_CONNID_DSP);
2487
2488 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2489 if (status < 0)
2490 return status;
2491
2492 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2493 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2494
2495 *port_map = res;
2496
2497 return (res < 0) ? res : 0;
2498}
2499
d5c21b88
IM		 2500/*
2501 * Free router ports
2502 */
01ef7dbf
IM		 2503static int dsp_free_router_ports(struct hda_codec *codec)
2504{
2505 int status = 0;
2506
2507 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2508 if (status < 0)
2509 return status;
2510
2511 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2512 VENDOR_CHIPIO_PORT_FREE_SET,
2513 MEM_CONNID_DSP);
2514
2515 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2516
2517 return status;
2518}
2519
d5c21b88
IM		 2520/*
2521 * Allocate DSP ports for the download stream
2522 */
01ef7dbf
IM		 2523static int dsp_allocate_ports(struct hda_codec *codec,
2524 unsigned int num_chans,
2525 unsigned int rate_multi, unsigned int *port_map)
2526{
2527 int status;
2528
4e76a883 2529 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2530
2531 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2532 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2533 return -EINVAL;
2534 }
2535
2536 status = dsp_allocate_router_ports(codec, num_chans,
2537 rate_multi, 0, port_map);
2538
4e76a883 2539 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2540
2541 return status;
2542}
2543
01ef7dbf
IM		 2544static int dsp_allocate_ports_format(struct hda_codec *codec,
2545 const unsigned short fmt,
2546 unsigned int *port_map)
2547{
2548 int status;
2549 unsigned int num_chans;
2550
2551 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2552 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2553 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2554
2555 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2556 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2557 return -EINVAL;
2558 }
2559
2560 num_chans = get_hdafmt_chs(fmt) + 1;
2561
2562 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2563
2564 return status;
2565}
2566
d5c21b88
IM		 2567/*
2568 * free DSP ports
2569 */
2570static int dsp_free_ports(struct hda_codec *codec)
2571{
2572 int status;
2573
4e76a883 2574 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2575
2576 status = dsp_free_router_ports(codec);
2577 if (status < 0) {
4e76a883 2578 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2579 return status;
2580 }
4e76a883 2581 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2582
2583 return status;
2584}
2585
01ef7dbf
IM		 2586/*
2587 * HDA DMA engine stuffs for DSP code download
2588 */
2589struct dma_engine {
2590 struct hda_codec *codec;
2591 unsigned short m_converter_format;
2592 struct snd_dma_buffer *dmab;
2593 unsigned int buf_size;
2594};
2595
2596
2597enum dma_state {
2598 DMA_STATE_STOP = 0,
2599 DMA_STATE_RUN = 1
2600};
2601
6194b99d 2602static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2603 unsigned int sample_rate,
2604 unsigned short channels,
01ef7dbf
IM		 2605 unsigned short *hda_format)
2606{
2607 unsigned int format_val;
2608
b7d023e1
TI		 2609 format_val = snd_hdac_calc_stream_format(sample_rate,
2610 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2611
2612 if (hda_format)
2613 *hda_format = (unsigned short)format_val;
2614
2615 return 0;
2616}
2617
d5c21b88
IM		 2618/*
2619 * Reset DMA for DSP download
2620 */
01ef7dbf
IM		 2621static int dma_reset(struct dma_engine *dma)
2622{
2623 struct hda_codec *codec = dma->codec;
2624 struct ca0132_spec *spec = codec->spec;
2625 int status;
2626
b3667bd7 2627 if (dma->dmab->area)
01ef7dbf
IM		 2628 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2629
2630 status = snd_hda_codec_load_dsp_prepare(codec,
2631 dma->m_converter_format,
2632 dma->buf_size,
2633 dma->dmab);
2634 if (status < 0)
2635 return status;
2636 spec->dsp_stream_id = status;
2637 return 0;
2638}
2639
2640static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2641{
01ef7dbf
IM		 2642 bool cmd;
2643
01ef7dbf
IM		 2644 switch (state) {
2645 case DMA_STATE_STOP:
2646 cmd = false;
2647 break;
2648 case DMA_STATE_RUN:
2649 cmd = true;
2650 break;
2651 default:
c41999a2
DH		 2652 return 0;
2653 }
01ef7dbf
IM		 2654
2655 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2656 return 0;
95c6e9cb
IM		 2657}
2658
01ef7dbf
IM		 2659static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2660{
2661 return dma->dmab->bytes;
2662}
95c6e9cb 2663
01ef7dbf
IM		 2664static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2665{
2666 return dma->dmab->area;
2667}
95c6e9cb 2668
01ef7dbf
IM		 2669static int dma_xfer(struct dma_engine *dma,
2670 const unsigned int *data,
2671 unsigned int count)
2672{
2673 memcpy(dma->dmab->area, data, count);
2674 return 0;
2675}
95c6e9cb 2676
01ef7dbf
IM		 2677static void dma_get_converter_format(
2678 struct dma_engine *dma,
2679 unsigned short *format)
2680{
2681 if (format)
2682 *format = dma->m_converter_format;
2683}
95c6e9cb 2684
01ef7dbf 2685static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2686{
01ef7dbf 2687 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2688
01ef7dbf 2689 return spec->dsp_stream_id;
95c6e9cb
IM		 2690}
2691
01ef7dbf
IM		 2692struct dsp_image_seg {
2693 u32 magic;
2694 u32 chip_addr;
2695 u32 count;
2696 u32 data[0];
2697};
2698
2699static const u32 g_magic_value = 0x4c46584d;
2700static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2701
2702static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2703{
01ef7dbf
IM		 2704 return p->magic == g_magic_value;
2705}
95c6e9cb 2706
01ef7dbf
IM		 2707static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2708{
2709 return g_chip_addr_magic_value == p->chip_addr;
2710}
95c6e9cb 2711
01ef7dbf
IM		 2712static bool is_last(const struct dsp_image_seg *p)
2713{
2714 return p->count == 0;
2715}
95c6e9cb 2716
01ef7dbf
IM		 2717static size_t dsp_sizeof(const struct dsp_image_seg *p)
2718{
2719 return sizeof(*p) + p->count*sizeof(u32);
2720}
2721
2722static const struct dsp_image_seg *get_next_seg_ptr(
2723 const struct dsp_image_seg *p)
2724{
2725 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2726}
2727
2728/*
01ef7dbf 2729 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2730 */
8ae3124b 2731#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2732
d5c21b88
IM		 2733/*
2734 * Program a list of address/data pairs via the ChipIO widget.
2735 * The segment data is in the format of successive pairs of words.
2736 * These are repeated as indicated by the segment's count field.
2737 */
01ef7dbf
IM		 2738static int dspxfr_hci_write(struct hda_codec *codec,
2739 const struct dsp_image_seg *fls)
95c6e9cb 2740{
01ef7dbf
IM		 2741 int status;
2742 const u32 *data;
2743 unsigned int count;
95c6e9cb 2744
01ef7dbf 2745 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2746 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2747 return -EINVAL;
95c6e9cb
IM		 2748 }
2749
01ef7dbf
IM		 2750 count = fls->count;
2751 data = (u32 *)(fls->data);
2752 while (count >= 2) {
2753 status = chipio_write(codec, data[0], data[1]);
2754 if (status < 0) {
4e76a883 2755 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2756 return status;
2757 }
2758 count -= 2;
2759 data += 2;
2760 }
2761 return 0;
95c6e9cb
IM		 2762}
2763
d5c21b88
IM		 2764/**
2765 * Write a block of data into DSP code or data RAM using pre-allocated
2766 * DMA engine.
2767 *
2768 * @codec: the HDA codec
2769 * @fls: pointer to a fast load image
2770 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2771 * no relocation
2772 * @dma_engine: pointer to DMA engine to be used for DSP download
2773 * @dma_chan: The number of DMA channels used for DSP download
2774 * @port_map_mask: port mapping
2775 * @ovly: TRUE if overlay format is required
2776 *
2777 * Returns zero or a negative error code.
2778 */
01ef7dbf
IM		 2779static int dspxfr_one_seg(struct hda_codec *codec,
2780 const struct dsp_image_seg *fls,
2781 unsigned int reloc,
2782 struct dma_engine *dma_engine,
2783 unsigned int dma_chan,
2784 unsigned int port_map_mask,
2785 bool ovly)
95c6e9cb 2786{
406261ce 2787 int status = 0;
01ef7dbf
IM		 2788 bool comm_dma_setup_done = false;
2789 const unsigned int *data;
2790 unsigned int chip_addx;
2791 unsigned int words_to_write;
2792 unsigned int buffer_size_words;
2793 unsigned char *buffer_addx;
2794 unsigned short hda_format;
2795 unsigned int sample_rate_div;
2796 unsigned int sample_rate_mul;
2797 unsigned int num_chans;
2798 unsigned int hda_frame_size_words;
2799 unsigned int remainder_words;
2800 const u32 *data_remainder;
2801 u32 chip_addx_remainder;
2802 unsigned int run_size_words;
2803 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2804 unsigned long timeout;
2805 bool dma_active;
01ef7dbf
IM		 2806
2807 if (fls == NULL)
2808 return -EINVAL;
2809 if (is_hci_prog_list_seg(fls)) {
2810 hci_write = fls;
2811 fls = get_next_seg_ptr(fls);
2812 }
95c6e9cb 2813
01ef7dbf 2814 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2815 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2816 return dspxfr_hci_write(codec, hci_write);
2817 }
95c6e9cb 2818
01ef7dbf 2819 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2820 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2821 return -EINVAL;
95c6e9cb
IM		 2822 }
2823
01ef7dbf
IM		 2824 data = fls->data;
2825 chip_addx = fls->chip_addr,
2826 words_to_write = fls->count;
2827
2828 if (!words_to_write)
2829 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2830 if (reloc)
2831 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2832
2833 if (!UC_RANGE(chip_addx, words_to_write) &&
2834 !X_RANGE_ALL(chip_addx, words_to_write) &&
2835 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2836 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2837 return -EINVAL;
95c6e9cb
IM		 2838 }
2839
01ef7dbf
IM		 2840 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2841 sizeof(u32);
2842
2843 buffer_addx = dma_get_buffer_addr(dma_engine);
2844
2845 if (buffer_addx == NULL) {
4e76a883 2846 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2847 return -EINVAL;
2848 }
2849
2850 dma_get_converter_format(dma_engine, &hda_format);
2851 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2852 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2853 num_chans = get_hdafmt_chs(hda_format) + 1;
2854
2855 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2856 (num_chans * sample_rate_mul / sample_rate_div));
2857
3bc085a1 2858 if (hda_frame_size_words == 0) {
4e76a883 2859 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2860 return -EINVAL;
2861 }
2862
01ef7dbf
IM		 2863 buffer_size_words = min(buffer_size_words,
2864 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2865 65536 : 32768));
2866 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2867 codec_dbg(codec,
01ef7dbf
IM		 2868 "chpadr=0x%08x frmsz=%u nchan=%u "
2869 "rate_mul=%u div=%u bufsz=%u\n",
2870 chip_addx, hda_frame_size_words, num_chans,
2871 sample_rate_mul, sample_rate_div, buffer_size_words);
2872
3bc085a1 2873 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2874 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2875 return -EINVAL;
2876 }
2877
2878 remainder_words = words_to_write % hda_frame_size_words;
2879 data_remainder = data;
2880 chip_addx_remainder = chip_addx;
2881
2882 data += remainder_words;
2883 chip_addx += remainder_words*sizeof(u32);
2884 words_to_write -= remainder_words;
2885
2886 while (words_to_write != 0) {
2887 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2888 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2889 words_to_write, run_size_words, remainder_words);
2890 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2891 if (!comm_dma_setup_done) {
2892 status = dsp_dma_stop(codec, dma_chan, ovly);
2893 if (status < 0)
425a7880 2894 return status;
01ef7dbf
IM		 2895 status = dsp_dma_setup_common(codec, chip_addx,
2896 dma_chan, port_map_mask, ovly);
2897 if (status < 0)
2898 return status;
2899 comm_dma_setup_done = true;
2900 }
2901
2902 status = dsp_dma_setup(codec, chip_addx,
2903 run_size_words, dma_chan);
2904 if (status < 0)
2905 return status;
2906 status = dsp_dma_start(codec, dma_chan, ovly);
2907 if (status < 0)
2908 return status;
2909 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2910 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2911 return -EIO;
2912 }
2913 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2914 if (status < 0)
2915 return status;
2916 if (remainder_words != 0) {
2917 status = chipio_write_multiple(codec,
2918 chip_addx_remainder,
2919 data_remainder,
2920 remainder_words);
b3667bd7
TI		 2921 if (status < 0)
2922 return status;
01ef7dbf
IM		 2923 remainder_words = 0;
2924 }
2925 if (hci_write) {
2926 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2927 if (status < 0)
2928 return status;
01ef7dbf
IM		 2929 hci_write = NULL;
2930 }
6d67530e
IM		 2931
2932 timeout = jiffies + msecs_to_jiffies(2000);
2933 do {
2934 dma_active = dsp_is_dma_active(codec, dma_chan);
2935 if (!dma_active)
01ef7dbf 2936 break;
6d67530e
IM		 2937 msleep(20);
2938 } while (time_before(jiffies, timeout));
2939 if (dma_active)
2940 break;
2941
4e76a883 2942 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2943 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2944 status = dma_reset(dma_engine);
01ef7dbf
IM		 2945
2946 if (status < 0)
2947 return status;
2948
2949 data += run_size_words;
2950 chip_addx += run_size_words*sizeof(u32);
2951 words_to_write -= run_size_words;
2952 }
2953
2954 if (remainder_words != 0) {
2955 status = chipio_write_multiple(codec, chip_addx_remainder,
2956 data_remainder, remainder_words);
2957 }
2958
2959 return status;
95c6e9cb
IM		 2960}
2961
d5c21b88
IM		 2962/**
2963 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2964 *
2965 * @codec: the HDA codec
2966 * @fls_data: pointer to a fast load image
2967 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2968 * no relocation
e97249dd 2969 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2970 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2971 * @ovly: TRUE if overlay format is required
2972 *
2973 * Returns zero or a negative error code.
2974 */
01ef7dbf
IM		 2975static int dspxfr_image(struct hda_codec *codec,
2976 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2977 unsigned int reloc,
2978 unsigned int sample_rate,
2979 unsigned short channels,
01ef7dbf 2980 bool ovly)
95c6e9cb
IM		 2981{
2982 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2983 int status;
2984 unsigned short hda_format = 0;
2985 unsigned int response;
2986 unsigned char stream_id = 0;
2987 struct dma_engine *dma_engine;
2988 unsigned int dma_chan;
2989 unsigned int port_map_mask;
2990
2991 if (fls_data == NULL)
2992 return -EINVAL;
2993
2994 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2995 if (!dma_engine)
2996 return -ENOMEM;
95c6e9cb 2997
01ef7dbf
IM		 2998 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2999 if (!dma_engine->dmab) {
549e8292
TI		 3000 kfree(dma_engine);
3001 return -ENOMEM;
01ef7dbf 3002 }
95c6e9cb 3003
01ef7dbf 3004 dma_engine->codec = codec;
6194b99d 3005 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 3006 dma_engine->m_converter_format = hda_format;
3007 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3008 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3009
8ae3124b 3010 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 3011
3012 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3013 hda_format, &response);
3014
3015 if (status < 0) {
4e76a883 3016 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 3017 goto exit;
3018 }
3019
3020 status = snd_hda_codec_load_dsp_prepare(codec,
3021 dma_engine->m_converter_format,
3022 dma_engine->buf_size,
3023 dma_engine->dmab);
3024 if (status < 0)
95c6e9cb 3025 goto exit;
01ef7dbf
IM		 3026 spec->dsp_stream_id = status;
3027
3028 if (ovly) {
3029 status = dspio_alloc_dma_chan(codec, &dma_chan);
3030 if (status < 0) {
4e76a883 3031 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 3032 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 3033 goto exit;
3034 }
3035 }
95c6e9cb 3036
01ef7dbf
IM		 3037 port_map_mask = 0;
3038 status = dsp_allocate_ports_format(codec, hda_format,
3039 &port_map_mask);
3040 if (status < 0) {
4e76a883 3041 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 3042 goto exit;
3043 }
3044
3045 stream_id = dma_get_stream_id(dma_engine);
3046 status = codec_set_converter_stream_channel(codec,
3047 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3048 if (status < 0) {
4e76a883 3049 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 3050 goto exit;
3051 }
3052
3053 while ((fls_data != NULL) && !is_last(fls_data)) {
3054 if (!is_valid(fls_data)) {
4e76a883 3055 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 3056 status = -EINVAL;
3057 goto exit;
3058 }
3059 status = dspxfr_one_seg(codec, fls_data, reloc,
3060 dma_engine, dma_chan,
3061 port_map_mask, ovly);
3062 if (status < 0)
3063 break;
3064
3065 if (is_hci_prog_list_seg(fls_data))
3066 fls_data = get_next_seg_ptr(fls_data);
3067
3068 if ((fls_data != NULL) && !is_last(fls_data))
3069 fls_data = get_next_seg_ptr(fls_data);
3070 }
3071
3072 if (port_map_mask != 0)
3073 status = dsp_free_ports(codec);
3074
3075 if (status < 0)
95c6e9cb
IM		 3076 goto exit;
3077
01ef7dbf
IM		 3078 status = codec_set_converter_stream_channel(codec,
3079 WIDGET_CHIP_CTRL, 0, 0, &response);
3080
95c6e9cb 3081exit:
01ef7dbf
IM		 3082 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3083 dspio_free_dma_chan(codec, dma_chan);
3084
b3667bd7 3085 if (dma_engine->dmab->area)
01ef7dbf
IM		 3086 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3087 kfree(dma_engine->dmab);
3088 kfree(dma_engine);
3089
3090 return status;
95c6e9cb
IM		 3091}
3092
3093/*
01ef7dbf 3094 * CA0132 DSP download stuffs.
95c6e9cb 3095 */
01ef7dbf 3096static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 3097{
009b8f97 3098 struct ca0132_spec *spec = codec->spec;
4e76a883 3099 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 3100 if (!spec->use_alt_functions) {
3101 /*set DSP speaker to 2.0 configuration*/
3102 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3103 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 3104
009b8f97
CM		 3105 /*update write pointer*/
3106 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3107 }
01ef7dbf 3108}
95c6e9cb 3109
d5c21b88 3110/**
e60b2c7f 3111 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 3112 *
3113 * @codec: the HDA codec
3114 * @fls: pointer to a fast load image
3115 * @ovly: TRUE if overlay format is required
3116 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3117 * no relocation
3118 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3119 * @router_chans: number of audio router channels to be allocated (0 means use
3120 * internal defaults; max is 32)
3121 *
e60b2c7f
TI		 3122 * Download DSP from a DSP Image Fast Load structure. This structure is a
3123 * linear, non-constant sized element array of structures, each of which
3124 * contain the count of the data to be loaded, the data itself, and the
3125 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 3126 * Returns zero or a negative error code.
3127 */
01ef7dbf
IM		 3128static int dspload_image(struct hda_codec *codec,
3129 const struct dsp_image_seg *fls,
3130 bool ovly,
3131 unsigned int reloc,
3132 bool autostart,
3133 int router_chans)
3134{
3135 int status = 0;
e97249dd
IM		 3136 unsigned int sample_rate;
3137 unsigned short channels;
01ef7dbf 3138
4e76a883 3139 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 3140 if (router_chans == 0) {
3141 if (!ovly)
3142 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3143 else
3144 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3145 }
95c6e9cb 3146
e97249dd
IM		 3147 sample_rate = 48000;
3148 channels = (unsigned short)router_chans;
01ef7dbf 3149
e97249dd
IM		 3150 while (channels > 16) {
3151 sample_rate *= 2;
3152 channels /= 2;
01ef7dbf
IM		 3153 }
3154
01ef7dbf 3155 do {
4e76a883 3156 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3157 if (!ovly)
3158 status = dsp_reset(codec);
3159
3160 if (status < 0)
3161 break;
3162
4e76a883 3163 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3164 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3165 ovly);
01ef7dbf
IM		 3166
3167 if (status < 0)
3168 break;
3169
4e76a883 3170 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3171 if (autostart && !ovly) {
3172 dspload_post_setup(codec);
3173 status = dsp_set_run_state(codec);
3174 }
3175
4e76a883 3176 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3177 } while (0);
3178
3179 return status;
3180}
3181
f664417e 3182#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3183static bool dspload_is_loaded(struct hda_codec *codec)
3184{
3185 unsigned int data = 0;
3186 int status = 0;
3187
3188 status = chipio_read(codec, 0x40004, &data);
3189 if ((status < 0) || (data != 1))
3190 return false;
3191
3192 return true;
3193}
f664417e
TI		 3194#else
3195#define dspload_is_loaded(codec) false
3196#endif
01ef7dbf
IM		 3197
3198static bool dspload_wait_loaded(struct hda_codec *codec)
3199{
6d67530e 3200 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3201
3202 do {
01ef7dbf 3203 if (dspload_is_loaded(codec)) {
d9684bb5 3204 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3205 return true;
3206 }
6d67530e
IM		 3207 msleep(20);
3208 } while (time_before(jiffies, timeout));
01ef7dbf 3209
d9684bb5 3210 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3211 return false;
95c6e9cb
IM		 3212}
3213
e93ac30a 3214/*
b9b41345
CM		 3215 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3216 * based cards, and has a second mmio region, region2, that's used for special
3217 * commands.
e93ac30a
CM		 3218 */
3219
a62e4739
CM		 3220/*
3221 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3222 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3223 * The first eight bits are just the number of the pin. So far, I've only seen
3224 * this number go to 7.
b9b41345
CM		 3225 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3226 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3227 * then off to send that bit.
a62e4739 3228 */
b9b41345 3229static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
a62e4739
CM		 3230 bool enable)
3231{
3232 struct ca0132_spec *spec = codec->spec;
3233 unsigned short gpio_data;
3234
3235 gpio_data = gpio_pin & 0xF;
3236 gpio_data |= ((enable << 8) & 0x100);
3237
3238 writew(gpio_data, spec->mem_base + 0x320);
3239}
3240
b9b41345
CM		 3241/*
3242 * Special pci region2 commands that are only used by the AE-5. They follow
3243 * a set format, and require reads at certain points to seemingly 'clear'
3244 * the response data. My first tests didn't do these reads, and would cause
3245 * the card to get locked up until the memory was read. These commands
3246 * seem to work with three distinct values that I've taken to calling group,
3247 * target-id, and value.
3248 */
3249static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3250 unsigned int target, unsigned int value)
3251{
3252 struct ca0132_spec *spec = codec->spec;
3253 unsigned int write_val;
3254
3255 writel(0x0000007e, spec->mem_base + 0x210);
3256 readl(spec->mem_base + 0x210);
3257 writel(0x0000005a, spec->mem_base + 0x210);
3258 readl(spec->mem_base + 0x210);
3259 readl(spec->mem_base + 0x210);
3260
3261 writel(0x00800005, spec->mem_base + 0x20c);
3262 writel(group, spec->mem_base + 0x804);
3263
3264 writel(0x00800005, spec->mem_base + 0x20c);
3265 write_val = (target & 0xff);
3266 write_val |= (value << 8);
3267
3268
3269 writel(write_val, spec->mem_base + 0x204);
3270 /*
3271 * Need delay here or else it goes too fast and works inconsistently.
3272 */
3273 msleep(20);
3274
3275 readl(spec->mem_base + 0x860);
3276 readl(spec->mem_base + 0x854);
3277 readl(spec->mem_base + 0x840);
3278
3279 writel(0x00800004, spec->mem_base + 0x20c);
3280 writel(0x00000000, spec->mem_base + 0x210);
3281 readl(spec->mem_base + 0x210);
3282 readl(spec->mem_base + 0x210);
3283}
3284
212de2e7
CM		 3285/*
3286 * This second type of command is used for setting the sound filter type.
3287 */
3288static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3289 unsigned int group, unsigned int target, unsigned int value)
3290{
3291 struct ca0132_spec *spec = codec->spec;
3292 unsigned int write_val;
3293
3294 writel(0x0000007e, spec->mem_base + 0x210);
3295 readl(spec->mem_base + 0x210);
3296 writel(0x0000005a, spec->mem_base + 0x210);
3297 readl(spec->mem_base + 0x210);
3298 readl(spec->mem_base + 0x210);
3299
3300 writel(0x00800003, spec->mem_base + 0x20c);
3301 writel(group, spec->mem_base + 0x804);
3302
3303 writel(0x00800005, spec->mem_base + 0x20c);
3304 write_val = (target & 0xff);
3305 write_val |= (value << 8);
3306
3307
3308 writel(write_val, spec->mem_base + 0x204);
3309 msleep(20);
3310 readl(spec->mem_base + 0x860);
3311 readl(spec->mem_base + 0x854);
3312 readl(spec->mem_base + 0x840);
3313
3314 writel(0x00800004, spec->mem_base + 0x20c);
3315 writel(0x00000000, spec->mem_base + 0x210);
3316 readl(spec->mem_base + 0x210);
3317 readl(spec->mem_base + 0x210);
3318}
3319
b9b41345
CM		 3320/*
3321 * Setup GPIO for the other variants of Core3D.
3322 */
3323
e93ac30a
CM		 3324/*
3325 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3326 * the card shows as having no GPIO pins.
3327 */
3328static void ca0132_gpio_init(struct hda_codec *codec)
3329{
3330 struct ca0132_spec *spec = codec->spec;
3331
3332 switch (spec->quirk) {
3333 case QUIRK_SBZ:
03c9b6b1 3334 case QUIRK_AE5:
e93ac30a
CM		 3335 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3336 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3337 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3338 break;
3339 case QUIRK_R3DI:
3340 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3341 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3342 break;
3343 }
3344
3345}
3346
3347/* Sets the GPIO for audio output. */
3348static void ca0132_gpio_setup(struct hda_codec *codec)
3349{
3350 struct ca0132_spec *spec = codec->spec;
3351
3352 switch (spec->quirk) {
3353 case QUIRK_SBZ:
3354 snd_hda_codec_write(codec, 0x01, 0,
3355 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3356 snd_hda_codec_write(codec, 0x01, 0,
3357 AC_VERB_SET_GPIO_MASK, 0x07);
3358 snd_hda_codec_write(codec, 0x01, 0,
3359 AC_VERB_SET_GPIO_DATA, 0x04);
3360 snd_hda_codec_write(codec, 0x01, 0,
3361 AC_VERB_SET_GPIO_DATA, 0x06);
3362 break;
3363 case QUIRK_R3DI:
3364 snd_hda_codec_write(codec, 0x01, 0,
3365 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3366 snd_hda_codec_write(codec, 0x01, 0,
3367 AC_VERB_SET_GPIO_MASK, 0x1F);
3368 snd_hda_codec_write(codec, 0x01, 0,
3369 AC_VERB_SET_GPIO_DATA, 0x0C);
3370 break;
3371 }
3372}
3373
7e6ed62e
CM		 3374/*
3375 * GPIO control functions for the Recon3D integrated.
3376 */
3377
3378enum r3di_gpio_bit {
3379 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3380 R3DI_MIC_SELECT_BIT = 1,
3381 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3382 R3DI_OUT_SELECT_BIT = 2,
3383 /*
3384 * I dunno what this actually does, but it stays on until the dsp
3385 * is downloaded.
3386 */
3387 R3DI_GPIO_DSP_DOWNLOADING = 3,
3388 /*
3389 * Same as above, no clue what it does, but it comes on after the dsp
3390 * is downloaded.
3391 */
3392 R3DI_GPIO_DSP_DOWNLOADED = 4
3393};
3394
3395enum r3di_mic_select {
3396 /* Set GPIO bit 1 to 0 for rear mic */
3397 R3DI_REAR_MIC = 0,
3398 /* Set GPIO bit 1 to 1 for front microphone*/
3399 R3DI_FRONT_MIC = 1
3400};
3401
3402enum r3di_out_select {
3403 /* Set GPIO bit 2 to 0 for headphone */
3404 R3DI_HEADPHONE_OUT = 0,
3405 /* Set GPIO bit 2 to 1 for speaker */
3406 R3DI_LINE_OUT = 1
3407};
3408enum r3di_dsp_status {
3409 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3410 R3DI_DSP_DOWNLOADING = 0,
3411 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3412 R3DI_DSP_DOWNLOADED = 1
3413};
3414
7cb9d94c
CM		 3415
3416static void r3di_gpio_mic_set(struct hda_codec *codec,
3417 enum r3di_mic_select cur_mic)
3418{
3419 unsigned int cur_gpio;
3420
3421 /* Get the current GPIO Data setup */
3422 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3423
3424 switch (cur_mic) {
3425 case R3DI_REAR_MIC:
3426 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3427 break;
3428 case R3DI_FRONT_MIC:
3429 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3430 break;
3431 }
3432 snd_hda_codec_write(codec, codec->core.afg, 0,
3433 AC_VERB_SET_GPIO_DATA, cur_gpio);
3434}
3435
3436static void r3di_gpio_out_set(struct hda_codec *codec,
3437 enum r3di_out_select cur_out)
3438{
3439 unsigned int cur_gpio;
3440
3441 /* Get the current GPIO Data setup */
3442 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3443
3444 switch (cur_out) {
3445 case R3DI_HEADPHONE_OUT:
3446 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3447 break;
3448 case R3DI_LINE_OUT:
3449 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3450 break;
3451 }
3452 snd_hda_codec_write(codec, codec->core.afg, 0,
3453 AC_VERB_SET_GPIO_DATA, cur_gpio);
3454}
3455
7e6ed62e
CM		 3456static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3457 enum r3di_dsp_status dsp_status)
3458{
3459 unsigned int cur_gpio;
3460
3461 /* Get the current GPIO Data setup */
3462 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3463
3464 switch (dsp_status) {
3465 case R3DI_DSP_DOWNLOADING:
3466 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3467 snd_hda_codec_write(codec, codec->core.afg, 0,
3468 AC_VERB_SET_GPIO_DATA, cur_gpio);
3469 break;
3470 case R3DI_DSP_DOWNLOADED:
3471 /* Set DOWNLOADING bit to 0. */
3472 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3473
3474 snd_hda_codec_write(codec, codec->core.afg, 0,
3475 AC_VERB_SET_GPIO_DATA, cur_gpio);
3476
3477 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3478 break;
3479 }
3480
3481 snd_hda_codec_write(codec, codec->core.afg, 0,
3482 AC_VERB_SET_GPIO_DATA, cur_gpio);
3483}
3484
825315bc
IM		 3485/*
3486 * PCM callbacks
3487 */
95c6e9cb
IM		 3488static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3489 struct hda_codec *codec,
3490 unsigned int stream_tag,
3491 unsigned int format,
3492 struct snd_pcm_substream *substream)
3493{
3494 struct ca0132_spec *spec = codec->spec;
825315bc 3495
28fba950 3496 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3497
3498 return 0;
95c6e9cb
IM		 3499}
3500
3501static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3502 struct hda_codec *codec,
3503 struct snd_pcm_substream *substream)
3504{
3505 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3506
3507 if (spec->dsp_state == DSP_DOWNLOADING)
3508 return 0;
3509
3510 /*If Playback effects are on, allow stream some time to flush
3511 *effects tail*/
3512 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3513 msleep(50);
3514
28fba950 3515 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3516
3517 return 0;
95c6e9cb
IM		 3518}
3519
e8412ca4
DR		 3520static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3521 struct hda_codec *codec,
3522 struct snd_pcm_substream *substream)
3523{
3524 struct ca0132_spec *spec = codec->spec;
3525 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3526 struct snd_pcm_runtime *runtime = substream->runtime;
3527
3528 if (spec->dsp_state != DSP_DOWNLOADED)
3529 return 0;
3530
3531 /* Add latency if playback enhancement and either effect is enabled. */
3532 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3533 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3534 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3535 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3536 }
3537
3538 /* Applying Speaker EQ adds latency as well. */
3539 if (spec->cur_out_type == SPEAKER_OUT)
3540 latency += DSP_SPEAKER_OUT_LATENCY;
3541
3542 return (latency * runtime->rate) / 1000;
3543}
3544
95c6e9cb
IM		 3545/*
3546 * Digital out
3547 */
27ebeb0b
TI		 3548static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3549 struct hda_codec *codec,
3550 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3551{
3552 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3553 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3554}
3555
27ebeb0b 3556static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3557 struct hda_codec *codec,
3558 unsigned int stream_tag,
3559 unsigned int format,
3560 struct snd_pcm_substream *substream)
3561{
3562 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3563 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3564 stream_tag, format, substream);
95c6e9cb
IM		 3565}
3566
27ebeb0b 3567static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3568 struct hda_codec *codec,
95c6e9cb
IM		 3569 struct snd_pcm_substream *substream)
3570{
3571 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3572 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3573}
3574
27ebeb0b
TI		 3575static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3576 struct hda_codec *codec,
3577 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3578{
3579 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3580 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3581}
3582
825315bc
IM		 3583/*
3584 * Analog capture
3585 */
3586static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3587 struct hda_codec *codec,
3588 unsigned int stream_tag,
3589 unsigned int format,
3590 struct snd_pcm_substream *substream)
3591{
13c12dbe 3592 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3593 stream_tag, 0, format);
825315bc
IM		 3594
3595 return 0;
3596}
3597
3598static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3599 struct hda_codec *codec,
3600 struct snd_pcm_substream *substream)
3601{
3602 struct ca0132_spec *spec = codec->spec;
3603
3604 if (spec->dsp_state == DSP_DOWNLOADING)
3605 return 0;
3606
28fba950 3607 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3608 return 0;
3609}
3610
e8412ca4
DR		 3611static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3612 struct hda_codec *codec,
3613 struct snd_pcm_substream *substream)
3614{
3615 struct ca0132_spec *spec = codec->spec;
3616 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3617 struct snd_pcm_runtime *runtime = substream->runtime;
3618
3619 if (spec->dsp_state != DSP_DOWNLOADED)
3620 return 0;
3621
3622 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3623 latency += DSP_CRYSTAL_VOICE_LATENCY;
3624
3625 return (latency * runtime->rate) / 1000;
3626}
3627
e90f29e4
IM		 3628/*
3629 * Controls stuffs.
3630 */
3631
3632/*
3633 * Mixer controls helpers.
3634 */
3635#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3636 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3637 .name = xname, \
3638 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3639 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3640 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3641 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3642 .info = ca0132_volume_info, \
3643 .get = ca0132_volume_get, \
3644 .put = ca0132_volume_put, \
3645 .tlv = { .c = ca0132_volume_tlv }, \
3646 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3647
017310fb
CM		 3648/*
3649 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3650 * volume put, which is used for setting the DSP volume. This was done because
3651 * the ca0132 functions were taking too much time and causing lag.
3652 */
3653#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3654 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3655 .name = xname, \
3656 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3657 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3658 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3659 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3660 .info = snd_hda_mixer_amp_volume_info, \
3661 .get = snd_hda_mixer_amp_volume_get, \
3662 .put = ca0132_alt_volume_put, \
3663 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3664 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3665
e90f29e4
IM		 3666#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3667 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3668 .name = xname, \
3669 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3670 .info = snd_hda_mixer_amp_switch_info, \
3671 .get = ca0132_switch_get, \
3672 .put = ca0132_switch_put, \
3673 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3674
3675/* stereo */
3676#define CA0132_CODEC_VOL(xname, nid, dir) \
3677 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3678#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3679 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3680#define CA0132_CODEC_MUTE(xname, nid, dir) \
3681 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3682
017310fb
CM		 3683/* lookup tables */
3684/*
3685 * Lookup table with decibel values for the DSP. When volume is changed in
3686 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3687 * these values have decimal points, probably because the Windows driver
3688 * actually uses floating point. We can't here, so I made a lookup table of
3689 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3690 * DAC's, and 9 is the maximum.
3691 */
3692static const unsigned int float_vol_db_lookup[] = {
36930xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
36940xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
36950xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
36960xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
36970xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
36980xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
36990xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
37000xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
37010xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
37020xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
37030xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
37040xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
37050xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
37060xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
37070xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
37080x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
37090x40C00000, 0x40E00000, 0x41000000, 0x41100000
3710};
3711
47cdf76e
CM		 3712/*
3713 * This table counts from float 0 to 1 in increments of .01, which is
3714 * useful for a few different sliders.
3715 */
3716static const unsigned int float_zero_to_one_lookup[] = {
37170x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37180x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37190x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37200x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
37210x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
37220x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
37230x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
37240x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
37250x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
37260x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
37270x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
37280x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
37290x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
37300x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
37310x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
37320x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
37330x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3734};
3735
3736/*
3737 * This table counts from float 10 to 1000, which is the range of the x-bass
3738 * crossover slider in Windows.
3739 */
3740static const unsigned int float_xbass_xover_lookup[] = {
37410x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
37420x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
37430x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
37440x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
37450x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
37460x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
37470x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
37480x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
37490x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
37500x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
37510x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
37520x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
37530x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
37540x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
37550x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
37560x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
37570x44728000, 0x44750000, 0x44778000, 0x447A0000
3758};
3759
4091fb95 3760/* The following are for tuning of products */
44f0c978
IM		 3761#ifdef ENABLE_TUNING_CONTROLS
3762
3763static unsigned int voice_focus_vals_lookup[] = {
37640x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
37650x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
37660x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
37670x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
37680x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
37690x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
37700x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
37710x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
37720x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
37730x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
37740x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
37750x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
37760x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
37770x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
37780x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
37790x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
37800x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
37810x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
37820x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
37830x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
37840x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
37850x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
37860x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
37870x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
37880x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
37890x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
37900x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3791};
3792
3793static unsigned int mic_svm_vals_lookup[] = {
37940x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37950x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37960x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37970x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
37980x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
37990x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
38000x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
38010x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
38020x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
38030x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
38040x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
38050x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
38060x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
38070x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
38080x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
38090x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
38100x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3811};
3812
3813static unsigned int equalizer_vals_lookup[] = {
38140xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
38150xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
38160xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
38170xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
38180x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
38190x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
38200x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
38210x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
38220x41C00000
3823};
3824
3825static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3826 unsigned int *lookup, int idx)
3827{
3828 int i = 0;
3829
3830 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3831 if (nid == ca0132_tuning_ctls[i].nid)
3832 break;
3833
3834 snd_hda_power_up(codec);
447fd8e9 3835 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3836 ca0132_tuning_ctls[i].req,
3837 &(lookup[idx]), sizeof(unsigned int));
3838 snd_hda_power_down(codec);
3839
3840 return 1;
3841}
3842
3843static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3844 struct snd_ctl_elem_value *ucontrol)
3845{
3846 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3847 struct ca0132_spec *spec = codec->spec;
3848 hda_nid_t nid = get_amp_nid(kcontrol);
3849 long *valp = ucontrol->value.integer.value;
3850 int idx = nid - TUNING_CTL_START_NID;
3851
3852 *valp = spec->cur_ctl_vals[idx];
3853 return 0;
3854}
3855
3856static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3857 struct snd_ctl_elem_info *uinfo)
3858{
3859 int chs = get_amp_channels(kcontrol);
3860 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3861 uinfo->count = chs == 3 ? 2 : 1;
3862 uinfo->value.integer.min = 20;
3863 uinfo->value.integer.max = 180;
3864 uinfo->value.integer.step = 1;
3865
3866 return 0;
3867}
3868
3869static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3870 struct snd_ctl_elem_value *ucontrol)
3871{
3872 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3873 struct ca0132_spec *spec = codec->spec;
3874 hda_nid_t nid = get_amp_nid(kcontrol);
3875 long *valp = ucontrol->value.integer.value;
3876 int idx;
3877
3878 idx = nid - TUNING_CTL_START_NID;
3879 /* any change? */
3880 if (spec->cur_ctl_vals[idx] == *valp)
3881 return 0;
3882
3883 spec->cur_ctl_vals[idx] = *valp;
3884
3885 idx = *valp - 20;
3886 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3887
3888 return 1;
3889}
3890
3891static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3892 struct snd_ctl_elem_info *uinfo)
3893{
3894 int chs = get_amp_channels(kcontrol);
3895 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3896 uinfo->count = chs == 3 ? 2 : 1;
3897 uinfo->value.integer.min = 0;
3898 uinfo->value.integer.max = 100;
3899 uinfo->value.integer.step = 1;
3900
3901 return 0;
3902}
3903
3904static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3905 struct snd_ctl_elem_value *ucontrol)
3906{
3907 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3908 struct ca0132_spec *spec = codec->spec;
3909 hda_nid_t nid = get_amp_nid(kcontrol);
3910 long *valp = ucontrol->value.integer.value;
3911 int idx;
3912
3913 idx = nid - TUNING_CTL_START_NID;
3914 /* any change? */
3915 if (spec->cur_ctl_vals[idx] == *valp)
3916 return 0;
3917
3918 spec->cur_ctl_vals[idx] = *valp;
3919
3920 idx = *valp;
3921 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3922
3923 return 0;
3924}
3925
3926static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3927 struct snd_ctl_elem_info *uinfo)
3928{
3929 int chs = get_amp_channels(kcontrol);
3930 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3931 uinfo->count = chs == 3 ? 2 : 1;
3932 uinfo->value.integer.min = 0;
3933 uinfo->value.integer.max = 48;
3934 uinfo->value.integer.step = 1;
3935
3936 return 0;
3937}
3938
3939static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3940 struct snd_ctl_elem_value *ucontrol)
3941{
3942 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3943 struct ca0132_spec *spec = codec->spec;
3944 hda_nid_t nid = get_amp_nid(kcontrol);
3945 long *valp = ucontrol->value.integer.value;
3946 int idx;
3947
3948 idx = nid - TUNING_CTL_START_NID;
3949 /* any change? */
3950 if (spec->cur_ctl_vals[idx] == *valp)
3951 return 0;
3952
3953 spec->cur_ctl_vals[idx] = *valp;
3954
3955 idx = *valp;
3956 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3957
3958 return 1;
3959}
3960
8e142e9e
TS		 3961static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3962static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3963
3964static int add_tuning_control(struct hda_codec *codec,
3965 hda_nid_t pnid, hda_nid_t nid,
3966 const char *name, int dir)
3967{
975cc02a 3968 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3969 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3970 struct snd_kcontrol_new knew =
3971 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3972
3973 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3974 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3975 knew.tlv.c = 0;
3976 knew.tlv.p = 0;
3977 switch (pnid) {
3978 case VOICE_FOCUS:
3979 knew.info = voice_focus_ctl_info;
3980 knew.get = tuning_ctl_get;
3981 knew.put = voice_focus_ctl_put;
3982 knew.tlv.p = voice_focus_db_scale;
3983 break;
3984 case MIC_SVM:
3985 knew.info = mic_svm_ctl_info;
3986 knew.get = tuning_ctl_get;
3987 knew.put = mic_svm_ctl_put;
3988 break;
3989 case EQUALIZER:
3990 knew.info = equalizer_ctl_info;
3991 knew.get = tuning_ctl_get;
3992 knew.put = equalizer_ctl_put;
3993 knew.tlv.p = eq_db_scale;
3994 break;
3995 default:
3996 return 0;
3997 }
3998 knew.private_value =
3999 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4000 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4001 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4002}
4003
4004static int add_tuning_ctls(struct hda_codec *codec)
4005{
4006 int i;
4007 int err;
4008
4009 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4010 err = add_tuning_control(codec,
4011 ca0132_tuning_ctls[i].parent_nid,
4012 ca0132_tuning_ctls[i].nid,
4013 ca0132_tuning_ctls[i].name,
4014 ca0132_tuning_ctls[i].direct);
4015 if (err < 0)
4016 return err;
4017 }
4018
4019 return 0;
4020}
4021
4022static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4023{
4024 struct ca0132_spec *spec = codec->spec;
4025 int i;
4026
4027 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4028 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4029 /* SVM level defaults to 0.74. */
4030 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4031
4032 /* EQ defaults to 0dB. */
4033 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4034 spec->cur_ctl_vals[i] = 24;
4035}
4036#endif /*ENABLE_TUNING_CONTROLS*/
4037
5aaca44d
IM		 4038/*
4039 * Select the active output.
4040 * If autodetect is enabled, output will be selected based on jack detection.
4041 * If jack inserted, headphone will be selected, else built-in speakers
4042 * If autodetect is disabled, output will be selected based on selection.
4043 */
4044static int ca0132_select_out(struct hda_codec *codec)
4045{
4046 struct ca0132_spec *spec = codec->spec;
4047 unsigned int pin_ctl;
4048 int jack_present;
4049 int auto_jack;
4050 unsigned int tmp;
4051 int err;
4052
4e76a883 4053 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 4054
664c7155 4055 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4056
4057 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4058
4059 if (auto_jack)
fe14f39e 4060 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 4061 else
4062 jack_present =
4063 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4064
4065 if (jack_present)
4066 spec->cur_out_type = HEADPHONE_OUT;
4067 else
4068 spec->cur_out_type = SPEAKER_OUT;
4069
4070 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 4071 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 4072 /*speaker out config*/
4073 tmp = FLOAT_ONE;
4074 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4075 if (err < 0)
4076 goto exit;
4077 /*enable speaker EQ*/
4078 tmp = FLOAT_ONE;
4079 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4080 if (err < 0)
4081 goto exit;
4082
4083 /* Setup EAPD */
4084 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4085 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4086 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4087 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4088 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4089 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4090 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4091 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4092
4093 /* disable headphone node */
4094 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4095 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4096 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4097 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4098 /* enable speaker node */
4099 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 4100 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4101 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4102 pin_ctl | PIN_OUT);
5aaca44d 4103 } else {
4e76a883 4104 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 4105 /*headphone out config*/
4106 tmp = FLOAT_ZERO;
4107 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4108 if (err < 0)
4109 goto exit;
4110 /*disable speaker EQ*/
4111 tmp = FLOAT_ZERO;
4112 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4113 if (err < 0)
4114 goto exit;
4115
4116 /* Setup EAPD */
4117 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4118 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4119 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4120 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4121 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4122 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4123 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4124 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4125
4126 /* disable speaker*/
4127 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4128 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4129 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4130 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4131 /* enable headphone*/
4132 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4133 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4134 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4135 pin_ctl | PIN_HP);
5aaca44d
IM		 4136 }
4137
4138exit:
664c7155 4139 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4140
4141 return err < 0 ? err : 0;
4142}
4143
212de2e7 4144static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
8e6bc6b3 4145static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
212de2e7 4146
2283c85b
CM		 4147static void ae5_mmio_select_out(struct hda_codec *codec)
4148{
4149 struct ca0132_spec *spec = codec->spec;
4150 unsigned int i;
4151
4152 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++)
4153 ca0113_mmio_command_set(codec,
4154 ae5_ca0113_output_presets[spec->cur_out_type].group[i],
4155 ae5_ca0113_output_presets[spec->cur_out_type].target[i],
4156 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]);
4157}
4158
746fc9de
CM		 4159/*
4160 * These are the commands needed to setup output on each of the different card
4161 * types.
4162 */
4163static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4164{
4165 struct ca0132_spec *spec = codec->spec;
2283c85b 4166 unsigned int tmp;
746fc9de
CM		 4167
4168 switch (spec->cur_out_type) {
4169 case SPEAKER_OUT:
4170 switch (spec->quirk) {
4171 case QUIRK_SBZ:
4172 ca0113_mmio_gpio_set(codec, 7, false);
4173 ca0113_mmio_gpio_set(codec, 4, true);
4174 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4175 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de
CM		 4176 break;
4177 case QUIRK_R3DI:
2283c85b 4178 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4179 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4180 break;
4181 case QUIRK_R3D:
2283c85b 4182 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4183 ca0113_mmio_gpio_set(codec, 1, true);
4184 break;
2283c85b
CM		 4185 case QUIRK_AE5:
4186 ae5_mmio_select_out(codec);
212de2e7 4187 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4188 tmp = FLOAT_ZERO;
4189 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4190 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4191 chipio_set_control_param(codec, 0x0d, 0xa4);
4192 chipio_write(codec, 0x18b03c, 0x00000012);
4193 break;
746fc9de
CM		 4194 }
4195 break;
4196 case HEADPHONE_OUT:
4197 switch (spec->quirk) {
4198 case QUIRK_SBZ:
4199 ca0113_mmio_gpio_set(codec, 7, true);
4200 ca0113_mmio_gpio_set(codec, 4, true);
4201 ca0113_mmio_gpio_set(codec, 1, false);
2283c85b 4202 chipio_set_control_param(codec, 0x0d, 0x12);
746fc9de
CM		 4203 break;
4204 case QUIRK_R3DI:
2283c85b 4205 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4206 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4207 break;
4208 case QUIRK_R3D:
2283c85b 4209 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4210 ca0113_mmio_gpio_set(codec, 0x1, false);
4211 break;
2283c85b
CM		 4212 case QUIRK_AE5:
4213 ae5_mmio_select_out(codec);
212de2e7
CM		 4214 ae5_headphone_gain_set(codec,
4215 spec->ae5_headphone_gain_val);
2283c85b
CM		 4216 tmp = FLOAT_ONE;
4217 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4218 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4219 chipio_set_control_param(codec, 0x0d, 0xa1);
4220 chipio_write(codec, 0x18b03c, 0x00000012);
4221 break;
746fc9de
CM		 4222 }
4223 break;
4224 case SURROUND_OUT:
4225 switch (spec->quirk) {
4226 case QUIRK_SBZ:
4227 ca0113_mmio_gpio_set(codec, 7, false);
4228 ca0113_mmio_gpio_set(codec, 4, true);
4229 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4230 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de
CM		 4231 break;
4232 case QUIRK_R3DI:
2283c85b 4233 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4234 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4235 break;
4236 case QUIRK_R3D:
4237 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b
CM		 4238 chipio_set_control_param(codec, 0x0d, 0x24);
4239 break;
4240 case QUIRK_AE5:
4241 ae5_mmio_select_out(codec);
212de2e7 4242 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4243 tmp = FLOAT_ZERO;
4244 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4245 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4246 chipio_set_control_param(codec, 0x0d, 0xa4);
4247 chipio_write(codec, 0x18b03c, 0x00000012);
746fc9de
CM		 4248 break;
4249 }
4250 break;
4251 }
4252}
4253
7cb9d94c
CM		 4254/*
4255 * This function behaves similarly to the ca0132_select_out funciton above,
4256 * except with a few differences. It adds the ability to select the current
4257 * output with an enumerated control "output source" if the auto detect
4258 * mute switch is set to off. If the auto detect mute switch is enabled, it
4259 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4260 * It also adds the ability to auto-detect the front headphone port. The only
4261 * way to select surround is to disable auto detect, and set Surround with the
4262 * enumerated control.
4263 */
4264static int ca0132_alt_select_out(struct hda_codec *codec)
4265{
4266 struct ca0132_spec *spec = codec->spec;
4267 unsigned int pin_ctl;
4268 int jack_present;
4269 int auto_jack;
4270 unsigned int i;
4271 unsigned int tmp;
4272 int err;
4273 /* Default Headphone is rear headphone */
4274 hda_nid_t headphone_nid = spec->out_pins[1];
4275
4276 codec_dbg(codec, "%s\n", __func__);
4277
4278 snd_hda_power_up_pm(codec);
4279
4280 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4281
4282 /*
4283 * If headphone rear or front is plugged in, set to headphone.
4284 * If neither is plugged in, set to rear line out. Only if
4285 * hp/speaker auto detect is enabled.
4286 */
4287 if (auto_jack) {
4288 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4289 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4290
4291 if (jack_present)
4292 spec->cur_out_type = HEADPHONE_OUT;
4293 else
4294 spec->cur_out_type = SPEAKER_OUT;
4295 } else
4296 spec->cur_out_type = spec->out_enum_val;
4297
4298 /* Begin DSP output switch */
4299 tmp = FLOAT_ONE;
4300 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4301 if (err < 0)
4302 goto exit;
4303
746fc9de
CM		 4304 ca0132_alt_select_out_quirk_handler(codec);
4305
7cb9d94c
CM		 4306 switch (spec->cur_out_type) {
4307 case SPEAKER_OUT:
4308 codec_dbg(codec, "%s speaker\n", __func__);
7cb9d94c
CM		 4309
4310 /* disable headphone node */
4311 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4312 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4313 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4314 pin_ctl & ~PIN_HP);
4315 /* enable line-out node */
4316 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4317 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4318 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4319 pin_ctl | PIN_OUT);
4320 /* Enable EAPD */
4321 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4322 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4323
4324 /* If PlayEnhancement is enabled, set different source */
4325 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4326 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4327 else
4328 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4329 break;
4330 case HEADPHONE_OUT:
4331 codec_dbg(codec, "%s hp\n", __func__);
7cb9d94c
CM		 4332
4333 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4334 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4335
4336 /* disable speaker*/
4337 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4338 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4339 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4340 pin_ctl & ~PIN_HP);
4341
4342 /* enable headphone, either front or rear */
4343
4344 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4345 headphone_nid = spec->out_pins[2];
4346 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4347 headphone_nid = spec->out_pins[1];
4348
4349 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4350 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4351 snd_hda_set_pin_ctl(codec, headphone_nid,
4352 pin_ctl | PIN_HP);
4353
4354 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4355 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4356 else
4357 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4358 break;
4359 case SURROUND_OUT:
4360 codec_dbg(codec, "%s surround\n", __func__);
746fc9de 4361
7cb9d94c
CM		 4362 /* enable line out node */
4363 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4364 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4365 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4366 pin_ctl | PIN_OUT);
4367 /* Disable headphone out */
4368 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4369 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4370 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4371 pin_ctl & ~PIN_HP);
4372 /* Enable EAPD on line out */
4373 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4374 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4375 /* enable center/lfe out node */
4376 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4377 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4378 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4379 pin_ctl | PIN_OUT);
4380 /* Now set rear surround node as out. */
4381 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4382 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4383 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4384 pin_ctl | PIN_OUT);
4385
8e6bc6b3 4386 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
7cb9d94c
CM		 4387 break;
4388 }
8e6bc6b3
CM		 4389 /*
4390 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT.
4391 * With this set though, X_BASS cannot be enabled. So, if we have OutFX
4392 * enabled, we need to make sure X_BASS is off, otherwise everything
4393 * sounds all muffled. Running ca0132_effects_set with X_BASS as the
4394 * effect should sort this out.
4395 */
4396 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4397 ca0132_effects_set(codec, X_BASS,
4398 spec->effects_switch[X_BASS - EFFECT_START_NID]);
7cb9d94c 4399
2283c85b 4400 /* run through the output dsp commands for the selected output. */
7cb9d94c
CM		 4401 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4402 err = dspio_set_uint_param(codec,
4403 alt_out_presets[spec->cur_out_type].mids[i],
4404 alt_out_presets[spec->cur_out_type].reqs[i],
4405 alt_out_presets[spec->cur_out_type].vals[i]);
4406
4407 if (err < 0)
4408 goto exit;
4409 }
4410
4411exit:
4412 snd_hda_power_down_pm(codec);
4413
4414 return err < 0 ? err : 0;
4415}
4416
993884f6
CCC		 4417static void ca0132_unsol_hp_delayed(struct work_struct *work)
4418{
4419 struct ca0132_spec *spec = container_of(
4420 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4421 struct hda_jack_tbl *jack;
4422
7cb9d94c
CM		 4423 if (spec->use_alt_functions)
4424 ca0132_alt_select_out(spec->codec);
4425 else
4426 ca0132_select_out(spec->codec);
4427
d5c016b5 4428 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4429 if (jack) {
4430 jack->block_report = 0;
4431 snd_hda_jack_report_sync(spec->codec);
4432 }
993884f6
CCC		 4433}
4434
5aaca44d
IM		 4435static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4436static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
e0026d03
CM		 4437static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4438static int stop_mic1(struct hda_codec *codec);
4439static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4440static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4441
4442/*
4443 * Select the active VIP source
4444 */
4445static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4446{
4447 struct ca0132_spec *spec = codec->spec;
4448 unsigned int tmp;
4449
e8f1bd5d 4450 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4451 return 0;
4452
4453 /* if CrystalVoice if off, vipsource should be 0 */
4454 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4455 (val == 0)) {
4456 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4457 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4458 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4459 if (spec->cur_mic_type == DIGITAL_MIC)
4460 tmp = FLOAT_TWO;
4461 else
4462 tmp = FLOAT_ONE;
4463 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4464 tmp = FLOAT_ZERO;
4465 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4466 } else {
4467 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4468 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4469 if (spec->cur_mic_type == DIGITAL_MIC)
4470 tmp = FLOAT_TWO;
4471 else
4472 tmp = FLOAT_ONE;
4473 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4474 tmp = FLOAT_ONE;
4475 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4476 msleep(20);
4477 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4478 }
4479
4480 return 1;
4481}
4482
e0026d03
CM		 4483static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4484{
4485 struct ca0132_spec *spec = codec->spec;
4486 unsigned int tmp;
4487
4488 if (spec->dsp_state != DSP_DOWNLOADED)
4489 return 0;
4490
4491 codec_dbg(codec, "%s\n", __func__);
4492
4493 chipio_set_stream_control(codec, 0x03, 0);
4494 chipio_set_stream_control(codec, 0x04, 0);
4495
4496 /* if CrystalVoice is off, vipsource should be 0 */
4497 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4498 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4499 codec_dbg(codec, "%s: off.", __func__);
4500 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4501
4502 tmp = FLOAT_ZERO;
4503 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4504
4505 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4506 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4507 if (spec->quirk == QUIRK_R3DI)
4508 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4509
4510
4511 if (spec->in_enum_val == REAR_LINE_IN)
4512 tmp = FLOAT_ZERO;
4513 else {
4514 if (spec->quirk == QUIRK_SBZ)
4515 tmp = FLOAT_THREE;
4516 else
4517 tmp = FLOAT_ONE;
4518 }
4519
4520 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4521
4522 } else {
4523 codec_dbg(codec, "%s: on.", __func__);
4524 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4525 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4526 if (spec->quirk == QUIRK_R3DI)
4527 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4528
4529 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4530 tmp = FLOAT_TWO;
4531 else
4532 tmp = FLOAT_ONE;
4533 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4534
4535 tmp = FLOAT_ONE;
4536 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4537
4538 msleep(20);
4539 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4540 }
4541
4542 chipio_set_stream_control(codec, 0x03, 1);
4543 chipio_set_stream_control(codec, 0x04, 1);
4544
4545 return 1;
4546}
4547
5aaca44d
IM		 4548/*
4549 * Select the active microphone.
4550 * If autodetect is enabled, mic will be selected based on jack detection.
4551 * If jack inserted, ext.mic will be selected, else built-in mic
4552 * If autodetect is disabled, mic will be selected based on selection.
4553 */
4554static int ca0132_select_mic(struct hda_codec *codec)
4555{
4556 struct ca0132_spec *spec = codec->spec;
4557 int jack_present;
4558 int auto_jack;
4559
4e76a883 4560 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4561
664c7155 4562 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4563
4564 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4565
4566 if (auto_jack)
fe14f39e 4567 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4568 else
4569 jack_present =
4570 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4571
4572 if (jack_present)
4573 spec->cur_mic_type = LINE_MIC_IN;
4574 else
4575 spec->cur_mic_type = DIGITAL_MIC;
4576
4577 if (spec->cur_mic_type == DIGITAL_MIC) {
4578 /* enable digital Mic */
4579 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4580 ca0132_set_dmic(codec, 1);
4581 ca0132_mic_boost_set(codec, 0);
4582 /* set voice focus */
4583 ca0132_effects_set(codec, VOICE_FOCUS,
4584 spec->effects_switch
4585 [VOICE_FOCUS - EFFECT_START_NID]);
4586 } else {
4587 /* disable digital Mic */
4588 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4589 ca0132_set_dmic(codec, 0);
4590 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4591 /* disable voice focus */
4592 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4593 }
4594
664c7155 4595 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4596
4597 return 0;
4598}
4599
7cb9d94c
CM		 4600/*
4601 * Select the active input.
4602 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4603 * The front mic has no jack-detection, so the only way to switch to it
4604 * is to do it manually in alsamixer.
4605 */
4606static int ca0132_alt_select_in(struct hda_codec *codec)
4607{
4608 struct ca0132_spec *spec = codec->spec;
4609 unsigned int tmp;
4610
4611 codec_dbg(codec, "%s\n", __func__);
4612
4613 snd_hda_power_up_pm(codec);
4614
4615 chipio_set_stream_control(codec, 0x03, 0);
4616 chipio_set_stream_control(codec, 0x04, 0);
4617
4618 spec->cur_mic_type = spec->in_enum_val;
4619
4620 switch (spec->cur_mic_type) {
4621 case REAR_MIC:
4622 switch (spec->quirk) {
4623 case QUIRK_SBZ:
42aa3a16 4624 case QUIRK_R3D:
b9b41345 4625 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4626 tmp = FLOAT_THREE;
4627 break;
4628 case QUIRK_R3DI:
4629 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4630 tmp = FLOAT_ONE;
4631 break;
f231daaf
CM		 4632 case QUIRK_AE5:
4633 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4634 tmp = FLOAT_THREE;
4635 break;
7cb9d94c
CM		 4636 default:
4637 tmp = FLOAT_ONE;
4638 break;
4639 }
4640
4641 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4642 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4643 if (spec->quirk == QUIRK_R3DI)
4644 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4645
4646 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4647
4648 chipio_set_stream_control(codec, 0x03, 1);
4649 chipio_set_stream_control(codec, 0x04, 1);
f231daaf
CM		 4650 switch (spec->quirk) {
4651 case QUIRK_SBZ:
7cb9d94c
CM		 4652 chipio_write(codec, 0x18B098, 0x0000000C);
4653 chipio_write(codec, 0x18B09C, 0x0000000C);
f231daaf
CM		 4654 break;
4655 case QUIRK_AE5:
4656 chipio_write(codec, 0x18B098, 0x0000000C);
4657 chipio_write(codec, 0x18B09C, 0x0000004C);
4658 break;
7cb9d94c 4659 }
47cdf76e 4660 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4661 break;
4662 case REAR_LINE_IN:
4663 ca0132_mic_boost_set(codec, 0);
4664 switch (spec->quirk) {
4665 case QUIRK_SBZ:
42aa3a16 4666 case QUIRK_R3D:
b9b41345 4667 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4668 break;
4669 case QUIRK_R3DI:
4670 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4671 break;
f231daaf
CM		 4672 case QUIRK_AE5:
4673 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4674 break;
7cb9d94c
CM		 4675 }
4676
4677 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4678 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4679 if (spec->quirk == QUIRK_R3DI)
4680 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4681
4682 tmp = FLOAT_ZERO;
4683 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4684
f231daaf
CM		 4685 switch (spec->quirk) {
4686 case QUIRK_SBZ:
4687 case QUIRK_AE5:
7cb9d94c
CM		 4688 chipio_write(codec, 0x18B098, 0x00000000);
4689 chipio_write(codec, 0x18B09C, 0x00000000);
f231daaf 4690 break;
7cb9d94c 4691 }
7cb9d94c
CM		 4692 chipio_set_stream_control(codec, 0x03, 1);
4693 chipio_set_stream_control(codec, 0x04, 1);
4694 break;
4695 case FRONT_MIC:
4696 switch (spec->quirk) {
4697 case QUIRK_SBZ:
42aa3a16 4698 case QUIRK_R3D:
b9b41345
CM		 4699 ca0113_mmio_gpio_set(codec, 0, true);
4700 ca0113_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4701 tmp = FLOAT_THREE;
4702 break;
4703 case QUIRK_R3DI:
4704 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4705 tmp = FLOAT_ONE;
4706 break;
f231daaf
CM		 4707 case QUIRK_AE5:
4708 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f);
4709 tmp = FLOAT_THREE;
4710 break;
7cb9d94c
CM		 4711 default:
4712 tmp = FLOAT_ONE;
4713 break;
4714 }
4715
4716 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4717 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4718 if (spec->quirk == QUIRK_R3DI)
4719 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4720
4721 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4722
4723 chipio_set_stream_control(codec, 0x03, 1);
4724 chipio_set_stream_control(codec, 0x04, 1);
4725
f231daaf
CM		 4726 switch (spec->quirk) {
4727 case QUIRK_SBZ:
7cb9d94c
CM		 4728 chipio_write(codec, 0x18B098, 0x0000000C);
4729 chipio_write(codec, 0x18B09C, 0x000000CC);
f231daaf
CM		 4730 break;
4731 case QUIRK_AE5:
4732 chipio_write(codec, 0x18B098, 0x0000000C);
4733 chipio_write(codec, 0x18B09C, 0x0000004C);
4734 break;
7cb9d94c 4735 }
47cdf76e 4736 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4737 break;
4738 }
e0026d03 4739 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4740
4741 snd_hda_power_down_pm(codec);
4742 return 0;
7cb9d94c
CM		 4743}
4744
a7e76271
IM		 4745/*
4746 * Check if VNODE settings take effect immediately.
4747 */
4748static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4749 hda_nid_t vnid,
4750 hda_nid_t *shared_nid)
4751{
4752 struct ca0132_spec *spec = codec->spec;
4753 hda_nid_t nid;
a7e76271
IM		 4754
4755 switch (vnid) {
4756 case VNID_SPK:
4757 nid = spec->shared_out_nid;
a7e76271
IM		 4758 break;
4759 case VNID_MIC:
4760 nid = spec->shared_mic_nid;
a7e76271
IM		 4761 break;
4762 default:
9a0869f4 4763 return false;
a7e76271
IM		 4764 }
4765
9a0869f4 4766 if (shared_nid)
a7e76271
IM		 4767 *shared_nid = nid;
4768
9a0869f4 4769 return true;
a7e76271
IM		 4770}
4771
4772/*
4773* The following functions are control change helpers.
4774* They return 0 if no changed. Return 1 if changed.
4775*/
4776static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4777{
4778 struct ca0132_spec *spec = codec->spec;
4779 unsigned int tmp;
4780
4781 /* based on CrystalVoice state to enable VoiceFX. */
4782 if (enable) {
4783 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4784 FLOAT_ONE : FLOAT_ZERO;
4785 } else {
4786 tmp = FLOAT_ZERO;
4787 }
4788
4789 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4790 ca0132_voicefx.reqs[0], tmp);
4791
4792 return 1;
4793}
4794
5aaca44d
IM		 4795/*
4796 * Set the effects parameters
4797 */
4798static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4799{
4800 struct ca0132_spec *spec = codec->spec;
009b8f97 4801 unsigned int on, tmp;
5aaca44d
IM		 4802 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4803 int err = 0;
4804 int idx = nid - EFFECT_START_NID;
4805
4806 if ((idx < 0) || (idx >= num_fx))
4807 return 0; /* no changed */
4808
4809 /* for out effect, qualify with PE */
4810 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4811 /* if PE if off, turn off out effects. */
4812 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4813 val = 0;
8e6bc6b3
CM		 4814 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS)
4815 val = 0;
5aaca44d
IM		 4816 }
4817
4818 /* for in effect, qualify with CrystalVoice */
4819 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4820 /* if CrystalVoice if off, turn off in effects. */
4821 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4822 val = 0;
4823
4824 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4825 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4826 val = 0;
009b8f97
CM		 4827
4828 /* If Voice Focus on SBZ, set to two channel. */
7cb9d94c
CM		 4829 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4830 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4831 if (spec->effects_switch[CRYSTAL_VOICE -
4832 EFFECT_START_NID]) {
4833
4834 if (spec->effects_switch[VOICE_FOCUS -
4835 EFFECT_START_NID]) {
4836 tmp = FLOAT_TWO;
4837 val = 1;
4838 } else
4839 tmp = FLOAT_ONE;
4840
4841 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4842 }
4843 }
4844 /*
4845 * For SBZ noise reduction, there's an extra command
4846 * to module ID 0x47. No clue why.
4847 */
7cb9d94c
CM		 4848 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4849 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4850 if (spec->effects_switch[CRYSTAL_VOICE -
4851 EFFECT_START_NID]) {
4852 if (spec->effects_switch[NOISE_REDUCTION -
4853 EFFECT_START_NID])
4854 tmp = FLOAT_ONE;
4855 else
4856 tmp = FLOAT_ZERO;
4857 } else
4858 tmp = FLOAT_ZERO;
4859
4860 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4861 }
7cb9d94c
CM		 4862
4863 /* If rear line in disable effects. */
4864 if (spec->use_alt_functions &&
4865 spec->in_enum_val == REAR_LINE_IN)
4866 val = 0;
5aaca44d
IM		 4867 }
4868
4e76a883 4869 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4870 nid, val);
4871
4872 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4873 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4874 ca0132_effects[idx].reqs[0], on);
4875
4876 if (err < 0)
4877 return 0; /* no changed */
4878
4879 return 1;
4880}
4881
a7e76271
IM		 4882/*
4883 * Turn on/off Playback Enhancements
4884 */
4885static int ca0132_pe_switch_set(struct hda_codec *codec)
4886{
4887 struct ca0132_spec *spec = codec->spec;
4888 hda_nid_t nid;
4889 int i, ret = 0;
4890
4e76a883 4891 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4892 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4893
7cb9d94c
CM		 4894 if (spec->use_alt_functions)
4895 ca0132_alt_select_out(codec);
4896
a7e76271
IM		 4897 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4898 nid = OUT_EFFECT_START_NID;
4899 /* PE affects all out effects */
4900 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4901 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4902
4903 return ret;
4904}
4905
5aaca44d
IM		 4906/* Check if Mic1 is streaming, if so, stop streaming */
4907static int stop_mic1(struct hda_codec *codec)
4908{
4909 struct ca0132_spec *spec = codec->spec;
4910 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4911 AC_VERB_GET_CONV, 0);
4912 if (oldval != 0)
4913 snd_hda_codec_write(codec, spec->adcs[0], 0,
4914 AC_VERB_SET_CHANNEL_STREAMID,
4915 0);
4916 return oldval;
4917}
4918
4919/* Resume Mic1 streaming if it was stopped. */
4920static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4921{
4922 struct ca0132_spec *spec = codec->spec;
4923 /* Restore the previous stream and channel */
4924 if (oldval != 0)
4925 snd_hda_codec_write(codec, spec->adcs[0], 0,
4926 AC_VERB_SET_CHANNEL_STREAMID,
4927 oldval);
4928}
4929
4930/*
a7e76271 4931 * Turn on/off CrystalVoice
5aaca44d 4932 */
a7e76271
IM		 4933static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4934{
4935 struct ca0132_spec *spec = codec->spec;
4936 hda_nid_t nid;
4937 int i, ret = 0;
4938 unsigned int oldval;
4939
4e76a883 4940 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4941 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4942
4943 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4944 nid = IN_EFFECT_START_NID;
4945 /* CrystalVoice affects all in effects */
4946 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4947 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4948
4949 /* including VoiceFX */
4950 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4951
4952 /* set correct vipsource */
4953 oldval = stop_mic1(codec);
e0026d03
CM		 4954 if (spec->use_alt_functions)
4955 ret |= ca0132_alt_set_vipsource(codec, 1);
4956 else
4957 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 4958 resume_mic1(codec, oldval);
4959 return ret;
4960}
4961
5aaca44d
IM		 4962static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4963{
4964 struct ca0132_spec *spec = codec->spec;
4965 int ret = 0;
4966
4967 if (val) /* on */
4968 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4969 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4970 else /* off */
4971 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4972 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4973
4974 return ret;
4975}
4976
47cdf76e
CM		 4977static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4978{
4979 struct ca0132_spec *spec = codec->spec;
4980 int ret = 0;
4981
4982 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4983 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4984 return ret;
4985}
4986
212de2e7
CM		 4987static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
4988{
4989 unsigned int i;
4990
4991 for (i = 0; i < 4; i++)
4992 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
4993 ae5_headphone_gain_presets[val].vals[i]);
4994 return 0;
4995}
4996
a7e76271
IM		 4997static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4998 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 4999{
a7e76271
IM		 5000 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5001 hda_nid_t nid = get_amp_nid(kcontrol);
5002 hda_nid_t shared_nid = 0;
5003 bool effective;
5004 int ret = 0;
95c6e9cb 5005 struct ca0132_spec *spec = codec->spec;
a7e76271 5006 int auto_jack;
95c6e9cb 5007
a7e76271
IM		 5008 if (nid == VNID_HP_SEL) {
5009 auto_jack =
5010 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 5011 if (!auto_jack) {
5012 if (spec->use_alt_functions)
5013 ca0132_alt_select_out(codec);
5014 else
5015 ca0132_select_out(codec);
5016 }
a7e76271
IM		 5017 return 1;
5018 }
95c6e9cb 5019
a7e76271
IM		 5020 if (nid == VNID_AMIC1_SEL) {
5021 auto_jack =
5022 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5023 if (!auto_jack)
5024 ca0132_select_mic(codec);
5025 return 1;
5026 }
95c6e9cb 5027
a7e76271 5028 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 5029 if (spec->use_alt_functions)
5030 ca0132_alt_select_out(codec);
5031 else
5032 ca0132_select_out(codec);
a7e76271
IM		 5033 return 1;
5034 }
95c6e9cb 5035
a7e76271
IM		 5036 if (nid == VNID_AMIC1_ASEL) {
5037 ca0132_select_mic(codec);
5038 return 1;
95c6e9cb 5039 }
a7e76271
IM		 5040
5041 /* if effective conditions, then update hw immediately. */
5042 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5043 if (effective) {
5044 int dir = get_amp_direction(kcontrol);
5045 int ch = get_amp_channels(kcontrol);
5046 unsigned long pval;
5047
5048 mutex_lock(&codec->control_mutex);
5049 pval = kcontrol->private_value;
5050 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5051 0, dir);
5052 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5053 kcontrol->private_value = pval;
5054 mutex_unlock(&codec->control_mutex);
95c6e9cb 5055 }
95c6e9cb 5056
a7e76271 5057 return ret;
95c6e9cb 5058}
a7e76271 5059/* End of control change helpers. */
47cdf76e
CM		 5060/*
5061 * Below I've added controls to mess with the effect levels, I've only enabled
5062 * them on the Sound Blaster Z, but they would probably also work on the
5063 * Chromebook. I figured they were probably tuned specifically for it, and left
5064 * out for a reason.
5065 */
5066
5067/* Sets DSP effect level from the sliders above the controls */
5068static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5069 const unsigned int *lookup, int idx)
5070{
5071 int i = 0;
5072 unsigned int y;
5073 /*
5074 * For X_BASS, req 2 is actually crossover freq instead of
5075 * effect level
5076 */
5077 if (nid == X_BASS)
5078 y = 2;
5079 else
5080 y = 1;
5081
5082 snd_hda_power_up(codec);
5083 if (nid == XBASS_XOVER) {
5084 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5085 if (ca0132_effects[i].nid == X_BASS)
5086 break;
5087
5088 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5089 ca0132_effects[i].reqs[1],
5090 &(lookup[idx - 1]), sizeof(unsigned int));
5091 } else {
5092 /* Find the actual effect structure */
5093 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5094 if (nid == ca0132_effects[i].nid)
5095 break;
5096
5097 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5098 ca0132_effects[i].reqs[y],
5099 &(lookup[idx]), sizeof(unsigned int));
5100 }
5101
5102 snd_hda_power_down(codec);
5103
5104 return 0;
5105}
5106
5107static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5108 struct snd_ctl_elem_value *ucontrol)
5109{
5110 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5111 struct ca0132_spec *spec = codec->spec;
5112 long *valp = ucontrol->value.integer.value;
5113
5114 *valp = spec->xbass_xover_freq;
5115 return 0;
5116}
5117
5118static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5119 struct snd_ctl_elem_value *ucontrol)
5120{
5121 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5122 struct ca0132_spec *spec = codec->spec;
5123 hda_nid_t nid = get_amp_nid(kcontrol);
5124 long *valp = ucontrol->value.integer.value;
5125 int idx = nid - OUT_EFFECT_START_NID;
5126
5127 *valp = spec->fx_ctl_val[idx];
5128 return 0;
5129}
5130
5131/*
5132 * The X-bass crossover starts at 10hz, so the min is 1. The
5133 * frequency is set in multiples of 10.
5134 */
5135static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5136 struct snd_ctl_elem_info *uinfo)
5137{
5138 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5139 uinfo->count = 1;
5140 uinfo->value.integer.min = 1;
5141 uinfo->value.integer.max = 100;
5142 uinfo->value.integer.step = 1;
5143
5144 return 0;
5145}
5146
5147static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5148 struct snd_ctl_elem_info *uinfo)
5149{
5150 int chs = get_amp_channels(kcontrol);
5151
5152 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5153 uinfo->count = chs == 3 ? 2 : 1;
5154 uinfo->value.integer.min = 0;
5155 uinfo->value.integer.max = 100;
5156 uinfo->value.integer.step = 1;
5157
5158 return 0;
5159}
5160
5161static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5162 struct snd_ctl_elem_value *ucontrol)
5163{
5164 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5165 struct ca0132_spec *spec = codec->spec;
5166 hda_nid_t nid = get_amp_nid(kcontrol);
5167 long *valp = ucontrol->value.integer.value;
5168 int idx;
5169
5170 /* any change? */
5171 if (spec->xbass_xover_freq == *valp)
5172 return 0;
5173
5174 spec->xbass_xover_freq = *valp;
5175
5176 idx = *valp;
5177 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5178
5179 return 0;
5180}
5181
5182static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5183 struct snd_ctl_elem_value *ucontrol)
5184{
5185 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5186 struct ca0132_spec *spec = codec->spec;
5187 hda_nid_t nid = get_amp_nid(kcontrol);
5188 long *valp = ucontrol->value.integer.value;
5189 int idx;
5190
5191 idx = nid - EFFECT_START_NID;
5192 /* any change? */
5193 if (spec->fx_ctl_val[idx] == *valp)
5194 return 0;
5195
5196 spec->fx_ctl_val[idx] = *valp;
5197
5198 idx = *valp;
5199 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5200
5201 return 0;
5202}
5203
5204
5205/*
5206 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5207 * only has off or full 30 dB, and didn't like making a volume slider that has
5208 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5209 */
5210#define MIC_BOOST_NUM_OF_STEPS 4
5211#define MIC_BOOST_ENUM_MAX_STRLEN 10
5212
5213static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5214 struct snd_ctl_elem_info *uinfo)
5215{
5216 char *sfx = "dB";
5217 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5218
5219 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5220 uinfo->count = 1;
5221 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5222 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5223 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5224 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5225 strcpy(uinfo->value.enumerated.name, namestr);
5226 return 0;
5227}
5228
5229static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5230 struct snd_ctl_elem_value *ucontrol)
5231{
5232 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5233 struct ca0132_spec *spec = codec->spec;
5234
5235 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5236 return 0;
5237}
5238
5239static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5240 struct snd_ctl_elem_value *ucontrol)
5241{
5242 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5243 struct ca0132_spec *spec = codec->spec;
5244 int sel = ucontrol->value.enumerated.item[0];
5245 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5246
5247 if (sel >= items)
5248 return 0;
5249
5250 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5251 sel);
5252
5253 spec->mic_boost_enum_val = sel;
5254
5255 if (spec->in_enum_val != REAR_LINE_IN)
5256 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5257
5258 return 1;
5259}
5260
212de2e7
CM		 5261/*
5262 * Sound BlasterX AE-5 Headphone Gain Controls.
5263 */
5264#define AE5_HEADPHONE_GAIN_MAX 3
5265static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5266 struct snd_ctl_elem_info *uinfo)
5267{
5268 char *sfx = " Ohms)";
5269 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5270
5271 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5272 uinfo->count = 1;
5273 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5274 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5275 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5276 sprintf(namestr, "%s %s",
5277 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5278 sfx);
5279 strcpy(uinfo->value.enumerated.name, namestr);
5280 return 0;
5281}
5282
5283static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5284 struct snd_ctl_elem_value *ucontrol)
5285{
5286 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5287 struct ca0132_spec *spec = codec->spec;
5288
5289 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5290 return 0;
5291}
5292
5293static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5294 struct snd_ctl_elem_value *ucontrol)
5295{
5296 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5297 struct ca0132_spec *spec = codec->spec;
5298 int sel = ucontrol->value.enumerated.item[0];
5299 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5300
5301 if (sel >= items)
5302 return 0;
5303
5304 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5305 sel);
5306
5307 spec->ae5_headphone_gain_val = sel;
5308
5309 if (spec->out_enum_val == HEADPHONE_OUT)
5310 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5311
5312 return 1;
5313}
5314
5315/*
5316 * Sound BlasterX AE-5 sound filter enumerated control.
5317 */
5318#define AE5_SOUND_FILTER_MAX 3
5319
5320static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5321 struct snd_ctl_elem_info *uinfo)
5322{
5323 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5324
5325 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5326 uinfo->count = 1;
5327 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5328 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5329 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5330 sprintf(namestr, "%s",
5331 ae5_filter_presets[uinfo->value.enumerated.item].name);
5332 strcpy(uinfo->value.enumerated.name, namestr);
5333 return 0;
5334}
5335
5336static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5337 struct snd_ctl_elem_value *ucontrol)
5338{
5339 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5340 struct ca0132_spec *spec = codec->spec;
5341
5342 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5343 return 0;
5344}
5345
5346static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5347 struct snd_ctl_elem_value *ucontrol)
5348{
5349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5350 struct ca0132_spec *spec = codec->spec;
5351 int sel = ucontrol->value.enumerated.item[0];
5352 unsigned int items = AE5_SOUND_FILTER_MAX;
5353
5354 if (sel >= items)
5355 return 0;
5356
5357 codec_dbg(codec, "ae5_sound_filter: %s\n",
5358 ae5_filter_presets[sel].name);
5359
5360 spec->ae5_filter_val = sel;
5361
5362 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5363 ae5_filter_presets[sel].val);
5364
5365 return 1;
5366}
95c6e9cb 5367
7cb9d94c
CM		 5368/*
5369 * Input Select Control for alternative ca0132 codecs. This exists because
5370 * front microphone has no auto-detect, and we need a way to set the rear
5371 * as line-in
5372 */
5373static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5374 struct snd_ctl_elem_info *uinfo)
5375{
5376 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5377 uinfo->count = 1;
5378 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5379 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5380 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5381 strcpy(uinfo->value.enumerated.name,
5382 in_src_str[uinfo->value.enumerated.item]);
5383 return 0;
5384}
5385
5386static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5387 struct snd_ctl_elem_value *ucontrol)
5388{
5389 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5390 struct ca0132_spec *spec = codec->spec;
5391
5392 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5393 return 0;
5394}
5395
5396static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5397 struct snd_ctl_elem_value *ucontrol)
5398{
5399 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5400 struct ca0132_spec *spec = codec->spec;
5401 int sel = ucontrol->value.enumerated.item[0];
5402 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5403
5404 if (sel >= items)
5405 return 0;
5406
5407 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5408 sel, in_src_str[sel]);
5409
5410 spec->in_enum_val = sel;
5411
5412 ca0132_alt_select_in(codec);
5413
5414 return 1;
5415}
5416
5417/* Sound Blaster Z Output Select Control */
5418static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5419 struct snd_ctl_elem_info *uinfo)
5420{
5421 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5422 uinfo->count = 1;
5423 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5424 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5425 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5426 strcpy(uinfo->value.enumerated.name,
5427 alt_out_presets[uinfo->value.enumerated.item].name);
5428 return 0;
5429}
5430
5431static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5432 struct snd_ctl_elem_value *ucontrol)
5433{
5434 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5435 struct ca0132_spec *spec = codec->spec;
5436
5437 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5438 return 0;
5439}
5440
5441static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5442 struct snd_ctl_elem_value *ucontrol)
5443{
5444 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5445 struct ca0132_spec *spec = codec->spec;
5446 int sel = ucontrol->value.enumerated.item[0];
5447 unsigned int items = NUM_OF_OUTPUTS;
5448 unsigned int auto_jack;
5449
5450 if (sel >= items)
5451 return 0;
5452
5453 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5454 sel, alt_out_presets[sel].name);
5455
5456 spec->out_enum_val = sel;
5457
5458 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5459
5460 if (!auto_jack)
5461 ca0132_alt_select_out(codec);
5462
5463 return 1;
5464}
5465
47cdf76e
CM		 5466/*
5467 * Smart Volume output setting control. Three different settings, Normal,
5468 * which takes the value from the smart volume slider. The two others, loud
5469 * and night, disregard the slider value and have uneditable values.
5470 */
5471#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5472static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5473
5474static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5475 struct snd_ctl_elem_info *uinfo)
5476{
5477 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5478 uinfo->count = 1;
5479 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5480 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5481 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5482 strcpy(uinfo->value.enumerated.name,
5483 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5484 return 0;
5485}
5486
5487static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5488 struct snd_ctl_elem_value *ucontrol)
5489{
5490 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5491 struct ca0132_spec *spec = codec->spec;
5492
5493 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5494 return 0;
5495}
5496
5497static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5498 struct snd_ctl_elem_value *ucontrol)
5499{
5500 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5501 struct ca0132_spec *spec = codec->spec;
5502 int sel = ucontrol->value.enumerated.item[0];
5503 unsigned int items = NUM_OF_SVM_SETTINGS;
5504 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5505 unsigned int tmp;
5506
5507 if (sel >= items)
5508 return 0;
5509
5510 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5511 sel, out_svm_set_enum_str[sel]);
5512
5513 spec->smart_volume_setting = sel;
5514
5515 switch (sel) {
5516 case 0:
5517 tmp = FLOAT_ZERO;
5518 break;
5519 case 1:
5520 tmp = FLOAT_ONE;
5521 break;
5522 case 2:
5523 tmp = FLOAT_TWO;
5524 break;
5525 default:
5526 tmp = FLOAT_ZERO;
5527 break;
5528 }
5529 /* Req 2 is the Smart Volume Setting req. */
5530 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5531 ca0132_effects[idx].reqs[2], tmp);
5532 return 1;
5533}
5534
5535/* Sound Blaster Z EQ preset controls */
5536static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5537 struct snd_ctl_elem_info *uinfo)
5538{
c5f13d75 5539 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5540
5541 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5542 uinfo->count = 1;
5543 uinfo->value.enumerated.items = items;
5544 if (uinfo->value.enumerated.item >= items)
5545 uinfo->value.enumerated.item = items - 1;
5546 strcpy(uinfo->value.enumerated.name,
5547 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5548 return 0;
5549}
5550
5551static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5552 struct snd_ctl_elem_value *ucontrol)
5553{
5554 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5555 struct ca0132_spec *spec = codec->spec;
5556
5557 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5558 return 0;
5559}
5560
5561static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5562 struct snd_ctl_elem_value *ucontrol)
5563{
5564 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5565 struct ca0132_spec *spec = codec->spec;
5566 int i, err = 0;
5567 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5568 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5569
5570 if (sel >= items)
5571 return 0;
5572
5573 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5574 ca0132_alt_eq_presets[sel].name);
5575 /*
5576 * Idx 0 is default.
5577 * Default needs to qualify with CrystalVoice state.
5578 */
5579 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5580 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5581 ca0132_alt_eq_enum.reqs[i],
5582 ca0132_alt_eq_presets[sel].vals[i]);
5583 if (err < 0)
5584 break;
5585 }
5586
5587 if (err >= 0)
5588 spec->eq_preset_val = sel;
5589
5590 return 1;
5591}
5592
a7e76271
IM		 5593static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5594 struct snd_ctl_elem_info *uinfo)
5595{
a9291f46 5596 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5597
5598 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5599 uinfo->count = 1;
5600 uinfo->value.enumerated.items = items;
5601 if (uinfo->value.enumerated.item >= items)
5602 uinfo->value.enumerated.item = items - 1;
5603 strcpy(uinfo->value.enumerated.name,
5604 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5605 return 0;
5606}
95c6e9cb 5607
a7e76271 5608static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5609 struct snd_ctl_elem_value *ucontrol)
5610{
5611 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5612 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5613
a7e76271 5614 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5615 return 0;
5616}
5617
a7e76271 5618static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5619 struct snd_ctl_elem_value *ucontrol)
5620{
5621 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5622 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5623 int i, err = 0;
5624 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5625
a9291f46 5626 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5627 return 0;
5628
4e76a883 5629 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5630 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5631
a7e76271
IM		 5632 /*
5633 * Idx 0 is default.
5634 * Default needs to qualify with CrystalVoice state.
5635 */
5636 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5637 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5638 ca0132_voicefx.reqs[i],
5639 ca0132_voicefx_presets[sel].vals[i]);
5640 if (err < 0)
5641 break;
5642 }
95c6e9cb 5643
a7e76271
IM		 5644 if (err >= 0) {
5645 spec->voicefx_val = sel;
5646 /* enable voice fx */
5647 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5648 }
95c6e9cb 5649
a7e76271 5650 return 1;
95c6e9cb
IM		 5651}
5652
a7e76271
IM		 5653static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5654 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5655{
5656 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5657 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5658 hda_nid_t nid = get_amp_nid(kcontrol);
5659 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5660 long *valp = ucontrol->value.integer.value;
5661
a7e76271
IM		 5662 /* vnode */
5663 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5664 if (ch & 1) {
5665 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5666 valp++;
5667 }
5668 if (ch & 2) {
5669 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5670 valp++;
5671 }
5672 return 0;
5673 }
5674
5675 /* effects, include PE and CrystalVoice */
5676 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5677 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5678 return 0;
5679 }
5680
5681 /* mic boost */
5682 if (nid == spec->input_pins[0]) {
5683 *valp = spec->cur_mic_boost;
5684 return 0;
5685 }
5686
95c6e9cb
IM		 5687 return 0;
5688}
5689
a7e76271
IM		 5690static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5691 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5692{
5693 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5694 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5695 hda_nid_t nid = get_amp_nid(kcontrol);
5696 int ch = get_amp_channels(kcontrol);
95c6e9cb 5697 long *valp = ucontrol->value.integer.value;
a7e76271 5698 int changed = 1;
95c6e9cb 5699
4e76a883 5700 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5701 nid, *valp);
95c6e9cb
IM		 5702
5703 snd_hda_power_up(codec);
a7e76271
IM		 5704 /* vnode */
5705 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5706 if (ch & 1) {
5707 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5708 valp++;
5709 }
5710 if (ch & 2) {
5711 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5712 valp++;
5713 }
5714 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5715 goto exit;
5716 }
95c6e9cb 5717
a7e76271
IM		 5718 /* PE */
5719 if (nid == PLAY_ENHANCEMENT) {
5720 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5721 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5722 goto exit;
a7e76271 5723 }
95c6e9cb 5724
a7e76271
IM		 5725 /* CrystalVoice */
5726 if (nid == CRYSTAL_VOICE) {
5727 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5728 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5729 goto exit;
a7e76271 5730 }
95c6e9cb 5731
a7e76271
IM		 5732 /* out and in effects */
5733 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5734 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5735 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5736 changed = ca0132_effects_set(codec, nid, *valp);
5737 goto exit;
5738 }
5739
5740 /* mic boost */
5741 if (nid == spec->input_pins[0]) {
5742 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 5743 if (spec->use_alt_functions) {
5744 if (spec->in_enum_val != REAR_LINE_IN)
5745 changed = ca0132_mic_boost_set(codec, *valp);
5746 } else {
5747 /* Mic boost does not apply to Digital Mic */
5748 if (spec->cur_mic_type != DIGITAL_MIC)
5749 changed = ca0132_mic_boost_set(codec, *valp);
5750 }
a7e76271 5751
a7e76271
IM		 5752 goto exit;
5753 }
95c6e9cb 5754
a7e76271 5755exit:
95c6e9cb 5756 snd_hda_power_down(codec);
a7e76271 5757 return changed;
95c6e9cb
IM		 5758}
5759
a7e76271
IM		 5760/*
5761 * Volume related
5762 */
017310fb
CM		 5763/*
5764 * Sets the internal DSP decibel level to match the DAC for output, and the
5765 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5766 * all alternative codecs set DSP playback volume.
5767 */
5768static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5769{
5770 struct ca0132_spec *spec = codec->spec;
5771 unsigned int dsp_dir;
5772 unsigned int lookup_val;
5773
5774 if (nid == VNID_SPK)
5775 dsp_dir = DSP_VOL_OUT;
5776 else
5777 dsp_dir = DSP_VOL_IN;
5778
5779 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5780
5781 dspio_set_uint_param(codec,
5782 ca0132_alt_vol_ctls[dsp_dir].mid,
5783 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5784 float_vol_db_lookup[lookup_val]);
5785
5786 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5787
5788 dspio_set_uint_param(codec,
5789 ca0132_alt_vol_ctls[dsp_dir].mid,
5790 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5791 float_vol_db_lookup[lookup_val]);
5792
5793 dspio_set_uint_param(codec,
5794 ca0132_alt_vol_ctls[dsp_dir].mid,
5795 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5796}
5797
a7e76271
IM		 5798static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5799 struct snd_ctl_elem_info *uinfo)
5800{
5801 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5802 struct ca0132_spec *spec = codec->spec;
5803 hda_nid_t nid = get_amp_nid(kcontrol);
5804 int ch = get_amp_channels(kcontrol);
5805 int dir = get_amp_direction(kcontrol);
5806 unsigned long pval;
5807 int err;
5808
5809 switch (nid) {
5810 case VNID_SPK:
5811 /* follow shared_out info */
5812 nid = spec->shared_out_nid;
5813 mutex_lock(&codec->control_mutex);
5814 pval = kcontrol->private_value;
5815 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5816 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5817 kcontrol->private_value = pval;
5818 mutex_unlock(&codec->control_mutex);
5819 break;
5820 case VNID_MIC:
5821 /* follow shared_mic info */
5822 nid = spec->shared_mic_nid;
5823 mutex_lock(&codec->control_mutex);
5824 pval = kcontrol->private_value;
5825 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5826 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5827 kcontrol->private_value = pval;
5828 mutex_unlock(&codec->control_mutex);
5829 break;
5830 default:
5831 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5832 }
5833 return err;
5834}
5835
5836static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5837 struct snd_ctl_elem_value *ucontrol)
5838{
5839 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5840 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5841 hda_nid_t nid = get_amp_nid(kcontrol);
5842 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5843 long *valp = ucontrol->value.integer.value;
5844
a7e76271
IM		 5845 /* store the left and right volume */
5846 if (ch & 1) {
5847 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5848 valp++;
5849 }
5850 if (ch & 2) {
5851 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5852 valp++;
5853 }
95c6e9cb
IM		 5854 return 0;
5855}
5856
a7e76271 5857static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5858 struct snd_ctl_elem_value *ucontrol)
5859{
5860 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5861 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5862 hda_nid_t nid = get_amp_nid(kcontrol);
5863 int ch = get_amp_channels(kcontrol);
95c6e9cb 5864 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5865 hda_nid_t shared_nid = 0;
5866 bool effective;
5867 int changed = 1;
5868
5869 /* store the left and right volume */
5870 if (ch & 1) {
5871 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5872 valp++;
5873 }
5874 if (ch & 2) {
5875 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5876 valp++;
5877 }
95c6e9cb 5878
a7e76271
IM		 5879 /* if effective conditions, then update hw immediately. */
5880 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5881 if (effective) {
5882 int dir = get_amp_direction(kcontrol);
5883 unsigned long pval;
5884
5885 snd_hda_power_up(codec);
5886 mutex_lock(&codec->control_mutex);
5887 pval = kcontrol->private_value;
5888 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5889 0, dir);
5890 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5891 kcontrol->private_value = pval;
5892 mutex_unlock(&codec->control_mutex);
5893 snd_hda_power_down(codec);
5894 }
95c6e9cb 5895
a7e76271 5896 return changed;
95c6e9cb
IM		 5897}
5898
017310fb
CM		 5899/*
5900 * This function is the same as the one above, because using an if statement
5901 * inside of the above volume control for the DSP volume would cause too much
5902 * lag. This is a lot more smooth.
5903 */
5904static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5905 struct snd_ctl_elem_value *ucontrol)
5906{
5907 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5908 struct ca0132_spec *spec = codec->spec;
5909 hda_nid_t nid = get_amp_nid(kcontrol);
5910 int ch = get_amp_channels(kcontrol);
5911 long *valp = ucontrol->value.integer.value;
5912 hda_nid_t vnid = 0;
5913 int changed = 1;
5914
5915 switch (nid) {
5916 case 0x02:
5917 vnid = VNID_SPK;
5918 break;
5919 case 0x07:
5920 vnid = VNID_MIC;
5921 break;
5922 }
5923
5924 /* store the left and right volume */
5925 if (ch & 1) {
5926 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5927 valp++;
5928 }
5929 if (ch & 2) {
5930 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5931 valp++;
5932 }
5933
5934 snd_hda_power_up(codec);
5935 ca0132_alt_dsp_volume_put(codec, vnid);
5936 mutex_lock(&codec->control_mutex);
5937 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5938 mutex_unlock(&codec->control_mutex);
5939 snd_hda_power_down(codec);
5940
5941 return changed;
5942}
5943
a7e76271
IM		 5944static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5945 unsigned int size, unsigned int __user *tlv)
95c6e9cb 5946{
a7e76271
IM		 5947 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5948 struct ca0132_spec *spec = codec->spec;
5949 hda_nid_t nid = get_amp_nid(kcontrol);
5950 int ch = get_amp_channels(kcontrol);
5951 int dir = get_amp_direction(kcontrol);
5952 unsigned long pval;
5953 int err;
5954
5955 switch (nid) {
5956 case VNID_SPK:
5957 /* follow shared_out tlv */
5958 nid = spec->shared_out_nid;
5959 mutex_lock(&codec->control_mutex);
5960 pval = kcontrol->private_value;
5961 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5962 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5963 kcontrol->private_value = pval;
5964 mutex_unlock(&codec->control_mutex);
5965 break;
5966 case VNID_MIC:
5967 /* follow shared_mic tlv */
5968 nid = spec->shared_mic_nid;
5969 mutex_lock(&codec->control_mutex);
5970 pval = kcontrol->private_value;
5971 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5972 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5973 kcontrol->private_value = pval;
5974 mutex_unlock(&codec->control_mutex);
5975 break;
5976 default:
5977 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5978 }
5979 return err;
95c6e9cb
IM		 5980}
5981
47cdf76e
CM		 5982/* Add volume slider control for effect level */
5983static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5984 const char *pfx, int dir)
5985{
47cdf76e
CM		 5986 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5987 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5988 struct snd_kcontrol_new knew =
5989 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5990
0cc1aa71 5991 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 5992
bb86124c 5993 knew.tlv.c = NULL;
47cdf76e
CM		 5994
5995 switch (nid) {
5996 case XBASS_XOVER:
5997 knew.info = ca0132_alt_xbass_xover_slider_info;
5998 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5999 knew.put = ca0132_alt_xbass_xover_slider_put;
6000 break;
6001 default:
6002 knew.info = ca0132_alt_effect_slider_info;
6003 knew.get = ca0132_alt_slider_ctl_get;
6004 knew.put = ca0132_alt_effect_slider_put;
6005 knew.private_value =
6006 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6007 break;
6008 }
6009
6010 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6011}
6012
6013/*
6014 * Added FX: prefix for the alternative codecs, because otherwise the surround
6015 * effect would conflict with the Surround sound volume control. Also seems more
6016 * clear as to what the switches do. Left alone for others.
6017 */
a7e76271
IM		 6018static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6019 const char *pfx, int dir)
95c6e9cb 6020{
47cdf76e 6021 struct ca0132_spec *spec = codec->spec;
975cc02a 6022 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 6023 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 6024 struct snd_kcontrol_new knew =
a7e76271 6025 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 6026 /* If using alt_controls, add FX: prefix. But, don't add FX:
6027 * prefix to OutFX or InFX enable controls.
6028 */
6029 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 6030 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 6031 else
6032 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6033
95c6e9cb
IM		 6034 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6035}
6036
a7e76271 6037static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 6038{
6039 struct snd_kcontrol_new knew =
a7e76271
IM		 6040 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6041 VOICEFX, 1, 0, HDA_INPUT);
6042 knew.info = ca0132_voicefx_info;
6043 knew.get = ca0132_voicefx_get;
6044 knew.put = ca0132_voicefx_put;
6045 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 6046}
6047
47cdf76e
CM		 6048/* Create the EQ Preset control */
6049static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6050{
6051 struct snd_kcontrol_new knew =
6052 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6053 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6054 knew.info = ca0132_alt_eq_preset_info;
6055 knew.get = ca0132_alt_eq_preset_get;
6056 knew.put = ca0132_alt_eq_preset_put;
6057 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6058 snd_ctl_new1(&knew, codec));
6059}
6060
6061/*
6062 * Add enumerated control for the three different settings of the smart volume
6063 * output effect. Normal just uses the slider value, and loud and night are
6064 * their own things that ignore that value.
6065 */
6066static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6067{
6068 struct snd_kcontrol_new knew =
6069 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6070 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6071 knew.info = ca0132_alt_svm_setting_info;
6072 knew.get = ca0132_alt_svm_setting_get;
6073 knew.put = ca0132_alt_svm_setting_put;
6074 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6075 snd_ctl_new1(&knew, codec));
6076
6077}
6078
7cb9d94c
CM		 6079/*
6080 * Create an Output Select enumerated control for codecs with surround
6081 * out capabilities.
6082 */
6083static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6084{
6085 struct snd_kcontrol_new knew =
6086 HDA_CODEC_MUTE_MONO("Output Select",
6087 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6088 knew.info = ca0132_alt_output_select_get_info;
6089 knew.get = ca0132_alt_output_select_get;
6090 knew.put = ca0132_alt_output_select_put;
6091 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6092 snd_ctl_new1(&knew, codec));
6093}
6094
6095/*
6096 * Create an Input Source enumerated control for the alternate ca0132 codecs
6097 * because the front microphone has no auto-detect, and Line-in has to be set
6098 * somehow.
6099 */
6100static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6101{
6102 struct snd_kcontrol_new knew =
6103 HDA_CODEC_MUTE_MONO("Input Source",
6104 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6105 knew.info = ca0132_alt_input_source_info;
6106 knew.get = ca0132_alt_input_source_get;
6107 knew.put = ca0132_alt_input_source_put;
6108 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6109 snd_ctl_new1(&knew, codec));
6110}
6111
47cdf76e
CM		 6112/*
6113 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6114 * more control than the original mic boost, which is either full 30dB or off.
6115 */
6116static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6117{
6118 struct snd_kcontrol_new knew =
6119 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6120 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6121 knew.info = ca0132_alt_mic_boost_info;
6122 knew.get = ca0132_alt_mic_boost_get;
6123 knew.put = ca0132_alt_mic_boost_put;
6124 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6125 snd_ctl_new1(&knew, codec));
6126
6127}
6128
212de2e7
CM		 6129/*
6130 * Add headphone gain enumerated control for the AE-5. This switches between
6131 * three modes, low, medium, and high. When non-headphone outputs are selected,
6132 * it is automatically set to high. This is the same behavior as Windows.
6133 */
6134static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6135{
6136 struct snd_kcontrol_new knew =
6137 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
4b432ad4 6138 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6139 knew.info = ae5_headphone_gain_info;
6140 knew.get = ae5_headphone_gain_get;
6141 knew.put = ae5_headphone_gain_put;
6142 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6143 snd_ctl_new1(&knew, codec));
6144}
6145
6146/*
6147 * Add sound filter enumerated control for the AE-5. This adds three different
6148 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6149 * read into it, it changes the DAC's interpolation filter.
6150 */
6151static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6152{
6153 struct snd_kcontrol_new knew =
6154 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
4b432ad4 6155 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6156 knew.info = ae5_sound_filter_info;
6157 knew.get = ae5_sound_filter_get;
6158 knew.put = ae5_sound_filter_put;
6159 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6160 snd_ctl_new1(&knew, codec));
6161}
6162
47cdf76e
CM		 6163/*
6164 * Need to create slave controls for the alternate codecs that have surround
6165 * capabilities.
6166 */
6167static const char * const ca0132_alt_slave_pfxs[] = {
6168 "Front", "Surround", "Center", "LFE", NULL,
6169};
6170
6171/*
6172 * Also need special channel map, because the default one is incorrect.
6173 * I think this has to do with the pin for rear surround being 0x11,
6174 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6175 */
9c4a665e 6176static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 6177 { .channels = 2,
6178 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6179 { .channels = 4,
6180 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6181 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6182 { .channels = 6,
6183 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6184 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6185 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6186 { }
6187};
6188
6189/* Add the correct chmap for streams with 6 channels. */
6190static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6191{
6192 int err = 0;
6193 struct hda_pcm *pcm;
6194
6195 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6196 struct hda_pcm_stream *hinfo =
6197 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6198 struct snd_pcm_chmap *chmap;
6199 const struct snd_pcm_chmap_elem *elem;
6200
6201 elem = ca0132_alt_chmaps;
6202 if (hinfo->channels_max == 6) {
6203 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6204 SNDRV_PCM_STREAM_PLAYBACK,
6205 elem, hinfo->channels_max, 0, &chmap);
6206 if (err < 0)
6207 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6208 }
6209 }
6210}
6211
a7e76271
IM		 6212/*
6213 * When changing Node IDs for Mixer Controls below, make sure to update
6214 * Node IDs in ca0132_config() as well.
6215 */
b0eaa072 6216static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 6217 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6218 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6219 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6220 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6221 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6222 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6223 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6224 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6225 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6226 0x12, 1, HDA_INPUT),
6227 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6228 VNID_HP_SEL, 1, HDA_OUTPUT),
6229 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6230 VNID_AMIC1_SEL, 1, HDA_INPUT),
6231 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6232 VNID_HP_ASEL, 1, HDA_OUTPUT),
6233 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6234 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6235 { } /* end */
6236};
6237
017310fb 6238/*
e25e3445
CM		 6239 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6240 * surround controls. Also sets both the Front Playback and Capture Volume
6241 * controls to alt so they set the DSP's decibel level.
017310fb 6242 */
e25e3445 6243static const struct snd_kcontrol_new desktop_mixer[] = {
017310fb
CM		 6244 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6245 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6246 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6247 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6248 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6249 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6250 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6251 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6252 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6253 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6254 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6255 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6256 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6257 VNID_HP_ASEL, 1, HDA_OUTPUT),
6258 { } /* end */
6259};
6260
6261/*
6262 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6263 * because it doesn't set decibel levels for the DSP for capture.
6264 */
b0eaa072 6265static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 6266 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6267 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6268 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6269 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6270 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6271 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6272 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6273 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6274 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6275 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6276 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6277 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6278 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6279 VNID_HP_ASEL, 1, HDA_OUTPUT),
6280 { } /* end */
6281};
6282
e90f29e4
IM		 6283static int ca0132_build_controls(struct hda_codec *codec)
6284{
6285 struct ca0132_spec *spec = codec->spec;
47cdf76e 6286 int i, num_fx, num_sliders;
e90f29e4
IM		 6287 int err = 0;
6288
6289 /* Add Mixer controls */
6290 for (i = 0; i < spec->num_mixers; i++) {
6291 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6292 if (err < 0)
6293 return err;
6294 }
47cdf76e
CM		 6295 /* Setup vmaster with surround slaves for desktop ca0132 devices */
6296 if (spec->use_alt_functions) {
6297 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6298 spec->tlv);
6299 snd_hda_add_vmaster(codec, "Master Playback Volume",
6300 spec->tlv, ca0132_alt_slave_pfxs,
6301 "Playback Volume");
6302 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6303 NULL, ca0132_alt_slave_pfxs,
6304 "Playback Switch",
6305 true, &spec->vmaster_mute.sw_kctl);
6306
6307 }
e90f29e4
IM		 6308
6309 /* Add in and out effects controls.
6310 * VoiceFX, PE and CrystalVoice are added separately.
6311 */
6312 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6313 for (i = 0; i < num_fx; i++) {
e25e3445
CM		 6314 /* SBZ and R3D break if Echo Cancellation is used. */
6315 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D) {
47cdf76e
CM		 6316 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6317 OUT_EFFECTS_COUNT))
6318 continue;
6319 }
6320
e90f29e4
IM		 6321 err = add_fx_switch(codec, ca0132_effects[i].nid,
6322 ca0132_effects[i].name,
6323 ca0132_effects[i].direct);
6324 if (err < 0)
6325 return err;
6326 }
47cdf76e
CM		 6327 /*
6328 * If codec has use_alt_controls set to true, add effect level sliders,
6329 * EQ presets, and Smart Volume presets. Also, change names to add FX
6330 * prefix, and change PlayEnhancement and CrystalVoice to match.
6331 */
6332 if (spec->use_alt_controls) {
6333 ca0132_alt_add_svm_enum(codec);
6334 add_ca0132_alt_eq_presets(codec);
6335 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6336 "Enable OutFX", 0);
6337 if (err < 0)
6338 return err;
e90f29e4 6339
47cdf76e
CM		 6340 err = add_fx_switch(codec, CRYSTAL_VOICE,
6341 "Enable InFX", 1);
6342 if (err < 0)
6343 return err;
e90f29e4 6344
47cdf76e
CM		 6345 num_sliders = OUT_EFFECTS_COUNT - 1;
6346 for (i = 0; i < num_sliders; i++) {
6347 err = ca0132_alt_add_effect_slider(codec,
6348 ca0132_effects[i].nid,
6349 ca0132_effects[i].name,
6350 ca0132_effects[i].direct);
6351 if (err < 0)
6352 return err;
6353 }
6354
6355 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6356 "X-Bass Crossover", EFX_DIR_OUT);
6357
6358 if (err < 0)
6359 return err;
6360 } else {
6361 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6362 "PlayEnhancement", 0);
6363 if (err < 0)
6364 return err;
e90f29e4 6365
47cdf76e
CM		 6366 err = add_fx_switch(codec, CRYSTAL_VOICE,
6367 "CrystalVoice", 1);
6368 if (err < 0)
6369 return err;
6370 }
e90f29e4
IM		 6371 add_voicefx(codec);
6372
7cb9d94c
CM		 6373 /*
6374 * If the codec uses alt_functions, you need the enumerated controls
6375 * to select the new outputs and inputs, plus add the new mic boost
6376 * setting control.
6377 */
6378 if (spec->use_alt_functions) {
6379 ca0132_alt_add_output_enum(codec);
6380 ca0132_alt_add_input_enum(codec);
47cdf76e 6381 ca0132_alt_add_mic_boost_enum(codec);
7cb9d94c 6382 }
212de2e7
CM		 6383
6384 if (spec->quirk == QUIRK_AE5) {
6385 ae5_add_headphone_gain_enum(codec);
6386 ae5_add_sound_filter_enum(codec);
6387 }
e90f29e4
IM		 6388#ifdef ENABLE_TUNING_CONTROLS
6389 add_tuning_ctls(codec);
6390#endif
6391
6392 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6393 if (err < 0)
6394 return err;
6395
6396 if (spec->dig_out) {
6397 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6398 spec->dig_out);
6399 if (err < 0)
6400 return err;
6401 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6402 if (err < 0)
6403 return err;
6404 /* spec->multiout.share_spdif = 1; */
6405 }
6406
6407 if (spec->dig_in) {
6408 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6409 if (err < 0)
6410 return err;
6411 }
47cdf76e
CM		 6412
6413 if (spec->use_alt_functions)
6414 ca0132_alt_add_chmap_ctls(codec);
6415
e90f29e4
IM		 6416 return 0;
6417}
6418
7675a2a9
CM		 6419static int dbpro_build_controls(struct hda_codec *codec)
6420{
6421 struct ca0132_spec *spec = codec->spec;
6422 int err = 0;
6423
6424 if (spec->dig_out) {
6425 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6426 spec->dig_out);
6427 if (err < 0)
6428 return err;
6429 }
6430
6431 if (spec->dig_in) {
6432 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6433 if (err < 0)
6434 return err;
6435 }
6436
6437 return 0;
6438}
6439
a7e76271 6440/*
e90f29e4 6441 * PCM
a7e76271 6442 */
071f1344 6443static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 6444 .substreams = 1,
6445 .channels_min = 2,
825315bc 6446 .channels_max = 6,
a7e76271 6447 .ops = {
a7e76271 6448 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 6449 .cleanup = ca0132_playback_pcm_cleanup,
6450 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 6451 },
6452};
6453
071f1344 6454static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 6455 .substreams = 1,
6456 .channels_min = 2,
6457 .channels_max = 2,
825315bc
IM		 6458 .ops = {
6459 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 6460 .cleanup = ca0132_capture_pcm_cleanup,
6461 .get_delay = ca0132_capture_pcm_delay,
825315bc 6462 },
a7e76271
IM		 6463};
6464
071f1344 6465static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 6466 .substreams = 1,
6467 .channels_min = 2,
6468 .channels_max = 2,
6469 .ops = {
6470 .open = ca0132_dig_playback_pcm_open,
6471 .close = ca0132_dig_playback_pcm_close,
6472 .prepare = ca0132_dig_playback_pcm_prepare,
6473 .cleanup = ca0132_dig_playback_pcm_cleanup
6474 },
6475};
6476
071f1344 6477static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 6478 .substreams = 1,
6479 .channels_min = 2,
6480 .channels_max = 2,
6481};
6482
6483static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 6484{
6485 struct ca0132_spec *spec = codec->spec;
bbbc7e85 6486 struct hda_pcm *info;
a7e76271 6487
bbbc7e85
TI		 6488 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6489 if (!info)
6490 return -ENOMEM;
47cdf76e
CM		 6491 if (spec->use_alt_functions) {
6492 info->own_chmap = true;
6493 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6494 = ca0132_alt_chmaps;
6495 }
a7e76271
IM		 6496 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6497 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6498 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6499 spec->multiout.max_channels;
6500 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 6501 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 6502 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 6503
009b8f97 6504 /* With the DSP enabled, desktops don't use this ADC. */
5f8ddc6e 6505 if (!spec->use_alt_functions) {
009b8f97
CM		 6506 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6507 if (!info)
6508 return -ENOMEM;
6509 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6510 ca0132_pcm_analog_capture;
6511 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6512 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6513 }
825315bc 6514
bbbc7e85
TI		 6515 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6516 if (!info)
6517 return -ENOMEM;
825315bc
IM		 6518 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6519 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6520 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6521
a7e76271
IM		 6522 if (!spec->dig_out && !spec->dig_in)
6523 return 0;
6524
bbbc7e85
TI		 6525 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6526 if (!info)
6527 return -ENOMEM;
a7e76271
IM		 6528 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6529 if (spec->dig_out) {
6530 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6531 ca0132_pcm_digital_playback;
6532 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6533 }
6534 if (spec->dig_in) {
6535 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6536 ca0132_pcm_digital_capture;
6537 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6538 }
95c6e9cb 6539
a7e76271 6540 return 0;
95c6e9cb
IM		 6541}
6542
7675a2a9
CM		 6543static int dbpro_build_pcms(struct hda_codec *codec)
6544{
6545 struct ca0132_spec *spec = codec->spec;
6546 struct hda_pcm *info;
6547
6548 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
6549 if (!info)
6550 return -ENOMEM;
6551 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6552 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6553 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6554
6555
6556 if (!spec->dig_out && !spec->dig_in)
6557 return 0;
6558
6559 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6560 if (!info)
6561 return -ENOMEM;
6562 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6563 if (spec->dig_out) {
6564 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6565 ca0132_pcm_digital_playback;
6566 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6567 }
6568 if (spec->dig_in) {
6569 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6570 ca0132_pcm_digital_capture;
6571 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6572 }
6573
6574 return 0;
6575}
6576
441aa6a0
IM		 6577static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6578{
6579 if (pin) {
a0c041cb 6580 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6581 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6582 snd_hda_codec_write(codec, pin, 0,
6583 AC_VERB_SET_AMP_GAIN_MUTE,
6584 AMP_OUT_UNMUTE);
6585 }
6586 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6587 snd_hda_codec_write(codec, dac, 0,
6588 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6589}
6590
6591static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6592{
6593 if (pin) {
a0c041cb 6594 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6595 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6596 snd_hda_codec_write(codec, pin, 0,
6597 AC_VERB_SET_AMP_GAIN_MUTE,
6598 AMP_IN_UNMUTE(0));
6599 }
6600 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6601 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6602 AMP_IN_UNMUTE(0));
6603
6604 /* init to 0 dB and unmute. */
6605 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6606 HDA_AMP_VOLMASK, 0x5a);
6607 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6608 HDA_AMP_MUTE, 0);
6609 }
6610}
6611
5aaca44d
IM		 6612static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6613{
6614 unsigned int caps;
6615
6616 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6617 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6618 snd_hda_override_amp_caps(codec, nid, dir, caps);
6619}
6620
6621/*
6622 * Switch between Digital built-in mic and analog mic.
6623 */
6624static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6625{
6626 struct ca0132_spec *spec = codec->spec;
6627 unsigned int tmp;
6628 u8 val;
6629 unsigned int oldval;
6630
4e76a883 6631 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6632
6633 oldval = stop_mic1(codec);
6634 ca0132_set_vipsource(codec, 0);
6635 if (enable) {
6636 /* set DMic input as 2-ch */
6637 tmp = FLOAT_TWO;
6638 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6639
6640 val = spec->dmic_ctl;
6641 val |= 0x80;
6642 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6643 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6644
6645 if (!(spec->dmic_ctl & 0x20))
6646 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6647 } else {
6648 /* set AMic input as mono */
6649 tmp = FLOAT_ONE;
6650 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6651
6652 val = spec->dmic_ctl;
6653 /* clear bit7 and bit5 to disable dmic */
6654 val &= 0x5f;
6655 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6656 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6657
6658 if (!(spec->dmic_ctl & 0x20))
6659 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6660 }
6661 ca0132_set_vipsource(codec, 1);
6662 resume_mic1(codec, oldval);
6663}
6664
6665/*
6666 * Initialization for Digital Mic.
6667 */
6668static void ca0132_init_dmic(struct hda_codec *codec)
6669{
6670 struct ca0132_spec *spec = codec->spec;
6671 u8 val;
6672
6673 /* Setup Digital Mic here, but don't enable.
6674 * Enable based on jack detect.
6675 */
6676
6677 /* MCLK uses MPIO1, set to enable.
6678 * Bit 2-0: MPIO select
6679 * Bit 3: set to disable
6680 * Bit 7-4: reserved
6681 */
6682 val = 0x01;
6683 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6684 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6685
6686 /* Data1 uses MPIO3. Data2 not use
6687 * Bit 2-0: Data1 MPIO select
6688 * Bit 3: set disable Data1
6689 * Bit 6-4: Data2 MPIO select
6690 * Bit 7: set disable Data2
6691 */
6692 val = 0x83;
6693 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6694 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6695
6696 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6697 * Bit 3-0: Channel mask
6698 * Bit 4: set for 48KHz, clear for 32KHz
6699 * Bit 5: mode
6700 * Bit 6: set to select Data2, clear for Data1
6701 * Bit 7: set to enable DMic, clear for AMic
6702 */
a57a46b9
AB		 6703 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6704 val = 0x33;
6705 else
6706 val = 0x23;
5aaca44d
IM		 6707 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6708 spec->dmic_ctl = val;
6709 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6710 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6711}
6712
6713/*
6714 * Initialization for Analog Mic 2
6715 */
6716static void ca0132_init_analog_mic2(struct hda_codec *codec)
6717{
6718 struct ca0132_spec *spec = codec->spec;
6719
6720 mutex_lock(&spec->chipio_mutex);
6721 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6722 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6723 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6724 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6725 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6726 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6727 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6728 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6729 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6730 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6731 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6732 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6733 mutex_unlock(&spec->chipio_mutex);
6734}
6735
6736static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6737{
6738 struct ca0132_spec *spec = codec->spec;
6739 int i;
5aaca44d 6740
4e76a883 6741 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6742 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6743
6744 for (i = 0; i < spec->multiout.num_dacs; i++)
6745 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6746
6747 for (i = 0; i < spec->num_outputs; i++)
6748 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6749
6750 for (i = 0; i < spec->num_inputs; i++) {
6751 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6752 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6753 }
6754}
6755
7e6ed62e 6756/*
6ef0e91e
CM		 6757 * Creates a dummy stream to bind the output to. This seems to have to be done
6758 * after changing the main outputs source and destination streams.
7e6ed62e 6759 */
6ef0e91e 6760static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
447fd8e9 6761{
6ef0e91e
CM		 6762 struct ca0132_spec *spec = codec->spec;
6763 unsigned int stream_format;
447fd8e9 6764
6ef0e91e
CM		 6765 stream_format = snd_hdac_calc_stream_format(48000, 2,
6766 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7e6ed62e 6767
6ef0e91e
CM		 6768 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6769 0, stream_format);
7e6ed62e 6770
6ef0e91e 6771 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7e6ed62e
CM		 6772}
6773
38ba69ff 6774/*
6ef0e91e 6775 * Initialize mic for non-chromebook ca0132 implementations.
38ba69ff 6776 */
6ef0e91e 6777static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
38ba69ff 6778{
6ef0e91e 6779 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6780 unsigned int tmp;
6781
6782 /* Mic 1 Setup */
6783 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6784 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6ef0e91e
CM		 6785 if (spec->quirk == QUIRK_R3DI) {
6786 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6787 tmp = FLOAT_ONE;
6788 } else
6789 tmp = FLOAT_THREE;
38ba69ff
CM		 6790 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6791
6ef0e91e 6792 /* Mic 2 setup (not present on desktop cards) */
38ba69ff
CM		 6793 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6794 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6ef0e91e
CM		 6795 if (spec->quirk == QUIRK_R3DI)
6796 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
38ba69ff
CM		 6797 tmp = FLOAT_ZERO;
6798 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
38ba69ff
CM		 6799}
6800
6801/*
6802 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6803 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6804 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6805 * having an updated DAC, which changes the destination to that DAC.
6806 */
6807static void sbz_connect_streams(struct hda_codec *codec)
6808{
6809 struct ca0132_spec *spec = codec->spec;
6810
6811 mutex_lock(&spec->chipio_mutex);
6812
6813 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6814
6815 chipio_set_stream_channels(codec, 0x0C, 6);
6816 chipio_set_stream_control(codec, 0x0C, 1);
6817
6818 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6819 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6820
6821 /* Setup stream 0x14 with it's source and destination points */
6822 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6823 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6824 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6825 chipio_set_stream_channels(codec, 0x14, 2);
6826 chipio_set_stream_control(codec, 0x14, 1);
6827
6828 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6829
6830 mutex_unlock(&spec->chipio_mutex);
38ba69ff
CM		 6831}
6832
6833/*
6834 * Write data through ChipIO to setup proper stream destinations.
6835 * Not sure how it exactly works, but it seems to direct data
6836 * to different destinations. Example is f8 to c0, e0 to c0.
6837 * All I know is, if you don't set these, you get no sound.
6838 */
6839static void sbz_chipio_startup_data(struct hda_codec *codec)
6840{
6841 struct ca0132_spec *spec = codec->spec;
6842
6843 mutex_lock(&spec->chipio_mutex);
6844 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6845
6846 /* These control audio output */
6847 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6848 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6849 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6850 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6851 /* Signal to update I think */
6852 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6853
6854 chipio_set_stream_channels(codec, 0x0C, 6);
6855 chipio_set_stream_control(codec, 0x0C, 1);
6856 /* No clue what these control */
6857 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6858 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6859 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6860 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6861 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6862 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6863 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6864 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6865 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6866 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6867 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6868 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6869
6870 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6871
6872 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6873 mutex_unlock(&spec->chipio_mutex);
6874}
6875
447fd8e9 6876/*
6ef0e91e
CM		 6877 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
6878 * done after the DSP is loaded.
447fd8e9 6879 */
6ef0e91e 6880static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
447fd8e9 6881{
6ef0e91e 6882 struct ca0132_spec *spec = codec->spec;
447fd8e9
CM		 6883 unsigned int tmp;
6884
6ef0e91e
CM		 6885 switch (spec->quirk) {
6886 case QUIRK_SBZ:
6887 case QUIRK_AE5:
6888 tmp = 0x00000003;
6889 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6890 tmp = 0x00000000;
6891 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6892 tmp = 0x00000001;
6893 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6894 tmp = 0x00000004;
6895 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6896 tmp = 0x00000005;
6897 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6898 tmp = 0x00000000;
6899 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6900 break;
6901 case QUIRK_R3D:
6902 case QUIRK_R3DI:
6903 tmp = 0x00000000;
6904 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6905 tmp = 0x00000001;
6906 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6907 tmp = 0x00000004;
6908 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6909 tmp = 0x00000005;
6910 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6911 tmp = 0x00000000;
6912 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6913 break;
6914 }
447fd8e9
CM		 6915}
6916
6ef0e91e 6917static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
38ba69ff 6918{
6ef0e91e 6919 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6920 unsigned int tmp;
6921
6922 chipio_set_stream_control(codec, 0x03, 0);
6923 chipio_set_stream_control(codec, 0x04, 0);
6924
6925 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6926 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6927
6928 tmp = FLOAT_THREE;
6929 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6930
6931 chipio_set_stream_control(codec, 0x03, 1);
6932 chipio_set_stream_control(codec, 0x04, 1);
6933
6ef0e91e
CM		 6934 switch (spec->quirk) {
6935 case QUIRK_SBZ:
6936 chipio_write(codec, 0x18b098, 0x0000000c);
6937 chipio_write(codec, 0x18b09C, 0x0000000c);
6938 break;
6939 case QUIRK_AE5:
6940 chipio_write(codec, 0x18b098, 0x0000000c);
6941 chipio_write(codec, 0x18b09c, 0x0000004c);
6942 break;
6943 }
38ba69ff
CM		 6944}
6945
415cd844
CM		 6946static void ae5_post_dsp_register_set(struct hda_codec *codec)
6947{
6948 struct ca0132_spec *spec = codec->spec;
6949
6950 chipio_8051_write_direct(codec, 0x93, 0x10);
6951 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6952 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
6953 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6954 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
6955
6956 writeb(0xff, spec->mem_base + 0x304);
6957 writeb(0xff, spec->mem_base + 0x304);
6958 writeb(0xff, spec->mem_base + 0x304);
6959 writeb(0xff, spec->mem_base + 0x304);
6960 writeb(0x00, spec->mem_base + 0x100);
6961 writeb(0xff, spec->mem_base + 0x304);
6962 writeb(0x00, spec->mem_base + 0x100);
6963 writeb(0xff, spec->mem_base + 0x304);
6964 writeb(0x00, spec->mem_base + 0x100);
6965 writeb(0xff, spec->mem_base + 0x304);
6966 writeb(0x00, spec->mem_base + 0x100);
6967 writeb(0xff, spec->mem_base + 0x304);
6968
6969 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
6970 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
6971 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
6972}
6973
6974static void ae5_post_dsp_param_setup(struct hda_codec *codec)
6975{
6976 /*
6977 * Param3 in the 8051's memory is represented by the ascii string 'mch'
6978 * which seems to be 'multichannel'. This is also mentioned in the
6979 * AE-5's registry values in Windows.
6980 */
6981 chipio_set_control_param(codec, 3, 0);
6982 /*
6983 * I believe ASI is 'audio serial interface' and that it's used to
6984 * change colors on the external LED strip connected to the AE-5.
6985 */
6986 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
6987
6988 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
6989 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
6990
6991 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6992 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
6993 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6994 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
6995 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6996 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
6997}
6998
6999static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7000{
7001 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7002 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7003 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7004 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7005
7006 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7007 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7008 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7009 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7010
7011 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7012 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7013 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7014 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7015
7016 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7017 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7018 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7019 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7020
7021 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7022 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7023 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7024 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7025}
7026
7027static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7028{
7029 struct ca0132_spec *spec = codec->spec;
7030
7031 mutex_lock(&spec->chipio_mutex);
7032
7033 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7034
7035 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7036
7037 chipio_set_stream_channels(codec, 0x0C, 6);
7038 chipio_set_stream_control(codec, 0x0C, 1);
7039
7040 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7041
7042 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7043 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7044 chipio_set_stream_channels(codec, 0x18, 6);
7045 chipio_set_stream_control(codec, 0x18, 1);
7046
7047 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7048
7049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7050 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7051 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7052 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7053
7054 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7055
7056 mutex_unlock(&spec->chipio_mutex);
7057}
7058
7059static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7060{
7061 struct ca0132_spec *spec = codec->spec;
7062
7063 mutex_lock(&spec->chipio_mutex);
7064
7065 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7066 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7067 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7068 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7069
7070 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7071 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7072 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7073 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7074 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7075 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7076 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7077 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7078 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7079 ca0113_mmio_gpio_set(codec, 0, true);
7080 ca0113_mmio_gpio_set(codec, 1, true);
7081 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7082
7083 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7084
7085 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7086 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7087
7088 mutex_unlock(&spec->chipio_mutex);
7089}
7090
5aaca44d
IM		 7091/*
7092 * Setup default parameters for DSP
7093 */
7094static void ca0132_setup_defaults(struct hda_codec *codec)
7095{
e8f1bd5d 7096 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7097 unsigned int tmp;
7098 int num_fx;
7099 int idx, i;
7100
e8f1bd5d 7101 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 7102 return;
7103
7104 /* out, in effects + voicefx */
7105 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7106 for (idx = 0; idx < num_fx; idx++) {
7107 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7108 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
7109 ca0132_effects[idx].reqs[i],
7110 ca0132_effects[idx].def_vals[i]);
7111 }
7112 }
7113
7114 /*remove DSP headroom*/
7115 tmp = FLOAT_ZERO;
7116 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7117
7118 /*set speaker EQ bypass attenuation*/
7119 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
7120
7121 /* set AMic1 and AMic2 as mono mic */
7122 tmp = FLOAT_ONE;
7123 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7124 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7125
7126 /* set AMic1 as CrystalVoice input */
7127 tmp = FLOAT_ONE;
7128 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
7129
7130 /* set WUH source */
7131 tmp = FLOAT_TWO;
7132 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7133}
7134
7e6ed62e 7135/*
c986f50c 7136 * Setup default parameters for Recon3D/Recon3Di DSP.
7e6ed62e
CM		 7137 */
7138
c986f50c 7139static void r3d_setup_defaults(struct hda_codec *codec)
7e6ed62e
CM		 7140{
7141 struct ca0132_spec *spec = codec->spec;
7142 unsigned int tmp;
7143 int num_fx;
7144 int idx, i;
7145
7146 if (spec->dsp_state != DSP_DOWNLOADED)
7147 return;
7148
6ef0e91e
CM		 7149 ca0132_alt_dsp_scp_startup(codec);
7150 ca0132_alt_init_analog_mics(codec);
7e6ed62e
CM		 7151
7152 /*remove DSP headroom*/
7153 tmp = FLOAT_ZERO;
7154 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7155
7156 /* set WUH source */
7157 tmp = FLOAT_TWO;
7158 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7159 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7160
7161 /* Set speaker source? */
7162 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7163
c986f50c
CM		 7164 if (spec->quirk == QUIRK_R3DI)
7165 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7e6ed62e
CM		 7166
7167 /* Setup effect defaults */
7168 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7169 for (idx = 0; idx < num_fx; idx++) {
7170 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7171 dspio_set_uint_param(codec,
7172 ca0132_effects[idx].mid,
7173 ca0132_effects[idx].reqs[i],
7174 ca0132_effects[idx].def_vals[i]);
7175 }
7176 }
7e6ed62e
CM		 7177}
7178
38ba69ff
CM		 7179/*
7180 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
7181 * than the Chromebook setup.
7182 */
7183static void sbz_setup_defaults(struct hda_codec *codec)
7184{
7185 struct ca0132_spec *spec = codec->spec;
6ef0e91e 7186 unsigned int tmp;
38ba69ff
CM		 7187 int num_fx;
7188 int idx, i;
7189
7190 if (spec->dsp_state != DSP_DOWNLOADED)
7191 return;
7192
6ef0e91e
CM		 7193 ca0132_alt_dsp_scp_startup(codec);
7194 ca0132_alt_init_analog_mics(codec);
38ba69ff 7195 sbz_connect_streams(codec);
38ba69ff
CM		 7196 sbz_chipio_startup_data(codec);
7197
7198 chipio_set_stream_control(codec, 0x03, 1);
7199 chipio_set_stream_control(codec, 0x04, 1);
7200
7201 /*
7202 * Sets internal input loopback to off, used to have a switch to
7203 * enable input loopback, but turned out to be way too buggy.
7204 */
7205 tmp = FLOAT_ONE;
7206 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7207 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7208
7209 /*remove DSP headroom*/
7210 tmp = FLOAT_ZERO;
7211 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7212
7213 /* set WUH source */
7214 tmp = FLOAT_TWO;
7215 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7216 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7217
7218 /* Set speaker source? */
7219 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7220
6ef0e91e 7221 ca0132_alt_dsp_initial_mic_setup(codec);
38ba69ff
CM		 7222
7223 /* out, in effects + voicefx */
7224 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7225 for (idx = 0; idx < num_fx; idx++) {
7226 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7227 dspio_set_uint_param(codec,
7228 ca0132_effects[idx].mid,
7229 ca0132_effects[idx].reqs[i],
7230 ca0132_effects[idx].def_vals[i]);
7231 }
7232 }
7233
6ef0e91e 7234 ca0132_alt_create_dummy_stream(codec);
38ba69ff
CM		 7235}
7236
415cd844
CM		 7237/*
7238 * Setup default parameters for the Sound BlasterX AE-5 DSP.
7239 */
7240static void ae5_setup_defaults(struct hda_codec *codec)
7241{
7242 struct ca0132_spec *spec = codec->spec;
7243 unsigned int tmp;
7244 int num_fx;
7245 int idx, i;
7246
7247 if (spec->dsp_state != DSP_DOWNLOADED)
7248 return;
7249
7250 ca0132_alt_dsp_scp_startup(codec);
7251 ca0132_alt_init_analog_mics(codec);
7252 chipio_set_stream_control(codec, 0x03, 1);
7253 chipio_set_stream_control(codec, 0x04, 1);
7254
7255 /* New, unknown SCP req's */
7256 tmp = FLOAT_ZERO;
7257 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
7258 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
7259 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
7260 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
7261
7262 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
7263 ca0113_mmio_gpio_set(codec, 0, false);
7264 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
7265
7266 /* Internal loopback off */
7267 tmp = FLOAT_ONE;
7268 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7269 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7270
7271 /*remove DSP headroom*/
7272 tmp = FLOAT_ZERO;
7273 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7274
7275 /* set WUH source */
7276 tmp = FLOAT_TWO;
7277 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7278 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7279
7280 /* Set speaker source? */
7281 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7282
7283 ca0132_alt_dsp_initial_mic_setup(codec);
7284 ae5_post_dsp_register_set(codec);
7285 ae5_post_dsp_param_setup(codec);
7286 ae5_post_dsp_pll_setup(codec);
7287 ae5_post_dsp_stream_setup(codec);
7288 ae5_post_dsp_startup_data(codec);
7289
7290 /* out, in effects + voicefx */
7291 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7292 for (idx = 0; idx < num_fx; idx++) {
7293 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7294 dspio_set_uint_param(codec,
7295 ca0132_effects[idx].mid,
7296 ca0132_effects[idx].reqs[i],
7297 ca0132_effects[idx].def_vals[i]);
7298 }
7299 }
7300
7301 ca0132_alt_create_dummy_stream(codec);
7302}
7303
5aaca44d
IM		 7304/*
7305 * Initialization of flags in chip
7306 */
7307static void ca0132_init_flags(struct hda_codec *codec)
7308{
009b8f97
CM		 7309 struct ca0132_spec *spec = codec->spec;
7310
7311 if (spec->use_alt_functions) {
7312 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
7313 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
7314 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
7315 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
7316 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
7317 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7318 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
7319 chipio_set_control_flag(codec,
7320 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7321 chipio_set_control_flag(codec,
7322 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
7323 } else {
7324 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7325 chipio_set_control_flag(codec,
7326 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
7327 chipio_set_control_flag(codec,
7328 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
7329 chipio_set_control_flag(codec,
7330 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
7331 chipio_set_control_flag(codec,
7332 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7333 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
7334 }
5aaca44d
IM		 7335}
7336
7337/*
7338 * Initialization of parameters in chip
7339 */
7340static void ca0132_init_params(struct hda_codec *codec)
7341{
009b8f97
CM		 7342 struct ca0132_spec *spec = codec->spec;
7343
7344 if (spec->use_alt_functions) {
7345 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7346 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
7347 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
7348 chipio_set_control_param(codec, 0, 0);
7349 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
7350 }
7351
5aaca44d
IM		 7352 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
7353 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
7354}
95c6e9cb 7355
e90f29e4
IM		 7356static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
7357{
7358 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
7359 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
7360 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
7361 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
7362 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
7363 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
7364
406261ce
IM		 7365 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7366 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 7367 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7368}
7369
7370static bool ca0132_download_dsp_images(struct hda_codec *codec)
7371{
7372 bool dsp_loaded = false;
8a19bcee 7373 struct ca0132_spec *spec = codec->spec;
e90f29e4 7374 const struct dsp_image_seg *dsp_os_image;
15e4ba66 7375 const struct firmware *fw_entry;
8a19bcee
CM		 7376 /*
7377 * Alternate firmwares for different variants. The Recon3Di apparently
7378 * can use the default firmware, but I'll leave the option in case
7379 * it needs it again.
7380 */
7381 switch (spec->quirk) {
7382 case QUIRK_SBZ:
7a928186
CM		 7383 case QUIRK_R3D:
7384 case QUIRK_AE5:
7385 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8a19bcee 7386 codec->card->dev) != 0) {
6ef0e91e 7387 codec_dbg(codec, "Desktop firmware not found.");
8a19bcee
CM		 7388 spec->alt_firmware_present = false;
7389 } else {
7a928186 7390 codec_dbg(codec, "Desktop firmware selected.");
8a19bcee
CM		 7391 spec->alt_firmware_present = true;
7392 }
7393 break;
7394 case QUIRK_R3DI:
7395 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
7396 codec->card->dev) != 0) {
7397 codec_dbg(codec, "Recon3Di alt firmware not detected.");
7398 spec->alt_firmware_present = false;
7399 } else {
7400 codec_dbg(codec, "Recon3Di firmware selected.");
7401 spec->alt_firmware_present = true;
7402 }
7403 break;
7404 default:
7405 spec->alt_firmware_present = false;
7406 break;
7407 }
7408 /*
7409 * Use default ctefx.bin if no alt firmware is detected, or if none
7410 * exists for your particular codec.
7411 */
7412 if (!spec->alt_firmware_present) {
7413 codec_dbg(codec, "Default firmware selected.");
7414 if (request_firmware(&fw_entry, EFX_FILE,
7415 codec->card->dev) != 0)
7416 return false;
7417 }
e90f29e4 7418
15e4ba66 7419 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 7420 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 7421 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 7422 goto exit_download;
7423 }
7424
e90f29e4
IM		 7425 dsp_loaded = dspload_wait_loaded(codec);
7426
d1d28500 7427exit_download:
15e4ba66
TI		 7428 release_firmware(fw_entry);
7429
e90f29e4
IM		 7430 return dsp_loaded;
7431}
7432
7433static void ca0132_download_dsp(struct hda_codec *codec)
7434{
7435 struct ca0132_spec *spec = codec->spec;
7436
9a0869f4
TI		 7437#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7438 return; /* NOP */
7439#endif
e90f29e4 7440
e24aa0a4
TI		 7441 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7442 return; /* don't retry failures */
7443
b714a710 7444 chipio_enable_clocks(codec);
e93ac30a
CM		 7445 if (spec->dsp_state != DSP_DOWNLOADED) {
7446 spec->dsp_state = DSP_DOWNLOADING;
7447
7448 if (!ca0132_download_dsp_images(codec))
7449 spec->dsp_state = DSP_DOWNLOAD_FAILED;
7450 else
7451 spec->dsp_state = DSP_DOWNLOADED;
7452 }
e90f29e4 7453
009b8f97
CM		 7454 /* For codecs using alt functions, this is already done earlier */
7455 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 7456 ca0132_set_dsp_msr(codec, true);
7457}
7458
f8fb1170
TI		 7459static void ca0132_process_dsp_response(struct hda_codec *codec,
7460 struct hda_jack_callback *callback)
e90f29e4
IM		 7461{
7462 struct ca0132_spec *spec = codec->spec;
7463
4e76a883 7464 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 7465 if (spec->wait_scp) {
7466 if (dspio_get_response_data(codec) >= 0)
7467 spec->wait_scp = 0;
7468 }
7469
7470 dspio_clear_response_queue(codec);
7471}
7472
f8fb1170 7473static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 7474{
993884f6 7475 struct ca0132_spec *spec = codec->spec;
2ebab40e 7476 struct hda_jack_tbl *tbl;
e90f29e4 7477
f8fb1170
TI		 7478 /* Delay enabling the HP amp, to let the mic-detection
7479 * state machine run.
7480 */
7481 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 7482 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 7483 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7484 if (tbl)
7485 tbl->block_report = 1;
f8fb1170
TI		 7486}
7487
7488static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7489{
a1b7f016
CM		 7490 struct ca0132_spec *spec = codec->spec;
7491
7492 if (spec->use_alt_functions)
7493 ca0132_alt_select_in(codec);
7494 else
7495 ca0132_select_mic(codec);
f8fb1170
TI		 7496}
7497
7498static void ca0132_init_unsol(struct hda_codec *codec)
7499{
d5c016b5
GM		 7500 struct ca0132_spec *spec = codec->spec;
7501 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7502 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 7503 amic_callback);
7504 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7505 ca0132_process_dsp_response);
63177afc 7506 /* Front headphone jack detection */
009b8f97 7507 if (spec->use_alt_functions)
63177afc
CM		 7508 snd_hda_jack_detect_enable_callback(codec,
7509 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 7510}
7511
5aaca44d
IM		 7512/*
7513 * Verbs tables.
7514 */
7515
7516/* Sends before DSP download. */
7517static struct hda_verb ca0132_base_init_verbs[] = {
7518 /*enable ct extension*/
7519 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 7520 {}
7521};
7522
7523/* Send at exit. */
7524static struct hda_verb ca0132_base_exit_verbs[] = {
7525 /*set afg to D3*/
7526 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7527 /*disable ct extension*/
7528 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7529 {}
7530};
7531
8a19bcee 7532/* Other verbs tables. Sends after DSP download. */
e93ac30a 7533
5aaca44d
IM		 7534static struct hda_verb ca0132_init_verbs0[] = {
7535 /* chip init verbs */
7536 {0x15, 0x70D, 0xF0},
7537 {0x15, 0x70E, 0xFE},
7538 {0x15, 0x707, 0x75},
7539 {0x15, 0x707, 0xD3},
7540 {0x15, 0x707, 0x09},
7541 {0x15, 0x707, 0x53},
7542 {0x15, 0x707, 0xD4},
7543 {0x15, 0x707, 0xEF},
7544 {0x15, 0x707, 0x75},
7545 {0x15, 0x707, 0xD3},
7546 {0x15, 0x707, 0x09},
7547 {0x15, 0x707, 0x02},
7548 {0x15, 0x707, 0x37},
7549 {0x15, 0x707, 0x78},
7550 {0x15, 0x53C, 0xCE},
7551 {0x15, 0x575, 0xC9},
7552 {0x15, 0x53D, 0xCE},
7553 {0x15, 0x5B7, 0xC9},
7554 {0x15, 0x70D, 0xE8},
7555 {0x15, 0x70E, 0xFE},
7556 {0x15, 0x707, 0x02},
7557 {0x15, 0x707, 0x68},
7558 {0x15, 0x707, 0x62},
7559 {0x15, 0x53A, 0xCE},
7560 {0x15, 0x546, 0xC9},
7561 {0x15, 0x53B, 0xCE},
7562 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 7563 {}
7564};
7565
e42c7c73
CM		 7566/* Extra init verbs for desktop cards. */
7567static struct hda_verb ca0132_init_verbs1[] = {
e93ac30a
CM		 7568 {0x15, 0x70D, 0x20},
7569 {0x15, 0x70E, 0x19},
7570 {0x15, 0x707, 0x00},
7571 {0x15, 0x539, 0xCE},
7572 {0x15, 0x546, 0xC9},
7573 {0x15, 0x70D, 0xB7},
7574 {0x15, 0x70E, 0x09},
7575 {0x15, 0x707, 0x10},
7576 {0x15, 0x70D, 0xAF},
7577 {0x15, 0x70E, 0x09},
7578 {0x15, 0x707, 0x01},
7579 {0x15, 0x707, 0x05},
7580 {0x15, 0x70D, 0x73},
7581 {0x15, 0x70E, 0x09},
7582 {0x15, 0x707, 0x14},
7583 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 7584 {}
7585};
7586
95c6e9cb
IM		 7587static void ca0132_init_chip(struct hda_codec *codec)
7588{
7589 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7590 int num_fx;
7591 int i;
7592 unsigned int on;
95c6e9cb
IM		 7593
7594 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 7595
7596 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 7597 if (!spec->use_alt_functions)
7598 spec->cur_mic_type = DIGITAL_MIC;
7599 else
7600 spec->cur_mic_type = REAR_MIC;
7601
5aaca44d
IM		 7602 spec->cur_mic_boost = 0;
7603
7604 for (i = 0; i < VNODES_COUNT; i++) {
7605 spec->vnode_lvol[i] = 0x5a;
7606 spec->vnode_rvol[i] = 0x5a;
7607 spec->vnode_lswitch[i] = 0;
7608 spec->vnode_rswitch[i] = 0;
7609 }
7610
7611 /*
7612 * Default states for effects are in ca0132_effects[].
7613 */
7614 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7615 for (i = 0; i < num_fx; i++) {
7616 on = (unsigned int)ca0132_effects[i].reqs[0];
7617 spec->effects_switch[i] = on ? 1 : 0;
7618 }
47cdf76e
CM		 7619 /*
7620 * Sets defaults for the effect slider controls, only for alternative
7621 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7622 */
7623 if (spec->use_alt_controls) {
7624 spec->xbass_xover_freq = 8;
7625 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7626 spec->fx_ctl_val[i] = effect_slider_defaults[i];
7627 }
5aaca44d
IM		 7628
7629 spec->voicefx_val = 0;
7630 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7631 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7632
44f0c978
IM		 7633#ifdef ENABLE_TUNING_CONTROLS
7634 ca0132_init_tuning_defaults(codec);
7635#endif
95c6e9cb
IM		 7636}
7637
2e48b2b7
CM		 7638/*
7639 * Recon3Di exit specific commands.
7640 */
7641/* prevents popping noise on shutdown */
7642static void r3di_gpio_shutdown(struct hda_codec *codec)
7643{
7644 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7645}
7646
7647/*
7648 * Sound Blaster Z exit specific commands.
7649 */
7650static void sbz_region2_exit(struct hda_codec *codec)
7651{
7652 struct ca0132_spec *spec = codec->spec;
7653 unsigned int i;
7654
7655 for (i = 0; i < 4; i++)
7656 writeb(0x0, spec->mem_base + 0x100);
7657 for (i = 0; i < 8; i++)
7658 writeb(0xb3, spec->mem_base + 0x304);
a62e4739 7659
b9b41345
CM		 7660 ca0113_mmio_gpio_set(codec, 0, false);
7661 ca0113_mmio_gpio_set(codec, 1, false);
7662 ca0113_mmio_gpio_set(codec, 4, true);
7663 ca0113_mmio_gpio_set(codec, 5, false);
7664 ca0113_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 7665}
7666
7667static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7668{
7669 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7670 unsigned int i;
7671
7672 snd_hda_codec_write(codec, 0x11, 0,
7673 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7674
7675 for (i = 0; i < 5; i++)
7676 snd_hda_codec_write(codec, pins[i], 0,
7677 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7678}
7679
2f295f91 7680static void ca0132_clear_unsolicited(struct hda_codec *codec)
2e48b2b7
CM		 7681{
7682 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7683 unsigned int i;
7684
7685 for (i = 0; i < 7; i++) {
7686 snd_hda_codec_write(codec, pins[i], 0,
7687 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7688 }
7689}
7690
7691/* On shutdown, sends commands in sets of three */
7692static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7693 int mask, int data)
7694{
7695 if (dir >= 0)
7696 snd_hda_codec_write(codec, 0x01, 0,
7697 AC_VERB_SET_GPIO_DIRECTION, dir);
7698 if (mask >= 0)
7699 snd_hda_codec_write(codec, 0x01, 0,
7700 AC_VERB_SET_GPIO_MASK, mask);
7701
7702 if (data >= 0)
7703 snd_hda_codec_write(codec, 0x01, 0,
7704 AC_VERB_SET_GPIO_DATA, data);
7705}
7706
7675a2a9
CM		 7707static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
7708{
7709 hda_nid_t pins[7] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
7710 unsigned int i;
7711
7712 for (i = 0; i < 7; i++)
7713 snd_hda_codec_write(codec, pins[i], 0,
7714 AC_VERB_SET_POWER_STATE, 0x03);
7715}
7716
2e48b2b7
CM		 7717static void sbz_exit_chip(struct hda_codec *codec)
7718{
009b8f97
CM		 7719 chipio_set_stream_control(codec, 0x03, 0);
7720 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 7721
7722 /* Mess with GPIO */
7723 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7724 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7725 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7726
009b8f97
CM		 7727 chipio_set_stream_control(codec, 0x14, 0);
7728 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7729
7730 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7731 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7732
7733 chipio_write(codec, 0x18a020, 0x00000083);
7734
7735 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7736 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7737 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7738
009b8f97 7739 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7740
7741 chipio_set_control_param(codec, 0x0D, 0x24);
7742
2f295f91 7743 ca0132_clear_unsolicited(codec);
2e48b2b7
CM		 7744 sbz_set_pin_ctl_default(codec);
7745
7746 snd_hda_codec_write(codec, 0x0B, 0,
7747 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7748
2e48b2b7
CM		 7749 sbz_region2_exit(codec);
7750}
7751
2f295f91
CM		 7752static void r3d_exit_chip(struct hda_codec *codec)
7753{
7754 ca0132_clear_unsolicited(codec);
7755 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7756 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7757}
7758
edb1b3ab
CM		 7759static void ae5_exit_chip(struct hda_codec *codec)
7760{
7761 chipio_set_stream_control(codec, 0x03, 0);
7762 chipio_set_stream_control(codec, 0x04, 0);
7763
7764 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7765 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7766 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7767 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7768 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7769 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
7770 ca0113_mmio_gpio_set(codec, 0, false);
7771 ca0113_mmio_gpio_set(codec, 1, false);
7772
7773 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7774 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7775
7776 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7777
7778 chipio_set_stream_control(codec, 0x18, 0);
7779 chipio_set_stream_control(codec, 0x0c, 0);
7780
7781 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
7782}
7783
95c6e9cb
IM		 7784static void ca0132_exit_chip(struct hda_codec *codec)
7785{
7786 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7787
7788 if (dspload_is_loaded(codec))
7789 dsp_reset(codec);
95c6e9cb
IM		 7790}
7791
38ba69ff
CM		 7792/*
7793 * This fixes a problem that was hard to reproduce. Very rarely, I would
7794 * boot up, and there would be no sound, but the DSP indicated it had loaded
7795 * properly. I did a few memory dumps to see if anything was different, and
7796 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7797 * checks if those areas are uninitialized, and if they are, it'll attempt to
7798 * reload the card 3 times. Usually it fixes by the second.
7799 */
7800static void sbz_dsp_startup_check(struct hda_codec *codec)
7801{
7802 struct ca0132_spec *spec = codec->spec;
7803 unsigned int dsp_data_check[4];
7804 unsigned int cur_address = 0x390;
7805 unsigned int i;
7806 unsigned int failure = 0;
7807 unsigned int reload = 3;
7808
7809 if (spec->startup_check_entered)
7810 return;
7811
7812 spec->startup_check_entered = true;
7813
7814 for (i = 0; i < 4; i++) {
7815 chipio_read(codec, cur_address, &dsp_data_check[i]);
7816 cur_address += 0x4;
7817 }
7818 for (i = 0; i < 4; i++) {
7819 if (dsp_data_check[i] == 0xa1a2a3a4)
7820 failure = 1;
7821 }
7822
7823 codec_dbg(codec, "Startup Check: %d ", failure);
7824 if (failure)
7825 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7826 /*
7827 * While the failure condition is true, and we haven't reached our
7828 * three reload limit, continue trying to reload the driver and
7829 * fix the issue.
7830 */
7831 while (failure && (reload != 0)) {
7832 codec_info(codec, "Reloading... Tries left: %d", reload);
7833 sbz_exit_chip(codec);
7834 spec->dsp_state = DSP_DOWNLOAD_INIT;
7835 codec->patch_ops.init(codec);
7836 failure = 0;
7837 for (i = 0; i < 4; i++) {
7838 chipio_read(codec, cur_address, &dsp_data_check[i]);
7839 cur_address += 0x4;
7840 }
7841 for (i = 0; i < 4; i++) {
7842 if (dsp_data_check[i] == 0xa1a2a3a4)
7843 failure = 1;
7844 }
7845 reload--;
7846 }
7847
7848 if (!failure && reload < 3)
7849 codec_info(codec, "DSP fixed.");
7850
7851 if (!failure)
7852 return;
7853
7854 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7855}
7856
e93ac30a
CM		 7857/*
7858 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7859 * extra precision for decibel values. If you had the dB value in floating point
7860 * you would take the value after the decimal point, multiply by 64, and divide
7861 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7862 * implement fixed point or floating point dB volumes. For now, I'll set them
7863 * to 0 just incase a value has lingered from a boot into Windows.
7864 */
7865static void ca0132_alt_vol_setup(struct hda_codec *codec)
7866{
7867 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7868 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7869 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7870 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7871 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7872 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7873 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7874 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7875}
7876
7877/*
7878 * Extra commands that don't really fit anywhere else.
7879 */
7880static void sbz_pre_dsp_setup(struct hda_codec *codec)
7881{
7882 struct ca0132_spec *spec = codec->spec;
7883
7884 writel(0x00820680, spec->mem_base + 0x01C);
7885 writel(0x00820680, spec->mem_base + 0x01C);
7886
e93ac30a
CM		 7887 chipio_write(codec, 0x18b0a4, 0x000000c2);
7888
7889 snd_hda_codec_write(codec, 0x11, 0,
7890 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7891}
7892
e42c7c73
CM		 7893static void r3d_pre_dsp_setup(struct hda_codec *codec)
7894{
e42c7c73
CM		 7895 chipio_write(codec, 0x18b0a4, 0x000000c2);
7896
7897 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7898 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7899 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7900 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7901 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7902 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7903
7904 snd_hda_codec_write(codec, 0x11, 0,
7905 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7906}
7907
e93ac30a
CM		 7908static void r3di_pre_dsp_setup(struct hda_codec *codec)
7909{
7910 chipio_write(codec, 0x18b0a4, 0x000000c2);
7911
7912 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7913 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7914 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7915 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7916 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7917 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7918
7919 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7920 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7921 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7922 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7923 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7924 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7925 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7926 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7927
7928 snd_hda_codec_write(codec, 0x11, 0,
7929 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7930}
7931
e93ac30a
CM		 7932/*
7933 * These are sent before the DSP is downloaded. Not sure
7934 * what they do, or if they're necessary. Could possibly
7935 * be removed. Figure they're better to leave in.
7936 */
e42c7c73 7937static void ca0132_mmio_init(struct hda_codec *codec)
e93ac30a
CM		 7938{
7939 struct ca0132_spec *spec = codec->spec;
7940
ce715448
CM		 7941 if (spec->quirk == QUIRK_AE5)
7942 writel(0x00000001, spec->mem_base + 0x400);
7943 else
7944 writel(0x00000000, spec->mem_base + 0x400);
7945
7946 if (spec->quirk == QUIRK_AE5)
7947 writel(0x00000001, spec->mem_base + 0x408);
7948 else
7949 writel(0x00000000, spec->mem_base + 0x408);
7950
7951 if (spec->quirk == QUIRK_AE5)
7952 writel(0x00000001, spec->mem_base + 0x40c);
7953 else
7954 writel(0x00000000, spec->mem_base + 0x40C);
7955
e93ac30a 7956 writel(0x00880680, spec->mem_base + 0x01C);
ce715448
CM		 7957
7958 if (spec->quirk == QUIRK_AE5)
7959 writel(0x00000080, spec->mem_base + 0xC0C);
7960 else
7961 writel(0x00000083, spec->mem_base + 0xC0C);
7962
e93ac30a
CM		 7963 writel(0x00000030, spec->mem_base + 0xC00);
7964 writel(0x00000000, spec->mem_base + 0xC04);
ce715448
CM		 7965
7966 if (spec->quirk == QUIRK_AE5)
7967 writel(0x00000000, spec->mem_base + 0xC0C);
7968 else
7969 writel(0x00000003, spec->mem_base + 0xC0C);
7970
e93ac30a
CM		 7971 writel(0x00000003, spec->mem_base + 0xC0C);
7972 writel(0x00000003, spec->mem_base + 0xC0C);
7973 writel(0x00000003, spec->mem_base + 0xC0C);
ce715448
CM		 7974
7975 if (spec->quirk == QUIRK_AE5)
7976 writel(0x00000001, spec->mem_base + 0xC08);
7977 else
7978 writel(0x000000C1, spec->mem_base + 0xC08);
7979
e93ac30a
CM		 7980 writel(0x000000F1, spec->mem_base + 0xC08);
7981 writel(0x00000001, spec->mem_base + 0xC08);
7982 writel(0x000000C7, spec->mem_base + 0xC08);
7983 writel(0x000000C1, spec->mem_base + 0xC08);
7984 writel(0x00000080, spec->mem_base + 0xC04);
ce715448
CM		 7985
7986 if (spec->quirk == QUIRK_AE5) {
7987 writel(0x00000000, spec->mem_base + 0x42c);
7988 writel(0x00000000, spec->mem_base + 0x46c);
7989 writel(0x00000000, spec->mem_base + 0x4ac);
7990 writel(0x00000000, spec->mem_base + 0x4ec);
7991 writel(0x00000000, spec->mem_base + 0x43c);
7992 writel(0x00000000, spec->mem_base + 0x47c);
7993 writel(0x00000000, spec->mem_base + 0x4bc);
7994 writel(0x00000000, spec->mem_base + 0x4fc);
7995 writel(0x00000600, spec->mem_base + 0x100);
7996 writel(0x00000014, spec->mem_base + 0x410);
7997 writel(0x0000060f, spec->mem_base + 0x100);
7998 writel(0x0000070f, spec->mem_base + 0x100);
7999 writel(0x00000aff, spec->mem_base + 0x830);
8000 writel(0x00000000, spec->mem_base + 0x86c);
8001 writel(0x0000006b, spec->mem_base + 0x800);
8002 writel(0x00000001, spec->mem_base + 0x86c);
8003 writel(0x0000006b, spec->mem_base + 0x800);
8004 writel(0x00000057, spec->mem_base + 0x804);
8005 writel(0x00800000, spec->mem_base + 0x20c);
8006 }
e93ac30a
CM		 8007}
8008
b9b41345
CM		 8009/*
8010 * This function writes to some SFR's, does some region2 writes, and then
8011 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
8012 * what it does.
8013 */
8014static void ae5_register_set(struct hda_codec *codec)
8015{
8016 struct ca0132_spec *spec = codec->spec;
8017
8018 chipio_8051_write_direct(codec, 0x93, 0x10);
8019 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8020 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8021 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8022 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8023
8024 writeb(0x0f, spec->mem_base + 0x304);
8025 writeb(0x0f, spec->mem_base + 0x304);
8026 writeb(0x0f, spec->mem_base + 0x304);
8027 writeb(0x0f, spec->mem_base + 0x304);
8028 writeb(0x0e, spec->mem_base + 0x100);
8029 writeb(0x1f, spec->mem_base + 0x304);
8030 writeb(0x0c, spec->mem_base + 0x100);
8031 writeb(0x3f, spec->mem_base + 0x304);
8032 writeb(0x08, spec->mem_base + 0x100);
8033 writeb(0x7f, spec->mem_base + 0x304);
8034 writeb(0x00, spec->mem_base + 0x100);
8035 writeb(0xff, spec->mem_base + 0x304);
8036
8037 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
8038
8039 chipio_8051_write_direct(codec, 0x90, 0x00);
8040 chipio_8051_write_direct(codec, 0x90, 0x10);
8041
8042 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8043
8044 chipio_write(codec, 0x18b0a4, 0x000000c2);
8045
8046 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8047 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8048}
8049
e93ac30a
CM		 8050/*
8051 * Extra init functions for alternative ca0132 codecs. Done
8052 * here so they don't clutter up the main ca0132_init function
8053 * anymore than they have to.
8054 */
8055static void ca0132_alt_init(struct hda_codec *codec)
8056{
8057 struct ca0132_spec *spec = codec->spec;
8058
8059 ca0132_alt_vol_setup(codec);
8060
8061 switch (spec->quirk) {
8062 case QUIRK_SBZ:
8063 codec_dbg(codec, "SBZ alt_init");
8064 ca0132_gpio_init(codec);
8065 sbz_pre_dsp_setup(codec);
8066 snd_hda_sequence_write(codec, spec->chip_init_verbs);
e42c7c73 8067 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
e93ac30a
CM		 8068 break;
8069 case QUIRK_R3DI:
8070 codec_dbg(codec, "R3DI alt_init");
8071 ca0132_gpio_init(codec);
8072 ca0132_gpio_setup(codec);
7e6ed62e 8073 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 8074 r3di_pre_dsp_setup(codec);
8075 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8076 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
8077 break;
e42c7c73
CM		 8078 case QUIRK_R3D:
8079 r3d_pre_dsp_setup(codec);
8080 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8081 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8082 break;
03c9b6b1
CM		 8083 case QUIRK_AE5:
8084 ca0132_gpio_init(codec);
8085 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8086 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
8087 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8088 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
8089 chipio_write(codec, 0x18b030, 0x00000020);
8090 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8091 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8092 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8093 break;
e93ac30a
CM		 8094 }
8095}
8096
95c6e9cb
IM		 8097static int ca0132_init(struct hda_codec *codec)
8098{
8099 struct ca0132_spec *spec = codec->spec;
8100 struct auto_pin_cfg *cfg = &spec->autocfg;
8101 int i;
e93ac30a
CM		 8102 bool dsp_loaded;
8103
8104 /*
8105 * If the DSP is already downloaded, and init has been entered again,
8106 * there's only two reasons for it. One, the codec has awaken from a
8107 * suspended state, and in that case dspload_is_loaded will return
8108 * false, and the init will be ran again. The other reason it gets
8109 * re entered is on startup for some reason it triggers a suspend and
8110 * resume state. In this case, it will check if the DSP is downloaded,
8111 * and not run the init function again. For codecs using alt_functions,
8112 * it will check if the DSP is loaded properly.
8113 */
8114 if (spec->dsp_state == DSP_DOWNLOADED) {
8115 dsp_loaded = dspload_is_loaded(codec);
8116 if (!dsp_loaded) {
8117 spec->dsp_reload = true;
8118 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 8119 } else {
8120 if (spec->quirk == QUIRK_SBZ)
8121 sbz_dsp_startup_check(codec);
e93ac30a 8122 return 0;
38ba69ff 8123 }
e93ac30a 8124 }
95c6e9cb 8125
e24aa0a4
TI		 8126 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
8127 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 8128 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 8129
e42c7c73
CM		 8130 if (spec->use_pci_mmio)
8131 ca0132_mmio_init(codec);
e93ac30a 8132
664c7155 8133 snd_hda_power_up_pm(codec);
5aaca44d 8134
b9b41345
CM		 8135 if (spec->quirk == QUIRK_AE5)
8136 ae5_register_set(codec);
8137
f8fb1170 8138 ca0132_init_unsol(codec);
5aaca44d
IM		 8139 ca0132_init_params(codec);
8140 ca0132_init_flags(codec);
7e6ed62e 8141
5aaca44d 8142 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 8143
365c7f25 8144 if (spec->use_alt_functions)
e93ac30a
CM		 8145 ca0132_alt_init(codec);
8146
01ef7dbf 8147 ca0132_download_dsp(codec);
7e6ed62e 8148
5aaca44d 8149 ca0132_refresh_widget_caps(codec);
e93ac30a 8150
7e6ed62e
CM		 8151 switch (spec->quirk) {
8152 case QUIRK_R3DI:
c986f50c
CM		 8153 case QUIRK_R3D:
8154 r3d_setup_defaults(codec);
7e6ed62e 8155 break;
126b75e0 8156 case QUIRK_SBZ:
d97420d2 8157 sbz_setup_defaults(codec);
126b75e0 8158 break;
415cd844
CM		 8159 case QUIRK_AE5:
8160 ae5_setup_defaults(codec);
8161 break;
126b75e0 8162 default:
38ba69ff
CM		 8163 ca0132_setup_defaults(codec);
8164 ca0132_init_analog_mic2(codec);
8165 ca0132_init_dmic(codec);
7e6ed62e 8166 break;
38ba69ff 8167 }
5aaca44d
IM		 8168
8169 for (i = 0; i < spec->num_outputs; i++)
8170 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 8171
95c6e9cb
IM		 8172 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8173
8174 for (i = 0; i < spec->num_inputs; i++)
8175 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8176
8177 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8178
009b8f97 8179 if (!spec->use_alt_functions) {
e93ac30a
CM		 8180 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8181 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8182 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
8183 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8184 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
8185 }
8186
7cb9d94c 8187 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 8188 ca0132_gpio_setup(codec);
8189
d5c016b5 8190 snd_hda_sequence_write(codec, spec->spec_init_verbs);
d97420d2 8191 if (spec->use_alt_functions) {
7cb9d94c
CM		 8192 ca0132_alt_select_out(codec);
8193 ca0132_alt_select_in(codec);
d97420d2 8194 } else {
7cb9d94c
CM		 8195 ca0132_select_out(codec);
8196 ca0132_select_mic(codec);
7cb9d94c 8197 }
5aaca44d 8198
a73d511c
IM		 8199 snd_hda_jack_report_sync(codec);
8200
e93ac30a
CM		 8201 /*
8202 * Re set the PlayEnhancement switch on a resume event, because the
8203 * controls will not be reloaded.
8204 */
8205 if (spec->dsp_reload) {
8206 spec->dsp_reload = false;
8207 ca0132_pe_switch_set(codec);
8208 }
8209
664c7155 8210 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 8211
8212 return 0;
8213}
8214
7675a2a9
CM		 8215static int dbpro_init(struct hda_codec *codec)
8216{
8217 struct ca0132_spec *spec = codec->spec;
8218 struct auto_pin_cfg *cfg = &spec->autocfg;
8219 unsigned int i;
8220
8221 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8222 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8223
8224 for (i = 0; i < spec->num_inputs; i++)
8225 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8226
8227 return 0;
8228}
8229
95c6e9cb
IM		 8230static void ca0132_free(struct hda_codec *codec)
8231{
5aaca44d
IM		 8232 struct ca0132_spec *spec = codec->spec;
8233
993884f6 8234 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 8235 snd_hda_power_up(codec);
2e48b2b7
CM		 8236 switch (spec->quirk) {
8237 case QUIRK_SBZ:
8238 sbz_exit_chip(codec);
8239 break;
2f295f91
CM		 8240 case QUIRK_R3D:
8241 r3d_exit_chip(codec);
8242 break;
edb1b3ab
CM		 8243 case QUIRK_AE5:
8244 ae5_exit_chip(codec);
8245 break;
2e48b2b7
CM		 8246 case QUIRK_R3DI:
8247 r3di_gpio_shutdown(codec);
2e48b2b7
CM		 8248 break;
8249 }
2f295f91
CM		 8250
8251 snd_hda_sequence_write(codec, spec->base_exit_verbs);
8252 ca0132_exit_chip(codec);
8253
5aaca44d 8254 snd_hda_power_down(codec);
aa31704f
CM		 8255 if (spec->mem_base)
8256 iounmap(spec->mem_base);
d5c016b5 8257 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 8258 kfree(codec->spec);
8259}
8260
7675a2a9
CM		 8261static void dbpro_free(struct hda_codec *codec)
8262{
8263 struct ca0132_spec *spec = codec->spec;
8264
8265 zxr_dbpro_power_state_shutdown(codec);
8266
8267 kfree(spec->spec_init_verbs);
8268 kfree(codec->spec);
8269}
8270
2e48b2b7
CM		 8271static void ca0132_reboot_notify(struct hda_codec *codec)
8272{
8273 codec->patch_ops.free(codec);
8274}
8275
071f1344 8276static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 8277 .build_controls = ca0132_build_controls,
8278 .build_pcms = ca0132_build_pcms,
8279 .init = ca0132_init,
8280 .free = ca0132_free,
f8fb1170 8281 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 8282 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 8283};
8284
7675a2a9
CM		 8285static const struct hda_codec_ops dbpro_patch_ops = {
8286 .build_controls = dbpro_build_controls,
8287 .build_pcms = dbpro_build_pcms,
8288 .init = dbpro_init,
8289 .free = dbpro_free,
8290};
8291
441aa6a0
IM		 8292static void ca0132_config(struct hda_codec *codec)
8293{
8294 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 8295
8296 spec->dacs[0] = 0x2;
8297 spec->dacs[1] = 0x3;
8298 spec->dacs[2] = 0x4;
8299
8300 spec->multiout.dac_nids = spec->dacs;
8301 spec->multiout.num_dacs = 3;
441aa6a0 8302
009b8f97 8303 if (!spec->use_alt_functions)
63177afc
CM		 8304 spec->multiout.max_channels = 2;
8305 else
8306 spec->multiout.max_channels = 6;
8307
8308 switch (spec->quirk) {
8309 case QUIRK_ALIENWARE:
d06feaf0 8310 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
fe14f39e 8311 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
d06feaf0
CM		 8312 break;
8313 case QUIRK_SBZ:
8314 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
8315 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
8316 break;
6dcd7244
CM		 8317 case QUIRK_ZXR:
8318 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
8319 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
8320 break;
d06feaf0
CM		 8321 case QUIRK_R3D:
8322 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
8323 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
8324 break;
8325 case QUIRK_R3DI:
8326 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
8327 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8328 break;
8329 case QUIRK_AE5:
8330 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
8331 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8332 break;
8333 }
fe14f39e 8334
d06feaf0
CM		 8335 switch (spec->quirk) {
8336 case QUIRK_ALIENWARE:
fe14f39e
TI		 8337 spec->num_outputs = 2;
8338 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8339 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 8340 spec->shared_out_nid = 0x2;
8341 spec->unsol_tag_hp = 0x0f;
8342
8343 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8344 spec->adcs[1] = 0x8; /* analog mic2 */
8345 spec->adcs[2] = 0xa; /* what u hear */
8346
8347 spec->num_inputs = 3;
8348 spec->input_pins[0] = 0x12;
8349 spec->input_pins[1] = 0x11;
8350 spec->input_pins[2] = 0x13;
8351 spec->shared_mic_nid = 0x7;
8352 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 8353 break;
8354 case QUIRK_SBZ:
7f73df95 8355 case QUIRK_R3D:
63177afc
CM		 8356 spec->num_outputs = 2;
8357 spec->out_pins[0] = 0x0B; /* Line out */
8358 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8359 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8360 spec->out_pins[3] = 0x11; /* Rear surround */
8361 spec->shared_out_nid = 0x2;
8362 spec->unsol_tag_hp = spec->out_pins[1];
8363 spec->unsol_tag_front_hp = spec->out_pins[2];
8364
8365 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8366 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8367 spec->adcs[2] = 0xa; /* what u hear */
8368
8369 spec->num_inputs = 2;
8370 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8371 spec->input_pins[1] = 0x13; /* What U Hear */
8372 spec->shared_mic_nid = 0x7;
8373 spec->unsol_tag_amic1 = spec->input_pins[0];
8374
8375 /* SPDIF I/O */
8376 spec->dig_out = 0x05;
8377 spec->multiout.dig_out_nid = spec->dig_out;
6dcd7244
CM		 8378 spec->dig_in = 0x09;
8379 break;
8380 case QUIRK_ZXR:
8381 spec->num_outputs = 2;
8382 spec->out_pins[0] = 0x0B; /* Line out */
8383 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8384 spec->out_pins[2] = 0x10; /* Center/LFE */
8385 spec->out_pins[3] = 0x11; /* Rear surround */
8386 spec->shared_out_nid = 0x2;
8387 spec->unsol_tag_hp = spec->out_pins[1];
8388 spec->unsol_tag_front_hp = spec->out_pins[2];
8389
8390 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8391 spec->adcs[1] = 0x8; /* Not connected, no front mic */
8392 spec->adcs[2] = 0xa; /* what u hear */
8393
8394 spec->num_inputs = 2;
8395 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8396 spec->input_pins[1] = 0x13; /* What U Hear */
8397 spec->shared_mic_nid = 0x7;
8398 spec->unsol_tag_amic1 = spec->input_pins[0];
8399 break;
8400 case QUIRK_ZXR_DBPRO:
8401 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
8402
8403 spec->num_inputs = 1;
8404 spec->input_pins[0] = 0x11; /* RCA Line-in */
8405
8406 spec->dig_out = 0x05;
8407 spec->multiout.dig_out_nid = spec->dig_out;
8408
63177afc 8409 spec->dig_in = 0x09;
63177afc 8410 break;
d06feaf0
CM		 8411 case QUIRK_AE5:
8412 spec->num_outputs = 2;
8413 spec->out_pins[0] = 0x0B; /* Line out */
8414 spec->out_pins[1] = 0x11; /* Rear headphone out */
8415 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8416 spec->out_pins[3] = 0x0F; /* Rear surround */
8417 spec->shared_out_nid = 0x2;
8418 spec->unsol_tag_hp = spec->out_pins[1];
8419 spec->unsol_tag_front_hp = spec->out_pins[2];
8420
8421 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8422 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8423 spec->adcs[2] = 0xa; /* what u hear */
63177afc 8424
d06feaf0
CM		 8425 spec->num_inputs = 2;
8426 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8427 spec->input_pins[1] = 0x13; /* What U Hear */
8428 spec->shared_mic_nid = 0x7;
8429 spec->unsol_tag_amic1 = spec->input_pins[0];
8430
8431 /* SPDIF I/O */
8432 spec->dig_out = 0x05;
8433 spec->multiout.dig_out_nid = spec->dig_out;
8434 break;
8435 case QUIRK_R3DI:
63177afc
CM		 8436 spec->num_outputs = 2;
8437 spec->out_pins[0] = 0x0B; /* Line out */
8438 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8439 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8440 spec->out_pins[3] = 0x11; /* Rear surround */
8441 spec->shared_out_nid = 0x2;
8442 spec->unsol_tag_hp = spec->out_pins[1];
8443 spec->unsol_tag_front_hp = spec->out_pins[2];
8444
8445 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
8446 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
8447 spec->adcs[2] = 0x0a; /* what u hear */
8448
8449 spec->num_inputs = 2;
8450 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8451 spec->input_pins[1] = 0x13; /* What U Hear */
8452 spec->shared_mic_nid = 0x7;
8453 spec->unsol_tag_amic1 = spec->input_pins[0];
8454
8455 /* SPDIF I/O */
8456 spec->dig_out = 0x05;
8457 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 8458 break;
8459 default:
fe14f39e
TI		 8460 spec->num_outputs = 2;
8461 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8462 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 8463 spec->shared_out_nid = 0x2;
8464 spec->unsol_tag_hp = spec->out_pins[1];
8465
8466 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8467 spec->adcs[1] = 0x8; /* analog mic2 */
8468 spec->adcs[2] = 0xa; /* what u hear */
8469
8470 spec->num_inputs = 3;
8471 spec->input_pins[0] = 0x12;
8472 spec->input_pins[1] = 0x11;
8473 spec->input_pins[2] = 0x13;
8474 spec->shared_mic_nid = 0x7;
8475 spec->unsol_tag_amic1 = spec->input_pins[0];
8476
8477 /* SPDIF I/O */
8478 spec->dig_out = 0x05;
8479 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 8480 spec->dig_in = 0x09;
63177afc 8481 break;
d5c016b5 8482 }
441aa6a0
IM		 8483}
8484
d5c016b5
GM		 8485static int ca0132_prepare_verbs(struct hda_codec *codec)
8486{
8487/* Verbs + terminator (an empty element) */
a3d90d67 8488#define NUM_SPEC_VERBS 2
d5c016b5
GM		 8489 struct ca0132_spec *spec = codec->spec;
8490
8491 spec->chip_init_verbs = ca0132_init_verbs0;
88268ce8
CM		 8492 /*
8493 * Since desktop cards use pci_mmio, this can be used to determine
8494 * whether or not to use these verbs instead of a separate bool.
8495 */
8496 if (spec->use_pci_mmio)
e42c7c73 8497 spec->desktop_init_verbs = ca0132_init_verbs1;
6396bb22
KC		 8498 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
8499 sizeof(struct hda_verb),
8500 GFP_KERNEL);
d5c016b5
GM		 8501 if (!spec->spec_init_verbs)
8502 return -ENOMEM;
8503
d5c016b5 8504 /* config EAPD */
a3d90d67
AB		 8505 spec->spec_init_verbs[0].nid = 0x0b;
8506 spec->spec_init_verbs[0].param = 0x78D;
8507 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 8508
8509 /* Previously commented configuration */
8510 /*
a3d90d67
AB		 8511 spec->spec_init_verbs[2].nid = 0x0b;
8512 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8513 spec->spec_init_verbs[2].verb = 0x02;
8514
8515 spec->spec_init_verbs[3].nid = 0x10;
8516 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 8517 spec->spec_init_verbs[3].verb = 0x02;
8518
8519 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 8520 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 8521 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 8522 */
8523
8524 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8525 return 0;
8526}
8527
b29733db
CM		 8528/*
8529 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
8530 * Sound Blaster Z cards. However, they have different HDA codec subsystem
8531 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
8532 * daughter boards ID.
8533 */
8534static void sbz_detect_quirk(struct hda_codec *codec)
8535{
8536 struct ca0132_spec *spec = codec->spec;
8537
8538 switch (codec->core.subsystem_id) {
8539 case 0x11020033:
8540 spec->quirk = QUIRK_ZXR;
8541 break;
8542 case 0x1102003f:
8543 spec->quirk = QUIRK_ZXR_DBPRO;
8544 break;
8545 default:
8546 spec->quirk = QUIRK_SBZ;
8547 break;
8548 }
8549}
8550
95c6e9cb
IM		 8551static int patch_ca0132(struct hda_codec *codec)
8552{
8553 struct ca0132_spec *spec;
a73d511c 8554 int err;
d5c016b5 8555 const struct snd_pci_quirk *quirk;
95c6e9cb 8556
4e76a883 8557 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 8558
8559 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8560 if (!spec)
8561 return -ENOMEM;
8562 codec->spec = spec;
993884f6 8563 spec->codec = codec;
95c6e9cb 8564
225068ab
TI		 8565 codec->patch_ops = ca0132_patch_ops;
8566 codec->pcm_format_first = 1;
8567 codec->no_sticky_stream = 1;
8568
d5c016b5
GM		 8569 /* Detect codec quirk */
8570 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8571 if (quirk)
8572 spec->quirk = quirk->value;
8573 else
8574 spec->quirk = QUIRK_NONE;
8575
b29733db
CM		 8576 if (spec->quirk == QUIRK_SBZ)
8577 sbz_detect_quirk(codec);
8578
e24aa0a4 8579 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 8580 spec->num_mixers = 1;
017310fb
CM		 8581
8582 /* Set which mixers each quirk uses. */
8583 switch (spec->quirk) {
8584 case QUIRK_SBZ:
e25e3445 8585 spec->mixers[0] = desktop_mixer;
017310fb
CM		 8586 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8587 break;
7675a2a9
CM		 8588 case QUIRK_ZXR_DBPRO:
8589 codec->patch_ops = dbpro_patch_ops;
8590 break;
e25e3445
CM		 8591 case QUIRK_R3D:
8592 spec->mixers[0] = desktop_mixer;
8593 snd_hda_codec_set_name(codec, "Recon3D");
8594 break;
017310fb
CM		 8595 case QUIRK_R3DI:
8596 spec->mixers[0] = r3di_mixer;
8597 snd_hda_codec_set_name(codec, "Recon3Di");
8598 break;
88268ce8
CM		 8599 case QUIRK_AE5:
8600 spec->mixers[0] = desktop_mixer;
8601 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8602 break;
017310fb
CM		 8603 default:
8604 spec->mixers[0] = ca0132_mixer;
8605 break;
8606 }
a7e76271 8607
08eca6b1 8608 /* Setup whether or not to use alt functions/controls/pci_mmio */
009b8f97
CM		 8609 switch (spec->quirk) {
8610 case QUIRK_SBZ:
e42c7c73 8611 case QUIRK_R3D:
88268ce8 8612 case QUIRK_AE5:
08eca6b1
CM		 8613 spec->use_alt_controls = true;
8614 spec->use_alt_functions = true;
8615 spec->use_pci_mmio = true;
8616 break;
009b8f97 8617 case QUIRK_R3DI:
47cdf76e 8618 spec->use_alt_controls = true;
009b8f97 8619 spec->use_alt_functions = true;
08eca6b1 8620 spec->use_pci_mmio = false;
009b8f97
CM		 8621 break;
8622 default:
47cdf76e 8623 spec->use_alt_controls = false;
009b8f97 8624 spec->use_alt_functions = false;
08eca6b1 8625 spec->use_pci_mmio = false;
009b8f97
CM		 8626 break;
8627 }
8628
08eca6b1
CM		 8629 if (spec->use_pci_mmio) {
8630 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8631 if (spec->mem_base == NULL) {
8632 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8633 spec->quirk = QUIRK_NONE;
8634 }
8635 }
8636
5aaca44d
IM		 8637 spec->base_init_verbs = ca0132_base_init_verbs;
8638 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 8639
993884f6
CCC		 8640 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8641
95c6e9cb
IM		 8642 ca0132_init_chip(codec);
8643
8644 ca0132_config(codec);
8645
d5c016b5
GM		 8646 err = ca0132_prepare_verbs(codec);
8647 if (err < 0)
cc91ceaf 8648 goto error;
d5c016b5 8649
a73d511c
IM		 8650 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8651 if (err < 0)
cc91ceaf 8652 goto error;
a73d511c 8653
95c6e9cb 8654 return 0;
cc91ceaf
TI		 8655
8656 error:
8657 ca0132_free(codec);
8658 return err;
95c6e9cb
IM		 8659}
8660
8661/*
8662 * patch entries
8663 */
b9a94a9c
TI		 8664static struct hda_device_id snd_hda_id_ca0132[] = {
8665 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 8666 {} /* terminator */
8667};
b9a94a9c 8668MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 8669
8670MODULE_LICENSE("GPL");
406261ce 8671MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 8672
d8a766a1 8673static struct hda_codec_driver ca0132_driver = {
b9a94a9c 8674 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 8675};
8676
d8a766a1 8677module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)