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ALSA: hda/ca0132 - Merge post-dsp functions + cleanup
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb 34#include <sound/core.h>
be57bfff 35#include <sound/hda_codec.h>
95c6e9cb 36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
38ba69ff 52#define FLOAT_THREE 0x40400000
7cb9d94c 53#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 54#define FLOAT_MINUS_5 0xc0a00000
55
ef6b2ead
IM		 56#define UNSOL_TAG_DSP 0x16
57
4aa3bb0c
IM		 58#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
ef6b2ead
IM		 66#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 68
95c6e9cb
IM		 69#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
4aa3bb0c
IM		 72#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
01ef7dbf 83#define EFX_FILE "ctefx.bin"
7a928186 84#define DESKTOP_EFX_FILE "ctefx-desktop.bin"
8a19bcee 85#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 86
24f3cede 87#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 88MODULE_FIRMWARE(EFX_FILE);
7a928186 89MODULE_FIRMWARE(DESKTOP_EFX_FILE);
8a19bcee 90MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 91#endif
01ef7dbf 92
3a03f83b 93static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 94
7cb9d94c 95#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 96enum {
97 SPEAKER_OUT,
7cb9d94c
CM		 98 HEADPHONE_OUT,
99 SURROUND_OUT
ef6b2ead
IM		 100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
7cb9d94c 107/* Strings for Input Source Enum Control */
3a03f83b 108static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
ef6b2ead
IM		 116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
7cb9d94c
CM		 149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
155 MIC_BOOST_ENUM
ef6b2ead
IM		 156#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
157};
158
159/* Effects values size*/
160#define EFFECT_VALS_MAX_COUNT 12
161
47cdf76e
CM		 162/*
163 * Default values for the effect slider controls, they are in order of their
164 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
165 * X-bass.
166 */
167static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
168/* Amount of effect level sliders for ca0132_alt controls. */
169#define EFFECT_LEVEL_SLIDERS 5
170
e8412ca4
DR		 171/* Latency introduced by DSP blocks in milliseconds. */
172#define DSP_CAPTURE_INIT_LATENCY 0
173#define DSP_CRYSTAL_VOICE_LATENCY 124
174#define DSP_PLAYBACK_INIT_LATENCY 13
175#define DSP_PLAY_ENHANCEMENT_LATENCY 30
176#define DSP_SPEAKER_OUT_LATENCY 7
177
ef6b2ead 178struct ct_effect {
975cc02a 179 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 180 hda_nid_t nid;
181 int mid; /*effect module ID*/
182 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
183 int direct; /* 0:output; 1:input*/
184 int params; /* number of default non-on/off params */
185 /*effect default values, 1st is on/off. */
186 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
187};
188
189#define EFX_DIR_OUT 0
190#define EFX_DIR_IN 1
191
862154bb 192static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 193 { .name = "Surround",
194 .nid = SURROUND,
195 .mid = 0x96,
196 .reqs = {0, 1},
197 .direct = EFX_DIR_OUT,
198 .params = 1,
199 .def_vals = {0x3F800000, 0x3F2B851F}
200 },
201 { .name = "Crystalizer",
202 .nid = CRYSTALIZER,
203 .mid = 0x96,
204 .reqs = {7, 8},
205 .direct = EFX_DIR_OUT,
206 .params = 1,
207 .def_vals = {0x3F800000, 0x3F266666}
208 },
209 { .name = "Dialog Plus",
210 .nid = DIALOG_PLUS,
211 .mid = 0x96,
212 .reqs = {2, 3},
213 .direct = EFX_DIR_OUT,
214 .params = 1,
215 .def_vals = {0x00000000, 0x3F000000}
216 },
217 { .name = "Smart Volume",
218 .nid = SMART_VOLUME,
219 .mid = 0x96,
220 .reqs = {4, 5, 6},
221 .direct = EFX_DIR_OUT,
222 .params = 2,
223 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
224 },
225 { .name = "X-Bass",
226 .nid = X_BASS,
227 .mid = 0x96,
228 .reqs = {24, 23, 25},
229 .direct = EFX_DIR_OUT,
230 .params = 2,
231 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
232 },
233 { .name = "Equalizer",
234 .nid = EQUALIZER,
235 .mid = 0x96,
236 .reqs = {9, 10, 11, 12, 13, 14,
237 15, 16, 17, 18, 19, 20},
238 .direct = EFX_DIR_OUT,
239 .params = 11,
240 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
241 0x00000000, 0x00000000, 0x00000000, 0x00000000,
242 0x00000000, 0x00000000, 0x00000000, 0x00000000}
243 },
244 { .name = "Echo Cancellation",
245 .nid = ECHO_CANCELLATION,
246 .mid = 0x95,
247 .reqs = {0, 1, 2, 3},
248 .direct = EFX_DIR_IN,
249 .params = 3,
250 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
251 },
252 { .name = "Voice Focus",
253 .nid = VOICE_FOCUS,
254 .mid = 0x95,
255 .reqs = {6, 7, 8, 9},
256 .direct = EFX_DIR_IN,
257 .params = 3,
258 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
259 },
260 { .name = "Mic SVM",
261 .nid = MIC_SVM,
262 .mid = 0x95,
263 .reqs = {44, 45},
264 .direct = EFX_DIR_IN,
265 .params = 1,
266 .def_vals = {0x00000000, 0x3F3D70A4}
267 },
268 { .name = "Noise Reduction",
269 .nid = NOISE_REDUCTION,
270 .mid = 0x95,
271 .reqs = {4, 5},
272 .direct = EFX_DIR_IN,
273 .params = 1,
274 .def_vals = {0x3F800000, 0x3F000000}
275 },
276 { .name = "VoiceFX",
277 .nid = VOICEFX,
278 .mid = 0x95,
279 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
280 .direct = EFX_DIR_IN,
281 .params = 8,
282 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
283 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
284 0x00000000}
285 }
286};
287
288/* Tuning controls */
289#ifdef ENABLE_TUNING_CONTROLS
290
291enum {
292#define TUNING_CTL_START_NID 0xC0
293 WEDGE_ANGLE = TUNING_CTL_START_NID,
294 SVM_LEVEL,
295 EQUALIZER_BAND_0,
296 EQUALIZER_BAND_1,
297 EQUALIZER_BAND_2,
298 EQUALIZER_BAND_3,
299 EQUALIZER_BAND_4,
300 EQUALIZER_BAND_5,
301 EQUALIZER_BAND_6,
302 EQUALIZER_BAND_7,
303 EQUALIZER_BAND_8,
304 EQUALIZER_BAND_9,
305 TUNING_CTL_END_NID
306#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
307};
308
309struct ct_tuning_ctl {
975cc02a 310 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 311 hda_nid_t parent_nid;
312 hda_nid_t nid;
313 int mid; /*effect module ID*/
314 int req; /*effect module request*/
315 int direct; /* 0:output; 1:input*/
316 unsigned int def_val;/*effect default values*/
317};
318
862154bb 319static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 320 { .name = "Wedge Angle",
321 .parent_nid = VOICE_FOCUS,
322 .nid = WEDGE_ANGLE,
323 .mid = 0x95,
324 .req = 8,
325 .direct = EFX_DIR_IN,
326 .def_val = 0x41F00000
327 },
328 { .name = "SVM Level",
329 .parent_nid = MIC_SVM,
330 .nid = SVM_LEVEL,
331 .mid = 0x95,
332 .req = 45,
333 .direct = EFX_DIR_IN,
334 .def_val = 0x3F3D70A4
335 },
336 { .name = "EQ Band0",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_0,
339 .mid = 0x96,
340 .req = 11,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
343 },
344 { .name = "EQ Band1",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_1,
347 .mid = 0x96,
348 .req = 12,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
351 },
352 { .name = "EQ Band2",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_2,
355 .mid = 0x96,
356 .req = 13,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
359 },
360 { .name = "EQ Band3",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_3,
363 .mid = 0x96,
364 .req = 14,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
367 },
368 { .name = "EQ Band4",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_4,
371 .mid = 0x96,
372 .req = 15,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
375 },
376 { .name = "EQ Band5",
377 .parent_nid = EQUALIZER,
378 .nid = EQUALIZER_BAND_5,
379 .mid = 0x96,
380 .req = 16,
381 .direct = EFX_DIR_OUT,
382 .def_val = 0x00000000
383 },
384 { .name = "EQ Band6",
385 .parent_nid = EQUALIZER,
386 .nid = EQUALIZER_BAND_6,
387 .mid = 0x96,
388 .req = 17,
389 .direct = EFX_DIR_OUT,
390 .def_val = 0x00000000
391 },
392 { .name = "EQ Band7",
393 .parent_nid = EQUALIZER,
394 .nid = EQUALIZER_BAND_7,
395 .mid = 0x96,
396 .req = 18,
397 .direct = EFX_DIR_OUT,
398 .def_val = 0x00000000
399 },
400 { .name = "EQ Band8",
401 .parent_nid = EQUALIZER,
402 .nid = EQUALIZER_BAND_8,
403 .mid = 0x96,
404 .req = 19,
405 .direct = EFX_DIR_OUT,
406 .def_val = 0x00000000
407 },
408 { .name = "EQ Band9",
409 .parent_nid = EQUALIZER,
410 .nid = EQUALIZER_BAND_9,
411 .mid = 0x96,
412 .req = 20,
413 .direct = EFX_DIR_OUT,
414 .def_val = 0x00000000
415 }
416};
417#endif
418
419/* Voice FX Presets */
420#define VOICEFX_MAX_PARAM_COUNT 9
421
422struct ct_voicefx {
423 char *name;
424 hda_nid_t nid;
425 int mid;
426 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
427};
428
429struct ct_voicefx_preset {
430 char *name; /*preset name*/
431 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
432};
433
862154bb 434static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 435 .name = "VoiceFX Capture Switch",
436 .nid = VOICEFX,
437 .mid = 0x95,
438 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
439};
440
862154bb 441static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 442 { .name = "Neutral",
443 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
444 0x44FA0000, 0x3F800000, 0x3F800000,
445 0x3F800000, 0x00000000, 0x00000000 }
446 },
447 { .name = "Female2Male",
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3F19999A, 0x3F866666,
450 0x3F800000, 0x00000000, 0x00000000 }
451 },
452 { .name = "Male2Female",
453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
454 0x450AC000, 0x4017AE14, 0x3F6B851F,
455 0x3F800000, 0x00000000, 0x00000000 }
456 },
457 { .name = "ScrappyKid",
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x40400000, 0x3F28F5C3,
460 0x3F800000, 0x00000000, 0x00000000 }
461 },
462 { .name = "Elderly",
463 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
464 0x44E10000, 0x3FB33333, 0x3FB9999A,
465 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 },
467 { .name = "Orc",
468 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
469 0x45098000, 0x3F266666, 0x3FC00000,
470 0x3F800000, 0x00000000, 0x00000000 }
471 },
472 { .name = "Elf",
473 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
474 0x45193000, 0x3F8E147B, 0x3F75C28F,
475 0x3F800000, 0x00000000, 0x00000000 }
476 },
477 { .name = "Dwarf",
478 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
479 0x45007000, 0x3F451EB8, 0x3F7851EC,
480 0x3F800000, 0x00000000, 0x00000000 }
481 },
482 { .name = "AlienBrute",
483 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
484 0x451F6000, 0x3F266666, 0x3FA7D945,
485 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 },
487 { .name = "Robot",
488 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
489 0x44FA0000, 0x3FB2718B, 0x3F800000,
490 0xBC07010E, 0x00000000, 0x00000000 }
491 },
492 { .name = "Marine",
493 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
494 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
495 0x3F0A3D71, 0x00000000, 0x00000000 }
496 },
497 { .name = "Emo",
498 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
499 0x44FA0000, 0x3F800000, 0x3F800000,
500 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 },
502 { .name = "DeepVoice",
503 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
504 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
505 0x3F800000, 0x00000000, 0x00000000 }
506 },
507 { .name = "Munchkin",
508 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
509 0x44FA0000, 0x3F800000, 0x3F1A043C,
510 0x3F800000, 0x00000000, 0x00000000 }
511 }
512};
513
47cdf76e
CM		 514/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
515
516#define EQ_PRESET_MAX_PARAM_COUNT 11
517
518struct ct_eq {
519 char *name;
520 hda_nid_t nid;
521 int mid;
522 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
523};
524
525struct ct_eq_preset {
526 char *name; /*preset name*/
527 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
528};
529
862154bb 530static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 531 .name = "FX: Equalizer Preset Switch",
532 .nid = EQ_PRESET_ENUM,
533 .mid = 0x96,
534 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
535};
536
537
862154bb 538static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 539 { .name = "Flat",
540 .vals = { 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000, 0x00000000,
542 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000 }
544 },
545 { .name = "Acoustic",
546 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
547 0x40000000, 0x00000000, 0x00000000,
548 0x00000000, 0x00000000, 0x40000000,
549 0x40000000, 0x40000000 }
550 },
551 { .name = "Classical",
552 .vals = { 0x00000000, 0x00000000, 0x40C00000,
553 0x40C00000, 0x40466666, 0x00000000,
554 0x00000000, 0x00000000, 0x00000000,
555 0x40466666, 0x40466666 }
556 },
557 { .name = "Country",
558 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
559 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
560 0x00000000, 0x00000000, 0x40000000,
561 0x40466666, 0x40800000 }
562 },
563 { .name = "Dance",
564 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
565 0x40466666, 0x40866666, 0xBF99999A,
566 0xBF99999A, 0x00000000, 0x00000000,
567 0x40800000, 0x40800000 }
568 },
569 { .name = "Jazz",
570 .vals = { 0x00000000, 0x00000000, 0x00000000,
571 0x3F8CCCCD, 0x40800000, 0x40800000,
572 0x40800000, 0x00000000, 0x3F8CCCCD,
573 0x40466666, 0x40466666 }
574 },
575 { .name = "New Age",
576 .vals = { 0x00000000, 0x00000000, 0x40000000,
577 0x40000000, 0x00000000, 0x00000000,
578 0x00000000, 0x3F8CCCCD, 0x40000000,
579 0x40000000, 0x40000000 }
580 },
581 { .name = "Pop",
582 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
583 0x40000000, 0x40000000, 0x00000000,
584 0xBF99999A, 0xBF99999A, 0x00000000,
585 0x40466666, 0x40C00000 }
586 },
587 { .name = "Rock",
588 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
589 0x3F8CCCCD, 0x40000000, 0xBF99999A,
590 0xBF99999A, 0x00000000, 0x00000000,
591 0x40800000, 0x40800000 }
592 },
593 { .name = "Vocal",
594 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
595 0xBF99999A, 0x00000000, 0x40466666,
596 0x40800000, 0x40466666, 0x00000000,
597 0x00000000, 0x3F8CCCCD }
598 }
599};
600
7cb9d94c
CM		 601/* DSP command sequences for ca0132_alt_select_out */
602#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
603struct ca0132_alt_out_set {
604 char *name; /*preset name*/
605 unsigned char commands;
606 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
607 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
608 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
609};
610
611static const struct ca0132_alt_out_set alt_out_presets[] = {
612 { .name = "Line Out",
613 .commands = 7,
614 .mids = { 0x96, 0x96, 0x96, 0x8F,
615 0x96, 0x96, 0x96 },
616 .reqs = { 0x19, 0x17, 0x18, 0x01,
617 0x1F, 0x15, 0x3A },
618 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
619 0x00000000, 0x00000000, 0x00000000,
620 0x00000000 }
621 },
622 { .name = "Headphone",
623 .commands = 7,
624 .mids = { 0x96, 0x96, 0x96, 0x8F,
625 0x96, 0x96, 0x96 },
626 .reqs = { 0x19, 0x17, 0x18, 0x01,
627 0x1F, 0x15, 0x3A },
628 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
629 0x00000000, 0x00000000, 0x00000000,
630 0x00000000 }
631 },
632 { .name = "Surround",
633 .commands = 8,
634 .mids = { 0x96, 0x8F, 0x96, 0x96,
635 0x96, 0x96, 0x96, 0x96 },
636 .reqs = { 0x18, 0x01, 0x1F, 0x15,
637 0x3A, 0x1A, 0x1B, 0x1C },
638 .vals = { 0x00000000, 0x00000000, 0x00000000,
639 0x00000000, 0x00000000, 0x00000000,
640 0x00000000, 0x00000000 }
641 }
642};
643
017310fb
CM		 644/*
645 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
646 * and I don't know what the third req is, but it's always zero. I assume it's
647 * some sort of update or set command to tell the DSP there's new volume info.
648 */
649#define DSP_VOL_OUT 0
650#define DSP_VOL_IN 1
651
652struct ct_dsp_volume_ctl {
653 hda_nid_t vnid;
654 int mid; /* module ID*/
655 unsigned int reqs[3]; /* scp req ID */
656};
657
862154bb 658static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 659 { .vnid = VNID_SPK,
660 .mid = 0x32,
661 .reqs = {3, 4, 2}
662 },
663 { .vnid = VNID_MIC,
664 .mid = 0x37,
665 .reqs = {2, 3, 1}
666 }
667};
668
95c6e9cb
IM		 669enum hda_cmd_vendor_io {
670 /* for DspIO node */
671 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
672 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
673
674 VENDOR_DSPIO_STATUS = 0xF01,
675 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
676 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
677 VENDOR_DSPIO_DSP_INIT = 0x703,
678 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
679 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
680
681 /* for ChipIO node */
682 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
683 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
684 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
685 VENDOR_CHIPIO_DATA_LOW = 0x300,
686 VENDOR_CHIPIO_DATA_HIGH = 0x400,
687
bf85a91c
CM		 688 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
689 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
690
95c6e9cb
IM		 691 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
692 VENDOR_CHIPIO_STATUS = 0xF01,
693 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
694 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
695
4aa3bb0c
IM		 696 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
697 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
bf85a91c
CM		 698 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
699 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
700 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
4aa3bb0c 701
95c6e9cb 702 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 703 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 704
705 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
706 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
707 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
708 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
709 VENDOR_CHIPIO_FLAG_SET = 0x70F,
710 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 711 VENDOR_CHIPIO_PARAM_SET = 0x710,
712 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 713
714 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
715 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
716 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
717 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
718
4aa3bb0c
IM		 719 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
720 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
721 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
722 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
723
724 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
725 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
726 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
727 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
728 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
729 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
730
731 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 732};
733
734/*
735 * Control flag IDs
736 */
737enum control_flag_id {
738 /* Connection manager stream setup is bypassed/enabled */
739 CONTROL_FLAG_C_MGR = 0,
740 /* DSP DMA is bypassed/enabled */
741 CONTROL_FLAG_DMA = 1,
742 /* 8051 'idle' mode is disabled/enabled */
743 CONTROL_FLAG_IDLE_ENABLE = 2,
744 /* Tracker for the SPDIF-in path is bypassed/enabled */
745 CONTROL_FLAG_TRACKER = 3,
746 /* DigitalOut to Spdif2Out connection is disabled/enabled */
747 CONTROL_FLAG_SPDIF2OUT = 4,
748 /* Digital Microphone is disabled/enabled */
749 CONTROL_FLAG_DMIC = 5,
750 /* ADC_B rate is 48 kHz/96 kHz */
751 CONTROL_FLAG_ADC_B_96KHZ = 6,
752 /* ADC_C rate is 48 kHz/96 kHz */
753 CONTROL_FLAG_ADC_C_96KHZ = 7,
754 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
755 CONTROL_FLAG_DAC_96KHZ = 8,
756 /* DSP rate is 48 kHz/96 kHz */
757 CONTROL_FLAG_DSP_96KHZ = 9,
758 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
759 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
760 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
761 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
762 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
763 CONTROL_FLAG_DECODE_LOOP = 12,
764 /* De-emphasis filter on DAC-1 disabled/enabled */
765 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
766 /* De-emphasis filter on DAC-2 disabled/enabled */
767 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
768 /* De-emphasis filter on DAC-3 disabled/enabled */
769 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
770 /* High-pass filter on ADC_B disabled/enabled */
771 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
772 /* High-pass filter on ADC_C disabled/enabled */
773 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
774 /* Common mode on Port_A disabled/enabled */
775 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
776 /* Common mode on Port_D disabled/enabled */
777 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
778 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
779 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
780 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 781 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 782 /* ASI rate is 48kHz/96kHz */
783 CONTROL_FLAG_ASI_96KHZ = 22,
784 /* DAC power settings able to control attached ports no/yes */
785 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
786 /* Clock Stop OK reporting is disabled/enabled */
787 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
788 /* Number of control flags */
789 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
790};
791
792/*
793 * Control parameter IDs
794 */
4aa3bb0c 795enum control_param_id {
ef6b2ead
IM		 796 /* 0: None, 1: Mic1In*/
797 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 798 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
799 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 800 /* Port A output stage gain setting to use when 16 Ohm output
801 * impedance is selected*/
802 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
803 /* Port D output stage gain setting to use when 16 Ohm output
804 * impedance is selected*/
805 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb 806
bf85a91c
CM		 807 /*
808 * This control param name was found in the 8051 memory, and makes
809 * sense given the fact the AE-5 uses it and has the ASI flag set.
810 */
811 CONTROL_PARAM_ASI = 23,
812
95c6e9cb
IM		 813 /* Stream Control */
814
815 /* Select stream with the given ID */
816 CONTROL_PARAM_STREAM_ID = 24,
817 /* Source connection point for the selected stream */
818 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
819 /* Destination connection point for the selected stream */
820 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
821 /* Number of audio channels in the selected stream */
822 CONTROL_PARAM_STREAMS_CHANNELS = 27,
823 /*Enable control for the selected stream */
824 CONTROL_PARAM_STREAM_CONTROL = 28,
825
826 /* Connection Point Control */
827
828 /* Select connection point with the given ID */
829 CONTROL_PARAM_CONN_POINT_ID = 29,
830 /* Connection point sample rate */
831 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
832
833 /* Node Control */
834
835 /* Select HDA node with the given ID */
836 CONTROL_PARAM_NODE_ID = 31
837};
838
839/*
840 * Dsp Io Status codes
841 */
842enum hda_vendor_status_dspio {
843 /* Success */
844 VENDOR_STATUS_DSPIO_OK = 0x00,
845 /* Busy, unable to accept new command, the host must retry */
846 VENDOR_STATUS_DSPIO_BUSY = 0x01,
847 /* SCP command queue is full */
848 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
849 /* SCP response queue is empty */
850 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
851};
852
853/*
854 * Chip Io Status codes
855 */
856enum hda_vendor_status_chipio {
857 /* Success */
858 VENDOR_STATUS_CHIPIO_OK = 0x00,
859 /* Busy, unable to accept new command, the host must retry */
860 VENDOR_STATUS_CHIPIO_BUSY = 0x01
861};
862
863/*
864 * CA0132 sample rate
865 */
866enum ca0132_sample_rate {
867 SR_6_000 = 0x00,
868 SR_8_000 = 0x01,
869 SR_9_600 = 0x02,
870 SR_11_025 = 0x03,
871 SR_16_000 = 0x04,
872 SR_22_050 = 0x05,
873 SR_24_000 = 0x06,
874 SR_32_000 = 0x07,
875 SR_44_100 = 0x08,
876 SR_48_000 = 0x09,
877 SR_88_200 = 0x0A,
878 SR_96_000 = 0x0B,
879 SR_144_000 = 0x0C,
880 SR_176_400 = 0x0D,
881 SR_192_000 = 0x0E,
882 SR_384_000 = 0x0F,
883
884 SR_COUNT = 0x10,
885
886 SR_RATE_UNKNOWN = 0x1F
887};
888
01ef7dbf
IM		 889enum dsp_download_state {
890 DSP_DOWNLOAD_FAILED = -1,
891 DSP_DOWNLOAD_INIT = 0,
892 DSP_DOWNLOADING = 1,
893 DSP_DOWNLOADED = 2
894};
895
01ef7dbf
IM		 896/* retrieve parameters from hda format */
897#define get_hdafmt_chs(fmt) (fmt & 0xf)
898#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
899#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
900#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
901
902/*
903 * CA0132 specific
904 */
905
906struct ca0132_spec {
b0eaa072 907 const struct snd_kcontrol_new *mixers[5];
a7e76271 908 unsigned int num_mixers;
5aaca44d
IM		 909 const struct hda_verb *base_init_verbs;
910 const struct hda_verb *base_exit_verbs;
d5c016b5 911 const struct hda_verb *chip_init_verbs;
e42c7c73 912 const struct hda_verb *desktop_init_verbs;
d5c016b5 913 struct hda_verb *spec_init_verbs;
01ef7dbf 914 struct auto_pin_cfg autocfg;
5aaca44d
IM		 915
916 /* Nodes configurations */
01ef7dbf
IM		 917 struct hda_multi_out multiout;
918 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
919 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 920 unsigned int num_outputs;
01ef7dbf
IM		 921 hda_nid_t input_pins[AUTO_PIN_LAST];
922 hda_nid_t adcs[AUTO_PIN_LAST];
923 hda_nid_t dig_out;
924 hda_nid_t dig_in;
925 unsigned int num_inputs;
a7e76271
IM		 926 hda_nid_t shared_mic_nid;
927 hda_nid_t shared_out_nid;
d5c016b5 928 hda_nid_t unsol_tag_hp;
63177afc 929 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 930 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 931
932 /* chip access */
933 struct mutex chipio_mutex; /* chip access mutex */
934 u32 curr_chip_addx;
935
936 /* DSP download related */
937 enum dsp_download_state dsp_state;
938 unsigned int dsp_stream_id;
939 unsigned int wait_scp;
940 unsigned int wait_scp_header;
941 unsigned int wait_num_data;
942 unsigned int scp_resp_header;
943 unsigned int scp_resp_data[4];
944 unsigned int scp_resp_count;
8a19bcee 945 bool alt_firmware_present;
38ba69ff 946 bool startup_check_entered;
e93ac30a 947 bool dsp_reload;
5aaca44d
IM		 948
949 /* mixer and effects related */
950 unsigned char dmic_ctl;
951 int cur_out_type;
952 int cur_mic_type;
953 long vnode_lvol[VNODES_COUNT];
954 long vnode_rvol[VNODES_COUNT];
955 long vnode_lswitch[VNODES_COUNT];
956 long vnode_rswitch[VNODES_COUNT];
957 long effects_switch[EFFECTS_COUNT];
958 long voicefx_val;
959 long cur_mic_boost;
7cb9d94c
CM		 960 /* ca0132_alt control related values */
961 unsigned char in_enum_val;
962 unsigned char out_enum_val;
47cdf76e
CM		 963 unsigned char mic_boost_enum_val;
964 unsigned char smart_volume_setting;
965 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
966 long xbass_xover_freq;
967 long eq_preset_val;
968 unsigned int tlv[4];
969 struct hda_vmaster_mute_hook vmaster_mute;
970
44f0c978 971
993884f6
CCC		 972 struct hda_codec *codec;
973 struct delayed_work unsol_hp_work;
d5c016b5 974 int quirk;
993884f6 975
44f0c978
IM		 976#ifdef ENABLE_TUNING_CONTROLS
977 long cur_ctl_vals[TUNING_CTLS_COUNT];
978#endif
aa31704f 979 /*
08eca6b1
CM		 980 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
981 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
982 * things.
aa31704f 983 */
08eca6b1 984 bool use_pci_mmio;
aa31704f 985 void __iomem *mem_base;
009b8f97
CM		 986
987 /*
988 * Whether or not to use the alt functions like alt_select_out,
989 * alt_select_in, etc. Only used on desktop codecs for now, because of
990 * surround sound support.
991 */
992 bool use_alt_functions;
47cdf76e
CM		 993
994 /*
995 * Whether or not to use alt controls: volume effect sliders, EQ
996 * presets, smart volume presets, and new control names with FX prefix.
997 * Renames PlayEnhancement and CrystalVoice too.
998 */
999 bool use_alt_controls;
01ef7dbf
IM		 1000};
1001
d5c016b5
GM		 1002/*
1003 * CA0132 quirks table
1004 */
1005enum {
1006 QUIRK_NONE,
1007 QUIRK_ALIENWARE,
a57a46b9 1008 QUIRK_ALIENWARE_M17XR4,
8a19bcee
CM		 1009 QUIRK_SBZ,
1010 QUIRK_R3DI,
8f8c523c 1011 QUIRK_R3D,
f6276463 1012 QUIRK_AE5,
d5c016b5
GM		 1013};
1014
fe14f39e
TI		 1015static const struct hda_pintbl alienware_pincfgs[] = {
1016 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1017 { 0x0c, 0x411111f0 }, /* N/A */
1018 { 0x0d, 0x411111f0 }, /* N/A */
1019 { 0x0e, 0x411111f0 }, /* N/A */
1020 { 0x0f, 0x0321101f }, /* HP */
1021 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1022 { 0x11, 0x03a11021 }, /* Mic */
1023 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1024 { 0x13, 0x411111f0 }, /* N/A */
1025 { 0x18, 0x411111f0 }, /* N/A */
1026 {}
1027};
1028
63177afc
CM		 1029/* Sound Blaster Z pin configs taken from Windows Driver */
1030static const struct hda_pintbl sbz_pincfgs[] = {
1031 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1032 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1033 { 0x0d, 0x014510f0 }, /* Digital Out */
1034 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1035 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1036 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1037 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1038 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1039 { 0x13, 0x908700f0 }, /* What U Hear In*/
1040 { 0x18, 0x50d000f0 }, /* N/A */
1041 {}
1042};
1043
7f73df95
CM		 1044/* Recon3D pin configs taken from Windows Driver */
1045static const struct hda_pintbl r3d_pincfgs[] = {
1046 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1047 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1048 { 0x0d, 0x014510f0 }, /* Digital Out */
1049 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1050 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1051 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1052 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1053 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1054 { 0x13, 0x908700f0 }, /* What U Hear In*/
1055 { 0x18, 0x50d000f0 }, /* N/A */
1056 {}
1057};
1058
d06feaf0
CM		 1059/* Sound Blaster AE-5 pin configs taken from Windows Driver */
1060static const struct hda_pintbl ae5_pincfgs[] = {
1061 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1062 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1063 { 0x0d, 0x014510f0 }, /* Digital Out */
1064 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1065 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1066 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1067 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1068 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1069 { 0x13, 0x908700f0 }, /* What U Hear In*/
1070 { 0x18, 0x50d000f0 }, /* N/A */
1071 {}
1072};
1073
63177afc
CM		 1074/* Recon3D integrated pin configs taken from Windows Driver */
1075static const struct hda_pintbl r3di_pincfgs[] = {
1076 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1077 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1078 { 0x0d, 0x014510f0 }, /* Digital Out */
1079 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1080 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1081 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1082 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1083 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1084 { 0x13, 0x908700f0 }, /* What U Hear In*/
1085 { 0x18, 0x500000f0 }, /* N/A */
1086 {}
1087};
1088
d5c016b5 1089static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1090 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1091 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1092 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1093 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1094 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1095 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1096 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1097 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1098 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
8f8c523c 1099 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
f6276463 1100 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
d5c016b5
GM		 1101 {}
1102};
1103
01ef7dbf
IM		 1104/*
1105 * CA0132 codec access
1106 */
399ae725 1107static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1108 unsigned int verb, unsigned int parm, unsigned int *res)
1109{
1110 unsigned int response;
1111 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1112 *res = response;
1113
1114 return ((response == -1) ? -1 : 0);
1115}
1116
1117static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1118 unsigned short converter_format, unsigned int *res)
1119{
1120 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1121 converter_format & 0xffff, res);
1122}
1123
1124static int codec_set_converter_stream_channel(struct hda_codec *codec,
1125 hda_nid_t nid, unsigned char stream,
1126 unsigned char channel, unsigned int *res)
1127{
1128 unsigned char converter_stream_channel = 0;
1129
1130 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1131 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1132 converter_stream_channel, res);
1133}
1134
1135/* Chip access helper function */
1136static int chipio_send(struct hda_codec *codec,
1137 unsigned int reg,
1138 unsigned int data)
1139{
1140 unsigned int res;
6d67530e 1141 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1142
1143 /* send bits of data specified by reg */
1144 do {
1145 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1146 reg, data);
1147 if (res == VENDOR_STATUS_CHIPIO_OK)
1148 return 0;
6d67530e
IM		 1149 msleep(20);
1150 } while (time_before(jiffies, timeout));
1151
01ef7dbf
IM		 1152 return -EIO;
1153}
1154
1155/*
1156 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1157 */
1158static int chipio_write_address(struct hda_codec *codec,
1159 unsigned int chip_addx)
1160{
4861af80 1161 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1162 int res;
1163
4861af80
IM		 1164 if (spec->curr_chip_addx == chip_addx)
1165 return 0;
1166
01ef7dbf
IM		 1167 /* send low 16 bits of the address */
1168 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1169 chip_addx & 0xffff);
1170
1171 if (res != -EIO) {
1172 /* send high 16 bits of the address */
1173 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1174 chip_addx >> 16);
1175 }
1176
d1600401 1177 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1178
4861af80 1179 return res;
01ef7dbf
IM		 1180}
1181
1182/*
1183 * Write data through the vendor widget -- NOT protected by the Mutex!
1184 */
01ef7dbf
IM		 1185static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1186{
5aaca44d 1187 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1188 int res;
1189
1190 /* send low 16 bits of the data */
1191 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1192
1193 if (res != -EIO) {
1194 /* send high 16 bits of the data */
1195 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1196 data >> 16);
1197 }
1198
5aaca44d
IM		 1199 /*If no error encountered, automatically increment the address
1200 as per chip behaviour*/
1201 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1202 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1203 return res;
1204}
1205
d5c21b88
IM		 1206/*
1207 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1208 */
01ef7dbf
IM		 1209static int chipio_write_data_multiple(struct hda_codec *codec,
1210 const u32 *data,
1211 unsigned int count)
1212{
1213 int status = 0;
1214
1215 if (data == NULL) {
4e76a883 1216 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1217 return -EINVAL;
1218 }
1219
1220 while ((count-- != 0) && (status == 0))
1221 status = chipio_write_data(codec, *data++);
1222
1223 return status;
1224}
1225
1226
1227/*
1228 * Read data through the vendor widget -- NOT protected by the Mutex!
1229 */
1230static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1231{
5aaca44d 1232 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1233 int res;
1234
1235 /* post read */
1236 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1237
1238 if (res != -EIO) {
1239 /* read status */
1240 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1241 }
1242
1243 if (res != -EIO) {
1244 /* read data */
1245 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1246 VENDOR_CHIPIO_HIC_READ_DATA,
1247 0);
1248 }
1249
5aaca44d
IM		 1250 /*If no error encountered, automatically increment the address
1251 as per chip behaviour*/
1252 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1253 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1254 return res;
1255}
1256
1257/*
1258 * Write given value to the given address through the chip I/O widget.
1259 * protected by the Mutex
1260 */
1261static int chipio_write(struct hda_codec *codec,
1262 unsigned int chip_addx, const unsigned int data)
1263{
1264 struct ca0132_spec *spec = codec->spec;
1265 int err;
1266
1267 mutex_lock(&spec->chipio_mutex);
1268
1269 /* write the address, and if successful proceed to write data */
1270 err = chipio_write_address(codec, chip_addx);
1271 if (err < 0)
1272 goto exit;
1273
1274 err = chipio_write_data(codec, data);
1275 if (err < 0)
1276 goto exit;
1277
1278exit:
1279 mutex_unlock(&spec->chipio_mutex);
1280 return err;
1281}
1282
38ba69ff
CM		 1283/*
1284 * Write given value to the given address through the chip I/O widget.
1285 * not protected by the Mutex
1286 */
1287static int chipio_write_no_mutex(struct hda_codec *codec,
1288 unsigned int chip_addx, const unsigned int data)
1289{
1290 int err;
1291
1292
1293 /* write the address, and if successful proceed to write data */
1294 err = chipio_write_address(codec, chip_addx);
1295 if (err < 0)
1296 goto exit;
1297
1298 err = chipio_write_data(codec, data);
1299 if (err < 0)
1300 goto exit;
1301
1302exit:
1303 return err;
1304}
1305
d5c21b88
IM		 1306/*
1307 * Write multiple values to the given address through the chip I/O widget.
1308 * protected by the Mutex
1309 */
01ef7dbf
IM		 1310static int chipio_write_multiple(struct hda_codec *codec,
1311 u32 chip_addx,
1312 const u32 *data,
1313 unsigned int count)
1314{
1315 struct ca0132_spec *spec = codec->spec;
1316 int status;
1317
1318 mutex_lock(&spec->chipio_mutex);
4861af80 1319 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1320 if (status < 0)
1321 goto error;
1322
1323 status = chipio_write_data_multiple(codec, data, count);
1324error:
1325 mutex_unlock(&spec->chipio_mutex);
1326
1327 return status;
1328}
1329
1330/*
1331 * Read the given address through the chip I/O widget
1332 * protected by the Mutex
1333 */
1334static int chipio_read(struct hda_codec *codec,
1335 unsigned int chip_addx, unsigned int *data)
1336{
1337 struct ca0132_spec *spec = codec->spec;
1338 int err;
1339
1340 mutex_lock(&spec->chipio_mutex);
1341
1342 /* write the address, and if successful proceed to write data */
1343 err = chipio_write_address(codec, chip_addx);
1344 if (err < 0)
1345 goto exit;
1346
1347 err = chipio_read_data(codec, data);
1348 if (err < 0)
1349 goto exit;
1350
1351exit:
1352 mutex_unlock(&spec->chipio_mutex);
1353 return err;
1354}
1355
d5c21b88
IM		 1356/*
1357 * Set chip control flags through the chip I/O widget.
1358 */
01ef7dbf
IM		 1359static void chipio_set_control_flag(struct hda_codec *codec,
1360 enum control_flag_id flag_id,
1361 bool flag_state)
1362{
1363 unsigned int val;
1364 unsigned int flag_bit;
1365
1366 flag_bit = (flag_state ? 1 : 0);
1367 val = (flag_bit << 7) | (flag_id);
1368 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1369 VENDOR_CHIPIO_FLAG_SET, val);
1370}
1371
d5c21b88
IM		 1372/*
1373 * Set chip parameters through the chip I/O widget.
1374 */
01ef7dbf
IM		 1375static void chipio_set_control_param(struct hda_codec *codec,
1376 enum control_param_id param_id, int param_val)
1377{
1378 struct ca0132_spec *spec = codec->spec;
1379 int val;
1380
1381 if ((param_id < 32) && (param_val < 8)) {
1382 val = (param_val << 5) | (param_id);
1383 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1384 VENDOR_CHIPIO_PARAM_SET, val);
1385 } else {
1386 mutex_lock(&spec->chipio_mutex);
1387 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1388 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1389 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1390 param_id);
1391 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1392 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1393 param_val);
1394 }
1395 mutex_unlock(&spec->chipio_mutex);
1396 }
1397}
1398
009b8f97
CM		 1399/*
1400 * Set chip parameters through the chip I/O widget. NO MUTEX.
1401 */
1402static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1403 enum control_param_id param_id, int param_val)
1404{
1405 int val;
1406
1407 if ((param_id < 32) && (param_val < 8)) {
1408 val = (param_val << 5) | (param_id);
1409 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1410 VENDOR_CHIPIO_PARAM_SET, val);
1411 } else {
1412 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1413 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1414 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1415 param_id);
1416 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1417 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1418 param_val);
1419 }
1420 }
1421}
38ba69ff
CM		 1422/*
1423 * Connect stream to a source point, and then connect
1424 * that source point to a destination point.
1425 */
1426static void chipio_set_stream_source_dest(struct hda_codec *codec,
1427 int streamid, int source_point, int dest_point)
1428{
1429 chipio_set_control_param_no_mutex(codec,
1430 CONTROL_PARAM_STREAM_ID, streamid);
1431 chipio_set_control_param_no_mutex(codec,
1432 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1433 chipio_set_control_param_no_mutex(codec,
1434 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1435}
1436
1437/*
1438 * Set number of channels in the selected stream.
1439 */
1440static void chipio_set_stream_channels(struct hda_codec *codec,
1441 int streamid, unsigned int channels)
1442{
1443 chipio_set_control_param_no_mutex(codec,
1444 CONTROL_PARAM_STREAM_ID, streamid);
1445 chipio_set_control_param_no_mutex(codec,
1446 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1447}
009b8f97
CM		 1448
1449/*
1450 * Enable/Disable audio stream.
1451 */
1452static void chipio_set_stream_control(struct hda_codec *codec,
1453 int streamid, int enable)
1454{
1455 chipio_set_control_param_no_mutex(codec,
1456 CONTROL_PARAM_STREAM_ID, streamid);
1457 chipio_set_control_param_no_mutex(codec,
1458 CONTROL_PARAM_STREAM_CONTROL, enable);
1459}
1460
38ba69ff
CM		 1461
1462/*
1463 * Set sampling rate of the connection point. NO MUTEX.
1464 */
1465static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1466 int connid, enum ca0132_sample_rate rate)
1467{
1468 chipio_set_control_param_no_mutex(codec,
1469 CONTROL_PARAM_CONN_POINT_ID, connid);
1470 chipio_set_control_param_no_mutex(codec,
1471 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1472}
1473
d5c21b88
IM		 1474/*
1475 * Set sampling rate of the connection point.
1476 */
01ef7dbf
IM		 1477static void chipio_set_conn_rate(struct hda_codec *codec,
1478 int connid, enum ca0132_sample_rate rate)
1479{
1480 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1481 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1482 rate);
1483}
1484
b9b41345
CM		 1485/*
1486 * Writes to the 8051's internal address space directly instead of indirectly,
1487 * giving access to the special function registers located at addresses
1488 * 0x80-0xFF.
1489 */
1490static void chipio_8051_write_direct(struct hda_codec *codec,
1491 unsigned int addr, unsigned int data)
1492{
1493 unsigned int verb;
1494
1495 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1496 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1497}
1498
d5c21b88
IM		 1499/*
1500 * Enable clocks.
1501 */
01ef7dbf
IM		 1502static void chipio_enable_clocks(struct hda_codec *codec)
1503{
1504 struct ca0132_spec *spec = codec->spec;
1505
1506 mutex_lock(&spec->chipio_mutex);
1507 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1508 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1509 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1510 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1511 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1512 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1513 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1514 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1515 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1516 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1517 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1518 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1519 mutex_unlock(&spec->chipio_mutex);
1520}
1521
1522/*
1523 * CA0132 DSP IO stuffs
1524 */
1525static int dspio_send(struct hda_codec *codec, unsigned int reg,
1526 unsigned int data)
1527{
b645d796 1528 int res;
6d67530e 1529 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1530
1531 /* send bits of data specified by reg to dsp */
1532 do {
1533 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1534 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1535 return res;
6d67530e
IM		 1536 msleep(20);
1537 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1538
1539 return -EIO;
1540}
1541
d5c21b88
IM		 1542/*
1543 * Wait for DSP to be ready for commands
1544 */
01ef7dbf
IM		 1545static void dspio_write_wait(struct hda_codec *codec)
1546{
4861af80
IM		 1547 int status;
1548 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1549
01ef7dbf 1550 do {
4861af80
IM		 1551 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1552 VENDOR_DSPIO_STATUS, 0);
1553 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1554 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1555 break;
1556 msleep(1);
1557 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1558}
1559
d5c21b88
IM		 1560/*
1561 * Write SCP data to DSP
1562 */
01ef7dbf
IM		 1563static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1564{
1565 struct ca0132_spec *spec = codec->spec;
1566 int status;
1567
1568 dspio_write_wait(codec);
1569
1570 mutex_lock(&spec->chipio_mutex);
1571 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1572 scp_data & 0xffff);
1573 if (status < 0)
1574 goto error;
1575
1576 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1577 scp_data >> 16);
1578 if (status < 0)
1579 goto error;
1580
1581 /* OK, now check if the write itself has executed*/
1582 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1583 VENDOR_DSPIO_STATUS, 0);
1584error:
1585 mutex_unlock(&spec->chipio_mutex);
1586
1587 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1588 -EIO : 0;
1589}
1590
d5c21b88
IM		 1591/*
1592 * Write multiple SCP data to DSP
1593 */
01ef7dbf
IM		 1594static int dspio_write_multiple(struct hda_codec *codec,
1595 unsigned int *buffer, unsigned int size)
1596{
1597 int status = 0;
1598 unsigned int count;
1599
a16fbb85 1600 if (buffer == NULL)
01ef7dbf
IM		 1601 return -EINVAL;
1602
1603 count = 0;
1604 while (count < size) {
1605 status = dspio_write(codec, *buffer++);
1606 if (status != 0)
1607 break;
1608 count++;
1609 }
1610
1611 return status;
1612}
1613
a73d511c
IM		 1614static int dspio_read(struct hda_codec *codec, unsigned int *data)
1615{
1616 int status;
1617
1618 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1619 if (status == -EIO)
1620 return status;
1621
1622 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1623 if (status == -EIO ||
1624 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1625 return -EIO;
1626
1627 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1628 VENDOR_DSPIO_SCP_READ_DATA, 0);
1629
1630 return 0;
1631}
1632
1633static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1634 unsigned int *buf_size, unsigned int size_count)
1635{
1636 int status = 0;
1637 unsigned int size = *buf_size;
1638 unsigned int count;
1639 unsigned int skip_count;
1640 unsigned int dummy;
1641
a16fbb85 1642 if (buffer == NULL)
a73d511c
IM		 1643 return -1;
1644
1645 count = 0;
1646 while (count < size && count < size_count) {
1647 status = dspio_read(codec, buffer++);
1648 if (status != 0)
1649 break;
1650 count++;
1651 }
1652
1653 skip_count = count;
1654 if (status == 0) {
1655 while (skip_count < size) {
1656 status = dspio_read(codec, &dummy);
1657 if (status != 0)
1658 break;
1659 skip_count++;
1660 }
1661 }
1662 *buf_size = count;
1663
1664 return status;
1665}
1666
d5c21b88
IM		 1667/*
1668 * Construct the SCP header using corresponding fields
1669 */
01ef7dbf
IM		 1670static inline unsigned int
1671make_scp_header(unsigned int target_id, unsigned int source_id,
1672 unsigned int get_flag, unsigned int req,
1673 unsigned int device_flag, unsigned int resp_flag,
1674 unsigned int error_flag, unsigned int data_size)
1675{
1676 unsigned int header = 0;
1677
1678 header = (data_size & 0x1f) << 27;
1679 header |= (error_flag & 0x01) << 26;
1680 header |= (resp_flag & 0x01) << 25;
1681 header |= (device_flag & 0x01) << 24;
1682 header |= (req & 0x7f) << 17;
1683 header |= (get_flag & 0x01) << 16;
1684 header |= (source_id & 0xff) << 8;
1685 header |= target_id & 0xff;
1686
1687 return header;
1688}
1689
d5c21b88
IM		 1690/*
1691 * Extract corresponding fields from SCP header
1692 */
01ef7dbf
IM		 1693static inline void
1694extract_scp_header(unsigned int header,
1695 unsigned int *target_id, unsigned int *source_id,
1696 unsigned int *get_flag, unsigned int *req,
1697 unsigned int *device_flag, unsigned int *resp_flag,
1698 unsigned int *error_flag, unsigned int *data_size)
1699{
1700 if (data_size)
1701 *data_size = (header >> 27) & 0x1f;
1702 if (error_flag)
1703 *error_flag = (header >> 26) & 0x01;
1704 if (resp_flag)
1705 *resp_flag = (header >> 25) & 0x01;
1706 if (device_flag)
1707 *device_flag = (header >> 24) & 0x01;
1708 if (req)
1709 *req = (header >> 17) & 0x7f;
1710 if (get_flag)
1711 *get_flag = (header >> 16) & 0x01;
1712 if (source_id)
1713 *source_id = (header >> 8) & 0xff;
1714 if (target_id)
1715 *target_id = header & 0xff;
1716}
1717
1718#define SCP_MAX_DATA_WORDS (16)
1719
1720/* Structure to contain any SCP message */
1721struct scp_msg {
1722 unsigned int hdr;
1723 unsigned int data[SCP_MAX_DATA_WORDS];
1724};
1725
a73d511c
IM		 1726static void dspio_clear_response_queue(struct hda_codec *codec)
1727{
1728 unsigned int dummy = 0;
1729 int status = -1;
1730
1731 /* clear all from the response queue */
1732 do {
1733 status = dspio_read(codec, &dummy);
1734 } while (status == 0);
1735}
1736
1737static int dspio_get_response_data(struct hda_codec *codec)
1738{
1739 struct ca0132_spec *spec = codec->spec;
1740 unsigned int data = 0;
1741 unsigned int count;
1742
1743 if (dspio_read(codec, &data) < 0)
1744 return -EIO;
1745
1746 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1747 spec->scp_resp_header = data;
1748 spec->scp_resp_count = data >> 27;
1749 count = spec->wait_num_data;
1750 dspio_read_multiple(codec, spec->scp_resp_data,
1751 &spec->scp_resp_count, count);
1752 return 0;
1753 }
1754
1755 return -EIO;
1756}
1757
d5c21b88
IM		 1758/*
1759 * Send SCP message to DSP
1760 */
01ef7dbf
IM		 1761static int dspio_send_scp_message(struct hda_codec *codec,
1762 unsigned char *send_buf,
1763 unsigned int send_buf_size,
1764 unsigned char *return_buf,
1765 unsigned int return_buf_size,
1766 unsigned int *bytes_returned)
1767{
1768 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1769 int status = -1;
1770 unsigned int scp_send_size = 0;
1771 unsigned int total_size;
1772 bool waiting_for_resp = false;
1773 unsigned int header;
1774 struct scp_msg *ret_msg;
1775 unsigned int resp_src_id, resp_target_id;
1776 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1777
1778 if (bytes_returned)
1779 *bytes_returned = 0;
1780
1781 /* get scp header from buffer */
1782 header = *((unsigned int *)send_buf);
1783 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1784 &device_flag, NULL, NULL, &data_size);
1785 scp_send_size = data_size + 1;
1786 total_size = (scp_send_size * 4);
1787
1788 if (send_buf_size < total_size)
1789 return -EINVAL;
1790
1791 if (get_flag || device_flag) {
1792 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1793 return -EINVAL;
1794
1795 spec->wait_scp_header = *((unsigned int *)send_buf);
1796
1797 /* swap source id with target id */
1798 resp_target_id = src_id;
1799 resp_src_id = target_id;
1800 spec->wait_scp_header &= 0xffff0000;
1801 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1802 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1803 spec->wait_scp = 1;
1804 waiting_for_resp = true;
1805 }
1806
1807 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1808 scp_send_size);
1809 if (status < 0) {
1810 spec->wait_scp = 0;
1811 return status;
1812 }
1813
1814 if (waiting_for_resp) {
6d67530e 1815 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1816 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1817 do {
1818 msleep(20);
6d67530e 1819 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1820 waiting_for_resp = false;
6d67530e 1821 if (!spec->wait_scp) {
01ef7dbf
IM		 1822 ret_msg = (struct scp_msg *)return_buf;
1823 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1824 memcpy(&ret_msg->data, spec->scp_resp_data,
1825 spec->wait_num_data);
1826 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1827 status = 0;
1828 } else {
1829 status = -EIO;
1830 }
1831 spec->wait_scp = 0;
1832 }
1833
1834 return status;
1835}
1836
d5c21b88
IM		 1837/**
1838 * Prepare and send the SCP message to DSP
1839 * @codec: the HDA codec
1840 * @mod_id: ID of the DSP module to send the command
1841 * @req: ID of request to send to the DSP module
1842 * @dir: SET or GET
1843 * @data: pointer to the data to send with the request, request specific
1844 * @len: length of the data, in bytes
1845 * @reply: point to the buffer to hold data returned for a reply
1846 * @reply_len: length of the reply buffer returned from GET
1847 *
1848 * Returns zero or a negative error code.
1849 */
01ef7dbf 1850static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1851 int mod_id, int src_id, int req, int dir, const void *data,
1852 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1853{
1854 int status = 0;
1855 struct scp_msg scp_send, scp_reply;
1856 unsigned int ret_bytes, send_size, ret_size;
1857 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1858 unsigned int reply_data_size;
1859
1860 memset(&scp_send, 0, sizeof(scp_send));
1861 memset(&scp_reply, 0, sizeof(scp_reply));
1862
1863 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1864 return -EINVAL;
1865
1866 if (dir == SCP_GET && reply == NULL) {
4e76a883 1867 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1868 return -EINVAL;
1869 }
1870
1871 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1872 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1873 return -EINVAL;
1874 }
1875
447fd8e9 1876 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1877 0, 0, 0, len/sizeof(unsigned int));
1878 if (data != NULL && len > 0) {
1879 len = min((unsigned int)(sizeof(scp_send.data)), len);
1880 memcpy(scp_send.data, data, len);
1881 }
1882
1883 ret_bytes = 0;
1884 send_size = sizeof(unsigned int) + len;
1885 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1886 send_size, (unsigned char *)&scp_reply,
1887 sizeof(scp_reply), &ret_bytes);
1888
1889 if (status < 0) {
4e76a883 1890 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1891 return status;
1892 }
1893
1894 /* extract send and reply headers members */
1895 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1896 NULL, NULL, NULL, NULL, NULL);
1897 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1898 &reply_resp_flag, &reply_error_flag,
1899 &reply_data_size);
1900
1901 if (!send_get_flag)
1902 return 0;
1903
1904 if (reply_resp_flag && !reply_error_flag) {
1905 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1906 / sizeof(unsigned int);
1907
1908 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1909 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1910 return -EINVAL;
1911 } else if (ret_size != reply_data_size) {
4e76a883 1912 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1913 return -EINVAL;
46a049da
AB		 1914 } else if (!reply) {
1915 codec_dbg(codec, "NULL reply\n");
1916 return -EINVAL;
01ef7dbf
IM		 1917 } else {
1918 *reply_len = ret_size*sizeof(unsigned int);
1919 memcpy(reply, scp_reply.data, *reply_len);
1920 }
1921 } else {
4e76a883 1922 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1923 return -EIO;
1924 }
1925
1926 return status;
1927}
1928
5aaca44d
IM		 1929/*
1930 * Set DSP parameters
1931 */
1932static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 1933 int src_id, int req, const void *data, unsigned int len)
5aaca44d 1934{
447fd8e9
CM		 1935 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1936 NULL);
5aaca44d
IM		 1937}
1938
1939static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 1940 int req, const unsigned int data)
5aaca44d 1941{
447fd8e9
CM		 1942 return dspio_set_param(codec, mod_id, 0x20, req, &data,
1943 sizeof(unsigned int));
1944}
1945
1946static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1947 int req, const unsigned int data)
1948{
1949 return dspio_set_param(codec, mod_id, 0x00, req, &data,
1950 sizeof(unsigned int));
5aaca44d
IM		 1951}
1952
d5c21b88
IM		 1953/*
1954 * Allocate a DSP DMA channel via an SCP message
1955 */
01ef7dbf
IM		 1956static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1957{
1958 int status = 0;
1959 unsigned int size = sizeof(dma_chan);
1960
4e76a883 1961 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 1962 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1963 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1964 dma_chan, &size);
01ef7dbf
IM		 1965
1966 if (status < 0) {
4e76a883 1967 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1968 return status;
1969 }
1970
1971 if ((*dma_chan + 1) == 0) {
4e76a883 1972 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1973 return -EBUSY;
1974 }
1975
4e76a883
TI		 1976 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1977 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1978
1979 return status;
1980}
1981
d5c21b88
IM		 1982/*
1983 * Free a DSP DMA via an SCP message
1984 */
01ef7dbf
IM		 1985static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1986{
1987 int status = 0;
1988 unsigned int dummy = 0;
1989
4e76a883
TI		 1990 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1991 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 1992
447fd8e9
CM		 1993 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1994 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1995 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 1996
1997 if (status < 0) {
4e76a883 1998 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1999 return status;
2000 }
2001
4e76a883 2002 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 2003
2004 return status;
2005}
2006
2007/*
d5c21b88 2008 * (Re)start the DSP
01ef7dbf
IM		 2009 */
2010static int dsp_set_run_state(struct hda_codec *codec)
2011{
2012 unsigned int dbg_ctrl_reg;
2013 unsigned int halt_state;
2014 int err;
2015
2016 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2017 if (err < 0)
2018 return err;
2019
2020 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2021 DSP_DBGCNTL_STATE_LOBIT;
2022
2023 if (halt_state != 0) {
2024 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2025 DSP_DBGCNTL_SS_MASK);
2026 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2027 dbg_ctrl_reg);
2028 if (err < 0)
2029 return err;
2030
2031 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2032 DSP_DBGCNTL_EXEC_MASK;
2033 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2034 dbg_ctrl_reg);
2035 if (err < 0)
2036 return err;
2037 }
2038
2039 return 0;
2040}
2041
d5c21b88
IM		 2042/*
2043 * Reset the DSP
2044 */
01ef7dbf
IM		 2045static int dsp_reset(struct hda_codec *codec)
2046{
2047 unsigned int res;
2048 int retry = 20;
2049
4e76a883 2050 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 2051 do {
2052 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2053 retry--;
2054 } while (res == -EIO && retry);
2055
2056 if (!retry) {
4e76a883 2057 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 2058 return -EIO;
2059 }
2060
2061 return 0;
2062}
2063
d5c21b88
IM		 2064/*
2065 * Convert chip address to DSP address
2066 */
01ef7dbf
IM		 2067static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2068 bool *code, bool *yram)
2069{
2070 *code = *yram = false;
2071
2072 if (UC_RANGE(chip_addx, 1)) {
2073 *code = true;
2074 return UC_OFF(chip_addx);
2075 } else if (X_RANGE_ALL(chip_addx, 1)) {
2076 return X_OFF(chip_addx);
2077 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2078 *yram = true;
2079 return Y_OFF(chip_addx);
2080 }
2081
4a8b89f9 2082 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2083}
2084
d5c21b88
IM		 2085/*
2086 * Check if the DSP DMA is active
2087 */
01ef7dbf
IM		 2088static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2089{
2090 unsigned int dma_chnlstart_reg;
2091
2092 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2093
2094 return ((dma_chnlstart_reg & (1 <<
2095 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2096}
2097
2098static int dsp_dma_setup_common(struct hda_codec *codec,
2099 unsigned int chip_addx,
2100 unsigned int dma_chan,
2101 unsigned int port_map_mask,
2102 bool ovly)
2103{
2104 int status = 0;
2105 unsigned int chnl_prop;
2106 unsigned int dsp_addx;
2107 unsigned int active;
2108 bool code, yram;
2109
4e76a883 2110 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2111
2112 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2113 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2114 return -EINVAL;
2115 }
2116
2117 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2118 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2119 return -EBUSY;
2120 }
2121
2122 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2123
2124 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2125 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2126 return -ENXIO;
2127 }
2128
2129 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2130 active = 0;
2131
4e76a883 2132 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2133
2134 if (ovly) {
2135 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2136 &chnl_prop);
2137
2138 if (status < 0) {
4e76a883 2139 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2140 return status;
2141 }
4e76a883 2142 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2143 }
2144
2145 if (!code)
2146 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2147 else
2148 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2149
2150 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2151
2152 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2153 if (status < 0) {
4e76a883 2154 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2155 return status;
2156 }
4e76a883 2157 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2158
2159 if (ovly) {
2160 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2161 &active);
2162
2163 if (status < 0) {
4e76a883 2164 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2165 return status;
2166 }
4e76a883 2167 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2168 }
2169
2170 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2171 DSPDMAC_ACTIVE_AAR_MASK;
2172
2173 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2174 if (status < 0) {
4e76a883 2175 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2176 return status;
2177 }
2178
4e76a883 2179 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2180
2181 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2182 port_map_mask);
2183 if (status < 0) {
4e76a883 2184 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2185 return status;
2186 }
4e76a883 2187 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2188
2189 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2190 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2191 if (status < 0) {
4e76a883 2192 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2193 return status;
2194 }
4e76a883 2195 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2196
4e76a883 2197 codec_dbg(codec,
01ef7dbf
IM		 2198 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2199 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2200 chip_addx, dsp_addx, dma_chan,
2201 port_map_mask, chnl_prop, active);
2202
4e76a883 2203 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2204
2205 return 0;
2206}
2207
d5c21b88
IM		 2208/*
2209 * Setup the DSP DMA per-transfer-specific registers
2210 */
01ef7dbf
IM		 2211static int dsp_dma_setup(struct hda_codec *codec,
2212 unsigned int chip_addx,
2213 unsigned int count,
2214 unsigned int dma_chan)
2215{
2216 int status = 0;
2217 bool code, yram;
2218 unsigned int dsp_addx;
2219 unsigned int addr_field;
2220 unsigned int incr_field;
2221 unsigned int base_cnt;
2222 unsigned int cur_cnt;
2223 unsigned int dma_cfg = 0;
2224 unsigned int adr_ofs = 0;
2225 unsigned int xfr_cnt = 0;
2226 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2227 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2228
4e76a883 2229 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2230
2231 if (count > max_dma_count) {
4e76a883 2232 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2233 return -EINVAL;
2234 }
2235
2236 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2237 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2238 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2239 return -ENXIO;
2240 }
2241
4e76a883 2242 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2243
2244 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2245 incr_field = 0;
2246
2247 if (!code) {
2248 addr_field <<= 1;
2249 if (yram)
2250 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2251
2252 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2253 }
2254
2255 dma_cfg = addr_field + incr_field;
2256 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2257 dma_cfg);
2258 if (status < 0) {
4e76a883 2259 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2260 return status;
2261 }
4e76a883 2262 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2263
2264 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2265 (code ? 0 : 1));
2266
2267 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2268 adr_ofs);
2269 if (status < 0) {
4e76a883 2270 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2271 return status;
2272 }
4e76a883 2273 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2274
2275 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2276
2277 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2278
2279 xfr_cnt = base_cnt | cur_cnt;
2280
2281 status = chipio_write(codec,
2282 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2283 if (status < 0) {
4e76a883 2284 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2285 return status;
2286 }
4e76a883 2287 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2288
4e76a883 2289 codec_dbg(codec,
01ef7dbf
IM		 2290 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2291 "ADROFS=0x%x, XFRCNT=0x%x\n",
2292 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2293
4e76a883 2294 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2295
2296 return 0;
2297}
2298
d5c21b88
IM		 2299/*
2300 * Start the DSP DMA
2301 */
01ef7dbf
IM		 2302static int dsp_dma_start(struct hda_codec *codec,
2303 unsigned int dma_chan, bool ovly)
2304{
2305 unsigned int reg = 0;
2306 int status = 0;
2307
4e76a883 2308 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2309
2310 if (ovly) {
2311 status = chipio_read(codec,
2312 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2313
2314 if (status < 0) {
4e76a883 2315 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2316 return status;
2317 }
4e76a883 2318 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2319
2320 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2321 DSPDMAC_CHNLSTART_DIS_MASK);
2322 }
2323
2324 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2325 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2326 if (status < 0) {
4e76a883 2327 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2328 return status;
2329 }
4e76a883 2330 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2331
2332 return status;
2333}
2334
d5c21b88
IM		 2335/*
2336 * Stop the DSP DMA
2337 */
01ef7dbf
IM		 2338static int dsp_dma_stop(struct hda_codec *codec,
2339 unsigned int dma_chan, bool ovly)
2340{
2341 unsigned int reg = 0;
2342 int status = 0;
2343
4e76a883 2344 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2345
2346 if (ovly) {
2347 status = chipio_read(codec,
2348 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2349
2350 if (status < 0) {
4e76a883 2351 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2352 return status;
2353 }
4e76a883 2354 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2355 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2356 DSPDMAC_CHNLSTART_DIS_MASK);
2357 }
2358
2359 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2360 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2361 if (status < 0) {
4e76a883 2362 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2363 return status;
2364 }
4e76a883 2365 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2366
2367 return status;
2368}
2369
d5c21b88
IM		 2370/**
2371 * Allocate router ports
2372 *
2373 * @codec: the HDA codec
2374 * @num_chans: number of channels in the stream
2375 * @ports_per_channel: number of ports per channel
2376 * @start_device: start device
2377 * @port_map: pointer to the port list to hold the allocated ports
2378 *
2379 * Returns zero or a negative error code.
2380 */
01ef7dbf
IM		 2381static int dsp_allocate_router_ports(struct hda_codec *codec,
2382 unsigned int num_chans,
2383 unsigned int ports_per_channel,
2384 unsigned int start_device,
2385 unsigned int *port_map)
2386{
2387 int status = 0;
2388 int res;
2389 u8 val;
2390
2391 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2392 if (status < 0)
2393 return status;
2394
2395 val = start_device << 6;
2396 val |= (ports_per_channel - 1) << 4;
2397 val |= num_chans - 1;
2398
2399 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2400 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2401 val);
2402
2403 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2404 VENDOR_CHIPIO_PORT_ALLOC_SET,
2405 MEM_CONNID_DSP);
2406
2407 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2408 if (status < 0)
2409 return status;
2410
2411 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2412 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2413
2414 *port_map = res;
2415
2416 return (res < 0) ? res : 0;
2417}
2418
d5c21b88
IM		 2419/*
2420 * Free router ports
2421 */
01ef7dbf
IM		 2422static int dsp_free_router_ports(struct hda_codec *codec)
2423{
2424 int status = 0;
2425
2426 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2427 if (status < 0)
2428 return status;
2429
2430 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2431 VENDOR_CHIPIO_PORT_FREE_SET,
2432 MEM_CONNID_DSP);
2433
2434 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2435
2436 return status;
2437}
2438
d5c21b88
IM		 2439/*
2440 * Allocate DSP ports for the download stream
2441 */
01ef7dbf
IM		 2442static int dsp_allocate_ports(struct hda_codec *codec,
2443 unsigned int num_chans,
2444 unsigned int rate_multi, unsigned int *port_map)
2445{
2446 int status;
2447
4e76a883 2448 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2449
2450 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2451 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2452 return -EINVAL;
2453 }
2454
2455 status = dsp_allocate_router_ports(codec, num_chans,
2456 rate_multi, 0, port_map);
2457
4e76a883 2458 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2459
2460 return status;
2461}
2462
01ef7dbf
IM		 2463static int dsp_allocate_ports_format(struct hda_codec *codec,
2464 const unsigned short fmt,
2465 unsigned int *port_map)
2466{
2467 int status;
2468 unsigned int num_chans;
2469
2470 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2471 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2472 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2473
2474 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2475 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2476 return -EINVAL;
2477 }
2478
2479 num_chans = get_hdafmt_chs(fmt) + 1;
2480
2481 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2482
2483 return status;
2484}
2485
d5c21b88
IM		 2486/*
2487 * free DSP ports
2488 */
2489static int dsp_free_ports(struct hda_codec *codec)
2490{
2491 int status;
2492
4e76a883 2493 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2494
2495 status = dsp_free_router_ports(codec);
2496 if (status < 0) {
4e76a883 2497 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2498 return status;
2499 }
4e76a883 2500 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2501
2502 return status;
2503}
2504
01ef7dbf
IM		 2505/*
2506 * HDA DMA engine stuffs for DSP code download
2507 */
2508struct dma_engine {
2509 struct hda_codec *codec;
2510 unsigned short m_converter_format;
2511 struct snd_dma_buffer *dmab;
2512 unsigned int buf_size;
2513};
2514
2515
2516enum dma_state {
2517 DMA_STATE_STOP = 0,
2518 DMA_STATE_RUN = 1
2519};
2520
6194b99d 2521static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2522 unsigned int sample_rate,
2523 unsigned short channels,
01ef7dbf
IM		 2524 unsigned short *hda_format)
2525{
2526 unsigned int format_val;
2527
b7d023e1
TI		 2528 format_val = snd_hdac_calc_stream_format(sample_rate,
2529 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2530
2531 if (hda_format)
2532 *hda_format = (unsigned short)format_val;
2533
2534 return 0;
2535}
2536
d5c21b88
IM		 2537/*
2538 * Reset DMA for DSP download
2539 */
01ef7dbf
IM		 2540static int dma_reset(struct dma_engine *dma)
2541{
2542 struct hda_codec *codec = dma->codec;
2543 struct ca0132_spec *spec = codec->spec;
2544 int status;
2545
b3667bd7 2546 if (dma->dmab->area)
01ef7dbf
IM		 2547 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2548
2549 status = snd_hda_codec_load_dsp_prepare(codec,
2550 dma->m_converter_format,
2551 dma->buf_size,
2552 dma->dmab);
2553 if (status < 0)
2554 return status;
2555 spec->dsp_stream_id = status;
2556 return 0;
2557}
2558
2559static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2560{
01ef7dbf
IM		 2561 bool cmd;
2562
01ef7dbf
IM		 2563 switch (state) {
2564 case DMA_STATE_STOP:
2565 cmd = false;
2566 break;
2567 case DMA_STATE_RUN:
2568 cmd = true;
2569 break;
2570 default:
c41999a2
DH		 2571 return 0;
2572 }
01ef7dbf
IM		 2573
2574 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2575 return 0;
95c6e9cb
IM		 2576}
2577
01ef7dbf
IM		 2578static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2579{
2580 return dma->dmab->bytes;
2581}
95c6e9cb 2582
01ef7dbf
IM		 2583static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2584{
2585 return dma->dmab->area;
2586}
95c6e9cb 2587
01ef7dbf
IM		 2588static int dma_xfer(struct dma_engine *dma,
2589 const unsigned int *data,
2590 unsigned int count)
2591{
2592 memcpy(dma->dmab->area, data, count);
2593 return 0;
2594}
95c6e9cb 2595
01ef7dbf
IM		 2596static void dma_get_converter_format(
2597 struct dma_engine *dma,
2598 unsigned short *format)
2599{
2600 if (format)
2601 *format = dma->m_converter_format;
2602}
95c6e9cb 2603
01ef7dbf 2604static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2605{
01ef7dbf 2606 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2607
01ef7dbf 2608 return spec->dsp_stream_id;
95c6e9cb
IM		 2609}
2610
01ef7dbf
IM		 2611struct dsp_image_seg {
2612 u32 magic;
2613 u32 chip_addr;
2614 u32 count;
2615 u32 data[0];
2616};
2617
2618static const u32 g_magic_value = 0x4c46584d;
2619static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2620
2621static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2622{
01ef7dbf
IM		 2623 return p->magic == g_magic_value;
2624}
95c6e9cb 2625
01ef7dbf
IM		 2626static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2627{
2628 return g_chip_addr_magic_value == p->chip_addr;
2629}
95c6e9cb 2630
01ef7dbf
IM		 2631static bool is_last(const struct dsp_image_seg *p)
2632{
2633 return p->count == 0;
2634}
95c6e9cb 2635
01ef7dbf
IM		 2636static size_t dsp_sizeof(const struct dsp_image_seg *p)
2637{
2638 return sizeof(*p) + p->count*sizeof(u32);
2639}
2640
2641static const struct dsp_image_seg *get_next_seg_ptr(
2642 const struct dsp_image_seg *p)
2643{
2644 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2645}
2646
2647/*
01ef7dbf 2648 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2649 */
8ae3124b 2650#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2651
d5c21b88
IM		 2652/*
2653 * Program a list of address/data pairs via the ChipIO widget.
2654 * The segment data is in the format of successive pairs of words.
2655 * These are repeated as indicated by the segment's count field.
2656 */
01ef7dbf
IM		 2657static int dspxfr_hci_write(struct hda_codec *codec,
2658 const struct dsp_image_seg *fls)
95c6e9cb 2659{
01ef7dbf
IM		 2660 int status;
2661 const u32 *data;
2662 unsigned int count;
95c6e9cb 2663
01ef7dbf 2664 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2665 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2666 return -EINVAL;
95c6e9cb
IM		 2667 }
2668
01ef7dbf
IM		 2669 count = fls->count;
2670 data = (u32 *)(fls->data);
2671 while (count >= 2) {
2672 status = chipio_write(codec, data[0], data[1]);
2673 if (status < 0) {
4e76a883 2674 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2675 return status;
2676 }
2677 count -= 2;
2678 data += 2;
2679 }
2680 return 0;
95c6e9cb
IM		 2681}
2682
d5c21b88
IM		 2683/**
2684 * Write a block of data into DSP code or data RAM using pre-allocated
2685 * DMA engine.
2686 *
2687 * @codec: the HDA codec
2688 * @fls: pointer to a fast load image
2689 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2690 * no relocation
2691 * @dma_engine: pointer to DMA engine to be used for DSP download
2692 * @dma_chan: The number of DMA channels used for DSP download
2693 * @port_map_mask: port mapping
2694 * @ovly: TRUE if overlay format is required
2695 *
2696 * Returns zero or a negative error code.
2697 */
01ef7dbf
IM		 2698static int dspxfr_one_seg(struct hda_codec *codec,
2699 const struct dsp_image_seg *fls,
2700 unsigned int reloc,
2701 struct dma_engine *dma_engine,
2702 unsigned int dma_chan,
2703 unsigned int port_map_mask,
2704 bool ovly)
95c6e9cb 2705{
406261ce 2706 int status = 0;
01ef7dbf
IM		 2707 bool comm_dma_setup_done = false;
2708 const unsigned int *data;
2709 unsigned int chip_addx;
2710 unsigned int words_to_write;
2711 unsigned int buffer_size_words;
2712 unsigned char *buffer_addx;
2713 unsigned short hda_format;
2714 unsigned int sample_rate_div;
2715 unsigned int sample_rate_mul;
2716 unsigned int num_chans;
2717 unsigned int hda_frame_size_words;
2718 unsigned int remainder_words;
2719 const u32 *data_remainder;
2720 u32 chip_addx_remainder;
2721 unsigned int run_size_words;
2722 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2723 unsigned long timeout;
2724 bool dma_active;
01ef7dbf
IM		 2725
2726 if (fls == NULL)
2727 return -EINVAL;
2728 if (is_hci_prog_list_seg(fls)) {
2729 hci_write = fls;
2730 fls = get_next_seg_ptr(fls);
2731 }
95c6e9cb 2732
01ef7dbf 2733 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2734 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2735 return dspxfr_hci_write(codec, hci_write);
2736 }
95c6e9cb 2737
01ef7dbf 2738 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2739 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2740 return -EINVAL;
95c6e9cb
IM		 2741 }
2742
01ef7dbf
IM		 2743 data = fls->data;
2744 chip_addx = fls->chip_addr,
2745 words_to_write = fls->count;
2746
2747 if (!words_to_write)
2748 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2749 if (reloc)
2750 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2751
2752 if (!UC_RANGE(chip_addx, words_to_write) &&
2753 !X_RANGE_ALL(chip_addx, words_to_write) &&
2754 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2755 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2756 return -EINVAL;
95c6e9cb
IM		 2757 }
2758
01ef7dbf
IM		 2759 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2760 sizeof(u32);
2761
2762 buffer_addx = dma_get_buffer_addr(dma_engine);
2763
2764 if (buffer_addx == NULL) {
4e76a883 2765 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2766 return -EINVAL;
2767 }
2768
2769 dma_get_converter_format(dma_engine, &hda_format);
2770 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2771 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2772 num_chans = get_hdafmt_chs(hda_format) + 1;
2773
2774 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2775 (num_chans * sample_rate_mul / sample_rate_div));
2776
3bc085a1 2777 if (hda_frame_size_words == 0) {
4e76a883 2778 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2779 return -EINVAL;
2780 }
2781
01ef7dbf
IM		 2782 buffer_size_words = min(buffer_size_words,
2783 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2784 65536 : 32768));
2785 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2786 codec_dbg(codec,
01ef7dbf
IM		 2787 "chpadr=0x%08x frmsz=%u nchan=%u "
2788 "rate_mul=%u div=%u bufsz=%u\n",
2789 chip_addx, hda_frame_size_words, num_chans,
2790 sample_rate_mul, sample_rate_div, buffer_size_words);
2791
3bc085a1 2792 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2793 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2794 return -EINVAL;
2795 }
2796
2797 remainder_words = words_to_write % hda_frame_size_words;
2798 data_remainder = data;
2799 chip_addx_remainder = chip_addx;
2800
2801 data += remainder_words;
2802 chip_addx += remainder_words*sizeof(u32);
2803 words_to_write -= remainder_words;
2804
2805 while (words_to_write != 0) {
2806 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2807 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2808 words_to_write, run_size_words, remainder_words);
2809 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2810 if (!comm_dma_setup_done) {
2811 status = dsp_dma_stop(codec, dma_chan, ovly);
2812 if (status < 0)
425a7880 2813 return status;
01ef7dbf
IM		 2814 status = dsp_dma_setup_common(codec, chip_addx,
2815 dma_chan, port_map_mask, ovly);
2816 if (status < 0)
2817 return status;
2818 comm_dma_setup_done = true;
2819 }
2820
2821 status = dsp_dma_setup(codec, chip_addx,
2822 run_size_words, dma_chan);
2823 if (status < 0)
2824 return status;
2825 status = dsp_dma_start(codec, dma_chan, ovly);
2826 if (status < 0)
2827 return status;
2828 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2829 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2830 return -EIO;
2831 }
2832 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2833 if (status < 0)
2834 return status;
2835 if (remainder_words != 0) {
2836 status = chipio_write_multiple(codec,
2837 chip_addx_remainder,
2838 data_remainder,
2839 remainder_words);
b3667bd7
TI		 2840 if (status < 0)
2841 return status;
01ef7dbf
IM		 2842 remainder_words = 0;
2843 }
2844 if (hci_write) {
2845 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2846 if (status < 0)
2847 return status;
01ef7dbf
IM		 2848 hci_write = NULL;
2849 }
6d67530e
IM		 2850
2851 timeout = jiffies + msecs_to_jiffies(2000);
2852 do {
2853 dma_active = dsp_is_dma_active(codec, dma_chan);
2854 if (!dma_active)
01ef7dbf 2855 break;
6d67530e
IM		 2856 msleep(20);
2857 } while (time_before(jiffies, timeout));
2858 if (dma_active)
2859 break;
2860
4e76a883 2861 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2862 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2863 status = dma_reset(dma_engine);
01ef7dbf
IM		 2864
2865 if (status < 0)
2866 return status;
2867
2868 data += run_size_words;
2869 chip_addx += run_size_words*sizeof(u32);
2870 words_to_write -= run_size_words;
2871 }
2872
2873 if (remainder_words != 0) {
2874 status = chipio_write_multiple(codec, chip_addx_remainder,
2875 data_remainder, remainder_words);
2876 }
2877
2878 return status;
95c6e9cb
IM		 2879}
2880
d5c21b88
IM		 2881/**
2882 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2883 *
2884 * @codec: the HDA codec
2885 * @fls_data: pointer to a fast load image
2886 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2887 * no relocation
e97249dd 2888 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2889 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2890 * @ovly: TRUE if overlay format is required
2891 *
2892 * Returns zero or a negative error code.
2893 */
01ef7dbf
IM		 2894static int dspxfr_image(struct hda_codec *codec,
2895 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2896 unsigned int reloc,
2897 unsigned int sample_rate,
2898 unsigned short channels,
01ef7dbf 2899 bool ovly)
95c6e9cb
IM		 2900{
2901 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2902 int status;
2903 unsigned short hda_format = 0;
2904 unsigned int response;
2905 unsigned char stream_id = 0;
2906 struct dma_engine *dma_engine;
2907 unsigned int dma_chan;
2908 unsigned int port_map_mask;
2909
2910 if (fls_data == NULL)
2911 return -EINVAL;
2912
2913 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2914 if (!dma_engine)
2915 return -ENOMEM;
95c6e9cb 2916
01ef7dbf
IM		 2917 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2918 if (!dma_engine->dmab) {
549e8292
TI		 2919 kfree(dma_engine);
2920 return -ENOMEM;
01ef7dbf 2921 }
95c6e9cb 2922
01ef7dbf 2923 dma_engine->codec = codec;
6194b99d 2924 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2925 dma_engine->m_converter_format = hda_format;
2926 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2927 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2928
8ae3124b 2929 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2930
2931 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2932 hda_format, &response);
2933
2934 if (status < 0) {
4e76a883 2935 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2936 goto exit;
2937 }
2938
2939 status = snd_hda_codec_load_dsp_prepare(codec,
2940 dma_engine->m_converter_format,
2941 dma_engine->buf_size,
2942 dma_engine->dmab);
2943 if (status < 0)
95c6e9cb 2944 goto exit;
01ef7dbf
IM		 2945 spec->dsp_stream_id = status;
2946
2947 if (ovly) {
2948 status = dspio_alloc_dma_chan(codec, &dma_chan);
2949 if (status < 0) {
4e76a883 2950 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2951 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2952 goto exit;
2953 }
2954 }
95c6e9cb 2955
01ef7dbf
IM		 2956 port_map_mask = 0;
2957 status = dsp_allocate_ports_format(codec, hda_format,
2958 &port_map_mask);
2959 if (status < 0) {
4e76a883 2960 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2961 goto exit;
2962 }
2963
2964 stream_id = dma_get_stream_id(dma_engine);
2965 status = codec_set_converter_stream_channel(codec,
2966 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2967 if (status < 0) {
4e76a883 2968 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2969 goto exit;
2970 }
2971
2972 while ((fls_data != NULL) && !is_last(fls_data)) {
2973 if (!is_valid(fls_data)) {
4e76a883 2974 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2975 status = -EINVAL;
2976 goto exit;
2977 }
2978 status = dspxfr_one_seg(codec, fls_data, reloc,
2979 dma_engine, dma_chan,
2980 port_map_mask, ovly);
2981 if (status < 0)
2982 break;
2983
2984 if (is_hci_prog_list_seg(fls_data))
2985 fls_data = get_next_seg_ptr(fls_data);
2986
2987 if ((fls_data != NULL) && !is_last(fls_data))
2988 fls_data = get_next_seg_ptr(fls_data);
2989 }
2990
2991 if (port_map_mask != 0)
2992 status = dsp_free_ports(codec);
2993
2994 if (status < 0)
95c6e9cb
IM		 2995 goto exit;
2996
01ef7dbf
IM		 2997 status = codec_set_converter_stream_channel(codec,
2998 WIDGET_CHIP_CTRL, 0, 0, &response);
2999
95c6e9cb 3000exit:
01ef7dbf
IM		 3001 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3002 dspio_free_dma_chan(codec, dma_chan);
3003
b3667bd7 3004 if (dma_engine->dmab->area)
01ef7dbf
IM		 3005 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3006 kfree(dma_engine->dmab);
3007 kfree(dma_engine);
3008
3009 return status;
95c6e9cb
IM		 3010}
3011
3012/*
01ef7dbf 3013 * CA0132 DSP download stuffs.
95c6e9cb 3014 */
01ef7dbf 3015static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 3016{
009b8f97 3017 struct ca0132_spec *spec = codec->spec;
4e76a883 3018 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 3019 if (!spec->use_alt_functions) {
3020 /*set DSP speaker to 2.0 configuration*/
3021 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3022 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 3023
009b8f97
CM		 3024 /*update write pointer*/
3025 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3026 }
01ef7dbf 3027}
95c6e9cb 3028
d5c21b88 3029/**
e60b2c7f 3030 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 3031 *
3032 * @codec: the HDA codec
3033 * @fls: pointer to a fast load image
3034 * @ovly: TRUE if overlay format is required
3035 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3036 * no relocation
3037 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3038 * @router_chans: number of audio router channels to be allocated (0 means use
3039 * internal defaults; max is 32)
3040 *
e60b2c7f
TI		 3041 * Download DSP from a DSP Image Fast Load structure. This structure is a
3042 * linear, non-constant sized element array of structures, each of which
3043 * contain the count of the data to be loaded, the data itself, and the
3044 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 3045 * Returns zero or a negative error code.
3046 */
01ef7dbf
IM		 3047static int dspload_image(struct hda_codec *codec,
3048 const struct dsp_image_seg *fls,
3049 bool ovly,
3050 unsigned int reloc,
3051 bool autostart,
3052 int router_chans)
3053{
3054 int status = 0;
e97249dd
IM		 3055 unsigned int sample_rate;
3056 unsigned short channels;
01ef7dbf 3057
4e76a883 3058 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 3059 if (router_chans == 0) {
3060 if (!ovly)
3061 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3062 else
3063 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3064 }
95c6e9cb 3065
e97249dd
IM		 3066 sample_rate = 48000;
3067 channels = (unsigned short)router_chans;
01ef7dbf 3068
e97249dd
IM		 3069 while (channels > 16) {
3070 sample_rate *= 2;
3071 channels /= 2;
01ef7dbf
IM		 3072 }
3073
01ef7dbf 3074 do {
4e76a883 3075 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3076 if (!ovly)
3077 status = dsp_reset(codec);
3078
3079 if (status < 0)
3080 break;
3081
4e76a883 3082 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3083 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3084 ovly);
01ef7dbf
IM		 3085
3086 if (status < 0)
3087 break;
3088
4e76a883 3089 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3090 if (autostart && !ovly) {
3091 dspload_post_setup(codec);
3092 status = dsp_set_run_state(codec);
3093 }
3094
4e76a883 3095 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3096 } while (0);
3097
3098 return status;
3099}
3100
f664417e 3101#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3102static bool dspload_is_loaded(struct hda_codec *codec)
3103{
3104 unsigned int data = 0;
3105 int status = 0;
3106
3107 status = chipio_read(codec, 0x40004, &data);
3108 if ((status < 0) || (data != 1))
3109 return false;
3110
3111 return true;
3112}
f664417e
TI		 3113#else
3114#define dspload_is_loaded(codec) false
3115#endif
01ef7dbf
IM		 3116
3117static bool dspload_wait_loaded(struct hda_codec *codec)
3118{
6d67530e 3119 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3120
3121 do {
01ef7dbf 3122 if (dspload_is_loaded(codec)) {
d9684bb5 3123 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3124 return true;
3125 }
6d67530e
IM		 3126 msleep(20);
3127 } while (time_before(jiffies, timeout));
01ef7dbf 3128
d9684bb5 3129 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3130 return false;
95c6e9cb
IM		 3131}
3132
e93ac30a 3133/*
b9b41345
CM		 3134 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3135 * based cards, and has a second mmio region, region2, that's used for special
3136 * commands.
e93ac30a
CM		 3137 */
3138
a62e4739
CM		 3139/*
3140 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3141 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3142 * The first eight bits are just the number of the pin. So far, I've only seen
3143 * this number go to 7.
b9b41345
CM		 3144 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3145 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3146 * then off to send that bit.
a62e4739 3147 */
b9b41345 3148static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
a62e4739
CM		 3149 bool enable)
3150{
3151 struct ca0132_spec *spec = codec->spec;
3152 unsigned short gpio_data;
3153
3154 gpio_data = gpio_pin & 0xF;
3155 gpio_data |= ((enable << 8) & 0x100);
3156
3157 writew(gpio_data, spec->mem_base + 0x320);
3158}
3159
b9b41345
CM		 3160/*
3161 * Special pci region2 commands that are only used by the AE-5. They follow
3162 * a set format, and require reads at certain points to seemingly 'clear'
3163 * the response data. My first tests didn't do these reads, and would cause
3164 * the card to get locked up until the memory was read. These commands
3165 * seem to work with three distinct values that I've taken to calling group,
3166 * target-id, and value.
3167 */
3168static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3169 unsigned int target, unsigned int value)
3170{
3171 struct ca0132_spec *spec = codec->spec;
3172 unsigned int write_val;
3173
3174 writel(0x0000007e, spec->mem_base + 0x210);
3175 readl(spec->mem_base + 0x210);
3176 writel(0x0000005a, spec->mem_base + 0x210);
3177 readl(spec->mem_base + 0x210);
3178 readl(spec->mem_base + 0x210);
3179
3180 writel(0x00800005, spec->mem_base + 0x20c);
3181 writel(group, spec->mem_base + 0x804);
3182
3183 writel(0x00800005, spec->mem_base + 0x20c);
3184 write_val = (target & 0xff);
3185 write_val |= (value << 8);
3186
3187
3188 writel(write_val, spec->mem_base + 0x204);
3189 /*
3190 * Need delay here or else it goes too fast and works inconsistently.
3191 */
3192 msleep(20);
3193
3194 readl(spec->mem_base + 0x860);
3195 readl(spec->mem_base + 0x854);
3196 readl(spec->mem_base + 0x840);
3197
3198 writel(0x00800004, spec->mem_base + 0x20c);
3199 writel(0x00000000, spec->mem_base + 0x210);
3200 readl(spec->mem_base + 0x210);
3201 readl(spec->mem_base + 0x210);
3202}
3203
3204/*
3205 * Setup GPIO for the other variants of Core3D.
3206 */
3207
e93ac30a
CM		 3208/*
3209 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3210 * the card shows as having no GPIO pins.
3211 */
3212static void ca0132_gpio_init(struct hda_codec *codec)
3213{
3214 struct ca0132_spec *spec = codec->spec;
3215
3216 switch (spec->quirk) {
3217 case QUIRK_SBZ:
03c9b6b1 3218 case QUIRK_AE5:
e93ac30a
CM		 3219 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3220 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3221 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3222 break;
3223 case QUIRK_R3DI:
3224 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3225 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3226 break;
3227 }
3228
3229}
3230
3231/* Sets the GPIO for audio output. */
3232static void ca0132_gpio_setup(struct hda_codec *codec)
3233{
3234 struct ca0132_spec *spec = codec->spec;
3235
3236 switch (spec->quirk) {
3237 case QUIRK_SBZ:
3238 snd_hda_codec_write(codec, 0x01, 0,
3239 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3240 snd_hda_codec_write(codec, 0x01, 0,
3241 AC_VERB_SET_GPIO_MASK, 0x07);
3242 snd_hda_codec_write(codec, 0x01, 0,
3243 AC_VERB_SET_GPIO_DATA, 0x04);
3244 snd_hda_codec_write(codec, 0x01, 0,
3245 AC_VERB_SET_GPIO_DATA, 0x06);
3246 break;
3247 case QUIRK_R3DI:
3248 snd_hda_codec_write(codec, 0x01, 0,
3249 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3250 snd_hda_codec_write(codec, 0x01, 0,
3251 AC_VERB_SET_GPIO_MASK, 0x1F);
3252 snd_hda_codec_write(codec, 0x01, 0,
3253 AC_VERB_SET_GPIO_DATA, 0x0C);
3254 break;
3255 }
3256}
3257
7e6ed62e
CM		 3258/*
3259 * GPIO control functions for the Recon3D integrated.
3260 */
3261
3262enum r3di_gpio_bit {
3263 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3264 R3DI_MIC_SELECT_BIT = 1,
3265 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3266 R3DI_OUT_SELECT_BIT = 2,
3267 /*
3268 * I dunno what this actually does, but it stays on until the dsp
3269 * is downloaded.
3270 */
3271 R3DI_GPIO_DSP_DOWNLOADING = 3,
3272 /*
3273 * Same as above, no clue what it does, but it comes on after the dsp
3274 * is downloaded.
3275 */
3276 R3DI_GPIO_DSP_DOWNLOADED = 4
3277};
3278
3279enum r3di_mic_select {
3280 /* Set GPIO bit 1 to 0 for rear mic */
3281 R3DI_REAR_MIC = 0,
3282 /* Set GPIO bit 1 to 1 for front microphone*/
3283 R3DI_FRONT_MIC = 1
3284};
3285
3286enum r3di_out_select {
3287 /* Set GPIO bit 2 to 0 for headphone */
3288 R3DI_HEADPHONE_OUT = 0,
3289 /* Set GPIO bit 2 to 1 for speaker */
3290 R3DI_LINE_OUT = 1
3291};
3292enum r3di_dsp_status {
3293 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3294 R3DI_DSP_DOWNLOADING = 0,
3295 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3296 R3DI_DSP_DOWNLOADED = 1
3297};
3298
7cb9d94c
CM		 3299
3300static void r3di_gpio_mic_set(struct hda_codec *codec,
3301 enum r3di_mic_select cur_mic)
3302{
3303 unsigned int cur_gpio;
3304
3305 /* Get the current GPIO Data setup */
3306 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3307
3308 switch (cur_mic) {
3309 case R3DI_REAR_MIC:
3310 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3311 break;
3312 case R3DI_FRONT_MIC:
3313 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3314 break;
3315 }
3316 snd_hda_codec_write(codec, codec->core.afg, 0,
3317 AC_VERB_SET_GPIO_DATA, cur_gpio);
3318}
3319
3320static void r3di_gpio_out_set(struct hda_codec *codec,
3321 enum r3di_out_select cur_out)
3322{
3323 unsigned int cur_gpio;
3324
3325 /* Get the current GPIO Data setup */
3326 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3327
3328 switch (cur_out) {
3329 case R3DI_HEADPHONE_OUT:
3330 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3331 break;
3332 case R3DI_LINE_OUT:
3333 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3334 break;
3335 }
3336 snd_hda_codec_write(codec, codec->core.afg, 0,
3337 AC_VERB_SET_GPIO_DATA, cur_gpio);
3338}
3339
7e6ed62e
CM		 3340static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3341 enum r3di_dsp_status dsp_status)
3342{
3343 unsigned int cur_gpio;
3344
3345 /* Get the current GPIO Data setup */
3346 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3347
3348 switch (dsp_status) {
3349 case R3DI_DSP_DOWNLOADING:
3350 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3351 snd_hda_codec_write(codec, codec->core.afg, 0,
3352 AC_VERB_SET_GPIO_DATA, cur_gpio);
3353 break;
3354 case R3DI_DSP_DOWNLOADED:
3355 /* Set DOWNLOADING bit to 0. */
3356 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3357
3358 snd_hda_codec_write(codec, codec->core.afg, 0,
3359 AC_VERB_SET_GPIO_DATA, cur_gpio);
3360
3361 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3362 break;
3363 }
3364
3365 snd_hda_codec_write(codec, codec->core.afg, 0,
3366 AC_VERB_SET_GPIO_DATA, cur_gpio);
3367}
3368
825315bc
IM		 3369/*
3370 * PCM callbacks
3371 */
95c6e9cb
IM		 3372static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3373 struct hda_codec *codec,
3374 unsigned int stream_tag,
3375 unsigned int format,
3376 struct snd_pcm_substream *substream)
3377{
3378 struct ca0132_spec *spec = codec->spec;
825315bc 3379
28fba950 3380 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3381
3382 return 0;
95c6e9cb
IM		 3383}
3384
3385static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3386 struct hda_codec *codec,
3387 struct snd_pcm_substream *substream)
3388{
3389 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3390
3391 if (spec->dsp_state == DSP_DOWNLOADING)
3392 return 0;
3393
3394 /*If Playback effects are on, allow stream some time to flush
3395 *effects tail*/
3396 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3397 msleep(50);
3398
28fba950 3399 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3400
3401 return 0;
95c6e9cb
IM		 3402}
3403
e8412ca4
DR		 3404static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3405 struct hda_codec *codec,
3406 struct snd_pcm_substream *substream)
3407{
3408 struct ca0132_spec *spec = codec->spec;
3409 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3410 struct snd_pcm_runtime *runtime = substream->runtime;
3411
3412 if (spec->dsp_state != DSP_DOWNLOADED)
3413 return 0;
3414
3415 /* Add latency if playback enhancement and either effect is enabled. */
3416 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3417 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3418 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3419 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3420 }
3421
3422 /* Applying Speaker EQ adds latency as well. */
3423 if (spec->cur_out_type == SPEAKER_OUT)
3424 latency += DSP_SPEAKER_OUT_LATENCY;
3425
3426 return (latency * runtime->rate) / 1000;
3427}
3428
95c6e9cb
IM		 3429/*
3430 * Digital out
3431 */
27ebeb0b
TI		 3432static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3433 struct hda_codec *codec,
3434 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3435{
3436 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3437 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3438}
3439
27ebeb0b 3440static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3441 struct hda_codec *codec,
3442 unsigned int stream_tag,
3443 unsigned int format,
3444 struct snd_pcm_substream *substream)
3445{
3446 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3447 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3448 stream_tag, format, substream);
95c6e9cb
IM		 3449}
3450
27ebeb0b 3451static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3452 struct hda_codec *codec,
95c6e9cb
IM		 3453 struct snd_pcm_substream *substream)
3454{
3455 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3456 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3457}
3458
27ebeb0b
TI		 3459static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3460 struct hda_codec *codec,
3461 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3462{
3463 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3464 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3465}
3466
825315bc
IM		 3467/*
3468 * Analog capture
3469 */
3470static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3471 struct hda_codec *codec,
3472 unsigned int stream_tag,
3473 unsigned int format,
3474 struct snd_pcm_substream *substream)
3475{
13c12dbe 3476 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3477 stream_tag, 0, format);
825315bc
IM		 3478
3479 return 0;
3480}
3481
3482static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3483 struct hda_codec *codec,
3484 struct snd_pcm_substream *substream)
3485{
3486 struct ca0132_spec *spec = codec->spec;
3487
3488 if (spec->dsp_state == DSP_DOWNLOADING)
3489 return 0;
3490
28fba950 3491 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3492 return 0;
3493}
3494
e8412ca4
DR		 3495static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3496 struct hda_codec *codec,
3497 struct snd_pcm_substream *substream)
3498{
3499 struct ca0132_spec *spec = codec->spec;
3500 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3501 struct snd_pcm_runtime *runtime = substream->runtime;
3502
3503 if (spec->dsp_state != DSP_DOWNLOADED)
3504 return 0;
3505
3506 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3507 latency += DSP_CRYSTAL_VOICE_LATENCY;
3508
3509 return (latency * runtime->rate) / 1000;
3510}
3511
e90f29e4
IM		 3512/*
3513 * Controls stuffs.
3514 */
3515
3516/*
3517 * Mixer controls helpers.
3518 */
3519#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3520 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3521 .name = xname, \
3522 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3523 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3524 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3525 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3526 .info = ca0132_volume_info, \
3527 .get = ca0132_volume_get, \
3528 .put = ca0132_volume_put, \
3529 .tlv = { .c = ca0132_volume_tlv }, \
3530 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3531
017310fb
CM		 3532/*
3533 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3534 * volume put, which is used for setting the DSP volume. This was done because
3535 * the ca0132 functions were taking too much time and causing lag.
3536 */
3537#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3538 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3539 .name = xname, \
3540 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3541 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3542 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3543 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3544 .info = snd_hda_mixer_amp_volume_info, \
3545 .get = snd_hda_mixer_amp_volume_get, \
3546 .put = ca0132_alt_volume_put, \
3547 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3548 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3549
e90f29e4
IM		 3550#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3551 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3552 .name = xname, \
3553 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3554 .info = snd_hda_mixer_amp_switch_info, \
3555 .get = ca0132_switch_get, \
3556 .put = ca0132_switch_put, \
3557 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3558
3559/* stereo */
3560#define CA0132_CODEC_VOL(xname, nid, dir) \
3561 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3562#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3563 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3564#define CA0132_CODEC_MUTE(xname, nid, dir) \
3565 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3566
017310fb
CM		 3567/* lookup tables */
3568/*
3569 * Lookup table with decibel values for the DSP. When volume is changed in
3570 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3571 * these values have decimal points, probably because the Windows driver
3572 * actually uses floating point. We can't here, so I made a lookup table of
3573 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3574 * DAC's, and 9 is the maximum.
3575 */
3576static const unsigned int float_vol_db_lookup[] = {
35770xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
35780xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
35790xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
35800xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
35810xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
35820xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
35830xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
35840xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
35850xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
35860xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
35870xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
35880xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
35890xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
35900xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
35910xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
35920x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
35930x40C00000, 0x40E00000, 0x41000000, 0x41100000
3594};
3595
47cdf76e
CM		 3596/*
3597 * This table counts from float 0 to 1 in increments of .01, which is
3598 * useful for a few different sliders.
3599 */
3600static const unsigned int float_zero_to_one_lookup[] = {
36010x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
36020x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
36030x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
36040x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
36050x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
36060x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
36070x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
36080x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
36090x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
36100x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
36110x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
36120x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
36130x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
36140x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
36150x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
36160x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
36170x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3618};
3619
3620/*
3621 * This table counts from float 10 to 1000, which is the range of the x-bass
3622 * crossover slider in Windows.
3623 */
3624static const unsigned int float_xbass_xover_lookup[] = {
36250x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
36260x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
36270x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
36280x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
36290x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
36300x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
36310x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
36320x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
36330x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
36340x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
36350x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
36360x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
36370x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
36380x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
36390x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
36400x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
36410x44728000, 0x44750000, 0x44778000, 0x447A0000
3642};
3643
4091fb95 3644/* The following are for tuning of products */
44f0c978
IM		 3645#ifdef ENABLE_TUNING_CONTROLS
3646
3647static unsigned int voice_focus_vals_lookup[] = {
36480x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
36490x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
36500x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
36510x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
36520x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
36530x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
36540x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
36550x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
36560x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
36570x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
36580x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
36590x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
36600x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
36610x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
36620x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
36630x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
36640x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
36650x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
36660x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
36670x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
36680x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
36690x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
36700x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
36710x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
36720x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
36730x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
36740x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3675};
3676
3677static unsigned int mic_svm_vals_lookup[] = {
36780x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
36790x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
36800x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
36810x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
36820x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
36830x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
36840x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
36850x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
36860x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
36870x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
36880x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
36890x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
36900x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
36910x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
36920x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
36930x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
36940x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3695};
3696
3697static unsigned int equalizer_vals_lookup[] = {
36980xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
36990xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
37000xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
37010xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
37020x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
37030x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
37040x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
37050x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
37060x41C00000
3707};
3708
3709static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3710 unsigned int *lookup, int idx)
3711{
3712 int i = 0;
3713
3714 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3715 if (nid == ca0132_tuning_ctls[i].nid)
3716 break;
3717
3718 snd_hda_power_up(codec);
447fd8e9 3719 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3720 ca0132_tuning_ctls[i].req,
3721 &(lookup[idx]), sizeof(unsigned int));
3722 snd_hda_power_down(codec);
3723
3724 return 1;
3725}
3726
3727static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3728 struct snd_ctl_elem_value *ucontrol)
3729{
3730 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3731 struct ca0132_spec *spec = codec->spec;
3732 hda_nid_t nid = get_amp_nid(kcontrol);
3733 long *valp = ucontrol->value.integer.value;
3734 int idx = nid - TUNING_CTL_START_NID;
3735
3736 *valp = spec->cur_ctl_vals[idx];
3737 return 0;
3738}
3739
3740static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3741 struct snd_ctl_elem_info *uinfo)
3742{
3743 int chs = get_amp_channels(kcontrol);
3744 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3745 uinfo->count = chs == 3 ? 2 : 1;
3746 uinfo->value.integer.min = 20;
3747 uinfo->value.integer.max = 180;
3748 uinfo->value.integer.step = 1;
3749
3750 return 0;
3751}
3752
3753static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3754 struct snd_ctl_elem_value *ucontrol)
3755{
3756 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3757 struct ca0132_spec *spec = codec->spec;
3758 hda_nid_t nid = get_amp_nid(kcontrol);
3759 long *valp = ucontrol->value.integer.value;
3760 int idx;
3761
3762 idx = nid - TUNING_CTL_START_NID;
3763 /* any change? */
3764 if (spec->cur_ctl_vals[idx] == *valp)
3765 return 0;
3766
3767 spec->cur_ctl_vals[idx] = *valp;
3768
3769 idx = *valp - 20;
3770 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3771
3772 return 1;
3773}
3774
3775static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3776 struct snd_ctl_elem_info *uinfo)
3777{
3778 int chs = get_amp_channels(kcontrol);
3779 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3780 uinfo->count = chs == 3 ? 2 : 1;
3781 uinfo->value.integer.min = 0;
3782 uinfo->value.integer.max = 100;
3783 uinfo->value.integer.step = 1;
3784
3785 return 0;
3786}
3787
3788static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3789 struct snd_ctl_elem_value *ucontrol)
3790{
3791 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3792 struct ca0132_spec *spec = codec->spec;
3793 hda_nid_t nid = get_amp_nid(kcontrol);
3794 long *valp = ucontrol->value.integer.value;
3795 int idx;
3796
3797 idx = nid - TUNING_CTL_START_NID;
3798 /* any change? */
3799 if (spec->cur_ctl_vals[idx] == *valp)
3800 return 0;
3801
3802 spec->cur_ctl_vals[idx] = *valp;
3803
3804 idx = *valp;
3805 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3806
3807 return 0;
3808}
3809
3810static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3811 struct snd_ctl_elem_info *uinfo)
3812{
3813 int chs = get_amp_channels(kcontrol);
3814 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3815 uinfo->count = chs == 3 ? 2 : 1;
3816 uinfo->value.integer.min = 0;
3817 uinfo->value.integer.max = 48;
3818 uinfo->value.integer.step = 1;
3819
3820 return 0;
3821}
3822
3823static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3824 struct snd_ctl_elem_value *ucontrol)
3825{
3826 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3827 struct ca0132_spec *spec = codec->spec;
3828 hda_nid_t nid = get_amp_nid(kcontrol);
3829 long *valp = ucontrol->value.integer.value;
3830 int idx;
3831
3832 idx = nid - TUNING_CTL_START_NID;
3833 /* any change? */
3834 if (spec->cur_ctl_vals[idx] == *valp)
3835 return 0;
3836
3837 spec->cur_ctl_vals[idx] = *valp;
3838
3839 idx = *valp;
3840 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3841
3842 return 1;
3843}
3844
8e142e9e
TS		 3845static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3846static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3847
3848static int add_tuning_control(struct hda_codec *codec,
3849 hda_nid_t pnid, hda_nid_t nid,
3850 const char *name, int dir)
3851{
975cc02a 3852 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3853 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3854 struct snd_kcontrol_new knew =
3855 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3856
3857 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3858 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3859 knew.tlv.c = 0;
3860 knew.tlv.p = 0;
3861 switch (pnid) {
3862 case VOICE_FOCUS:
3863 knew.info = voice_focus_ctl_info;
3864 knew.get = tuning_ctl_get;
3865 knew.put = voice_focus_ctl_put;
3866 knew.tlv.p = voice_focus_db_scale;
3867 break;
3868 case MIC_SVM:
3869 knew.info = mic_svm_ctl_info;
3870 knew.get = tuning_ctl_get;
3871 knew.put = mic_svm_ctl_put;
3872 break;
3873 case EQUALIZER:
3874 knew.info = equalizer_ctl_info;
3875 knew.get = tuning_ctl_get;
3876 knew.put = equalizer_ctl_put;
3877 knew.tlv.p = eq_db_scale;
3878 break;
3879 default:
3880 return 0;
3881 }
3882 knew.private_value =
3883 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3884 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3885 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3886}
3887
3888static int add_tuning_ctls(struct hda_codec *codec)
3889{
3890 int i;
3891 int err;
3892
3893 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3894 err = add_tuning_control(codec,
3895 ca0132_tuning_ctls[i].parent_nid,
3896 ca0132_tuning_ctls[i].nid,
3897 ca0132_tuning_ctls[i].name,
3898 ca0132_tuning_ctls[i].direct);
3899 if (err < 0)
3900 return err;
3901 }
3902
3903 return 0;
3904}
3905
3906static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3907{
3908 struct ca0132_spec *spec = codec->spec;
3909 int i;
3910
3911 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3912 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3913 /* SVM level defaults to 0.74. */
3914 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3915
3916 /* EQ defaults to 0dB. */
3917 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3918 spec->cur_ctl_vals[i] = 24;
3919}
3920#endif /*ENABLE_TUNING_CONTROLS*/
3921
5aaca44d
IM		 3922/*
3923 * Select the active output.
3924 * If autodetect is enabled, output will be selected based on jack detection.
3925 * If jack inserted, headphone will be selected, else built-in speakers
3926 * If autodetect is disabled, output will be selected based on selection.
3927 */
3928static int ca0132_select_out(struct hda_codec *codec)
3929{
3930 struct ca0132_spec *spec = codec->spec;
3931 unsigned int pin_ctl;
3932 int jack_present;
3933 int auto_jack;
3934 unsigned int tmp;
3935 int err;
3936
4e76a883 3937 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3938
664c7155 3939 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3940
3941 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3942
3943 if (auto_jack)
fe14f39e 3944 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3945 else
3946 jack_present =
3947 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3948
3949 if (jack_present)
3950 spec->cur_out_type = HEADPHONE_OUT;
3951 else
3952 spec->cur_out_type = SPEAKER_OUT;
3953
3954 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3955 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3956 /*speaker out config*/
3957 tmp = FLOAT_ONE;
3958 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3959 if (err < 0)
3960 goto exit;
3961 /*enable speaker EQ*/
3962 tmp = FLOAT_ONE;
3963 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3964 if (err < 0)
3965 goto exit;
3966
3967 /* Setup EAPD */
3968 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3969 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3970 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3971 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3972 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3973 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3974 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3975 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3976
3977 /* disable headphone node */
3978 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3979 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3980 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3981 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3982 /* enable speaker node */
3983 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 3984 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3985 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3986 pin_ctl | PIN_OUT);
5aaca44d 3987 } else {
4e76a883 3988 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3989 /*headphone out config*/
3990 tmp = FLOAT_ZERO;
3991 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3992 if (err < 0)
3993 goto exit;
3994 /*disable speaker EQ*/
3995 tmp = FLOAT_ZERO;
3996 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3997 if (err < 0)
3998 goto exit;
3999
4000 /* Setup EAPD */
4001 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4002 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4003 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4004 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4005 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4006 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4007 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4008 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4009
4010 /* disable speaker*/
4011 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4012 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4013 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4014 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4015 /* enable headphone*/
4016 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4017 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4018 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4019 pin_ctl | PIN_HP);
5aaca44d
IM		 4020 }
4021
4022exit:
664c7155 4023 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4024
4025 return err < 0 ? err : 0;
4026}
4027
7cb9d94c
CM		 4028/*
4029 * This function behaves similarly to the ca0132_select_out funciton above,
4030 * except with a few differences. It adds the ability to select the current
4031 * output with an enumerated control "output source" if the auto detect
4032 * mute switch is set to off. If the auto detect mute switch is enabled, it
4033 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4034 * It also adds the ability to auto-detect the front headphone port. The only
4035 * way to select surround is to disable auto detect, and set Surround with the
4036 * enumerated control.
4037 */
4038static int ca0132_alt_select_out(struct hda_codec *codec)
4039{
4040 struct ca0132_spec *spec = codec->spec;
4041 unsigned int pin_ctl;
4042 int jack_present;
4043 int auto_jack;
4044 unsigned int i;
4045 unsigned int tmp;
4046 int err;
4047 /* Default Headphone is rear headphone */
4048 hda_nid_t headphone_nid = spec->out_pins[1];
4049
4050 codec_dbg(codec, "%s\n", __func__);
4051
4052 snd_hda_power_up_pm(codec);
4053
4054 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4055
4056 /*
4057 * If headphone rear or front is plugged in, set to headphone.
4058 * If neither is plugged in, set to rear line out. Only if
4059 * hp/speaker auto detect is enabled.
4060 */
4061 if (auto_jack) {
4062 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4063 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4064
4065 if (jack_present)
4066 spec->cur_out_type = HEADPHONE_OUT;
4067 else
4068 spec->cur_out_type = SPEAKER_OUT;
4069 } else
4070 spec->cur_out_type = spec->out_enum_val;
4071
4072 /* Begin DSP output switch */
4073 tmp = FLOAT_ONE;
4074 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4075 if (err < 0)
4076 goto exit;
4077
4078 switch (spec->cur_out_type) {
4079 case SPEAKER_OUT:
4080 codec_dbg(codec, "%s speaker\n", __func__);
4081 /*speaker out config*/
4082 switch (spec->quirk) {
4083 case QUIRK_SBZ:
b9b41345
CM		 4084 ca0113_mmio_gpio_set(codec, 7, false);
4085 ca0113_mmio_gpio_set(codec, 4, true);
4086 ca0113_mmio_gpio_set(codec, 1, true);
7cb9d94c
CM		 4087 chipio_set_control_param(codec, 0x0D, 0x18);
4088 break;
4089 case QUIRK_R3DI:
4090 chipio_set_control_param(codec, 0x0D, 0x24);
4091 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4092 break;
42aa3a16
CM		 4093 case QUIRK_R3D:
4094 chipio_set_control_param(codec, 0x0D, 0x24);
b9b41345 4095 ca0113_mmio_gpio_set(codec, 1, true);
42aa3a16 4096 break;
7cb9d94c
CM		 4097 }
4098
4099 /* disable headphone node */
4100 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4101 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4102 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4103 pin_ctl & ~PIN_HP);
4104 /* enable line-out node */
4105 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4106 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4107 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4108 pin_ctl | PIN_OUT);
4109 /* Enable EAPD */
4110 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4111 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4112
4113 /* If PlayEnhancement is enabled, set different source */
4114 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4115 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4116 else
4117 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4118 break;
4119 case HEADPHONE_OUT:
4120 codec_dbg(codec, "%s hp\n", __func__);
4121 /* Headphone out config*/
4122 switch (spec->quirk) {
4123 case QUIRK_SBZ:
b9b41345
CM		 4124 ca0113_mmio_gpio_set(codec, 7, true);
4125 ca0113_mmio_gpio_set(codec, 4, true);
4126 ca0113_mmio_gpio_set(codec, 1, false);
7cb9d94c
CM		 4127 chipio_set_control_param(codec, 0x0D, 0x12);
4128 break;
4129 case QUIRK_R3DI:
4130 chipio_set_control_param(codec, 0x0D, 0x21);
4131 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4132 break;
42aa3a16
CM		 4133 case QUIRK_R3D:
4134 chipio_set_control_param(codec, 0x0D, 0x21);
b9b41345 4135 ca0113_mmio_gpio_set(codec, 0x1, false);
42aa3a16 4136 break;
7cb9d94c
CM		 4137 }
4138
4139 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4140 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4141
4142 /* disable speaker*/
4143 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4144 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4145 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4146 pin_ctl & ~PIN_HP);
4147
4148 /* enable headphone, either front or rear */
4149
4150 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4151 headphone_nid = spec->out_pins[2];
4152 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4153 headphone_nid = spec->out_pins[1];
4154
4155 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4156 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4157 snd_hda_set_pin_ctl(codec, headphone_nid,
4158 pin_ctl | PIN_HP);
4159
4160 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4161 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4162 else
4163 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4164 break;
4165 case SURROUND_OUT:
4166 codec_dbg(codec, "%s surround\n", __func__);
4167 /* Surround out config*/
4168 switch (spec->quirk) {
4169 case QUIRK_SBZ:
b9b41345
CM		 4170 ca0113_mmio_gpio_set(codec, 7, false);
4171 ca0113_mmio_gpio_set(codec, 4, true);
4172 ca0113_mmio_gpio_set(codec, 1, true);
7cb9d94c
CM		 4173 chipio_set_control_param(codec, 0x0D, 0x18);
4174 break;
4175 case QUIRK_R3DI:
4176 chipio_set_control_param(codec, 0x0D, 0x24);
4177 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4178 break;
42aa3a16 4179 case QUIRK_R3D:
b9b41345 4180 ca0113_mmio_gpio_set(codec, 1, true);
42aa3a16
CM		 4181 chipio_set_control_param(codec, 0x0D, 0x24);
4182 break;
7cb9d94c
CM		 4183 }
4184 /* enable line out node */
4185 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4186 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4187 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4188 pin_ctl | PIN_OUT);
4189 /* Disable headphone out */
4190 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4191 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4192 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4193 pin_ctl & ~PIN_HP);
4194 /* Enable EAPD on line out */
4195 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4196 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4197 /* enable center/lfe out node */
4198 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4199 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4200 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4201 pin_ctl | PIN_OUT);
4202 /* Now set rear surround node as out. */
4203 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4204 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4205 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4206 pin_ctl | PIN_OUT);
4207
4208 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4209 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4210 else
4211 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4212 break;
4213 }
4214
4215 /* run through the output dsp commands for line-out */
4216 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4217 err = dspio_set_uint_param(codec,
4218 alt_out_presets[spec->cur_out_type].mids[i],
4219 alt_out_presets[spec->cur_out_type].reqs[i],
4220 alt_out_presets[spec->cur_out_type].vals[i]);
4221
4222 if (err < 0)
4223 goto exit;
4224 }
4225
4226exit:
4227 snd_hda_power_down_pm(codec);
4228
4229 return err < 0 ? err : 0;
4230}
4231
993884f6
CCC		 4232static void ca0132_unsol_hp_delayed(struct work_struct *work)
4233{
4234 struct ca0132_spec *spec = container_of(
4235 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4236 struct hda_jack_tbl *jack;
4237
7cb9d94c
CM		 4238 if (spec->use_alt_functions)
4239 ca0132_alt_select_out(spec->codec);
4240 else
4241 ca0132_select_out(spec->codec);
4242
d5c016b5 4243 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4244 if (jack) {
4245 jack->block_report = 0;
4246 snd_hda_jack_report_sync(spec->codec);
4247 }
993884f6
CCC		 4248}
4249
5aaca44d
IM		 4250static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4251static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4252static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
e0026d03
CM		 4253static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4254static int stop_mic1(struct hda_codec *codec);
4255static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4256static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4257
4258/*
4259 * Select the active VIP source
4260 */
4261static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4262{
4263 struct ca0132_spec *spec = codec->spec;
4264 unsigned int tmp;
4265
e8f1bd5d 4266 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4267 return 0;
4268
4269 /* if CrystalVoice if off, vipsource should be 0 */
4270 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4271 (val == 0)) {
4272 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4273 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4274 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4275 if (spec->cur_mic_type == DIGITAL_MIC)
4276 tmp = FLOAT_TWO;
4277 else
4278 tmp = FLOAT_ONE;
4279 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4280 tmp = FLOAT_ZERO;
4281 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4282 } else {
4283 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4284 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4285 if (spec->cur_mic_type == DIGITAL_MIC)
4286 tmp = FLOAT_TWO;
4287 else
4288 tmp = FLOAT_ONE;
4289 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4290 tmp = FLOAT_ONE;
4291 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4292 msleep(20);
4293 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4294 }
4295
4296 return 1;
4297}
4298
e0026d03
CM		 4299static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4300{
4301 struct ca0132_spec *spec = codec->spec;
4302 unsigned int tmp;
4303
4304 if (spec->dsp_state != DSP_DOWNLOADED)
4305 return 0;
4306
4307 codec_dbg(codec, "%s\n", __func__);
4308
4309 chipio_set_stream_control(codec, 0x03, 0);
4310 chipio_set_stream_control(codec, 0x04, 0);
4311
4312 /* if CrystalVoice is off, vipsource should be 0 */
4313 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4314 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4315 codec_dbg(codec, "%s: off.", __func__);
4316 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4317
4318 tmp = FLOAT_ZERO;
4319 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4320
4321 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4322 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4323 if (spec->quirk == QUIRK_R3DI)
4324 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4325
4326
4327 if (spec->in_enum_val == REAR_LINE_IN)
4328 tmp = FLOAT_ZERO;
4329 else {
4330 if (spec->quirk == QUIRK_SBZ)
4331 tmp = FLOAT_THREE;
4332 else
4333 tmp = FLOAT_ONE;
4334 }
4335
4336 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4337
4338 } else {
4339 codec_dbg(codec, "%s: on.", __func__);
4340 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4341 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4342 if (spec->quirk == QUIRK_R3DI)
4343 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4344
4345 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4346 tmp = FLOAT_TWO;
4347 else
4348 tmp = FLOAT_ONE;
4349 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4350
4351 tmp = FLOAT_ONE;
4352 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4353
4354 msleep(20);
4355 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4356 }
4357
4358 chipio_set_stream_control(codec, 0x03, 1);
4359 chipio_set_stream_control(codec, 0x04, 1);
4360
4361 return 1;
4362}
4363
5aaca44d
IM		 4364/*
4365 * Select the active microphone.
4366 * If autodetect is enabled, mic will be selected based on jack detection.
4367 * If jack inserted, ext.mic will be selected, else built-in mic
4368 * If autodetect is disabled, mic will be selected based on selection.
4369 */
4370static int ca0132_select_mic(struct hda_codec *codec)
4371{
4372 struct ca0132_spec *spec = codec->spec;
4373 int jack_present;
4374 int auto_jack;
4375
4e76a883 4376 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4377
664c7155 4378 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4379
4380 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4381
4382 if (auto_jack)
fe14f39e 4383 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4384 else
4385 jack_present =
4386 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4387
4388 if (jack_present)
4389 spec->cur_mic_type = LINE_MIC_IN;
4390 else
4391 spec->cur_mic_type = DIGITAL_MIC;
4392
4393 if (spec->cur_mic_type == DIGITAL_MIC) {
4394 /* enable digital Mic */
4395 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4396 ca0132_set_dmic(codec, 1);
4397 ca0132_mic_boost_set(codec, 0);
4398 /* set voice focus */
4399 ca0132_effects_set(codec, VOICE_FOCUS,
4400 spec->effects_switch
4401 [VOICE_FOCUS - EFFECT_START_NID]);
4402 } else {
4403 /* disable digital Mic */
4404 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4405 ca0132_set_dmic(codec, 0);
4406 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4407 /* disable voice focus */
4408 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4409 }
4410
664c7155 4411 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4412
4413 return 0;
4414}
4415
7cb9d94c
CM		 4416/*
4417 * Select the active input.
4418 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4419 * The front mic has no jack-detection, so the only way to switch to it
4420 * is to do it manually in alsamixer.
4421 */
4422static int ca0132_alt_select_in(struct hda_codec *codec)
4423{
4424 struct ca0132_spec *spec = codec->spec;
4425 unsigned int tmp;
4426
4427 codec_dbg(codec, "%s\n", __func__);
4428
4429 snd_hda_power_up_pm(codec);
4430
4431 chipio_set_stream_control(codec, 0x03, 0);
4432 chipio_set_stream_control(codec, 0x04, 0);
4433
4434 spec->cur_mic_type = spec->in_enum_val;
4435
4436 switch (spec->cur_mic_type) {
4437 case REAR_MIC:
4438 switch (spec->quirk) {
4439 case QUIRK_SBZ:
42aa3a16 4440 case QUIRK_R3D:
b9b41345 4441 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4442 tmp = FLOAT_THREE;
4443 break;
4444 case QUIRK_R3DI:
4445 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4446 tmp = FLOAT_ONE;
4447 break;
4448 default:
4449 tmp = FLOAT_ONE;
4450 break;
4451 }
4452
4453 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4454 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4455 if (spec->quirk == QUIRK_R3DI)
4456 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4457
4458 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4459
4460 chipio_set_stream_control(codec, 0x03, 1);
4461 chipio_set_stream_control(codec, 0x04, 1);
4462
4463 if (spec->quirk == QUIRK_SBZ) {
4464 chipio_write(codec, 0x18B098, 0x0000000C);
4465 chipio_write(codec, 0x18B09C, 0x0000000C);
4466 }
47cdf76e 4467 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4468 break;
4469 case REAR_LINE_IN:
4470 ca0132_mic_boost_set(codec, 0);
4471 switch (spec->quirk) {
4472 case QUIRK_SBZ:
42aa3a16 4473 case QUIRK_R3D:
b9b41345 4474 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4475 break;
4476 case QUIRK_R3DI:
4477 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4478 break;
4479 }
4480
4481 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4482 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4483 if (spec->quirk == QUIRK_R3DI)
4484 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4485
4486 tmp = FLOAT_ZERO;
4487 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4488
4489 if (spec->quirk == QUIRK_SBZ) {
4490 chipio_write(codec, 0x18B098, 0x00000000);
4491 chipio_write(codec, 0x18B09C, 0x00000000);
4492 }
4493
4494 chipio_set_stream_control(codec, 0x03, 1);
4495 chipio_set_stream_control(codec, 0x04, 1);
4496 break;
4497 case FRONT_MIC:
4498 switch (spec->quirk) {
4499 case QUIRK_SBZ:
42aa3a16 4500 case QUIRK_R3D:
b9b41345
CM		 4501 ca0113_mmio_gpio_set(codec, 0, true);
4502 ca0113_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4503 tmp = FLOAT_THREE;
4504 break;
4505 case QUIRK_R3DI:
4506 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4507 tmp = FLOAT_ONE;
4508 break;
4509 default:
4510 tmp = FLOAT_ONE;
4511 break;
4512 }
4513
4514 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4515 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4516 if (spec->quirk == QUIRK_R3DI)
4517 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4518
4519 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4520
4521 chipio_set_stream_control(codec, 0x03, 1);
4522 chipio_set_stream_control(codec, 0x04, 1);
4523
4524 if (spec->quirk == QUIRK_SBZ) {
4525 chipio_write(codec, 0x18B098, 0x0000000C);
4526 chipio_write(codec, 0x18B09C, 0x000000CC);
4527 }
47cdf76e 4528 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4529 break;
4530 }
e0026d03 4531 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4532
4533 snd_hda_power_down_pm(codec);
4534 return 0;
4535
4536}
4537
a7e76271
IM		 4538/*
4539 * Check if VNODE settings take effect immediately.
4540 */
4541static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4542 hda_nid_t vnid,
4543 hda_nid_t *shared_nid)
4544{
4545 struct ca0132_spec *spec = codec->spec;
4546 hda_nid_t nid;
a7e76271
IM		 4547
4548 switch (vnid) {
4549 case VNID_SPK:
4550 nid = spec->shared_out_nid;
a7e76271
IM		 4551 break;
4552 case VNID_MIC:
4553 nid = spec->shared_mic_nid;
a7e76271
IM		 4554 break;
4555 default:
9a0869f4 4556 return false;
a7e76271
IM		 4557 }
4558
9a0869f4 4559 if (shared_nid)
a7e76271
IM		 4560 *shared_nid = nid;
4561
9a0869f4 4562 return true;
a7e76271
IM		 4563}
4564
4565/*
4566* The following functions are control change helpers.
4567* They return 0 if no changed. Return 1 if changed.
4568*/
4569static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4570{
4571 struct ca0132_spec *spec = codec->spec;
4572 unsigned int tmp;
4573
4574 /* based on CrystalVoice state to enable VoiceFX. */
4575 if (enable) {
4576 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4577 FLOAT_ONE : FLOAT_ZERO;
4578 } else {
4579 tmp = FLOAT_ZERO;
4580 }
4581
4582 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4583 ca0132_voicefx.reqs[0], tmp);
4584
4585 return 1;
4586}
4587
5aaca44d
IM		 4588/*
4589 * Set the effects parameters
4590 */
4591static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4592{
4593 struct ca0132_spec *spec = codec->spec;
009b8f97 4594 unsigned int on, tmp;
5aaca44d
IM		 4595 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4596 int err = 0;
4597 int idx = nid - EFFECT_START_NID;
4598
4599 if ((idx < 0) || (idx >= num_fx))
4600 return 0; /* no changed */
4601
4602 /* for out effect, qualify with PE */
4603 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4604 /* if PE if off, turn off out effects. */
4605 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4606 val = 0;
4607 }
4608
4609 /* for in effect, qualify with CrystalVoice */
4610 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4611 /* if CrystalVoice if off, turn off in effects. */
4612 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4613 val = 0;
4614
4615 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4616 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4617 val = 0;
009b8f97
CM		 4618
4619 /* If Voice Focus on SBZ, set to two channel. */
7cb9d94c
CM		 4620 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4621 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4622 if (spec->effects_switch[CRYSTAL_VOICE -
4623 EFFECT_START_NID]) {
4624
4625 if (spec->effects_switch[VOICE_FOCUS -
4626 EFFECT_START_NID]) {
4627 tmp = FLOAT_TWO;
4628 val = 1;
4629 } else
4630 tmp = FLOAT_ONE;
4631
4632 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4633 }
4634 }
4635 /*
4636 * For SBZ noise reduction, there's an extra command
4637 * to module ID 0x47. No clue why.
4638 */
7cb9d94c
CM		 4639 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4640 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4641 if (spec->effects_switch[CRYSTAL_VOICE -
4642 EFFECT_START_NID]) {
4643 if (spec->effects_switch[NOISE_REDUCTION -
4644 EFFECT_START_NID])
4645 tmp = FLOAT_ONE;
4646 else
4647 tmp = FLOAT_ZERO;
4648 } else
4649 tmp = FLOAT_ZERO;
4650
4651 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4652 }
7cb9d94c
CM		 4653
4654 /* If rear line in disable effects. */
4655 if (spec->use_alt_functions &&
4656 spec->in_enum_val == REAR_LINE_IN)
4657 val = 0;
5aaca44d
IM		 4658 }
4659
4e76a883 4660 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4661 nid, val);
4662
4663 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4664 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4665 ca0132_effects[idx].reqs[0], on);
4666
4667 if (err < 0)
4668 return 0; /* no changed */
4669
4670 return 1;
4671}
4672
a7e76271
IM		 4673/*
4674 * Turn on/off Playback Enhancements
4675 */
4676static int ca0132_pe_switch_set(struct hda_codec *codec)
4677{
4678 struct ca0132_spec *spec = codec->spec;
4679 hda_nid_t nid;
4680 int i, ret = 0;
4681
4e76a883 4682 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4683 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4684
7cb9d94c
CM		 4685 if (spec->use_alt_functions)
4686 ca0132_alt_select_out(codec);
4687
a7e76271
IM		 4688 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4689 nid = OUT_EFFECT_START_NID;
4690 /* PE affects all out effects */
4691 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4692 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4693
4694 return ret;
4695}
4696
5aaca44d
IM		 4697/* Check if Mic1 is streaming, if so, stop streaming */
4698static int stop_mic1(struct hda_codec *codec)
4699{
4700 struct ca0132_spec *spec = codec->spec;
4701 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4702 AC_VERB_GET_CONV, 0);
4703 if (oldval != 0)
4704 snd_hda_codec_write(codec, spec->adcs[0], 0,
4705 AC_VERB_SET_CHANNEL_STREAMID,
4706 0);
4707 return oldval;
4708}
4709
4710/* Resume Mic1 streaming if it was stopped. */
4711static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4712{
4713 struct ca0132_spec *spec = codec->spec;
4714 /* Restore the previous stream and channel */
4715 if (oldval != 0)
4716 snd_hda_codec_write(codec, spec->adcs[0], 0,
4717 AC_VERB_SET_CHANNEL_STREAMID,
4718 oldval);
4719}
4720
4721/*
a7e76271 4722 * Turn on/off CrystalVoice
5aaca44d 4723 */
a7e76271
IM		 4724static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4725{
4726 struct ca0132_spec *spec = codec->spec;
4727 hda_nid_t nid;
4728 int i, ret = 0;
4729 unsigned int oldval;
4730
4e76a883 4731 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4732 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4733
4734 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4735 nid = IN_EFFECT_START_NID;
4736 /* CrystalVoice affects all in effects */
4737 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4738 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4739
4740 /* including VoiceFX */
4741 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4742
4743 /* set correct vipsource */
4744 oldval = stop_mic1(codec);
e0026d03
CM		 4745 if (spec->use_alt_functions)
4746 ret |= ca0132_alt_set_vipsource(codec, 1);
4747 else
4748 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 4749 resume_mic1(codec, oldval);
4750 return ret;
4751}
4752
5aaca44d
IM		 4753static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4754{
4755 struct ca0132_spec *spec = codec->spec;
4756 int ret = 0;
4757
4758 if (val) /* on */
4759 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4760 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4761 else /* off */
4762 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4763 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4764
4765 return ret;
4766}
4767
47cdf76e
CM		 4768static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4769{
4770 struct ca0132_spec *spec = codec->spec;
4771 int ret = 0;
4772
4773 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4774 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4775 return ret;
4776}
4777
a7e76271
IM		 4778static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4779 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 4780{
a7e76271
IM		 4781 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4782 hda_nid_t nid = get_amp_nid(kcontrol);
4783 hda_nid_t shared_nid = 0;
4784 bool effective;
4785 int ret = 0;
95c6e9cb 4786 struct ca0132_spec *spec = codec->spec;
a7e76271 4787 int auto_jack;
95c6e9cb 4788
a7e76271
IM		 4789 if (nid == VNID_HP_SEL) {
4790 auto_jack =
4791 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 4792 if (!auto_jack) {
4793 if (spec->use_alt_functions)
4794 ca0132_alt_select_out(codec);
4795 else
4796 ca0132_select_out(codec);
4797 }
a7e76271
IM		 4798 return 1;
4799 }
95c6e9cb 4800
a7e76271
IM		 4801 if (nid == VNID_AMIC1_SEL) {
4802 auto_jack =
4803 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4804 if (!auto_jack)
4805 ca0132_select_mic(codec);
4806 return 1;
4807 }
95c6e9cb 4808
a7e76271 4809 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 4810 if (spec->use_alt_functions)
4811 ca0132_alt_select_out(codec);
4812 else
4813 ca0132_select_out(codec);
a7e76271
IM		 4814 return 1;
4815 }
95c6e9cb 4816
a7e76271
IM		 4817 if (nid == VNID_AMIC1_ASEL) {
4818 ca0132_select_mic(codec);
4819 return 1;
95c6e9cb 4820 }
a7e76271
IM		 4821
4822 /* if effective conditions, then update hw immediately. */
4823 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4824 if (effective) {
4825 int dir = get_amp_direction(kcontrol);
4826 int ch = get_amp_channels(kcontrol);
4827 unsigned long pval;
4828
4829 mutex_lock(&codec->control_mutex);
4830 pval = kcontrol->private_value;
4831 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4832 0, dir);
4833 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4834 kcontrol->private_value = pval;
4835 mutex_unlock(&codec->control_mutex);
95c6e9cb 4836 }
95c6e9cb 4837
a7e76271 4838 return ret;
95c6e9cb 4839}
a7e76271 4840/* End of control change helpers. */
47cdf76e
CM		 4841/*
4842 * Below I've added controls to mess with the effect levels, I've only enabled
4843 * them on the Sound Blaster Z, but they would probably also work on the
4844 * Chromebook. I figured they were probably tuned specifically for it, and left
4845 * out for a reason.
4846 */
4847
4848/* Sets DSP effect level from the sliders above the controls */
4849static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4850 const unsigned int *lookup, int idx)
4851{
4852 int i = 0;
4853 unsigned int y;
4854 /*
4855 * For X_BASS, req 2 is actually crossover freq instead of
4856 * effect level
4857 */
4858 if (nid == X_BASS)
4859 y = 2;
4860 else
4861 y = 1;
4862
4863 snd_hda_power_up(codec);
4864 if (nid == XBASS_XOVER) {
4865 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4866 if (ca0132_effects[i].nid == X_BASS)
4867 break;
4868
4869 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4870 ca0132_effects[i].reqs[1],
4871 &(lookup[idx - 1]), sizeof(unsigned int));
4872 } else {
4873 /* Find the actual effect structure */
4874 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4875 if (nid == ca0132_effects[i].nid)
4876 break;
4877
4878 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4879 ca0132_effects[i].reqs[y],
4880 &(lookup[idx]), sizeof(unsigned int));
4881 }
4882
4883 snd_hda_power_down(codec);
4884
4885 return 0;
4886}
4887
4888static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4889 struct snd_ctl_elem_value *ucontrol)
4890{
4891 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4892 struct ca0132_spec *spec = codec->spec;
4893 long *valp = ucontrol->value.integer.value;
4894
4895 *valp = spec->xbass_xover_freq;
4896 return 0;
4897}
4898
4899static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4900 struct snd_ctl_elem_value *ucontrol)
4901{
4902 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4903 struct ca0132_spec *spec = codec->spec;
4904 hda_nid_t nid = get_amp_nid(kcontrol);
4905 long *valp = ucontrol->value.integer.value;
4906 int idx = nid - OUT_EFFECT_START_NID;
4907
4908 *valp = spec->fx_ctl_val[idx];
4909 return 0;
4910}
4911
4912/*
4913 * The X-bass crossover starts at 10hz, so the min is 1. The
4914 * frequency is set in multiples of 10.
4915 */
4916static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4917 struct snd_ctl_elem_info *uinfo)
4918{
4919 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4920 uinfo->count = 1;
4921 uinfo->value.integer.min = 1;
4922 uinfo->value.integer.max = 100;
4923 uinfo->value.integer.step = 1;
4924
4925 return 0;
4926}
4927
4928static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4929 struct snd_ctl_elem_info *uinfo)
4930{
4931 int chs = get_amp_channels(kcontrol);
4932
4933 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4934 uinfo->count = chs == 3 ? 2 : 1;
4935 uinfo->value.integer.min = 0;
4936 uinfo->value.integer.max = 100;
4937 uinfo->value.integer.step = 1;
4938
4939 return 0;
4940}
4941
4942static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4943 struct snd_ctl_elem_value *ucontrol)
4944{
4945 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4946 struct ca0132_spec *spec = codec->spec;
4947 hda_nid_t nid = get_amp_nid(kcontrol);
4948 long *valp = ucontrol->value.integer.value;
4949 int idx;
4950
4951 /* any change? */
4952 if (spec->xbass_xover_freq == *valp)
4953 return 0;
4954
4955 spec->xbass_xover_freq = *valp;
4956
4957 idx = *valp;
4958 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4959
4960 return 0;
4961}
4962
4963static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4964 struct snd_ctl_elem_value *ucontrol)
4965{
4966 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4967 struct ca0132_spec *spec = codec->spec;
4968 hda_nid_t nid = get_amp_nid(kcontrol);
4969 long *valp = ucontrol->value.integer.value;
4970 int idx;
4971
4972 idx = nid - EFFECT_START_NID;
4973 /* any change? */
4974 if (spec->fx_ctl_val[idx] == *valp)
4975 return 0;
4976
4977 spec->fx_ctl_val[idx] = *valp;
4978
4979 idx = *valp;
4980 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4981
4982 return 0;
4983}
4984
4985
4986/*
4987 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4988 * only has off or full 30 dB, and didn't like making a volume slider that has
4989 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4990 */
4991#define MIC_BOOST_NUM_OF_STEPS 4
4992#define MIC_BOOST_ENUM_MAX_STRLEN 10
4993
4994static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4995 struct snd_ctl_elem_info *uinfo)
4996{
4997 char *sfx = "dB";
4998 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4999
5000 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5001 uinfo->count = 1;
5002 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5003 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5004 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5005 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5006 strcpy(uinfo->value.enumerated.name, namestr);
5007 return 0;
5008}
5009
5010static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5011 struct snd_ctl_elem_value *ucontrol)
5012{
5013 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5014 struct ca0132_spec *spec = codec->spec;
5015
5016 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5017 return 0;
5018}
5019
5020static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5021 struct snd_ctl_elem_value *ucontrol)
5022{
5023 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5024 struct ca0132_spec *spec = codec->spec;
5025 int sel = ucontrol->value.enumerated.item[0];
5026 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5027
5028 if (sel >= items)
5029 return 0;
5030
5031 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5032 sel);
5033
5034 spec->mic_boost_enum_val = sel;
5035
5036 if (spec->in_enum_val != REAR_LINE_IN)
5037 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5038
5039 return 1;
5040}
5041
95c6e9cb 5042
7cb9d94c
CM		 5043/*
5044 * Input Select Control for alternative ca0132 codecs. This exists because
5045 * front microphone has no auto-detect, and we need a way to set the rear
5046 * as line-in
5047 */
5048static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5049 struct snd_ctl_elem_info *uinfo)
5050{
5051 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5052 uinfo->count = 1;
5053 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5054 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5055 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5056 strcpy(uinfo->value.enumerated.name,
5057 in_src_str[uinfo->value.enumerated.item]);
5058 return 0;
5059}
5060
5061static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5062 struct snd_ctl_elem_value *ucontrol)
5063{
5064 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5065 struct ca0132_spec *spec = codec->spec;
5066
5067 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5068 return 0;
5069}
5070
5071static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5072 struct snd_ctl_elem_value *ucontrol)
5073{
5074 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5075 struct ca0132_spec *spec = codec->spec;
5076 int sel = ucontrol->value.enumerated.item[0];
5077 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5078
5079 if (sel >= items)
5080 return 0;
5081
5082 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5083 sel, in_src_str[sel]);
5084
5085 spec->in_enum_val = sel;
5086
5087 ca0132_alt_select_in(codec);
5088
5089 return 1;
5090}
5091
5092/* Sound Blaster Z Output Select Control */
5093static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5094 struct snd_ctl_elem_info *uinfo)
5095{
5096 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5097 uinfo->count = 1;
5098 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5099 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5100 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5101 strcpy(uinfo->value.enumerated.name,
5102 alt_out_presets[uinfo->value.enumerated.item].name);
5103 return 0;
5104}
5105
5106static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5107 struct snd_ctl_elem_value *ucontrol)
5108{
5109 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5110 struct ca0132_spec *spec = codec->spec;
5111
5112 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5113 return 0;
5114}
5115
5116static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5117 struct snd_ctl_elem_value *ucontrol)
5118{
5119 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5120 struct ca0132_spec *spec = codec->spec;
5121 int sel = ucontrol->value.enumerated.item[0];
5122 unsigned int items = NUM_OF_OUTPUTS;
5123 unsigned int auto_jack;
5124
5125 if (sel >= items)
5126 return 0;
5127
5128 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5129 sel, alt_out_presets[sel].name);
5130
5131 spec->out_enum_val = sel;
5132
5133 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5134
5135 if (!auto_jack)
5136 ca0132_alt_select_out(codec);
5137
5138 return 1;
5139}
5140
47cdf76e
CM		 5141/*
5142 * Smart Volume output setting control. Three different settings, Normal,
5143 * which takes the value from the smart volume slider. The two others, loud
5144 * and night, disregard the slider value and have uneditable values.
5145 */
5146#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5147static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5148
5149static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5150 struct snd_ctl_elem_info *uinfo)
5151{
5152 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5153 uinfo->count = 1;
5154 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5155 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5156 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5157 strcpy(uinfo->value.enumerated.name,
5158 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5159 return 0;
5160}
5161
5162static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5163 struct snd_ctl_elem_value *ucontrol)
5164{
5165 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5166 struct ca0132_spec *spec = codec->spec;
5167
5168 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5169 return 0;
5170}
5171
5172static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5173 struct snd_ctl_elem_value *ucontrol)
5174{
5175 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5176 struct ca0132_spec *spec = codec->spec;
5177 int sel = ucontrol->value.enumerated.item[0];
5178 unsigned int items = NUM_OF_SVM_SETTINGS;
5179 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5180 unsigned int tmp;
5181
5182 if (sel >= items)
5183 return 0;
5184
5185 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5186 sel, out_svm_set_enum_str[sel]);
5187
5188 spec->smart_volume_setting = sel;
5189
5190 switch (sel) {
5191 case 0:
5192 tmp = FLOAT_ZERO;
5193 break;
5194 case 1:
5195 tmp = FLOAT_ONE;
5196 break;
5197 case 2:
5198 tmp = FLOAT_TWO;
5199 break;
5200 default:
5201 tmp = FLOAT_ZERO;
5202 break;
5203 }
5204 /* Req 2 is the Smart Volume Setting req. */
5205 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5206 ca0132_effects[idx].reqs[2], tmp);
5207 return 1;
5208}
5209
5210/* Sound Blaster Z EQ preset controls */
5211static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5212 struct snd_ctl_elem_info *uinfo)
5213{
c5f13d75 5214 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5215
5216 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5217 uinfo->count = 1;
5218 uinfo->value.enumerated.items = items;
5219 if (uinfo->value.enumerated.item >= items)
5220 uinfo->value.enumerated.item = items - 1;
5221 strcpy(uinfo->value.enumerated.name,
5222 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5223 return 0;
5224}
5225
5226static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5227 struct snd_ctl_elem_value *ucontrol)
5228{
5229 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5230 struct ca0132_spec *spec = codec->spec;
5231
5232 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5233 return 0;
5234}
5235
5236static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5237 struct snd_ctl_elem_value *ucontrol)
5238{
5239 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5240 struct ca0132_spec *spec = codec->spec;
5241 int i, err = 0;
5242 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5243 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5244
5245 if (sel >= items)
5246 return 0;
5247
5248 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5249 ca0132_alt_eq_presets[sel].name);
5250 /*
5251 * Idx 0 is default.
5252 * Default needs to qualify with CrystalVoice state.
5253 */
5254 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5255 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5256 ca0132_alt_eq_enum.reqs[i],
5257 ca0132_alt_eq_presets[sel].vals[i]);
5258 if (err < 0)
5259 break;
5260 }
5261
5262 if (err >= 0)
5263 spec->eq_preset_val = sel;
5264
5265 return 1;
5266}
5267
a7e76271
IM		 5268static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5269 struct snd_ctl_elem_info *uinfo)
5270{
a9291f46 5271 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5272
5273 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5274 uinfo->count = 1;
5275 uinfo->value.enumerated.items = items;
5276 if (uinfo->value.enumerated.item >= items)
5277 uinfo->value.enumerated.item = items - 1;
5278 strcpy(uinfo->value.enumerated.name,
5279 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5280 return 0;
5281}
95c6e9cb 5282
a7e76271 5283static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5284 struct snd_ctl_elem_value *ucontrol)
5285{
5286 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5287 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5288
a7e76271 5289 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5290 return 0;
5291}
5292
a7e76271 5293static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5294 struct snd_ctl_elem_value *ucontrol)
5295{
5296 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5297 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5298 int i, err = 0;
5299 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5300
a9291f46 5301 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5302 return 0;
5303
4e76a883 5304 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5305 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5306
a7e76271
IM		 5307 /*
5308 * Idx 0 is default.
5309 * Default needs to qualify with CrystalVoice state.
5310 */
5311 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5312 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5313 ca0132_voicefx.reqs[i],
5314 ca0132_voicefx_presets[sel].vals[i]);
5315 if (err < 0)
5316 break;
5317 }
95c6e9cb 5318
a7e76271
IM		 5319 if (err >= 0) {
5320 spec->voicefx_val = sel;
5321 /* enable voice fx */
5322 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5323 }
95c6e9cb 5324
a7e76271 5325 return 1;
95c6e9cb
IM		 5326}
5327
a7e76271
IM		 5328static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5329 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5330{
5331 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5332 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5333 hda_nid_t nid = get_amp_nid(kcontrol);
5334 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5335 long *valp = ucontrol->value.integer.value;
5336
a7e76271
IM		 5337 /* vnode */
5338 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5339 if (ch & 1) {
5340 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5341 valp++;
5342 }
5343 if (ch & 2) {
5344 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5345 valp++;
5346 }
5347 return 0;
5348 }
5349
5350 /* effects, include PE and CrystalVoice */
5351 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5352 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5353 return 0;
5354 }
5355
5356 /* mic boost */
5357 if (nid == spec->input_pins[0]) {
5358 *valp = spec->cur_mic_boost;
5359 return 0;
5360 }
5361
95c6e9cb
IM		 5362 return 0;
5363}
5364
a7e76271
IM		 5365static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5366 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5367{
5368 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5369 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5370 hda_nid_t nid = get_amp_nid(kcontrol);
5371 int ch = get_amp_channels(kcontrol);
95c6e9cb 5372 long *valp = ucontrol->value.integer.value;
a7e76271 5373 int changed = 1;
95c6e9cb 5374
4e76a883 5375 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5376 nid, *valp);
95c6e9cb
IM		 5377
5378 snd_hda_power_up(codec);
a7e76271
IM		 5379 /* vnode */
5380 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5381 if (ch & 1) {
5382 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5383 valp++;
5384 }
5385 if (ch & 2) {
5386 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5387 valp++;
5388 }
5389 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5390 goto exit;
5391 }
95c6e9cb 5392
a7e76271
IM		 5393 /* PE */
5394 if (nid == PLAY_ENHANCEMENT) {
5395 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5396 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5397 goto exit;
a7e76271 5398 }
95c6e9cb 5399
a7e76271
IM		 5400 /* CrystalVoice */
5401 if (nid == CRYSTAL_VOICE) {
5402 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5403 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5404 goto exit;
a7e76271 5405 }
95c6e9cb 5406
a7e76271
IM		 5407 /* out and in effects */
5408 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5409 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5410 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5411 changed = ca0132_effects_set(codec, nid, *valp);
5412 goto exit;
5413 }
5414
5415 /* mic boost */
5416 if (nid == spec->input_pins[0]) {
5417 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 5418 if (spec->use_alt_functions) {
5419 if (spec->in_enum_val != REAR_LINE_IN)
5420 changed = ca0132_mic_boost_set(codec, *valp);
5421 } else {
5422 /* Mic boost does not apply to Digital Mic */
5423 if (spec->cur_mic_type != DIGITAL_MIC)
5424 changed = ca0132_mic_boost_set(codec, *valp);
5425 }
a7e76271 5426
a7e76271
IM		 5427 goto exit;
5428 }
95c6e9cb 5429
a7e76271 5430exit:
95c6e9cb 5431 snd_hda_power_down(codec);
a7e76271 5432 return changed;
95c6e9cb
IM		 5433}
5434
a7e76271
IM		 5435/*
5436 * Volume related
5437 */
017310fb
CM		 5438/*
5439 * Sets the internal DSP decibel level to match the DAC for output, and the
5440 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5441 * all alternative codecs set DSP playback volume.
5442 */
5443static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5444{
5445 struct ca0132_spec *spec = codec->spec;
5446 unsigned int dsp_dir;
5447 unsigned int lookup_val;
5448
5449 if (nid == VNID_SPK)
5450 dsp_dir = DSP_VOL_OUT;
5451 else
5452 dsp_dir = DSP_VOL_IN;
5453
5454 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5455
5456 dspio_set_uint_param(codec,
5457 ca0132_alt_vol_ctls[dsp_dir].mid,
5458 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5459 float_vol_db_lookup[lookup_val]);
5460
5461 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5462
5463 dspio_set_uint_param(codec,
5464 ca0132_alt_vol_ctls[dsp_dir].mid,
5465 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5466 float_vol_db_lookup[lookup_val]);
5467
5468 dspio_set_uint_param(codec,
5469 ca0132_alt_vol_ctls[dsp_dir].mid,
5470 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5471}
5472
a7e76271
IM		 5473static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5474 struct snd_ctl_elem_info *uinfo)
5475{
5476 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5477 struct ca0132_spec *spec = codec->spec;
5478 hda_nid_t nid = get_amp_nid(kcontrol);
5479 int ch = get_amp_channels(kcontrol);
5480 int dir = get_amp_direction(kcontrol);
5481 unsigned long pval;
5482 int err;
5483
5484 switch (nid) {
5485 case VNID_SPK:
5486 /* follow shared_out info */
5487 nid = spec->shared_out_nid;
5488 mutex_lock(&codec->control_mutex);
5489 pval = kcontrol->private_value;
5490 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5491 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5492 kcontrol->private_value = pval;
5493 mutex_unlock(&codec->control_mutex);
5494 break;
5495 case VNID_MIC:
5496 /* follow shared_mic info */
5497 nid = spec->shared_mic_nid;
5498 mutex_lock(&codec->control_mutex);
5499 pval = kcontrol->private_value;
5500 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5501 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5502 kcontrol->private_value = pval;
5503 mutex_unlock(&codec->control_mutex);
5504 break;
5505 default:
5506 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5507 }
5508 return err;
5509}
5510
5511static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5512 struct snd_ctl_elem_value *ucontrol)
5513{
5514 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5515 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5516 hda_nid_t nid = get_amp_nid(kcontrol);
5517 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5518 long *valp = ucontrol->value.integer.value;
5519
a7e76271
IM		 5520 /* store the left and right volume */
5521 if (ch & 1) {
5522 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5523 valp++;
5524 }
5525 if (ch & 2) {
5526 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5527 valp++;
5528 }
95c6e9cb
IM		 5529 return 0;
5530}
5531
a7e76271 5532static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5533 struct snd_ctl_elem_value *ucontrol)
5534{
5535 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5536 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5537 hda_nid_t nid = get_amp_nid(kcontrol);
5538 int ch = get_amp_channels(kcontrol);
95c6e9cb 5539 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5540 hda_nid_t shared_nid = 0;
5541 bool effective;
5542 int changed = 1;
5543
5544 /* store the left and right volume */
5545 if (ch & 1) {
5546 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5547 valp++;
5548 }
5549 if (ch & 2) {
5550 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5551 valp++;
5552 }
95c6e9cb 5553
a7e76271
IM		 5554 /* if effective conditions, then update hw immediately. */
5555 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5556 if (effective) {
5557 int dir = get_amp_direction(kcontrol);
5558 unsigned long pval;
5559
5560 snd_hda_power_up(codec);
5561 mutex_lock(&codec->control_mutex);
5562 pval = kcontrol->private_value;
5563 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5564 0, dir);
5565 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5566 kcontrol->private_value = pval;
5567 mutex_unlock(&codec->control_mutex);
5568 snd_hda_power_down(codec);
5569 }
95c6e9cb 5570
a7e76271 5571 return changed;
95c6e9cb
IM		 5572}
5573
017310fb
CM		 5574/*
5575 * This function is the same as the one above, because using an if statement
5576 * inside of the above volume control for the DSP volume would cause too much
5577 * lag. This is a lot more smooth.
5578 */
5579static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5580 struct snd_ctl_elem_value *ucontrol)
5581{
5582 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5583 struct ca0132_spec *spec = codec->spec;
5584 hda_nid_t nid = get_amp_nid(kcontrol);
5585 int ch = get_amp_channels(kcontrol);
5586 long *valp = ucontrol->value.integer.value;
5587 hda_nid_t vnid = 0;
5588 int changed = 1;
5589
5590 switch (nid) {
5591 case 0x02:
5592 vnid = VNID_SPK;
5593 break;
5594 case 0x07:
5595 vnid = VNID_MIC;
5596 break;
5597 }
5598
5599 /* store the left and right volume */
5600 if (ch & 1) {
5601 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5602 valp++;
5603 }
5604 if (ch & 2) {
5605 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5606 valp++;
5607 }
5608
5609 snd_hda_power_up(codec);
5610 ca0132_alt_dsp_volume_put(codec, vnid);
5611 mutex_lock(&codec->control_mutex);
5612 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5613 mutex_unlock(&codec->control_mutex);
5614 snd_hda_power_down(codec);
5615
5616 return changed;
5617}
5618
a7e76271
IM		 5619static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5620 unsigned int size, unsigned int __user *tlv)
95c6e9cb 5621{
a7e76271
IM		 5622 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5623 struct ca0132_spec *spec = codec->spec;
5624 hda_nid_t nid = get_amp_nid(kcontrol);
5625 int ch = get_amp_channels(kcontrol);
5626 int dir = get_amp_direction(kcontrol);
5627 unsigned long pval;
5628 int err;
5629
5630 switch (nid) {
5631 case VNID_SPK:
5632 /* follow shared_out tlv */
5633 nid = spec->shared_out_nid;
5634 mutex_lock(&codec->control_mutex);
5635 pval = kcontrol->private_value;
5636 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5637 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5638 kcontrol->private_value = pval;
5639 mutex_unlock(&codec->control_mutex);
5640 break;
5641 case VNID_MIC:
5642 /* follow shared_mic tlv */
5643 nid = spec->shared_mic_nid;
5644 mutex_lock(&codec->control_mutex);
5645 pval = kcontrol->private_value;
5646 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5647 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5648 kcontrol->private_value = pval;
5649 mutex_unlock(&codec->control_mutex);
5650 break;
5651 default:
5652 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5653 }
5654 return err;
95c6e9cb
IM		 5655}
5656
47cdf76e
CM		 5657/* Add volume slider control for effect level */
5658static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5659 const char *pfx, int dir)
5660{
47cdf76e
CM		 5661 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5662 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5663 struct snd_kcontrol_new knew =
5664 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5665
0cc1aa71 5666 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 5667
bb86124c 5668 knew.tlv.c = NULL;
47cdf76e
CM		 5669
5670 switch (nid) {
5671 case XBASS_XOVER:
5672 knew.info = ca0132_alt_xbass_xover_slider_info;
5673 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5674 knew.put = ca0132_alt_xbass_xover_slider_put;
5675 break;
5676 default:
5677 knew.info = ca0132_alt_effect_slider_info;
5678 knew.get = ca0132_alt_slider_ctl_get;
5679 knew.put = ca0132_alt_effect_slider_put;
5680 knew.private_value =
5681 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5682 break;
5683 }
5684
5685 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5686}
5687
5688/*
5689 * Added FX: prefix for the alternative codecs, because otherwise the surround
5690 * effect would conflict with the Surround sound volume control. Also seems more
5691 * clear as to what the switches do. Left alone for others.
5692 */
a7e76271
IM		 5693static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5694 const char *pfx, int dir)
95c6e9cb 5695{
47cdf76e 5696 struct ca0132_spec *spec = codec->spec;
975cc02a 5697 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 5698 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 5699 struct snd_kcontrol_new knew =
a7e76271 5700 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 5701 /* If using alt_controls, add FX: prefix. But, don't add FX:
5702 * prefix to OutFX or InFX enable controls.
5703 */
5704 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 5705 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 5706 else
5707 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5708
95c6e9cb
IM		 5709 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5710}
5711
a7e76271 5712static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 5713{
5714 struct snd_kcontrol_new knew =
a7e76271
IM		 5715 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5716 VOICEFX, 1, 0, HDA_INPUT);
5717 knew.info = ca0132_voicefx_info;
5718 knew.get = ca0132_voicefx_get;
5719 knew.put = ca0132_voicefx_put;
5720 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 5721}
5722
47cdf76e
CM		 5723/* Create the EQ Preset control */
5724static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5725{
5726 struct snd_kcontrol_new knew =
5727 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5728 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5729 knew.info = ca0132_alt_eq_preset_info;
5730 knew.get = ca0132_alt_eq_preset_get;
5731 knew.put = ca0132_alt_eq_preset_put;
5732 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5733 snd_ctl_new1(&knew, codec));
5734}
5735
5736/*
5737 * Add enumerated control for the three different settings of the smart volume
5738 * output effect. Normal just uses the slider value, and loud and night are
5739 * their own things that ignore that value.
5740 */
5741static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5742{
5743 struct snd_kcontrol_new knew =
5744 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5745 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5746 knew.info = ca0132_alt_svm_setting_info;
5747 knew.get = ca0132_alt_svm_setting_get;
5748 knew.put = ca0132_alt_svm_setting_put;
5749 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5750 snd_ctl_new1(&knew, codec));
5751
5752}
5753
7cb9d94c
CM		 5754/*
5755 * Create an Output Select enumerated control for codecs with surround
5756 * out capabilities.
5757 */
5758static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5759{
5760 struct snd_kcontrol_new knew =
5761 HDA_CODEC_MUTE_MONO("Output Select",
5762 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5763 knew.info = ca0132_alt_output_select_get_info;
5764 knew.get = ca0132_alt_output_select_get;
5765 knew.put = ca0132_alt_output_select_put;
5766 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5767 snd_ctl_new1(&knew, codec));
5768}
5769
5770/*
5771 * Create an Input Source enumerated control for the alternate ca0132 codecs
5772 * because the front microphone has no auto-detect, and Line-in has to be set
5773 * somehow.
5774 */
5775static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5776{
5777 struct snd_kcontrol_new knew =
5778 HDA_CODEC_MUTE_MONO("Input Source",
5779 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5780 knew.info = ca0132_alt_input_source_info;
5781 knew.get = ca0132_alt_input_source_get;
5782 knew.put = ca0132_alt_input_source_put;
5783 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5784 snd_ctl_new1(&knew, codec));
5785}
5786
47cdf76e
CM		 5787/*
5788 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5789 * more control than the original mic boost, which is either full 30dB or off.
5790 */
5791static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5792{
5793 struct snd_kcontrol_new knew =
5794 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5795 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5796 knew.info = ca0132_alt_mic_boost_info;
5797 knew.get = ca0132_alt_mic_boost_get;
5798 knew.put = ca0132_alt_mic_boost_put;
5799 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5800 snd_ctl_new1(&knew, codec));
5801
5802}
5803
5804/*
5805 * Need to create slave controls for the alternate codecs that have surround
5806 * capabilities.
5807 */
5808static const char * const ca0132_alt_slave_pfxs[] = {
5809 "Front", "Surround", "Center", "LFE", NULL,
5810};
5811
5812/*
5813 * Also need special channel map, because the default one is incorrect.
5814 * I think this has to do with the pin for rear surround being 0x11,
5815 * and the center/lfe being 0x10. Usually the pin order is the opposite.
5816 */
9c4a665e 5817static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 5818 { .channels = 2,
5819 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5820 { .channels = 4,
5821 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5822 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5823 { .channels = 6,
5824 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5825 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5826 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5827 { }
5828};
5829
5830/* Add the correct chmap for streams with 6 channels. */
5831static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5832{
5833 int err = 0;
5834 struct hda_pcm *pcm;
5835
5836 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5837 struct hda_pcm_stream *hinfo =
5838 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5839 struct snd_pcm_chmap *chmap;
5840 const struct snd_pcm_chmap_elem *elem;
5841
5842 elem = ca0132_alt_chmaps;
5843 if (hinfo->channels_max == 6) {
5844 err = snd_pcm_add_chmap_ctls(pcm->pcm,
5845 SNDRV_PCM_STREAM_PLAYBACK,
5846 elem, hinfo->channels_max, 0, &chmap);
5847 if (err < 0)
5848 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5849 }
5850 }
5851}
5852
a7e76271
IM		 5853/*
5854 * When changing Node IDs for Mixer Controls below, make sure to update
5855 * Node IDs in ca0132_config() as well.
5856 */
b0eaa072 5857static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 5858 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5859 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5860 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5861 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5862 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5863 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5864 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5865 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5866 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5867 0x12, 1, HDA_INPUT),
5868 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5869 VNID_HP_SEL, 1, HDA_OUTPUT),
5870 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5871 VNID_AMIC1_SEL, 1, HDA_INPUT),
5872 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5873 VNID_HP_ASEL, 1, HDA_OUTPUT),
5874 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5875 VNID_AMIC1_ASEL, 1, HDA_INPUT),
5876 { } /* end */
5877};
5878
017310fb 5879/*
e25e3445
CM		 5880 * Desktop specific control mixer. Removes auto-detect for mic, and adds
5881 * surround controls. Also sets both the Front Playback and Capture Volume
5882 * controls to alt so they set the DSP's decibel level.
017310fb 5883 */
e25e3445 5884static const struct snd_kcontrol_new desktop_mixer[] = {
017310fb
CM		 5885 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5886 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5887 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5888 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5889 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5890 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5891 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5892 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5893 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5894 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5895 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5896 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5897 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5898 VNID_HP_ASEL, 1, HDA_OUTPUT),
5899 { } /* end */
5900};
5901
5902/*
5903 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5904 * because it doesn't set decibel levels for the DSP for capture.
5905 */
b0eaa072 5906static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 5907 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5908 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5909 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5910 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5911 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5912 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5913 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5914 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5915 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5916 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5917 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5918 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5919 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5920 VNID_HP_ASEL, 1, HDA_OUTPUT),
5921 { } /* end */
5922};
5923
e90f29e4
IM		 5924static int ca0132_build_controls(struct hda_codec *codec)
5925{
5926 struct ca0132_spec *spec = codec->spec;
47cdf76e 5927 int i, num_fx, num_sliders;
e90f29e4
IM		 5928 int err = 0;
5929
5930 /* Add Mixer controls */
5931 for (i = 0; i < spec->num_mixers; i++) {
5932 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5933 if (err < 0)
5934 return err;
5935 }
47cdf76e
CM		 5936 /* Setup vmaster with surround slaves for desktop ca0132 devices */
5937 if (spec->use_alt_functions) {
5938 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5939 spec->tlv);
5940 snd_hda_add_vmaster(codec, "Master Playback Volume",
5941 spec->tlv, ca0132_alt_slave_pfxs,
5942 "Playback Volume");
5943 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5944 NULL, ca0132_alt_slave_pfxs,
5945 "Playback Switch",
5946 true, &spec->vmaster_mute.sw_kctl);
5947
5948 }
e90f29e4
IM		 5949
5950 /* Add in and out effects controls.
5951 * VoiceFX, PE and CrystalVoice are added separately.
5952 */
5953 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5954 for (i = 0; i < num_fx; i++) {
e25e3445
CM		 5955 /* SBZ and R3D break if Echo Cancellation is used. */
5956 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D) {
47cdf76e
CM		 5957 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5958 OUT_EFFECTS_COUNT))
5959 continue;
5960 }
5961
e90f29e4
IM		 5962 err = add_fx_switch(codec, ca0132_effects[i].nid,
5963 ca0132_effects[i].name,
5964 ca0132_effects[i].direct);
5965 if (err < 0)
5966 return err;
5967 }
47cdf76e
CM		 5968 /*
5969 * If codec has use_alt_controls set to true, add effect level sliders,
5970 * EQ presets, and Smart Volume presets. Also, change names to add FX
5971 * prefix, and change PlayEnhancement and CrystalVoice to match.
5972 */
5973 if (spec->use_alt_controls) {
5974 ca0132_alt_add_svm_enum(codec);
5975 add_ca0132_alt_eq_presets(codec);
5976 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5977 "Enable OutFX", 0);
5978 if (err < 0)
5979 return err;
e90f29e4 5980
47cdf76e
CM		 5981 err = add_fx_switch(codec, CRYSTAL_VOICE,
5982 "Enable InFX", 1);
5983 if (err < 0)
5984 return err;
e90f29e4 5985
47cdf76e
CM		 5986 num_sliders = OUT_EFFECTS_COUNT - 1;
5987 for (i = 0; i < num_sliders; i++) {
5988 err = ca0132_alt_add_effect_slider(codec,
5989 ca0132_effects[i].nid,
5990 ca0132_effects[i].name,
5991 ca0132_effects[i].direct);
5992 if (err < 0)
5993 return err;
5994 }
5995
5996 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5997 "X-Bass Crossover", EFX_DIR_OUT);
5998
5999 if (err < 0)
6000 return err;
6001 } else {
6002 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6003 "PlayEnhancement", 0);
6004 if (err < 0)
6005 return err;
e90f29e4 6006
47cdf76e
CM		 6007 err = add_fx_switch(codec, CRYSTAL_VOICE,
6008 "CrystalVoice", 1);
6009 if (err < 0)
6010 return err;
6011 }
e90f29e4
IM		 6012 add_voicefx(codec);
6013
7cb9d94c
CM		 6014 /*
6015 * If the codec uses alt_functions, you need the enumerated controls
6016 * to select the new outputs and inputs, plus add the new mic boost
6017 * setting control.
6018 */
6019 if (spec->use_alt_functions) {
6020 ca0132_alt_add_output_enum(codec);
6021 ca0132_alt_add_input_enum(codec);
47cdf76e 6022 ca0132_alt_add_mic_boost_enum(codec);
7cb9d94c 6023 }
e90f29e4
IM		 6024#ifdef ENABLE_TUNING_CONTROLS
6025 add_tuning_ctls(codec);
6026#endif
6027
6028 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6029 if (err < 0)
6030 return err;
6031
6032 if (spec->dig_out) {
6033 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6034 spec->dig_out);
6035 if (err < 0)
6036 return err;
6037 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6038 if (err < 0)
6039 return err;
6040 /* spec->multiout.share_spdif = 1; */
6041 }
6042
6043 if (spec->dig_in) {
6044 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6045 if (err < 0)
6046 return err;
6047 }
47cdf76e
CM		 6048
6049 if (spec->use_alt_functions)
6050 ca0132_alt_add_chmap_ctls(codec);
6051
e90f29e4
IM		 6052 return 0;
6053}
6054
a7e76271 6055/*
e90f29e4 6056 * PCM
a7e76271 6057 */
071f1344 6058static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 6059 .substreams = 1,
6060 .channels_min = 2,
825315bc 6061 .channels_max = 6,
a7e76271 6062 .ops = {
a7e76271 6063 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 6064 .cleanup = ca0132_playback_pcm_cleanup,
6065 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 6066 },
6067};
6068
071f1344 6069static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 6070 .substreams = 1,
6071 .channels_min = 2,
6072 .channels_max = 2,
825315bc
IM		 6073 .ops = {
6074 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 6075 .cleanup = ca0132_capture_pcm_cleanup,
6076 .get_delay = ca0132_capture_pcm_delay,
825315bc 6077 },
a7e76271
IM		 6078};
6079
071f1344 6080static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 6081 .substreams = 1,
6082 .channels_min = 2,
6083 .channels_max = 2,
6084 .ops = {
6085 .open = ca0132_dig_playback_pcm_open,
6086 .close = ca0132_dig_playback_pcm_close,
6087 .prepare = ca0132_dig_playback_pcm_prepare,
6088 .cleanup = ca0132_dig_playback_pcm_cleanup
6089 },
6090};
6091
071f1344 6092static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 6093 .substreams = 1,
6094 .channels_min = 2,
6095 .channels_max = 2,
6096};
6097
6098static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 6099{
6100 struct ca0132_spec *spec = codec->spec;
bbbc7e85 6101 struct hda_pcm *info;
a7e76271 6102
bbbc7e85
TI		 6103 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6104 if (!info)
6105 return -ENOMEM;
47cdf76e
CM		 6106 if (spec->use_alt_functions) {
6107 info->own_chmap = true;
6108 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6109 = ca0132_alt_chmaps;
6110 }
a7e76271
IM		 6111 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6112 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6113 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6114 spec->multiout.max_channels;
6115 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 6116 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 6117 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 6118
009b8f97 6119 /* With the DSP enabled, desktops don't use this ADC. */
5f8ddc6e 6120 if (!spec->use_alt_functions) {
009b8f97
CM		 6121 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6122 if (!info)
6123 return -ENOMEM;
6124 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6125 ca0132_pcm_analog_capture;
6126 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6127 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6128 }
825315bc 6129
bbbc7e85
TI		 6130 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6131 if (!info)
6132 return -ENOMEM;
825315bc
IM		 6133 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6134 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6135 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6136
a7e76271
IM		 6137 if (!spec->dig_out && !spec->dig_in)
6138 return 0;
6139
bbbc7e85
TI		 6140 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6141 if (!info)
6142 return -ENOMEM;
a7e76271
IM		 6143 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6144 if (spec->dig_out) {
6145 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6146 ca0132_pcm_digital_playback;
6147 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6148 }
6149 if (spec->dig_in) {
6150 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6151 ca0132_pcm_digital_capture;
6152 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6153 }
95c6e9cb 6154
a7e76271 6155 return 0;
95c6e9cb
IM		 6156}
6157
441aa6a0
IM		 6158static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6159{
6160 if (pin) {
a0c041cb 6161 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6162 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6163 snd_hda_codec_write(codec, pin, 0,
6164 AC_VERB_SET_AMP_GAIN_MUTE,
6165 AMP_OUT_UNMUTE);
6166 }
6167 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6168 snd_hda_codec_write(codec, dac, 0,
6169 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6170}
6171
6172static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6173{
6174 if (pin) {
a0c041cb 6175 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6176 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6177 snd_hda_codec_write(codec, pin, 0,
6178 AC_VERB_SET_AMP_GAIN_MUTE,
6179 AMP_IN_UNMUTE(0));
6180 }
6181 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6182 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6183 AMP_IN_UNMUTE(0));
6184
6185 /* init to 0 dB and unmute. */
6186 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6187 HDA_AMP_VOLMASK, 0x5a);
6188 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6189 HDA_AMP_MUTE, 0);
6190 }
6191}
6192
5aaca44d
IM		 6193static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6194{
6195 unsigned int caps;
6196
6197 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6198 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6199 snd_hda_override_amp_caps(codec, nid, dir, caps);
6200}
6201
6202/*
6203 * Switch between Digital built-in mic and analog mic.
6204 */
6205static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6206{
6207 struct ca0132_spec *spec = codec->spec;
6208 unsigned int tmp;
6209 u8 val;
6210 unsigned int oldval;
6211
4e76a883 6212 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6213
6214 oldval = stop_mic1(codec);
6215 ca0132_set_vipsource(codec, 0);
6216 if (enable) {
6217 /* set DMic input as 2-ch */
6218 tmp = FLOAT_TWO;
6219 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6220
6221 val = spec->dmic_ctl;
6222 val |= 0x80;
6223 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6224 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6225
6226 if (!(spec->dmic_ctl & 0x20))
6227 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6228 } else {
6229 /* set AMic input as mono */
6230 tmp = FLOAT_ONE;
6231 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6232
6233 val = spec->dmic_ctl;
6234 /* clear bit7 and bit5 to disable dmic */
6235 val &= 0x5f;
6236 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6237 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6238
6239 if (!(spec->dmic_ctl & 0x20))
6240 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6241 }
6242 ca0132_set_vipsource(codec, 1);
6243 resume_mic1(codec, oldval);
6244}
6245
6246/*
6247 * Initialization for Digital Mic.
6248 */
6249static void ca0132_init_dmic(struct hda_codec *codec)
6250{
6251 struct ca0132_spec *spec = codec->spec;
6252 u8 val;
6253
6254 /* Setup Digital Mic here, but don't enable.
6255 * Enable based on jack detect.
6256 */
6257
6258 /* MCLK uses MPIO1, set to enable.
6259 * Bit 2-0: MPIO select
6260 * Bit 3: set to disable
6261 * Bit 7-4: reserved
6262 */
6263 val = 0x01;
6264 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6265 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6266
6267 /* Data1 uses MPIO3. Data2 not use
6268 * Bit 2-0: Data1 MPIO select
6269 * Bit 3: set disable Data1
6270 * Bit 6-4: Data2 MPIO select
6271 * Bit 7: set disable Data2
6272 */
6273 val = 0x83;
6274 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6275 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6276
6277 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6278 * Bit 3-0: Channel mask
6279 * Bit 4: set for 48KHz, clear for 32KHz
6280 * Bit 5: mode
6281 * Bit 6: set to select Data2, clear for Data1
6282 * Bit 7: set to enable DMic, clear for AMic
6283 */
a57a46b9
AB		 6284 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6285 val = 0x33;
6286 else
6287 val = 0x23;
5aaca44d
IM		 6288 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6289 spec->dmic_ctl = val;
6290 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6291 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6292}
6293
6294/*
6295 * Initialization for Analog Mic 2
6296 */
6297static void ca0132_init_analog_mic2(struct hda_codec *codec)
6298{
6299 struct ca0132_spec *spec = codec->spec;
6300
6301 mutex_lock(&spec->chipio_mutex);
6302 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6303 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6304 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6305 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6306 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6307 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6308 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6309 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6310 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6311 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6312 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6313 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6314 mutex_unlock(&spec->chipio_mutex);
6315}
6316
6317static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6318{
6319 struct ca0132_spec *spec = codec->spec;
6320 int i;
5aaca44d 6321
4e76a883 6322 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6323 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6324
6325 for (i = 0; i < spec->multiout.num_dacs; i++)
6326 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6327
6328 for (i = 0; i < spec->num_outputs; i++)
6329 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6330
6331 for (i = 0; i < spec->num_inputs; i++) {
6332 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6333 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6334 }
6335}
6336
7e6ed62e 6337/*
6ef0e91e
CM		 6338 * Creates a dummy stream to bind the output to. This seems to have to be done
6339 * after changing the main outputs source and destination streams.
7e6ed62e 6340 */
6ef0e91e 6341static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
447fd8e9 6342{
6ef0e91e
CM		 6343 struct ca0132_spec *spec = codec->spec;
6344 unsigned int stream_format;
447fd8e9 6345
6ef0e91e
CM		 6346 stream_format = snd_hdac_calc_stream_format(48000, 2,
6347 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7e6ed62e 6348
6ef0e91e
CM		 6349 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6350 0, stream_format);
7e6ed62e 6351
6ef0e91e 6352 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7e6ed62e
CM		 6353}
6354
38ba69ff 6355/*
6ef0e91e 6356 * Initialize mic for non-chromebook ca0132 implementations.
38ba69ff 6357 */
6ef0e91e 6358static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
38ba69ff 6359{
6ef0e91e 6360 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6361 unsigned int tmp;
6362
6363 /* Mic 1 Setup */
6364 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6365 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6ef0e91e
CM		 6366 if (spec->quirk == QUIRK_R3DI) {
6367 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6368 tmp = FLOAT_ONE;
6369 } else
6370 tmp = FLOAT_THREE;
38ba69ff
CM		 6371 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6372
6ef0e91e 6373 /* Mic 2 setup (not present on desktop cards) */
38ba69ff
CM		 6374 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6375 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6ef0e91e
CM		 6376 if (spec->quirk == QUIRK_R3DI)
6377 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
38ba69ff
CM		 6378 tmp = FLOAT_ZERO;
6379 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
38ba69ff
CM		 6380}
6381
6382/*
6383 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6384 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6385 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6386 * having an updated DAC, which changes the destination to that DAC.
6387 */
6388static void sbz_connect_streams(struct hda_codec *codec)
6389{
6390 struct ca0132_spec *spec = codec->spec;
6391
6392 mutex_lock(&spec->chipio_mutex);
6393
6394 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6395
6396 chipio_set_stream_channels(codec, 0x0C, 6);
6397 chipio_set_stream_control(codec, 0x0C, 1);
6398
6399 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6400 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6401
6402 /* Setup stream 0x14 with it's source and destination points */
6403 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6404 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6405 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6406 chipio_set_stream_channels(codec, 0x14, 2);
6407 chipio_set_stream_control(codec, 0x14, 1);
6408
6409 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6410
6411 mutex_unlock(&spec->chipio_mutex);
38ba69ff
CM		 6412}
6413
6414/*
6415 * Write data through ChipIO to setup proper stream destinations.
6416 * Not sure how it exactly works, but it seems to direct data
6417 * to different destinations. Example is f8 to c0, e0 to c0.
6418 * All I know is, if you don't set these, you get no sound.
6419 */
6420static void sbz_chipio_startup_data(struct hda_codec *codec)
6421{
6422 struct ca0132_spec *spec = codec->spec;
6423
6424 mutex_lock(&spec->chipio_mutex);
6425 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6426
6427 /* These control audio output */
6428 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6429 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6430 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6431 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6432 /* Signal to update I think */
6433 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6434
6435 chipio_set_stream_channels(codec, 0x0C, 6);
6436 chipio_set_stream_control(codec, 0x0C, 1);
6437 /* No clue what these control */
6438 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6439 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6440 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6441 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6442 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6443 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6444 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6445 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6446 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6447 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6448 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6449 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6450
6451 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6452
6453 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6454 mutex_unlock(&spec->chipio_mutex);
6455}
6456
447fd8e9 6457/*
6ef0e91e
CM		 6458 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
6459 * done after the DSP is loaded.
447fd8e9 6460 */
6ef0e91e 6461static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
447fd8e9 6462{
6ef0e91e 6463 struct ca0132_spec *spec = codec->spec;
447fd8e9
CM		 6464 unsigned int tmp;
6465
6ef0e91e
CM		 6466 switch (spec->quirk) {
6467 case QUIRK_SBZ:
6468 case QUIRK_AE5:
6469 tmp = 0x00000003;
6470 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6471 tmp = 0x00000000;
6472 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6473 tmp = 0x00000001;
6474 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6475 tmp = 0x00000004;
6476 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6477 tmp = 0x00000005;
6478 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6479 tmp = 0x00000000;
6480 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6481 break;
6482 case QUIRK_R3D:
6483 case QUIRK_R3DI:
6484 tmp = 0x00000000;
6485 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6486 tmp = 0x00000001;
6487 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6488 tmp = 0x00000004;
6489 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6490 tmp = 0x00000005;
6491 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6492 tmp = 0x00000000;
6493 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6494 break;
6495 }
447fd8e9
CM		 6496}
6497
6ef0e91e 6498static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
38ba69ff 6499{
6ef0e91e 6500 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6501 unsigned int tmp;
6502
6503 chipio_set_stream_control(codec, 0x03, 0);
6504 chipio_set_stream_control(codec, 0x04, 0);
6505
6506 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6507 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6508
6509 tmp = FLOAT_THREE;
6510 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6511
6512 chipio_set_stream_control(codec, 0x03, 1);
6513 chipio_set_stream_control(codec, 0x04, 1);
6514
6ef0e91e
CM		 6515 switch (spec->quirk) {
6516 case QUIRK_SBZ:
6517 chipio_write(codec, 0x18b098, 0x0000000c);
6518 chipio_write(codec, 0x18b09C, 0x0000000c);
6519 break;
6520 case QUIRK_AE5:
6521 chipio_write(codec, 0x18b098, 0x0000000c);
6522 chipio_write(codec, 0x18b09c, 0x0000004c);
6523 break;
6524 }
38ba69ff
CM		 6525}
6526
5aaca44d
IM		 6527/*
6528 * Setup default parameters for DSP
6529 */
6530static void ca0132_setup_defaults(struct hda_codec *codec)
6531{
e8f1bd5d 6532 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 6533 unsigned int tmp;
6534 int num_fx;
6535 int idx, i;
6536
e8f1bd5d 6537 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 6538 return;
6539
6540 /* out, in effects + voicefx */
6541 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6542 for (idx = 0; idx < num_fx; idx++) {
6543 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6544 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6545 ca0132_effects[idx].reqs[i],
6546 ca0132_effects[idx].def_vals[i]);
6547 }
6548 }
6549
6550 /*remove DSP headroom*/
6551 tmp = FLOAT_ZERO;
6552 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6553
6554 /*set speaker EQ bypass attenuation*/
6555 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6556
6557 /* set AMic1 and AMic2 as mono mic */
6558 tmp = FLOAT_ONE;
6559 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6560 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6561
6562 /* set AMic1 as CrystalVoice input */
6563 tmp = FLOAT_ONE;
6564 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6565
6566 /* set WUH source */
6567 tmp = FLOAT_TWO;
6568 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6569}
6570
7e6ed62e 6571/*
c986f50c 6572 * Setup default parameters for Recon3D/Recon3Di DSP.
7e6ed62e
CM		 6573 */
6574
c986f50c 6575static void r3d_setup_defaults(struct hda_codec *codec)
7e6ed62e
CM		 6576{
6577 struct ca0132_spec *spec = codec->spec;
6578 unsigned int tmp;
6579 int num_fx;
6580 int idx, i;
6581
6582 if (spec->dsp_state != DSP_DOWNLOADED)
6583 return;
6584
6ef0e91e
CM		 6585 ca0132_alt_dsp_scp_startup(codec);
6586 ca0132_alt_init_analog_mics(codec);
7e6ed62e
CM		 6587
6588 /*remove DSP headroom*/
6589 tmp = FLOAT_ZERO;
6590 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6591
6592 /* set WUH source */
6593 tmp = FLOAT_TWO;
6594 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6595 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6596
6597 /* Set speaker source? */
6598 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6599
c986f50c
CM		 6600 if (spec->quirk == QUIRK_R3DI)
6601 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7e6ed62e
CM		 6602
6603 /* Setup effect defaults */
6604 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6605 for (idx = 0; idx < num_fx; idx++) {
6606 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6607 dspio_set_uint_param(codec,
6608 ca0132_effects[idx].mid,
6609 ca0132_effects[idx].reqs[i],
6610 ca0132_effects[idx].def_vals[i]);
6611 }
6612 }
7e6ed62e
CM		 6613}
6614
38ba69ff
CM		 6615/*
6616 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6617 * than the Chromebook setup.
6618 */
6619static void sbz_setup_defaults(struct hda_codec *codec)
6620{
6621 struct ca0132_spec *spec = codec->spec;
6ef0e91e 6622 unsigned int tmp;
38ba69ff
CM		 6623 int num_fx;
6624 int idx, i;
6625
6626 if (spec->dsp_state != DSP_DOWNLOADED)
6627 return;
6628
6ef0e91e
CM		 6629 ca0132_alt_dsp_scp_startup(codec);
6630 ca0132_alt_init_analog_mics(codec);
38ba69ff 6631 sbz_connect_streams(codec);
38ba69ff
CM		 6632 sbz_chipio_startup_data(codec);
6633
6634 chipio_set_stream_control(codec, 0x03, 1);
6635 chipio_set_stream_control(codec, 0x04, 1);
6636
6637 /*
6638 * Sets internal input loopback to off, used to have a switch to
6639 * enable input loopback, but turned out to be way too buggy.
6640 */
6641 tmp = FLOAT_ONE;
6642 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6643 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6644
6645 /*remove DSP headroom*/
6646 tmp = FLOAT_ZERO;
6647 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6648
6649 /* set WUH source */
6650 tmp = FLOAT_TWO;
6651 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6652 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6653
6654 /* Set speaker source? */
6655 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6656
6ef0e91e 6657 ca0132_alt_dsp_initial_mic_setup(codec);
38ba69ff
CM		 6658
6659 /* out, in effects + voicefx */
6660 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6661 for (idx = 0; idx < num_fx; idx++) {
6662 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6663 dspio_set_uint_param(codec,
6664 ca0132_effects[idx].mid,
6665 ca0132_effects[idx].reqs[i],
6666 ca0132_effects[idx].def_vals[i]);
6667 }
6668 }
6669
6ef0e91e 6670 ca0132_alt_create_dummy_stream(codec);
38ba69ff
CM		 6671}
6672
5aaca44d
IM		 6673/*
6674 * Initialization of flags in chip
6675 */
6676static void ca0132_init_flags(struct hda_codec *codec)
6677{
009b8f97
CM		 6678 struct ca0132_spec *spec = codec->spec;
6679
6680 if (spec->use_alt_functions) {
6681 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6682 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6683 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6684 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6685 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6686 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6687 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6688 chipio_set_control_flag(codec,
6689 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6690 chipio_set_control_flag(codec,
6691 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6692 } else {
6693 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6694 chipio_set_control_flag(codec,
6695 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6696 chipio_set_control_flag(codec,
6697 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6698 chipio_set_control_flag(codec,
6699 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6700 chipio_set_control_flag(codec,
6701 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6702 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6703 }
5aaca44d
IM		 6704}
6705
6706/*
6707 * Initialization of parameters in chip
6708 */
6709static void ca0132_init_params(struct hda_codec *codec)
6710{
009b8f97
CM		 6711 struct ca0132_spec *spec = codec->spec;
6712
6713 if (spec->use_alt_functions) {
6714 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6715 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6716 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6717 chipio_set_control_param(codec, 0, 0);
6718 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6719 }
6720
5aaca44d
IM		 6721 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6722 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6723}
95c6e9cb 6724
e90f29e4
IM		 6725static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6726{
6727 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6728 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6729 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6730 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6731 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6732 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6733
406261ce
IM		 6734 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6735 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 6736 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6737}
6738
6739static bool ca0132_download_dsp_images(struct hda_codec *codec)
6740{
6741 bool dsp_loaded = false;
8a19bcee 6742 struct ca0132_spec *spec = codec->spec;
e90f29e4 6743 const struct dsp_image_seg *dsp_os_image;
15e4ba66 6744 const struct firmware *fw_entry;
8a19bcee
CM		 6745 /*
6746 * Alternate firmwares for different variants. The Recon3Di apparently
6747 * can use the default firmware, but I'll leave the option in case
6748 * it needs it again.
6749 */
6750 switch (spec->quirk) {
6751 case QUIRK_SBZ:
7a928186
CM		 6752 case QUIRK_R3D:
6753 case QUIRK_AE5:
6754 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8a19bcee 6755 codec->card->dev) != 0) {
6ef0e91e 6756 codec_dbg(codec, "Desktop firmware not found.");
8a19bcee
CM		 6757 spec->alt_firmware_present = false;
6758 } else {
7a928186 6759 codec_dbg(codec, "Desktop firmware selected.");
8a19bcee
CM		 6760 spec->alt_firmware_present = true;
6761 }
6762 break;
6763 case QUIRK_R3DI:
6764 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6765 codec->card->dev) != 0) {
6766 codec_dbg(codec, "Recon3Di alt firmware not detected.");
6767 spec->alt_firmware_present = false;
6768 } else {
6769 codec_dbg(codec, "Recon3Di firmware selected.");
6770 spec->alt_firmware_present = true;
6771 }
6772 break;
6773 default:
6774 spec->alt_firmware_present = false;
6775 break;
6776 }
6777 /*
6778 * Use default ctefx.bin if no alt firmware is detected, or if none
6779 * exists for your particular codec.
6780 */
6781 if (!spec->alt_firmware_present) {
6782 codec_dbg(codec, "Default firmware selected.");
6783 if (request_firmware(&fw_entry, EFX_FILE,
6784 codec->card->dev) != 0)
6785 return false;
6786 }
e90f29e4 6787
15e4ba66 6788 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 6789 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 6790 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 6791 goto exit_download;
6792 }
6793
e90f29e4
IM		 6794 dsp_loaded = dspload_wait_loaded(codec);
6795
d1d28500 6796exit_download:
15e4ba66
TI		 6797 release_firmware(fw_entry);
6798
e90f29e4
IM		 6799 return dsp_loaded;
6800}
6801
6802static void ca0132_download_dsp(struct hda_codec *codec)
6803{
6804 struct ca0132_spec *spec = codec->spec;
6805
9a0869f4
TI		 6806#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6807 return; /* NOP */
6808#endif
e90f29e4 6809
e24aa0a4
TI		 6810 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6811 return; /* don't retry failures */
6812
b714a710 6813 chipio_enable_clocks(codec);
e93ac30a
CM		 6814 if (spec->dsp_state != DSP_DOWNLOADED) {
6815 spec->dsp_state = DSP_DOWNLOADING;
6816
6817 if (!ca0132_download_dsp_images(codec))
6818 spec->dsp_state = DSP_DOWNLOAD_FAILED;
6819 else
6820 spec->dsp_state = DSP_DOWNLOADED;
6821 }
e90f29e4 6822
009b8f97
CM		 6823 /* For codecs using alt functions, this is already done earlier */
6824 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 6825 ca0132_set_dsp_msr(codec, true);
6826}
6827
f8fb1170
TI		 6828static void ca0132_process_dsp_response(struct hda_codec *codec,
6829 struct hda_jack_callback *callback)
e90f29e4
IM		 6830{
6831 struct ca0132_spec *spec = codec->spec;
6832
4e76a883 6833 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 6834 if (spec->wait_scp) {
6835 if (dspio_get_response_data(codec) >= 0)
6836 spec->wait_scp = 0;
6837 }
6838
6839 dspio_clear_response_queue(codec);
6840}
6841
f8fb1170 6842static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 6843{
993884f6 6844 struct ca0132_spec *spec = codec->spec;
2ebab40e 6845 struct hda_jack_tbl *tbl;
e90f29e4 6846
f8fb1170
TI		 6847 /* Delay enabling the HP amp, to let the mic-detection
6848 * state machine run.
6849 */
6850 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 6851 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 6852 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6853 if (tbl)
6854 tbl->block_report = 1;
f8fb1170
TI		 6855}
6856
6857static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6858{
a1b7f016
CM		 6859 struct ca0132_spec *spec = codec->spec;
6860
6861 if (spec->use_alt_functions)
6862 ca0132_alt_select_in(codec);
6863 else
6864 ca0132_select_mic(codec);
f8fb1170
TI		 6865}
6866
6867static void ca0132_init_unsol(struct hda_codec *codec)
6868{
d5c016b5
GM		 6869 struct ca0132_spec *spec = codec->spec;
6870 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6871 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 6872 amic_callback);
6873 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6874 ca0132_process_dsp_response);
63177afc 6875 /* Front headphone jack detection */
009b8f97 6876 if (spec->use_alt_functions)
63177afc
CM		 6877 snd_hda_jack_detect_enable_callback(codec,
6878 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 6879}
6880
5aaca44d
IM		 6881/*
6882 * Verbs tables.
6883 */
6884
6885/* Sends before DSP download. */
6886static struct hda_verb ca0132_base_init_verbs[] = {
6887 /*enable ct extension*/
6888 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 6889 {}
6890};
6891
6892/* Send at exit. */
6893static struct hda_verb ca0132_base_exit_verbs[] = {
6894 /*set afg to D3*/
6895 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
6896 /*disable ct extension*/
6897 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6898 {}
6899};
6900
8a19bcee 6901/* Other verbs tables. Sends after DSP download. */
e93ac30a 6902
5aaca44d
IM		 6903static struct hda_verb ca0132_init_verbs0[] = {
6904 /* chip init verbs */
6905 {0x15, 0x70D, 0xF0},
6906 {0x15, 0x70E, 0xFE},
6907 {0x15, 0x707, 0x75},
6908 {0x15, 0x707, 0xD3},
6909 {0x15, 0x707, 0x09},
6910 {0x15, 0x707, 0x53},
6911 {0x15, 0x707, 0xD4},
6912 {0x15, 0x707, 0xEF},
6913 {0x15, 0x707, 0x75},
6914 {0x15, 0x707, 0xD3},
6915 {0x15, 0x707, 0x09},
6916 {0x15, 0x707, 0x02},
6917 {0x15, 0x707, 0x37},
6918 {0x15, 0x707, 0x78},
6919 {0x15, 0x53C, 0xCE},
6920 {0x15, 0x575, 0xC9},
6921 {0x15, 0x53D, 0xCE},
6922 {0x15, 0x5B7, 0xC9},
6923 {0x15, 0x70D, 0xE8},
6924 {0x15, 0x70E, 0xFE},
6925 {0x15, 0x707, 0x02},
6926 {0x15, 0x707, 0x68},
6927 {0x15, 0x707, 0x62},
6928 {0x15, 0x53A, 0xCE},
6929 {0x15, 0x546, 0xC9},
6930 {0x15, 0x53B, 0xCE},
6931 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 6932 {}
6933};
6934
e42c7c73
CM		 6935/* Extra init verbs for desktop cards. */
6936static struct hda_verb ca0132_init_verbs1[] = {
e93ac30a
CM		 6937 {0x15, 0x70D, 0x20},
6938 {0x15, 0x70E, 0x19},
6939 {0x15, 0x707, 0x00},
6940 {0x15, 0x539, 0xCE},
6941 {0x15, 0x546, 0xC9},
6942 {0x15, 0x70D, 0xB7},
6943 {0x15, 0x70E, 0x09},
6944 {0x15, 0x707, 0x10},
6945 {0x15, 0x70D, 0xAF},
6946 {0x15, 0x70E, 0x09},
6947 {0x15, 0x707, 0x01},
6948 {0x15, 0x707, 0x05},
6949 {0x15, 0x70D, 0x73},
6950 {0x15, 0x70E, 0x09},
6951 {0x15, 0x707, 0x14},
6952 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 6953 {}
6954};
6955
95c6e9cb
IM		 6956static void ca0132_init_chip(struct hda_codec *codec)
6957{
6958 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 6959 int num_fx;
6960 int i;
6961 unsigned int on;
95c6e9cb
IM		 6962
6963 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 6964
6965 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 6966 if (!spec->use_alt_functions)
6967 spec->cur_mic_type = DIGITAL_MIC;
6968 else
6969 spec->cur_mic_type = REAR_MIC;
6970
5aaca44d
IM		 6971 spec->cur_mic_boost = 0;
6972
6973 for (i = 0; i < VNODES_COUNT; i++) {
6974 spec->vnode_lvol[i] = 0x5a;
6975 spec->vnode_rvol[i] = 0x5a;
6976 spec->vnode_lswitch[i] = 0;
6977 spec->vnode_rswitch[i] = 0;
6978 }
6979
6980 /*
6981 * Default states for effects are in ca0132_effects[].
6982 */
6983 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6984 for (i = 0; i < num_fx; i++) {
6985 on = (unsigned int)ca0132_effects[i].reqs[0];
6986 spec->effects_switch[i] = on ? 1 : 0;
6987 }
47cdf76e
CM		 6988 /*
6989 * Sets defaults for the effect slider controls, only for alternative
6990 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6991 */
6992 if (spec->use_alt_controls) {
6993 spec->xbass_xover_freq = 8;
6994 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6995 spec->fx_ctl_val[i] = effect_slider_defaults[i];
6996 }
5aaca44d
IM		 6997
6998 spec->voicefx_val = 0;
6999 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7000 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7001
44f0c978
IM		 7002#ifdef ENABLE_TUNING_CONTROLS
7003 ca0132_init_tuning_defaults(codec);
7004#endif
95c6e9cb
IM		 7005}
7006
2e48b2b7
CM		 7007/*
7008 * Recon3Di exit specific commands.
7009 */
7010/* prevents popping noise on shutdown */
7011static void r3di_gpio_shutdown(struct hda_codec *codec)
7012{
7013 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7014}
7015
7016/*
7017 * Sound Blaster Z exit specific commands.
7018 */
7019static void sbz_region2_exit(struct hda_codec *codec)
7020{
7021 struct ca0132_spec *spec = codec->spec;
7022 unsigned int i;
7023
7024 for (i = 0; i < 4; i++)
7025 writeb(0x0, spec->mem_base + 0x100);
7026 for (i = 0; i < 8; i++)
7027 writeb(0xb3, spec->mem_base + 0x304);
a62e4739 7028
b9b41345
CM		 7029 ca0113_mmio_gpio_set(codec, 0, false);
7030 ca0113_mmio_gpio_set(codec, 1, false);
7031 ca0113_mmio_gpio_set(codec, 4, true);
7032 ca0113_mmio_gpio_set(codec, 5, false);
7033 ca0113_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 7034}
7035
7036static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7037{
7038 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7039 unsigned int i;
7040
7041 snd_hda_codec_write(codec, 0x11, 0,
7042 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7043
7044 for (i = 0; i < 5; i++)
7045 snd_hda_codec_write(codec, pins[i], 0,
7046 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7047}
7048
2f295f91 7049static void ca0132_clear_unsolicited(struct hda_codec *codec)
2e48b2b7
CM		 7050{
7051 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7052 unsigned int i;
7053
7054 for (i = 0; i < 7; i++) {
7055 snd_hda_codec_write(codec, pins[i], 0,
7056 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7057 }
7058}
7059
7060/* On shutdown, sends commands in sets of three */
7061static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7062 int mask, int data)
7063{
7064 if (dir >= 0)
7065 snd_hda_codec_write(codec, 0x01, 0,
7066 AC_VERB_SET_GPIO_DIRECTION, dir);
7067 if (mask >= 0)
7068 snd_hda_codec_write(codec, 0x01, 0,
7069 AC_VERB_SET_GPIO_MASK, mask);
7070
7071 if (data >= 0)
7072 snd_hda_codec_write(codec, 0x01, 0,
7073 AC_VERB_SET_GPIO_DATA, data);
7074}
7075
7076static void sbz_exit_chip(struct hda_codec *codec)
7077{
009b8f97
CM		 7078 chipio_set_stream_control(codec, 0x03, 0);
7079 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 7080
7081 /* Mess with GPIO */
7082 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7083 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7084 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7085
009b8f97
CM		 7086 chipio_set_stream_control(codec, 0x14, 0);
7087 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7088
7089 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7090 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7091
7092 chipio_write(codec, 0x18a020, 0x00000083);
7093
7094 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7095 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7096 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7097
009b8f97 7098 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7099
7100 chipio_set_control_param(codec, 0x0D, 0x24);
7101
2f295f91 7102 ca0132_clear_unsolicited(codec);
2e48b2b7
CM		 7103 sbz_set_pin_ctl_default(codec);
7104
7105 snd_hda_codec_write(codec, 0x0B, 0,
7106 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7107
2e48b2b7
CM		 7108 sbz_region2_exit(codec);
7109}
7110
2f295f91
CM		 7111static void r3d_exit_chip(struct hda_codec *codec)
7112{
7113 ca0132_clear_unsolicited(codec);
7114 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7115 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7116}
7117
95c6e9cb
IM		 7118static void ca0132_exit_chip(struct hda_codec *codec)
7119{
7120 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7121
7122 if (dspload_is_loaded(codec))
7123 dsp_reset(codec);
95c6e9cb
IM		 7124}
7125
38ba69ff
CM		 7126/*
7127 * This fixes a problem that was hard to reproduce. Very rarely, I would
7128 * boot up, and there would be no sound, but the DSP indicated it had loaded
7129 * properly. I did a few memory dumps to see if anything was different, and
7130 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7131 * checks if those areas are uninitialized, and if they are, it'll attempt to
7132 * reload the card 3 times. Usually it fixes by the second.
7133 */
7134static void sbz_dsp_startup_check(struct hda_codec *codec)
7135{
7136 struct ca0132_spec *spec = codec->spec;
7137 unsigned int dsp_data_check[4];
7138 unsigned int cur_address = 0x390;
7139 unsigned int i;
7140 unsigned int failure = 0;
7141 unsigned int reload = 3;
7142
7143 if (spec->startup_check_entered)
7144 return;
7145
7146 spec->startup_check_entered = true;
7147
7148 for (i = 0; i < 4; i++) {
7149 chipio_read(codec, cur_address, &dsp_data_check[i]);
7150 cur_address += 0x4;
7151 }
7152 for (i = 0; i < 4; i++) {
7153 if (dsp_data_check[i] == 0xa1a2a3a4)
7154 failure = 1;
7155 }
7156
7157 codec_dbg(codec, "Startup Check: %d ", failure);
7158 if (failure)
7159 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7160 /*
7161 * While the failure condition is true, and we haven't reached our
7162 * three reload limit, continue trying to reload the driver and
7163 * fix the issue.
7164 */
7165 while (failure && (reload != 0)) {
7166 codec_info(codec, "Reloading... Tries left: %d", reload);
7167 sbz_exit_chip(codec);
7168 spec->dsp_state = DSP_DOWNLOAD_INIT;
7169 codec->patch_ops.init(codec);
7170 failure = 0;
7171 for (i = 0; i < 4; i++) {
7172 chipio_read(codec, cur_address, &dsp_data_check[i]);
7173 cur_address += 0x4;
7174 }
7175 for (i = 0; i < 4; i++) {
7176 if (dsp_data_check[i] == 0xa1a2a3a4)
7177 failure = 1;
7178 }
7179 reload--;
7180 }
7181
7182 if (!failure && reload < 3)
7183 codec_info(codec, "DSP fixed.");
7184
7185 if (!failure)
7186 return;
7187
7188 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7189}
7190
e93ac30a
CM		 7191/*
7192 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7193 * extra precision for decibel values. If you had the dB value in floating point
7194 * you would take the value after the decimal point, multiply by 64, and divide
7195 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7196 * implement fixed point or floating point dB volumes. For now, I'll set them
7197 * to 0 just incase a value has lingered from a boot into Windows.
7198 */
7199static void ca0132_alt_vol_setup(struct hda_codec *codec)
7200{
7201 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7202 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7203 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7204 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7205 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7206 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7207 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7208 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7209}
7210
7211/*
7212 * Extra commands that don't really fit anywhere else.
7213 */
7214static void sbz_pre_dsp_setup(struct hda_codec *codec)
7215{
7216 struct ca0132_spec *spec = codec->spec;
7217
7218 writel(0x00820680, spec->mem_base + 0x01C);
7219 writel(0x00820680, spec->mem_base + 0x01C);
7220
e93ac30a
CM		 7221 chipio_write(codec, 0x18b0a4, 0x000000c2);
7222
7223 snd_hda_codec_write(codec, 0x11, 0,
7224 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7225}
7226
e42c7c73
CM		 7227static void r3d_pre_dsp_setup(struct hda_codec *codec)
7228{
e42c7c73
CM		 7229 chipio_write(codec, 0x18b0a4, 0x000000c2);
7230
7231 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7232 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7233 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7234 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7235 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7236 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7237
7238 snd_hda_codec_write(codec, 0x11, 0,
7239 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7240}
7241
e93ac30a
CM		 7242static void r3di_pre_dsp_setup(struct hda_codec *codec)
7243{
7244 chipio_write(codec, 0x18b0a4, 0x000000c2);
7245
7246 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7247 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7248 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7249 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7250 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7251 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7252
7253 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7254 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7255 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7256 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7257 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7258 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7259 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7260 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7261
7262 snd_hda_codec_write(codec, 0x11, 0,
7263 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7264}
7265
e93ac30a
CM		 7266/*
7267 * These are sent before the DSP is downloaded. Not sure
7268 * what they do, or if they're necessary. Could possibly
7269 * be removed. Figure they're better to leave in.
7270 */
e42c7c73 7271static void ca0132_mmio_init(struct hda_codec *codec)
e93ac30a
CM		 7272{
7273 struct ca0132_spec *spec = codec->spec;
7274
ce715448
CM		 7275 if (spec->quirk == QUIRK_AE5)
7276 writel(0x00000001, spec->mem_base + 0x400);
7277 else
7278 writel(0x00000000, spec->mem_base + 0x400);
7279
7280 if (spec->quirk == QUIRK_AE5)
7281 writel(0x00000001, spec->mem_base + 0x408);
7282 else
7283 writel(0x00000000, spec->mem_base + 0x408);
7284
7285 if (spec->quirk == QUIRK_AE5)
7286 writel(0x00000001, spec->mem_base + 0x40c);
7287 else
7288 writel(0x00000000, spec->mem_base + 0x40C);
7289
e93ac30a 7290 writel(0x00880680, spec->mem_base + 0x01C);
ce715448
CM		 7291
7292 if (spec->quirk == QUIRK_AE5)
7293 writel(0x00000080, spec->mem_base + 0xC0C);
7294 else
7295 writel(0x00000083, spec->mem_base + 0xC0C);
7296
e93ac30a
CM		 7297 writel(0x00000030, spec->mem_base + 0xC00);
7298 writel(0x00000000, spec->mem_base + 0xC04);
ce715448
CM		 7299
7300 if (spec->quirk == QUIRK_AE5)
7301 writel(0x00000000, spec->mem_base + 0xC0C);
7302 else
7303 writel(0x00000003, spec->mem_base + 0xC0C);
7304
e93ac30a
CM		 7305 writel(0x00000003, spec->mem_base + 0xC0C);
7306 writel(0x00000003, spec->mem_base + 0xC0C);
7307 writel(0x00000003, spec->mem_base + 0xC0C);
ce715448
CM		 7308
7309 if (spec->quirk == QUIRK_AE5)
7310 writel(0x00000001, spec->mem_base + 0xC08);
7311 else
7312 writel(0x000000C1, spec->mem_base + 0xC08);
7313
e93ac30a
CM		 7314 writel(0x000000F1, spec->mem_base + 0xC08);
7315 writel(0x00000001, spec->mem_base + 0xC08);
7316 writel(0x000000C7, spec->mem_base + 0xC08);
7317 writel(0x000000C1, spec->mem_base + 0xC08);
7318 writel(0x00000080, spec->mem_base + 0xC04);
ce715448
CM		 7319
7320 if (spec->quirk == QUIRK_AE5) {
7321 writel(0x00000000, spec->mem_base + 0x42c);
7322 writel(0x00000000, spec->mem_base + 0x46c);
7323 writel(0x00000000, spec->mem_base + 0x4ac);
7324 writel(0x00000000, spec->mem_base + 0x4ec);
7325 writel(0x00000000, spec->mem_base + 0x43c);
7326 writel(0x00000000, spec->mem_base + 0x47c);
7327 writel(0x00000000, spec->mem_base + 0x4bc);
7328 writel(0x00000000, spec->mem_base + 0x4fc);
7329 writel(0x00000600, spec->mem_base + 0x100);
7330 writel(0x00000014, spec->mem_base + 0x410);
7331 writel(0x0000060f, spec->mem_base + 0x100);
7332 writel(0x0000070f, spec->mem_base + 0x100);
7333 writel(0x00000aff, spec->mem_base + 0x830);
7334 writel(0x00000000, spec->mem_base + 0x86c);
7335 writel(0x0000006b, spec->mem_base + 0x800);
7336 writel(0x00000001, spec->mem_base + 0x86c);
7337 writel(0x0000006b, spec->mem_base + 0x800);
7338 writel(0x00000057, spec->mem_base + 0x804);
7339 writel(0x00800000, spec->mem_base + 0x20c);
7340 }
e93ac30a
CM		 7341}
7342
b9b41345
CM		 7343/*
7344 * This function writes to some SFR's, does some region2 writes, and then
7345 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
7346 * what it does.
7347 */
7348static void ae5_register_set(struct hda_codec *codec)
7349{
7350 struct ca0132_spec *spec = codec->spec;
7351
7352 chipio_8051_write_direct(codec, 0x93, 0x10);
7353 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7354 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7355 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7356 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7357
7358 writeb(0x0f, spec->mem_base + 0x304);
7359 writeb(0x0f, spec->mem_base + 0x304);
7360 writeb(0x0f, spec->mem_base + 0x304);
7361 writeb(0x0f, spec->mem_base + 0x304);
7362 writeb(0x0e, spec->mem_base + 0x100);
7363 writeb(0x1f, spec->mem_base + 0x304);
7364 writeb(0x0c, spec->mem_base + 0x100);
7365 writeb(0x3f, spec->mem_base + 0x304);
7366 writeb(0x08, spec->mem_base + 0x100);
7367 writeb(0x7f, spec->mem_base + 0x304);
7368 writeb(0x00, spec->mem_base + 0x100);
7369 writeb(0xff, spec->mem_base + 0x304);
7370
7371 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7372
7373 chipio_8051_write_direct(codec, 0x90, 0x00);
7374 chipio_8051_write_direct(codec, 0x90, 0x10);
7375
7376 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7377
7378 chipio_write(codec, 0x18b0a4, 0x000000c2);
7379
7380 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
7381 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
7382}
7383
e93ac30a
CM		 7384/*
7385 * Extra init functions for alternative ca0132 codecs. Done
7386 * here so they don't clutter up the main ca0132_init function
7387 * anymore than they have to.
7388 */
7389static void ca0132_alt_init(struct hda_codec *codec)
7390{
7391 struct ca0132_spec *spec = codec->spec;
7392
7393 ca0132_alt_vol_setup(codec);
7394
7395 switch (spec->quirk) {
7396 case QUIRK_SBZ:
7397 codec_dbg(codec, "SBZ alt_init");
7398 ca0132_gpio_init(codec);
7399 sbz_pre_dsp_setup(codec);
7400 snd_hda_sequence_write(codec, spec->chip_init_verbs);
e42c7c73 7401 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
e93ac30a
CM		 7402 break;
7403 case QUIRK_R3DI:
7404 codec_dbg(codec, "R3DI alt_init");
7405 ca0132_gpio_init(codec);
7406 ca0132_gpio_setup(codec);
7e6ed62e 7407 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 7408 r3di_pre_dsp_setup(codec);
7409 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7410 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7411 break;
e42c7c73
CM		 7412 case QUIRK_R3D:
7413 r3d_pre_dsp_setup(codec);
7414 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7415 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7416 break;
03c9b6b1
CM		 7417 case QUIRK_AE5:
7418 ca0132_gpio_init(codec);
7419 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7420 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
7421 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7422 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
7423 chipio_write(codec, 0x18b030, 0x00000020);
7424 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7425 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7426 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7427 break;
e93ac30a
CM		 7428 }
7429}
7430
95c6e9cb
IM		 7431static int ca0132_init(struct hda_codec *codec)
7432{
7433 struct ca0132_spec *spec = codec->spec;
7434 struct auto_pin_cfg *cfg = &spec->autocfg;
7435 int i;
e93ac30a
CM		 7436 bool dsp_loaded;
7437
7438 /*
7439 * If the DSP is already downloaded, and init has been entered again,
7440 * there's only two reasons for it. One, the codec has awaken from a
7441 * suspended state, and in that case dspload_is_loaded will return
7442 * false, and the init will be ran again. The other reason it gets
7443 * re entered is on startup for some reason it triggers a suspend and
7444 * resume state. In this case, it will check if the DSP is downloaded,
7445 * and not run the init function again. For codecs using alt_functions,
7446 * it will check if the DSP is loaded properly.
7447 */
7448 if (spec->dsp_state == DSP_DOWNLOADED) {
7449 dsp_loaded = dspload_is_loaded(codec);
7450 if (!dsp_loaded) {
7451 spec->dsp_reload = true;
7452 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 7453 } else {
7454 if (spec->quirk == QUIRK_SBZ)
7455 sbz_dsp_startup_check(codec);
e93ac30a 7456 return 0;
38ba69ff 7457 }
e93ac30a 7458 }
95c6e9cb 7459
e24aa0a4
TI		 7460 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7461 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 7462 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 7463
e42c7c73
CM		 7464 if (spec->use_pci_mmio)
7465 ca0132_mmio_init(codec);
e93ac30a 7466
664c7155 7467 snd_hda_power_up_pm(codec);
5aaca44d 7468
b9b41345
CM		 7469 if (spec->quirk == QUIRK_AE5)
7470 ae5_register_set(codec);
7471
f8fb1170 7472 ca0132_init_unsol(codec);
5aaca44d
IM		 7473 ca0132_init_params(codec);
7474 ca0132_init_flags(codec);
7e6ed62e 7475
5aaca44d 7476 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 7477
365c7f25 7478 if (spec->use_alt_functions)
e93ac30a
CM		 7479 ca0132_alt_init(codec);
7480
01ef7dbf 7481 ca0132_download_dsp(codec);
7e6ed62e 7482
5aaca44d 7483 ca0132_refresh_widget_caps(codec);
e93ac30a 7484
7e6ed62e
CM		 7485 switch (spec->quirk) {
7486 case QUIRK_R3DI:
c986f50c
CM		 7487 case QUIRK_R3D:
7488 r3d_setup_defaults(codec);
7e6ed62e 7489 break;
126b75e0 7490 case QUIRK_SBZ:
d97420d2 7491 sbz_setup_defaults(codec);
126b75e0
AB		 7492 break;
7493 default:
38ba69ff
CM		 7494 ca0132_setup_defaults(codec);
7495 ca0132_init_analog_mic2(codec);
7496 ca0132_init_dmic(codec);
7e6ed62e 7497 break;
38ba69ff 7498 }
5aaca44d
IM		 7499
7500 for (i = 0; i < spec->num_outputs; i++)
7501 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 7502
95c6e9cb
IM		 7503 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7504
7505 for (i = 0; i < spec->num_inputs; i++)
7506 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7507
7508 init_input(codec, cfg->dig_in_pin, spec->dig_in);
7509
009b8f97 7510 if (!spec->use_alt_functions) {
e93ac30a
CM		 7511 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7512 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7513 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7514 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7515 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7516 }
7517
7cb9d94c 7518 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 7519 ca0132_gpio_setup(codec);
7520
d5c016b5 7521 snd_hda_sequence_write(codec, spec->spec_init_verbs);
d97420d2 7522 if (spec->use_alt_functions) {
7cb9d94c
CM		 7523 ca0132_alt_select_out(codec);
7524 ca0132_alt_select_in(codec);
d97420d2 7525 } else {
7cb9d94c
CM		 7526 ca0132_select_out(codec);
7527 ca0132_select_mic(codec);
7cb9d94c 7528 }
5aaca44d 7529
a73d511c
IM		 7530 snd_hda_jack_report_sync(codec);
7531
e93ac30a
CM		 7532 /*
7533 * Re set the PlayEnhancement switch on a resume event, because the
7534 * controls will not be reloaded.
7535 */
7536 if (spec->dsp_reload) {
7537 spec->dsp_reload = false;
7538 ca0132_pe_switch_set(codec);
7539 }
7540
664c7155 7541 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 7542
7543 return 0;
7544}
7545
95c6e9cb
IM		 7546static void ca0132_free(struct hda_codec *codec)
7547{
5aaca44d
IM		 7548 struct ca0132_spec *spec = codec->spec;
7549
993884f6 7550 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 7551 snd_hda_power_up(codec);
2e48b2b7
CM		 7552 switch (spec->quirk) {
7553 case QUIRK_SBZ:
7554 sbz_exit_chip(codec);
7555 break;
2f295f91
CM		 7556 case QUIRK_R3D:
7557 r3d_exit_chip(codec);
7558 break;
2e48b2b7
CM		 7559 case QUIRK_R3DI:
7560 r3di_gpio_shutdown(codec);
2e48b2b7
CM		 7561 break;
7562 }
2f295f91
CM		 7563
7564 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7565 ca0132_exit_chip(codec);
7566
5aaca44d 7567 snd_hda_power_down(codec);
aa31704f
CM		 7568 if (spec->mem_base)
7569 iounmap(spec->mem_base);
d5c016b5 7570 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 7571 kfree(codec->spec);
7572}
7573
2e48b2b7
CM		 7574static void ca0132_reboot_notify(struct hda_codec *codec)
7575{
7576 codec->patch_ops.free(codec);
7577}
7578
071f1344 7579static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 7580 .build_controls = ca0132_build_controls,
7581 .build_pcms = ca0132_build_pcms,
7582 .init = ca0132_init,
7583 .free = ca0132_free,
f8fb1170 7584 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 7585 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 7586};
7587
441aa6a0
IM		 7588static void ca0132_config(struct hda_codec *codec)
7589{
7590 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 7591
7592 spec->dacs[0] = 0x2;
7593 spec->dacs[1] = 0x3;
7594 spec->dacs[2] = 0x4;
7595
7596 spec->multiout.dac_nids = spec->dacs;
7597 spec->multiout.num_dacs = 3;
441aa6a0 7598
009b8f97 7599 if (!spec->use_alt_functions)
63177afc
CM		 7600 spec->multiout.max_channels = 2;
7601 else
7602 spec->multiout.max_channels = 6;
7603
7604 switch (spec->quirk) {
7605 case QUIRK_ALIENWARE:
d06feaf0 7606 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
fe14f39e 7607 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
d06feaf0
CM		 7608 break;
7609 case QUIRK_SBZ:
7610 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7611 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7612 break;
7613 case QUIRK_R3D:
7614 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
7615 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
7616 break;
7617 case QUIRK_R3DI:
7618 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7619 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7620 break;
7621 case QUIRK_AE5:
7622 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
7623 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7624 break;
7625 }
fe14f39e 7626
d06feaf0
CM		 7627 switch (spec->quirk) {
7628 case QUIRK_ALIENWARE:
fe14f39e
TI		 7629 spec->num_outputs = 2;
7630 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 7631 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 7632 spec->shared_out_nid = 0x2;
7633 spec->unsol_tag_hp = 0x0f;
7634
7635 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7636 spec->adcs[1] = 0x8; /* analog mic2 */
7637 spec->adcs[2] = 0xa; /* what u hear */
7638
7639 spec->num_inputs = 3;
7640 spec->input_pins[0] = 0x12;
7641 spec->input_pins[1] = 0x11;
7642 spec->input_pins[2] = 0x13;
7643 spec->shared_mic_nid = 0x7;
7644 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 7645 break;
7646 case QUIRK_SBZ:
7f73df95 7647 case QUIRK_R3D:
63177afc
CM		 7648 spec->num_outputs = 2;
7649 spec->out_pins[0] = 0x0B; /* Line out */
7650 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7651 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7652 spec->out_pins[3] = 0x11; /* Rear surround */
7653 spec->shared_out_nid = 0x2;
7654 spec->unsol_tag_hp = spec->out_pins[1];
7655 spec->unsol_tag_front_hp = spec->out_pins[2];
7656
7657 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7658 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7659 spec->adcs[2] = 0xa; /* what u hear */
7660
7661 spec->num_inputs = 2;
7662 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7663 spec->input_pins[1] = 0x13; /* What U Hear */
7664 spec->shared_mic_nid = 0x7;
7665 spec->unsol_tag_amic1 = spec->input_pins[0];
7666
7667 /* SPDIF I/O */
7668 spec->dig_out = 0x05;
7669 spec->multiout.dig_out_nid = spec->dig_out;
63177afc 7670 spec->dig_in = 0x09;
63177afc 7671 break;
d06feaf0
CM		 7672 case QUIRK_AE5:
7673 spec->num_outputs = 2;
7674 spec->out_pins[0] = 0x0B; /* Line out */
7675 spec->out_pins[1] = 0x11; /* Rear headphone out */
7676 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7677 spec->out_pins[3] = 0x0F; /* Rear surround */
7678 spec->shared_out_nid = 0x2;
7679 spec->unsol_tag_hp = spec->out_pins[1];
7680 spec->unsol_tag_front_hp = spec->out_pins[2];
7681
7682 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7683 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7684 spec->adcs[2] = 0xa; /* what u hear */
63177afc 7685
d06feaf0
CM		 7686 spec->num_inputs = 2;
7687 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7688 spec->input_pins[1] = 0x13; /* What U Hear */
7689 spec->shared_mic_nid = 0x7;
7690 spec->unsol_tag_amic1 = spec->input_pins[0];
7691
7692 /* SPDIF I/O */
7693 spec->dig_out = 0x05;
7694 spec->multiout.dig_out_nid = spec->dig_out;
7695 break;
7696 case QUIRK_R3DI:
63177afc
CM		 7697 spec->num_outputs = 2;
7698 spec->out_pins[0] = 0x0B; /* Line out */
7699 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7700 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7701 spec->out_pins[3] = 0x11; /* Rear surround */
7702 spec->shared_out_nid = 0x2;
7703 spec->unsol_tag_hp = spec->out_pins[1];
7704 spec->unsol_tag_front_hp = spec->out_pins[2];
7705
7706 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7707 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7708 spec->adcs[2] = 0x0a; /* what u hear */
7709
7710 spec->num_inputs = 2;
7711 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7712 spec->input_pins[1] = 0x13; /* What U Hear */
7713 spec->shared_mic_nid = 0x7;
7714 spec->unsol_tag_amic1 = spec->input_pins[0];
7715
7716 /* SPDIF I/O */
7717 spec->dig_out = 0x05;
7718 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 7719 break;
7720 default:
fe14f39e
TI		 7721 spec->num_outputs = 2;
7722 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 7723 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 7724 spec->shared_out_nid = 0x2;
7725 spec->unsol_tag_hp = spec->out_pins[1];
7726
7727 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7728 spec->adcs[1] = 0x8; /* analog mic2 */
7729 spec->adcs[2] = 0xa; /* what u hear */
7730
7731 spec->num_inputs = 3;
7732 spec->input_pins[0] = 0x12;
7733 spec->input_pins[1] = 0x11;
7734 spec->input_pins[2] = 0x13;
7735 spec->shared_mic_nid = 0x7;
7736 spec->unsol_tag_amic1 = spec->input_pins[0];
7737
7738 /* SPDIF I/O */
7739 spec->dig_out = 0x05;
7740 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 7741 spec->dig_in = 0x09;
63177afc 7742 break;
d5c016b5 7743 }
441aa6a0
IM		 7744}
7745
d5c016b5
GM		 7746static int ca0132_prepare_verbs(struct hda_codec *codec)
7747{
7748/* Verbs + terminator (an empty element) */
a3d90d67 7749#define NUM_SPEC_VERBS 2
d5c016b5
GM		 7750 struct ca0132_spec *spec = codec->spec;
7751
7752 spec->chip_init_verbs = ca0132_init_verbs0;
88268ce8
CM		 7753 /*
7754 * Since desktop cards use pci_mmio, this can be used to determine
7755 * whether or not to use these verbs instead of a separate bool.
7756 */
7757 if (spec->use_pci_mmio)
e42c7c73 7758 spec->desktop_init_verbs = ca0132_init_verbs1;
6396bb22
KC		 7759 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7760 sizeof(struct hda_verb),
7761 GFP_KERNEL);
d5c016b5
GM		 7762 if (!spec->spec_init_verbs)
7763 return -ENOMEM;
7764
d5c016b5 7765 /* config EAPD */
a3d90d67
AB		 7766 spec->spec_init_verbs[0].nid = 0x0b;
7767 spec->spec_init_verbs[0].param = 0x78D;
7768 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 7769
7770 /* Previously commented configuration */
7771 /*
a3d90d67
AB		 7772 spec->spec_init_verbs[2].nid = 0x0b;
7773 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
7774 spec->spec_init_verbs[2].verb = 0x02;
7775
7776 spec->spec_init_verbs[3].nid = 0x10;
7777 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 7778 spec->spec_init_verbs[3].verb = 0x02;
7779
7780 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 7781 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 7782 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 7783 */
7784
7785 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7786 return 0;
7787}
7788
95c6e9cb
IM		 7789static int patch_ca0132(struct hda_codec *codec)
7790{
7791 struct ca0132_spec *spec;
a73d511c 7792 int err;
d5c016b5 7793 const struct snd_pci_quirk *quirk;
95c6e9cb 7794
4e76a883 7795 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 7796
7797 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7798 if (!spec)
7799 return -ENOMEM;
7800 codec->spec = spec;
993884f6 7801 spec->codec = codec;
95c6e9cb 7802
225068ab
TI		 7803 codec->patch_ops = ca0132_patch_ops;
7804 codec->pcm_format_first = 1;
7805 codec->no_sticky_stream = 1;
7806
d5c016b5
GM		 7807 /* Detect codec quirk */
7808 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7809 if (quirk)
7810 spec->quirk = quirk->value;
7811 else
7812 spec->quirk = QUIRK_NONE;
7813
e24aa0a4 7814 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 7815 spec->num_mixers = 1;
017310fb
CM		 7816
7817 /* Set which mixers each quirk uses. */
7818 switch (spec->quirk) {
7819 case QUIRK_SBZ:
e25e3445 7820 spec->mixers[0] = desktop_mixer;
017310fb
CM		 7821 snd_hda_codec_set_name(codec, "Sound Blaster Z");
7822 break;
e25e3445
CM		 7823 case QUIRK_R3D:
7824 spec->mixers[0] = desktop_mixer;
7825 snd_hda_codec_set_name(codec, "Recon3D");
7826 break;
017310fb
CM		 7827 case QUIRK_R3DI:
7828 spec->mixers[0] = r3di_mixer;
7829 snd_hda_codec_set_name(codec, "Recon3Di");
7830 break;
88268ce8
CM		 7831 case QUIRK_AE5:
7832 spec->mixers[0] = desktop_mixer;
7833 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
7834 break;
017310fb
CM		 7835 default:
7836 spec->mixers[0] = ca0132_mixer;
7837 break;
7838 }
a7e76271 7839
08eca6b1 7840 /* Setup whether or not to use alt functions/controls/pci_mmio */
009b8f97
CM		 7841 switch (spec->quirk) {
7842 case QUIRK_SBZ:
e42c7c73 7843 case QUIRK_R3D:
88268ce8 7844 case QUIRK_AE5:
08eca6b1
CM		 7845 spec->use_alt_controls = true;
7846 spec->use_alt_functions = true;
7847 spec->use_pci_mmio = true;
7848 break;
009b8f97 7849 case QUIRK_R3DI:
47cdf76e 7850 spec->use_alt_controls = true;
009b8f97 7851 spec->use_alt_functions = true;
08eca6b1 7852 spec->use_pci_mmio = false;
009b8f97
CM		 7853 break;
7854 default:
47cdf76e 7855 spec->use_alt_controls = false;
009b8f97 7856 spec->use_alt_functions = false;
08eca6b1 7857 spec->use_pci_mmio = false;
009b8f97
CM		 7858 break;
7859 }
7860
08eca6b1
CM		 7861 if (spec->use_pci_mmio) {
7862 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7863 if (spec->mem_base == NULL) {
7864 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
7865 spec->quirk = QUIRK_NONE;
7866 }
7867 }
7868
5aaca44d
IM		 7869 spec->base_init_verbs = ca0132_base_init_verbs;
7870 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 7871
993884f6
CCC		 7872 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7873
95c6e9cb
IM		 7874 ca0132_init_chip(codec);
7875
7876 ca0132_config(codec);
7877
d5c016b5
GM		 7878 err = ca0132_prepare_verbs(codec);
7879 if (err < 0)
cc91ceaf 7880 goto error;
d5c016b5 7881
a73d511c
IM		 7882 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7883 if (err < 0)
cc91ceaf 7884 goto error;
a73d511c 7885
95c6e9cb 7886 return 0;
cc91ceaf
TI		 7887
7888 error:
7889 ca0132_free(codec);
7890 return err;
95c6e9cb
IM		 7891}
7892
7893/*
7894 * patch entries
7895 */
b9a94a9c
TI		 7896static struct hda_device_id snd_hda_id_ca0132[] = {
7897 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 7898 {} /* terminator */
7899};
b9a94a9c 7900MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 7901
7902MODULE_LICENSE("GPL");
406261ce 7903MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 7904
d8a766a1 7905static struct hda_codec_driver ca0132_driver = {
b9a94a9c 7906 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 7907};
7908
d8a766a1 7909module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)