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ALSA: hda - Add DSP firmware enums and defs to CA0132 codec
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/pci.h>
28#include <linux/mutex.h>
da155d5b 29#include <linux/module.h>
4aa3bb0c 30#include <linux/firmware.h>
95c6e9cb
IM		 31#include <sound/core.h>
32#include "hda_codec.h"
33#include "hda_local.h"
128bc4ba 34#include "hda_auto_parser.h"
95c6e9cb 35
bcd109c0
IM		 36#include "ca0132_regs.h"
37
4aa3bb0c
IM		 38#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
39#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
40
41#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
42#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
43#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
44
45#define MASTERCONTROL 0x80
46#define MASTERCONTROL_ALLOC_DMA_CHAN 9
47
95c6e9cb
IM		 48#define WIDGET_CHIP_CTRL 0x15
49#define WIDGET_DSP_CTRL 0x16
50
51#define WUH_MEM_CONNID 10
52#define DSP_MEM_CONNID 16
53
4aa3bb0c
IM		 54#define MEM_CONNID_MICIN1 3
55#define MEM_CONNID_MICIN2 5
56#define MEM_CONNID_MICOUT1 12
57#define MEM_CONNID_MICOUT2 14
58#define MEM_CONNID_WUH 10
59#define MEM_CONNID_DSP 16
60#define MEM_CONNID_DMIC 100
61
62#define SCP_SET 0
63#define SCP_GET 1
64
95c6e9cb
IM		 65enum hda_cmd_vendor_io {
66 /* for DspIO node */
67 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
68 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
69
70 VENDOR_DSPIO_STATUS = 0xF01,
71 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
72 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
73 VENDOR_DSPIO_DSP_INIT = 0x703,
74 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
75 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
76
77 /* for ChipIO node */
78 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
79 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
80 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
81 VENDOR_CHIPIO_DATA_LOW = 0x300,
82 VENDOR_CHIPIO_DATA_HIGH = 0x400,
83
84 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
85 VENDOR_CHIPIO_STATUS = 0xF01,
86 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
87 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
88
4aa3bb0c
IM		 89 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
90 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
91
95c6e9cb 92 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 93 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 94
95 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
96 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
97 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
98 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
99 VENDOR_CHIPIO_FLAG_SET = 0x70F,
100 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 101 VENDOR_CHIPIO_PARAM_SET = 0x710,
102 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 103
104 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
105 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
106 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
107 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
108
4aa3bb0c
IM		 109 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
110 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
111 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
112 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
113
114 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
115 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
116 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
117 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
118 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
119 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
120
121 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 122};
123
124/*
125 * Control flag IDs
126 */
127enum control_flag_id {
128 /* Connection manager stream setup is bypassed/enabled */
129 CONTROL_FLAG_C_MGR = 0,
130 /* DSP DMA is bypassed/enabled */
131 CONTROL_FLAG_DMA = 1,
132 /* 8051 'idle' mode is disabled/enabled */
133 CONTROL_FLAG_IDLE_ENABLE = 2,
134 /* Tracker for the SPDIF-in path is bypassed/enabled */
135 CONTROL_FLAG_TRACKER = 3,
136 /* DigitalOut to Spdif2Out connection is disabled/enabled */
137 CONTROL_FLAG_SPDIF2OUT = 4,
138 /* Digital Microphone is disabled/enabled */
139 CONTROL_FLAG_DMIC = 5,
140 /* ADC_B rate is 48 kHz/96 kHz */
141 CONTROL_FLAG_ADC_B_96KHZ = 6,
142 /* ADC_C rate is 48 kHz/96 kHz */
143 CONTROL_FLAG_ADC_C_96KHZ = 7,
144 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
145 CONTROL_FLAG_DAC_96KHZ = 8,
146 /* DSP rate is 48 kHz/96 kHz */
147 CONTROL_FLAG_DSP_96KHZ = 9,
148 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
149 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
150 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
151 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
152 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
153 CONTROL_FLAG_DECODE_LOOP = 12,
154 /* De-emphasis filter on DAC-1 disabled/enabled */
155 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
156 /* De-emphasis filter on DAC-2 disabled/enabled */
157 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
158 /* De-emphasis filter on DAC-3 disabled/enabled */
159 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
160 /* High-pass filter on ADC_B disabled/enabled */
161 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
162 /* High-pass filter on ADC_C disabled/enabled */
163 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
164 /* Common mode on Port_A disabled/enabled */
165 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
166 /* Common mode on Port_D disabled/enabled */
167 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
168 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
169 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
170 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 171 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 172 /* ASI rate is 48kHz/96kHz */
173 CONTROL_FLAG_ASI_96KHZ = 22,
174 /* DAC power settings able to control attached ports no/yes */
175 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
176 /* Clock Stop OK reporting is disabled/enabled */
177 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
178 /* Number of control flags */
179 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
180};
181
182/*
183 * Control parameter IDs
184 */
4aa3bb0c 185enum control_param_id {
95c6e9cb
IM		 186 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
187 CONTROL_PARAM_SPDIF1_SOURCE = 2,
188
189 /* Stream Control */
190
191 /* Select stream with the given ID */
192 CONTROL_PARAM_STREAM_ID = 24,
193 /* Source connection point for the selected stream */
194 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
195 /* Destination connection point for the selected stream */
196 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
197 /* Number of audio channels in the selected stream */
198 CONTROL_PARAM_STREAMS_CHANNELS = 27,
199 /*Enable control for the selected stream */
200 CONTROL_PARAM_STREAM_CONTROL = 28,
201
202 /* Connection Point Control */
203
204 /* Select connection point with the given ID */
205 CONTROL_PARAM_CONN_POINT_ID = 29,
206 /* Connection point sample rate */
207 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
208
209 /* Node Control */
210
211 /* Select HDA node with the given ID */
212 CONTROL_PARAM_NODE_ID = 31
213};
214
215/*
216 * Dsp Io Status codes
217 */
218enum hda_vendor_status_dspio {
219 /* Success */
220 VENDOR_STATUS_DSPIO_OK = 0x00,
221 /* Busy, unable to accept new command, the host must retry */
222 VENDOR_STATUS_DSPIO_BUSY = 0x01,
223 /* SCP command queue is full */
224 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
225 /* SCP response queue is empty */
226 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
227};
228
229/*
230 * Chip Io Status codes
231 */
232enum hda_vendor_status_chipio {
233 /* Success */
234 VENDOR_STATUS_CHIPIO_OK = 0x00,
235 /* Busy, unable to accept new command, the host must retry */
236 VENDOR_STATUS_CHIPIO_BUSY = 0x01
237};
238
239/*
240 * CA0132 sample rate
241 */
242enum ca0132_sample_rate {
243 SR_6_000 = 0x00,
244 SR_8_000 = 0x01,
245 SR_9_600 = 0x02,
246 SR_11_025 = 0x03,
247 SR_16_000 = 0x04,
248 SR_22_050 = 0x05,
249 SR_24_000 = 0x06,
250 SR_32_000 = 0x07,
251 SR_44_100 = 0x08,
252 SR_48_000 = 0x09,
253 SR_88_200 = 0x0A,
254 SR_96_000 = 0x0B,
255 SR_144_000 = 0x0C,
256 SR_176_400 = 0x0D,
257 SR_192_000 = 0x0E,
258 SR_384_000 = 0x0F,
259
260 SR_COUNT = 0x10,
261
262 SR_RATE_UNKNOWN = 0x1F
263};
264
265/*
266 * Scp Helper function
267 */
268enum get_set {
269 IS_SET = 0,
270 IS_GET = 1,
271};
272
273/*
274 * Duplicated from ca0110 codec
275 */
276
277static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
278{
279 if (pin) {
cdd03ced 280 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
95c6e9cb
IM		 281 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
282 snd_hda_codec_write(codec, pin, 0,
283 AC_VERB_SET_AMP_GAIN_MUTE,
284 AMP_OUT_UNMUTE);
285 }
8e13fc1c 286 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
95c6e9cb
IM		 287 snd_hda_codec_write(codec, dac, 0,
288 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
289}
290
291static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
292{
293 if (pin) {
4740860b
TI		 294 snd_hda_set_pin_ctl(codec, pin, PIN_IN |
295 snd_hda_get_default_vref(codec, pin));
95c6e9cb
IM		 296 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
297 snd_hda_codec_write(codec, pin, 0,
298 AC_VERB_SET_AMP_GAIN_MUTE,
299 AMP_IN_UNMUTE(0));
300 }
8e13fc1c 301 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP))
95c6e9cb
IM		 302 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
303 AMP_IN_UNMUTE(0));
304}
305
306static char *dirstr[2] = { "Playback", "Capture" };
307
308static int _add_switch(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
309 int chan, int dir)
310{
311 char namestr[44];
312 int type = dir ? HDA_INPUT : HDA_OUTPUT;
313 struct snd_kcontrol_new knew =
314 HDA_CODEC_MUTE_MONO(namestr, nid, chan, 0, type);
c41999a2
DH		 315 if ((query_amp_caps(codec, nid, type) & AC_AMPCAP_MUTE) == 0) {
316 snd_printdd("Skipping '%s %s Switch' (no mute on node 0x%x)\n", pfx, dirstr[dir], nid);
317 return 0;
318 }
95c6e9cb
IM		 319 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
320 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
321}
322
323static int _add_volume(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
324 int chan, int dir)
325{
326 char namestr[44];
327 int type = dir ? HDA_INPUT : HDA_OUTPUT;
328 struct snd_kcontrol_new knew =
329 HDA_CODEC_VOLUME_MONO(namestr, nid, chan, 0, type);
c41999a2
DH		 330 if ((query_amp_caps(codec, nid, type) & AC_AMPCAP_NUM_STEPS) == 0) {
331 snd_printdd("Skipping '%s %s Volume' (no amp on node 0x%x)\n", pfx, dirstr[dir], nid);
332 return 0;
333 }
95c6e9cb
IM		 334 sprintf(namestr, "%s %s Volume", pfx, dirstr[dir]);
335 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
336}
337
338#define add_out_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 0)
339#define add_out_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 0)
340#define add_in_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 1)
341#define add_in_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 1)
342#define add_mono_switch(codec, nid, pfx, chan) \
343 _add_switch(codec, nid, pfx, chan, 0)
344#define add_mono_volume(codec, nid, pfx, chan) \
345 _add_volume(codec, nid, pfx, chan, 0)
346#define add_in_mono_switch(codec, nid, pfx, chan) \
347 _add_switch(codec, nid, pfx, chan, 1)
348#define add_in_mono_volume(codec, nid, pfx, chan) \
349 _add_volume(codec, nid, pfx, chan, 1)
350
351
352/*
353 * CA0132 specific
354 */
355
356struct ca0132_spec {
357 struct auto_pin_cfg autocfg;
358 struct hda_multi_out multiout;
359 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
360 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
361 hda_nid_t hp_dac;
362 hda_nid_t input_pins[AUTO_PIN_LAST];
363 hda_nid_t adcs[AUTO_PIN_LAST];
364 hda_nid_t dig_out;
365 hda_nid_t dig_in;
366 unsigned int num_inputs;
367 long curr_hp_switch;
368 long curr_hp_volume[2];
369 long curr_speaker_switch;
370 struct mutex chipio_mutex;
371 const char *input_labels[AUTO_PIN_LAST];
372 struct hda_pcm pcm_rec[2]; /* PCM information */
373};
374
375/* Chip access helper function */
376static int chipio_send(struct hda_codec *codec,
377 unsigned int reg,
378 unsigned int data)
379{
380 unsigned int res;
381 int retry = 50;
382
383 /* send bits of data specified by reg */
384 do {
385 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
386 reg, data);
387 if (res == VENDOR_STATUS_CHIPIO_OK)
388 return 0;
389 } while (--retry);
390 return -EIO;
391}
392
393/*
394 * Write chip address through the vendor widget -- NOT protected by the Mutex!
395 */
396static int chipio_write_address(struct hda_codec *codec,
397 unsigned int chip_addx)
398{
399 int res;
400
401 /* send low 16 bits of the address */
402 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
403 chip_addx & 0xffff);
404
405 if (res != -EIO) {
406 /* send high 16 bits of the address */
407 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
408 chip_addx >> 16);
409 }
410
411 return res;
412}
413
414/*
415 * Write data through the vendor widget -- NOT protected by the Mutex!
416 */
417
418static int chipio_write_data(struct hda_codec *codec, unsigned int data)
419{
420 int res;
421
422 /* send low 16 bits of the data */
423 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
424
425 if (res != -EIO) {
426 /* send high 16 bits of the data */
427 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
428 data >> 16);
429 }
430
431 return res;
432}
433
434/*
435 * Read data through the vendor widget -- NOT protected by the Mutex!
436 */
437static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
438{
439 int res;
440
441 /* post read */
442 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
443
444 if (res != -EIO) {
445 /* read status */
446 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
447 }
448
449 if (res != -EIO) {
450 /* read data */
451 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
452 VENDOR_CHIPIO_HIC_READ_DATA,
453 0);
454 }
455
456 return res;
457}
458
459/*
460 * Write given value to the given address through the chip I/O widget.
461 * protected by the Mutex
462 */
463static int chipio_write(struct hda_codec *codec,
464 unsigned int chip_addx, const unsigned int data)
465{
466 struct ca0132_spec *spec = codec->spec;
467 int err;
468
469 mutex_lock(&spec->chipio_mutex);
470
471 /* write the address, and if successful proceed to write data */
472 err = chipio_write_address(codec, chip_addx);
473 if (err < 0)
474 goto exit;
475
476 err = chipio_write_data(codec, data);
477 if (err < 0)
478 goto exit;
479
480exit:
481 mutex_unlock(&spec->chipio_mutex);
482 return err;
483}
484
485/*
486 * Read the given address through the chip I/O widget
487 * protected by the Mutex
488 */
489static int chipio_read(struct hda_codec *codec,
490 unsigned int chip_addx, unsigned int *data)
491{
492 struct ca0132_spec *spec = codec->spec;
493 int err;
494
495 mutex_lock(&spec->chipio_mutex);
496
497 /* write the address, and if successful proceed to write data */
498 err = chipio_write_address(codec, chip_addx);
499 if (err < 0)
500 goto exit;
501
502 err = chipio_read_data(codec, data);
503 if (err < 0)
504 goto exit;
505
506exit:
507 mutex_unlock(&spec->chipio_mutex);
508 return err;
509}
510
511/*
27ebeb0b 512 * PCM callbacks
95c6e9cb 513 */
27ebeb0b
TI		 514static int ca0132_playback_pcm_open(struct hda_pcm_stream *hinfo,
515 struct hda_codec *codec,
516 struct snd_pcm_substream *substream)
95c6e9cb 517{
27ebeb0b
TI		 518 struct ca0132_spec *spec = codec->spec;
519 return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream,
520 hinfo);
95c6e9cb
IM		 521}
522
95c6e9cb
IM		 523static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
524 struct hda_codec *codec,
525 unsigned int stream_tag,
526 unsigned int format,
527 struct snd_pcm_substream *substream)
528{
529 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 530 return snd_hda_multi_out_analog_prepare(codec, &spec->multiout,
531 stream_tag, format, substream);
95c6e9cb
IM		 532}
533
534static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
535 struct hda_codec *codec,
536 struct snd_pcm_substream *substream)
537{
538 struct ca0132_spec *spec = codec->spec;
27ebeb0b 539 return snd_hda_multi_out_analog_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 540}
541
542/*
543 * Digital out
544 */
27ebeb0b
TI		 545static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
546 struct hda_codec *codec,
547 struct snd_pcm_substream *substream)
95c6e9cb
IM		 548{
549 struct ca0132_spec *spec = codec->spec;
27ebeb0b 550 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 551}
552
27ebeb0b 553static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 554 struct hda_codec *codec,
555 unsigned int stream_tag,
556 unsigned int format,
557 struct snd_pcm_substream *substream)
558{
559 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 560 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
561 stream_tag, format, substream);
95c6e9cb
IM		 562}
563
27ebeb0b 564static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 565 struct hda_codec *codec,
95c6e9cb
IM		 566 struct snd_pcm_substream *substream)
567{
568 struct ca0132_spec *spec = codec->spec;
27ebeb0b 569 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 570}
571
27ebeb0b
TI		 572static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
573 struct hda_codec *codec,
574 struct snd_pcm_substream *substream)
95c6e9cb
IM		 575{
576 struct ca0132_spec *spec = codec->spec;
27ebeb0b 577 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 578}
579
580/*
581 */
582static struct hda_pcm_stream ca0132_pcm_analog_playback = {
583 .substreams = 1,
584 .channels_min = 2,
585 .channels_max = 2,
586 .ops = {
27ebeb0b 587 .open = ca0132_playback_pcm_open,
95c6e9cb
IM		 588 .prepare = ca0132_playback_pcm_prepare,
589 .cleanup = ca0132_playback_pcm_cleanup
590 },
591};
592
593static struct hda_pcm_stream ca0132_pcm_analog_capture = {
594 .substreams = 1,
595 .channels_min = 2,
596 .channels_max = 2,
95c6e9cb
IM		 597};
598
599static struct hda_pcm_stream ca0132_pcm_digital_playback = {
600 .substreams = 1,
601 .channels_min = 2,
602 .channels_max = 2,
603 .ops = {
27ebeb0b
TI		 604 .open = ca0132_dig_playback_pcm_open,
605 .close = ca0132_dig_playback_pcm_close,
95c6e9cb
IM		 606 .prepare = ca0132_dig_playback_pcm_prepare,
607 .cleanup = ca0132_dig_playback_pcm_cleanup
608 },
609};
610
611static struct hda_pcm_stream ca0132_pcm_digital_capture = {
612 .substreams = 1,
613 .channels_min = 2,
614 .channels_max = 2,
95c6e9cb
IM		 615};
616
617static int ca0132_build_pcms(struct hda_codec *codec)
618{
619 struct ca0132_spec *spec = codec->spec;
620 struct hda_pcm *info = spec->pcm_rec;
621
622 codec->pcm_info = info;
623 codec->num_pcms = 0;
624
625 info->name = "CA0132 Analog";
626 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
627 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
628 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
629 spec->multiout.max_channels;
630 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
631 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_inputs;
632 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
633 codec->num_pcms++;
634
635 if (!spec->dig_out && !spec->dig_in)
636 return 0;
637
638 info++;
639 info->name = "CA0132 Digital";
640 info->pcm_type = HDA_PCM_TYPE_SPDIF;
641 if (spec->dig_out) {
642 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
643 ca0132_pcm_digital_playback;
644 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
645 }
646 if (spec->dig_in) {
647 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
648 ca0132_pcm_digital_capture;
649 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
650 }
651 codec->num_pcms++;
652
653 return 0;
654}
655
656#define REG_CODEC_MUTE 0x18b014
657#define REG_CODEC_HP_VOL_L 0x18b070
658#define REG_CODEC_HP_VOL_R 0x18b074
659
660static int ca0132_hp_switch_get(struct snd_kcontrol *kcontrol,
661 struct snd_ctl_elem_value *ucontrol)
662{
663 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
664 struct ca0132_spec *spec = codec->spec;
665 long *valp = ucontrol->value.integer.value;
666
667 *valp = spec->curr_hp_switch;
668 return 0;
669}
670
671static int ca0132_hp_switch_put(struct snd_kcontrol *kcontrol,
672 struct snd_ctl_elem_value *ucontrol)
673{
674 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
675 struct ca0132_spec *spec = codec->spec;
676 long *valp = ucontrol->value.integer.value;
677 unsigned int data;
678 int err;
679
680 /* any change? */
681 if (spec->curr_hp_switch == *valp)
682 return 0;
683
684 snd_hda_power_up(codec);
685
686 err = chipio_read(codec, REG_CODEC_MUTE, &data);
687 if (err < 0)
b97f6bfd 688 goto exit;
95c6e9cb
IM		 689
690 /* *valp 0 is mute, 1 is unmute */
691 data = (data & 0x7f) | (*valp ? 0 : 0x80);
b97f6bfd 692 err = chipio_write(codec, REG_CODEC_MUTE, data);
95c6e9cb 693 if (err < 0)
b97f6bfd 694 goto exit;
95c6e9cb
IM		 695
696 spec->curr_hp_switch = *valp;
697
b97f6bfd 698 exit:
95c6e9cb 699 snd_hda_power_down(codec);
b97f6bfd 700 return err < 0 ? err : 1;
95c6e9cb
IM		 701}
702
703static int ca0132_speaker_switch_get(struct snd_kcontrol *kcontrol,
704 struct snd_ctl_elem_value *ucontrol)
705{
706 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
707 struct ca0132_spec *spec = codec->spec;
708 long *valp = ucontrol->value.integer.value;
709
710 *valp = spec->curr_speaker_switch;
711 return 0;
712}
713
714static int ca0132_speaker_switch_put(struct snd_kcontrol *kcontrol,
715 struct snd_ctl_elem_value *ucontrol)
716{
717 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
718 struct ca0132_spec *spec = codec->spec;
719 long *valp = ucontrol->value.integer.value;
720 unsigned int data;
721 int err;
722
723 /* any change? */
724 if (spec->curr_speaker_switch == *valp)
725 return 0;
726
727 snd_hda_power_up(codec);
728
729 err = chipio_read(codec, REG_CODEC_MUTE, &data);
730 if (err < 0)
b97f6bfd 731 goto exit;
95c6e9cb
IM		 732
733 /* *valp 0 is mute, 1 is unmute */
734 data = (data & 0xef) | (*valp ? 0 : 0x10);
b97f6bfd 735 err = chipio_write(codec, REG_CODEC_MUTE, data);
95c6e9cb 736 if (err < 0)
b97f6bfd 737 goto exit;
95c6e9cb
IM		 738
739 spec->curr_speaker_switch = *valp;
740
b97f6bfd 741 exit:
95c6e9cb 742 snd_hda_power_down(codec);
b97f6bfd 743 return err < 0 ? err : 1;
95c6e9cb
IM		 744}
745
746static int ca0132_hp_volume_get(struct snd_kcontrol *kcontrol,
747 struct snd_ctl_elem_value *ucontrol)
748{
749 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
750 struct ca0132_spec *spec = codec->spec;
751 long *valp = ucontrol->value.integer.value;
752
753 *valp++ = spec->curr_hp_volume[0];
754 *valp = spec->curr_hp_volume[1];
755 return 0;
756}
757
758static int ca0132_hp_volume_put(struct snd_kcontrol *kcontrol,
759 struct snd_ctl_elem_value *ucontrol)
760{
761 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
762 struct ca0132_spec *spec = codec->spec;
763 long *valp = ucontrol->value.integer.value;
764 long left_vol, right_vol;
765 unsigned int data;
766 int val;
767 int err;
768
769 left_vol = *valp++;
770 right_vol = *valp;
771
772 /* any change? */
773 if ((spec->curr_hp_volume[0] == left_vol) &&
774 (spec->curr_hp_volume[1] == right_vol))
775 return 0;
776
777 snd_hda_power_up(codec);
778
779 err = chipio_read(codec, REG_CODEC_HP_VOL_L, &data);
780 if (err < 0)
b97f6bfd 781 goto exit;
95c6e9cb
IM		 782
783 val = 31 - left_vol;
784 data = (data & 0xe0) | val;
b97f6bfd 785 err = chipio_write(codec, REG_CODEC_HP_VOL_L, data);
95c6e9cb 786 if (err < 0)
b97f6bfd 787 goto exit;
95c6e9cb
IM		 788
789 val = 31 - right_vol;
790 data = (data & 0xe0) | val;
b97f6bfd 791 err = chipio_write(codec, REG_CODEC_HP_VOL_R, data);
95c6e9cb 792 if (err < 0)
b97f6bfd 793 goto exit;
95c6e9cb
IM		 794
795 spec->curr_hp_volume[0] = left_vol;
796 spec->curr_hp_volume[1] = right_vol;
797
b97f6bfd 798 exit:
95c6e9cb 799 snd_hda_power_down(codec);
b97f6bfd 800 return err < 0 ? err : 1;
95c6e9cb
IM		 801}
802
803static int add_hp_switch(struct hda_codec *codec, hda_nid_t nid)
804{
805 struct snd_kcontrol_new knew =
806 HDA_CODEC_MUTE_MONO("Headphone Playback Switch",
807 nid, 1, 0, HDA_OUTPUT);
808 knew.get = ca0132_hp_switch_get;
809 knew.put = ca0132_hp_switch_put;
810 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
811}
812
813static int add_hp_volume(struct hda_codec *codec, hda_nid_t nid)
814{
815 struct snd_kcontrol_new knew =
816 HDA_CODEC_VOLUME_MONO("Headphone Playback Volume",
817 nid, 3, 0, HDA_OUTPUT);
818 knew.get = ca0132_hp_volume_get;
819 knew.put = ca0132_hp_volume_put;
820 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
821}
822
823static int add_speaker_switch(struct hda_codec *codec, hda_nid_t nid)
824{
825 struct snd_kcontrol_new knew =
826 HDA_CODEC_MUTE_MONO("Speaker Playback Switch",
827 nid, 1, 0, HDA_OUTPUT);
828 knew.get = ca0132_speaker_switch_get;
829 knew.put = ca0132_speaker_switch_put;
830 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
831}
832
833static void ca0132_fix_hp_caps(struct hda_codec *codec)
834{
835 struct ca0132_spec *spec = codec->spec;
836 struct auto_pin_cfg *cfg = &spec->autocfg;
837 unsigned int caps;
838
839 /* set mute-capable, 1db step, 32 steps, ofs 6 */
840 caps = 0x80031f06;
841 snd_hda_override_amp_caps(codec, cfg->hp_pins[0], HDA_OUTPUT, caps);
842}
843
844static int ca0132_build_controls(struct hda_codec *codec)
845{
846 struct ca0132_spec *spec = codec->spec;
847 struct auto_pin_cfg *cfg = &spec->autocfg;
848 int i, err;
849
850 if (spec->multiout.num_dacs) {
851 err = add_speaker_switch(codec, spec->out_pins[0]);
852 if (err < 0)
853 return err;
854 }
855
856 if (cfg->hp_outs) {
857 ca0132_fix_hp_caps(codec);
858 err = add_hp_switch(codec, cfg->hp_pins[0]);
859 if (err < 0)
860 return err;
861 err = add_hp_volume(codec, cfg->hp_pins[0]);
862 if (err < 0)
863 return err;
864 }
865
866 for (i = 0; i < spec->num_inputs; i++) {
867 const char *label = spec->input_labels[i];
868
869 err = add_in_switch(codec, spec->adcs[i], label);
870 if (err < 0)
871 return err;
872 err = add_in_volume(codec, spec->adcs[i], label);
873 if (err < 0)
874 return err;
875 if (cfg->inputs[i].type == AUTO_PIN_MIC) {
876 /* add Mic-Boost */
877 err = add_in_mono_volume(codec, spec->input_pins[i],
878 "Mic Boost", 1);
879 if (err < 0)
880 return err;
881 }
882 }
883
884 if (spec->dig_out) {
efb9f469
TI		 885 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
886 spec->dig_out);
95c6e9cb
IM		 887 if (err < 0)
888 return err;
8e13fc1c 889 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
95c6e9cb
IM		 890 if (err < 0)
891 return err;
8e13fc1c 892 /* spec->multiout.share_spdif = 1; */
95c6e9cb
IM		 893 }
894
895 if (spec->dig_in) {
896 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
897 if (err < 0)
898 return err;
95c6e9cb
IM		 899 }
900 return 0;
901}
902
903
904static void ca0132_set_ct_ext(struct hda_codec *codec, int enable)
905{
906 /* Set Creative extension */
907 snd_printdd("SET CREATIVE EXTENSION\n");
908 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
909 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE,
910 enable);
911 msleep(20);
912}
913
914
915static void ca0132_config(struct hda_codec *codec)
916{
917 struct ca0132_spec *spec = codec->spec;
918 struct auto_pin_cfg *cfg = &spec->autocfg;
919
27ebeb0b
TI		 920 codec->pcm_format_first = 1;
921 codec->no_sticky_stream = 1;
922
95c6e9cb
IM		 923 /* line-outs */
924 cfg->line_outs = 1;
925 cfg->line_out_pins[0] = 0x0b; /* front */
926 cfg->line_out_type = AUTO_PIN_LINE_OUT;
927
928 spec->dacs[0] = 0x02;
929 spec->out_pins[0] = 0x0b;
930 spec->multiout.dac_nids = spec->dacs;
931 spec->multiout.num_dacs = 1;
932 spec->multiout.max_channels = 2;
933
934 /* headphone */
935 cfg->hp_outs = 1;
936 cfg->hp_pins[0] = 0x0f;
937
938 spec->hp_dac = 0;
939 spec->multiout.hp_nid = 0;
940
941 /* inputs */
942 cfg->num_inputs = 2; /* Mic-in and line-in */
943 cfg->inputs[0].pin = 0x12;
944 cfg->inputs[0].type = AUTO_PIN_MIC;
945 cfg->inputs[1].pin = 0x11;
946 cfg->inputs[1].type = AUTO_PIN_LINE_IN;
947
948 /* Mic-in */
949 spec->input_pins[0] = 0x12;
55cf87fe 950 spec->input_labels[0] = "Mic";
95c6e9cb
IM		 951 spec->adcs[0] = 0x07;
952
953 /* Line-In */
954 spec->input_pins[1] = 0x11;
55cf87fe 955 spec->input_labels[1] = "Line";
95c6e9cb
IM		 956 spec->adcs[1] = 0x08;
957 spec->num_inputs = 2;
8e13fc1c
TI		 958
959 /* SPDIF I/O */
960 spec->dig_out = 0x05;
961 spec->multiout.dig_out_nid = spec->dig_out;
962 cfg->dig_out_pins[0] = 0x0c;
963 cfg->dig_outs = 1;
964 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
965 spec->dig_in = 0x09;
966 cfg->dig_in_pin = 0x0e;
967 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
95c6e9cb
IM		 968}
969
970static void ca0132_init_chip(struct hda_codec *codec)
971{
972 struct ca0132_spec *spec = codec->spec;
973
974 mutex_init(&spec->chipio_mutex);
975}
976
977static void ca0132_exit_chip(struct hda_codec *codec)
978{
979 /* put any chip cleanup stuffs here. */
980}
981
982static int ca0132_init(struct hda_codec *codec)
983{
984 struct ca0132_spec *spec = codec->spec;
985 struct auto_pin_cfg *cfg = &spec->autocfg;
986 int i;
987
988 for (i = 0; i < spec->multiout.num_dacs; i++) {
989 init_output(codec, spec->out_pins[i],
990 spec->multiout.dac_nids[i]);
991 }
992 init_output(codec, cfg->hp_pins[0], spec->hp_dac);
993 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
994
995 for (i = 0; i < spec->num_inputs; i++)
996 init_input(codec, spec->input_pins[i], spec->adcs[i]);
997
998 init_input(codec, cfg->dig_in_pin, spec->dig_in);
999
1000 ca0132_set_ct_ext(codec, 1);
1001
1002 return 0;
1003}
1004
1005
1006static void ca0132_free(struct hda_codec *codec)
1007{
1008 ca0132_set_ct_ext(codec, 0);
1009 ca0132_exit_chip(codec);
1010 kfree(codec->spec);
1011}
1012
1013static struct hda_codec_ops ca0132_patch_ops = {
1014 .build_controls = ca0132_build_controls,
1015 .build_pcms = ca0132_build_pcms,
1016 .init = ca0132_init,
1017 .free = ca0132_free,
1018};
1019
1020
1021
1022static int patch_ca0132(struct hda_codec *codec)
1023{
1024 struct ca0132_spec *spec;
1025
1026 snd_printdd("patch_ca0132\n");
1027
1028 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1029 if (!spec)
1030 return -ENOMEM;
1031 codec->spec = spec;
1032
1033 ca0132_init_chip(codec);
1034
1035 ca0132_config(codec);
1036
1037 codec->patch_ops = ca0132_patch_ops;
1038
1039 return 0;
1040}
1041
1042/*
1043 * patch entries
1044 */
1045static struct hda_codec_preset snd_hda_preset_ca0132[] = {
1046 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
1047 {} /* terminator */
1048};
1049
1050MODULE_ALIAS("snd-hda-codec-id:11020011");
1051
1052MODULE_LICENSE("GPL");
1053MODULE_DESCRIPTION("Creative CA0132, CA0132 HD-audio codec");
1054
1055static struct hda_codec_preset_list ca0132_list = {
1056 .preset = snd_hda_preset_ca0132,
1057 .owner = THIS_MODULE,
1058};
1059
1060static int __init patch_ca0132_init(void)
1061{
1062 return snd_hda_add_codec_preset(&ca0132_list);
1063}
1064
1065static void __exit patch_ca0132_exit(void)
1066{
1067 snd_hda_delete_codec_preset(&ca0132_list);
1068}
1069
1070module_init(patch_ca0132_init)
1071module_exit(patch_ca0132_exit)
Linux 6.x block layer and io_uring tree(s)