Commit | Line | Data |
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95c6e9cb IM |
1 | /* |
2 | * HD audio interface patch for Creative CA0132 chip | |
3 | * | |
4 | * Copyright (c) 2011, Creative Technology Ltd. | |
5 | * | |
6 | * Based on patch_ca0110.c | |
7 | * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> | |
8 | * | |
9 | * This driver is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This driver is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/slab.h> | |
95c6e9cb | 27 | #include <linux/mutex.h> |
da155d5b | 28 | #include <linux/module.h> |
4aa3bb0c | 29 | #include <linux/firmware.h> |
a9291f46 | 30 | #include <linux/kernel.h> |
aa31704f CM |
31 | #include <linux/types.h> |
32 | #include <linux/io.h> | |
33 | #include <linux/pci.h> | |
95c6e9cb IM |
34 | #include <sound/core.h> |
35 | #include "hda_codec.h" | |
36 | #include "hda_local.h" | |
128bc4ba | 37 | #include "hda_auto_parser.h" |
5aaca44d | 38 | #include "hda_jack.h" |
95c6e9cb | 39 | |
bcd109c0 IM |
40 | #include "ca0132_regs.h" |
41 | ||
ef6b2ead IM |
42 | /* Enable this to see controls for tuning purpose. */ |
43 | /*#define ENABLE_TUNING_CONTROLS*/ | |
44 | ||
8e142e9e TS |
45 | #ifdef ENABLE_TUNING_CONTROLS |
46 | #include <sound/tlv.h> | |
47 | #endif | |
48 | ||
ef6b2ead IM |
49 | #define FLOAT_ZERO 0x00000000 |
50 | #define FLOAT_ONE 0x3f800000 | |
51 | #define FLOAT_TWO 0x40000000 | |
38ba69ff | 52 | #define FLOAT_THREE 0x40400000 |
ef6b2ead IM |
53 | #define FLOAT_MINUS_5 0xc0a00000 |
54 | ||
ef6b2ead IM |
55 | #define UNSOL_TAG_DSP 0x16 |
56 | ||
4aa3bb0c IM |
57 | #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) |
58 | #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) | |
59 | ||
60 | #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 | |
61 | #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 | |
62 | #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 | |
63 | ||
64 | #define MASTERCONTROL 0x80 | |
ef6b2ead IM |
65 | #define MASTERCONTROL_ALLOC_DMA_CHAN 10 |
66 | #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 | |
4aa3bb0c | 67 | |
95c6e9cb IM |
68 | #define WIDGET_CHIP_CTRL 0x15 |
69 | #define WIDGET_DSP_CTRL 0x16 | |
70 | ||
4aa3bb0c IM |
71 | #define MEM_CONNID_MICIN1 3 |
72 | #define MEM_CONNID_MICIN2 5 | |
73 | #define MEM_CONNID_MICOUT1 12 | |
74 | #define MEM_CONNID_MICOUT2 14 | |
75 | #define MEM_CONNID_WUH 10 | |
76 | #define MEM_CONNID_DSP 16 | |
77 | #define MEM_CONNID_DMIC 100 | |
78 | ||
79 | #define SCP_SET 0 | |
80 | #define SCP_GET 1 | |
81 | ||
01ef7dbf | 82 | #define EFX_FILE "ctefx.bin" |
8a19bcee CM |
83 | #define SBZ_EFX_FILE "ctefx-sbz.bin" |
84 | #define R3DI_EFX_FILE "ctefx-r3di.bin" | |
01ef7dbf | 85 | |
24f3cede | 86 | #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP |
01ef7dbf | 87 | MODULE_FIRMWARE(EFX_FILE); |
8a19bcee CM |
88 | MODULE_FIRMWARE(SBZ_EFX_FILE); |
89 | MODULE_FIRMWARE(R3DI_EFX_FILE); | |
7a527ede | 90 | #endif |
01ef7dbf | 91 | |
8a19bcee | 92 | static const char *dirstr[2] = { "Playback", "Capture" }; |
ef6b2ead IM |
93 | |
94 | enum { | |
95 | SPEAKER_OUT, | |
96 | HEADPHONE_OUT | |
97 | }; | |
98 | ||
99 | enum { | |
100 | DIGITAL_MIC, | |
101 | LINE_MIC_IN | |
102 | }; | |
103 | ||
104 | enum { | |
105 | #define VNODE_START_NID 0x80 | |
106 | VNID_SPK = VNODE_START_NID, /* Speaker vnid */ | |
107 | VNID_MIC, | |
108 | VNID_HP_SEL, | |
109 | VNID_AMIC1_SEL, | |
110 | VNID_HP_ASEL, | |
111 | VNID_AMIC1_ASEL, | |
112 | VNODE_END_NID, | |
113 | #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) | |
114 | ||
115 | #define EFFECT_START_NID 0x90 | |
116 | #define OUT_EFFECT_START_NID EFFECT_START_NID | |
117 | SURROUND = OUT_EFFECT_START_NID, | |
118 | CRYSTALIZER, | |
119 | DIALOG_PLUS, | |
120 | SMART_VOLUME, | |
121 | X_BASS, | |
122 | EQUALIZER, | |
123 | OUT_EFFECT_END_NID, | |
124 | #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) | |
125 | ||
126 | #define IN_EFFECT_START_NID OUT_EFFECT_END_NID | |
127 | ECHO_CANCELLATION = IN_EFFECT_START_NID, | |
128 | VOICE_FOCUS, | |
129 | MIC_SVM, | |
130 | NOISE_REDUCTION, | |
131 | IN_EFFECT_END_NID, | |
132 | #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) | |
133 | ||
134 | VOICEFX = IN_EFFECT_END_NID, | |
135 | PLAY_ENHANCEMENT, | |
136 | CRYSTAL_VOICE, | |
137 | EFFECT_END_NID | |
138 | #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) | |
139 | }; | |
140 | ||
141 | /* Effects values size*/ | |
142 | #define EFFECT_VALS_MAX_COUNT 12 | |
143 | ||
e8412ca4 DR |
144 | /* Latency introduced by DSP blocks in milliseconds. */ |
145 | #define DSP_CAPTURE_INIT_LATENCY 0 | |
146 | #define DSP_CRYSTAL_VOICE_LATENCY 124 | |
147 | #define DSP_PLAYBACK_INIT_LATENCY 13 | |
148 | #define DSP_PLAY_ENHANCEMENT_LATENCY 30 | |
149 | #define DSP_SPEAKER_OUT_LATENCY 7 | |
150 | ||
ef6b2ead | 151 | struct ct_effect { |
975cc02a | 152 | char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; |
ef6b2ead IM |
153 | hda_nid_t nid; |
154 | int mid; /*effect module ID*/ | |
155 | int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ | |
156 | int direct; /* 0:output; 1:input*/ | |
157 | int params; /* number of default non-on/off params */ | |
158 | /*effect default values, 1st is on/off. */ | |
159 | unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; | |
160 | }; | |
161 | ||
162 | #define EFX_DIR_OUT 0 | |
163 | #define EFX_DIR_IN 1 | |
164 | ||
165 | static struct ct_effect ca0132_effects[EFFECTS_COUNT] = { | |
166 | { .name = "Surround", | |
167 | .nid = SURROUND, | |
168 | .mid = 0x96, | |
169 | .reqs = {0, 1}, | |
170 | .direct = EFX_DIR_OUT, | |
171 | .params = 1, | |
172 | .def_vals = {0x3F800000, 0x3F2B851F} | |
173 | }, | |
174 | { .name = "Crystalizer", | |
175 | .nid = CRYSTALIZER, | |
176 | .mid = 0x96, | |
177 | .reqs = {7, 8}, | |
178 | .direct = EFX_DIR_OUT, | |
179 | .params = 1, | |
180 | .def_vals = {0x3F800000, 0x3F266666} | |
181 | }, | |
182 | { .name = "Dialog Plus", | |
183 | .nid = DIALOG_PLUS, | |
184 | .mid = 0x96, | |
185 | .reqs = {2, 3}, | |
186 | .direct = EFX_DIR_OUT, | |
187 | .params = 1, | |
188 | .def_vals = {0x00000000, 0x3F000000} | |
189 | }, | |
190 | { .name = "Smart Volume", | |
191 | .nid = SMART_VOLUME, | |
192 | .mid = 0x96, | |
193 | .reqs = {4, 5, 6}, | |
194 | .direct = EFX_DIR_OUT, | |
195 | .params = 2, | |
196 | .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} | |
197 | }, | |
198 | { .name = "X-Bass", | |
199 | .nid = X_BASS, | |
200 | .mid = 0x96, | |
201 | .reqs = {24, 23, 25}, | |
202 | .direct = EFX_DIR_OUT, | |
203 | .params = 2, | |
204 | .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} | |
205 | }, | |
206 | { .name = "Equalizer", | |
207 | .nid = EQUALIZER, | |
208 | .mid = 0x96, | |
209 | .reqs = {9, 10, 11, 12, 13, 14, | |
210 | 15, 16, 17, 18, 19, 20}, | |
211 | .direct = EFX_DIR_OUT, | |
212 | .params = 11, | |
213 | .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, | |
214 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, | |
215 | 0x00000000, 0x00000000, 0x00000000, 0x00000000} | |
216 | }, | |
217 | { .name = "Echo Cancellation", | |
218 | .nid = ECHO_CANCELLATION, | |
219 | .mid = 0x95, | |
220 | .reqs = {0, 1, 2, 3}, | |
221 | .direct = EFX_DIR_IN, | |
222 | .params = 3, | |
223 | .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} | |
224 | }, | |
225 | { .name = "Voice Focus", | |
226 | .nid = VOICE_FOCUS, | |
227 | .mid = 0x95, | |
228 | .reqs = {6, 7, 8, 9}, | |
229 | .direct = EFX_DIR_IN, | |
230 | .params = 3, | |
231 | .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} | |
232 | }, | |
233 | { .name = "Mic SVM", | |
234 | .nid = MIC_SVM, | |
235 | .mid = 0x95, | |
236 | .reqs = {44, 45}, | |
237 | .direct = EFX_DIR_IN, | |
238 | .params = 1, | |
239 | .def_vals = {0x00000000, 0x3F3D70A4} | |
240 | }, | |
241 | { .name = "Noise Reduction", | |
242 | .nid = NOISE_REDUCTION, | |
243 | .mid = 0x95, | |
244 | .reqs = {4, 5}, | |
245 | .direct = EFX_DIR_IN, | |
246 | .params = 1, | |
247 | .def_vals = {0x3F800000, 0x3F000000} | |
248 | }, | |
249 | { .name = "VoiceFX", | |
250 | .nid = VOICEFX, | |
251 | .mid = 0x95, | |
252 | .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, | |
253 | .direct = EFX_DIR_IN, | |
254 | .params = 8, | |
255 | .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, | |
256 | 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, | |
257 | 0x00000000} | |
258 | } | |
259 | }; | |
260 | ||
261 | /* Tuning controls */ | |
262 | #ifdef ENABLE_TUNING_CONTROLS | |
263 | ||
264 | enum { | |
265 | #define TUNING_CTL_START_NID 0xC0 | |
266 | WEDGE_ANGLE = TUNING_CTL_START_NID, | |
267 | SVM_LEVEL, | |
268 | EQUALIZER_BAND_0, | |
269 | EQUALIZER_BAND_1, | |
270 | EQUALIZER_BAND_2, | |
271 | EQUALIZER_BAND_3, | |
272 | EQUALIZER_BAND_4, | |
273 | EQUALIZER_BAND_5, | |
274 | EQUALIZER_BAND_6, | |
275 | EQUALIZER_BAND_7, | |
276 | EQUALIZER_BAND_8, | |
277 | EQUALIZER_BAND_9, | |
278 | TUNING_CTL_END_NID | |
279 | #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) | |
280 | }; | |
281 | ||
282 | struct ct_tuning_ctl { | |
975cc02a | 283 | char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; |
ef6b2ead IM |
284 | hda_nid_t parent_nid; |
285 | hda_nid_t nid; | |
286 | int mid; /*effect module ID*/ | |
287 | int req; /*effect module request*/ | |
288 | int direct; /* 0:output; 1:input*/ | |
289 | unsigned int def_val;/*effect default values*/ | |
290 | }; | |
291 | ||
292 | static struct ct_tuning_ctl ca0132_tuning_ctls[] = { | |
293 | { .name = "Wedge Angle", | |
294 | .parent_nid = VOICE_FOCUS, | |
295 | .nid = WEDGE_ANGLE, | |
296 | .mid = 0x95, | |
297 | .req = 8, | |
298 | .direct = EFX_DIR_IN, | |
299 | .def_val = 0x41F00000 | |
300 | }, | |
301 | { .name = "SVM Level", | |
302 | .parent_nid = MIC_SVM, | |
303 | .nid = SVM_LEVEL, | |
304 | .mid = 0x95, | |
305 | .req = 45, | |
306 | .direct = EFX_DIR_IN, | |
307 | .def_val = 0x3F3D70A4 | |
308 | }, | |
309 | { .name = "EQ Band0", | |
310 | .parent_nid = EQUALIZER, | |
311 | .nid = EQUALIZER_BAND_0, | |
312 | .mid = 0x96, | |
313 | .req = 11, | |
314 | .direct = EFX_DIR_OUT, | |
315 | .def_val = 0x00000000 | |
316 | }, | |
317 | { .name = "EQ Band1", | |
318 | .parent_nid = EQUALIZER, | |
319 | .nid = EQUALIZER_BAND_1, | |
320 | .mid = 0x96, | |
321 | .req = 12, | |
322 | .direct = EFX_DIR_OUT, | |
323 | .def_val = 0x00000000 | |
324 | }, | |
325 | { .name = "EQ Band2", | |
326 | .parent_nid = EQUALIZER, | |
327 | .nid = EQUALIZER_BAND_2, | |
328 | .mid = 0x96, | |
329 | .req = 13, | |
330 | .direct = EFX_DIR_OUT, | |
331 | .def_val = 0x00000000 | |
332 | }, | |
333 | { .name = "EQ Band3", | |
334 | .parent_nid = EQUALIZER, | |
335 | .nid = EQUALIZER_BAND_3, | |
336 | .mid = 0x96, | |
337 | .req = 14, | |
338 | .direct = EFX_DIR_OUT, | |
339 | .def_val = 0x00000000 | |
340 | }, | |
341 | { .name = "EQ Band4", | |
342 | .parent_nid = EQUALIZER, | |
343 | .nid = EQUALIZER_BAND_4, | |
344 | .mid = 0x96, | |
345 | .req = 15, | |
346 | .direct = EFX_DIR_OUT, | |
347 | .def_val = 0x00000000 | |
348 | }, | |
349 | { .name = "EQ Band5", | |
350 | .parent_nid = EQUALIZER, | |
351 | .nid = EQUALIZER_BAND_5, | |
352 | .mid = 0x96, | |
353 | .req = 16, | |
354 | .direct = EFX_DIR_OUT, | |
355 | .def_val = 0x00000000 | |
356 | }, | |
357 | { .name = "EQ Band6", | |
358 | .parent_nid = EQUALIZER, | |
359 | .nid = EQUALIZER_BAND_6, | |
360 | .mid = 0x96, | |
361 | .req = 17, | |
362 | .direct = EFX_DIR_OUT, | |
363 | .def_val = 0x00000000 | |
364 | }, | |
365 | { .name = "EQ Band7", | |
366 | .parent_nid = EQUALIZER, | |
367 | .nid = EQUALIZER_BAND_7, | |
368 | .mid = 0x96, | |
369 | .req = 18, | |
370 | .direct = EFX_DIR_OUT, | |
371 | .def_val = 0x00000000 | |
372 | }, | |
373 | { .name = "EQ Band8", | |
374 | .parent_nid = EQUALIZER, | |
375 | .nid = EQUALIZER_BAND_8, | |
376 | .mid = 0x96, | |
377 | .req = 19, | |
378 | .direct = EFX_DIR_OUT, | |
379 | .def_val = 0x00000000 | |
380 | }, | |
381 | { .name = "EQ Band9", | |
382 | .parent_nid = EQUALIZER, | |
383 | .nid = EQUALIZER_BAND_9, | |
384 | .mid = 0x96, | |
385 | .req = 20, | |
386 | .direct = EFX_DIR_OUT, | |
387 | .def_val = 0x00000000 | |
388 | } | |
389 | }; | |
390 | #endif | |
391 | ||
392 | /* Voice FX Presets */ | |
393 | #define VOICEFX_MAX_PARAM_COUNT 9 | |
394 | ||
395 | struct ct_voicefx { | |
396 | char *name; | |
397 | hda_nid_t nid; | |
398 | int mid; | |
399 | int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ | |
400 | }; | |
401 | ||
402 | struct ct_voicefx_preset { | |
403 | char *name; /*preset name*/ | |
404 | unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; | |
405 | }; | |
406 | ||
ccd7bd3d | 407 | static struct ct_voicefx ca0132_voicefx = { |
ef6b2ead IM |
408 | .name = "VoiceFX Capture Switch", |
409 | .nid = VOICEFX, | |
410 | .mid = 0x95, | |
411 | .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} | |
412 | }; | |
413 | ||
ccd7bd3d | 414 | static struct ct_voicefx_preset ca0132_voicefx_presets[] = { |
ef6b2ead IM |
415 | { .name = "Neutral", |
416 | .vals = { 0x00000000, 0x43C80000, 0x44AF0000, | |
417 | 0x44FA0000, 0x3F800000, 0x3F800000, | |
418 | 0x3F800000, 0x00000000, 0x00000000 } | |
419 | }, | |
420 | { .name = "Female2Male", | |
421 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, | |
422 | 0x44FA0000, 0x3F19999A, 0x3F866666, | |
423 | 0x3F800000, 0x00000000, 0x00000000 } | |
424 | }, | |
425 | { .name = "Male2Female", | |
426 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, | |
427 | 0x450AC000, 0x4017AE14, 0x3F6B851F, | |
428 | 0x3F800000, 0x00000000, 0x00000000 } | |
429 | }, | |
430 | { .name = "ScrappyKid", | |
431 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, | |
432 | 0x44FA0000, 0x40400000, 0x3F28F5C3, | |
433 | 0x3F800000, 0x00000000, 0x00000000 } | |
434 | }, | |
435 | { .name = "Elderly", | |
436 | .vals = { 0x3F800000, 0x44324000, 0x44BB8000, | |
437 | 0x44E10000, 0x3FB33333, 0x3FB9999A, | |
438 | 0x3F800000, 0x3E3A2E43, 0x00000000 } | |
439 | }, | |
440 | { .name = "Orc", | |
441 | .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, | |
442 | 0x45098000, 0x3F266666, 0x3FC00000, | |
443 | 0x3F800000, 0x00000000, 0x00000000 } | |
444 | }, | |
445 | { .name = "Elf", | |
446 | .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, | |
447 | 0x45193000, 0x3F8E147B, 0x3F75C28F, | |
448 | 0x3F800000, 0x00000000, 0x00000000 } | |
449 | }, | |
450 | { .name = "Dwarf", | |
451 | .vals = { 0x3F800000, 0x43930000, 0x44BEE000, | |
452 | 0x45007000, 0x3F451EB8, 0x3F7851EC, | |
453 | 0x3F800000, 0x00000000, 0x00000000 } | |
454 | }, | |
455 | { .name = "AlienBrute", | |
456 | .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, | |
457 | 0x451F6000, 0x3F266666, 0x3FA7D945, | |
458 | 0x3F800000, 0x3CF5C28F, 0x00000000 } | |
459 | }, | |
460 | { .name = "Robot", | |
461 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, | |
462 | 0x44FA0000, 0x3FB2718B, 0x3F800000, | |
463 | 0xBC07010E, 0x00000000, 0x00000000 } | |
464 | }, | |
465 | { .name = "Marine", | |
466 | .vals = { 0x3F800000, 0x43C20000, 0x44906000, | |
467 | 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, | |
468 | 0x3F0A3D71, 0x00000000, 0x00000000 } | |
469 | }, | |
470 | { .name = "Emo", | |
471 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, | |
472 | 0x44FA0000, 0x3F800000, 0x3F800000, | |
473 | 0x3E4CCCCD, 0x00000000, 0x00000000 } | |
474 | }, | |
475 | { .name = "DeepVoice", | |
476 | .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, | |
477 | 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, | |
478 | 0x3F800000, 0x00000000, 0x00000000 } | |
479 | }, | |
480 | { .name = "Munchkin", | |
481 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, | |
482 | 0x44FA0000, 0x3F800000, 0x3F1A043C, | |
483 | 0x3F800000, 0x00000000, 0x00000000 } | |
484 | } | |
485 | }; | |
486 | ||
95c6e9cb IM |
487 | enum hda_cmd_vendor_io { |
488 | /* for DspIO node */ | |
489 | VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, | |
490 | VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, | |
491 | ||
492 | VENDOR_DSPIO_STATUS = 0xF01, | |
493 | VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, | |
494 | VENDOR_DSPIO_SCP_READ_DATA = 0xF02, | |
495 | VENDOR_DSPIO_DSP_INIT = 0x703, | |
496 | VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, | |
497 | VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, | |
498 | ||
499 | /* for ChipIO node */ | |
500 | VENDOR_CHIPIO_ADDRESS_LOW = 0x000, | |
501 | VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, | |
502 | VENDOR_CHIPIO_STREAM_FORMAT = 0x200, | |
503 | VENDOR_CHIPIO_DATA_LOW = 0x300, | |
504 | VENDOR_CHIPIO_DATA_HIGH = 0x400, | |
505 | ||
506 | VENDOR_CHIPIO_GET_PARAMETER = 0xF00, | |
507 | VENDOR_CHIPIO_STATUS = 0xF01, | |
508 | VENDOR_CHIPIO_HIC_POST_READ = 0x702, | |
509 | VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, | |
510 | ||
4aa3bb0c IM |
511 | VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, |
512 | VENDOR_CHIPIO_8051_DATA_READ = 0xF07, | |
513 | ||
95c6e9cb | 514 | VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, |
4aa3bb0c | 515 | VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, |
95c6e9cb IM |
516 | |
517 | VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, | |
518 | VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, | |
519 | VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, | |
520 | VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, | |
521 | VENDOR_CHIPIO_FLAG_SET = 0x70F, | |
522 | VENDOR_CHIPIO_FLAGS_GET = 0xF0F, | |
4aa3bb0c IM |
523 | VENDOR_CHIPIO_PARAM_SET = 0x710, |
524 | VENDOR_CHIPIO_PARAM_GET = 0xF10, | |
95c6e9cb IM |
525 | |
526 | VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, | |
527 | VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, | |
528 | VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, | |
529 | VENDOR_CHIPIO_PORT_FREE_SET = 0x713, | |
530 | ||
4aa3bb0c IM |
531 | VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, |
532 | VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, | |
533 | VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, | |
534 | VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, | |
535 | ||
536 | VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, | |
537 | VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, | |
538 | VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, | |
539 | VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, | |
540 | VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, | |
541 | VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, | |
542 | ||
543 | VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D | |
95c6e9cb IM |
544 | }; |
545 | ||
546 | /* | |
547 | * Control flag IDs | |
548 | */ | |
549 | enum control_flag_id { | |
550 | /* Connection manager stream setup is bypassed/enabled */ | |
551 | CONTROL_FLAG_C_MGR = 0, | |
552 | /* DSP DMA is bypassed/enabled */ | |
553 | CONTROL_FLAG_DMA = 1, | |
554 | /* 8051 'idle' mode is disabled/enabled */ | |
555 | CONTROL_FLAG_IDLE_ENABLE = 2, | |
556 | /* Tracker for the SPDIF-in path is bypassed/enabled */ | |
557 | CONTROL_FLAG_TRACKER = 3, | |
558 | /* DigitalOut to Spdif2Out connection is disabled/enabled */ | |
559 | CONTROL_FLAG_SPDIF2OUT = 4, | |
560 | /* Digital Microphone is disabled/enabled */ | |
561 | CONTROL_FLAG_DMIC = 5, | |
562 | /* ADC_B rate is 48 kHz/96 kHz */ | |
563 | CONTROL_FLAG_ADC_B_96KHZ = 6, | |
564 | /* ADC_C rate is 48 kHz/96 kHz */ | |
565 | CONTROL_FLAG_ADC_C_96KHZ = 7, | |
566 | /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ | |
567 | CONTROL_FLAG_DAC_96KHZ = 8, | |
568 | /* DSP rate is 48 kHz/96 kHz */ | |
569 | CONTROL_FLAG_DSP_96KHZ = 9, | |
570 | /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ | |
571 | CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, | |
572 | /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ | |
573 | CONTROL_FLAG_SRC_RATE_96KHZ = 11, | |
574 | /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ | |
575 | CONTROL_FLAG_DECODE_LOOP = 12, | |
576 | /* De-emphasis filter on DAC-1 disabled/enabled */ | |
577 | CONTROL_FLAG_DAC1_DEEMPHASIS = 13, | |
578 | /* De-emphasis filter on DAC-2 disabled/enabled */ | |
579 | CONTROL_FLAG_DAC2_DEEMPHASIS = 14, | |
580 | /* De-emphasis filter on DAC-3 disabled/enabled */ | |
581 | CONTROL_FLAG_DAC3_DEEMPHASIS = 15, | |
582 | /* High-pass filter on ADC_B disabled/enabled */ | |
583 | CONTROL_FLAG_ADC_B_HIGH_PASS = 16, | |
584 | /* High-pass filter on ADC_C disabled/enabled */ | |
585 | CONTROL_FLAG_ADC_C_HIGH_PASS = 17, | |
586 | /* Common mode on Port_A disabled/enabled */ | |
587 | CONTROL_FLAG_PORT_A_COMMON_MODE = 18, | |
588 | /* Common mode on Port_D disabled/enabled */ | |
589 | CONTROL_FLAG_PORT_D_COMMON_MODE = 19, | |
590 | /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ | |
591 | CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, | |
592 | /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ | |
4aa3bb0c | 593 | CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, |
95c6e9cb IM |
594 | /* ASI rate is 48kHz/96kHz */ |
595 | CONTROL_FLAG_ASI_96KHZ = 22, | |
596 | /* DAC power settings able to control attached ports no/yes */ | |
597 | CONTROL_FLAG_DACS_CONTROL_PORTS = 23, | |
598 | /* Clock Stop OK reporting is disabled/enabled */ | |
599 | CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, | |
600 | /* Number of control flags */ | |
601 | CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) | |
602 | }; | |
603 | ||
604 | /* | |
605 | * Control parameter IDs | |
606 | */ | |
4aa3bb0c | 607 | enum control_param_id { |
ef6b2ead IM |
608 | /* 0: None, 1: Mic1In*/ |
609 | CONTROL_PARAM_VIP_SOURCE = 1, | |
95c6e9cb IM |
610 | /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ |
611 | CONTROL_PARAM_SPDIF1_SOURCE = 2, | |
ef6b2ead IM |
612 | /* Port A output stage gain setting to use when 16 Ohm output |
613 | * impedance is selected*/ | |
614 | CONTROL_PARAM_PORTA_160OHM_GAIN = 8, | |
615 | /* Port D output stage gain setting to use when 16 Ohm output | |
616 | * impedance is selected*/ | |
617 | CONTROL_PARAM_PORTD_160OHM_GAIN = 10, | |
95c6e9cb IM |
618 | |
619 | /* Stream Control */ | |
620 | ||
621 | /* Select stream with the given ID */ | |
622 | CONTROL_PARAM_STREAM_ID = 24, | |
623 | /* Source connection point for the selected stream */ | |
624 | CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, | |
625 | /* Destination connection point for the selected stream */ | |
626 | CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, | |
627 | /* Number of audio channels in the selected stream */ | |
628 | CONTROL_PARAM_STREAMS_CHANNELS = 27, | |
629 | /*Enable control for the selected stream */ | |
630 | CONTROL_PARAM_STREAM_CONTROL = 28, | |
631 | ||
632 | /* Connection Point Control */ | |
633 | ||
634 | /* Select connection point with the given ID */ | |
635 | CONTROL_PARAM_CONN_POINT_ID = 29, | |
636 | /* Connection point sample rate */ | |
637 | CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, | |
638 | ||
639 | /* Node Control */ | |
640 | ||
641 | /* Select HDA node with the given ID */ | |
642 | CONTROL_PARAM_NODE_ID = 31 | |
643 | }; | |
644 | ||
645 | /* | |
646 | * Dsp Io Status codes | |
647 | */ | |
648 | enum hda_vendor_status_dspio { | |
649 | /* Success */ | |
650 | VENDOR_STATUS_DSPIO_OK = 0x00, | |
651 | /* Busy, unable to accept new command, the host must retry */ | |
652 | VENDOR_STATUS_DSPIO_BUSY = 0x01, | |
653 | /* SCP command queue is full */ | |
654 | VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, | |
655 | /* SCP response queue is empty */ | |
656 | VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 | |
657 | }; | |
658 | ||
659 | /* | |
660 | * Chip Io Status codes | |
661 | */ | |
662 | enum hda_vendor_status_chipio { | |
663 | /* Success */ | |
664 | VENDOR_STATUS_CHIPIO_OK = 0x00, | |
665 | /* Busy, unable to accept new command, the host must retry */ | |
666 | VENDOR_STATUS_CHIPIO_BUSY = 0x01 | |
667 | }; | |
668 | ||
669 | /* | |
670 | * CA0132 sample rate | |
671 | */ | |
672 | enum ca0132_sample_rate { | |
673 | SR_6_000 = 0x00, | |
674 | SR_8_000 = 0x01, | |
675 | SR_9_600 = 0x02, | |
676 | SR_11_025 = 0x03, | |
677 | SR_16_000 = 0x04, | |
678 | SR_22_050 = 0x05, | |
679 | SR_24_000 = 0x06, | |
680 | SR_32_000 = 0x07, | |
681 | SR_44_100 = 0x08, | |
682 | SR_48_000 = 0x09, | |
683 | SR_88_200 = 0x0A, | |
684 | SR_96_000 = 0x0B, | |
685 | SR_144_000 = 0x0C, | |
686 | SR_176_400 = 0x0D, | |
687 | SR_192_000 = 0x0E, | |
688 | SR_384_000 = 0x0F, | |
689 | ||
690 | SR_COUNT = 0x10, | |
691 | ||
692 | SR_RATE_UNKNOWN = 0x1F | |
693 | }; | |
694 | ||
01ef7dbf IM |
695 | enum dsp_download_state { |
696 | DSP_DOWNLOAD_FAILED = -1, | |
697 | DSP_DOWNLOAD_INIT = 0, | |
698 | DSP_DOWNLOADING = 1, | |
699 | DSP_DOWNLOADED = 2 | |
700 | }; | |
701 | ||
01ef7dbf IM |
702 | /* retrieve parameters from hda format */ |
703 | #define get_hdafmt_chs(fmt) (fmt & 0xf) | |
704 | #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) | |
705 | #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) | |
706 | #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) | |
707 | ||
708 | /* | |
709 | * CA0132 specific | |
710 | */ | |
711 | ||
712 | struct ca0132_spec { | |
a7e76271 IM |
713 | struct snd_kcontrol_new *mixers[5]; |
714 | unsigned int num_mixers; | |
5aaca44d IM |
715 | const struct hda_verb *base_init_verbs; |
716 | const struct hda_verb *base_exit_verbs; | |
d5c016b5 | 717 | const struct hda_verb *chip_init_verbs; |
e93ac30a | 718 | const struct hda_verb *sbz_init_verbs; |
d5c016b5 | 719 | struct hda_verb *spec_init_verbs; |
01ef7dbf | 720 | struct auto_pin_cfg autocfg; |
5aaca44d IM |
721 | |
722 | /* Nodes configurations */ | |
01ef7dbf IM |
723 | struct hda_multi_out multiout; |
724 | hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; | |
725 | hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; | |
5aaca44d | 726 | unsigned int num_outputs; |
01ef7dbf IM |
727 | hda_nid_t input_pins[AUTO_PIN_LAST]; |
728 | hda_nid_t adcs[AUTO_PIN_LAST]; | |
729 | hda_nid_t dig_out; | |
730 | hda_nid_t dig_in; | |
731 | unsigned int num_inputs; | |
a7e76271 IM |
732 | hda_nid_t shared_mic_nid; |
733 | hda_nid_t shared_out_nid; | |
d5c016b5 | 734 | hda_nid_t unsol_tag_hp; |
63177afc | 735 | hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ |
d5c016b5 | 736 | hda_nid_t unsol_tag_amic1; |
01ef7dbf IM |
737 | |
738 | /* chip access */ | |
739 | struct mutex chipio_mutex; /* chip access mutex */ | |
740 | u32 curr_chip_addx; | |
741 | ||
742 | /* DSP download related */ | |
743 | enum dsp_download_state dsp_state; | |
744 | unsigned int dsp_stream_id; | |
745 | unsigned int wait_scp; | |
746 | unsigned int wait_scp_header; | |
747 | unsigned int wait_num_data; | |
748 | unsigned int scp_resp_header; | |
749 | unsigned int scp_resp_data[4]; | |
750 | unsigned int scp_resp_count; | |
8a19bcee | 751 | bool alt_firmware_present; |
38ba69ff | 752 | bool startup_check_entered; |
e93ac30a | 753 | bool dsp_reload; |
5aaca44d IM |
754 | |
755 | /* mixer and effects related */ | |
756 | unsigned char dmic_ctl; | |
757 | int cur_out_type; | |
758 | int cur_mic_type; | |
759 | long vnode_lvol[VNODES_COUNT]; | |
760 | long vnode_rvol[VNODES_COUNT]; | |
761 | long vnode_lswitch[VNODES_COUNT]; | |
762 | long vnode_rswitch[VNODES_COUNT]; | |
763 | long effects_switch[EFFECTS_COUNT]; | |
764 | long voicefx_val; | |
765 | long cur_mic_boost; | |
44f0c978 | 766 | |
993884f6 CCC |
767 | struct hda_codec *codec; |
768 | struct delayed_work unsol_hp_work; | |
d5c016b5 | 769 | int quirk; |
993884f6 | 770 | |
44f0c978 IM |
771 | #ifdef ENABLE_TUNING_CONTROLS |
772 | long cur_ctl_vals[TUNING_CTLS_COUNT]; | |
773 | #endif | |
aa31704f CM |
774 | /* |
775 | * Sound Blaster Z PCI region 2 iomem, used for input and output | |
776 | * switching, and other unknown commands. | |
777 | */ | |
778 | void __iomem *mem_base; | |
009b8f97 CM |
779 | |
780 | /* | |
781 | * Whether or not to use the alt functions like alt_select_out, | |
782 | * alt_select_in, etc. Only used on desktop codecs for now, because of | |
783 | * surround sound support. | |
784 | */ | |
785 | bool use_alt_functions; | |
01ef7dbf IM |
786 | }; |
787 | ||
d5c016b5 GM |
788 | /* |
789 | * CA0132 quirks table | |
790 | */ | |
791 | enum { | |
792 | QUIRK_NONE, | |
793 | QUIRK_ALIENWARE, | |
8a19bcee CM |
794 | QUIRK_SBZ, |
795 | QUIRK_R3DI, | |
d5c016b5 GM |
796 | }; |
797 | ||
fe14f39e TI |
798 | static const struct hda_pintbl alienware_pincfgs[] = { |
799 | { 0x0b, 0x90170110 }, /* Builtin Speaker */ | |
800 | { 0x0c, 0x411111f0 }, /* N/A */ | |
801 | { 0x0d, 0x411111f0 }, /* N/A */ | |
802 | { 0x0e, 0x411111f0 }, /* N/A */ | |
803 | { 0x0f, 0x0321101f }, /* HP */ | |
804 | { 0x10, 0x411111f0 }, /* Headset? disabled for now */ | |
805 | { 0x11, 0x03a11021 }, /* Mic */ | |
806 | { 0x12, 0xd5a30140 }, /* Builtin Mic */ | |
807 | { 0x13, 0x411111f0 }, /* N/A */ | |
808 | { 0x18, 0x411111f0 }, /* N/A */ | |
809 | {} | |
810 | }; | |
811 | ||
63177afc CM |
812 | /* Sound Blaster Z pin configs taken from Windows Driver */ |
813 | static const struct hda_pintbl sbz_pincfgs[] = { | |
814 | { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ | |
815 | { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ | |
816 | { 0x0d, 0x014510f0 }, /* Digital Out */ | |
817 | { 0x0e, 0x01c510f0 }, /* SPDIF In */ | |
818 | { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ | |
819 | { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ | |
820 | { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ | |
821 | { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ | |
822 | { 0x13, 0x908700f0 }, /* What U Hear In*/ | |
823 | { 0x18, 0x50d000f0 }, /* N/A */ | |
824 | {} | |
825 | }; | |
826 | ||
827 | /* Recon3D integrated pin configs taken from Windows Driver */ | |
828 | static const struct hda_pintbl r3di_pincfgs[] = { | |
829 | { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ | |
830 | { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ | |
831 | { 0x0d, 0x014510f0 }, /* Digital Out */ | |
832 | { 0x0e, 0x41c520f0 }, /* SPDIF In */ | |
833 | { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ | |
834 | { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ | |
835 | { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ | |
836 | { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ | |
837 | { 0x13, 0x908700f0 }, /* What U Hear In*/ | |
838 | { 0x18, 0x500000f0 }, /* N/A */ | |
839 | {} | |
840 | }; | |
841 | ||
d5c016b5 | 842 | static const struct snd_pci_quirk ca0132_quirks[] = { |
5328e1ea GM |
843 | SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), |
844 | SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), | |
b5337cfe | 845 | SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), |
8a19bcee CM |
846 | SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), |
847 | SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), | |
848 | SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), | |
849 | SND_PCI_QUIRK(0x1458, 0xA036, "Recon3Di", QUIRK_R3DI), | |
d5c016b5 GM |
850 | {} |
851 | }; | |
852 | ||
01ef7dbf IM |
853 | /* |
854 | * CA0132 codec access | |
855 | */ | |
399ae725 | 856 | static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, |
01ef7dbf IM |
857 | unsigned int verb, unsigned int parm, unsigned int *res) |
858 | { | |
859 | unsigned int response; | |
860 | response = snd_hda_codec_read(codec, nid, 0, verb, parm); | |
861 | *res = response; | |
862 | ||
863 | return ((response == -1) ? -1 : 0); | |
864 | } | |
865 | ||
866 | static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, | |
867 | unsigned short converter_format, unsigned int *res) | |
868 | { | |
869 | return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, | |
870 | converter_format & 0xffff, res); | |
871 | } | |
872 | ||
873 | static int codec_set_converter_stream_channel(struct hda_codec *codec, | |
874 | hda_nid_t nid, unsigned char stream, | |
875 | unsigned char channel, unsigned int *res) | |
876 | { | |
877 | unsigned char converter_stream_channel = 0; | |
878 | ||
879 | converter_stream_channel = (stream << 4) | (channel & 0x0f); | |
880 | return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, | |
881 | converter_stream_channel, res); | |
882 | } | |
883 | ||
884 | /* Chip access helper function */ | |
885 | static int chipio_send(struct hda_codec *codec, | |
886 | unsigned int reg, | |
887 | unsigned int data) | |
888 | { | |
889 | unsigned int res; | |
6d67530e | 890 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
01ef7dbf IM |
891 | |
892 | /* send bits of data specified by reg */ | |
893 | do { | |
894 | res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, | |
895 | reg, data); | |
896 | if (res == VENDOR_STATUS_CHIPIO_OK) | |
897 | return 0; | |
6d67530e IM |
898 | msleep(20); |
899 | } while (time_before(jiffies, timeout)); | |
900 | ||
01ef7dbf IM |
901 | return -EIO; |
902 | } | |
903 | ||
904 | /* | |
905 | * Write chip address through the vendor widget -- NOT protected by the Mutex! | |
906 | */ | |
907 | static int chipio_write_address(struct hda_codec *codec, | |
908 | unsigned int chip_addx) | |
909 | { | |
4861af80 | 910 | struct ca0132_spec *spec = codec->spec; |
01ef7dbf IM |
911 | int res; |
912 | ||
4861af80 IM |
913 | if (spec->curr_chip_addx == chip_addx) |
914 | return 0; | |
915 | ||
01ef7dbf IM |
916 | /* send low 16 bits of the address */ |
917 | res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, | |
918 | chip_addx & 0xffff); | |
919 | ||
920 | if (res != -EIO) { | |
921 | /* send high 16 bits of the address */ | |
922 | res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, | |
923 | chip_addx >> 16); | |
924 | } | |
925 | ||
d1600401 | 926 | spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; |
01ef7dbf | 927 | |
4861af80 | 928 | return res; |
01ef7dbf IM |
929 | } |
930 | ||
931 | /* | |
932 | * Write data through the vendor widget -- NOT protected by the Mutex! | |
933 | */ | |
01ef7dbf IM |
934 | static int chipio_write_data(struct hda_codec *codec, unsigned int data) |
935 | { | |
5aaca44d | 936 | struct ca0132_spec *spec = codec->spec; |
01ef7dbf IM |
937 | int res; |
938 | ||
939 | /* send low 16 bits of the data */ | |
940 | res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); | |
941 | ||
942 | if (res != -EIO) { | |
943 | /* send high 16 bits of the data */ | |
944 | res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, | |
945 | data >> 16); | |
946 | } | |
947 | ||
5aaca44d IM |
948 | /*If no error encountered, automatically increment the address |
949 | as per chip behaviour*/ | |
950 | spec->curr_chip_addx = (res != -EIO) ? | |
d1600401 | 951 | (spec->curr_chip_addx + 4) : ~0U; |
01ef7dbf IM |
952 | return res; |
953 | } | |
954 | ||
d5c21b88 IM |
955 | /* |
956 | * Write multiple data through the vendor widget -- NOT protected by the Mutex! | |
957 | */ | |
01ef7dbf IM |
958 | static int chipio_write_data_multiple(struct hda_codec *codec, |
959 | const u32 *data, | |
960 | unsigned int count) | |
961 | { | |
962 | int status = 0; | |
963 | ||
964 | if (data == NULL) { | |
4e76a883 | 965 | codec_dbg(codec, "chipio_write_data null ptr\n"); |
01ef7dbf IM |
966 | return -EINVAL; |
967 | } | |
968 | ||
969 | while ((count-- != 0) && (status == 0)) | |
970 | status = chipio_write_data(codec, *data++); | |
971 | ||
972 | return status; | |
973 | } | |
974 | ||
975 | ||
976 | /* | |
977 | * Read data through the vendor widget -- NOT protected by the Mutex! | |
978 | */ | |
979 | static int chipio_read_data(struct hda_codec *codec, unsigned int *data) | |
980 | { | |
5aaca44d | 981 | struct ca0132_spec *spec = codec->spec; |
01ef7dbf IM |
982 | int res; |
983 | ||
984 | /* post read */ | |
985 | res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); | |
986 | ||
987 | if (res != -EIO) { | |
988 | /* read status */ | |
989 | res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); | |
990 | } | |
991 | ||
992 | if (res != -EIO) { | |
993 | /* read data */ | |
994 | *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, | |
995 | VENDOR_CHIPIO_HIC_READ_DATA, | |
996 | 0); | |
997 | } | |
998 | ||
5aaca44d IM |
999 | /*If no error encountered, automatically increment the address |
1000 | as per chip behaviour*/ | |
1001 | spec->curr_chip_addx = (res != -EIO) ? | |
d1600401 | 1002 | (spec->curr_chip_addx + 4) : ~0U; |
01ef7dbf IM |
1003 | return res; |
1004 | } | |
1005 | ||
1006 | /* | |
1007 | * Write given value to the given address through the chip I/O widget. | |
1008 | * protected by the Mutex | |
1009 | */ | |
1010 | static int chipio_write(struct hda_codec *codec, | |
1011 | unsigned int chip_addx, const unsigned int data) | |
1012 | { | |
1013 | struct ca0132_spec *spec = codec->spec; | |
1014 | int err; | |
1015 | ||
1016 | mutex_lock(&spec->chipio_mutex); | |
1017 | ||
1018 | /* write the address, and if successful proceed to write data */ | |
1019 | err = chipio_write_address(codec, chip_addx); | |
1020 | if (err < 0) | |
1021 | goto exit; | |
1022 | ||
1023 | err = chipio_write_data(codec, data); | |
1024 | if (err < 0) | |
1025 | goto exit; | |
1026 | ||
1027 | exit: | |
1028 | mutex_unlock(&spec->chipio_mutex); | |
1029 | return err; | |
1030 | } | |
1031 | ||
38ba69ff CM |
1032 | /* |
1033 | * Write given value to the given address through the chip I/O widget. | |
1034 | * not protected by the Mutex | |
1035 | */ | |
1036 | static int chipio_write_no_mutex(struct hda_codec *codec, | |
1037 | unsigned int chip_addx, const unsigned int data) | |
1038 | { | |
1039 | int err; | |
1040 | ||
1041 | ||
1042 | /* write the address, and if successful proceed to write data */ | |
1043 | err = chipio_write_address(codec, chip_addx); | |
1044 | if (err < 0) | |
1045 | goto exit; | |
1046 | ||
1047 | err = chipio_write_data(codec, data); | |
1048 | if (err < 0) | |
1049 | goto exit; | |
1050 | ||
1051 | exit: | |
1052 | return err; | |
1053 | } | |
1054 | ||
d5c21b88 IM |
1055 | /* |
1056 | * Write multiple values to the given address through the chip I/O widget. | |
1057 | * protected by the Mutex | |
1058 | */ | |
01ef7dbf IM |
1059 | static int chipio_write_multiple(struct hda_codec *codec, |
1060 | u32 chip_addx, | |
1061 | const u32 *data, | |
1062 | unsigned int count) | |
1063 | { | |
1064 | struct ca0132_spec *spec = codec->spec; | |
1065 | int status; | |
1066 | ||
1067 | mutex_lock(&spec->chipio_mutex); | |
4861af80 | 1068 | status = chipio_write_address(codec, chip_addx); |
01ef7dbf IM |
1069 | if (status < 0) |
1070 | goto error; | |
1071 | ||
1072 | status = chipio_write_data_multiple(codec, data, count); | |
1073 | error: | |
1074 | mutex_unlock(&spec->chipio_mutex); | |
1075 | ||
1076 | return status; | |
1077 | } | |
1078 | ||
1079 | /* | |
1080 | * Read the given address through the chip I/O widget | |
1081 | * protected by the Mutex | |
1082 | */ | |
1083 | static int chipio_read(struct hda_codec *codec, | |
1084 | unsigned int chip_addx, unsigned int *data) | |
1085 | { | |
1086 | struct ca0132_spec *spec = codec->spec; | |
1087 | int err; | |
1088 | ||
1089 | mutex_lock(&spec->chipio_mutex); | |
1090 | ||
1091 | /* write the address, and if successful proceed to write data */ | |
1092 | err = chipio_write_address(codec, chip_addx); | |
1093 | if (err < 0) | |
1094 | goto exit; | |
1095 | ||
1096 | err = chipio_read_data(codec, data); | |
1097 | if (err < 0) | |
1098 | goto exit; | |
1099 | ||
1100 | exit: | |
1101 | mutex_unlock(&spec->chipio_mutex); | |
1102 | return err; | |
1103 | } | |
1104 | ||
d5c21b88 IM |
1105 | /* |
1106 | * Set chip control flags through the chip I/O widget. | |
1107 | */ | |
01ef7dbf IM |
1108 | static void chipio_set_control_flag(struct hda_codec *codec, |
1109 | enum control_flag_id flag_id, | |
1110 | bool flag_state) | |
1111 | { | |
1112 | unsigned int val; | |
1113 | unsigned int flag_bit; | |
1114 | ||
1115 | flag_bit = (flag_state ? 1 : 0); | |
1116 | val = (flag_bit << 7) | (flag_id); | |
1117 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1118 | VENDOR_CHIPIO_FLAG_SET, val); | |
1119 | } | |
1120 | ||
d5c21b88 IM |
1121 | /* |
1122 | * Set chip parameters through the chip I/O widget. | |
1123 | */ | |
01ef7dbf IM |
1124 | static void chipio_set_control_param(struct hda_codec *codec, |
1125 | enum control_param_id param_id, int param_val) | |
1126 | { | |
1127 | struct ca0132_spec *spec = codec->spec; | |
1128 | int val; | |
1129 | ||
1130 | if ((param_id < 32) && (param_val < 8)) { | |
1131 | val = (param_val << 5) | (param_id); | |
1132 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1133 | VENDOR_CHIPIO_PARAM_SET, val); | |
1134 | } else { | |
1135 | mutex_lock(&spec->chipio_mutex); | |
1136 | if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { | |
1137 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1138 | VENDOR_CHIPIO_PARAM_EX_ID_SET, | |
1139 | param_id); | |
1140 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1141 | VENDOR_CHIPIO_PARAM_EX_VALUE_SET, | |
1142 | param_val); | |
1143 | } | |
1144 | mutex_unlock(&spec->chipio_mutex); | |
1145 | } | |
1146 | } | |
1147 | ||
009b8f97 CM |
1148 | /* |
1149 | * Set chip parameters through the chip I/O widget. NO MUTEX. | |
1150 | */ | |
1151 | static void chipio_set_control_param_no_mutex(struct hda_codec *codec, | |
1152 | enum control_param_id param_id, int param_val) | |
1153 | { | |
1154 | int val; | |
1155 | ||
1156 | if ((param_id < 32) && (param_val < 8)) { | |
1157 | val = (param_val << 5) | (param_id); | |
1158 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1159 | VENDOR_CHIPIO_PARAM_SET, val); | |
1160 | } else { | |
1161 | if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { | |
1162 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1163 | VENDOR_CHIPIO_PARAM_EX_ID_SET, | |
1164 | param_id); | |
1165 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1166 | VENDOR_CHIPIO_PARAM_EX_VALUE_SET, | |
1167 | param_val); | |
1168 | } | |
1169 | } | |
1170 | } | |
38ba69ff CM |
1171 | /* |
1172 | * Connect stream to a source point, and then connect | |
1173 | * that source point to a destination point. | |
1174 | */ | |
1175 | static void chipio_set_stream_source_dest(struct hda_codec *codec, | |
1176 | int streamid, int source_point, int dest_point) | |
1177 | { | |
1178 | chipio_set_control_param_no_mutex(codec, | |
1179 | CONTROL_PARAM_STREAM_ID, streamid); | |
1180 | chipio_set_control_param_no_mutex(codec, | |
1181 | CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); | |
1182 | chipio_set_control_param_no_mutex(codec, | |
1183 | CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); | |
1184 | } | |
1185 | ||
1186 | /* | |
1187 | * Set number of channels in the selected stream. | |
1188 | */ | |
1189 | static void chipio_set_stream_channels(struct hda_codec *codec, | |
1190 | int streamid, unsigned int channels) | |
1191 | { | |
1192 | chipio_set_control_param_no_mutex(codec, | |
1193 | CONTROL_PARAM_STREAM_ID, streamid); | |
1194 | chipio_set_control_param_no_mutex(codec, | |
1195 | CONTROL_PARAM_STREAMS_CHANNELS, channels); | |
1196 | } | |
009b8f97 CM |
1197 | |
1198 | /* | |
1199 | * Enable/Disable audio stream. | |
1200 | */ | |
1201 | static void chipio_set_stream_control(struct hda_codec *codec, | |
1202 | int streamid, int enable) | |
1203 | { | |
1204 | chipio_set_control_param_no_mutex(codec, | |
1205 | CONTROL_PARAM_STREAM_ID, streamid); | |
1206 | chipio_set_control_param_no_mutex(codec, | |
1207 | CONTROL_PARAM_STREAM_CONTROL, enable); | |
1208 | } | |
1209 | ||
38ba69ff CM |
1210 | |
1211 | /* | |
1212 | * Set sampling rate of the connection point. NO MUTEX. | |
1213 | */ | |
1214 | static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, | |
1215 | int connid, enum ca0132_sample_rate rate) | |
1216 | { | |
1217 | chipio_set_control_param_no_mutex(codec, | |
1218 | CONTROL_PARAM_CONN_POINT_ID, connid); | |
1219 | chipio_set_control_param_no_mutex(codec, | |
1220 | CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); | |
1221 | } | |
1222 | ||
d5c21b88 IM |
1223 | /* |
1224 | * Set sampling rate of the connection point. | |
1225 | */ | |
01ef7dbf IM |
1226 | static void chipio_set_conn_rate(struct hda_codec *codec, |
1227 | int connid, enum ca0132_sample_rate rate) | |
1228 | { | |
1229 | chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); | |
1230 | chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, | |
1231 | rate); | |
1232 | } | |
1233 | ||
d5c21b88 IM |
1234 | /* |
1235 | * Enable clocks. | |
1236 | */ | |
01ef7dbf IM |
1237 | static void chipio_enable_clocks(struct hda_codec *codec) |
1238 | { | |
1239 | struct ca0132_spec *spec = codec->spec; | |
1240 | ||
1241 | mutex_lock(&spec->chipio_mutex); | |
1242 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1243 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); | |
1244 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1245 | VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); | |
1246 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1247 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); | |
1248 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1249 | VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); | |
1250 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1251 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); | |
1252 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
1253 | VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); | |
1254 | mutex_unlock(&spec->chipio_mutex); | |
1255 | } | |
1256 | ||
1257 | /* | |
1258 | * CA0132 DSP IO stuffs | |
1259 | */ | |
1260 | static int dspio_send(struct hda_codec *codec, unsigned int reg, | |
1261 | unsigned int data) | |
1262 | { | |
b645d796 | 1263 | int res; |
6d67530e | 1264 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
01ef7dbf IM |
1265 | |
1266 | /* send bits of data specified by reg to dsp */ | |
1267 | do { | |
1268 | res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); | |
1269 | if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) | |
1270 | return res; | |
6d67530e IM |
1271 | msleep(20); |
1272 | } while (time_before(jiffies, timeout)); | |
01ef7dbf IM |
1273 | |
1274 | return -EIO; | |
1275 | } | |
1276 | ||
d5c21b88 IM |
1277 | /* |
1278 | * Wait for DSP to be ready for commands | |
1279 | */ | |
01ef7dbf IM |
1280 | static void dspio_write_wait(struct hda_codec *codec) |
1281 | { | |
4861af80 IM |
1282 | int status; |
1283 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); | |
01ef7dbf | 1284 | |
01ef7dbf | 1285 | do { |
4861af80 IM |
1286 | status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, |
1287 | VENDOR_DSPIO_STATUS, 0); | |
1288 | if ((status == VENDOR_STATUS_DSPIO_OK) || | |
1289 | (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) | |
1290 | break; | |
1291 | msleep(1); | |
1292 | } while (time_before(jiffies, timeout)); | |
01ef7dbf IM |
1293 | } |
1294 | ||
d5c21b88 IM |
1295 | /* |
1296 | * Write SCP data to DSP | |
1297 | */ | |
01ef7dbf IM |
1298 | static int dspio_write(struct hda_codec *codec, unsigned int scp_data) |
1299 | { | |
1300 | struct ca0132_spec *spec = codec->spec; | |
1301 | int status; | |
1302 | ||
1303 | dspio_write_wait(codec); | |
1304 | ||
1305 | mutex_lock(&spec->chipio_mutex); | |
1306 | status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, | |
1307 | scp_data & 0xffff); | |
1308 | if (status < 0) | |
1309 | goto error; | |
1310 | ||
1311 | status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, | |
1312 | scp_data >> 16); | |
1313 | if (status < 0) | |
1314 | goto error; | |
1315 | ||
1316 | /* OK, now check if the write itself has executed*/ | |
1317 | status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, | |
1318 | VENDOR_DSPIO_STATUS, 0); | |
1319 | error: | |
1320 | mutex_unlock(&spec->chipio_mutex); | |
1321 | ||
1322 | return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? | |
1323 | -EIO : 0; | |
1324 | } | |
1325 | ||
d5c21b88 IM |
1326 | /* |
1327 | * Write multiple SCP data to DSP | |
1328 | */ | |
01ef7dbf IM |
1329 | static int dspio_write_multiple(struct hda_codec *codec, |
1330 | unsigned int *buffer, unsigned int size) | |
1331 | { | |
1332 | int status = 0; | |
1333 | unsigned int count; | |
1334 | ||
a16fbb85 | 1335 | if (buffer == NULL) |
01ef7dbf IM |
1336 | return -EINVAL; |
1337 | ||
1338 | count = 0; | |
1339 | while (count < size) { | |
1340 | status = dspio_write(codec, *buffer++); | |
1341 | if (status != 0) | |
1342 | break; | |
1343 | count++; | |
1344 | } | |
1345 | ||
1346 | return status; | |
1347 | } | |
1348 | ||
a73d511c IM |
1349 | static int dspio_read(struct hda_codec *codec, unsigned int *data) |
1350 | { | |
1351 | int status; | |
1352 | ||
1353 | status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); | |
1354 | if (status == -EIO) | |
1355 | return status; | |
1356 | ||
1357 | status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); | |
1358 | if (status == -EIO || | |
1359 | status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) | |
1360 | return -EIO; | |
1361 | ||
1362 | *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, | |
1363 | VENDOR_DSPIO_SCP_READ_DATA, 0); | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, | |
1369 | unsigned int *buf_size, unsigned int size_count) | |
1370 | { | |
1371 | int status = 0; | |
1372 | unsigned int size = *buf_size; | |
1373 | unsigned int count; | |
1374 | unsigned int skip_count; | |
1375 | unsigned int dummy; | |
1376 | ||
a16fbb85 | 1377 | if (buffer == NULL) |
a73d511c IM |
1378 | return -1; |
1379 | ||
1380 | count = 0; | |
1381 | while (count < size && count < size_count) { | |
1382 | status = dspio_read(codec, buffer++); | |
1383 | if (status != 0) | |
1384 | break; | |
1385 | count++; | |
1386 | } | |
1387 | ||
1388 | skip_count = count; | |
1389 | if (status == 0) { | |
1390 | while (skip_count < size) { | |
1391 | status = dspio_read(codec, &dummy); | |
1392 | if (status != 0) | |
1393 | break; | |
1394 | skip_count++; | |
1395 | } | |
1396 | } | |
1397 | *buf_size = count; | |
1398 | ||
1399 | return status; | |
1400 | } | |
1401 | ||
d5c21b88 IM |
1402 | /* |
1403 | * Construct the SCP header using corresponding fields | |
1404 | */ | |
01ef7dbf IM |
1405 | static inline unsigned int |
1406 | make_scp_header(unsigned int target_id, unsigned int source_id, | |
1407 | unsigned int get_flag, unsigned int req, | |
1408 | unsigned int device_flag, unsigned int resp_flag, | |
1409 | unsigned int error_flag, unsigned int data_size) | |
1410 | { | |
1411 | unsigned int header = 0; | |
1412 | ||
1413 | header = (data_size & 0x1f) << 27; | |
1414 | header |= (error_flag & 0x01) << 26; | |
1415 | header |= (resp_flag & 0x01) << 25; | |
1416 | header |= (device_flag & 0x01) << 24; | |
1417 | header |= (req & 0x7f) << 17; | |
1418 | header |= (get_flag & 0x01) << 16; | |
1419 | header |= (source_id & 0xff) << 8; | |
1420 | header |= target_id & 0xff; | |
1421 | ||
1422 | return header; | |
1423 | } | |
1424 | ||
d5c21b88 IM |
1425 | /* |
1426 | * Extract corresponding fields from SCP header | |
1427 | */ | |
01ef7dbf IM |
1428 | static inline void |
1429 | extract_scp_header(unsigned int header, | |
1430 | unsigned int *target_id, unsigned int *source_id, | |
1431 | unsigned int *get_flag, unsigned int *req, | |
1432 | unsigned int *device_flag, unsigned int *resp_flag, | |
1433 | unsigned int *error_flag, unsigned int *data_size) | |
1434 | { | |
1435 | if (data_size) | |
1436 | *data_size = (header >> 27) & 0x1f; | |
1437 | if (error_flag) | |
1438 | *error_flag = (header >> 26) & 0x01; | |
1439 | if (resp_flag) | |
1440 | *resp_flag = (header >> 25) & 0x01; | |
1441 | if (device_flag) | |
1442 | *device_flag = (header >> 24) & 0x01; | |
1443 | if (req) | |
1444 | *req = (header >> 17) & 0x7f; | |
1445 | if (get_flag) | |
1446 | *get_flag = (header >> 16) & 0x01; | |
1447 | if (source_id) | |
1448 | *source_id = (header >> 8) & 0xff; | |
1449 | if (target_id) | |
1450 | *target_id = header & 0xff; | |
1451 | } | |
1452 | ||
1453 | #define SCP_MAX_DATA_WORDS (16) | |
1454 | ||
1455 | /* Structure to contain any SCP message */ | |
1456 | struct scp_msg { | |
1457 | unsigned int hdr; | |
1458 | unsigned int data[SCP_MAX_DATA_WORDS]; | |
1459 | }; | |
1460 | ||
a73d511c IM |
1461 | static void dspio_clear_response_queue(struct hda_codec *codec) |
1462 | { | |
1463 | unsigned int dummy = 0; | |
1464 | int status = -1; | |
1465 | ||
1466 | /* clear all from the response queue */ | |
1467 | do { | |
1468 | status = dspio_read(codec, &dummy); | |
1469 | } while (status == 0); | |
1470 | } | |
1471 | ||
1472 | static int dspio_get_response_data(struct hda_codec *codec) | |
1473 | { | |
1474 | struct ca0132_spec *spec = codec->spec; | |
1475 | unsigned int data = 0; | |
1476 | unsigned int count; | |
1477 | ||
1478 | if (dspio_read(codec, &data) < 0) | |
1479 | return -EIO; | |
1480 | ||
1481 | if ((data & 0x00ffffff) == spec->wait_scp_header) { | |
1482 | spec->scp_resp_header = data; | |
1483 | spec->scp_resp_count = data >> 27; | |
1484 | count = spec->wait_num_data; | |
1485 | dspio_read_multiple(codec, spec->scp_resp_data, | |
1486 | &spec->scp_resp_count, count); | |
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | return -EIO; | |
1491 | } | |
1492 | ||
d5c21b88 IM |
1493 | /* |
1494 | * Send SCP message to DSP | |
1495 | */ | |
01ef7dbf IM |
1496 | static int dspio_send_scp_message(struct hda_codec *codec, |
1497 | unsigned char *send_buf, | |
1498 | unsigned int send_buf_size, | |
1499 | unsigned char *return_buf, | |
1500 | unsigned int return_buf_size, | |
1501 | unsigned int *bytes_returned) | |
1502 | { | |
1503 | struct ca0132_spec *spec = codec->spec; | |
01ef7dbf IM |
1504 | int status = -1; |
1505 | unsigned int scp_send_size = 0; | |
1506 | unsigned int total_size; | |
1507 | bool waiting_for_resp = false; | |
1508 | unsigned int header; | |
1509 | struct scp_msg *ret_msg; | |
1510 | unsigned int resp_src_id, resp_target_id; | |
1511 | unsigned int data_size, src_id, target_id, get_flag, device_flag; | |
1512 | ||
1513 | if (bytes_returned) | |
1514 | *bytes_returned = 0; | |
1515 | ||
1516 | /* get scp header from buffer */ | |
1517 | header = *((unsigned int *)send_buf); | |
1518 | extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, | |
1519 | &device_flag, NULL, NULL, &data_size); | |
1520 | scp_send_size = data_size + 1; | |
1521 | total_size = (scp_send_size * 4); | |
1522 | ||
1523 | if (send_buf_size < total_size) | |
1524 | return -EINVAL; | |
1525 | ||
1526 | if (get_flag || device_flag) { | |
1527 | if (!return_buf || return_buf_size < 4 || !bytes_returned) | |
1528 | return -EINVAL; | |
1529 | ||
1530 | spec->wait_scp_header = *((unsigned int *)send_buf); | |
1531 | ||
1532 | /* swap source id with target id */ | |
1533 | resp_target_id = src_id; | |
1534 | resp_src_id = target_id; | |
1535 | spec->wait_scp_header &= 0xffff0000; | |
1536 | spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); | |
1537 | spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; | |
1538 | spec->wait_scp = 1; | |
1539 | waiting_for_resp = true; | |
1540 | } | |
1541 | ||
1542 | status = dspio_write_multiple(codec, (unsigned int *)send_buf, | |
1543 | scp_send_size); | |
1544 | if (status < 0) { | |
1545 | spec->wait_scp = 0; | |
1546 | return status; | |
1547 | } | |
1548 | ||
1549 | if (waiting_for_resp) { | |
6d67530e | 1550 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
01ef7dbf | 1551 | memset(return_buf, 0, return_buf_size); |
01ef7dbf IM |
1552 | do { |
1553 | msleep(20); | |
6d67530e | 1554 | } while (spec->wait_scp && time_before(jiffies, timeout)); |
01ef7dbf | 1555 | waiting_for_resp = false; |
6d67530e | 1556 | if (!spec->wait_scp) { |
01ef7dbf IM |
1557 | ret_msg = (struct scp_msg *)return_buf; |
1558 | memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); | |
1559 | memcpy(&ret_msg->data, spec->scp_resp_data, | |
1560 | spec->wait_num_data); | |
1561 | *bytes_returned = (spec->scp_resp_count + 1) * 4; | |
1562 | status = 0; | |
1563 | } else { | |
1564 | status = -EIO; | |
1565 | } | |
1566 | spec->wait_scp = 0; | |
1567 | } | |
1568 | ||
1569 | return status; | |
1570 | } | |
1571 | ||
d5c21b88 IM |
1572 | /** |
1573 | * Prepare and send the SCP message to DSP | |
1574 | * @codec: the HDA codec | |
1575 | * @mod_id: ID of the DSP module to send the command | |
1576 | * @req: ID of request to send to the DSP module | |
1577 | * @dir: SET or GET | |
1578 | * @data: pointer to the data to send with the request, request specific | |
1579 | * @len: length of the data, in bytes | |
1580 | * @reply: point to the buffer to hold data returned for a reply | |
1581 | * @reply_len: length of the reply buffer returned from GET | |
1582 | * | |
1583 | * Returns zero or a negative error code. | |
1584 | */ | |
01ef7dbf | 1585 | static int dspio_scp(struct hda_codec *codec, |
447fd8e9 CM |
1586 | int mod_id, int src_id, int req, int dir, const void *data, |
1587 | unsigned int len, void *reply, unsigned int *reply_len) | |
01ef7dbf IM |
1588 | { |
1589 | int status = 0; | |
1590 | struct scp_msg scp_send, scp_reply; | |
1591 | unsigned int ret_bytes, send_size, ret_size; | |
1592 | unsigned int send_get_flag, reply_resp_flag, reply_error_flag; | |
1593 | unsigned int reply_data_size; | |
1594 | ||
1595 | memset(&scp_send, 0, sizeof(scp_send)); | |
1596 | memset(&scp_reply, 0, sizeof(scp_reply)); | |
1597 | ||
1598 | if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) | |
1599 | return -EINVAL; | |
1600 | ||
1601 | if (dir == SCP_GET && reply == NULL) { | |
4e76a883 | 1602 | codec_dbg(codec, "dspio_scp get but has no buffer\n"); |
01ef7dbf IM |
1603 | return -EINVAL; |
1604 | } | |
1605 | ||
1606 | if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { | |
4e76a883 | 1607 | codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); |
01ef7dbf IM |
1608 | return -EINVAL; |
1609 | } | |
1610 | ||
447fd8e9 | 1611 | scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, |
01ef7dbf IM |
1612 | 0, 0, 0, len/sizeof(unsigned int)); |
1613 | if (data != NULL && len > 0) { | |
1614 | len = min((unsigned int)(sizeof(scp_send.data)), len); | |
1615 | memcpy(scp_send.data, data, len); | |
1616 | } | |
1617 | ||
1618 | ret_bytes = 0; | |
1619 | send_size = sizeof(unsigned int) + len; | |
1620 | status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, | |
1621 | send_size, (unsigned char *)&scp_reply, | |
1622 | sizeof(scp_reply), &ret_bytes); | |
1623 | ||
1624 | if (status < 0) { | |
4e76a883 | 1625 | codec_dbg(codec, "dspio_scp: send scp msg failed\n"); |
01ef7dbf IM |
1626 | return status; |
1627 | } | |
1628 | ||
1629 | /* extract send and reply headers members */ | |
1630 | extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, | |
1631 | NULL, NULL, NULL, NULL, NULL); | |
1632 | extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, | |
1633 | &reply_resp_flag, &reply_error_flag, | |
1634 | &reply_data_size); | |
1635 | ||
1636 | if (!send_get_flag) | |
1637 | return 0; | |
1638 | ||
1639 | if (reply_resp_flag && !reply_error_flag) { | |
1640 | ret_size = (ret_bytes - sizeof(scp_reply.hdr)) | |
1641 | / sizeof(unsigned int); | |
1642 | ||
1643 | if (*reply_len < ret_size*sizeof(unsigned int)) { | |
4e76a883 | 1644 | codec_dbg(codec, "reply too long for buf\n"); |
01ef7dbf IM |
1645 | return -EINVAL; |
1646 | } else if (ret_size != reply_data_size) { | |
4e76a883 | 1647 | codec_dbg(codec, "RetLen and HdrLen .NE.\n"); |
01ef7dbf | 1648 | return -EINVAL; |
46a049da AB |
1649 | } else if (!reply) { |
1650 | codec_dbg(codec, "NULL reply\n"); | |
1651 | return -EINVAL; | |
01ef7dbf IM |
1652 | } else { |
1653 | *reply_len = ret_size*sizeof(unsigned int); | |
1654 | memcpy(reply, scp_reply.data, *reply_len); | |
1655 | } | |
1656 | } else { | |
4e76a883 | 1657 | codec_dbg(codec, "reply ill-formed or errflag set\n"); |
01ef7dbf IM |
1658 | return -EIO; |
1659 | } | |
1660 | ||
1661 | return status; | |
1662 | } | |
1663 | ||
5aaca44d IM |
1664 | /* |
1665 | * Set DSP parameters | |
1666 | */ | |
1667 | static int dspio_set_param(struct hda_codec *codec, int mod_id, | |
447fd8e9 | 1668 | int src_id, int req, const void *data, unsigned int len) |
5aaca44d | 1669 | { |
447fd8e9 CM |
1670 | return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, |
1671 | NULL); | |
5aaca44d IM |
1672 | } |
1673 | ||
1674 | static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, | |
447fd8e9 | 1675 | int req, const unsigned int data) |
5aaca44d | 1676 | { |
447fd8e9 CM |
1677 | return dspio_set_param(codec, mod_id, 0x20, req, &data, |
1678 | sizeof(unsigned int)); | |
1679 | } | |
1680 | ||
1681 | static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, | |
1682 | int req, const unsigned int data) | |
1683 | { | |
1684 | return dspio_set_param(codec, mod_id, 0x00, req, &data, | |
1685 | sizeof(unsigned int)); | |
5aaca44d IM |
1686 | } |
1687 | ||
d5c21b88 IM |
1688 | /* |
1689 | * Allocate a DSP DMA channel via an SCP message | |
1690 | */ | |
01ef7dbf IM |
1691 | static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) |
1692 | { | |
1693 | int status = 0; | |
1694 | unsigned int size = sizeof(dma_chan); | |
1695 | ||
4e76a883 | 1696 | codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); |
447fd8e9 CM |
1697 | status = dspio_scp(codec, MASTERCONTROL, 0x20, |
1698 | MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, | |
1699 | dma_chan, &size); | |
01ef7dbf IM |
1700 | |
1701 | if (status < 0) { | |
4e76a883 | 1702 | codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); |
01ef7dbf IM |
1703 | return status; |
1704 | } | |
1705 | ||
1706 | if ((*dma_chan + 1) == 0) { | |
4e76a883 | 1707 | codec_dbg(codec, "no free dma channels to allocate\n"); |
01ef7dbf IM |
1708 | return -EBUSY; |
1709 | } | |
1710 | ||
4e76a883 TI |
1711 | codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); |
1712 | codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); | |
01ef7dbf IM |
1713 | |
1714 | return status; | |
1715 | } | |
1716 | ||
d5c21b88 IM |
1717 | /* |
1718 | * Free a DSP DMA via an SCP message | |
1719 | */ | |
01ef7dbf IM |
1720 | static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) |
1721 | { | |
1722 | int status = 0; | |
1723 | unsigned int dummy = 0; | |
1724 | ||
4e76a883 TI |
1725 | codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); |
1726 | codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); | |
01ef7dbf | 1727 | |
447fd8e9 CM |
1728 | status = dspio_scp(codec, MASTERCONTROL, 0x20, |
1729 | MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, | |
1730 | sizeof(dma_chan), NULL, &dummy); | |
01ef7dbf IM |
1731 | |
1732 | if (status < 0) { | |
4e76a883 | 1733 | codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); |
01ef7dbf IM |
1734 | return status; |
1735 | } | |
1736 | ||
4e76a883 | 1737 | codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); |
01ef7dbf IM |
1738 | |
1739 | return status; | |
1740 | } | |
1741 | ||
1742 | /* | |
d5c21b88 | 1743 | * (Re)start the DSP |
01ef7dbf IM |
1744 | */ |
1745 | static int dsp_set_run_state(struct hda_codec *codec) | |
1746 | { | |
1747 | unsigned int dbg_ctrl_reg; | |
1748 | unsigned int halt_state; | |
1749 | int err; | |
1750 | ||
1751 | err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); | |
1752 | if (err < 0) | |
1753 | return err; | |
1754 | ||
1755 | halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> | |
1756 | DSP_DBGCNTL_STATE_LOBIT; | |
1757 | ||
1758 | if (halt_state != 0) { | |
1759 | dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & | |
1760 | DSP_DBGCNTL_SS_MASK); | |
1761 | err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, | |
1762 | dbg_ctrl_reg); | |
1763 | if (err < 0) | |
1764 | return err; | |
1765 | ||
1766 | dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & | |
1767 | DSP_DBGCNTL_EXEC_MASK; | |
1768 | err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, | |
1769 | dbg_ctrl_reg); | |
1770 | if (err < 0) | |
1771 | return err; | |
1772 | } | |
1773 | ||
1774 | return 0; | |
1775 | } | |
1776 | ||
d5c21b88 IM |
1777 | /* |
1778 | * Reset the DSP | |
1779 | */ | |
01ef7dbf IM |
1780 | static int dsp_reset(struct hda_codec *codec) |
1781 | { | |
1782 | unsigned int res; | |
1783 | int retry = 20; | |
1784 | ||
4e76a883 | 1785 | codec_dbg(codec, "dsp_reset\n"); |
01ef7dbf IM |
1786 | do { |
1787 | res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); | |
1788 | retry--; | |
1789 | } while (res == -EIO && retry); | |
1790 | ||
1791 | if (!retry) { | |
4e76a883 | 1792 | codec_dbg(codec, "dsp_reset timeout\n"); |
01ef7dbf IM |
1793 | return -EIO; |
1794 | } | |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | ||
d5c21b88 IM |
1799 | /* |
1800 | * Convert chip address to DSP address | |
1801 | */ | |
01ef7dbf IM |
1802 | static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, |
1803 | bool *code, bool *yram) | |
1804 | { | |
1805 | *code = *yram = false; | |
1806 | ||
1807 | if (UC_RANGE(chip_addx, 1)) { | |
1808 | *code = true; | |
1809 | return UC_OFF(chip_addx); | |
1810 | } else if (X_RANGE_ALL(chip_addx, 1)) { | |
1811 | return X_OFF(chip_addx); | |
1812 | } else if (Y_RANGE_ALL(chip_addx, 1)) { | |
1813 | *yram = true; | |
1814 | return Y_OFF(chip_addx); | |
1815 | } | |
1816 | ||
4a8b89f9 | 1817 | return INVALID_CHIP_ADDRESS; |
01ef7dbf IM |
1818 | } |
1819 | ||
d5c21b88 IM |
1820 | /* |
1821 | * Check if the DSP DMA is active | |
1822 | */ | |
01ef7dbf IM |
1823 | static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) |
1824 | { | |
1825 | unsigned int dma_chnlstart_reg; | |
1826 | ||
1827 | chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); | |
1828 | ||
1829 | return ((dma_chnlstart_reg & (1 << | |
1830 | (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); | |
1831 | } | |
1832 | ||
1833 | static int dsp_dma_setup_common(struct hda_codec *codec, | |
1834 | unsigned int chip_addx, | |
1835 | unsigned int dma_chan, | |
1836 | unsigned int port_map_mask, | |
1837 | bool ovly) | |
1838 | { | |
1839 | int status = 0; | |
1840 | unsigned int chnl_prop; | |
1841 | unsigned int dsp_addx; | |
1842 | unsigned int active; | |
1843 | bool code, yram; | |
1844 | ||
4e76a883 | 1845 | codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); |
01ef7dbf IM |
1846 | |
1847 | if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { | |
4e76a883 | 1848 | codec_dbg(codec, "dma chan num invalid\n"); |
01ef7dbf IM |
1849 | return -EINVAL; |
1850 | } | |
1851 | ||
1852 | if (dsp_is_dma_active(codec, dma_chan)) { | |
4e76a883 | 1853 | codec_dbg(codec, "dma already active\n"); |
01ef7dbf IM |
1854 | return -EBUSY; |
1855 | } | |
1856 | ||
1857 | dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); | |
1858 | ||
1859 | if (dsp_addx == INVALID_CHIP_ADDRESS) { | |
4e76a883 | 1860 | codec_dbg(codec, "invalid chip addr\n"); |
01ef7dbf IM |
1861 | return -ENXIO; |
1862 | } | |
1863 | ||
1864 | chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; | |
1865 | active = 0; | |
1866 | ||
4e76a883 | 1867 | codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); |
01ef7dbf IM |
1868 | |
1869 | if (ovly) { | |
1870 | status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, | |
1871 | &chnl_prop); | |
1872 | ||
1873 | if (status < 0) { | |
4e76a883 | 1874 | codec_dbg(codec, "read CHNLPROP Reg fail\n"); |
01ef7dbf IM |
1875 | return status; |
1876 | } | |
4e76a883 | 1877 | codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); |
01ef7dbf IM |
1878 | } |
1879 | ||
1880 | if (!code) | |
1881 | chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); | |
1882 | else | |
1883 | chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); | |
1884 | ||
1885 | chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); | |
1886 | ||
1887 | status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); | |
1888 | if (status < 0) { | |
4e76a883 | 1889 | codec_dbg(codec, "write CHNLPROP Reg fail\n"); |
01ef7dbf IM |
1890 | return status; |
1891 | } | |
4e76a883 | 1892 | codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); |
01ef7dbf IM |
1893 | |
1894 | if (ovly) { | |
1895 | status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, | |
1896 | &active); | |
1897 | ||
1898 | if (status < 0) { | |
4e76a883 | 1899 | codec_dbg(codec, "read ACTIVE Reg fail\n"); |
01ef7dbf IM |
1900 | return status; |
1901 | } | |
4e76a883 | 1902 | codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); |
01ef7dbf IM |
1903 | } |
1904 | ||
1905 | active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & | |
1906 | DSPDMAC_ACTIVE_AAR_MASK; | |
1907 | ||
1908 | status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); | |
1909 | if (status < 0) { | |
4e76a883 | 1910 | codec_dbg(codec, "write ACTIVE Reg fail\n"); |
01ef7dbf IM |
1911 | return status; |
1912 | } | |
1913 | ||
4e76a883 | 1914 | codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); |
01ef7dbf IM |
1915 | |
1916 | status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), | |
1917 | port_map_mask); | |
1918 | if (status < 0) { | |
4e76a883 | 1919 | codec_dbg(codec, "write AUDCHSEL Reg fail\n"); |
01ef7dbf IM |
1920 | return status; |
1921 | } | |
4e76a883 | 1922 | codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); |
01ef7dbf IM |
1923 | |
1924 | status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), | |
1925 | DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); | |
1926 | if (status < 0) { | |
4e76a883 | 1927 | codec_dbg(codec, "write IRQCNT Reg fail\n"); |
01ef7dbf IM |
1928 | return status; |
1929 | } | |
4e76a883 | 1930 | codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); |
01ef7dbf | 1931 | |
4e76a883 | 1932 | codec_dbg(codec, |
01ef7dbf IM |
1933 | "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " |
1934 | "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", | |
1935 | chip_addx, dsp_addx, dma_chan, | |
1936 | port_map_mask, chnl_prop, active); | |
1937 | ||
4e76a883 | 1938 | codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); |
01ef7dbf IM |
1939 | |
1940 | return 0; | |
1941 | } | |
1942 | ||
d5c21b88 IM |
1943 | /* |
1944 | * Setup the DSP DMA per-transfer-specific registers | |
1945 | */ | |
01ef7dbf IM |
1946 | static int dsp_dma_setup(struct hda_codec *codec, |
1947 | unsigned int chip_addx, | |
1948 | unsigned int count, | |
1949 | unsigned int dma_chan) | |
1950 | { | |
1951 | int status = 0; | |
1952 | bool code, yram; | |
1953 | unsigned int dsp_addx; | |
1954 | unsigned int addr_field; | |
1955 | unsigned int incr_field; | |
1956 | unsigned int base_cnt; | |
1957 | unsigned int cur_cnt; | |
1958 | unsigned int dma_cfg = 0; | |
1959 | unsigned int adr_ofs = 0; | |
1960 | unsigned int xfr_cnt = 0; | |
1961 | const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - | |
1962 | DSPDMAC_XFRCNT_BCNT_LOBIT + 1); | |
1963 | ||
4e76a883 | 1964 | codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); |
01ef7dbf IM |
1965 | |
1966 | if (count > max_dma_count) { | |
4e76a883 | 1967 | codec_dbg(codec, "count too big\n"); |
01ef7dbf IM |
1968 | return -EINVAL; |
1969 | } | |
1970 | ||
1971 | dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); | |
1972 | if (dsp_addx == INVALID_CHIP_ADDRESS) { | |
4e76a883 | 1973 | codec_dbg(codec, "invalid chip addr\n"); |
01ef7dbf IM |
1974 | return -ENXIO; |
1975 | } | |
1976 | ||
4e76a883 | 1977 | codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); |
01ef7dbf IM |
1978 | |
1979 | addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; | |
1980 | incr_field = 0; | |
1981 | ||
1982 | if (!code) { | |
1983 | addr_field <<= 1; | |
1984 | if (yram) | |
1985 | addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); | |
1986 | ||
1987 | incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); | |
1988 | } | |
1989 | ||
1990 | dma_cfg = addr_field + incr_field; | |
1991 | status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), | |
1992 | dma_cfg); | |
1993 | if (status < 0) { | |
4e76a883 | 1994 | codec_dbg(codec, "write DMACFG Reg fail\n"); |
01ef7dbf IM |
1995 | return status; |
1996 | } | |
4e76a883 | 1997 | codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); |
01ef7dbf IM |
1998 | |
1999 | adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + | |
2000 | (code ? 0 : 1)); | |
2001 | ||
2002 | status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), | |
2003 | adr_ofs); | |
2004 | if (status < 0) { | |
4e76a883 | 2005 | codec_dbg(codec, "write DSPADROFS Reg fail\n"); |
01ef7dbf IM |
2006 | return status; |
2007 | } | |
4e76a883 | 2008 | codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); |
01ef7dbf IM |
2009 | |
2010 | base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; | |
2011 | ||
2012 | cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; | |
2013 | ||
2014 | xfr_cnt = base_cnt | cur_cnt; | |
2015 | ||
2016 | status = chipio_write(codec, | |
2017 | DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); | |
2018 | if (status < 0) { | |
4e76a883 | 2019 | codec_dbg(codec, "write XFRCNT Reg fail\n"); |
01ef7dbf IM |
2020 | return status; |
2021 | } | |
4e76a883 | 2022 | codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); |
01ef7dbf | 2023 | |
4e76a883 | 2024 | codec_dbg(codec, |
01ef7dbf IM |
2025 | "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " |
2026 | "ADROFS=0x%x, XFRCNT=0x%x\n", | |
2027 | chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); | |
2028 | ||
4e76a883 | 2029 | codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); |
01ef7dbf IM |
2030 | |
2031 | return 0; | |
2032 | } | |
2033 | ||
d5c21b88 IM |
2034 | /* |
2035 | * Start the DSP DMA | |
2036 | */ | |
01ef7dbf IM |
2037 | static int dsp_dma_start(struct hda_codec *codec, |
2038 | unsigned int dma_chan, bool ovly) | |
2039 | { | |
2040 | unsigned int reg = 0; | |
2041 | int status = 0; | |
2042 | ||
4e76a883 | 2043 | codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); |
01ef7dbf IM |
2044 | |
2045 | if (ovly) { | |
2046 | status = chipio_read(codec, | |
2047 | DSPDMAC_CHNLSTART_INST_OFFSET, ®); | |
2048 | ||
2049 | if (status < 0) { | |
4e76a883 | 2050 | codec_dbg(codec, "read CHNLSTART reg fail\n"); |
01ef7dbf IM |
2051 | return status; |
2052 | } | |
4e76a883 | 2053 | codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); |
01ef7dbf IM |
2054 | |
2055 | reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | | |
2056 | DSPDMAC_CHNLSTART_DIS_MASK); | |
2057 | } | |
2058 | ||
2059 | status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, | |
2060 | reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); | |
2061 | if (status < 0) { | |
4e76a883 | 2062 | codec_dbg(codec, "write CHNLSTART reg fail\n"); |
01ef7dbf IM |
2063 | return status; |
2064 | } | |
4e76a883 | 2065 | codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); |
01ef7dbf IM |
2066 | |
2067 | return status; | |
2068 | } | |
2069 | ||
d5c21b88 IM |
2070 | /* |
2071 | * Stop the DSP DMA | |
2072 | */ | |
01ef7dbf IM |
2073 | static int dsp_dma_stop(struct hda_codec *codec, |
2074 | unsigned int dma_chan, bool ovly) | |
2075 | { | |
2076 | unsigned int reg = 0; | |
2077 | int status = 0; | |
2078 | ||
4e76a883 | 2079 | codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); |
01ef7dbf IM |
2080 | |
2081 | if (ovly) { | |
2082 | status = chipio_read(codec, | |
2083 | DSPDMAC_CHNLSTART_INST_OFFSET, ®); | |
2084 | ||
2085 | if (status < 0) { | |
4e76a883 | 2086 | codec_dbg(codec, "read CHNLSTART reg fail\n"); |
01ef7dbf IM |
2087 | return status; |
2088 | } | |
4e76a883 | 2089 | codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); |
01ef7dbf IM |
2090 | reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | |
2091 | DSPDMAC_CHNLSTART_DIS_MASK); | |
2092 | } | |
2093 | ||
2094 | status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, | |
2095 | reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); | |
2096 | if (status < 0) { | |
4e76a883 | 2097 | codec_dbg(codec, "write CHNLSTART reg fail\n"); |
01ef7dbf IM |
2098 | return status; |
2099 | } | |
4e76a883 | 2100 | codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); |
01ef7dbf IM |
2101 | |
2102 | return status; | |
2103 | } | |
2104 | ||
d5c21b88 IM |
2105 | /** |
2106 | * Allocate router ports | |
2107 | * | |
2108 | * @codec: the HDA codec | |
2109 | * @num_chans: number of channels in the stream | |
2110 | * @ports_per_channel: number of ports per channel | |
2111 | * @start_device: start device | |
2112 | * @port_map: pointer to the port list to hold the allocated ports | |
2113 | * | |
2114 | * Returns zero or a negative error code. | |
2115 | */ | |
01ef7dbf IM |
2116 | static int dsp_allocate_router_ports(struct hda_codec *codec, |
2117 | unsigned int num_chans, | |
2118 | unsigned int ports_per_channel, | |
2119 | unsigned int start_device, | |
2120 | unsigned int *port_map) | |
2121 | { | |
2122 | int status = 0; | |
2123 | int res; | |
2124 | u8 val; | |
2125 | ||
2126 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); | |
2127 | if (status < 0) | |
2128 | return status; | |
2129 | ||
2130 | val = start_device << 6; | |
2131 | val |= (ports_per_channel - 1) << 4; | |
2132 | val |= num_chans - 1; | |
2133 | ||
2134 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
2135 | VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, | |
2136 | val); | |
2137 | ||
2138 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
2139 | VENDOR_CHIPIO_PORT_ALLOC_SET, | |
2140 | MEM_CONNID_DSP); | |
2141 | ||
2142 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); | |
2143 | if (status < 0) | |
2144 | return status; | |
2145 | ||
2146 | res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, | |
2147 | VENDOR_CHIPIO_PORT_ALLOC_GET, 0); | |
2148 | ||
2149 | *port_map = res; | |
2150 | ||
2151 | return (res < 0) ? res : 0; | |
2152 | } | |
2153 | ||
d5c21b88 IM |
2154 | /* |
2155 | * Free router ports | |
2156 | */ | |
01ef7dbf IM |
2157 | static int dsp_free_router_ports(struct hda_codec *codec) |
2158 | { | |
2159 | int status = 0; | |
2160 | ||
2161 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); | |
2162 | if (status < 0) | |
2163 | return status; | |
2164 | ||
2165 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
2166 | VENDOR_CHIPIO_PORT_FREE_SET, | |
2167 | MEM_CONNID_DSP); | |
2168 | ||
2169 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); | |
2170 | ||
2171 | return status; | |
2172 | } | |
2173 | ||
d5c21b88 IM |
2174 | /* |
2175 | * Allocate DSP ports for the download stream | |
2176 | */ | |
01ef7dbf IM |
2177 | static int dsp_allocate_ports(struct hda_codec *codec, |
2178 | unsigned int num_chans, | |
2179 | unsigned int rate_multi, unsigned int *port_map) | |
2180 | { | |
2181 | int status; | |
2182 | ||
4e76a883 | 2183 | codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); |
01ef7dbf IM |
2184 | |
2185 | if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { | |
4e76a883 | 2186 | codec_dbg(codec, "bad rate multiple\n"); |
01ef7dbf IM |
2187 | return -EINVAL; |
2188 | } | |
2189 | ||
2190 | status = dsp_allocate_router_ports(codec, num_chans, | |
2191 | rate_multi, 0, port_map); | |
2192 | ||
4e76a883 | 2193 | codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); |
01ef7dbf IM |
2194 | |
2195 | return status; | |
2196 | } | |
2197 | ||
01ef7dbf IM |
2198 | static int dsp_allocate_ports_format(struct hda_codec *codec, |
2199 | const unsigned short fmt, | |
2200 | unsigned int *port_map) | |
2201 | { | |
2202 | int status; | |
2203 | unsigned int num_chans; | |
2204 | ||
2205 | unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; | |
2206 | unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; | |
2207 | unsigned int rate_multi = sample_rate_mul / sample_rate_div; | |
2208 | ||
2209 | if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { | |
4e76a883 | 2210 | codec_dbg(codec, "bad rate multiple\n"); |
01ef7dbf IM |
2211 | return -EINVAL; |
2212 | } | |
2213 | ||
2214 | num_chans = get_hdafmt_chs(fmt) + 1; | |
2215 | ||
2216 | status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); | |
2217 | ||
2218 | return status; | |
2219 | } | |
2220 | ||
d5c21b88 IM |
2221 | /* |
2222 | * free DSP ports | |
2223 | */ | |
2224 | static int dsp_free_ports(struct hda_codec *codec) | |
2225 | { | |
2226 | int status; | |
2227 | ||
4e76a883 | 2228 | codec_dbg(codec, " dsp_free_ports() -- begin\n"); |
d5c21b88 IM |
2229 | |
2230 | status = dsp_free_router_ports(codec); | |
2231 | if (status < 0) { | |
4e76a883 | 2232 | codec_dbg(codec, "free router ports fail\n"); |
d5c21b88 IM |
2233 | return status; |
2234 | } | |
4e76a883 | 2235 | codec_dbg(codec, " dsp_free_ports() -- complete\n"); |
d5c21b88 IM |
2236 | |
2237 | return status; | |
2238 | } | |
2239 | ||
01ef7dbf IM |
2240 | /* |
2241 | * HDA DMA engine stuffs for DSP code download | |
2242 | */ | |
2243 | struct dma_engine { | |
2244 | struct hda_codec *codec; | |
2245 | unsigned short m_converter_format; | |
2246 | struct snd_dma_buffer *dmab; | |
2247 | unsigned int buf_size; | |
2248 | }; | |
2249 | ||
2250 | ||
2251 | enum dma_state { | |
2252 | DMA_STATE_STOP = 0, | |
2253 | DMA_STATE_RUN = 1 | |
2254 | }; | |
2255 | ||
6194b99d | 2256 | static int dma_convert_to_hda_format(struct hda_codec *codec, |
e97249dd IM |
2257 | unsigned int sample_rate, |
2258 | unsigned short channels, | |
01ef7dbf IM |
2259 | unsigned short *hda_format) |
2260 | { | |
2261 | unsigned int format_val; | |
2262 | ||
b7d023e1 TI |
2263 | format_val = snd_hdac_calc_stream_format(sample_rate, |
2264 | channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); | |
01ef7dbf IM |
2265 | |
2266 | if (hda_format) | |
2267 | *hda_format = (unsigned short)format_val; | |
2268 | ||
2269 | return 0; | |
2270 | } | |
2271 | ||
d5c21b88 IM |
2272 | /* |
2273 | * Reset DMA for DSP download | |
2274 | */ | |
01ef7dbf IM |
2275 | static int dma_reset(struct dma_engine *dma) |
2276 | { | |
2277 | struct hda_codec *codec = dma->codec; | |
2278 | struct ca0132_spec *spec = codec->spec; | |
2279 | int status; | |
2280 | ||
b3667bd7 | 2281 | if (dma->dmab->area) |
01ef7dbf IM |
2282 | snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); |
2283 | ||
2284 | status = snd_hda_codec_load_dsp_prepare(codec, | |
2285 | dma->m_converter_format, | |
2286 | dma->buf_size, | |
2287 | dma->dmab); | |
2288 | if (status < 0) | |
2289 | return status; | |
2290 | spec->dsp_stream_id = status; | |
2291 | return 0; | |
2292 | } | |
2293 | ||
2294 | static int dma_set_state(struct dma_engine *dma, enum dma_state state) | |
95c6e9cb | 2295 | { |
01ef7dbf IM |
2296 | bool cmd; |
2297 | ||
01ef7dbf IM |
2298 | switch (state) { |
2299 | case DMA_STATE_STOP: | |
2300 | cmd = false; | |
2301 | break; | |
2302 | case DMA_STATE_RUN: | |
2303 | cmd = true; | |
2304 | break; | |
2305 | default: | |
c41999a2 DH |
2306 | return 0; |
2307 | } | |
01ef7dbf IM |
2308 | |
2309 | snd_hda_codec_load_dsp_trigger(dma->codec, cmd); | |
2310 | return 0; | |
95c6e9cb IM |
2311 | } |
2312 | ||
01ef7dbf IM |
2313 | static unsigned int dma_get_buffer_size(struct dma_engine *dma) |
2314 | { | |
2315 | return dma->dmab->bytes; | |
2316 | } | |
95c6e9cb | 2317 | |
01ef7dbf IM |
2318 | static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) |
2319 | { | |
2320 | return dma->dmab->area; | |
2321 | } | |
95c6e9cb | 2322 | |
01ef7dbf IM |
2323 | static int dma_xfer(struct dma_engine *dma, |
2324 | const unsigned int *data, | |
2325 | unsigned int count) | |
2326 | { | |
2327 | memcpy(dma->dmab->area, data, count); | |
2328 | return 0; | |
2329 | } | |
95c6e9cb | 2330 | |
01ef7dbf IM |
2331 | static void dma_get_converter_format( |
2332 | struct dma_engine *dma, | |
2333 | unsigned short *format) | |
2334 | { | |
2335 | if (format) | |
2336 | *format = dma->m_converter_format; | |
2337 | } | |
95c6e9cb | 2338 | |
01ef7dbf | 2339 | static unsigned int dma_get_stream_id(struct dma_engine *dma) |
95c6e9cb | 2340 | { |
01ef7dbf | 2341 | struct ca0132_spec *spec = dma->codec->spec; |
95c6e9cb | 2342 | |
01ef7dbf | 2343 | return spec->dsp_stream_id; |
95c6e9cb IM |
2344 | } |
2345 | ||
01ef7dbf IM |
2346 | struct dsp_image_seg { |
2347 | u32 magic; | |
2348 | u32 chip_addr; | |
2349 | u32 count; | |
2350 | u32 data[0]; | |
2351 | }; | |
2352 | ||
2353 | static const u32 g_magic_value = 0x4c46584d; | |
2354 | static const u32 g_chip_addr_magic_value = 0xFFFFFF01; | |
2355 | ||
2356 | static bool is_valid(const struct dsp_image_seg *p) | |
95c6e9cb | 2357 | { |
01ef7dbf IM |
2358 | return p->magic == g_magic_value; |
2359 | } | |
95c6e9cb | 2360 | |
01ef7dbf IM |
2361 | static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) |
2362 | { | |
2363 | return g_chip_addr_magic_value == p->chip_addr; | |
2364 | } | |
95c6e9cb | 2365 | |
01ef7dbf IM |
2366 | static bool is_last(const struct dsp_image_seg *p) |
2367 | { | |
2368 | return p->count == 0; | |
2369 | } | |
95c6e9cb | 2370 | |
01ef7dbf IM |
2371 | static size_t dsp_sizeof(const struct dsp_image_seg *p) |
2372 | { | |
2373 | return sizeof(*p) + p->count*sizeof(u32); | |
2374 | } | |
2375 | ||
2376 | static const struct dsp_image_seg *get_next_seg_ptr( | |
2377 | const struct dsp_image_seg *p) | |
2378 | { | |
2379 | return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); | |
95c6e9cb IM |
2380 | } |
2381 | ||
2382 | /* | |
01ef7dbf | 2383 | * CA0132 chip DSP transfer stuffs. For DSP download. |
95c6e9cb | 2384 | */ |
8ae3124b | 2385 | #define INVALID_DMA_CHANNEL (~0U) |
95c6e9cb | 2386 | |
d5c21b88 IM |
2387 | /* |
2388 | * Program a list of address/data pairs via the ChipIO widget. | |
2389 | * The segment data is in the format of successive pairs of words. | |
2390 | * These are repeated as indicated by the segment's count field. | |
2391 | */ | |
01ef7dbf IM |
2392 | static int dspxfr_hci_write(struct hda_codec *codec, |
2393 | const struct dsp_image_seg *fls) | |
95c6e9cb | 2394 | { |
01ef7dbf IM |
2395 | int status; |
2396 | const u32 *data; | |
2397 | unsigned int count; | |
95c6e9cb | 2398 | |
01ef7dbf | 2399 | if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { |
4e76a883 | 2400 | codec_dbg(codec, "hci_write invalid params\n"); |
01ef7dbf | 2401 | return -EINVAL; |
95c6e9cb IM |
2402 | } |
2403 | ||
01ef7dbf IM |
2404 | count = fls->count; |
2405 | data = (u32 *)(fls->data); | |
2406 | while (count >= 2) { | |
2407 | status = chipio_write(codec, data[0], data[1]); | |
2408 | if (status < 0) { | |
4e76a883 | 2409 | codec_dbg(codec, "hci_write chipio failed\n"); |
01ef7dbf IM |
2410 | return status; |
2411 | } | |
2412 | count -= 2; | |
2413 | data += 2; | |
2414 | } | |
2415 | return 0; | |
95c6e9cb IM |
2416 | } |
2417 | ||
d5c21b88 IM |
2418 | /** |
2419 | * Write a block of data into DSP code or data RAM using pre-allocated | |
2420 | * DMA engine. | |
2421 | * | |
2422 | * @codec: the HDA codec | |
2423 | * @fls: pointer to a fast load image | |
2424 | * @reloc: Relocation address for loading single-segment overlays, or 0 for | |
2425 | * no relocation | |
2426 | * @dma_engine: pointer to DMA engine to be used for DSP download | |
2427 | * @dma_chan: The number of DMA channels used for DSP download | |
2428 | * @port_map_mask: port mapping | |
2429 | * @ovly: TRUE if overlay format is required | |
2430 | * | |
2431 | * Returns zero or a negative error code. | |
2432 | */ | |
01ef7dbf IM |
2433 | static int dspxfr_one_seg(struct hda_codec *codec, |
2434 | const struct dsp_image_seg *fls, | |
2435 | unsigned int reloc, | |
2436 | struct dma_engine *dma_engine, | |
2437 | unsigned int dma_chan, | |
2438 | unsigned int port_map_mask, | |
2439 | bool ovly) | |
95c6e9cb | 2440 | { |
406261ce | 2441 | int status = 0; |
01ef7dbf IM |
2442 | bool comm_dma_setup_done = false; |
2443 | const unsigned int *data; | |
2444 | unsigned int chip_addx; | |
2445 | unsigned int words_to_write; | |
2446 | unsigned int buffer_size_words; | |
2447 | unsigned char *buffer_addx; | |
2448 | unsigned short hda_format; | |
2449 | unsigned int sample_rate_div; | |
2450 | unsigned int sample_rate_mul; | |
2451 | unsigned int num_chans; | |
2452 | unsigned int hda_frame_size_words; | |
2453 | unsigned int remainder_words; | |
2454 | const u32 *data_remainder; | |
2455 | u32 chip_addx_remainder; | |
2456 | unsigned int run_size_words; | |
2457 | const struct dsp_image_seg *hci_write = NULL; | |
6d67530e IM |
2458 | unsigned long timeout; |
2459 | bool dma_active; | |
01ef7dbf IM |
2460 | |
2461 | if (fls == NULL) | |
2462 | return -EINVAL; | |
2463 | if (is_hci_prog_list_seg(fls)) { | |
2464 | hci_write = fls; | |
2465 | fls = get_next_seg_ptr(fls); | |
2466 | } | |
95c6e9cb | 2467 | |
01ef7dbf | 2468 | if (hci_write && (!fls || is_last(fls))) { |
4e76a883 | 2469 | codec_dbg(codec, "hci_write\n"); |
01ef7dbf IM |
2470 | return dspxfr_hci_write(codec, hci_write); |
2471 | } | |
95c6e9cb | 2472 | |
01ef7dbf | 2473 | if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { |
4e76a883 | 2474 | codec_dbg(codec, "Invalid Params\n"); |
01ef7dbf | 2475 | return -EINVAL; |
95c6e9cb IM |
2476 | } |
2477 | ||
01ef7dbf IM |
2478 | data = fls->data; |
2479 | chip_addx = fls->chip_addr, | |
2480 | words_to_write = fls->count; | |
2481 | ||
2482 | if (!words_to_write) | |
2483 | return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; | |
2484 | if (reloc) | |
2485 | chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); | |
2486 | ||
2487 | if (!UC_RANGE(chip_addx, words_to_write) && | |
2488 | !X_RANGE_ALL(chip_addx, words_to_write) && | |
2489 | !Y_RANGE_ALL(chip_addx, words_to_write)) { | |
4e76a883 | 2490 | codec_dbg(codec, "Invalid chip_addx Params\n"); |
01ef7dbf | 2491 | return -EINVAL; |
95c6e9cb IM |
2492 | } |
2493 | ||
01ef7dbf IM |
2494 | buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / |
2495 | sizeof(u32); | |
2496 | ||
2497 | buffer_addx = dma_get_buffer_addr(dma_engine); | |
2498 | ||
2499 | if (buffer_addx == NULL) { | |
4e76a883 | 2500 | codec_dbg(codec, "dma_engine buffer NULL\n"); |
01ef7dbf IM |
2501 | return -EINVAL; |
2502 | } | |
2503 | ||
2504 | dma_get_converter_format(dma_engine, &hda_format); | |
2505 | sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; | |
2506 | sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; | |
2507 | num_chans = get_hdafmt_chs(hda_format) + 1; | |
2508 | ||
2509 | hda_frame_size_words = ((sample_rate_div == 0) ? 0 : | |
2510 | (num_chans * sample_rate_mul / sample_rate_div)); | |
2511 | ||
3bc085a1 | 2512 | if (hda_frame_size_words == 0) { |
4e76a883 | 2513 | codec_dbg(codec, "frmsz zero\n"); |
3bc085a1 XW |
2514 | return -EINVAL; |
2515 | } | |
2516 | ||
01ef7dbf IM |
2517 | buffer_size_words = min(buffer_size_words, |
2518 | (unsigned int)(UC_RANGE(chip_addx, 1) ? | |
2519 | 65536 : 32768)); | |
2520 | buffer_size_words -= buffer_size_words % hda_frame_size_words; | |
4e76a883 | 2521 | codec_dbg(codec, |
01ef7dbf IM |
2522 | "chpadr=0x%08x frmsz=%u nchan=%u " |
2523 | "rate_mul=%u div=%u bufsz=%u\n", | |
2524 | chip_addx, hda_frame_size_words, num_chans, | |
2525 | sample_rate_mul, sample_rate_div, buffer_size_words); | |
2526 | ||
3bc085a1 | 2527 | if (buffer_size_words < hda_frame_size_words) { |
4e76a883 | 2528 | codec_dbg(codec, "dspxfr_one_seg:failed\n"); |
01ef7dbf IM |
2529 | return -EINVAL; |
2530 | } | |
2531 | ||
2532 | remainder_words = words_to_write % hda_frame_size_words; | |
2533 | data_remainder = data; | |
2534 | chip_addx_remainder = chip_addx; | |
2535 | ||
2536 | data += remainder_words; | |
2537 | chip_addx += remainder_words*sizeof(u32); | |
2538 | words_to_write -= remainder_words; | |
2539 | ||
2540 | while (words_to_write != 0) { | |
2541 | run_size_words = min(buffer_size_words, words_to_write); | |
4e76a883 | 2542 | codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", |
01ef7dbf IM |
2543 | words_to_write, run_size_words, remainder_words); |
2544 | dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); | |
2545 | if (!comm_dma_setup_done) { | |
2546 | status = dsp_dma_stop(codec, dma_chan, ovly); | |
2547 | if (status < 0) | |
425a7880 | 2548 | return status; |
01ef7dbf IM |
2549 | status = dsp_dma_setup_common(codec, chip_addx, |
2550 | dma_chan, port_map_mask, ovly); | |
2551 | if (status < 0) | |
2552 | return status; | |
2553 | comm_dma_setup_done = true; | |
2554 | } | |
2555 | ||
2556 | status = dsp_dma_setup(codec, chip_addx, | |
2557 | run_size_words, dma_chan); | |
2558 | if (status < 0) | |
2559 | return status; | |
2560 | status = dsp_dma_start(codec, dma_chan, ovly); | |
2561 | if (status < 0) | |
2562 | return status; | |
2563 | if (!dsp_is_dma_active(codec, dma_chan)) { | |
4e76a883 | 2564 | codec_dbg(codec, "dspxfr:DMA did not start\n"); |
01ef7dbf IM |
2565 | return -EIO; |
2566 | } | |
2567 | status = dma_set_state(dma_engine, DMA_STATE_RUN); | |
2568 | if (status < 0) | |
2569 | return status; | |
2570 | if (remainder_words != 0) { | |
2571 | status = chipio_write_multiple(codec, | |
2572 | chip_addx_remainder, | |
2573 | data_remainder, | |
2574 | remainder_words); | |
b3667bd7 TI |
2575 | if (status < 0) |
2576 | return status; | |
01ef7dbf IM |
2577 | remainder_words = 0; |
2578 | } | |
2579 | if (hci_write) { | |
2580 | status = dspxfr_hci_write(codec, hci_write); | |
b3667bd7 TI |
2581 | if (status < 0) |
2582 | return status; | |
01ef7dbf IM |
2583 | hci_write = NULL; |
2584 | } | |
6d67530e IM |
2585 | |
2586 | timeout = jiffies + msecs_to_jiffies(2000); | |
2587 | do { | |
2588 | dma_active = dsp_is_dma_active(codec, dma_chan); | |
2589 | if (!dma_active) | |
01ef7dbf | 2590 | break; |
6d67530e IM |
2591 | msleep(20); |
2592 | } while (time_before(jiffies, timeout)); | |
2593 | if (dma_active) | |
2594 | break; | |
2595 | ||
4e76a883 | 2596 | codec_dbg(codec, "+++++ DMA complete\n"); |
01ef7dbf | 2597 | dma_set_state(dma_engine, DMA_STATE_STOP); |
b3667bd7 | 2598 | status = dma_reset(dma_engine); |
01ef7dbf IM |
2599 | |
2600 | if (status < 0) | |
2601 | return status; | |
2602 | ||
2603 | data += run_size_words; | |
2604 | chip_addx += run_size_words*sizeof(u32); | |
2605 | words_to_write -= run_size_words; | |
2606 | } | |
2607 | ||
2608 | if (remainder_words != 0) { | |
2609 | status = chipio_write_multiple(codec, chip_addx_remainder, | |
2610 | data_remainder, remainder_words); | |
2611 | } | |
2612 | ||
2613 | return status; | |
95c6e9cb IM |
2614 | } |
2615 | ||
d5c21b88 IM |
2616 | /** |
2617 | * Write the entire DSP image of a DSP code/data overlay to DSP memories | |
2618 | * | |
2619 | * @codec: the HDA codec | |
2620 | * @fls_data: pointer to a fast load image | |
2621 | * @reloc: Relocation address for loading single-segment overlays, or 0 for | |
2622 | * no relocation | |
e97249dd | 2623 | * @sample_rate: sampling rate of the stream used for DSP download |
e60b2c7f | 2624 | * @channels: channels of the stream used for DSP download |
d5c21b88 IM |
2625 | * @ovly: TRUE if overlay format is required |
2626 | * | |
2627 | * Returns zero or a negative error code. | |
2628 | */ | |
01ef7dbf IM |
2629 | static int dspxfr_image(struct hda_codec *codec, |
2630 | const struct dsp_image_seg *fls_data, | |
e97249dd IM |
2631 | unsigned int reloc, |
2632 | unsigned int sample_rate, | |
2633 | unsigned short channels, | |
01ef7dbf | 2634 | bool ovly) |
95c6e9cb IM |
2635 | { |
2636 | struct ca0132_spec *spec = codec->spec; | |
01ef7dbf IM |
2637 | int status; |
2638 | unsigned short hda_format = 0; | |
2639 | unsigned int response; | |
2640 | unsigned char stream_id = 0; | |
2641 | struct dma_engine *dma_engine; | |
2642 | unsigned int dma_chan; | |
2643 | unsigned int port_map_mask; | |
2644 | ||
2645 | if (fls_data == NULL) | |
2646 | return -EINVAL; | |
2647 | ||
2648 | dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); | |
549e8292 TI |
2649 | if (!dma_engine) |
2650 | return -ENOMEM; | |
95c6e9cb | 2651 | |
01ef7dbf IM |
2652 | dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); |
2653 | if (!dma_engine->dmab) { | |
549e8292 TI |
2654 | kfree(dma_engine); |
2655 | return -ENOMEM; | |
01ef7dbf | 2656 | } |
95c6e9cb | 2657 | |
01ef7dbf | 2658 | dma_engine->codec = codec; |
6194b99d | 2659 | dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); |
01ef7dbf IM |
2660 | dma_engine->m_converter_format = hda_format; |
2661 | dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : | |
2662 | DSP_DMA_WRITE_BUFLEN_INIT) * 2; | |
2663 | ||
8ae3124b | 2664 | dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; |
01ef7dbf IM |
2665 | |
2666 | status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, | |
2667 | hda_format, &response); | |
2668 | ||
2669 | if (status < 0) { | |
4e76a883 | 2670 | codec_dbg(codec, "set converter format fail\n"); |
01ef7dbf IM |
2671 | goto exit; |
2672 | } | |
2673 | ||
2674 | status = snd_hda_codec_load_dsp_prepare(codec, | |
2675 | dma_engine->m_converter_format, | |
2676 | dma_engine->buf_size, | |
2677 | dma_engine->dmab); | |
2678 | if (status < 0) | |
95c6e9cb | 2679 | goto exit; |
01ef7dbf IM |
2680 | spec->dsp_stream_id = status; |
2681 | ||
2682 | if (ovly) { | |
2683 | status = dspio_alloc_dma_chan(codec, &dma_chan); | |
2684 | if (status < 0) { | |
4e76a883 | 2685 | codec_dbg(codec, "alloc dmachan fail\n"); |
8ae3124b | 2686 | dma_chan = INVALID_DMA_CHANNEL; |
01ef7dbf IM |
2687 | goto exit; |
2688 | } | |
2689 | } | |
95c6e9cb | 2690 | |
01ef7dbf IM |
2691 | port_map_mask = 0; |
2692 | status = dsp_allocate_ports_format(codec, hda_format, | |
2693 | &port_map_mask); | |
2694 | if (status < 0) { | |
4e76a883 | 2695 | codec_dbg(codec, "alloc ports fail\n"); |
01ef7dbf IM |
2696 | goto exit; |
2697 | } | |
2698 | ||
2699 | stream_id = dma_get_stream_id(dma_engine); | |
2700 | status = codec_set_converter_stream_channel(codec, | |
2701 | WIDGET_CHIP_CTRL, stream_id, 0, &response); | |
2702 | if (status < 0) { | |
4e76a883 | 2703 | codec_dbg(codec, "set stream chan fail\n"); |
01ef7dbf IM |
2704 | goto exit; |
2705 | } | |
2706 | ||
2707 | while ((fls_data != NULL) && !is_last(fls_data)) { | |
2708 | if (!is_valid(fls_data)) { | |
4e76a883 | 2709 | codec_dbg(codec, "FLS check fail\n"); |
01ef7dbf IM |
2710 | status = -EINVAL; |
2711 | goto exit; | |
2712 | } | |
2713 | status = dspxfr_one_seg(codec, fls_data, reloc, | |
2714 | dma_engine, dma_chan, | |
2715 | port_map_mask, ovly); | |
2716 | if (status < 0) | |
2717 | break; | |
2718 | ||
2719 | if (is_hci_prog_list_seg(fls_data)) | |
2720 | fls_data = get_next_seg_ptr(fls_data); | |
2721 | ||
2722 | if ((fls_data != NULL) && !is_last(fls_data)) | |
2723 | fls_data = get_next_seg_ptr(fls_data); | |
2724 | } | |
2725 | ||
2726 | if (port_map_mask != 0) | |
2727 | status = dsp_free_ports(codec); | |
2728 | ||
2729 | if (status < 0) | |
95c6e9cb IM |
2730 | goto exit; |
2731 | ||
01ef7dbf IM |
2732 | status = codec_set_converter_stream_channel(codec, |
2733 | WIDGET_CHIP_CTRL, 0, 0, &response); | |
2734 | ||
95c6e9cb | 2735 | exit: |
01ef7dbf IM |
2736 | if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) |
2737 | dspio_free_dma_chan(codec, dma_chan); | |
2738 | ||
b3667bd7 | 2739 | if (dma_engine->dmab->area) |
01ef7dbf IM |
2740 | snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); |
2741 | kfree(dma_engine->dmab); | |
2742 | kfree(dma_engine); | |
2743 | ||
2744 | return status; | |
95c6e9cb IM |
2745 | } |
2746 | ||
2747 | /* | |
01ef7dbf | 2748 | * CA0132 DSP download stuffs. |
95c6e9cb | 2749 | */ |
01ef7dbf | 2750 | static void dspload_post_setup(struct hda_codec *codec) |
95c6e9cb | 2751 | { |
009b8f97 | 2752 | struct ca0132_spec *spec = codec->spec; |
4e76a883 | 2753 | codec_dbg(codec, "---- dspload_post_setup ------\n"); |
009b8f97 CM |
2754 | if (!spec->use_alt_functions) { |
2755 | /*set DSP speaker to 2.0 configuration*/ | |
2756 | chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); | |
2757 | chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); | |
95c6e9cb | 2758 | |
009b8f97 CM |
2759 | /*update write pointer*/ |
2760 | chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); | |
2761 | } | |
01ef7dbf | 2762 | } |
95c6e9cb | 2763 | |
d5c21b88 | 2764 | /** |
e60b2c7f | 2765 | * dspload_image - Download DSP from a DSP Image Fast Load structure. |
d5c21b88 IM |
2766 | * |
2767 | * @codec: the HDA codec | |
2768 | * @fls: pointer to a fast load image | |
2769 | * @ovly: TRUE if overlay format is required | |
2770 | * @reloc: Relocation address for loading single-segment overlays, or 0 for | |
2771 | * no relocation | |
2772 | * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE | |
2773 | * @router_chans: number of audio router channels to be allocated (0 means use | |
2774 | * internal defaults; max is 32) | |
2775 | * | |
e60b2c7f TI |
2776 | * Download DSP from a DSP Image Fast Load structure. This structure is a |
2777 | * linear, non-constant sized element array of structures, each of which | |
2778 | * contain the count of the data to be loaded, the data itself, and the | |
2779 | * corresponding starting chip address of the starting data location. | |
d5c21b88 IM |
2780 | * Returns zero or a negative error code. |
2781 | */ | |
01ef7dbf IM |
2782 | static int dspload_image(struct hda_codec *codec, |
2783 | const struct dsp_image_seg *fls, | |
2784 | bool ovly, | |
2785 | unsigned int reloc, | |
2786 | bool autostart, | |
2787 | int router_chans) | |
2788 | { | |
2789 | int status = 0; | |
e97249dd IM |
2790 | unsigned int sample_rate; |
2791 | unsigned short channels; | |
01ef7dbf | 2792 | |
4e76a883 | 2793 | codec_dbg(codec, "---- dspload_image begin ------\n"); |
01ef7dbf IM |
2794 | if (router_chans == 0) { |
2795 | if (!ovly) | |
2796 | router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; | |
2797 | else | |
2798 | router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; | |
2799 | } | |
95c6e9cb | 2800 | |
e97249dd IM |
2801 | sample_rate = 48000; |
2802 | channels = (unsigned short)router_chans; | |
01ef7dbf | 2803 | |
e97249dd IM |
2804 | while (channels > 16) { |
2805 | sample_rate *= 2; | |
2806 | channels /= 2; | |
01ef7dbf IM |
2807 | } |
2808 | ||
01ef7dbf | 2809 | do { |
4e76a883 | 2810 | codec_dbg(codec, "Ready to program DMA\n"); |
01ef7dbf IM |
2811 | if (!ovly) |
2812 | status = dsp_reset(codec); | |
2813 | ||
2814 | if (status < 0) | |
2815 | break; | |
2816 | ||
4e76a883 | 2817 | codec_dbg(codec, "dsp_reset() complete\n"); |
e97249dd IM |
2818 | status = dspxfr_image(codec, fls, reloc, sample_rate, channels, |
2819 | ovly); | |
01ef7dbf IM |
2820 | |
2821 | if (status < 0) | |
2822 | break; | |
2823 | ||
4e76a883 | 2824 | codec_dbg(codec, "dspxfr_image() complete\n"); |
01ef7dbf IM |
2825 | if (autostart && !ovly) { |
2826 | dspload_post_setup(codec); | |
2827 | status = dsp_set_run_state(codec); | |
2828 | } | |
2829 | ||
4e76a883 | 2830 | codec_dbg(codec, "LOAD FINISHED\n"); |
01ef7dbf IM |
2831 | } while (0); |
2832 | ||
2833 | return status; | |
2834 | } | |
2835 | ||
f664417e | 2836 | #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP |
01ef7dbf IM |
2837 | static bool dspload_is_loaded(struct hda_codec *codec) |
2838 | { | |
2839 | unsigned int data = 0; | |
2840 | int status = 0; | |
2841 | ||
2842 | status = chipio_read(codec, 0x40004, &data); | |
2843 | if ((status < 0) || (data != 1)) | |
2844 | return false; | |
2845 | ||
2846 | return true; | |
2847 | } | |
f664417e TI |
2848 | #else |
2849 | #define dspload_is_loaded(codec) false | |
2850 | #endif | |
01ef7dbf IM |
2851 | |
2852 | static bool dspload_wait_loaded(struct hda_codec *codec) | |
2853 | { | |
6d67530e | 2854 | unsigned long timeout = jiffies + msecs_to_jiffies(2000); |
01ef7dbf IM |
2855 | |
2856 | do { | |
01ef7dbf | 2857 | if (dspload_is_loaded(codec)) { |
d9684bb5 | 2858 | codec_info(codec, "ca0132 DSP downloaded and running\n"); |
01ef7dbf IM |
2859 | return true; |
2860 | } | |
6d67530e IM |
2861 | msleep(20); |
2862 | } while (time_before(jiffies, timeout)); | |
01ef7dbf | 2863 | |
d9684bb5 | 2864 | codec_err(codec, "ca0132 failed to download DSP\n"); |
01ef7dbf | 2865 | return false; |
95c6e9cb IM |
2866 | } |
2867 | ||
e93ac30a CM |
2868 | /* |
2869 | * Setup GPIO for the other variants of Core3D. | |
2870 | */ | |
2871 | ||
2872 | /* | |
2873 | * Sets up the GPIO pins so that they are discoverable. If this isn't done, | |
2874 | * the card shows as having no GPIO pins. | |
2875 | */ | |
2876 | static void ca0132_gpio_init(struct hda_codec *codec) | |
2877 | { | |
2878 | struct ca0132_spec *spec = codec->spec; | |
2879 | ||
2880 | switch (spec->quirk) { | |
2881 | case QUIRK_SBZ: | |
2882 | snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); | |
2883 | snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); | |
2884 | snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); | |
2885 | break; | |
2886 | case QUIRK_R3DI: | |
2887 | snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); | |
2888 | snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); | |
2889 | break; | |
2890 | } | |
2891 | ||
2892 | } | |
2893 | ||
2894 | /* Sets the GPIO for audio output. */ | |
2895 | static void ca0132_gpio_setup(struct hda_codec *codec) | |
2896 | { | |
2897 | struct ca0132_spec *spec = codec->spec; | |
2898 | ||
2899 | switch (spec->quirk) { | |
2900 | case QUIRK_SBZ: | |
2901 | snd_hda_codec_write(codec, 0x01, 0, | |
2902 | AC_VERB_SET_GPIO_DIRECTION, 0x07); | |
2903 | snd_hda_codec_write(codec, 0x01, 0, | |
2904 | AC_VERB_SET_GPIO_MASK, 0x07); | |
2905 | snd_hda_codec_write(codec, 0x01, 0, | |
2906 | AC_VERB_SET_GPIO_DATA, 0x04); | |
2907 | snd_hda_codec_write(codec, 0x01, 0, | |
2908 | AC_VERB_SET_GPIO_DATA, 0x06); | |
2909 | break; | |
2910 | case QUIRK_R3DI: | |
2911 | snd_hda_codec_write(codec, 0x01, 0, | |
2912 | AC_VERB_SET_GPIO_DIRECTION, 0x1E); | |
2913 | snd_hda_codec_write(codec, 0x01, 0, | |
2914 | AC_VERB_SET_GPIO_MASK, 0x1F); | |
2915 | snd_hda_codec_write(codec, 0x01, 0, | |
2916 | AC_VERB_SET_GPIO_DATA, 0x0C); | |
2917 | break; | |
2918 | } | |
2919 | } | |
2920 | ||
7e6ed62e CM |
2921 | /* |
2922 | * GPIO control functions for the Recon3D integrated. | |
2923 | */ | |
2924 | ||
2925 | enum r3di_gpio_bit { | |
2926 | /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ | |
2927 | R3DI_MIC_SELECT_BIT = 1, | |
2928 | /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ | |
2929 | R3DI_OUT_SELECT_BIT = 2, | |
2930 | /* | |
2931 | * I dunno what this actually does, but it stays on until the dsp | |
2932 | * is downloaded. | |
2933 | */ | |
2934 | R3DI_GPIO_DSP_DOWNLOADING = 3, | |
2935 | /* | |
2936 | * Same as above, no clue what it does, but it comes on after the dsp | |
2937 | * is downloaded. | |
2938 | */ | |
2939 | R3DI_GPIO_DSP_DOWNLOADED = 4 | |
2940 | }; | |
2941 | ||
2942 | enum r3di_mic_select { | |
2943 | /* Set GPIO bit 1 to 0 for rear mic */ | |
2944 | R3DI_REAR_MIC = 0, | |
2945 | /* Set GPIO bit 1 to 1 for front microphone*/ | |
2946 | R3DI_FRONT_MIC = 1 | |
2947 | }; | |
2948 | ||
2949 | enum r3di_out_select { | |
2950 | /* Set GPIO bit 2 to 0 for headphone */ | |
2951 | R3DI_HEADPHONE_OUT = 0, | |
2952 | /* Set GPIO bit 2 to 1 for speaker */ | |
2953 | R3DI_LINE_OUT = 1 | |
2954 | }; | |
2955 | enum r3di_dsp_status { | |
2956 | /* Set GPIO bit 3 to 1 until DSP is downloaded */ | |
2957 | R3DI_DSP_DOWNLOADING = 0, | |
2958 | /* Set GPIO bit 4 to 1 once DSP is downloaded */ | |
2959 | R3DI_DSP_DOWNLOADED = 1 | |
2960 | }; | |
2961 | ||
2962 | static void r3di_gpio_dsp_status_set(struct hda_codec *codec, | |
2963 | enum r3di_dsp_status dsp_status) | |
2964 | { | |
2965 | unsigned int cur_gpio; | |
2966 | ||
2967 | /* Get the current GPIO Data setup */ | |
2968 | cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); | |
2969 | ||
2970 | switch (dsp_status) { | |
2971 | case R3DI_DSP_DOWNLOADING: | |
2972 | cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); | |
2973 | snd_hda_codec_write(codec, codec->core.afg, 0, | |
2974 | AC_VERB_SET_GPIO_DATA, cur_gpio); | |
2975 | break; | |
2976 | case R3DI_DSP_DOWNLOADED: | |
2977 | /* Set DOWNLOADING bit to 0. */ | |
2978 | cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); | |
2979 | ||
2980 | snd_hda_codec_write(codec, codec->core.afg, 0, | |
2981 | AC_VERB_SET_GPIO_DATA, cur_gpio); | |
2982 | ||
2983 | cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); | |
2984 | break; | |
2985 | } | |
2986 | ||
2987 | snd_hda_codec_write(codec, codec->core.afg, 0, | |
2988 | AC_VERB_SET_GPIO_DATA, cur_gpio); | |
2989 | } | |
2990 | ||
825315bc IM |
2991 | /* |
2992 | * PCM callbacks | |
2993 | */ | |
95c6e9cb IM |
2994 | static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, |
2995 | struct hda_codec *codec, | |
2996 | unsigned int stream_tag, | |
2997 | unsigned int format, | |
2998 | struct snd_pcm_substream *substream) | |
2999 | { | |
3000 | struct ca0132_spec *spec = codec->spec; | |
825315bc | 3001 | |
28fba950 | 3002 | snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); |
825315bc IM |
3003 | |
3004 | return 0; | |
95c6e9cb IM |
3005 | } |
3006 | ||
3007 | static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, | |
3008 | struct hda_codec *codec, | |
3009 | struct snd_pcm_substream *substream) | |
3010 | { | |
3011 | struct ca0132_spec *spec = codec->spec; | |
825315bc IM |
3012 | |
3013 | if (spec->dsp_state == DSP_DOWNLOADING) | |
3014 | return 0; | |
3015 | ||
3016 | /*If Playback effects are on, allow stream some time to flush | |
3017 | *effects tail*/ | |
3018 | if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) | |
3019 | msleep(50); | |
3020 | ||
28fba950 | 3021 | snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); |
825315bc IM |
3022 | |
3023 | return 0; | |
95c6e9cb IM |
3024 | } |
3025 | ||
e8412ca4 DR |
3026 | static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, |
3027 | struct hda_codec *codec, | |
3028 | struct snd_pcm_substream *substream) | |
3029 | { | |
3030 | struct ca0132_spec *spec = codec->spec; | |
3031 | unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; | |
3032 | struct snd_pcm_runtime *runtime = substream->runtime; | |
3033 | ||
3034 | if (spec->dsp_state != DSP_DOWNLOADED) | |
3035 | return 0; | |
3036 | ||
3037 | /* Add latency if playback enhancement and either effect is enabled. */ | |
3038 | if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { | |
3039 | if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || | |
3040 | (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) | |
3041 | latency += DSP_PLAY_ENHANCEMENT_LATENCY; | |
3042 | } | |
3043 | ||
3044 | /* Applying Speaker EQ adds latency as well. */ | |
3045 | if (spec->cur_out_type == SPEAKER_OUT) | |
3046 | latency += DSP_SPEAKER_OUT_LATENCY; | |
3047 | ||
3048 | return (latency * runtime->rate) / 1000; | |
3049 | } | |
3050 | ||
95c6e9cb IM |
3051 | /* |
3052 | * Digital out | |
3053 | */ | |
27ebeb0b TI |
3054 | static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, |
3055 | struct hda_codec *codec, | |
3056 | struct snd_pcm_substream *substream) | |
95c6e9cb IM |
3057 | { |
3058 | struct ca0132_spec *spec = codec->spec; | |
27ebeb0b | 3059 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); |
95c6e9cb IM |
3060 | } |
3061 | ||
27ebeb0b | 3062 | static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, |
95c6e9cb IM |
3063 | struct hda_codec *codec, |
3064 | unsigned int stream_tag, | |
3065 | unsigned int format, | |
3066 | struct snd_pcm_substream *substream) | |
3067 | { | |
3068 | struct ca0132_spec *spec = codec->spec; | |
27ebeb0b TI |
3069 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, |
3070 | stream_tag, format, substream); | |
95c6e9cb IM |
3071 | } |
3072 | ||
27ebeb0b | 3073 | static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
95c6e9cb | 3074 | struct hda_codec *codec, |
95c6e9cb IM |
3075 | struct snd_pcm_substream *substream) |
3076 | { | |
3077 | struct ca0132_spec *spec = codec->spec; | |
27ebeb0b | 3078 | return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); |
95c6e9cb IM |
3079 | } |
3080 | ||
27ebeb0b TI |
3081 | static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, |
3082 | struct hda_codec *codec, | |
3083 | struct snd_pcm_substream *substream) | |
95c6e9cb IM |
3084 | { |
3085 | struct ca0132_spec *spec = codec->spec; | |
27ebeb0b | 3086 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); |
95c6e9cb IM |
3087 | } |
3088 | ||
825315bc IM |
3089 | /* |
3090 | * Analog capture | |
3091 | */ | |
3092 | static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3093 | struct hda_codec *codec, | |
3094 | unsigned int stream_tag, | |
3095 | unsigned int format, | |
3096 | struct snd_pcm_substream *substream) | |
3097 | { | |
13c12dbe | 3098 | snd_hda_codec_setup_stream(codec, hinfo->nid, |
28fba950 | 3099 | stream_tag, 0, format); |
825315bc IM |
3100 | |
3101 | return 0; | |
3102 | } | |
3103 | ||
3104 | static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, | |
3105 | struct hda_codec *codec, | |
3106 | struct snd_pcm_substream *substream) | |
3107 | { | |
3108 | struct ca0132_spec *spec = codec->spec; | |
3109 | ||
3110 | if (spec->dsp_state == DSP_DOWNLOADING) | |
3111 | return 0; | |
3112 | ||
28fba950 | 3113 | snd_hda_codec_cleanup_stream(codec, hinfo->nid); |
825315bc IM |
3114 | return 0; |
3115 | } | |
3116 | ||
e8412ca4 DR |
3117 | static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, |
3118 | struct hda_codec *codec, | |
3119 | struct snd_pcm_substream *substream) | |
3120 | { | |
3121 | struct ca0132_spec *spec = codec->spec; | |
3122 | unsigned int latency = DSP_CAPTURE_INIT_LATENCY; | |
3123 | struct snd_pcm_runtime *runtime = substream->runtime; | |
3124 | ||
3125 | if (spec->dsp_state != DSP_DOWNLOADED) | |
3126 | return 0; | |
3127 | ||
3128 | if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) | |
3129 | latency += DSP_CRYSTAL_VOICE_LATENCY; | |
3130 | ||
3131 | return (latency * runtime->rate) / 1000; | |
3132 | } | |
3133 | ||
e90f29e4 IM |
3134 | /* |
3135 | * Controls stuffs. | |
3136 | */ | |
3137 | ||
3138 | /* | |
3139 | * Mixer controls helpers. | |
3140 | */ | |
3141 | #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ | |
3142 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3143 | .name = xname, \ | |
3144 | .subdevice = HDA_SUBDEV_AMP_FLAG, \ | |
3145 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ | |
3146 | SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ | |
3147 | SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ | |
3148 | .info = ca0132_volume_info, \ | |
3149 | .get = ca0132_volume_get, \ | |
3150 | .put = ca0132_volume_put, \ | |
3151 | .tlv = { .c = ca0132_volume_tlv }, \ | |
3152 | .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } | |
3153 | ||
3154 | #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ | |
3155 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3156 | .name = xname, \ | |
3157 | .subdevice = HDA_SUBDEV_AMP_FLAG, \ | |
3158 | .info = snd_hda_mixer_amp_switch_info, \ | |
3159 | .get = ca0132_switch_get, \ | |
3160 | .put = ca0132_switch_put, \ | |
3161 | .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } | |
3162 | ||
3163 | /* stereo */ | |
3164 | #define CA0132_CODEC_VOL(xname, nid, dir) \ | |
3165 | CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) | |
3166 | #define CA0132_CODEC_MUTE(xname, nid, dir) \ | |
3167 | CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) | |
3168 | ||
4091fb95 | 3169 | /* The following are for tuning of products */ |
44f0c978 IM |
3170 | #ifdef ENABLE_TUNING_CONTROLS |
3171 | ||
3172 | static unsigned int voice_focus_vals_lookup[] = { | |
3173 | 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, | |
3174 | 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, | |
3175 | 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, | |
3176 | 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, | |
3177 | 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, | |
3178 | 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, | |
3179 | 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, | |
3180 | 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, | |
3181 | 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, | |
3182 | 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, | |
3183 | 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, | |
3184 | 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, | |
3185 | 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, | |
3186 | 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, | |
3187 | 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, | |
3188 | 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, | |
3189 | 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, | |
3190 | 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, | |
3191 | 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, | |
3192 | 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, | |
3193 | 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, | |
3194 | 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, | |
3195 | 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, | |
3196 | 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, | |
3197 | 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, | |
3198 | 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, | |
3199 | 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 | |
3200 | }; | |
3201 | ||
3202 | static unsigned int mic_svm_vals_lookup[] = { | |
3203 | 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, | |
3204 | 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, | |
3205 | 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, | |
3206 | 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, | |
3207 | 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, | |
3208 | 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, | |
3209 | 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, | |
3210 | 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, | |
3211 | 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, | |
3212 | 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, | |
3213 | 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, | |
3214 | 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, | |
3215 | 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, | |
3216 | 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, | |
3217 | 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, | |
3218 | 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, | |
3219 | 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 | |
3220 | }; | |
3221 | ||
3222 | static unsigned int equalizer_vals_lookup[] = { | |
3223 | 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, | |
3224 | 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, | |
3225 | 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, | |
3226 | 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, | |
3227 | 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, | |
3228 | 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, | |
3229 | 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, | |
3230 | 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, | |
3231 | 0x41C00000 | |
3232 | }; | |
3233 | ||
3234 | static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, | |
3235 | unsigned int *lookup, int idx) | |
3236 | { | |
3237 | int i = 0; | |
3238 | ||
3239 | for (i = 0; i < TUNING_CTLS_COUNT; i++) | |
3240 | if (nid == ca0132_tuning_ctls[i].nid) | |
3241 | break; | |
3242 | ||
3243 | snd_hda_power_up(codec); | |
447fd8e9 | 3244 | dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, |
44f0c978 IM |
3245 | ca0132_tuning_ctls[i].req, |
3246 | &(lookup[idx]), sizeof(unsigned int)); | |
3247 | snd_hda_power_down(codec); | |
3248 | ||
3249 | return 1; | |
3250 | } | |
3251 | ||
3252 | static int tuning_ctl_get(struct snd_kcontrol *kcontrol, | |
3253 | struct snd_ctl_elem_value *ucontrol) | |
3254 | { | |
3255 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
3256 | struct ca0132_spec *spec = codec->spec; | |
3257 | hda_nid_t nid = get_amp_nid(kcontrol); | |
3258 | long *valp = ucontrol->value.integer.value; | |
3259 | int idx = nid - TUNING_CTL_START_NID; | |
3260 | ||
3261 | *valp = spec->cur_ctl_vals[idx]; | |
3262 | return 0; | |
3263 | } | |
3264 | ||
3265 | static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, | |
3266 | struct snd_ctl_elem_info *uinfo) | |
3267 | { | |
3268 | int chs = get_amp_channels(kcontrol); | |
3269 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3270 | uinfo->count = chs == 3 ? 2 : 1; | |
3271 | uinfo->value.integer.min = 20; | |
3272 | uinfo->value.integer.max = 180; | |
3273 | uinfo->value.integer.step = 1; | |
3274 | ||
3275 | return 0; | |
3276 | } | |
3277 | ||
3278 | static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, | |
3279 | struct snd_ctl_elem_value *ucontrol) | |
3280 | { | |
3281 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
3282 | struct ca0132_spec *spec = codec->spec; | |
3283 | hda_nid_t nid = get_amp_nid(kcontrol); | |
3284 | long *valp = ucontrol->value.integer.value; | |
3285 | int idx; | |
3286 | ||
3287 | idx = nid - TUNING_CTL_START_NID; | |
3288 | /* any change? */ | |
3289 | if (spec->cur_ctl_vals[idx] == *valp) | |
3290 | return 0; | |
3291 | ||
3292 | spec->cur_ctl_vals[idx] = *valp; | |
3293 | ||
3294 | idx = *valp - 20; | |
3295 | tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); | |
3296 | ||
3297 | return 1; | |
3298 | } | |
3299 | ||
3300 | static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, | |
3301 | struct snd_ctl_elem_info *uinfo) | |
3302 | { | |
3303 | int chs = get_amp_channels(kcontrol); | |
3304 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3305 | uinfo->count = chs == 3 ? 2 : 1; | |
3306 | uinfo->value.integer.min = 0; | |
3307 | uinfo->value.integer.max = 100; | |
3308 | uinfo->value.integer.step = 1; | |
3309 | ||
3310 | return 0; | |
3311 | } | |
3312 | ||
3313 | static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, | |
3314 | struct snd_ctl_elem_value *ucontrol) | |
3315 | { | |
3316 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
3317 | struct ca0132_spec *spec = codec->spec; | |
3318 | hda_nid_t nid = get_amp_nid(kcontrol); | |
3319 | long *valp = ucontrol->value.integer.value; | |
3320 | int idx; | |
3321 | ||
3322 | idx = nid - TUNING_CTL_START_NID; | |
3323 | /* any change? */ | |
3324 | if (spec->cur_ctl_vals[idx] == *valp) | |
3325 | return 0; | |
3326 | ||
3327 | spec->cur_ctl_vals[idx] = *valp; | |
3328 | ||
3329 | idx = *valp; | |
3330 | tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); | |
3331 | ||
3332 | return 0; | |
3333 | } | |
3334 | ||
3335 | static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, | |
3336 | struct snd_ctl_elem_info *uinfo) | |
3337 | { | |
3338 | int chs = get_amp_channels(kcontrol); | |
3339 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3340 | uinfo->count = chs == 3 ? 2 : 1; | |
3341 | uinfo->value.integer.min = 0; | |
3342 | uinfo->value.integer.max = 48; | |
3343 | uinfo->value.integer.step = 1; | |
3344 | ||
3345 | return 0; | |
3346 | } | |
3347 | ||
3348 | static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, | |
3349 | struct snd_ctl_elem_value *ucontrol) | |
3350 | { | |
3351 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
3352 | struct ca0132_spec *spec = codec->spec; | |
3353 | hda_nid_t nid = get_amp_nid(kcontrol); | |
3354 | long *valp = ucontrol->value.integer.value; | |
3355 | int idx; | |
3356 | ||
3357 | idx = nid - TUNING_CTL_START_NID; | |
3358 | /* any change? */ | |
3359 | if (spec->cur_ctl_vals[idx] == *valp) | |
3360 | return 0; | |
3361 | ||
3362 | spec->cur_ctl_vals[idx] = *valp; | |
3363 | ||
3364 | idx = *valp; | |
3365 | tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); | |
3366 | ||
3367 | return 1; | |
3368 | } | |
3369 | ||
8e142e9e TS |
3370 | static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); |
3371 | static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); | |
44f0c978 IM |
3372 | |
3373 | static int add_tuning_control(struct hda_codec *codec, | |
3374 | hda_nid_t pnid, hda_nid_t nid, | |
3375 | const char *name, int dir) | |
3376 | { | |
975cc02a | 3377 | char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; |
44f0c978 IM |
3378 | int type = dir ? HDA_INPUT : HDA_OUTPUT; |
3379 | struct snd_kcontrol_new knew = | |
3380 | HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); | |
3381 | ||
3382 | knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | | |
3383 | SNDRV_CTL_ELEM_ACCESS_TLV_READ; | |
3384 | knew.tlv.c = 0; | |
3385 | knew.tlv.p = 0; | |
3386 | switch (pnid) { | |
3387 | case VOICE_FOCUS: | |
3388 | knew.info = voice_focus_ctl_info; | |
3389 | knew.get = tuning_ctl_get; | |
3390 | knew.put = voice_focus_ctl_put; | |
3391 | knew.tlv.p = voice_focus_db_scale; | |
3392 | break; | |
3393 | case MIC_SVM: | |
3394 | knew.info = mic_svm_ctl_info; | |
3395 | knew.get = tuning_ctl_get; | |
3396 | knew.put = mic_svm_ctl_put; | |
3397 | break; | |
3398 | case EQUALIZER: | |
3399 | knew.info = equalizer_ctl_info; | |
3400 | knew.get = tuning_ctl_get; | |
3401 | knew.put = equalizer_ctl_put; | |
3402 | knew.tlv.p = eq_db_scale; | |
3403 | break; | |
3404 | default: | |
3405 | return 0; | |
3406 | } | |
3407 | knew.private_value = | |
3408 | HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); | |
3409 | sprintf(namestr, "%s %s Volume", name, dirstr[dir]); | |
3410 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); | |
3411 | } | |
3412 | ||
3413 | static int add_tuning_ctls(struct hda_codec *codec) | |
3414 | { | |
3415 | int i; | |
3416 | int err; | |
3417 | ||
3418 | for (i = 0; i < TUNING_CTLS_COUNT; i++) { | |
3419 | err = add_tuning_control(codec, | |
3420 | ca0132_tuning_ctls[i].parent_nid, | |
3421 | ca0132_tuning_ctls[i].nid, | |
3422 | ca0132_tuning_ctls[i].name, | |
3423 | ca0132_tuning_ctls[i].direct); | |
3424 | if (err < 0) | |
3425 | return err; | |
3426 | } | |
3427 | ||
3428 | return 0; | |
3429 | } | |
3430 | ||
3431 | static void ca0132_init_tuning_defaults(struct hda_codec *codec) | |
3432 | { | |
3433 | struct ca0132_spec *spec = codec->spec; | |
3434 | int i; | |
3435 | ||
3436 | /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ | |
3437 | spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; | |
3438 | /* SVM level defaults to 0.74. */ | |
3439 | spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; | |
3440 | ||
3441 | /* EQ defaults to 0dB. */ | |
3442 | for (i = 2; i < TUNING_CTLS_COUNT; i++) | |
3443 | spec->cur_ctl_vals[i] = 24; | |
3444 | } | |
3445 | #endif /*ENABLE_TUNING_CONTROLS*/ | |
3446 | ||
5aaca44d IM |
3447 | /* |
3448 | * Select the active output. | |
3449 | * If autodetect is enabled, output will be selected based on jack detection. | |
3450 | * If jack inserted, headphone will be selected, else built-in speakers | |
3451 | * If autodetect is disabled, output will be selected based on selection. | |
3452 | */ | |
3453 | static int ca0132_select_out(struct hda_codec *codec) | |
3454 | { | |
3455 | struct ca0132_spec *spec = codec->spec; | |
3456 | unsigned int pin_ctl; | |
3457 | int jack_present; | |
3458 | int auto_jack; | |
3459 | unsigned int tmp; | |
3460 | int err; | |
3461 | ||
4e76a883 | 3462 | codec_dbg(codec, "ca0132_select_out\n"); |
5aaca44d | 3463 | |
664c7155 | 3464 | snd_hda_power_up_pm(codec); |
5aaca44d IM |
3465 | |
3466 | auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; | |
3467 | ||
3468 | if (auto_jack) | |
fe14f39e | 3469 | jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); |
5aaca44d IM |
3470 | else |
3471 | jack_present = | |
3472 | spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; | |
3473 | ||
3474 | if (jack_present) | |
3475 | spec->cur_out_type = HEADPHONE_OUT; | |
3476 | else | |
3477 | spec->cur_out_type = SPEAKER_OUT; | |
3478 | ||
3479 | if (spec->cur_out_type == SPEAKER_OUT) { | |
4e76a883 | 3480 | codec_dbg(codec, "ca0132_select_out speaker\n"); |
5aaca44d IM |
3481 | /*speaker out config*/ |
3482 | tmp = FLOAT_ONE; | |
3483 | err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); | |
3484 | if (err < 0) | |
3485 | goto exit; | |
3486 | /*enable speaker EQ*/ | |
3487 | tmp = FLOAT_ONE; | |
3488 | err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); | |
3489 | if (err < 0) | |
3490 | goto exit; | |
3491 | ||
3492 | /* Setup EAPD */ | |
3493 | snd_hda_codec_write(codec, spec->out_pins[1], 0, | |
3494 | VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); | |
3495 | snd_hda_codec_write(codec, spec->out_pins[0], 0, | |
3496 | AC_VERB_SET_EAPD_BTLENABLE, 0x00); | |
3497 | snd_hda_codec_write(codec, spec->out_pins[0], 0, | |
3498 | VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); | |
3499 | snd_hda_codec_write(codec, spec->out_pins[0], 0, | |
3500 | AC_VERB_SET_EAPD_BTLENABLE, 0x02); | |
3501 | ||
3502 | /* disable headphone node */ | |
3503 | pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, | |
3504 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
a0c041cb TI |
3505 | snd_hda_set_pin_ctl(codec, spec->out_pins[1], |
3506 | pin_ctl & ~PIN_HP); | |
5aaca44d IM |
3507 | /* enable speaker node */ |
3508 | pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, | |
8a19bcee | 3509 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
a0c041cb TI |
3510 | snd_hda_set_pin_ctl(codec, spec->out_pins[0], |
3511 | pin_ctl | PIN_OUT); | |
5aaca44d | 3512 | } else { |
4e76a883 | 3513 | codec_dbg(codec, "ca0132_select_out hp\n"); |
5aaca44d IM |
3514 | /*headphone out config*/ |
3515 | tmp = FLOAT_ZERO; | |
3516 | err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); | |
3517 | if (err < 0) | |
3518 | goto exit; | |
3519 | /*disable speaker EQ*/ | |
3520 | tmp = FLOAT_ZERO; | |
3521 | err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); | |
3522 | if (err < 0) | |
3523 | goto exit; | |
3524 | ||
3525 | /* Setup EAPD */ | |
3526 | snd_hda_codec_write(codec, spec->out_pins[0], 0, | |
3527 | VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); | |
3528 | snd_hda_codec_write(codec, spec->out_pins[0], 0, | |
3529 | AC_VERB_SET_EAPD_BTLENABLE, 0x00); | |
3530 | snd_hda_codec_write(codec, spec->out_pins[1], 0, | |
3531 | VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); | |
3532 | snd_hda_codec_write(codec, spec->out_pins[0], 0, | |
3533 | AC_VERB_SET_EAPD_BTLENABLE, 0x02); | |
3534 | ||
3535 | /* disable speaker*/ | |
3536 | pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, | |
3537 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
a0c041cb TI |
3538 | snd_hda_set_pin_ctl(codec, spec->out_pins[0], |
3539 | pin_ctl & ~PIN_HP); | |
5aaca44d IM |
3540 | /* enable headphone*/ |
3541 | pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, | |
3542 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
a0c041cb TI |
3543 | snd_hda_set_pin_ctl(codec, spec->out_pins[1], |
3544 | pin_ctl | PIN_HP); | |
5aaca44d IM |
3545 | } |
3546 | ||
3547 | exit: | |
664c7155 | 3548 | snd_hda_power_down_pm(codec); |
5aaca44d IM |
3549 | |
3550 | return err < 0 ? err : 0; | |
3551 | } | |
3552 | ||
993884f6 CCC |
3553 | static void ca0132_unsol_hp_delayed(struct work_struct *work) |
3554 | { | |
3555 | struct ca0132_spec *spec = container_of( | |
3556 | to_delayed_work(work), struct ca0132_spec, unsol_hp_work); | |
f8fb1170 TI |
3557 | struct hda_jack_tbl *jack; |
3558 | ||
993884f6 | 3559 | ca0132_select_out(spec->codec); |
d5c016b5 | 3560 | jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); |
f8fb1170 TI |
3561 | if (jack) { |
3562 | jack->block_report = 0; | |
3563 | snd_hda_jack_report_sync(spec->codec); | |
3564 | } | |
993884f6 CCC |
3565 | } |
3566 | ||
5aaca44d IM |
3567 | static void ca0132_set_dmic(struct hda_codec *codec, int enable); |
3568 | static int ca0132_mic_boost_set(struct hda_codec *codec, long val); | |
3569 | static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); | |
3570 | ||
3571 | /* | |
3572 | * Select the active VIP source | |
3573 | */ | |
3574 | static int ca0132_set_vipsource(struct hda_codec *codec, int val) | |
3575 | { | |
3576 | struct ca0132_spec *spec = codec->spec; | |
3577 | unsigned int tmp; | |
3578 | ||
e8f1bd5d | 3579 | if (spec->dsp_state != DSP_DOWNLOADED) |
5aaca44d IM |
3580 | return 0; |
3581 | ||
3582 | /* if CrystalVoice if off, vipsource should be 0 */ | |
3583 | if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || | |
3584 | (val == 0)) { | |
3585 | chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); | |
3586 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); | |
3587 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); | |
3588 | if (spec->cur_mic_type == DIGITAL_MIC) | |
3589 | tmp = FLOAT_TWO; | |
3590 | else | |
3591 | tmp = FLOAT_ONE; | |
3592 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); | |
3593 | tmp = FLOAT_ZERO; | |
3594 | dspio_set_uint_param(codec, 0x80, 0x05, tmp); | |
3595 | } else { | |
3596 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); | |
3597 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); | |
3598 | if (spec->cur_mic_type == DIGITAL_MIC) | |
3599 | tmp = FLOAT_TWO; | |
3600 | else | |
3601 | tmp = FLOAT_ONE; | |
3602 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); | |
3603 | tmp = FLOAT_ONE; | |
3604 | dspio_set_uint_param(codec, 0x80, 0x05, tmp); | |
3605 | msleep(20); | |
3606 | chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); | |
3607 | } | |
3608 | ||
3609 | return 1; | |
3610 | } | |
3611 | ||
3612 | /* | |
3613 | * Select the active microphone. | |
3614 | * If autodetect is enabled, mic will be selected based on jack detection. | |
3615 | * If jack inserted, ext.mic will be selected, else built-in mic | |
3616 | * If autodetect is disabled, mic will be selected based on selection. | |
3617 | */ | |
3618 | static int ca0132_select_mic(struct hda_codec *codec) | |
3619 | { | |
3620 | struct ca0132_spec *spec = codec->spec; | |
3621 | int jack_present; | |
3622 | int auto_jack; | |
3623 | ||
4e76a883 | 3624 | codec_dbg(codec, "ca0132_select_mic\n"); |
5aaca44d | 3625 | |
664c7155 | 3626 | snd_hda_power_up_pm(codec); |
5aaca44d IM |
3627 | |
3628 | auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; | |
3629 | ||
3630 | if (auto_jack) | |
fe14f39e | 3631 | jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); |
5aaca44d IM |
3632 | else |
3633 | jack_present = | |
3634 | spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; | |
3635 | ||
3636 | if (jack_present) | |
3637 | spec->cur_mic_type = LINE_MIC_IN; | |
3638 | else | |
3639 | spec->cur_mic_type = DIGITAL_MIC; | |
3640 | ||
3641 | if (spec->cur_mic_type == DIGITAL_MIC) { | |
3642 | /* enable digital Mic */ | |
3643 | chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); | |
3644 | ca0132_set_dmic(codec, 1); | |
3645 | ca0132_mic_boost_set(codec, 0); | |
3646 | /* set voice focus */ | |
3647 | ca0132_effects_set(codec, VOICE_FOCUS, | |
3648 | spec->effects_switch | |
3649 | [VOICE_FOCUS - EFFECT_START_NID]); | |
3650 | } else { | |
3651 | /* disable digital Mic */ | |
3652 | chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); | |
3653 | ca0132_set_dmic(codec, 0); | |
3654 | ca0132_mic_boost_set(codec, spec->cur_mic_boost); | |
3655 | /* disable voice focus */ | |
3656 | ca0132_effects_set(codec, VOICE_FOCUS, 0); | |
3657 | } | |
3658 | ||
664c7155 | 3659 | snd_hda_power_down_pm(codec); |
5aaca44d IM |
3660 | |
3661 | return 0; | |
3662 | } | |
3663 | ||
a7e76271 IM |
3664 | /* |
3665 | * Check if VNODE settings take effect immediately. | |
3666 | */ | |
3667 | static bool ca0132_is_vnode_effective(struct hda_codec *codec, | |
3668 | hda_nid_t vnid, | |
3669 | hda_nid_t *shared_nid) | |
3670 | { | |
3671 | struct ca0132_spec *spec = codec->spec; | |
3672 | hda_nid_t nid; | |
a7e76271 IM |
3673 | |
3674 | switch (vnid) { | |
3675 | case VNID_SPK: | |
3676 | nid = spec->shared_out_nid; | |
a7e76271 IM |
3677 | break; |
3678 | case VNID_MIC: | |
3679 | nid = spec->shared_mic_nid; | |
a7e76271 IM |
3680 | break; |
3681 | default: | |
9a0869f4 | 3682 | return false; |
a7e76271 IM |
3683 | } |
3684 | ||
9a0869f4 | 3685 | if (shared_nid) |
a7e76271 IM |
3686 | *shared_nid = nid; |
3687 | ||
9a0869f4 | 3688 | return true; |
a7e76271 IM |
3689 | } |
3690 | ||
3691 | /* | |
3692 | * The following functions are control change helpers. | |
3693 | * They return 0 if no changed. Return 1 if changed. | |
3694 | */ | |
3695 | static int ca0132_voicefx_set(struct hda_codec *codec, int enable) | |
3696 | { | |
3697 | struct ca0132_spec *spec = codec->spec; | |
3698 | unsigned int tmp; | |
3699 | ||
3700 | /* based on CrystalVoice state to enable VoiceFX. */ | |
3701 | if (enable) { | |
3702 | tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? | |
3703 | FLOAT_ONE : FLOAT_ZERO; | |
3704 | } else { | |
3705 | tmp = FLOAT_ZERO; | |
3706 | } | |
3707 | ||
3708 | dspio_set_uint_param(codec, ca0132_voicefx.mid, | |
3709 | ca0132_voicefx.reqs[0], tmp); | |
3710 | ||
3711 | return 1; | |
3712 | } | |
3713 | ||
5aaca44d IM |
3714 | /* |
3715 | * Set the effects parameters | |
3716 | */ | |
3717 | static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) | |
3718 | { | |
3719 | struct ca0132_spec *spec = codec->spec; | |
009b8f97 | 3720 | unsigned int on, tmp; |
5aaca44d IM |
3721 | int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; |
3722 | int err = 0; | |
3723 | int idx = nid - EFFECT_START_NID; | |
3724 | ||
3725 | if ((idx < 0) || (idx >= num_fx)) | |
3726 | return 0; /* no changed */ | |
3727 | ||
3728 | /* for out effect, qualify with PE */ | |
3729 | if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { | |
3730 | /* if PE if off, turn off out effects. */ | |
3731 | if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) | |
3732 | val = 0; | |
3733 | } | |
3734 | ||
3735 | /* for in effect, qualify with CrystalVoice */ | |
3736 | if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { | |
3737 | /* if CrystalVoice if off, turn off in effects. */ | |
3738 | if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) | |
3739 | val = 0; | |
3740 | ||
3741 | /* Voice Focus applies to 2-ch Mic, Digital Mic */ | |
3742 | if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) | |
3743 | val = 0; | |
009b8f97 CM |
3744 | |
3745 | /* If Voice Focus on SBZ, set to two channel. */ | |
3746 | if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)) { | |
3747 | if (spec->effects_switch[CRYSTAL_VOICE - | |
3748 | EFFECT_START_NID]) { | |
3749 | ||
3750 | if (spec->effects_switch[VOICE_FOCUS - | |
3751 | EFFECT_START_NID]) { | |
3752 | tmp = FLOAT_TWO; | |
3753 | val = 1; | |
3754 | } else | |
3755 | tmp = FLOAT_ONE; | |
3756 | ||
3757 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); | |
3758 | } | |
3759 | } | |
3760 | /* | |
3761 | * For SBZ noise reduction, there's an extra command | |
3762 | * to module ID 0x47. No clue why. | |
3763 | */ | |
3764 | if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)) { | |
3765 | if (spec->effects_switch[CRYSTAL_VOICE - | |
3766 | EFFECT_START_NID]) { | |
3767 | if (spec->effects_switch[NOISE_REDUCTION - | |
3768 | EFFECT_START_NID]) | |
3769 | tmp = FLOAT_ONE; | |
3770 | else | |
3771 | tmp = FLOAT_ZERO; | |
3772 | } else | |
3773 | tmp = FLOAT_ZERO; | |
3774 | ||
3775 | dspio_set_uint_param(codec, 0x47, 0x00, tmp); | |
3776 | } | |
5aaca44d IM |
3777 | } |
3778 | ||
4e76a883 | 3779 | codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", |
5aaca44d IM |
3780 | nid, val); |
3781 | ||
3782 | on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; | |
3783 | err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, | |
3784 | ca0132_effects[idx].reqs[0], on); | |
3785 | ||
3786 | if (err < 0) | |
3787 | return 0; /* no changed */ | |
3788 | ||
3789 | return 1; | |
3790 | } | |
3791 | ||
a7e76271 IM |
3792 | /* |
3793 | * Turn on/off Playback Enhancements | |
3794 | */ | |
3795 | static int ca0132_pe_switch_set(struct hda_codec *codec) | |
3796 | { | |
3797 | struct ca0132_spec *spec = codec->spec; | |
3798 | hda_nid_t nid; | |
3799 | int i, ret = 0; | |
3800 | ||
4e76a883 | 3801 | codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", |
a7e76271 IM |
3802 | spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); |
3803 | ||
3804 | i = OUT_EFFECT_START_NID - EFFECT_START_NID; | |
3805 | nid = OUT_EFFECT_START_NID; | |
3806 | /* PE affects all out effects */ | |
3807 | for (; nid < OUT_EFFECT_END_NID; nid++, i++) | |
3808 | ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); | |
3809 | ||
3810 | return ret; | |
3811 | } | |
3812 | ||
5aaca44d IM |
3813 | /* Check if Mic1 is streaming, if so, stop streaming */ |
3814 | static int stop_mic1(struct hda_codec *codec) | |
3815 | { | |
3816 | struct ca0132_spec *spec = codec->spec; | |
3817 | unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, | |
3818 | AC_VERB_GET_CONV, 0); | |
3819 | if (oldval != 0) | |
3820 | snd_hda_codec_write(codec, spec->adcs[0], 0, | |
3821 | AC_VERB_SET_CHANNEL_STREAMID, | |
3822 | 0); | |
3823 | return oldval; | |
3824 | } | |
3825 | ||
3826 | /* Resume Mic1 streaming if it was stopped. */ | |
3827 | static void resume_mic1(struct hda_codec *codec, unsigned int oldval) | |
3828 | { | |
3829 | struct ca0132_spec *spec = codec->spec; | |
3830 | /* Restore the previous stream and channel */ | |
3831 | if (oldval != 0) | |
3832 | snd_hda_codec_write(codec, spec->adcs[0], 0, | |
3833 | AC_VERB_SET_CHANNEL_STREAMID, | |
3834 | oldval); | |
3835 | } | |
3836 | ||
3837 | /* | |
a7e76271 | 3838 | * Turn on/off CrystalVoice |
5aaca44d | 3839 | */ |
a7e76271 IM |
3840 | static int ca0132_cvoice_switch_set(struct hda_codec *codec) |
3841 | { | |
3842 | struct ca0132_spec *spec = codec->spec; | |
3843 | hda_nid_t nid; | |
3844 | int i, ret = 0; | |
3845 | unsigned int oldval; | |
3846 | ||
4e76a883 | 3847 | codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", |
a7e76271 IM |
3848 | spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); |
3849 | ||
3850 | i = IN_EFFECT_START_NID - EFFECT_START_NID; | |
3851 | nid = IN_EFFECT_START_NID; | |
3852 | /* CrystalVoice affects all in effects */ | |
3853 | for (; nid < IN_EFFECT_END_NID; nid++, i++) | |
3854 | ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); | |
3855 | ||
3856 | /* including VoiceFX */ | |
3857 | ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); | |
3858 | ||
3859 | /* set correct vipsource */ | |
3860 | oldval = stop_mic1(codec); | |
3861 | ret |= ca0132_set_vipsource(codec, 1); | |
3862 | resume_mic1(codec, oldval); | |
3863 | return ret; | |
3864 | } | |
3865 | ||
5aaca44d IM |
3866 | static int ca0132_mic_boost_set(struct hda_codec *codec, long val) |
3867 | { | |
3868 | struct ca0132_spec *spec = codec->spec; | |
3869 | int ret = 0; | |
3870 | ||
3871 | if (val) /* on */ | |
3872 | ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, | |
3873 | HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); | |
3874 | else /* off */ | |
3875 | ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, | |
3876 | HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); | |
3877 | ||
3878 | return ret; | |
3879 | } | |
3880 | ||
a7e76271 IM |
3881 | static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, |
3882 | struct snd_ctl_elem_value *ucontrol) | |
95c6e9cb | 3883 | { |
a7e76271 IM |
3884 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
3885 | hda_nid_t nid = get_amp_nid(kcontrol); | |
3886 | hda_nid_t shared_nid = 0; | |
3887 | bool effective; | |
3888 | int ret = 0; | |
95c6e9cb | 3889 | struct ca0132_spec *spec = codec->spec; |
a7e76271 | 3890 | int auto_jack; |
95c6e9cb | 3891 | |
a7e76271 IM |
3892 | if (nid == VNID_HP_SEL) { |
3893 | auto_jack = | |
3894 | spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; | |
3895 | if (!auto_jack) | |
3896 | ca0132_select_out(codec); | |
3897 | return 1; | |
3898 | } | |
95c6e9cb | 3899 | |
a7e76271 IM |
3900 | if (nid == VNID_AMIC1_SEL) { |
3901 | auto_jack = | |
3902 | spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; | |
3903 | if (!auto_jack) | |
3904 | ca0132_select_mic(codec); | |
3905 | return 1; | |
3906 | } | |
95c6e9cb | 3907 | |
a7e76271 IM |
3908 | if (nid == VNID_HP_ASEL) { |
3909 | ca0132_select_out(codec); | |
3910 | return 1; | |
3911 | } | |
95c6e9cb | 3912 | |
a7e76271 IM |
3913 | if (nid == VNID_AMIC1_ASEL) { |
3914 | ca0132_select_mic(codec); | |
3915 | return 1; | |
95c6e9cb | 3916 | } |
a7e76271 IM |
3917 | |
3918 | /* if effective conditions, then update hw immediately. */ | |
3919 | effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); | |
3920 | if (effective) { | |
3921 | int dir = get_amp_direction(kcontrol); | |
3922 | int ch = get_amp_channels(kcontrol); | |
3923 | unsigned long pval; | |
3924 | ||
3925 | mutex_lock(&codec->control_mutex); | |
3926 | pval = kcontrol->private_value; | |
3927 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, | |
3928 | 0, dir); | |
3929 | ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); | |
3930 | kcontrol->private_value = pval; | |
3931 | mutex_unlock(&codec->control_mutex); | |
95c6e9cb | 3932 | } |
95c6e9cb | 3933 | |
a7e76271 | 3934 | return ret; |
95c6e9cb | 3935 | } |
a7e76271 | 3936 | /* End of control change helpers. */ |
95c6e9cb | 3937 | |
a7e76271 IM |
3938 | static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, |
3939 | struct snd_ctl_elem_info *uinfo) | |
3940 | { | |
a9291f46 | 3941 | unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); |
a7e76271 IM |
3942 | |
3943 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3944 | uinfo->count = 1; | |
3945 | uinfo->value.enumerated.items = items; | |
3946 | if (uinfo->value.enumerated.item >= items) | |
3947 | uinfo->value.enumerated.item = items - 1; | |
3948 | strcpy(uinfo->value.enumerated.name, | |
3949 | ca0132_voicefx_presets[uinfo->value.enumerated.item].name); | |
3950 | return 0; | |
3951 | } | |
95c6e9cb | 3952 | |
a7e76271 | 3953 | static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, |
95c6e9cb IM |
3954 | struct snd_ctl_elem_value *ucontrol) |
3955 | { | |
3956 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
3957 | struct ca0132_spec *spec = codec->spec; | |
95c6e9cb | 3958 | |
a7e76271 | 3959 | ucontrol->value.enumerated.item[0] = spec->voicefx_val; |
95c6e9cb IM |
3960 | return 0; |
3961 | } | |
3962 | ||
a7e76271 | 3963 | static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, |
95c6e9cb IM |
3964 | struct snd_ctl_elem_value *ucontrol) |
3965 | { | |
3966 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
3967 | struct ca0132_spec *spec = codec->spec; | |
a7e76271 IM |
3968 | int i, err = 0; |
3969 | int sel = ucontrol->value.enumerated.item[0]; | |
95c6e9cb | 3970 | |
a9291f46 | 3971 | if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) |
95c6e9cb IM |
3972 | return 0; |
3973 | ||
4e76a883 | 3974 | codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", |
a7e76271 | 3975 | sel, ca0132_voicefx_presets[sel].name); |
95c6e9cb | 3976 | |
a7e76271 IM |
3977 | /* |
3978 | * Idx 0 is default. | |
3979 | * Default needs to qualify with CrystalVoice state. | |
3980 | */ | |
3981 | for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { | |
3982 | err = dspio_set_uint_param(codec, ca0132_voicefx.mid, | |
3983 | ca0132_voicefx.reqs[i], | |
3984 | ca0132_voicefx_presets[sel].vals[i]); | |
3985 | if (err < 0) | |
3986 | break; | |
3987 | } | |
95c6e9cb | 3988 | |
a7e76271 IM |
3989 | if (err >= 0) { |
3990 | spec->voicefx_val = sel; | |
3991 | /* enable voice fx */ | |
3992 | ca0132_voicefx_set(codec, (sel ? 1 : 0)); | |
3993 | } | |
95c6e9cb | 3994 | |
a7e76271 | 3995 | return 1; |
95c6e9cb IM |
3996 | } |
3997 | ||
a7e76271 IM |
3998 | static int ca0132_switch_get(struct snd_kcontrol *kcontrol, |
3999 | struct snd_ctl_elem_value *ucontrol) | |
95c6e9cb IM |
4000 | { |
4001 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
4002 | struct ca0132_spec *spec = codec->spec; | |
a7e76271 IM |
4003 | hda_nid_t nid = get_amp_nid(kcontrol); |
4004 | int ch = get_amp_channels(kcontrol); | |
95c6e9cb IM |
4005 | long *valp = ucontrol->value.integer.value; |
4006 | ||
a7e76271 IM |
4007 | /* vnode */ |
4008 | if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { | |
4009 | if (ch & 1) { | |
4010 | *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; | |
4011 | valp++; | |
4012 | } | |
4013 | if (ch & 2) { | |
4014 | *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; | |
4015 | valp++; | |
4016 | } | |
4017 | return 0; | |
4018 | } | |
4019 | ||
4020 | /* effects, include PE and CrystalVoice */ | |
4021 | if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { | |
4022 | *valp = spec->effects_switch[nid - EFFECT_START_NID]; | |
4023 | return 0; | |
4024 | } | |
4025 | ||
4026 | /* mic boost */ | |
4027 | if (nid == spec->input_pins[0]) { | |
4028 | *valp = spec->cur_mic_boost; | |
4029 | return 0; | |
4030 | } | |
4031 | ||
95c6e9cb IM |
4032 | return 0; |
4033 | } | |
4034 | ||
a7e76271 IM |
4035 | static int ca0132_switch_put(struct snd_kcontrol *kcontrol, |
4036 | struct snd_ctl_elem_value *ucontrol) | |
95c6e9cb IM |
4037 | { |
4038 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
4039 | struct ca0132_spec *spec = codec->spec; | |
a7e76271 IM |
4040 | hda_nid_t nid = get_amp_nid(kcontrol); |
4041 | int ch = get_amp_channels(kcontrol); | |
95c6e9cb | 4042 | long *valp = ucontrol->value.integer.value; |
a7e76271 | 4043 | int changed = 1; |
95c6e9cb | 4044 | |
4e76a883 | 4045 | codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", |
a7e76271 | 4046 | nid, *valp); |
95c6e9cb IM |
4047 | |
4048 | snd_hda_power_up(codec); | |
a7e76271 IM |
4049 | /* vnode */ |
4050 | if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { | |
4051 | if (ch & 1) { | |
4052 | spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; | |
4053 | valp++; | |
4054 | } | |
4055 | if (ch & 2) { | |
4056 | spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; | |
4057 | valp++; | |
4058 | } | |
4059 | changed = ca0132_vnode_switch_set(kcontrol, ucontrol); | |
4060 | goto exit; | |
4061 | } | |
95c6e9cb | 4062 | |
a7e76271 IM |
4063 | /* PE */ |
4064 | if (nid == PLAY_ENHANCEMENT) { | |
4065 | spec->effects_switch[nid - EFFECT_START_NID] = *valp; | |
4066 | changed = ca0132_pe_switch_set(codec); | |
b97f6bfd | 4067 | goto exit; |
a7e76271 | 4068 | } |
95c6e9cb | 4069 | |
a7e76271 IM |
4070 | /* CrystalVoice */ |
4071 | if (nid == CRYSTAL_VOICE) { | |
4072 | spec->effects_switch[nid - EFFECT_START_NID] = *valp; | |
4073 | changed = ca0132_cvoice_switch_set(codec); | |
b97f6bfd | 4074 | goto exit; |
a7e76271 | 4075 | } |
95c6e9cb | 4076 | |
a7e76271 IM |
4077 | /* out and in effects */ |
4078 | if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || | |
4079 | ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { | |
4080 | spec->effects_switch[nid - EFFECT_START_NID] = *valp; | |
4081 | changed = ca0132_effects_set(codec, nid, *valp); | |
4082 | goto exit; | |
4083 | } | |
4084 | ||
4085 | /* mic boost */ | |
4086 | if (nid == spec->input_pins[0]) { | |
4087 | spec->cur_mic_boost = *valp; | |
4088 | ||
4089 | /* Mic boost does not apply to Digital Mic */ | |
4090 | if (spec->cur_mic_type != DIGITAL_MIC) | |
4091 | changed = ca0132_mic_boost_set(codec, *valp); | |
4092 | goto exit; | |
4093 | } | |
95c6e9cb | 4094 | |
a7e76271 | 4095 | exit: |
95c6e9cb | 4096 | snd_hda_power_down(codec); |
a7e76271 | 4097 | return changed; |
95c6e9cb IM |
4098 | } |
4099 | ||
a7e76271 IM |
4100 | /* |
4101 | * Volume related | |
4102 | */ | |
4103 | static int ca0132_volume_info(struct snd_kcontrol *kcontrol, | |
4104 | struct snd_ctl_elem_info *uinfo) | |
4105 | { | |
4106 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
4107 | struct ca0132_spec *spec = codec->spec; | |
4108 | hda_nid_t nid = get_amp_nid(kcontrol); | |
4109 | int ch = get_amp_channels(kcontrol); | |
4110 | int dir = get_amp_direction(kcontrol); | |
4111 | unsigned long pval; | |
4112 | int err; | |
4113 | ||
4114 | switch (nid) { | |
4115 | case VNID_SPK: | |
4116 | /* follow shared_out info */ | |
4117 | nid = spec->shared_out_nid; | |
4118 | mutex_lock(&codec->control_mutex); | |
4119 | pval = kcontrol->private_value; | |
4120 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); | |
4121 | err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); | |
4122 | kcontrol->private_value = pval; | |
4123 | mutex_unlock(&codec->control_mutex); | |
4124 | break; | |
4125 | case VNID_MIC: | |
4126 | /* follow shared_mic info */ | |
4127 | nid = spec->shared_mic_nid; | |
4128 | mutex_lock(&codec->control_mutex); | |
4129 | pval = kcontrol->private_value; | |
4130 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); | |
4131 | err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); | |
4132 | kcontrol->private_value = pval; | |
4133 | mutex_unlock(&codec->control_mutex); | |
4134 | break; | |
4135 | default: | |
4136 | err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); | |
4137 | } | |
4138 | return err; | |
4139 | } | |
4140 | ||
4141 | static int ca0132_volume_get(struct snd_kcontrol *kcontrol, | |
95c6e9cb IM |
4142 | struct snd_ctl_elem_value *ucontrol) |
4143 | { | |
4144 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
4145 | struct ca0132_spec *spec = codec->spec; | |
a7e76271 IM |
4146 | hda_nid_t nid = get_amp_nid(kcontrol); |
4147 | int ch = get_amp_channels(kcontrol); | |
95c6e9cb IM |
4148 | long *valp = ucontrol->value.integer.value; |
4149 | ||
a7e76271 IM |
4150 | /* store the left and right volume */ |
4151 | if (ch & 1) { | |
4152 | *valp = spec->vnode_lvol[nid - VNODE_START_NID]; | |
4153 | valp++; | |
4154 | } | |
4155 | if (ch & 2) { | |
4156 | *valp = spec->vnode_rvol[nid - VNODE_START_NID]; | |
4157 | valp++; | |
4158 | } | |
95c6e9cb IM |
4159 | return 0; |
4160 | } | |
4161 | ||
a7e76271 | 4162 | static int ca0132_volume_put(struct snd_kcontrol *kcontrol, |
95c6e9cb IM |
4163 | struct snd_ctl_elem_value *ucontrol) |
4164 | { | |
4165 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
4166 | struct ca0132_spec *spec = codec->spec; | |
a7e76271 IM |
4167 | hda_nid_t nid = get_amp_nid(kcontrol); |
4168 | int ch = get_amp_channels(kcontrol); | |
95c6e9cb | 4169 | long *valp = ucontrol->value.integer.value; |
a7e76271 IM |
4170 | hda_nid_t shared_nid = 0; |
4171 | bool effective; | |
4172 | int changed = 1; | |
4173 | ||
4174 | /* store the left and right volume */ | |
4175 | if (ch & 1) { | |
4176 | spec->vnode_lvol[nid - VNODE_START_NID] = *valp; | |
4177 | valp++; | |
4178 | } | |
4179 | if (ch & 2) { | |
4180 | spec->vnode_rvol[nid - VNODE_START_NID] = *valp; | |
4181 | valp++; | |
4182 | } | |
95c6e9cb | 4183 | |
a7e76271 IM |
4184 | /* if effective conditions, then update hw immediately. */ |
4185 | effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); | |
4186 | if (effective) { | |
4187 | int dir = get_amp_direction(kcontrol); | |
4188 | unsigned long pval; | |
4189 | ||
4190 | snd_hda_power_up(codec); | |
4191 | mutex_lock(&codec->control_mutex); | |
4192 | pval = kcontrol->private_value; | |
4193 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, | |
4194 | 0, dir); | |
4195 | changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); | |
4196 | kcontrol->private_value = pval; | |
4197 | mutex_unlock(&codec->control_mutex); | |
4198 | snd_hda_power_down(codec); | |
4199 | } | |
95c6e9cb | 4200 | |
a7e76271 | 4201 | return changed; |
95c6e9cb IM |
4202 | } |
4203 | ||
a7e76271 IM |
4204 | static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, |
4205 | unsigned int size, unsigned int __user *tlv) | |
95c6e9cb | 4206 | { |
a7e76271 IM |
4207 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
4208 | struct ca0132_spec *spec = codec->spec; | |
4209 | hda_nid_t nid = get_amp_nid(kcontrol); | |
4210 | int ch = get_amp_channels(kcontrol); | |
4211 | int dir = get_amp_direction(kcontrol); | |
4212 | unsigned long pval; | |
4213 | int err; | |
4214 | ||
4215 | switch (nid) { | |
4216 | case VNID_SPK: | |
4217 | /* follow shared_out tlv */ | |
4218 | nid = spec->shared_out_nid; | |
4219 | mutex_lock(&codec->control_mutex); | |
4220 | pval = kcontrol->private_value; | |
4221 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); | |
4222 | err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); | |
4223 | kcontrol->private_value = pval; | |
4224 | mutex_unlock(&codec->control_mutex); | |
4225 | break; | |
4226 | case VNID_MIC: | |
4227 | /* follow shared_mic tlv */ | |
4228 | nid = spec->shared_mic_nid; | |
4229 | mutex_lock(&codec->control_mutex); | |
4230 | pval = kcontrol->private_value; | |
4231 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); | |
4232 | err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); | |
4233 | kcontrol->private_value = pval; | |
4234 | mutex_unlock(&codec->control_mutex); | |
4235 | break; | |
4236 | default: | |
4237 | err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); | |
4238 | } | |
4239 | return err; | |
95c6e9cb IM |
4240 | } |
4241 | ||
a7e76271 IM |
4242 | static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, |
4243 | const char *pfx, int dir) | |
95c6e9cb | 4244 | { |
975cc02a | 4245 | char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; |
a7e76271 | 4246 | int type = dir ? HDA_INPUT : HDA_OUTPUT; |
95c6e9cb | 4247 | struct snd_kcontrol_new knew = |
a7e76271 IM |
4248 | CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); |
4249 | sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); | |
95c6e9cb IM |
4250 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
4251 | } | |
4252 | ||
a7e76271 | 4253 | static int add_voicefx(struct hda_codec *codec) |
95c6e9cb IM |
4254 | { |
4255 | struct snd_kcontrol_new knew = | |
a7e76271 IM |
4256 | HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, |
4257 | VOICEFX, 1, 0, HDA_INPUT); | |
4258 | knew.info = ca0132_voicefx_info; | |
4259 | knew.get = ca0132_voicefx_get; | |
4260 | knew.put = ca0132_voicefx_put; | |
4261 | return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); | |
95c6e9cb IM |
4262 | } |
4263 | ||
a7e76271 IM |
4264 | /* |
4265 | * When changing Node IDs for Mixer Controls below, make sure to update | |
4266 | * Node IDs in ca0132_config() as well. | |
4267 | */ | |
4268 | static struct snd_kcontrol_new ca0132_mixer[] = { | |
4269 | CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), | |
4270 | CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), | |
4271 | CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), | |
4272 | CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), | |
4273 | HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), | |
4274 | HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), | |
4275 | HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), | |
4276 | HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), | |
4277 | CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", | |
4278 | 0x12, 1, HDA_INPUT), | |
4279 | CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", | |
4280 | VNID_HP_SEL, 1, HDA_OUTPUT), | |
4281 | CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", | |
4282 | VNID_AMIC1_SEL, 1, HDA_INPUT), | |
4283 | CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", | |
4284 | VNID_HP_ASEL, 1, HDA_OUTPUT), | |
4285 | CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", | |
4286 | VNID_AMIC1_ASEL, 1, HDA_INPUT), | |
4287 | { } /* end */ | |
4288 | }; | |
4289 | ||
e90f29e4 IM |
4290 | static int ca0132_build_controls(struct hda_codec *codec) |
4291 | { | |
4292 | struct ca0132_spec *spec = codec->spec; | |
4293 | int i, num_fx; | |
4294 | int err = 0; | |
4295 | ||
4296 | /* Add Mixer controls */ | |
4297 | for (i = 0; i < spec->num_mixers; i++) { | |
4298 | err = snd_hda_add_new_ctls(codec, spec->mixers[i]); | |
4299 | if (err < 0) | |
4300 | return err; | |
4301 | } | |
4302 | ||
4303 | /* Add in and out effects controls. | |
4304 | * VoiceFX, PE and CrystalVoice are added separately. | |
4305 | */ | |
4306 | num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; | |
4307 | for (i = 0; i < num_fx; i++) { | |
4308 | err = add_fx_switch(codec, ca0132_effects[i].nid, | |
4309 | ca0132_effects[i].name, | |
4310 | ca0132_effects[i].direct); | |
4311 | if (err < 0) | |
4312 | return err; | |
4313 | } | |
4314 | ||
4315 | err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0); | |
4316 | if (err < 0) | |
4317 | return err; | |
4318 | ||
4319 | err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1); | |
4320 | if (err < 0) | |
4321 | return err; | |
4322 | ||
4323 | add_voicefx(codec); | |
4324 | ||
4325 | #ifdef ENABLE_TUNING_CONTROLS | |
4326 | add_tuning_ctls(codec); | |
4327 | #endif | |
4328 | ||
4329 | err = snd_hda_jack_add_kctls(codec, &spec->autocfg); | |
4330 | if (err < 0) | |
4331 | return err; | |
4332 | ||
4333 | if (spec->dig_out) { | |
4334 | err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, | |
4335 | spec->dig_out); | |
4336 | if (err < 0) | |
4337 | return err; | |
4338 | err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); | |
4339 | if (err < 0) | |
4340 | return err; | |
4341 | /* spec->multiout.share_spdif = 1; */ | |
4342 | } | |
4343 | ||
4344 | if (spec->dig_in) { | |
4345 | err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); | |
4346 | if (err < 0) | |
4347 | return err; | |
4348 | } | |
4349 | return 0; | |
4350 | } | |
4351 | ||
a7e76271 | 4352 | /* |
e90f29e4 | 4353 | * PCM |
a7e76271 | 4354 | */ |
071f1344 | 4355 | static const struct hda_pcm_stream ca0132_pcm_analog_playback = { |
a7e76271 IM |
4356 | .substreams = 1, |
4357 | .channels_min = 2, | |
825315bc | 4358 | .channels_max = 6, |
a7e76271 | 4359 | .ops = { |
a7e76271 | 4360 | .prepare = ca0132_playback_pcm_prepare, |
e8412ca4 DR |
4361 | .cleanup = ca0132_playback_pcm_cleanup, |
4362 | .get_delay = ca0132_playback_pcm_delay, | |
a7e76271 IM |
4363 | }, |
4364 | }; | |
4365 | ||
071f1344 | 4366 | static const struct hda_pcm_stream ca0132_pcm_analog_capture = { |
a7e76271 IM |
4367 | .substreams = 1, |
4368 | .channels_min = 2, | |
4369 | .channels_max = 2, | |
825315bc IM |
4370 | .ops = { |
4371 | .prepare = ca0132_capture_pcm_prepare, | |
e8412ca4 DR |
4372 | .cleanup = ca0132_capture_pcm_cleanup, |
4373 | .get_delay = ca0132_capture_pcm_delay, | |
825315bc | 4374 | }, |
a7e76271 IM |
4375 | }; |
4376 | ||
071f1344 | 4377 | static const struct hda_pcm_stream ca0132_pcm_digital_playback = { |
a7e76271 IM |
4378 | .substreams = 1, |
4379 | .channels_min = 2, | |
4380 | .channels_max = 2, | |
4381 | .ops = { | |
4382 | .open = ca0132_dig_playback_pcm_open, | |
4383 | .close = ca0132_dig_playback_pcm_close, | |
4384 | .prepare = ca0132_dig_playback_pcm_prepare, | |
4385 | .cleanup = ca0132_dig_playback_pcm_cleanup | |
4386 | }, | |
4387 | }; | |
4388 | ||
071f1344 | 4389 | static const struct hda_pcm_stream ca0132_pcm_digital_capture = { |
a7e76271 IM |
4390 | .substreams = 1, |
4391 | .channels_min = 2, | |
4392 | .channels_max = 2, | |
4393 | }; | |
4394 | ||
4395 | static int ca0132_build_pcms(struct hda_codec *codec) | |
95c6e9cb IM |
4396 | { |
4397 | struct ca0132_spec *spec = codec->spec; | |
bbbc7e85 | 4398 | struct hda_pcm *info; |
a7e76271 | 4399 | |
bbbc7e85 TI |
4400 | info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); |
4401 | if (!info) | |
4402 | return -ENOMEM; | |
a7e76271 IM |
4403 | info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; |
4404 | info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; | |
4405 | info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = | |
4406 | spec->multiout.max_channels; | |
4407 | info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; | |
825315bc | 4408 | info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; |
a7e76271 | 4409 | info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; |
a7e76271 | 4410 | |
009b8f97 CM |
4411 | /* With the DSP enabled, desktops don't use this ADC. */ |
4412 | if (spec->use_alt_functions) { | |
4413 | info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); | |
4414 | if (!info) | |
4415 | return -ENOMEM; | |
4416 | info->stream[SNDRV_PCM_STREAM_CAPTURE] = | |
4417 | ca0132_pcm_analog_capture; | |
4418 | info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; | |
4419 | info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; | |
4420 | } | |
825315bc | 4421 | |
bbbc7e85 TI |
4422 | info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); |
4423 | if (!info) | |
4424 | return -ENOMEM; | |
825315bc IM |
4425 | info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; |
4426 | info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; | |
4427 | info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; | |
825315bc | 4428 | |
a7e76271 IM |
4429 | if (!spec->dig_out && !spec->dig_in) |
4430 | return 0; | |
4431 | ||
bbbc7e85 TI |
4432 | info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); |
4433 | if (!info) | |
4434 | return -ENOMEM; | |
a7e76271 IM |
4435 | info->pcm_type = HDA_PCM_TYPE_SPDIF; |
4436 | if (spec->dig_out) { | |
4437 | info->stream[SNDRV_PCM_STREAM_PLAYBACK] = | |
4438 | ca0132_pcm_digital_playback; | |
4439 | info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; | |
4440 | } | |
4441 | if (spec->dig_in) { | |
4442 | info->stream[SNDRV_PCM_STREAM_CAPTURE] = | |
4443 | ca0132_pcm_digital_capture; | |
4444 | info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; | |
4445 | } | |
95c6e9cb | 4446 | |
a7e76271 | 4447 | return 0; |
95c6e9cb IM |
4448 | } |
4449 | ||
441aa6a0 IM |
4450 | static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) |
4451 | { | |
4452 | if (pin) { | |
a0c041cb | 4453 | snd_hda_set_pin_ctl(codec, pin, PIN_HP); |
441aa6a0 IM |
4454 | if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) |
4455 | snd_hda_codec_write(codec, pin, 0, | |
4456 | AC_VERB_SET_AMP_GAIN_MUTE, | |
4457 | AMP_OUT_UNMUTE); | |
4458 | } | |
4459 | if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) | |
4460 | snd_hda_codec_write(codec, dac, 0, | |
4461 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); | |
4462 | } | |
4463 | ||
4464 | static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) | |
4465 | { | |
4466 | if (pin) { | |
a0c041cb | 4467 | snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); |
441aa6a0 IM |
4468 | if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) |
4469 | snd_hda_codec_write(codec, pin, 0, | |
4470 | AC_VERB_SET_AMP_GAIN_MUTE, | |
4471 | AMP_IN_UNMUTE(0)); | |
4472 | } | |
4473 | if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { | |
4474 | snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, | |
4475 | AMP_IN_UNMUTE(0)); | |
4476 | ||
4477 | /* init to 0 dB and unmute. */ | |
4478 | snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, | |
4479 | HDA_AMP_VOLMASK, 0x5a); | |
4480 | snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, | |
4481 | HDA_AMP_MUTE, 0); | |
4482 | } | |
4483 | } | |
4484 | ||
5aaca44d IM |
4485 | static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) |
4486 | { | |
4487 | unsigned int caps; | |
4488 | ||
4489 | caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? | |
4490 | AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); | |
4491 | snd_hda_override_amp_caps(codec, nid, dir, caps); | |
4492 | } | |
4493 | ||
4494 | /* | |
4495 | * Switch between Digital built-in mic and analog mic. | |
4496 | */ | |
4497 | static void ca0132_set_dmic(struct hda_codec *codec, int enable) | |
4498 | { | |
4499 | struct ca0132_spec *spec = codec->spec; | |
4500 | unsigned int tmp; | |
4501 | u8 val; | |
4502 | unsigned int oldval; | |
4503 | ||
4e76a883 | 4504 | codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); |
5aaca44d IM |
4505 | |
4506 | oldval = stop_mic1(codec); | |
4507 | ca0132_set_vipsource(codec, 0); | |
4508 | if (enable) { | |
4509 | /* set DMic input as 2-ch */ | |
4510 | tmp = FLOAT_TWO; | |
4511 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); | |
4512 | ||
4513 | val = spec->dmic_ctl; | |
4514 | val |= 0x80; | |
4515 | snd_hda_codec_write(codec, spec->input_pins[0], 0, | |
4516 | VENDOR_CHIPIO_DMIC_CTL_SET, val); | |
4517 | ||
4518 | if (!(spec->dmic_ctl & 0x20)) | |
4519 | chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); | |
4520 | } else { | |
4521 | /* set AMic input as mono */ | |
4522 | tmp = FLOAT_ONE; | |
4523 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); | |
4524 | ||
4525 | val = spec->dmic_ctl; | |
4526 | /* clear bit7 and bit5 to disable dmic */ | |
4527 | val &= 0x5f; | |
4528 | snd_hda_codec_write(codec, spec->input_pins[0], 0, | |
4529 | VENDOR_CHIPIO_DMIC_CTL_SET, val); | |
4530 | ||
4531 | if (!(spec->dmic_ctl & 0x20)) | |
4532 | chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); | |
4533 | } | |
4534 | ca0132_set_vipsource(codec, 1); | |
4535 | resume_mic1(codec, oldval); | |
4536 | } | |
4537 | ||
4538 | /* | |
4539 | * Initialization for Digital Mic. | |
4540 | */ | |
4541 | static void ca0132_init_dmic(struct hda_codec *codec) | |
4542 | { | |
4543 | struct ca0132_spec *spec = codec->spec; | |
4544 | u8 val; | |
4545 | ||
4546 | /* Setup Digital Mic here, but don't enable. | |
4547 | * Enable based on jack detect. | |
4548 | */ | |
4549 | ||
4550 | /* MCLK uses MPIO1, set to enable. | |
4551 | * Bit 2-0: MPIO select | |
4552 | * Bit 3: set to disable | |
4553 | * Bit 7-4: reserved | |
4554 | */ | |
4555 | val = 0x01; | |
4556 | snd_hda_codec_write(codec, spec->input_pins[0], 0, | |
4557 | VENDOR_CHIPIO_DMIC_MCLK_SET, val); | |
4558 | ||
4559 | /* Data1 uses MPIO3. Data2 not use | |
4560 | * Bit 2-0: Data1 MPIO select | |
4561 | * Bit 3: set disable Data1 | |
4562 | * Bit 6-4: Data2 MPIO select | |
4563 | * Bit 7: set disable Data2 | |
4564 | */ | |
4565 | val = 0x83; | |
4566 | snd_hda_codec_write(codec, spec->input_pins[0], 0, | |
4567 | VENDOR_CHIPIO_DMIC_PIN_SET, val); | |
4568 | ||
4569 | /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. | |
4570 | * Bit 3-0: Channel mask | |
4571 | * Bit 4: set for 48KHz, clear for 32KHz | |
4572 | * Bit 5: mode | |
4573 | * Bit 6: set to select Data2, clear for Data1 | |
4574 | * Bit 7: set to enable DMic, clear for AMic | |
4575 | */ | |
4576 | val = 0x23; | |
4577 | /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ | |
4578 | spec->dmic_ctl = val; | |
4579 | snd_hda_codec_write(codec, spec->input_pins[0], 0, | |
4580 | VENDOR_CHIPIO_DMIC_CTL_SET, val); | |
4581 | } | |
4582 | ||
4583 | /* | |
4584 | * Initialization for Analog Mic 2 | |
4585 | */ | |
4586 | static void ca0132_init_analog_mic2(struct hda_codec *codec) | |
4587 | { | |
4588 | struct ca0132_spec *spec = codec->spec; | |
4589 | ||
4590 | mutex_lock(&spec->chipio_mutex); | |
4591 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
4592 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); | |
4593 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
4594 | VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); | |
4595 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
4596 | VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); | |
4597 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
4598 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); | |
4599 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
4600 | VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); | |
4601 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
4602 | VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); | |
4603 | mutex_unlock(&spec->chipio_mutex); | |
4604 | } | |
4605 | ||
4606 | static void ca0132_refresh_widget_caps(struct hda_codec *codec) | |
4607 | { | |
4608 | struct ca0132_spec *spec = codec->spec; | |
4609 | int i; | |
5aaca44d | 4610 | |
4e76a883 | 4611 | codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); |
7639a06c | 4612 | snd_hda_codec_update_widgets(codec); |
5aaca44d IM |
4613 | |
4614 | for (i = 0; i < spec->multiout.num_dacs; i++) | |
4615 | refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); | |
4616 | ||
4617 | for (i = 0; i < spec->num_outputs; i++) | |
4618 | refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); | |
4619 | ||
4620 | for (i = 0; i < spec->num_inputs; i++) { | |
4621 | refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); | |
4622 | refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); | |
4623 | } | |
4624 | } | |
4625 | ||
7e6ed62e CM |
4626 | /* |
4627 | * Recon3Di r3di_setup_defaults sub functions. | |
4628 | */ | |
4629 | ||
447fd8e9 CM |
4630 | static void r3di_dsp_scp_startup(struct hda_codec *codec) |
4631 | { | |
4632 | unsigned int tmp; | |
4633 | ||
4634 | tmp = 0x00000000; | |
4635 | dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); | |
4636 | ||
4637 | tmp = 0x00000001; | |
4638 | dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); | |
4639 | ||
4640 | tmp = 0x00000004; | |
4641 | dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); | |
4642 | ||
4643 | tmp = 0x00000005; | |
4644 | dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); | |
4645 | ||
4646 | tmp = 0x00000000; | |
4647 | dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); | |
4648 | ||
4649 | } | |
4650 | ||
7e6ed62e CM |
4651 | static void r3di_dsp_initial_mic_setup(struct hda_codec *codec) |
4652 | { | |
4653 | unsigned int tmp; | |
4654 | ||
4655 | /* Mic 1 Setup */ | |
4656 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); | |
4657 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); | |
4658 | /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */ | |
4659 | chipio_set_conn_rate(codec, 0x0F, SR_96_000); | |
4660 | tmp = FLOAT_ONE; | |
4661 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); | |
4662 | ||
4663 | /* Mic 2 Setup, even though it isn't connected on SBZ */ | |
4664 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); | |
4665 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); | |
4666 | chipio_set_conn_rate(codec, 0x0F, SR_96_000); | |
4667 | tmp = FLOAT_ZERO; | |
4668 | dspio_set_uint_param(codec, 0x80, 0x01, tmp); | |
4669 | } | |
4670 | ||
38ba69ff CM |
4671 | /* |
4672 | * Initialize Sound Blaster Z analog microphones. | |
4673 | */ | |
4674 | static void sbz_init_analog_mics(struct hda_codec *codec) | |
4675 | { | |
4676 | unsigned int tmp; | |
4677 | ||
4678 | /* Mic 1 Setup */ | |
4679 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); | |
4680 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); | |
4681 | tmp = FLOAT_THREE; | |
4682 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); | |
4683 | ||
4684 | /* Mic 2 Setup, even though it isn't connected on SBZ */ | |
4685 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); | |
4686 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); | |
4687 | tmp = FLOAT_ZERO; | |
4688 | dspio_set_uint_param(codec, 0x80, 0x01, tmp); | |
4689 | ||
4690 | } | |
4691 | ||
4692 | /* | |
4693 | * Sets the source of stream 0x14 to connpointID 0x48, and the destination | |
4694 | * connpointID to 0x91. If this isn't done, the destination is 0x71, and | |
4695 | * you get no sound. I'm guessing this has to do with the Sound Blaster Z | |
4696 | * having an updated DAC, which changes the destination to that DAC. | |
4697 | */ | |
4698 | static void sbz_connect_streams(struct hda_codec *codec) | |
4699 | { | |
4700 | struct ca0132_spec *spec = codec->spec; | |
4701 | ||
4702 | mutex_lock(&spec->chipio_mutex); | |
4703 | ||
4704 | codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); | |
4705 | ||
4706 | chipio_set_stream_channels(codec, 0x0C, 6); | |
4707 | chipio_set_stream_control(codec, 0x0C, 1); | |
4708 | ||
4709 | /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ | |
4710 | chipio_write_no_mutex(codec, 0x18a020, 0x00000043); | |
4711 | ||
4712 | /* Setup stream 0x14 with it's source and destination points */ | |
4713 | chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); | |
4714 | chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); | |
4715 | chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); | |
4716 | chipio_set_stream_channels(codec, 0x14, 2); | |
4717 | chipio_set_stream_control(codec, 0x14, 1); | |
4718 | ||
4719 | codec_dbg(codec, "Connect Streams exited, mutex released.\n"); | |
4720 | ||
4721 | mutex_unlock(&spec->chipio_mutex); | |
4722 | ||
4723 | } | |
4724 | ||
4725 | /* | |
4726 | * Write data through ChipIO to setup proper stream destinations. | |
4727 | * Not sure how it exactly works, but it seems to direct data | |
4728 | * to different destinations. Example is f8 to c0, e0 to c0. | |
4729 | * All I know is, if you don't set these, you get no sound. | |
4730 | */ | |
4731 | static void sbz_chipio_startup_data(struct hda_codec *codec) | |
4732 | { | |
4733 | struct ca0132_spec *spec = codec->spec; | |
4734 | ||
4735 | mutex_lock(&spec->chipio_mutex); | |
4736 | codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); | |
4737 | ||
4738 | /* These control audio output */ | |
4739 | chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); | |
4740 | chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); | |
4741 | chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); | |
4742 | chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); | |
4743 | /* Signal to update I think */ | |
4744 | chipio_write_no_mutex(codec, 0x19042c, 0x00000001); | |
4745 | ||
4746 | chipio_set_stream_channels(codec, 0x0C, 6); | |
4747 | chipio_set_stream_control(codec, 0x0C, 1); | |
4748 | /* No clue what these control */ | |
4749 | chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); | |
4750 | chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); | |
4751 | chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); | |
4752 | chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); | |
4753 | chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); | |
4754 | chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); | |
4755 | chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); | |
4756 | chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); | |
4757 | chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); | |
4758 | chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); | |
4759 | chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); | |
4760 | chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); | |
4761 | ||
4762 | chipio_write_no_mutex(codec, 0x19042c, 0x00000001); | |
4763 | ||
4764 | codec_dbg(codec, "Startup Data exited, mutex released.\n"); | |
4765 | mutex_unlock(&spec->chipio_mutex); | |
4766 | } | |
4767 | ||
447fd8e9 CM |
4768 | /* |
4769 | * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands | |
4770 | * without a 0x20 source like normal. | |
4771 | */ | |
4772 | static void sbz_dsp_scp_startup(struct hda_codec *codec) | |
4773 | { | |
4774 | unsigned int tmp; | |
4775 | ||
4776 | tmp = 0x00000003; | |
4777 | dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); | |
4778 | ||
4779 | tmp = 0x00000000; | |
4780 | dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); | |
4781 | ||
4782 | tmp = 0x00000001; | |
4783 | dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); | |
4784 | ||
4785 | tmp = 0x00000004; | |
4786 | dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); | |
4787 | ||
4788 | tmp = 0x00000005; | |
4789 | dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); | |
4790 | ||
4791 | tmp = 0x00000000; | |
4792 | dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); | |
4793 | ||
4794 | } | |
4795 | ||
38ba69ff CM |
4796 | static void sbz_dsp_initial_mic_setup(struct hda_codec *codec) |
4797 | { | |
4798 | unsigned int tmp; | |
4799 | ||
4800 | chipio_set_stream_control(codec, 0x03, 0); | |
4801 | chipio_set_stream_control(codec, 0x04, 0); | |
4802 | ||
4803 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); | |
4804 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); | |
4805 | ||
4806 | tmp = FLOAT_THREE; | |
4807 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); | |
4808 | ||
4809 | chipio_set_stream_control(codec, 0x03, 1); | |
4810 | chipio_set_stream_control(codec, 0x04, 1); | |
4811 | ||
4812 | chipio_write(codec, 0x18b098, 0x0000000c); | |
4813 | chipio_write(codec, 0x18b09C, 0x0000000c); | |
4814 | } | |
4815 | ||
5aaca44d IM |
4816 | /* |
4817 | * Setup default parameters for DSP | |
4818 | */ | |
4819 | static void ca0132_setup_defaults(struct hda_codec *codec) | |
4820 | { | |
e8f1bd5d | 4821 | struct ca0132_spec *spec = codec->spec; |
5aaca44d IM |
4822 | unsigned int tmp; |
4823 | int num_fx; | |
4824 | int idx, i; | |
4825 | ||
e8f1bd5d | 4826 | if (spec->dsp_state != DSP_DOWNLOADED) |
5aaca44d IM |
4827 | return; |
4828 | ||
4829 | /* out, in effects + voicefx */ | |
4830 | num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; | |
4831 | for (idx = 0; idx < num_fx; idx++) { | |
4832 | for (i = 0; i <= ca0132_effects[idx].params; i++) { | |
4833 | dspio_set_uint_param(codec, ca0132_effects[idx].mid, | |
4834 | ca0132_effects[idx].reqs[i], | |
4835 | ca0132_effects[idx].def_vals[i]); | |
4836 | } | |
4837 | } | |
4838 | ||
4839 | /*remove DSP headroom*/ | |
4840 | tmp = FLOAT_ZERO; | |
4841 | dspio_set_uint_param(codec, 0x96, 0x3C, tmp); | |
4842 | ||
4843 | /*set speaker EQ bypass attenuation*/ | |
4844 | dspio_set_uint_param(codec, 0x8f, 0x01, tmp); | |
4845 | ||
4846 | /* set AMic1 and AMic2 as mono mic */ | |
4847 | tmp = FLOAT_ONE; | |
4848 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); | |
4849 | dspio_set_uint_param(codec, 0x80, 0x01, tmp); | |
4850 | ||
4851 | /* set AMic1 as CrystalVoice input */ | |
4852 | tmp = FLOAT_ONE; | |
4853 | dspio_set_uint_param(codec, 0x80, 0x05, tmp); | |
4854 | ||
4855 | /* set WUH source */ | |
4856 | tmp = FLOAT_TWO; | |
4857 | dspio_set_uint_param(codec, 0x31, 0x00, tmp); | |
4858 | } | |
4859 | ||
7e6ed62e CM |
4860 | /* |
4861 | * Setup default parameters for Recon3Di DSP. | |
4862 | */ | |
4863 | ||
4864 | static void r3di_setup_defaults(struct hda_codec *codec) | |
4865 | { | |
4866 | struct ca0132_spec *spec = codec->spec; | |
4867 | unsigned int tmp; | |
4868 | int num_fx; | |
4869 | int idx, i; | |
4870 | ||
4871 | if (spec->dsp_state != DSP_DOWNLOADED) | |
4872 | return; | |
4873 | ||
447fd8e9 | 4874 | r3di_dsp_scp_startup(codec); |
7e6ed62e CM |
4875 | |
4876 | r3di_dsp_initial_mic_setup(codec); | |
4877 | ||
4878 | /*remove DSP headroom*/ | |
4879 | tmp = FLOAT_ZERO; | |
4880 | dspio_set_uint_param(codec, 0x96, 0x3C, tmp); | |
4881 | ||
4882 | /* set WUH source */ | |
4883 | tmp = FLOAT_TWO; | |
4884 | dspio_set_uint_param(codec, 0x31, 0x00, tmp); | |
4885 | chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); | |
4886 | ||
4887 | /* Set speaker source? */ | |
4888 | dspio_set_uint_param(codec, 0x32, 0x00, tmp); | |
4889 | ||
4890 | r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); | |
4891 | ||
4892 | /* Setup effect defaults */ | |
4893 | num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; | |
4894 | for (idx = 0; idx < num_fx; idx++) { | |
4895 | for (i = 0; i <= ca0132_effects[idx].params; i++) { | |
4896 | dspio_set_uint_param(codec, | |
4897 | ca0132_effects[idx].mid, | |
4898 | ca0132_effects[idx].reqs[i], | |
4899 | ca0132_effects[idx].def_vals[i]); | |
4900 | } | |
4901 | } | |
4902 | ||
4903 | } | |
4904 | ||
38ba69ff CM |
4905 | /* |
4906 | * Setup default parameters for the Sound Blaster Z DSP. A lot more going on | |
4907 | * than the Chromebook setup. | |
4908 | */ | |
4909 | static void sbz_setup_defaults(struct hda_codec *codec) | |
4910 | { | |
4911 | struct ca0132_spec *spec = codec->spec; | |
4912 | unsigned int tmp, stream_format; | |
4913 | int num_fx; | |
4914 | int idx, i; | |
4915 | ||
4916 | if (spec->dsp_state != DSP_DOWNLOADED) | |
4917 | return; | |
4918 | ||
447fd8e9 | 4919 | sbz_dsp_scp_startup(codec); |
38ba69ff CM |
4920 | |
4921 | sbz_init_analog_mics(codec); | |
4922 | ||
4923 | sbz_connect_streams(codec); | |
4924 | ||
4925 | sbz_chipio_startup_data(codec); | |
4926 | ||
4927 | chipio_set_stream_control(codec, 0x03, 1); | |
4928 | chipio_set_stream_control(codec, 0x04, 1); | |
4929 | ||
4930 | /* | |
4931 | * Sets internal input loopback to off, used to have a switch to | |
4932 | * enable input loopback, but turned out to be way too buggy. | |
4933 | */ | |
4934 | tmp = FLOAT_ONE; | |
4935 | dspio_set_uint_param(codec, 0x37, 0x08, tmp); | |
4936 | dspio_set_uint_param(codec, 0x37, 0x10, tmp); | |
4937 | ||
4938 | /*remove DSP headroom*/ | |
4939 | tmp = FLOAT_ZERO; | |
4940 | dspio_set_uint_param(codec, 0x96, 0x3C, tmp); | |
4941 | ||
4942 | /* set WUH source */ | |
4943 | tmp = FLOAT_TWO; | |
4944 | dspio_set_uint_param(codec, 0x31, 0x00, tmp); | |
4945 | chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); | |
4946 | ||
4947 | /* Set speaker source? */ | |
4948 | dspio_set_uint_param(codec, 0x32, 0x00, tmp); | |
4949 | ||
4950 | sbz_dsp_initial_mic_setup(codec); | |
4951 | ||
4952 | ||
4953 | /* out, in effects + voicefx */ | |
4954 | num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; | |
4955 | for (idx = 0; idx < num_fx; idx++) { | |
4956 | for (i = 0; i <= ca0132_effects[idx].params; i++) { | |
4957 | dspio_set_uint_param(codec, | |
4958 | ca0132_effects[idx].mid, | |
4959 | ca0132_effects[idx].reqs[i], | |
4960 | ca0132_effects[idx].def_vals[i]); | |
4961 | } | |
4962 | } | |
4963 | ||
4964 | /* | |
4965 | * Have to make a stream to bind the sound output to, otherwise | |
4966 | * you'll get dead audio. Before I did this, it would bind to an | |
4967 | * audio input, and would never work | |
4968 | */ | |
4969 | stream_format = snd_hdac_calc_stream_format(48000, 2, | |
4970 | SNDRV_PCM_FORMAT_S32_LE, 32, 0); | |
4971 | ||
4972 | snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, | |
4973 | 0, stream_format); | |
4974 | ||
4975 | snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); | |
4976 | ||
4977 | snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, | |
4978 | 0, stream_format); | |
4979 | ||
4980 | snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); | |
4981 | } | |
4982 | ||
5aaca44d IM |
4983 | /* |
4984 | * Initialization of flags in chip | |
4985 | */ | |
4986 | static void ca0132_init_flags(struct hda_codec *codec) | |
4987 | { | |
009b8f97 CM |
4988 | struct ca0132_spec *spec = codec->spec; |
4989 | ||
4990 | if (spec->use_alt_functions) { | |
4991 | chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); | |
4992 | chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); | |
4993 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); | |
4994 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); | |
4995 | chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); | |
4996 | chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); | |
4997 | chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); | |
4998 | chipio_set_control_flag(codec, | |
4999 | CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); | |
5000 | chipio_set_control_flag(codec, | |
5001 | CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); | |
5002 | } else { | |
5003 | chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); | |
5004 | chipio_set_control_flag(codec, | |
5005 | CONTROL_FLAG_PORT_A_COMMON_MODE, 0); | |
5006 | chipio_set_control_flag(codec, | |
5007 | CONTROL_FLAG_PORT_D_COMMON_MODE, 0); | |
5008 | chipio_set_control_flag(codec, | |
5009 | CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); | |
5010 | chipio_set_control_flag(codec, | |
5011 | CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); | |
5012 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); | |
5013 | } | |
5aaca44d IM |
5014 | } |
5015 | ||
5016 | /* | |
5017 | * Initialization of parameters in chip | |
5018 | */ | |
5019 | static void ca0132_init_params(struct hda_codec *codec) | |
5020 | { | |
009b8f97 CM |
5021 | struct ca0132_spec *spec = codec->spec; |
5022 | ||
5023 | if (spec->use_alt_functions) { | |
5024 | chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); | |
5025 | chipio_set_conn_rate(codec, 0x0B, SR_48_000); | |
5026 | chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); | |
5027 | chipio_set_control_param(codec, 0, 0); | |
5028 | chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); | |
5029 | } | |
5030 | ||
5aaca44d IM |
5031 | chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); |
5032 | chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); | |
5033 | } | |
95c6e9cb | 5034 | |
e90f29e4 IM |
5035 | static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) |
5036 | { | |
5037 | chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); | |
5038 | chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); | |
5039 | chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); | |
5040 | chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); | |
5041 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); | |
5042 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); | |
5043 | ||
406261ce IM |
5044 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); |
5045 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); | |
e90f29e4 IM |
5046 | chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); |
5047 | } | |
5048 | ||
5049 | static bool ca0132_download_dsp_images(struct hda_codec *codec) | |
5050 | { | |
5051 | bool dsp_loaded = false; | |
8a19bcee | 5052 | struct ca0132_spec *spec = codec->spec; |
e90f29e4 | 5053 | const struct dsp_image_seg *dsp_os_image; |
15e4ba66 | 5054 | const struct firmware *fw_entry; |
8a19bcee CM |
5055 | /* |
5056 | * Alternate firmwares for different variants. The Recon3Di apparently | |
5057 | * can use the default firmware, but I'll leave the option in case | |
5058 | * it needs it again. | |
5059 | */ | |
5060 | switch (spec->quirk) { | |
5061 | case QUIRK_SBZ: | |
5062 | if (request_firmware(&fw_entry, SBZ_EFX_FILE, | |
5063 | codec->card->dev) != 0) { | |
5064 | codec_dbg(codec, "SBZ alt firmware not detected. "); | |
5065 | spec->alt_firmware_present = false; | |
5066 | } else { | |
5067 | codec_dbg(codec, "Sound Blaster Z firmware selected."); | |
5068 | spec->alt_firmware_present = true; | |
5069 | } | |
5070 | break; | |
5071 | case QUIRK_R3DI: | |
5072 | if (request_firmware(&fw_entry, R3DI_EFX_FILE, | |
5073 | codec->card->dev) != 0) { | |
5074 | codec_dbg(codec, "Recon3Di alt firmware not detected."); | |
5075 | spec->alt_firmware_present = false; | |
5076 | } else { | |
5077 | codec_dbg(codec, "Recon3Di firmware selected."); | |
5078 | spec->alt_firmware_present = true; | |
5079 | } | |
5080 | break; | |
5081 | default: | |
5082 | spec->alt_firmware_present = false; | |
5083 | break; | |
5084 | } | |
5085 | /* | |
5086 | * Use default ctefx.bin if no alt firmware is detected, or if none | |
5087 | * exists for your particular codec. | |
5088 | */ | |
5089 | if (!spec->alt_firmware_present) { | |
5090 | codec_dbg(codec, "Default firmware selected."); | |
5091 | if (request_firmware(&fw_entry, EFX_FILE, | |
5092 | codec->card->dev) != 0) | |
5093 | return false; | |
5094 | } | |
e90f29e4 | 5095 | |
15e4ba66 | 5096 | dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); |
d1d28500 | 5097 | if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { |
d9684bb5 | 5098 | codec_err(codec, "ca0132 DSP load image failed\n"); |
d1d28500 DR |
5099 | goto exit_download; |
5100 | } | |
5101 | ||
e90f29e4 IM |
5102 | dsp_loaded = dspload_wait_loaded(codec); |
5103 | ||
d1d28500 | 5104 | exit_download: |
15e4ba66 TI |
5105 | release_firmware(fw_entry); |
5106 | ||
e90f29e4 IM |
5107 | return dsp_loaded; |
5108 | } | |
5109 | ||
5110 | static void ca0132_download_dsp(struct hda_codec *codec) | |
5111 | { | |
5112 | struct ca0132_spec *spec = codec->spec; | |
5113 | ||
9a0869f4 TI |
5114 | #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP |
5115 | return; /* NOP */ | |
5116 | #endif | |
e90f29e4 | 5117 | |
e24aa0a4 TI |
5118 | if (spec->dsp_state == DSP_DOWNLOAD_FAILED) |
5119 | return; /* don't retry failures */ | |
5120 | ||
b714a710 | 5121 | chipio_enable_clocks(codec); |
e93ac30a CM |
5122 | if (spec->dsp_state != DSP_DOWNLOADED) { |
5123 | spec->dsp_state = DSP_DOWNLOADING; | |
5124 | ||
5125 | if (!ca0132_download_dsp_images(codec)) | |
5126 | spec->dsp_state = DSP_DOWNLOAD_FAILED; | |
5127 | else | |
5128 | spec->dsp_state = DSP_DOWNLOADED; | |
5129 | } | |
e90f29e4 | 5130 | |
009b8f97 CM |
5131 | /* For codecs using alt functions, this is already done earlier */ |
5132 | if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions)) | |
e90f29e4 IM |
5133 | ca0132_set_dsp_msr(codec, true); |
5134 | } | |
5135 | ||
f8fb1170 TI |
5136 | static void ca0132_process_dsp_response(struct hda_codec *codec, |
5137 | struct hda_jack_callback *callback) | |
e90f29e4 IM |
5138 | { |
5139 | struct ca0132_spec *spec = codec->spec; | |
5140 | ||
4e76a883 | 5141 | codec_dbg(codec, "ca0132_process_dsp_response\n"); |
e90f29e4 IM |
5142 | if (spec->wait_scp) { |
5143 | if (dspio_get_response_data(codec) >= 0) | |
5144 | spec->wait_scp = 0; | |
5145 | } | |
5146 | ||
5147 | dspio_clear_response_queue(codec); | |
5148 | } | |
5149 | ||
f8fb1170 | 5150 | static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) |
e90f29e4 | 5151 | { |
993884f6 | 5152 | struct ca0132_spec *spec = codec->spec; |
2ebab40e | 5153 | struct hda_jack_tbl *tbl; |
e90f29e4 | 5154 | |
f8fb1170 TI |
5155 | /* Delay enabling the HP amp, to let the mic-detection |
5156 | * state machine run. | |
5157 | */ | |
5158 | cancel_delayed_work_sync(&spec->unsol_hp_work); | |
2f35c630 | 5159 | schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); |
2ebab40e TI |
5160 | tbl = snd_hda_jack_tbl_get(codec, cb->nid); |
5161 | if (tbl) | |
5162 | tbl->block_report = 1; | |
f8fb1170 TI |
5163 | } |
5164 | ||
5165 | static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) | |
5166 | { | |
5167 | ca0132_select_mic(codec); | |
5168 | } | |
5169 | ||
5170 | static void ca0132_init_unsol(struct hda_codec *codec) | |
5171 | { | |
d5c016b5 GM |
5172 | struct ca0132_spec *spec = codec->spec; |
5173 | snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); | |
5174 | snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, | |
f8fb1170 TI |
5175 | amic_callback); |
5176 | snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, | |
5177 | ca0132_process_dsp_response); | |
63177afc | 5178 | /* Front headphone jack detection */ |
009b8f97 | 5179 | if (spec->use_alt_functions) |
63177afc CM |
5180 | snd_hda_jack_detect_enable_callback(codec, |
5181 | spec->unsol_tag_front_hp, hp_callback); | |
e90f29e4 IM |
5182 | } |
5183 | ||
5aaca44d IM |
5184 | /* |
5185 | * Verbs tables. | |
5186 | */ | |
5187 | ||
5188 | /* Sends before DSP download. */ | |
5189 | static struct hda_verb ca0132_base_init_verbs[] = { | |
5190 | /*enable ct extension*/ | |
5191 | {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, | |
5aaca44d IM |
5192 | {} |
5193 | }; | |
5194 | ||
5195 | /* Send at exit. */ | |
5196 | static struct hda_verb ca0132_base_exit_verbs[] = { | |
5197 | /*set afg to D3*/ | |
5198 | {0x01, AC_VERB_SET_POWER_STATE, 0x03}, | |
5199 | /*disable ct extension*/ | |
5200 | {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, | |
5201 | {} | |
5202 | }; | |
5203 | ||
8a19bcee | 5204 | /* Other verbs tables. Sends after DSP download. */ |
e93ac30a | 5205 | |
5aaca44d IM |
5206 | static struct hda_verb ca0132_init_verbs0[] = { |
5207 | /* chip init verbs */ | |
5208 | {0x15, 0x70D, 0xF0}, | |
5209 | {0x15, 0x70E, 0xFE}, | |
5210 | {0x15, 0x707, 0x75}, | |
5211 | {0x15, 0x707, 0xD3}, | |
5212 | {0x15, 0x707, 0x09}, | |
5213 | {0x15, 0x707, 0x53}, | |
5214 | {0x15, 0x707, 0xD4}, | |
5215 | {0x15, 0x707, 0xEF}, | |
5216 | {0x15, 0x707, 0x75}, | |
5217 | {0x15, 0x707, 0xD3}, | |
5218 | {0x15, 0x707, 0x09}, | |
5219 | {0x15, 0x707, 0x02}, | |
5220 | {0x15, 0x707, 0x37}, | |
5221 | {0x15, 0x707, 0x78}, | |
5222 | {0x15, 0x53C, 0xCE}, | |
5223 | {0x15, 0x575, 0xC9}, | |
5224 | {0x15, 0x53D, 0xCE}, | |
5225 | {0x15, 0x5B7, 0xC9}, | |
5226 | {0x15, 0x70D, 0xE8}, | |
5227 | {0x15, 0x70E, 0xFE}, | |
5228 | {0x15, 0x707, 0x02}, | |
5229 | {0x15, 0x707, 0x68}, | |
5230 | {0x15, 0x707, 0x62}, | |
5231 | {0x15, 0x53A, 0xCE}, | |
5232 | {0x15, 0x546, 0xC9}, | |
5233 | {0x15, 0x53B, 0xCE}, | |
5234 | {0x15, 0x5E8, 0xC9}, | |
e93ac30a CM |
5235 | {} |
5236 | }; | |
5237 | ||
5238 | /* Extra init verbs for SBZ */ | |
5239 | static struct hda_verb sbz_init_verbs[] = { | |
5240 | {0x15, 0x70D, 0x20}, | |
5241 | {0x15, 0x70E, 0x19}, | |
5242 | {0x15, 0x707, 0x00}, | |
5243 | {0x15, 0x539, 0xCE}, | |
5244 | {0x15, 0x546, 0xC9}, | |
5245 | {0x15, 0x70D, 0xB7}, | |
5246 | {0x15, 0x70E, 0x09}, | |
5247 | {0x15, 0x707, 0x10}, | |
5248 | {0x15, 0x70D, 0xAF}, | |
5249 | {0x15, 0x70E, 0x09}, | |
5250 | {0x15, 0x707, 0x01}, | |
5251 | {0x15, 0x707, 0x05}, | |
5252 | {0x15, 0x70D, 0x73}, | |
5253 | {0x15, 0x70E, 0x09}, | |
5254 | {0x15, 0x707, 0x14}, | |
5255 | {0x15, 0x6FF, 0xC4}, | |
5aaca44d IM |
5256 | {} |
5257 | }; | |
5258 | ||
95c6e9cb IM |
5259 | static void ca0132_init_chip(struct hda_codec *codec) |
5260 | { | |
5261 | struct ca0132_spec *spec = codec->spec; | |
5aaca44d IM |
5262 | int num_fx; |
5263 | int i; | |
5264 | unsigned int on; | |
95c6e9cb IM |
5265 | |
5266 | mutex_init(&spec->chipio_mutex); | |
5aaca44d IM |
5267 | |
5268 | spec->cur_out_type = SPEAKER_OUT; | |
5269 | spec->cur_mic_type = DIGITAL_MIC; | |
5270 | spec->cur_mic_boost = 0; | |
5271 | ||
5272 | for (i = 0; i < VNODES_COUNT; i++) { | |
5273 | spec->vnode_lvol[i] = 0x5a; | |
5274 | spec->vnode_rvol[i] = 0x5a; | |
5275 | spec->vnode_lswitch[i] = 0; | |
5276 | spec->vnode_rswitch[i] = 0; | |
5277 | } | |
5278 | ||
5279 | /* | |
5280 | * Default states for effects are in ca0132_effects[]. | |
5281 | */ | |
5282 | num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; | |
5283 | for (i = 0; i < num_fx; i++) { | |
5284 | on = (unsigned int)ca0132_effects[i].reqs[0]; | |
5285 | spec->effects_switch[i] = on ? 1 : 0; | |
5286 | } | |
5287 | ||
5288 | spec->voicefx_val = 0; | |
5289 | spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; | |
5290 | spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; | |
5291 | ||
44f0c978 IM |
5292 | #ifdef ENABLE_TUNING_CONTROLS |
5293 | ca0132_init_tuning_defaults(codec); | |
5294 | #endif | |
95c6e9cb IM |
5295 | } |
5296 | ||
2e48b2b7 CM |
5297 | /* |
5298 | * Recon3Di exit specific commands. | |
5299 | */ | |
5300 | /* prevents popping noise on shutdown */ | |
5301 | static void r3di_gpio_shutdown(struct hda_codec *codec) | |
5302 | { | |
5303 | snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); | |
5304 | } | |
5305 | ||
5306 | /* | |
5307 | * Sound Blaster Z exit specific commands. | |
5308 | */ | |
5309 | static void sbz_region2_exit(struct hda_codec *codec) | |
5310 | { | |
5311 | struct ca0132_spec *spec = codec->spec; | |
5312 | unsigned int i; | |
5313 | ||
5314 | for (i = 0; i < 4; i++) | |
5315 | writeb(0x0, spec->mem_base + 0x100); | |
5316 | for (i = 0; i < 8; i++) | |
5317 | writeb(0xb3, spec->mem_base + 0x304); | |
5318 | /* | |
5319 | * I believe these are GPIO, with the right most hex digit being the | |
5320 | * gpio pin, and the second digit being on or off. We see this more in | |
5321 | * the input/output select functions. | |
5322 | */ | |
5323 | writew(0x0000, spec->mem_base + 0x320); | |
5324 | writew(0x0001, spec->mem_base + 0x320); | |
5325 | writew(0x0104, spec->mem_base + 0x320); | |
5326 | writew(0x0005, spec->mem_base + 0x320); | |
5327 | writew(0x0007, spec->mem_base + 0x320); | |
5328 | } | |
5329 | ||
5330 | static void sbz_set_pin_ctl_default(struct hda_codec *codec) | |
5331 | { | |
5332 | hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; | |
5333 | unsigned int i; | |
5334 | ||
5335 | snd_hda_codec_write(codec, 0x11, 0, | |
5336 | AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); | |
5337 | ||
5338 | for (i = 0; i < 5; i++) | |
5339 | snd_hda_codec_write(codec, pins[i], 0, | |
5340 | AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); | |
5341 | } | |
5342 | ||
5343 | static void sbz_clear_unsolicited(struct hda_codec *codec) | |
5344 | { | |
5345 | hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; | |
5346 | unsigned int i; | |
5347 | ||
5348 | for (i = 0; i < 7; i++) { | |
5349 | snd_hda_codec_write(codec, pins[i], 0, | |
5350 | AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); | |
5351 | } | |
5352 | } | |
5353 | ||
5354 | /* On shutdown, sends commands in sets of three */ | |
5355 | static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, | |
5356 | int mask, int data) | |
5357 | { | |
5358 | if (dir >= 0) | |
5359 | snd_hda_codec_write(codec, 0x01, 0, | |
5360 | AC_VERB_SET_GPIO_DIRECTION, dir); | |
5361 | if (mask >= 0) | |
5362 | snd_hda_codec_write(codec, 0x01, 0, | |
5363 | AC_VERB_SET_GPIO_MASK, mask); | |
5364 | ||
5365 | if (data >= 0) | |
5366 | snd_hda_codec_write(codec, 0x01, 0, | |
5367 | AC_VERB_SET_GPIO_DATA, data); | |
5368 | } | |
5369 | ||
5370 | static void sbz_exit_chip(struct hda_codec *codec) | |
5371 | { | |
009b8f97 CM |
5372 | chipio_set_stream_control(codec, 0x03, 0); |
5373 | chipio_set_stream_control(codec, 0x04, 0); | |
2e48b2b7 CM |
5374 | |
5375 | /* Mess with GPIO */ | |
5376 | sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); | |
5377 | sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); | |
5378 | sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); | |
5379 | ||
009b8f97 CM |
5380 | chipio_set_stream_control(codec, 0x14, 0); |
5381 | chipio_set_stream_control(codec, 0x0C, 0); | |
2e48b2b7 CM |
5382 | |
5383 | chipio_set_conn_rate(codec, 0x41, SR_192_000); | |
5384 | chipio_set_conn_rate(codec, 0x91, SR_192_000); | |
5385 | ||
5386 | chipio_write(codec, 0x18a020, 0x00000083); | |
5387 | ||
5388 | sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); | |
5389 | sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); | |
5390 | sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); | |
5391 | ||
009b8f97 | 5392 | chipio_set_stream_control(codec, 0x0C, 0); |
2e48b2b7 CM |
5393 | |
5394 | chipio_set_control_param(codec, 0x0D, 0x24); | |
5395 | ||
5396 | sbz_clear_unsolicited(codec); | |
5397 | sbz_set_pin_ctl_default(codec); | |
5398 | ||
5399 | snd_hda_codec_write(codec, 0x0B, 0, | |
5400 | AC_VERB_SET_EAPD_BTLENABLE, 0x00); | |
5401 | ||
5402 | if (dspload_is_loaded(codec)) | |
5403 | dsp_reset(codec); | |
5404 | ||
5405 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5406 | VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x00); | |
5407 | ||
5408 | sbz_region2_exit(codec); | |
5409 | } | |
5410 | ||
95c6e9cb IM |
5411 | static void ca0132_exit_chip(struct hda_codec *codec) |
5412 | { | |
5413 | /* put any chip cleanup stuffs here. */ | |
5aaca44d IM |
5414 | |
5415 | if (dspload_is_loaded(codec)) | |
5416 | dsp_reset(codec); | |
95c6e9cb IM |
5417 | } |
5418 | ||
38ba69ff CM |
5419 | /* |
5420 | * This fixes a problem that was hard to reproduce. Very rarely, I would | |
5421 | * boot up, and there would be no sound, but the DSP indicated it had loaded | |
5422 | * properly. I did a few memory dumps to see if anything was different, and | |
5423 | * there were a few areas of memory uninitialized with a1a2a3a4. This function | |
5424 | * checks if those areas are uninitialized, and if they are, it'll attempt to | |
5425 | * reload the card 3 times. Usually it fixes by the second. | |
5426 | */ | |
5427 | static void sbz_dsp_startup_check(struct hda_codec *codec) | |
5428 | { | |
5429 | struct ca0132_spec *spec = codec->spec; | |
5430 | unsigned int dsp_data_check[4]; | |
5431 | unsigned int cur_address = 0x390; | |
5432 | unsigned int i; | |
5433 | unsigned int failure = 0; | |
5434 | unsigned int reload = 3; | |
5435 | ||
5436 | if (spec->startup_check_entered) | |
5437 | return; | |
5438 | ||
5439 | spec->startup_check_entered = true; | |
5440 | ||
5441 | for (i = 0; i < 4; i++) { | |
5442 | chipio_read(codec, cur_address, &dsp_data_check[i]); | |
5443 | cur_address += 0x4; | |
5444 | } | |
5445 | for (i = 0; i < 4; i++) { | |
5446 | if (dsp_data_check[i] == 0xa1a2a3a4) | |
5447 | failure = 1; | |
5448 | } | |
5449 | ||
5450 | codec_dbg(codec, "Startup Check: %d ", failure); | |
5451 | if (failure) | |
5452 | codec_info(codec, "DSP not initialized properly. Attempting to fix."); | |
5453 | /* | |
5454 | * While the failure condition is true, and we haven't reached our | |
5455 | * three reload limit, continue trying to reload the driver and | |
5456 | * fix the issue. | |
5457 | */ | |
5458 | while (failure && (reload != 0)) { | |
5459 | codec_info(codec, "Reloading... Tries left: %d", reload); | |
5460 | sbz_exit_chip(codec); | |
5461 | spec->dsp_state = DSP_DOWNLOAD_INIT; | |
5462 | codec->patch_ops.init(codec); | |
5463 | failure = 0; | |
5464 | for (i = 0; i < 4; i++) { | |
5465 | chipio_read(codec, cur_address, &dsp_data_check[i]); | |
5466 | cur_address += 0x4; | |
5467 | } | |
5468 | for (i = 0; i < 4; i++) { | |
5469 | if (dsp_data_check[i] == 0xa1a2a3a4) | |
5470 | failure = 1; | |
5471 | } | |
5472 | reload--; | |
5473 | } | |
5474 | ||
5475 | if (!failure && reload < 3) | |
5476 | codec_info(codec, "DSP fixed."); | |
5477 | ||
5478 | if (!failure) | |
5479 | return; | |
5480 | ||
5481 | codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); | |
5482 | } | |
5483 | ||
e93ac30a CM |
5484 | /* |
5485 | * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add | |
5486 | * extra precision for decibel values. If you had the dB value in floating point | |
5487 | * you would take the value after the decimal point, multiply by 64, and divide | |
5488 | * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to | |
5489 | * implement fixed point or floating point dB volumes. For now, I'll set them | |
5490 | * to 0 just incase a value has lingered from a boot into Windows. | |
5491 | */ | |
5492 | static void ca0132_alt_vol_setup(struct hda_codec *codec) | |
5493 | { | |
5494 | snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); | |
5495 | snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); | |
5496 | snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); | |
5497 | snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); | |
5498 | snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); | |
5499 | snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); | |
5500 | snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); | |
5501 | snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); | |
5502 | } | |
5503 | ||
5504 | /* | |
5505 | * Extra commands that don't really fit anywhere else. | |
5506 | */ | |
5507 | static void sbz_pre_dsp_setup(struct hda_codec *codec) | |
5508 | { | |
5509 | struct ca0132_spec *spec = codec->spec; | |
5510 | ||
5511 | writel(0x00820680, spec->mem_base + 0x01C); | |
5512 | writel(0x00820680, spec->mem_base + 0x01C); | |
5513 | ||
5514 | snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc); | |
5515 | snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd); | |
5516 | snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe); | |
5517 | snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff); | |
5518 | ||
5519 | chipio_write(codec, 0x18b0a4, 0x000000c2); | |
5520 | ||
5521 | snd_hda_codec_write(codec, 0x11, 0, | |
5522 | AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); | |
5523 | } | |
5524 | ||
5525 | /* | |
5526 | * Extra commands that don't really fit anywhere else. | |
5527 | */ | |
5528 | static void r3di_pre_dsp_setup(struct hda_codec *codec) | |
5529 | { | |
5530 | chipio_write(codec, 0x18b0a4, 0x000000c2); | |
5531 | ||
5532 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5533 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); | |
5534 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5535 | VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); | |
5536 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5537 | VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); | |
5538 | ||
5539 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5540 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); | |
5541 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5542 | VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); | |
5543 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5544 | VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); | |
5545 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5546 | VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); | |
5547 | ||
5548 | snd_hda_codec_write(codec, 0x11, 0, | |
5549 | AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); | |
5550 | } | |
5551 | ||
5552 | ||
5553 | /* | |
5554 | * These are sent before the DSP is downloaded. Not sure | |
5555 | * what they do, or if they're necessary. Could possibly | |
5556 | * be removed. Figure they're better to leave in. | |
5557 | */ | |
5558 | static void sbz_region2_startup(struct hda_codec *codec) | |
5559 | { | |
5560 | struct ca0132_spec *spec = codec->spec; | |
5561 | ||
5562 | writel(0x00000000, spec->mem_base + 0x400); | |
5563 | writel(0x00000000, spec->mem_base + 0x408); | |
5564 | writel(0x00000000, spec->mem_base + 0x40C); | |
5565 | writel(0x00880680, spec->mem_base + 0x01C); | |
5566 | writel(0x00000083, spec->mem_base + 0xC0C); | |
5567 | writel(0x00000030, spec->mem_base + 0xC00); | |
5568 | writel(0x00000000, spec->mem_base + 0xC04); | |
5569 | writel(0x00000003, spec->mem_base + 0xC0C); | |
5570 | writel(0x00000003, spec->mem_base + 0xC0C); | |
5571 | writel(0x00000003, spec->mem_base + 0xC0C); | |
5572 | writel(0x00000003, spec->mem_base + 0xC0C); | |
5573 | writel(0x000000C1, spec->mem_base + 0xC08); | |
5574 | writel(0x000000F1, spec->mem_base + 0xC08); | |
5575 | writel(0x00000001, spec->mem_base + 0xC08); | |
5576 | writel(0x000000C7, spec->mem_base + 0xC08); | |
5577 | writel(0x000000C1, spec->mem_base + 0xC08); | |
5578 | writel(0x00000080, spec->mem_base + 0xC04); | |
5579 | } | |
5580 | ||
5581 | /* | |
5582 | * Extra init functions for alternative ca0132 codecs. Done | |
5583 | * here so they don't clutter up the main ca0132_init function | |
5584 | * anymore than they have to. | |
5585 | */ | |
5586 | static void ca0132_alt_init(struct hda_codec *codec) | |
5587 | { | |
5588 | struct ca0132_spec *spec = codec->spec; | |
5589 | ||
5590 | ca0132_alt_vol_setup(codec); | |
5591 | ||
5592 | switch (spec->quirk) { | |
5593 | case QUIRK_SBZ: | |
5594 | codec_dbg(codec, "SBZ alt_init"); | |
5595 | ca0132_gpio_init(codec); | |
5596 | sbz_pre_dsp_setup(codec); | |
5597 | snd_hda_sequence_write(codec, spec->chip_init_verbs); | |
5598 | snd_hda_sequence_write(codec, spec->sbz_init_verbs); | |
5599 | break; | |
5600 | case QUIRK_R3DI: | |
5601 | codec_dbg(codec, "R3DI alt_init"); | |
5602 | ca0132_gpio_init(codec); | |
5603 | ca0132_gpio_setup(codec); | |
7e6ed62e | 5604 | r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); |
e93ac30a CM |
5605 | r3di_pre_dsp_setup(codec); |
5606 | snd_hda_sequence_write(codec, spec->chip_init_verbs); | |
5607 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); | |
5608 | break; | |
5609 | } | |
5610 | } | |
5611 | ||
95c6e9cb IM |
5612 | static int ca0132_init(struct hda_codec *codec) |
5613 | { | |
5614 | struct ca0132_spec *spec = codec->spec; | |
5615 | struct auto_pin_cfg *cfg = &spec->autocfg; | |
5616 | int i; | |
e93ac30a CM |
5617 | bool dsp_loaded; |
5618 | ||
5619 | /* | |
5620 | * If the DSP is already downloaded, and init has been entered again, | |
5621 | * there's only two reasons for it. One, the codec has awaken from a | |
5622 | * suspended state, and in that case dspload_is_loaded will return | |
5623 | * false, and the init will be ran again. The other reason it gets | |
5624 | * re entered is on startup for some reason it triggers a suspend and | |
5625 | * resume state. In this case, it will check if the DSP is downloaded, | |
5626 | * and not run the init function again. For codecs using alt_functions, | |
5627 | * it will check if the DSP is loaded properly. | |
5628 | */ | |
5629 | if (spec->dsp_state == DSP_DOWNLOADED) { | |
5630 | dsp_loaded = dspload_is_loaded(codec); | |
5631 | if (!dsp_loaded) { | |
5632 | spec->dsp_reload = true; | |
5633 | spec->dsp_state = DSP_DOWNLOAD_INIT; | |
38ba69ff CM |
5634 | } else { |
5635 | if (spec->quirk == QUIRK_SBZ) | |
5636 | sbz_dsp_startup_check(codec); | |
e93ac30a | 5637 | return 0; |
38ba69ff | 5638 | } |
e93ac30a | 5639 | } |
95c6e9cb | 5640 | |
e24aa0a4 TI |
5641 | if (spec->dsp_state != DSP_DOWNLOAD_FAILED) |
5642 | spec->dsp_state = DSP_DOWNLOAD_INIT; | |
4a8b89f9 | 5643 | spec->curr_chip_addx = INVALID_CHIP_ADDRESS; |
5aaca44d | 5644 | |
e93ac30a CM |
5645 | if (spec->quirk == QUIRK_SBZ) |
5646 | sbz_region2_startup(codec); | |
5647 | ||
664c7155 | 5648 | snd_hda_power_up_pm(codec); |
5aaca44d | 5649 | |
f8fb1170 | 5650 | ca0132_init_unsol(codec); |
5aaca44d IM |
5651 | ca0132_init_params(codec); |
5652 | ca0132_init_flags(codec); | |
7e6ed62e | 5653 | |
5aaca44d | 5654 | snd_hda_sequence_write(codec, spec->base_init_verbs); |
e93ac30a CM |
5655 | |
5656 | if (spec->quirk != QUIRK_NONE) | |
5657 | ca0132_alt_init(codec); | |
5658 | ||
01ef7dbf | 5659 | ca0132_download_dsp(codec); |
7e6ed62e | 5660 | |
5aaca44d | 5661 | ca0132_refresh_widget_caps(codec); |
e93ac30a CM |
5662 | |
5663 | if (spec->quirk == QUIRK_SBZ) | |
5664 | writew(0x0107, spec->mem_base + 0x320); | |
5665 | ||
7e6ed62e CM |
5666 | switch (spec->quirk) { |
5667 | case QUIRK_R3DI: | |
5668 | r3di_setup_defaults(codec); | |
5669 | break; | |
5670 | case QUIRK_NONE: | |
5671 | case QUIRK_ALIENWARE: | |
38ba69ff CM |
5672 | ca0132_setup_defaults(codec); |
5673 | ca0132_init_analog_mic2(codec); | |
5674 | ca0132_init_dmic(codec); | |
7e6ed62e | 5675 | break; |
38ba69ff | 5676 | } |
5aaca44d IM |
5677 | |
5678 | for (i = 0; i < spec->num_outputs; i++) | |
5679 | init_output(codec, spec->out_pins[i], spec->dacs[0]); | |
01ef7dbf | 5680 | |
95c6e9cb IM |
5681 | init_output(codec, cfg->dig_out_pins[0], spec->dig_out); |
5682 | ||
5683 | for (i = 0; i < spec->num_inputs; i++) | |
5684 | init_input(codec, spec->input_pins[i], spec->adcs[i]); | |
5685 | ||
5686 | init_input(codec, cfg->dig_in_pin, spec->dig_in); | |
5687 | ||
009b8f97 | 5688 | if (!spec->use_alt_functions) { |
e93ac30a CM |
5689 | snd_hda_sequence_write(codec, spec->chip_init_verbs); |
5690 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5691 | VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); | |
5692 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, | |
5693 | VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); | |
5694 | } | |
5695 | ||
38ba69ff | 5696 | if (spec->quirk == QUIRK_SBZ) { |
e93ac30a | 5697 | ca0132_gpio_setup(codec); |
38ba69ff CM |
5698 | sbz_setup_defaults(codec); |
5699 | } | |
e93ac30a | 5700 | |
d5c016b5 | 5701 | snd_hda_sequence_write(codec, spec->spec_init_verbs); |
5aaca44d IM |
5702 | |
5703 | ca0132_select_out(codec); | |
5704 | ca0132_select_mic(codec); | |
5705 | ||
a73d511c IM |
5706 | snd_hda_jack_report_sync(codec); |
5707 | ||
e93ac30a CM |
5708 | /* |
5709 | * Re set the PlayEnhancement switch on a resume event, because the | |
5710 | * controls will not be reloaded. | |
5711 | */ | |
5712 | if (spec->dsp_reload) { | |
5713 | spec->dsp_reload = false; | |
5714 | ca0132_pe_switch_set(codec); | |
5715 | } | |
5716 | ||
664c7155 | 5717 | snd_hda_power_down_pm(codec); |
95c6e9cb IM |
5718 | |
5719 | return 0; | |
5720 | } | |
5721 | ||
95c6e9cb IM |
5722 | static void ca0132_free(struct hda_codec *codec) |
5723 | { | |
5aaca44d IM |
5724 | struct ca0132_spec *spec = codec->spec; |
5725 | ||
993884f6 | 5726 | cancel_delayed_work_sync(&spec->unsol_hp_work); |
5aaca44d | 5727 | snd_hda_power_up(codec); |
2e48b2b7 CM |
5728 | switch (spec->quirk) { |
5729 | case QUIRK_SBZ: | |
5730 | sbz_exit_chip(codec); | |
5731 | break; | |
5732 | case QUIRK_R3DI: | |
5733 | r3di_gpio_shutdown(codec); | |
5734 | snd_hda_sequence_write(codec, spec->base_exit_verbs); | |
5735 | ca0132_exit_chip(codec); | |
5736 | break; | |
5737 | default: | |
5738 | snd_hda_sequence_write(codec, spec->base_exit_verbs); | |
5739 | ca0132_exit_chip(codec); | |
5740 | break; | |
5741 | } | |
5aaca44d | 5742 | snd_hda_power_down(codec); |
aa31704f CM |
5743 | if (spec->mem_base) |
5744 | iounmap(spec->mem_base); | |
d5c016b5 | 5745 | kfree(spec->spec_init_verbs); |
95c6e9cb IM |
5746 | kfree(codec->spec); |
5747 | } | |
5748 | ||
2e48b2b7 CM |
5749 | static void ca0132_reboot_notify(struct hda_codec *codec) |
5750 | { | |
5751 | codec->patch_ops.free(codec); | |
5752 | } | |
5753 | ||
071f1344 | 5754 | static const struct hda_codec_ops ca0132_patch_ops = { |
95c6e9cb IM |
5755 | .build_controls = ca0132_build_controls, |
5756 | .build_pcms = ca0132_build_pcms, | |
5757 | .init = ca0132_init, | |
5758 | .free = ca0132_free, | |
f8fb1170 | 5759 | .unsol_event = snd_hda_jack_unsol_event, |
2e48b2b7 | 5760 | .reboot_notify = ca0132_reboot_notify, |
95c6e9cb IM |
5761 | }; |
5762 | ||
441aa6a0 IM |
5763 | static void ca0132_config(struct hda_codec *codec) |
5764 | { | |
5765 | struct ca0132_spec *spec = codec->spec; | |
5766 | struct auto_pin_cfg *cfg = &spec->autocfg; | |
5767 | ||
5768 | spec->dacs[0] = 0x2; | |
5769 | spec->dacs[1] = 0x3; | |
5770 | spec->dacs[2] = 0x4; | |
5771 | ||
5772 | spec->multiout.dac_nids = spec->dacs; | |
5773 | spec->multiout.num_dacs = 3; | |
441aa6a0 | 5774 | |
009b8f97 | 5775 | if (!spec->use_alt_functions) |
63177afc CM |
5776 | spec->multiout.max_channels = 2; |
5777 | else | |
5778 | spec->multiout.max_channels = 6; | |
5779 | ||
5780 | switch (spec->quirk) { | |
5781 | case QUIRK_ALIENWARE: | |
d5c016b5 | 5782 | codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n"); |
fe14f39e TI |
5783 | snd_hda_apply_pincfgs(codec, alienware_pincfgs); |
5784 | ||
5785 | spec->num_outputs = 2; | |
5786 | spec->out_pins[0] = 0x0b; /* speaker out */ | |
d5c016b5 | 5787 | spec->out_pins[1] = 0x0f; |
fe14f39e TI |
5788 | spec->shared_out_nid = 0x2; |
5789 | spec->unsol_tag_hp = 0x0f; | |
5790 | ||
5791 | spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ | |
5792 | spec->adcs[1] = 0x8; /* analog mic2 */ | |
5793 | spec->adcs[2] = 0xa; /* what u hear */ | |
5794 | ||
5795 | spec->num_inputs = 3; | |
5796 | spec->input_pins[0] = 0x12; | |
5797 | spec->input_pins[1] = 0x11; | |
5798 | spec->input_pins[2] = 0x13; | |
5799 | spec->shared_mic_nid = 0x7; | |
5800 | spec->unsol_tag_amic1 = 0x11; | |
63177afc CM |
5801 | break; |
5802 | case QUIRK_SBZ: | |
5803 | codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); | |
5804 | snd_hda_apply_pincfgs(codec, sbz_pincfgs); | |
5805 | ||
5806 | spec->num_outputs = 2; | |
5807 | spec->out_pins[0] = 0x0B; /* Line out */ | |
5808 | spec->out_pins[1] = 0x0F; /* Rear headphone out */ | |
5809 | spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ | |
5810 | spec->out_pins[3] = 0x11; /* Rear surround */ | |
5811 | spec->shared_out_nid = 0x2; | |
5812 | spec->unsol_tag_hp = spec->out_pins[1]; | |
5813 | spec->unsol_tag_front_hp = spec->out_pins[2]; | |
5814 | ||
5815 | spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ | |
5816 | spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ | |
5817 | spec->adcs[2] = 0xa; /* what u hear */ | |
5818 | ||
5819 | spec->num_inputs = 2; | |
5820 | spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ | |
5821 | spec->input_pins[1] = 0x13; /* What U Hear */ | |
5822 | spec->shared_mic_nid = 0x7; | |
5823 | spec->unsol_tag_amic1 = spec->input_pins[0]; | |
5824 | ||
5825 | /* SPDIF I/O */ | |
5826 | spec->dig_out = 0x05; | |
5827 | spec->multiout.dig_out_nid = spec->dig_out; | |
5828 | cfg->dig_out_pins[0] = 0x0c; | |
5829 | cfg->dig_outs = 1; | |
5830 | cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF; | |
5831 | spec->dig_in = 0x09; | |
5832 | cfg->dig_in_pin = 0x0e; | |
5833 | cfg->dig_in_type = HDA_PCM_TYPE_SPDIF; | |
5834 | break; | |
5835 | case QUIRK_R3DI: | |
5836 | codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); | |
5837 | snd_hda_apply_pincfgs(codec, r3di_pincfgs); | |
5838 | ||
5839 | spec->num_outputs = 2; | |
5840 | spec->out_pins[0] = 0x0B; /* Line out */ | |
5841 | spec->out_pins[1] = 0x0F; /* Rear headphone out */ | |
5842 | spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ | |
5843 | spec->out_pins[3] = 0x11; /* Rear surround */ | |
5844 | spec->shared_out_nid = 0x2; | |
5845 | spec->unsol_tag_hp = spec->out_pins[1]; | |
5846 | spec->unsol_tag_front_hp = spec->out_pins[2]; | |
5847 | ||
5848 | spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ | |
5849 | spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ | |
5850 | spec->adcs[2] = 0x0a; /* what u hear */ | |
5851 | ||
5852 | spec->num_inputs = 2; | |
5853 | spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ | |
5854 | spec->input_pins[1] = 0x13; /* What U Hear */ | |
5855 | spec->shared_mic_nid = 0x7; | |
5856 | spec->unsol_tag_amic1 = spec->input_pins[0]; | |
5857 | ||
5858 | /* SPDIF I/O */ | |
5859 | spec->dig_out = 0x05; | |
5860 | spec->multiout.dig_out_nid = spec->dig_out; | |
5861 | cfg->dig_out_pins[0] = 0x0c; | |
5862 | cfg->dig_outs = 1; | |
5863 | cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF; | |
5864 | break; | |
5865 | default: | |
fe14f39e TI |
5866 | spec->num_outputs = 2; |
5867 | spec->out_pins[0] = 0x0b; /* speaker out */ | |
d5c016b5 | 5868 | spec->out_pins[1] = 0x10; /* headphone out */ |
fe14f39e TI |
5869 | spec->shared_out_nid = 0x2; |
5870 | spec->unsol_tag_hp = spec->out_pins[1]; | |
5871 | ||
5872 | spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ | |
5873 | spec->adcs[1] = 0x8; /* analog mic2 */ | |
5874 | spec->adcs[2] = 0xa; /* what u hear */ | |
5875 | ||
5876 | spec->num_inputs = 3; | |
5877 | spec->input_pins[0] = 0x12; | |
5878 | spec->input_pins[1] = 0x11; | |
5879 | spec->input_pins[2] = 0x13; | |
5880 | spec->shared_mic_nid = 0x7; | |
5881 | spec->unsol_tag_amic1 = spec->input_pins[0]; | |
5882 | ||
5883 | /* SPDIF I/O */ | |
5884 | spec->dig_out = 0x05; | |
5885 | spec->multiout.dig_out_nid = spec->dig_out; | |
5886 | cfg->dig_out_pins[0] = 0x0c; | |
5887 | cfg->dig_outs = 1; | |
5888 | cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF; | |
5889 | spec->dig_in = 0x09; | |
5890 | cfg->dig_in_pin = 0x0e; | |
5891 | cfg->dig_in_type = HDA_PCM_TYPE_SPDIF; | |
63177afc | 5892 | break; |
d5c016b5 | 5893 | } |
441aa6a0 IM |
5894 | } |
5895 | ||
d5c016b5 GM |
5896 | static int ca0132_prepare_verbs(struct hda_codec *codec) |
5897 | { | |
5898 | /* Verbs + terminator (an empty element) */ | |
5899 | #define NUM_SPEC_VERBS 4 | |
5900 | struct ca0132_spec *spec = codec->spec; | |
5901 | ||
5902 | spec->chip_init_verbs = ca0132_init_verbs0; | |
e93ac30a CM |
5903 | if (spec->quirk == QUIRK_SBZ) |
5904 | spec->sbz_init_verbs = sbz_init_verbs; | |
d5c016b5 GM |
5905 | spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL); |
5906 | if (!spec->spec_init_verbs) | |
5907 | return -ENOMEM; | |
5908 | ||
5909 | /* HP jack autodetection */ | |
5910 | spec->spec_init_verbs[0].nid = spec->unsol_tag_hp; | |
5911 | spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE; | |
5912 | spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp; | |
5913 | ||
5914 | /* MIC1 jack autodetection */ | |
5915 | spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1; | |
5916 | spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE; | |
5917 | spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1; | |
5918 | ||
5919 | /* config EAPD */ | |
5920 | spec->spec_init_verbs[2].nid = 0x0b; | |
5921 | spec->spec_init_verbs[2].param = 0x78D; | |
5922 | spec->spec_init_verbs[2].verb = 0x00; | |
5923 | ||
5924 | /* Previously commented configuration */ | |
5925 | /* | |
5926 | spec->spec_init_verbs[3].nid = 0x0b; | |
5927 | spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE; | |
5928 | spec->spec_init_verbs[3].verb = 0x02; | |
5929 | ||
5930 | spec->spec_init_verbs[4].nid = 0x10; | |
5931 | spec->spec_init_verbs[4].param = 0x78D; | |
5932 | spec->spec_init_verbs[4].verb = 0x02; | |
5933 | ||
5934 | spec->spec_init_verbs[5].nid = 0x10; | |
5935 | spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE; | |
5936 | spec->spec_init_verbs[5].verb = 0x02; | |
5937 | */ | |
5938 | ||
5939 | /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ | |
5940 | return 0; | |
5941 | } | |
5942 | ||
95c6e9cb IM |
5943 | static int patch_ca0132(struct hda_codec *codec) |
5944 | { | |
5945 | struct ca0132_spec *spec; | |
a73d511c | 5946 | int err; |
d5c016b5 | 5947 | const struct snd_pci_quirk *quirk; |
95c6e9cb | 5948 | |
4e76a883 | 5949 | codec_dbg(codec, "patch_ca0132\n"); |
95c6e9cb IM |
5950 | |
5951 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
5952 | if (!spec) | |
5953 | return -ENOMEM; | |
5954 | codec->spec = spec; | |
993884f6 | 5955 | spec->codec = codec; |
95c6e9cb | 5956 | |
225068ab TI |
5957 | codec->patch_ops = ca0132_patch_ops; |
5958 | codec->pcm_format_first = 1; | |
5959 | codec->no_sticky_stream = 1; | |
5960 | ||
d5c016b5 GM |
5961 | /* Detect codec quirk */ |
5962 | quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); | |
5963 | if (quirk) | |
5964 | spec->quirk = quirk->value; | |
5965 | else | |
5966 | spec->quirk = QUIRK_NONE; | |
5967 | ||
aa31704f CM |
5968 | /* Setup BAR Region 2 for Sound Blaster Z */ |
5969 | if (spec->quirk == QUIRK_SBZ) { | |
5970 | spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); | |
5971 | if (spec->mem_base == NULL) { | |
5972 | codec_warn(codec, "pci_iomap failed!"); | |
5973 | codec_info(codec, "perhaps this is not an SBZ?"); | |
5974 | spec->quirk = QUIRK_NONE; | |
5975 | } | |
5976 | } | |
009b8f97 | 5977 | |
e24aa0a4 | 5978 | spec->dsp_state = DSP_DOWNLOAD_INIT; |
a7e76271 IM |
5979 | spec->num_mixers = 1; |
5980 | spec->mixers[0] = ca0132_mixer; | |
5981 | ||
009b8f97 CM |
5982 | /* Setup whether or not to use alt functions */ |
5983 | switch (spec->quirk) { | |
5984 | case QUIRK_SBZ: | |
5985 | case QUIRK_R3DI: | |
5986 | spec->use_alt_functions = true; | |
5987 | break; | |
5988 | default: | |
5989 | spec->use_alt_functions = false; | |
5990 | break; | |
5991 | } | |
5992 | ||
5aaca44d IM |
5993 | spec->base_init_verbs = ca0132_base_init_verbs; |
5994 | spec->base_exit_verbs = ca0132_base_exit_verbs; | |
5aaca44d | 5995 | |
993884f6 CCC |
5996 | INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); |
5997 | ||
95c6e9cb IM |
5998 | ca0132_init_chip(codec); |
5999 | ||
6000 | ca0132_config(codec); | |
6001 | ||
d5c016b5 GM |
6002 | err = ca0132_prepare_verbs(codec); |
6003 | if (err < 0) | |
cc91ceaf | 6004 | goto error; |
d5c016b5 | 6005 | |
a73d511c IM |
6006 | err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); |
6007 | if (err < 0) | |
cc91ceaf | 6008 | goto error; |
a73d511c | 6009 | |
95c6e9cb | 6010 | return 0; |
cc91ceaf TI |
6011 | |
6012 | error: | |
6013 | ca0132_free(codec); | |
6014 | return err; | |
95c6e9cb IM |
6015 | } |
6016 | ||
6017 | /* | |
6018 | * patch entries | |
6019 | */ | |
b9a94a9c TI |
6020 | static struct hda_device_id snd_hda_id_ca0132[] = { |
6021 | HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), | |
95c6e9cb IM |
6022 | {} /* terminator */ |
6023 | }; | |
b9a94a9c | 6024 | MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); |
95c6e9cb IM |
6025 | |
6026 | MODULE_LICENSE("GPL"); | |
406261ce | 6027 | MODULE_DESCRIPTION("Creative Sound Core3D codec"); |
95c6e9cb | 6028 | |
d8a766a1 | 6029 | static struct hda_codec_driver ca0132_driver = { |
b9a94a9c | 6030 | .id = snd_hda_id_ca0132, |
95c6e9cb IM |
6031 | }; |
6032 | ||
d8a766a1 | 6033 | module_hda_codec_driver(ca0132_driver); |