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ALSA: hda/ca0132: Shuffle to group together related code
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/pci.h>
28#include <linux/mutex.h>
da155d5b 29#include <linux/module.h>
4aa3bb0c 30#include <linux/firmware.h>
95c6e9cb
IM		 31#include <sound/core.h>
32#include "hda_codec.h"
33#include "hda_local.h"
128bc4ba 34#include "hda_auto_parser.h"
5aaca44d 35#include "hda_jack.h"
95c6e9cb 36
bcd109c0
IM		 37#include "ca0132_regs.h"
38
ef6b2ead
IM		 39/* Enable this to see controls for tuning purpose. */
40/*#define ENABLE_TUNING_CONTROLS*/
41
42#define FLOAT_ZERO 0x00000000
43#define FLOAT_ONE 0x3f800000
44#define FLOAT_TWO 0x40000000
45#define FLOAT_MINUS_5 0xc0a00000
46
47#define UNSOL_TAG_HP 0x10
48#define UNSOL_TAG_AMIC1 0x12
49#define UNSOL_TAG_DSP 0x16
50
4aa3bb0c
IM		 51#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
52#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
53
54#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
55#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
56#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
57
58#define MASTERCONTROL 0x80
ef6b2ead
IM		 59#define MASTERCONTROL_ALLOC_DMA_CHAN 10
60#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 61
95c6e9cb
IM		 62#define WIDGET_CHIP_CTRL 0x15
63#define WIDGET_DSP_CTRL 0x16
64
4aa3bb0c
IM		 65#define MEM_CONNID_MICIN1 3
66#define MEM_CONNID_MICIN2 5
67#define MEM_CONNID_MICOUT1 12
68#define MEM_CONNID_MICOUT2 14
69#define MEM_CONNID_WUH 10
70#define MEM_CONNID_DSP 16
71#define MEM_CONNID_DMIC 100
72
73#define SCP_SET 0
74#define SCP_GET 1
75
01ef7dbf
IM		 76#define EFX_FILE "ctefx.bin"
77
78MODULE_FIRMWARE(EFX_FILE);
79
ef6b2ead
IM		 80static char *dirstr[2] = { "Playback", "Capture" };
81
82enum {
83 SPEAKER_OUT,
84 HEADPHONE_OUT
85};
86
87enum {
88 DIGITAL_MIC,
89 LINE_MIC_IN
90};
91
92enum {
93#define VNODE_START_NID 0x80
94 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
95 VNID_MIC,
96 VNID_HP_SEL,
97 VNID_AMIC1_SEL,
98 VNID_HP_ASEL,
99 VNID_AMIC1_ASEL,
100 VNODE_END_NID,
101#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
102
103#define EFFECT_START_NID 0x90
104#define OUT_EFFECT_START_NID EFFECT_START_NID
105 SURROUND = OUT_EFFECT_START_NID,
106 CRYSTALIZER,
107 DIALOG_PLUS,
108 SMART_VOLUME,
109 X_BASS,
110 EQUALIZER,
111 OUT_EFFECT_END_NID,
112#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
113
114#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
115 ECHO_CANCELLATION = IN_EFFECT_START_NID,
116 VOICE_FOCUS,
117 MIC_SVM,
118 NOISE_REDUCTION,
119 IN_EFFECT_END_NID,
120#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
121
122 VOICEFX = IN_EFFECT_END_NID,
123 PLAY_ENHANCEMENT,
124 CRYSTAL_VOICE,
125 EFFECT_END_NID
126#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
127};
128
129/* Effects values size*/
130#define EFFECT_VALS_MAX_COUNT 12
131
132struct ct_effect {
133 char name[44];
134 hda_nid_t nid;
135 int mid; /*effect module ID*/
136 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
137 int direct; /* 0:output; 1:input*/
138 int params; /* number of default non-on/off params */
139 /*effect default values, 1st is on/off. */
140 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
141};
142
143#define EFX_DIR_OUT 0
144#define EFX_DIR_IN 1
145
146static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
147 { .name = "Surround",
148 .nid = SURROUND,
149 .mid = 0x96,
150 .reqs = {0, 1},
151 .direct = EFX_DIR_OUT,
152 .params = 1,
153 .def_vals = {0x3F800000, 0x3F2B851F}
154 },
155 { .name = "Crystalizer",
156 .nid = CRYSTALIZER,
157 .mid = 0x96,
158 .reqs = {7, 8},
159 .direct = EFX_DIR_OUT,
160 .params = 1,
161 .def_vals = {0x3F800000, 0x3F266666}
162 },
163 { .name = "Dialog Plus",
164 .nid = DIALOG_PLUS,
165 .mid = 0x96,
166 .reqs = {2, 3},
167 .direct = EFX_DIR_OUT,
168 .params = 1,
169 .def_vals = {0x00000000, 0x3F000000}
170 },
171 { .name = "Smart Volume",
172 .nid = SMART_VOLUME,
173 .mid = 0x96,
174 .reqs = {4, 5, 6},
175 .direct = EFX_DIR_OUT,
176 .params = 2,
177 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
178 },
179 { .name = "X-Bass",
180 .nid = X_BASS,
181 .mid = 0x96,
182 .reqs = {24, 23, 25},
183 .direct = EFX_DIR_OUT,
184 .params = 2,
185 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
186 },
187 { .name = "Equalizer",
188 .nid = EQUALIZER,
189 .mid = 0x96,
190 .reqs = {9, 10, 11, 12, 13, 14,
191 15, 16, 17, 18, 19, 20},
192 .direct = EFX_DIR_OUT,
193 .params = 11,
194 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
195 0x00000000, 0x00000000, 0x00000000, 0x00000000,
196 0x00000000, 0x00000000, 0x00000000, 0x00000000}
197 },
198 { .name = "Echo Cancellation",
199 .nid = ECHO_CANCELLATION,
200 .mid = 0x95,
201 .reqs = {0, 1, 2, 3},
202 .direct = EFX_DIR_IN,
203 .params = 3,
204 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
205 },
206 { .name = "Voice Focus",
207 .nid = VOICE_FOCUS,
208 .mid = 0x95,
209 .reqs = {6, 7, 8, 9},
210 .direct = EFX_DIR_IN,
211 .params = 3,
212 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
213 },
214 { .name = "Mic SVM",
215 .nid = MIC_SVM,
216 .mid = 0x95,
217 .reqs = {44, 45},
218 .direct = EFX_DIR_IN,
219 .params = 1,
220 .def_vals = {0x00000000, 0x3F3D70A4}
221 },
222 { .name = "Noise Reduction",
223 .nid = NOISE_REDUCTION,
224 .mid = 0x95,
225 .reqs = {4, 5},
226 .direct = EFX_DIR_IN,
227 .params = 1,
228 .def_vals = {0x3F800000, 0x3F000000}
229 },
230 { .name = "VoiceFX",
231 .nid = VOICEFX,
232 .mid = 0x95,
233 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
234 .direct = EFX_DIR_IN,
235 .params = 8,
236 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
237 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
238 0x00000000}
239 }
240};
241
242/* Tuning controls */
243#ifdef ENABLE_TUNING_CONTROLS
244
245enum {
246#define TUNING_CTL_START_NID 0xC0
247 WEDGE_ANGLE = TUNING_CTL_START_NID,
248 SVM_LEVEL,
249 EQUALIZER_BAND_0,
250 EQUALIZER_BAND_1,
251 EQUALIZER_BAND_2,
252 EQUALIZER_BAND_3,
253 EQUALIZER_BAND_4,
254 EQUALIZER_BAND_5,
255 EQUALIZER_BAND_6,
256 EQUALIZER_BAND_7,
257 EQUALIZER_BAND_8,
258 EQUALIZER_BAND_9,
259 TUNING_CTL_END_NID
260#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
261};
262
263struct ct_tuning_ctl {
264 char name[44];
265 hda_nid_t parent_nid;
266 hda_nid_t nid;
267 int mid; /*effect module ID*/
268 int req; /*effect module request*/
269 int direct; /* 0:output; 1:input*/
270 unsigned int def_val;/*effect default values*/
271};
272
273static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
274 { .name = "Wedge Angle",
275 .parent_nid = VOICE_FOCUS,
276 .nid = WEDGE_ANGLE,
277 .mid = 0x95,
278 .req = 8,
279 .direct = EFX_DIR_IN,
280 .def_val = 0x41F00000
281 },
282 { .name = "SVM Level",
283 .parent_nid = MIC_SVM,
284 .nid = SVM_LEVEL,
285 .mid = 0x95,
286 .req = 45,
287 .direct = EFX_DIR_IN,
288 .def_val = 0x3F3D70A4
289 },
290 { .name = "EQ Band0",
291 .parent_nid = EQUALIZER,
292 .nid = EQUALIZER_BAND_0,
293 .mid = 0x96,
294 .req = 11,
295 .direct = EFX_DIR_OUT,
296 .def_val = 0x00000000
297 },
298 { .name = "EQ Band1",
299 .parent_nid = EQUALIZER,
300 .nid = EQUALIZER_BAND_1,
301 .mid = 0x96,
302 .req = 12,
303 .direct = EFX_DIR_OUT,
304 .def_val = 0x00000000
305 },
306 { .name = "EQ Band2",
307 .parent_nid = EQUALIZER,
308 .nid = EQUALIZER_BAND_2,
309 .mid = 0x96,
310 .req = 13,
311 .direct = EFX_DIR_OUT,
312 .def_val = 0x00000000
313 },
314 { .name = "EQ Band3",
315 .parent_nid = EQUALIZER,
316 .nid = EQUALIZER_BAND_3,
317 .mid = 0x96,
318 .req = 14,
319 .direct = EFX_DIR_OUT,
320 .def_val = 0x00000000
321 },
322 { .name = "EQ Band4",
323 .parent_nid = EQUALIZER,
324 .nid = EQUALIZER_BAND_4,
325 .mid = 0x96,
326 .req = 15,
327 .direct = EFX_DIR_OUT,
328 .def_val = 0x00000000
329 },
330 { .name = "EQ Band5",
331 .parent_nid = EQUALIZER,
332 .nid = EQUALIZER_BAND_5,
333 .mid = 0x96,
334 .req = 16,
335 .direct = EFX_DIR_OUT,
336 .def_val = 0x00000000
337 },
338 { .name = "EQ Band6",
339 .parent_nid = EQUALIZER,
340 .nid = EQUALIZER_BAND_6,
341 .mid = 0x96,
342 .req = 17,
343 .direct = EFX_DIR_OUT,
344 .def_val = 0x00000000
345 },
346 { .name = "EQ Band7",
347 .parent_nid = EQUALIZER,
348 .nid = EQUALIZER_BAND_7,
349 .mid = 0x96,
350 .req = 18,
351 .direct = EFX_DIR_OUT,
352 .def_val = 0x00000000
353 },
354 { .name = "EQ Band8",
355 .parent_nid = EQUALIZER,
356 .nid = EQUALIZER_BAND_8,
357 .mid = 0x96,
358 .req = 19,
359 .direct = EFX_DIR_OUT,
360 .def_val = 0x00000000
361 },
362 { .name = "EQ Band9",
363 .parent_nid = EQUALIZER,
364 .nid = EQUALIZER_BAND_9,
365 .mid = 0x96,
366 .req = 20,
367 .direct = EFX_DIR_OUT,
368 .def_val = 0x00000000
369 }
370};
371#endif
372
373/* Voice FX Presets */
374#define VOICEFX_MAX_PARAM_COUNT 9
375
376struct ct_voicefx {
377 char *name;
378 hda_nid_t nid;
379 int mid;
380 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
381};
382
383struct ct_voicefx_preset {
384 char *name; /*preset name*/
385 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
386};
387
388struct ct_voicefx ca0132_voicefx = {
389 .name = "VoiceFX Capture Switch",
390 .nid = VOICEFX,
391 .mid = 0x95,
392 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
393};
394
395struct ct_voicefx_preset ca0132_voicefx_presets[] = {
396 { .name = "Neutral",
397 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
398 0x44FA0000, 0x3F800000, 0x3F800000,
399 0x3F800000, 0x00000000, 0x00000000 }
400 },
401 { .name = "Female2Male",
402 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
403 0x44FA0000, 0x3F19999A, 0x3F866666,
404 0x3F800000, 0x00000000, 0x00000000 }
405 },
406 { .name = "Male2Female",
407 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
408 0x450AC000, 0x4017AE14, 0x3F6B851F,
409 0x3F800000, 0x00000000, 0x00000000 }
410 },
411 { .name = "ScrappyKid",
412 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
413 0x44FA0000, 0x40400000, 0x3F28F5C3,
414 0x3F800000, 0x00000000, 0x00000000 }
415 },
416 { .name = "Elderly",
417 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
418 0x44E10000, 0x3FB33333, 0x3FB9999A,
419 0x3F800000, 0x3E3A2E43, 0x00000000 }
420 },
421 { .name = "Orc",
422 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
423 0x45098000, 0x3F266666, 0x3FC00000,
424 0x3F800000, 0x00000000, 0x00000000 }
425 },
426 { .name = "Elf",
427 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
428 0x45193000, 0x3F8E147B, 0x3F75C28F,
429 0x3F800000, 0x00000000, 0x00000000 }
430 },
431 { .name = "Dwarf",
432 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
433 0x45007000, 0x3F451EB8, 0x3F7851EC,
434 0x3F800000, 0x00000000, 0x00000000 }
435 },
436 { .name = "AlienBrute",
437 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
438 0x451F6000, 0x3F266666, 0x3FA7D945,
439 0x3F800000, 0x3CF5C28F, 0x00000000 }
440 },
441 { .name = "Robot",
442 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
443 0x44FA0000, 0x3FB2718B, 0x3F800000,
444 0xBC07010E, 0x00000000, 0x00000000 }
445 },
446 { .name = "Marine",
447 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
448 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
449 0x3F0A3D71, 0x00000000, 0x00000000 }
450 },
451 { .name = "Emo",
452 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
453 0x44FA0000, 0x3F800000, 0x3F800000,
454 0x3E4CCCCD, 0x00000000, 0x00000000 }
455 },
456 { .name = "DeepVoice",
457 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
458 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
459 0x3F800000, 0x00000000, 0x00000000 }
460 },
461 { .name = "Munchkin",
462 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
463 0x44FA0000, 0x3F800000, 0x3F1A043C,
464 0x3F800000, 0x00000000, 0x00000000 }
465 }
466};
467
95c6e9cb
IM		 468enum hda_cmd_vendor_io {
469 /* for DspIO node */
470 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
471 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
472
473 VENDOR_DSPIO_STATUS = 0xF01,
474 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
475 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
476 VENDOR_DSPIO_DSP_INIT = 0x703,
477 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
478 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
479
480 /* for ChipIO node */
481 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
482 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
483 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
484 VENDOR_CHIPIO_DATA_LOW = 0x300,
485 VENDOR_CHIPIO_DATA_HIGH = 0x400,
486
487 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
488 VENDOR_CHIPIO_STATUS = 0xF01,
489 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
490 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
491
4aa3bb0c
IM		 492 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
493 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
494
95c6e9cb 495 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 496 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 497
498 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
499 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
500 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
501 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
502 VENDOR_CHIPIO_FLAG_SET = 0x70F,
503 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 504 VENDOR_CHIPIO_PARAM_SET = 0x710,
505 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 506
507 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
508 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
509 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
510 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
511
4aa3bb0c
IM		 512 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
513 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
514 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
515 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
516
517 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
518 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
519 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
520 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
521 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
522 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
523
524 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 525};
526
527/*
528 * Control flag IDs
529 */
530enum control_flag_id {
531 /* Connection manager stream setup is bypassed/enabled */
532 CONTROL_FLAG_C_MGR = 0,
533 /* DSP DMA is bypassed/enabled */
534 CONTROL_FLAG_DMA = 1,
535 /* 8051 'idle' mode is disabled/enabled */
536 CONTROL_FLAG_IDLE_ENABLE = 2,
537 /* Tracker for the SPDIF-in path is bypassed/enabled */
538 CONTROL_FLAG_TRACKER = 3,
539 /* DigitalOut to Spdif2Out connection is disabled/enabled */
540 CONTROL_FLAG_SPDIF2OUT = 4,
541 /* Digital Microphone is disabled/enabled */
542 CONTROL_FLAG_DMIC = 5,
543 /* ADC_B rate is 48 kHz/96 kHz */
544 CONTROL_FLAG_ADC_B_96KHZ = 6,
545 /* ADC_C rate is 48 kHz/96 kHz */
546 CONTROL_FLAG_ADC_C_96KHZ = 7,
547 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
548 CONTROL_FLAG_DAC_96KHZ = 8,
549 /* DSP rate is 48 kHz/96 kHz */
550 CONTROL_FLAG_DSP_96KHZ = 9,
551 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
552 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
553 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
554 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
555 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
556 CONTROL_FLAG_DECODE_LOOP = 12,
557 /* De-emphasis filter on DAC-1 disabled/enabled */
558 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
559 /* De-emphasis filter on DAC-2 disabled/enabled */
560 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
561 /* De-emphasis filter on DAC-3 disabled/enabled */
562 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
563 /* High-pass filter on ADC_B disabled/enabled */
564 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
565 /* High-pass filter on ADC_C disabled/enabled */
566 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
567 /* Common mode on Port_A disabled/enabled */
568 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
569 /* Common mode on Port_D disabled/enabled */
570 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
571 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
572 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
573 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 574 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 575 /* ASI rate is 48kHz/96kHz */
576 CONTROL_FLAG_ASI_96KHZ = 22,
577 /* DAC power settings able to control attached ports no/yes */
578 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
579 /* Clock Stop OK reporting is disabled/enabled */
580 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
581 /* Number of control flags */
582 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
583};
584
585/*
586 * Control parameter IDs
587 */
4aa3bb0c 588enum control_param_id {
ef6b2ead
IM		 589 /* 0: None, 1: Mic1In*/
590 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 591 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
592 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 593 /* Port A output stage gain setting to use when 16 Ohm output
594 * impedance is selected*/
595 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
596 /* Port D output stage gain setting to use when 16 Ohm output
597 * impedance is selected*/
598 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 599
600 /* Stream Control */
601
602 /* Select stream with the given ID */
603 CONTROL_PARAM_STREAM_ID = 24,
604 /* Source connection point for the selected stream */
605 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
606 /* Destination connection point for the selected stream */
607 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
608 /* Number of audio channels in the selected stream */
609 CONTROL_PARAM_STREAMS_CHANNELS = 27,
610 /*Enable control for the selected stream */
611 CONTROL_PARAM_STREAM_CONTROL = 28,
612
613 /* Connection Point Control */
614
615 /* Select connection point with the given ID */
616 CONTROL_PARAM_CONN_POINT_ID = 29,
617 /* Connection point sample rate */
618 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
619
620 /* Node Control */
621
622 /* Select HDA node with the given ID */
623 CONTROL_PARAM_NODE_ID = 31
624};
625
626/*
627 * Dsp Io Status codes
628 */
629enum hda_vendor_status_dspio {
630 /* Success */
631 VENDOR_STATUS_DSPIO_OK = 0x00,
632 /* Busy, unable to accept new command, the host must retry */
633 VENDOR_STATUS_DSPIO_BUSY = 0x01,
634 /* SCP command queue is full */
635 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
636 /* SCP response queue is empty */
637 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
638};
639
640/*
641 * Chip Io Status codes
642 */
643enum hda_vendor_status_chipio {
644 /* Success */
645 VENDOR_STATUS_CHIPIO_OK = 0x00,
646 /* Busy, unable to accept new command, the host must retry */
647 VENDOR_STATUS_CHIPIO_BUSY = 0x01
648};
649
650/*
651 * CA0132 sample rate
652 */
653enum ca0132_sample_rate {
654 SR_6_000 = 0x00,
655 SR_8_000 = 0x01,
656 SR_9_600 = 0x02,
657 SR_11_025 = 0x03,
658 SR_16_000 = 0x04,
659 SR_22_050 = 0x05,
660 SR_24_000 = 0x06,
661 SR_32_000 = 0x07,
662 SR_44_100 = 0x08,
663 SR_48_000 = 0x09,
664 SR_88_200 = 0x0A,
665 SR_96_000 = 0x0B,
666 SR_144_000 = 0x0C,
667 SR_176_400 = 0x0D,
668 SR_192_000 = 0x0E,
669 SR_384_000 = 0x0F,
670
671 SR_COUNT = 0x10,
672
673 SR_RATE_UNKNOWN = 0x1F
674};
675
01ef7dbf
IM		 676enum dsp_download_state {
677 DSP_DOWNLOAD_FAILED = -1,
678 DSP_DOWNLOAD_INIT = 0,
679 DSP_DOWNLOADING = 1,
680 DSP_DOWNLOADED = 2
681};
682
01ef7dbf
IM		 683/* retrieve parameters from hda format */
684#define get_hdafmt_chs(fmt) (fmt & 0xf)
685#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
686#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
687#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
688
689/*
690 * CA0132 specific
691 */
692
693struct ca0132_spec {
a7e76271
IM		 694 struct snd_kcontrol_new *mixers[5];
695 unsigned int num_mixers;
5aaca44d
IM		 696 const struct hda_verb *base_init_verbs;
697 const struct hda_verb *base_exit_verbs;
698 const struct hda_verb *init_verbs[5];
699 unsigned int num_init_verbs; /* exclude base init verbs */
01ef7dbf 700 struct auto_pin_cfg autocfg;
5aaca44d
IM		 701
702 /* Nodes configurations */
01ef7dbf
IM		 703 struct hda_multi_out multiout;
704 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
705 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 706 unsigned int num_outputs;
01ef7dbf
IM		 707 hda_nid_t input_pins[AUTO_PIN_LAST];
708 hda_nid_t adcs[AUTO_PIN_LAST];
709 hda_nid_t dig_out;
710 hda_nid_t dig_in;
711 unsigned int num_inputs;
a7e76271
IM		 712 hda_nid_t shared_mic_nid;
713 hda_nid_t shared_out_nid;
5aaca44d 714 struct hda_pcm pcm_rec[5]; /* PCM information */
01ef7dbf
IM		 715
716 /* chip access */
717 struct mutex chipio_mutex; /* chip access mutex */
718 u32 curr_chip_addx;
719
720 /* DSP download related */
721 enum dsp_download_state dsp_state;
722 unsigned int dsp_stream_id;
723 unsigned int wait_scp;
724 unsigned int wait_scp_header;
725 unsigned int wait_num_data;
726 unsigned int scp_resp_header;
727 unsigned int scp_resp_data[4];
728 unsigned int scp_resp_count;
5aaca44d
IM		 729
730 /* mixer and effects related */
731 unsigned char dmic_ctl;
732 int cur_out_type;
733 int cur_mic_type;
734 long vnode_lvol[VNODES_COUNT];
735 long vnode_rvol[VNODES_COUNT];
736 long vnode_lswitch[VNODES_COUNT];
737 long vnode_rswitch[VNODES_COUNT];
738 long effects_switch[EFFECTS_COUNT];
739 long voicefx_val;
740 long cur_mic_boost;
44f0c978
IM		 741
742#ifdef ENABLE_TUNING_CONTROLS
743 long cur_ctl_vals[TUNING_CTLS_COUNT];
744#endif
01ef7dbf
IM		 745};
746
747/*
748 * CA0132 codec access
749 */
750unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
751 unsigned int verb, unsigned int parm, unsigned int *res)
752{
753 unsigned int response;
754 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
755 *res = response;
756
757 return ((response == -1) ? -1 : 0);
758}
759
760static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
761 unsigned short converter_format, unsigned int *res)
762{
763 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
764 converter_format & 0xffff, res);
765}
766
767static int codec_set_converter_stream_channel(struct hda_codec *codec,
768 hda_nid_t nid, unsigned char stream,
769 unsigned char channel, unsigned int *res)
770{
771 unsigned char converter_stream_channel = 0;
772
773 converter_stream_channel = (stream << 4) | (channel & 0x0f);
774 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
775 converter_stream_channel, res);
776}
777
778/* Chip access helper function */
779static int chipio_send(struct hda_codec *codec,
780 unsigned int reg,
781 unsigned int data)
782{
783 unsigned int res;
784 int retry = 50;
785
786 /* send bits of data specified by reg */
787 do {
788 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
789 reg, data);
790 if (res == VENDOR_STATUS_CHIPIO_OK)
791 return 0;
792 } while (--retry);
793 return -EIO;
794}
795
796/*
797 * Write chip address through the vendor widget -- NOT protected by the Mutex!
798 */
799static int chipio_write_address(struct hda_codec *codec,
800 unsigned int chip_addx)
801{
4861af80 802 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 803 int res;
804
4861af80
IM		 805 if (spec->curr_chip_addx == chip_addx)
806 return 0;
807
01ef7dbf
IM		 808 /* send low 16 bits of the address */
809 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
810 chip_addx & 0xffff);
811
812 if (res != -EIO) {
813 /* send high 16 bits of the address */
814 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
815 chip_addx >> 16);
816 }
817
4861af80 818 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
01ef7dbf 819
4861af80 820 return res;
01ef7dbf
IM		 821}
822
823/*
824 * Write data through the vendor widget -- NOT protected by the Mutex!
825 */
01ef7dbf
IM		 826static int chipio_write_data(struct hda_codec *codec, unsigned int data)
827{
5aaca44d 828 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 829 int res;
830
831 /* send low 16 bits of the data */
832 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
833
834 if (res != -EIO) {
835 /* send high 16 bits of the data */
836 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
837 data >> 16);
838 }
839
5aaca44d
IM		 840 /*If no error encountered, automatically increment the address
841 as per chip behaviour*/
842 spec->curr_chip_addx = (res != -EIO) ?
843 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 844 return res;
845}
846
d5c21b88
IM		 847/*
848 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
849 */
01ef7dbf
IM		 850static int chipio_write_data_multiple(struct hda_codec *codec,
851 const u32 *data,
852 unsigned int count)
853{
854 int status = 0;
855
856 if (data == NULL) {
857 snd_printdd(KERN_ERR "chipio_write_data null ptr");
858 return -EINVAL;
859 }
860
861 while ((count-- != 0) && (status == 0))
862 status = chipio_write_data(codec, *data++);
863
864 return status;
865}
866
867
868/*
869 * Read data through the vendor widget -- NOT protected by the Mutex!
870 */
871static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
872{
5aaca44d 873 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 874 int res;
875
876 /* post read */
877 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
878
879 if (res != -EIO) {
880 /* read status */
881 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
882 }
883
884 if (res != -EIO) {
885 /* read data */
886 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
887 VENDOR_CHIPIO_HIC_READ_DATA,
888 0);
889 }
890
5aaca44d
IM		 891 /*If no error encountered, automatically increment the address
892 as per chip behaviour*/
893 spec->curr_chip_addx = (res != -EIO) ?
894 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 895 return res;
896}
897
898/*
899 * Write given value to the given address through the chip I/O widget.
900 * protected by the Mutex
901 */
902static int chipio_write(struct hda_codec *codec,
903 unsigned int chip_addx, const unsigned int data)
904{
905 struct ca0132_spec *spec = codec->spec;
906 int err;
907
908 mutex_lock(&spec->chipio_mutex);
909
910 /* write the address, and if successful proceed to write data */
911 err = chipio_write_address(codec, chip_addx);
912 if (err < 0)
913 goto exit;
914
915 err = chipio_write_data(codec, data);
916 if (err < 0)
917 goto exit;
918
919exit:
920 mutex_unlock(&spec->chipio_mutex);
921 return err;
922}
923
d5c21b88
IM		 924/*
925 * Write multiple values to the given address through the chip I/O widget.
926 * protected by the Mutex
927 */
01ef7dbf
IM		 928static int chipio_write_multiple(struct hda_codec *codec,
929 u32 chip_addx,
930 const u32 *data,
931 unsigned int count)
932{
933 struct ca0132_spec *spec = codec->spec;
934 int status;
935
936 mutex_lock(&spec->chipio_mutex);
4861af80 937 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 938 if (status < 0)
939 goto error;
940
941 status = chipio_write_data_multiple(codec, data, count);
942error:
943 mutex_unlock(&spec->chipio_mutex);
944
945 return status;
946}
947
948/*
949 * Read the given address through the chip I/O widget
950 * protected by the Mutex
951 */
952static int chipio_read(struct hda_codec *codec,
953 unsigned int chip_addx, unsigned int *data)
954{
955 struct ca0132_spec *spec = codec->spec;
956 int err;
957
958 mutex_lock(&spec->chipio_mutex);
959
960 /* write the address, and if successful proceed to write data */
961 err = chipio_write_address(codec, chip_addx);
962 if (err < 0)
963 goto exit;
964
965 err = chipio_read_data(codec, data);
966 if (err < 0)
967 goto exit;
968
969exit:
970 mutex_unlock(&spec->chipio_mutex);
971 return err;
972}
973
d5c21b88
IM		 974/*
975 * Set chip control flags through the chip I/O widget.
976 */
01ef7dbf
IM		 977static void chipio_set_control_flag(struct hda_codec *codec,
978 enum control_flag_id flag_id,
979 bool flag_state)
980{
981 unsigned int val;
982 unsigned int flag_bit;
983
984 flag_bit = (flag_state ? 1 : 0);
985 val = (flag_bit << 7) | (flag_id);
986 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
987 VENDOR_CHIPIO_FLAG_SET, val);
988}
989
d5c21b88
IM		 990/*
991 * Set chip parameters through the chip I/O widget.
992 */
01ef7dbf
IM		 993static void chipio_set_control_param(struct hda_codec *codec,
994 enum control_param_id param_id, int param_val)
995{
996 struct ca0132_spec *spec = codec->spec;
997 int val;
998
999 if ((param_id < 32) && (param_val < 8)) {
1000 val = (param_val << 5) | (param_id);
1001 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1002 VENDOR_CHIPIO_PARAM_SET, val);
1003 } else {
1004 mutex_lock(&spec->chipio_mutex);
1005 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1006 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1007 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1008 param_id);
1009 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1010 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1011 param_val);
1012 }
1013 mutex_unlock(&spec->chipio_mutex);
1014 }
1015}
1016
d5c21b88
IM		 1017/*
1018 * Set sampling rate of the connection point.
1019 */
01ef7dbf
IM		 1020static void chipio_set_conn_rate(struct hda_codec *codec,
1021 int connid, enum ca0132_sample_rate rate)
1022{
1023 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1024 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1025 rate);
1026}
1027
d5c21b88
IM		 1028/*
1029 * Enable clocks.
1030 */
01ef7dbf
IM		 1031static void chipio_enable_clocks(struct hda_codec *codec)
1032{
1033 struct ca0132_spec *spec = codec->spec;
1034
1035 mutex_lock(&spec->chipio_mutex);
1036 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1037 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1039 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1041 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1043 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1044 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1045 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1046 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1047 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1048 mutex_unlock(&spec->chipio_mutex);
1049}
1050
1051/*
1052 * CA0132 DSP IO stuffs
1053 */
1054static int dspio_send(struct hda_codec *codec, unsigned int reg,
1055 unsigned int data)
1056{
1057 unsigned int res;
1058 int retry = 50;
1059
1060 /* send bits of data specified by reg to dsp */
1061 do {
1062 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1063 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1064 return res;
1065 } while (--retry);
1066
1067 return -EIO;
1068}
1069
d5c21b88
IM		 1070/*
1071 * Wait for DSP to be ready for commands
1072 */
01ef7dbf
IM		 1073static void dspio_write_wait(struct hda_codec *codec)
1074{
4861af80
IM		 1075 int status;
1076 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1077
01ef7dbf 1078 do {
4861af80
IM		 1079 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1080 VENDOR_DSPIO_STATUS, 0);
1081 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1082 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1083 break;
1084 msleep(1);
1085 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1086}
1087
d5c21b88
IM		 1088/*
1089 * Write SCP data to DSP
1090 */
01ef7dbf
IM		 1091static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1092{
1093 struct ca0132_spec *spec = codec->spec;
1094 int status;
1095
1096 dspio_write_wait(codec);
1097
1098 mutex_lock(&spec->chipio_mutex);
1099 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1100 scp_data & 0xffff);
1101 if (status < 0)
1102 goto error;
1103
1104 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1105 scp_data >> 16);
1106 if (status < 0)
1107 goto error;
1108
1109 /* OK, now check if the write itself has executed*/
1110 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1111 VENDOR_DSPIO_STATUS, 0);
1112error:
1113 mutex_unlock(&spec->chipio_mutex);
1114
1115 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1116 -EIO : 0;
1117}
1118
d5c21b88
IM		 1119/*
1120 * Write multiple SCP data to DSP
1121 */
01ef7dbf
IM		 1122static int dspio_write_multiple(struct hda_codec *codec,
1123 unsigned int *buffer, unsigned int size)
1124{
1125 int status = 0;
1126 unsigned int count;
1127
1128 if ((buffer == NULL))
1129 return -EINVAL;
1130
1131 count = 0;
1132 while (count < size) {
1133 status = dspio_write(codec, *buffer++);
1134 if (status != 0)
1135 break;
1136 count++;
1137 }
1138
1139 return status;
1140}
1141
a73d511c
IM		 1142static int dspio_read(struct hda_codec *codec, unsigned int *data)
1143{
1144 int status;
1145
1146 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1147 if (status == -EIO)
1148 return status;
1149
1150 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1151 if (status == -EIO ||
1152 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1153 return -EIO;
1154
1155 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1156 VENDOR_DSPIO_SCP_READ_DATA, 0);
1157
1158 return 0;
1159}
1160
1161static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1162 unsigned int *buf_size, unsigned int size_count)
1163{
1164 int status = 0;
1165 unsigned int size = *buf_size;
1166 unsigned int count;
1167 unsigned int skip_count;
1168 unsigned int dummy;
1169
1170 if ((buffer == NULL))
1171 return -1;
1172
1173 count = 0;
1174 while (count < size && count < size_count) {
1175 status = dspio_read(codec, buffer++);
1176 if (status != 0)
1177 break;
1178 count++;
1179 }
1180
1181 skip_count = count;
1182 if (status == 0) {
1183 while (skip_count < size) {
1184 status = dspio_read(codec, &dummy);
1185 if (status != 0)
1186 break;
1187 skip_count++;
1188 }
1189 }
1190 *buf_size = count;
1191
1192 return status;
1193}
1194
d5c21b88
IM		 1195/*
1196 * Construct the SCP header using corresponding fields
1197 */
01ef7dbf
IM		 1198static inline unsigned int
1199make_scp_header(unsigned int target_id, unsigned int source_id,
1200 unsigned int get_flag, unsigned int req,
1201 unsigned int device_flag, unsigned int resp_flag,
1202 unsigned int error_flag, unsigned int data_size)
1203{
1204 unsigned int header = 0;
1205
1206 header = (data_size & 0x1f) << 27;
1207 header |= (error_flag & 0x01) << 26;
1208 header |= (resp_flag & 0x01) << 25;
1209 header |= (device_flag & 0x01) << 24;
1210 header |= (req & 0x7f) << 17;
1211 header |= (get_flag & 0x01) << 16;
1212 header |= (source_id & 0xff) << 8;
1213 header |= target_id & 0xff;
1214
1215 return header;
1216}
1217
d5c21b88
IM		 1218/*
1219 * Extract corresponding fields from SCP header
1220 */
01ef7dbf
IM		 1221static inline void
1222extract_scp_header(unsigned int header,
1223 unsigned int *target_id, unsigned int *source_id,
1224 unsigned int *get_flag, unsigned int *req,
1225 unsigned int *device_flag, unsigned int *resp_flag,
1226 unsigned int *error_flag, unsigned int *data_size)
1227{
1228 if (data_size)
1229 *data_size = (header >> 27) & 0x1f;
1230 if (error_flag)
1231 *error_flag = (header >> 26) & 0x01;
1232 if (resp_flag)
1233 *resp_flag = (header >> 25) & 0x01;
1234 if (device_flag)
1235 *device_flag = (header >> 24) & 0x01;
1236 if (req)
1237 *req = (header >> 17) & 0x7f;
1238 if (get_flag)
1239 *get_flag = (header >> 16) & 0x01;
1240 if (source_id)
1241 *source_id = (header >> 8) & 0xff;
1242 if (target_id)
1243 *target_id = header & 0xff;
1244}
1245
1246#define SCP_MAX_DATA_WORDS (16)
1247
1248/* Structure to contain any SCP message */
1249struct scp_msg {
1250 unsigned int hdr;
1251 unsigned int data[SCP_MAX_DATA_WORDS];
1252};
1253
a73d511c
IM		 1254static void dspio_clear_response_queue(struct hda_codec *codec)
1255{
1256 unsigned int dummy = 0;
1257 int status = -1;
1258
1259 /* clear all from the response queue */
1260 do {
1261 status = dspio_read(codec, &dummy);
1262 } while (status == 0);
1263}
1264
1265static int dspio_get_response_data(struct hda_codec *codec)
1266{
1267 struct ca0132_spec *spec = codec->spec;
1268 unsigned int data = 0;
1269 unsigned int count;
1270
1271 if (dspio_read(codec, &data) < 0)
1272 return -EIO;
1273
1274 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1275 spec->scp_resp_header = data;
1276 spec->scp_resp_count = data >> 27;
1277 count = spec->wait_num_data;
1278 dspio_read_multiple(codec, spec->scp_resp_data,
1279 &spec->scp_resp_count, count);
1280 return 0;
1281 }
1282
1283 return -EIO;
1284}
1285
d5c21b88
IM		 1286/*
1287 * Send SCP message to DSP
1288 */
01ef7dbf
IM		 1289static int dspio_send_scp_message(struct hda_codec *codec,
1290 unsigned char *send_buf,
1291 unsigned int send_buf_size,
1292 unsigned char *return_buf,
1293 unsigned int return_buf_size,
1294 unsigned int *bytes_returned)
1295{
1296 struct ca0132_spec *spec = codec->spec;
1297 int retry;
1298 int status = -1;
1299 unsigned int scp_send_size = 0;
1300 unsigned int total_size;
1301 bool waiting_for_resp = false;
1302 unsigned int header;
1303 struct scp_msg *ret_msg;
1304 unsigned int resp_src_id, resp_target_id;
1305 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1306
1307 if (bytes_returned)
1308 *bytes_returned = 0;
1309
1310 /* get scp header from buffer */
1311 header = *((unsigned int *)send_buf);
1312 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1313 &device_flag, NULL, NULL, &data_size);
1314 scp_send_size = data_size + 1;
1315 total_size = (scp_send_size * 4);
1316
1317 if (send_buf_size < total_size)
1318 return -EINVAL;
1319
1320 if (get_flag || device_flag) {
1321 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1322 return -EINVAL;
1323
1324 spec->wait_scp_header = *((unsigned int *)send_buf);
1325
1326 /* swap source id with target id */
1327 resp_target_id = src_id;
1328 resp_src_id = target_id;
1329 spec->wait_scp_header &= 0xffff0000;
1330 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1331 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1332 spec->wait_scp = 1;
1333 waiting_for_resp = true;
1334 }
1335
1336 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1337 scp_send_size);
1338 if (status < 0) {
1339 spec->wait_scp = 0;
1340 return status;
1341 }
1342
1343 if (waiting_for_resp) {
1344 memset(return_buf, 0, return_buf_size);
1345 retry = 50;
1346 do {
1347 msleep(20);
1348 } while (spec->wait_scp && (--retry != 0));
1349 waiting_for_resp = false;
1350 if (retry != 0) {
1351 ret_msg = (struct scp_msg *)return_buf;
1352 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1353 memcpy(&ret_msg->data, spec->scp_resp_data,
1354 spec->wait_num_data);
1355 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1356 status = 0;
1357 } else {
1358 status = -EIO;
1359 }
1360 spec->wait_scp = 0;
1361 }
1362
1363 return status;
1364}
1365
d5c21b88
IM		 1366/**
1367 * Prepare and send the SCP message to DSP
1368 * @codec: the HDA codec
1369 * @mod_id: ID of the DSP module to send the command
1370 * @req: ID of request to send to the DSP module
1371 * @dir: SET or GET
1372 * @data: pointer to the data to send with the request, request specific
1373 * @len: length of the data, in bytes
1374 * @reply: point to the buffer to hold data returned for a reply
1375 * @reply_len: length of the reply buffer returned from GET
1376 *
1377 * Returns zero or a negative error code.
1378 */
01ef7dbf
IM		 1379static int dspio_scp(struct hda_codec *codec,
1380 int mod_id, int req, int dir, void *data, unsigned int len,
1381 void *reply, unsigned int *reply_len)
1382{
1383 int status = 0;
1384 struct scp_msg scp_send, scp_reply;
1385 unsigned int ret_bytes, send_size, ret_size;
1386 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1387 unsigned int reply_data_size;
1388
1389 memset(&scp_send, 0, sizeof(scp_send));
1390 memset(&scp_reply, 0, sizeof(scp_reply));
1391
1392 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1393 return -EINVAL;
1394
1395 if (dir == SCP_GET && reply == NULL) {
1396 snd_printdd(KERN_ERR "dspio_scp get but has no buffer");
1397 return -EINVAL;
1398 }
1399
1400 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1401 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms");
1402 return -EINVAL;
1403 }
1404
1405 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1406 0, 0, 0, len/sizeof(unsigned int));
1407 if (data != NULL && len > 0) {
1408 len = min((unsigned int)(sizeof(scp_send.data)), len);
1409 memcpy(scp_send.data, data, len);
1410 }
1411
1412 ret_bytes = 0;
1413 send_size = sizeof(unsigned int) + len;
1414 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1415 send_size, (unsigned char *)&scp_reply,
1416 sizeof(scp_reply), &ret_bytes);
1417
1418 if (status < 0) {
1419 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed");
1420 return status;
1421 }
1422
1423 /* extract send and reply headers members */
1424 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1425 NULL, NULL, NULL, NULL, NULL);
1426 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1427 &reply_resp_flag, &reply_error_flag,
1428 &reply_data_size);
1429
1430 if (!send_get_flag)
1431 return 0;
1432
1433 if (reply_resp_flag && !reply_error_flag) {
1434 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1435 / sizeof(unsigned int);
1436
1437 if (*reply_len < ret_size*sizeof(unsigned int)) {
1438 snd_printdd(KERN_ERR "reply too long for buf");
1439 return -EINVAL;
1440 } else if (ret_size != reply_data_size) {
1441 snd_printdd(KERN_ERR "RetLen and HdrLen .NE.");
1442 return -EINVAL;
1443 } else {
1444 *reply_len = ret_size*sizeof(unsigned int);
1445 memcpy(reply, scp_reply.data, *reply_len);
1446 }
1447 } else {
1448 snd_printdd(KERN_ERR "reply ill-formed or errflag set");
1449 return -EIO;
1450 }
1451
1452 return status;
1453}
1454
5aaca44d
IM		 1455/*
1456 * Set DSP parameters
1457 */
1458static int dspio_set_param(struct hda_codec *codec, int mod_id,
1459 int req, void *data, unsigned int len)
1460{
1461 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1462}
1463
1464static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1465 int req, unsigned int data)
1466{
1467 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1468}
1469
d5c21b88
IM		 1470/*
1471 * Allocate a DSP DMA channel via an SCP message
1472 */
01ef7dbf
IM		 1473static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1474{
1475 int status = 0;
1476 unsigned int size = sizeof(dma_chan);
1477
1478 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin");
1479 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1480 SCP_GET, NULL, 0, dma_chan, &size);
1481
1482 if (status < 0) {
1483 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed");
1484 return status;
1485 }
1486
1487 if ((*dma_chan + 1) == 0) {
1488 snd_printdd(KERN_INFO "no free dma channels to allocate");
1489 return -EBUSY;
1490 }
1491
1492 snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1493 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete");
1494
1495 return status;
1496}
1497
d5c21b88
IM		 1498/*
1499 * Free a DSP DMA via an SCP message
1500 */
01ef7dbf
IM		 1501static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1502{
1503 int status = 0;
1504 unsigned int dummy = 0;
1505
1506 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin");
1507 snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan);
1508
1509 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1510 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1511
1512 if (status < 0) {
1513 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed");
1514 return status;
1515 }
1516
1517 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete");
1518
1519 return status;
1520}
1521
1522/*
d5c21b88 1523 * (Re)start the DSP
01ef7dbf
IM		 1524 */
1525static int dsp_set_run_state(struct hda_codec *codec)
1526{
1527 unsigned int dbg_ctrl_reg;
1528 unsigned int halt_state;
1529 int err;
1530
1531 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1532 if (err < 0)
1533 return err;
1534
1535 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1536 DSP_DBGCNTL_STATE_LOBIT;
1537
1538 if (halt_state != 0) {
1539 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1540 DSP_DBGCNTL_SS_MASK);
1541 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1542 dbg_ctrl_reg);
1543 if (err < 0)
1544 return err;
1545
1546 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1547 DSP_DBGCNTL_EXEC_MASK;
1548 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1549 dbg_ctrl_reg);
1550 if (err < 0)
1551 return err;
1552 }
1553
1554 return 0;
1555}
1556
d5c21b88
IM		 1557/*
1558 * Reset the DSP
1559 */
01ef7dbf
IM		 1560static int dsp_reset(struct hda_codec *codec)
1561{
1562 unsigned int res;
1563 int retry = 20;
1564
1565 snd_printdd("dsp_reset\n");
1566 do {
1567 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1568 retry--;
1569 } while (res == -EIO && retry);
1570
1571 if (!retry) {
1572 snd_printdd("dsp_reset timeout\n");
1573 return -EIO;
1574 }
1575
1576 return 0;
1577}
1578
d5c21b88
IM		 1579/*
1580 * Convert chip address to DSP address
1581 */
01ef7dbf
IM		 1582static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1583 bool *code, bool *yram)
1584{
1585 *code = *yram = false;
1586
1587 if (UC_RANGE(chip_addx, 1)) {
1588 *code = true;
1589 return UC_OFF(chip_addx);
1590 } else if (X_RANGE_ALL(chip_addx, 1)) {
1591 return X_OFF(chip_addx);
1592 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1593 *yram = true;
1594 return Y_OFF(chip_addx);
1595 }
1596
1597 return (unsigned int)INVALID_CHIP_ADDRESS;
1598}
1599
d5c21b88
IM		 1600/*
1601 * Check if the DSP DMA is active
1602 */
01ef7dbf
IM		 1603static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1604{
1605 unsigned int dma_chnlstart_reg;
1606
1607 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1608
1609 return ((dma_chnlstart_reg & (1 <<
1610 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1611}
1612
1613static int dsp_dma_setup_common(struct hda_codec *codec,
1614 unsigned int chip_addx,
1615 unsigned int dma_chan,
1616 unsigned int port_map_mask,
1617 bool ovly)
1618{
1619 int status = 0;
1620 unsigned int chnl_prop;
1621 unsigned int dsp_addx;
1622 unsigned int active;
1623 bool code, yram;
1624
1625 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------");
1626
1627 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1628 snd_printdd(KERN_ERR "dma chan num invalid");
1629 return -EINVAL;
1630 }
1631
1632 if (dsp_is_dma_active(codec, dma_chan)) {
1633 snd_printdd(KERN_ERR "dma already active");
1634 return -EBUSY;
1635 }
1636
1637 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1638
1639 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1640 snd_printdd(KERN_ERR "invalid chip addr");
1641 return -ENXIO;
1642 }
1643
1644 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1645 active = 0;
1646
1647 snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm");
1648
1649 if (ovly) {
1650 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1651 &chnl_prop);
1652
1653 if (status < 0) {
1654 snd_printdd(KERN_ERR "read CHNLPROP Reg fail");
1655 return status;
1656 }
1657 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP");
1658 }
1659
1660 if (!code)
1661 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1662 else
1663 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1664
1665 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1666
1667 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1668 if (status < 0) {
1669 snd_printdd(KERN_ERR "write CHNLPROP Reg fail");
1670 return status;
1671 }
1672 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP");
1673
1674 if (ovly) {
1675 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1676 &active);
1677
1678 if (status < 0) {
1679 snd_printdd(KERN_ERR "read ACTIVE Reg fail");
1680 return status;
1681 }
1682 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE");
1683 }
1684
1685 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1686 DSPDMAC_ACTIVE_AAR_MASK;
1687
1688 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1689 if (status < 0) {
1690 snd_printdd(KERN_ERR "write ACTIVE Reg fail");
1691 return status;
1692 }
1693
1694 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE");
1695
1696 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1697 port_map_mask);
1698 if (status < 0) {
1699 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail");
1700 return status;
1701 }
1702 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL");
1703
1704 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1705 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1706 if (status < 0) {
1707 snd_printdd(KERN_ERR "write IRQCNT Reg fail");
1708 return status;
1709 }
1710 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT");
1711
1712 snd_printdd(
1713 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1714 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1715 chip_addx, dsp_addx, dma_chan,
1716 port_map_mask, chnl_prop, active);
1717
1718 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------");
1719
1720 return 0;
1721}
1722
d5c21b88
IM		 1723/*
1724 * Setup the DSP DMA per-transfer-specific registers
1725 */
01ef7dbf
IM		 1726static int dsp_dma_setup(struct hda_codec *codec,
1727 unsigned int chip_addx,
1728 unsigned int count,
1729 unsigned int dma_chan)
1730{
1731 int status = 0;
1732 bool code, yram;
1733 unsigned int dsp_addx;
1734 unsigned int addr_field;
1735 unsigned int incr_field;
1736 unsigned int base_cnt;
1737 unsigned int cur_cnt;
1738 unsigned int dma_cfg = 0;
1739 unsigned int adr_ofs = 0;
1740 unsigned int xfr_cnt = 0;
1741 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1742 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1743
1744 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------");
1745
1746 if (count > max_dma_count) {
1747 snd_printdd(KERN_ERR "count too big");
1748 return -EINVAL;
1749 }
1750
1751 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1752 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1753 snd_printdd(KERN_ERR "invalid chip addr");
1754 return -ENXIO;
1755 }
1756
1757 snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm");
1758
1759 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1760 incr_field = 0;
1761
1762 if (!code) {
1763 addr_field <<= 1;
1764 if (yram)
1765 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1766
1767 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1768 }
1769
1770 dma_cfg = addr_field + incr_field;
1771 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1772 dma_cfg);
1773 if (status < 0) {
1774 snd_printdd(KERN_ERR "write DMACFG Reg fail");
1775 return status;
1776 }
1777 snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG");
1778
1779 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1780 (code ? 0 : 1));
1781
1782 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1783 adr_ofs);
1784 if (status < 0) {
1785 snd_printdd(KERN_ERR "write DSPADROFS Reg fail");
1786 return status;
1787 }
1788 snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS");
1789
1790 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1791
1792 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1793
1794 xfr_cnt = base_cnt | cur_cnt;
1795
1796 status = chipio_write(codec,
1797 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1798 if (status < 0) {
1799 snd_printdd(KERN_ERR "write XFRCNT Reg fail");
1800 return status;
1801 }
1802 snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT");
1803
1804 snd_printdd(
1805 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1806 "ADROFS=0x%x, XFRCNT=0x%x\n",
1807 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1808
1809 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------");
1810
1811 return 0;
1812}
1813
d5c21b88
IM		 1814/*
1815 * Start the DSP DMA
1816 */
01ef7dbf
IM		 1817static int dsp_dma_start(struct hda_codec *codec,
1818 unsigned int dma_chan, bool ovly)
1819{
1820 unsigned int reg = 0;
1821 int status = 0;
1822
1823 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------");
1824
1825 if (ovly) {
1826 status = chipio_read(codec,
1827 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1828
1829 if (status < 0) {
1830 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1831 return status;
1832 }
1833 snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART");
1834
1835 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1836 DSPDMAC_CHNLSTART_DIS_MASK);
1837 }
1838
1839 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1840 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1841 if (status < 0) {
1842 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1843 return status;
1844 }
1845 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------");
1846
1847 return status;
1848}
1849
d5c21b88
IM		 1850/*
1851 * Stop the DSP DMA
1852 */
01ef7dbf
IM		 1853static int dsp_dma_stop(struct hda_codec *codec,
1854 unsigned int dma_chan, bool ovly)
1855{
1856 unsigned int reg = 0;
1857 int status = 0;
1858
1859 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------");
1860
1861 if (ovly) {
1862 status = chipio_read(codec,
1863 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1864
1865 if (status < 0) {
1866 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1867 return status;
1868 }
1869 snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART");
1870 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1871 DSPDMAC_CHNLSTART_DIS_MASK);
1872 }
1873
1874 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1875 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1876 if (status < 0) {
1877 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1878 return status;
1879 }
1880 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------");
1881
1882 return status;
1883}
1884
d5c21b88
IM		 1885/**
1886 * Allocate router ports
1887 *
1888 * @codec: the HDA codec
1889 * @num_chans: number of channels in the stream
1890 * @ports_per_channel: number of ports per channel
1891 * @start_device: start device
1892 * @port_map: pointer to the port list to hold the allocated ports
1893 *
1894 * Returns zero or a negative error code.
1895 */
01ef7dbf
IM		 1896static int dsp_allocate_router_ports(struct hda_codec *codec,
1897 unsigned int num_chans,
1898 unsigned int ports_per_channel,
1899 unsigned int start_device,
1900 unsigned int *port_map)
1901{
1902 int status = 0;
1903 int res;
1904 u8 val;
1905
1906 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1907 if (status < 0)
1908 return status;
1909
1910 val = start_device << 6;
1911 val |= (ports_per_channel - 1) << 4;
1912 val |= num_chans - 1;
1913
1914 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1915 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1916 val);
1917
1918 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1919 VENDOR_CHIPIO_PORT_ALLOC_SET,
1920 MEM_CONNID_DSP);
1921
1922 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1923 if (status < 0)
1924 return status;
1925
1926 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1927 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1928
1929 *port_map = res;
1930
1931 return (res < 0) ? res : 0;
1932}
1933
d5c21b88
IM		 1934/*
1935 * Free router ports
1936 */
01ef7dbf
IM		 1937static int dsp_free_router_ports(struct hda_codec *codec)
1938{
1939 int status = 0;
1940
1941 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1942 if (status < 0)
1943 return status;
1944
1945 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1946 VENDOR_CHIPIO_PORT_FREE_SET,
1947 MEM_CONNID_DSP);
1948
1949 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1950
1951 return status;
1952}
1953
d5c21b88
IM		 1954/*
1955 * Allocate DSP ports for the download stream
1956 */
01ef7dbf
IM		 1957static int dsp_allocate_ports(struct hda_codec *codec,
1958 unsigned int num_chans,
1959 unsigned int rate_multi, unsigned int *port_map)
1960{
1961 int status;
1962
1963 snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin");
1964
1965 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1966 snd_printdd(KERN_ERR "bad rate multiple");
1967 return -EINVAL;
1968 }
1969
1970 status = dsp_allocate_router_ports(codec, num_chans,
1971 rate_multi, 0, port_map);
1972
1973 snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete");
1974
1975 return status;
1976}
1977
01ef7dbf
IM		 1978static int dsp_allocate_ports_format(struct hda_codec *codec,
1979 const unsigned short fmt,
1980 unsigned int *port_map)
1981{
1982 int status;
1983 unsigned int num_chans;
1984
1985 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1986 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1987 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
1988
1989 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1990 snd_printdd(KERN_ERR "bad rate multiple");
1991 return -EINVAL;
1992 }
1993
1994 num_chans = get_hdafmt_chs(fmt) + 1;
1995
1996 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
1997
1998 return status;
1999}
2000
d5c21b88
IM		 2001/*
2002 * free DSP ports
2003 */
2004static int dsp_free_ports(struct hda_codec *codec)
2005{
2006 int status;
2007
2008 snd_printdd(KERN_INFO " dsp_free_ports() -- begin");
2009
2010 status = dsp_free_router_ports(codec);
2011 if (status < 0) {
2012 snd_printdd(KERN_ERR "free router ports fail");
2013 return status;
2014 }
2015 snd_printdd(KERN_INFO " dsp_free_ports() -- complete");
2016
2017 return status;
2018}
2019
01ef7dbf
IM		 2020/*
2021 * HDA DMA engine stuffs for DSP code download
2022 */
2023struct dma_engine {
2024 struct hda_codec *codec;
2025 unsigned short m_converter_format;
2026 struct snd_dma_buffer *dmab;
2027 unsigned int buf_size;
2028};
2029
2030
2031enum dma_state {
2032 DMA_STATE_STOP = 0,
2033 DMA_STATE_RUN = 1
2034};
2035
2036static int dma_convert_to_hda_format(
e97249dd
IM		 2037 unsigned int sample_rate,
2038 unsigned short channels,
01ef7dbf
IM		 2039 unsigned short *hda_format)
2040{
2041 unsigned int format_val;
2042
2043 format_val = snd_hda_calc_stream_format(
e97249dd
IM		 2044 sample_rate,
2045 channels,
01ef7dbf 2046 SNDRV_PCM_FORMAT_S32_LE,
e97249dd 2047 32, 0);
01ef7dbf
IM		 2048
2049 if (hda_format)
2050 *hda_format = (unsigned short)format_val;
2051
2052 return 0;
2053}
2054
d5c21b88
IM		 2055/*
2056 * Reset DMA for DSP download
2057 */
01ef7dbf
IM		 2058static int dma_reset(struct dma_engine *dma)
2059{
2060 struct hda_codec *codec = dma->codec;
2061 struct ca0132_spec *spec = codec->spec;
2062 int status;
2063
2064 if (dma->dmab)
2065 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2066
2067 status = snd_hda_codec_load_dsp_prepare(codec,
2068 dma->m_converter_format,
2069 dma->buf_size,
2070 dma->dmab);
2071 if (status < 0)
2072 return status;
2073 spec->dsp_stream_id = status;
2074 return 0;
2075}
2076
2077static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2078{
01ef7dbf
IM		 2079 bool cmd;
2080
2081 snd_printdd("dma_set_state state=%d\n", state);
2082
2083 switch (state) {
2084 case DMA_STATE_STOP:
2085 cmd = false;
2086 break;
2087 case DMA_STATE_RUN:
2088 cmd = true;
2089 break;
2090 default:
c41999a2
DH		 2091 return 0;
2092 }
01ef7dbf
IM		 2093
2094 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2095 return 0;
95c6e9cb
IM		 2096}
2097
01ef7dbf
IM		 2098static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2099{
2100 return dma->dmab->bytes;
2101}
95c6e9cb 2102
01ef7dbf
IM		 2103static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2104{
2105 return dma->dmab->area;
2106}
95c6e9cb 2107
01ef7dbf
IM		 2108static int dma_xfer(struct dma_engine *dma,
2109 const unsigned int *data,
2110 unsigned int count)
2111{
2112 memcpy(dma->dmab->area, data, count);
2113 return 0;
2114}
95c6e9cb 2115
01ef7dbf
IM		 2116static void dma_get_converter_format(
2117 struct dma_engine *dma,
2118 unsigned short *format)
2119{
2120 if (format)
2121 *format = dma->m_converter_format;
2122}
95c6e9cb 2123
01ef7dbf 2124static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2125{
01ef7dbf 2126 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2127
01ef7dbf 2128 return spec->dsp_stream_id;
95c6e9cb
IM		 2129}
2130
01ef7dbf
IM		 2131struct dsp_image_seg {
2132 u32 magic;
2133 u32 chip_addr;
2134 u32 count;
2135 u32 data[0];
2136};
2137
2138static const u32 g_magic_value = 0x4c46584d;
2139static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2140
2141static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2142{
01ef7dbf
IM		 2143 return p->magic == g_magic_value;
2144}
95c6e9cb 2145
01ef7dbf
IM		 2146static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2147{
2148 return g_chip_addr_magic_value == p->chip_addr;
2149}
95c6e9cb 2150
01ef7dbf
IM		 2151static bool is_last(const struct dsp_image_seg *p)
2152{
2153 return p->count == 0;
2154}
95c6e9cb 2155
01ef7dbf
IM		 2156static size_t dsp_sizeof(const struct dsp_image_seg *p)
2157{
2158 return sizeof(*p) + p->count*sizeof(u32);
2159}
2160
2161static const struct dsp_image_seg *get_next_seg_ptr(
2162 const struct dsp_image_seg *p)
2163{
2164 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2165}
2166
2167/*
01ef7dbf 2168 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2169 */
01ef7dbf 2170#define INVALID_DMA_CHANNEL (~0UL)
95c6e9cb 2171
d5c21b88
IM		 2172/*
2173 * Program a list of address/data pairs via the ChipIO widget.
2174 * The segment data is in the format of successive pairs of words.
2175 * These are repeated as indicated by the segment's count field.
2176 */
01ef7dbf
IM		 2177static int dspxfr_hci_write(struct hda_codec *codec,
2178 const struct dsp_image_seg *fls)
95c6e9cb 2179{
01ef7dbf
IM		 2180 int status;
2181 const u32 *data;
2182 unsigned int count;
95c6e9cb 2183
01ef7dbf
IM		 2184 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2185 snd_printdd(KERN_ERR "hci_write invalid params");
2186 return -EINVAL;
95c6e9cb
IM		 2187 }
2188
01ef7dbf
IM		 2189 count = fls->count;
2190 data = (u32 *)(fls->data);
2191 while (count >= 2) {
2192 status = chipio_write(codec, data[0], data[1]);
2193 if (status < 0) {
2194 snd_printdd(KERN_ERR "hci_write chipio failed");
2195 return status;
2196 }
2197 count -= 2;
2198 data += 2;
2199 }
2200 return 0;
95c6e9cb
IM		 2201}
2202
d5c21b88
IM		 2203/**
2204 * Write a block of data into DSP code or data RAM using pre-allocated
2205 * DMA engine.
2206 *
2207 * @codec: the HDA codec
2208 * @fls: pointer to a fast load image
2209 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2210 * no relocation
2211 * @dma_engine: pointer to DMA engine to be used for DSP download
2212 * @dma_chan: The number of DMA channels used for DSP download
2213 * @port_map_mask: port mapping
2214 * @ovly: TRUE if overlay format is required
2215 *
2216 * Returns zero or a negative error code.
2217 */
01ef7dbf
IM		 2218static int dspxfr_one_seg(struct hda_codec *codec,
2219 const struct dsp_image_seg *fls,
2220 unsigned int reloc,
2221 struct dma_engine *dma_engine,
2222 unsigned int dma_chan,
2223 unsigned int port_map_mask,
2224 bool ovly)
95c6e9cb 2225{
01ef7dbf
IM		 2226 int status;
2227 bool comm_dma_setup_done = false;
2228 const unsigned int *data;
2229 unsigned int chip_addx;
2230 unsigned int words_to_write;
2231 unsigned int buffer_size_words;
2232 unsigned char *buffer_addx;
2233 unsigned short hda_format;
2234 unsigned int sample_rate_div;
2235 unsigned int sample_rate_mul;
2236 unsigned int num_chans;
2237 unsigned int hda_frame_size_words;
2238 unsigned int remainder_words;
2239 const u32 *data_remainder;
2240 u32 chip_addx_remainder;
2241 unsigned int run_size_words;
2242 const struct dsp_image_seg *hci_write = NULL;
2243 int retry;
2244
2245 if (fls == NULL)
2246 return -EINVAL;
2247 if (is_hci_prog_list_seg(fls)) {
2248 hci_write = fls;
2249 fls = get_next_seg_ptr(fls);
2250 }
95c6e9cb 2251
01ef7dbf
IM		 2252 if (hci_write && (!fls || is_last(fls))) {
2253 snd_printdd("hci_write\n");
2254 return dspxfr_hci_write(codec, hci_write);
2255 }
95c6e9cb 2256
01ef7dbf
IM		 2257 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2258 snd_printdd("Invalid Params\n");
2259 return -EINVAL;
95c6e9cb
IM		 2260 }
2261
01ef7dbf
IM		 2262 data = fls->data;
2263 chip_addx = fls->chip_addr,
2264 words_to_write = fls->count;
2265
2266 if (!words_to_write)
2267 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2268 if (reloc)
2269 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2270
2271 if (!UC_RANGE(chip_addx, words_to_write) &&
2272 !X_RANGE_ALL(chip_addx, words_to_write) &&
2273 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2274 snd_printdd("Invalid chip_addx Params\n");
2275 return -EINVAL;
95c6e9cb
IM		 2276 }
2277
01ef7dbf
IM		 2278 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2279 sizeof(u32);
2280
2281 buffer_addx = dma_get_buffer_addr(dma_engine);
2282
2283 if (buffer_addx == NULL) {
2284 snd_printdd(KERN_ERR "dma_engine buffer NULL\n");
2285 return -EINVAL;
2286 }
2287
2288 dma_get_converter_format(dma_engine, &hda_format);
2289 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2290 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2291 num_chans = get_hdafmt_chs(hda_format) + 1;
2292
2293 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2294 (num_chans * sample_rate_mul / sample_rate_div));
2295
2296 buffer_size_words = min(buffer_size_words,
2297 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2298 65536 : 32768));
2299 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2300 snd_printdd(
2301 "chpadr=0x%08x frmsz=%u nchan=%u "
2302 "rate_mul=%u div=%u bufsz=%u\n",
2303 chip_addx, hda_frame_size_words, num_chans,
2304 sample_rate_mul, sample_rate_div, buffer_size_words);
2305
2306 if ((buffer_addx == NULL) || (hda_frame_size_words == 0) ||
2307 (buffer_size_words < hda_frame_size_words)) {
2308 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n");
2309 return -EINVAL;
2310 }
2311
2312 remainder_words = words_to_write % hda_frame_size_words;
2313 data_remainder = data;
2314 chip_addx_remainder = chip_addx;
2315
2316 data += remainder_words;
2317 chip_addx += remainder_words*sizeof(u32);
2318 words_to_write -= remainder_words;
2319
2320 while (words_to_write != 0) {
2321 run_size_words = min(buffer_size_words, words_to_write);
2322 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2323 words_to_write, run_size_words, remainder_words);
2324 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2325 if (!comm_dma_setup_done) {
2326 status = dsp_dma_stop(codec, dma_chan, ovly);
2327 if (status < 0)
2328 return -EIO;
2329 status = dsp_dma_setup_common(codec, chip_addx,
2330 dma_chan, port_map_mask, ovly);
2331 if (status < 0)
2332 return status;
2333 comm_dma_setup_done = true;
2334 }
2335
2336 status = dsp_dma_setup(codec, chip_addx,
2337 run_size_words, dma_chan);
2338 if (status < 0)
2339 return status;
2340 status = dsp_dma_start(codec, dma_chan, ovly);
2341 if (status < 0)
2342 return status;
2343 if (!dsp_is_dma_active(codec, dma_chan)) {
2344 snd_printdd(KERN_ERR "dspxfr:DMA did not start");
2345 return -EIO;
2346 }
2347 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2348 if (status < 0)
2349 return status;
2350 if (remainder_words != 0) {
2351 status = chipio_write_multiple(codec,
2352 chip_addx_remainder,
2353 data_remainder,
2354 remainder_words);
2355 remainder_words = 0;
2356 }
2357 if (hci_write) {
2358 status = dspxfr_hci_write(codec, hci_write);
2359 hci_write = NULL;
2360 }
2361 retry = 5000;
2362 while (dsp_is_dma_active(codec, dma_chan)) {
2363 if (--retry <= 0)
2364 break;
2365 }
2366 snd_printdd(KERN_INFO "+++++ DMA complete");
2367 dma_set_state(dma_engine, DMA_STATE_STOP);
2368 dma_reset(dma_engine);
2369
2370 if (status < 0)
2371 return status;
2372
2373 data += run_size_words;
2374 chip_addx += run_size_words*sizeof(u32);
2375 words_to_write -= run_size_words;
2376 }
2377
2378 if (remainder_words != 0) {
2379 status = chipio_write_multiple(codec, chip_addx_remainder,
2380 data_remainder, remainder_words);
2381 }
2382
2383 return status;
95c6e9cb
IM		 2384}
2385
d5c21b88
IM		 2386/**
2387 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2388 *
2389 * @codec: the HDA codec
2390 * @fls_data: pointer to a fast load image
2391 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2392 * no relocation
e97249dd
IM		 2393 * @sample_rate: sampling rate of the stream used for DSP download
2394 * @number_channels: channels of the stream used for DSP download
d5c21b88
IM		 2395 * @ovly: TRUE if overlay format is required
2396 *
2397 * Returns zero or a negative error code.
2398 */
01ef7dbf
IM		 2399static int dspxfr_image(struct hda_codec *codec,
2400 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2401 unsigned int reloc,
2402 unsigned int sample_rate,
2403 unsigned short channels,
01ef7dbf 2404 bool ovly)
95c6e9cb
IM		 2405{
2406 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2407 int status;
2408 unsigned short hda_format = 0;
2409 unsigned int response;
2410 unsigned char stream_id = 0;
2411 struct dma_engine *dma_engine;
2412 unsigned int dma_chan;
2413 unsigned int port_map_mask;
2414
2415 if (fls_data == NULL)
2416 return -EINVAL;
2417
2418 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
063bca09
TI		 2419 if (!dma_engine)
2420 return -ENOMEM;
95c6e9cb 2421
01ef7dbf
IM		 2422 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2423 if (!dma_engine->dmab) {
2424 status = -ENOMEM;
2425 goto exit;
2426 }
95c6e9cb 2427
01ef7dbf 2428 dma_engine->codec = codec;
e97249dd 2429 dma_convert_to_hda_format(sample_rate, channels, &hda_format);
01ef7dbf
IM		 2430 dma_engine->m_converter_format = hda_format;
2431 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2432 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2433
2434 dma_chan = 0;
2435
2436 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2437 hda_format, &response);
2438
2439 if (status < 0) {
2440 snd_printdd(KERN_ERR "set converter format fail");
2441 goto exit;
2442 }
2443
2444 status = snd_hda_codec_load_dsp_prepare(codec,
2445 dma_engine->m_converter_format,
2446 dma_engine->buf_size,
2447 dma_engine->dmab);
2448 if (status < 0)
95c6e9cb 2449 goto exit;
01ef7dbf
IM		 2450 spec->dsp_stream_id = status;
2451
2452 if (ovly) {
2453 status = dspio_alloc_dma_chan(codec, &dma_chan);
2454 if (status < 0) {
2455 snd_printdd(KERN_ERR "alloc dmachan fail");
2456 dma_chan = (unsigned int)INVALID_DMA_CHANNEL;
2457 goto exit;
2458 }
2459 }
95c6e9cb 2460
01ef7dbf
IM		 2461 port_map_mask = 0;
2462 status = dsp_allocate_ports_format(codec, hda_format,
2463 &port_map_mask);
2464 if (status < 0) {
2465 snd_printdd(KERN_ERR "alloc ports fail");
2466 goto exit;
2467 }
2468
2469 stream_id = dma_get_stream_id(dma_engine);
2470 status = codec_set_converter_stream_channel(codec,
2471 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2472 if (status < 0) {
2473 snd_printdd(KERN_ERR "set stream chan fail");
2474 goto exit;
2475 }
2476
2477 while ((fls_data != NULL) && !is_last(fls_data)) {
2478 if (!is_valid(fls_data)) {
2479 snd_printdd(KERN_ERR "FLS check fail");
2480 status = -EINVAL;
2481 goto exit;
2482 }
2483 status = dspxfr_one_seg(codec, fls_data, reloc,
2484 dma_engine, dma_chan,
2485 port_map_mask, ovly);
2486 if (status < 0)
2487 break;
2488
2489 if (is_hci_prog_list_seg(fls_data))
2490 fls_data = get_next_seg_ptr(fls_data);
2491
2492 if ((fls_data != NULL) && !is_last(fls_data))
2493 fls_data = get_next_seg_ptr(fls_data);
2494 }
2495
2496 if (port_map_mask != 0)
2497 status = dsp_free_ports(codec);
2498
2499 if (status < 0)
95c6e9cb
IM		 2500 goto exit;
2501
01ef7dbf
IM		 2502 status = codec_set_converter_stream_channel(codec,
2503 WIDGET_CHIP_CTRL, 0, 0, &response);
2504
95c6e9cb 2505exit:
01ef7dbf
IM		 2506 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2507 dspio_free_dma_chan(codec, dma_chan);
2508
2509 if (dma_engine->dmab)
2510 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2511 kfree(dma_engine->dmab);
2512 kfree(dma_engine);
2513
2514 return status;
95c6e9cb
IM		 2515}
2516
2517/*
01ef7dbf 2518 * CA0132 DSP download stuffs.
95c6e9cb 2519 */
01ef7dbf 2520static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2521{
01ef7dbf 2522 snd_printdd(KERN_INFO "---- dspload_post_setup ------");
95c6e9cb 2523
01ef7dbf
IM		 2524 /*set DSP speaker to 2.0 configuration*/
2525 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2526 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2527
01ef7dbf
IM		 2528 /*update write pointer*/
2529 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2530}
95c6e9cb 2531
d5c21b88
IM		 2532/**
2533 * Download DSP from a DSP Image Fast Load structure. This structure is a
2534 * linear, non-constant sized element array of structures, each of which
2535 * contain the count of the data to be loaded, the data itself, and the
2536 * corresponding starting chip address of the starting data location.
2537 *
2538 * @codec: the HDA codec
2539 * @fls: pointer to a fast load image
2540 * @ovly: TRUE if overlay format is required
2541 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2542 * no relocation
2543 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2544 * @router_chans: number of audio router channels to be allocated (0 means use
2545 * internal defaults; max is 32)
2546 *
2547 * Returns zero or a negative error code.
2548 */
01ef7dbf
IM		 2549static int dspload_image(struct hda_codec *codec,
2550 const struct dsp_image_seg *fls,
2551 bool ovly,
2552 unsigned int reloc,
2553 bool autostart,
2554 int router_chans)
2555{
2556 int status = 0;
e97249dd
IM		 2557 unsigned int sample_rate;
2558 unsigned short channels;
01ef7dbf
IM		 2559
2560 snd_printdd(KERN_INFO "---- dspload_image begin ------");
2561 if (router_chans == 0) {
2562 if (!ovly)
2563 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2564 else
2565 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2566 }
95c6e9cb 2567
e97249dd
IM		 2568 sample_rate = 48000;
2569 channels = (unsigned short)router_chans;
01ef7dbf 2570
e97249dd
IM		 2571 while (channels > 16) {
2572 sample_rate *= 2;
2573 channels /= 2;
01ef7dbf
IM		 2574 }
2575
01ef7dbf
IM		 2576 do {
2577 snd_printdd(KERN_INFO "Ready to program DMA");
2578 if (!ovly)
2579 status = dsp_reset(codec);
2580
2581 if (status < 0)
2582 break;
2583
2584 snd_printdd(KERN_INFO "dsp_reset() complete");
e97249dd
IM		 2585 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2586 ovly);
01ef7dbf
IM		 2587
2588 if (status < 0)
2589 break;
2590
2591 snd_printdd(KERN_INFO "dspxfr_image() complete");
2592 if (autostart && !ovly) {
2593 dspload_post_setup(codec);
2594 status = dsp_set_run_state(codec);
2595 }
2596
2597 snd_printdd(KERN_INFO "LOAD FINISHED");
2598 } while (0);
2599
2600 return status;
2601}
2602
c3b4eea2
IM		 2603static const struct firmware *fw_efx;
2604
2605static int request_firmware_cached(const struct firmware **firmware_p,
2606 const char *name, struct device *device)
2607{
2608 if (*firmware_p)
2609 return 0; /* already loaded */
2610 return request_firmware(firmware_p, name, device);
2611}
2612
2613static void release_cached_firmware(void)
2614{
2615 if (fw_efx) {
2616 release_firmware(fw_efx);
2617 fw_efx = NULL;
2618 }
2619}
2620
01ef7dbf
IM		 2621static bool dspload_is_loaded(struct hda_codec *codec)
2622{
2623 unsigned int data = 0;
2624 int status = 0;
2625
2626 status = chipio_read(codec, 0x40004, &data);
2627 if ((status < 0) || (data != 1))
2628 return false;
2629
2630 return true;
2631}
2632
2633static bool dspload_wait_loaded(struct hda_codec *codec)
2634{
2635 int retry = 100;
2636
2637 do {
2638 msleep(20);
2639 if (dspload_is_loaded(codec)) {
2640 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2641 return true;
2642 }
2643 } while (--retry);
2644
2645 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2646 return false;
95c6e9cb
IM		 2647}
2648
2649/*
825315bc 2650 * PCM stuffs
95c6e9cb 2651 */
825315bc
IM		 2652static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
2653 u32 stream_tag,
2654 int channel_id, int format)
95c6e9cb 2655{
825315bc
IM		 2656 unsigned int oldval, newval;
2657
2658 if (!nid)
2659 return;
2660
2661 snd_printdd(
2662 "ca0132_setup_stream: NID=0x%x, stream=0x%x, "
2663 "channel=%d, format=0x%x\n",
2664 nid, stream_tag, channel_id, format);
2665
2666 /* update the format-id if changed */
2667 oldval = snd_hda_codec_read(codec, nid, 0,
2668 AC_VERB_GET_STREAM_FORMAT,
2669 0);
2670 if (oldval != format) {
2671 msleep(20);
2672 snd_hda_codec_write(codec, nid, 0,
2673 AC_VERB_SET_STREAM_FORMAT,
2674 format);
2675 }
2676
2677 oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2678 newval = (stream_tag << 4) | channel_id;
2679 if (oldval != newval) {
2680 snd_hda_codec_write(codec, nid, 0,
2681 AC_VERB_SET_CHANNEL_STREAMID,
2682 newval);
2683 }
2684}
2685
2686static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
2687{
2688 unsigned int val;
2689
2690 if (!nid)
2691 return;
2692
2693 snd_printdd(KERN_INFO "ca0132_cleanup_stream: NID=0x%x\n", nid);
2694
2695 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2696 if (!val)
2697 return;
2698
2699 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
2700 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
95c6e9cb
IM		 2701}
2702
825315bc
IM		 2703/*
2704 * PCM callbacks
2705 */
95c6e9cb
IM		 2706static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2707 struct hda_codec *codec,
2708 unsigned int stream_tag,
2709 unsigned int format,
2710 struct snd_pcm_substream *substream)
2711{
2712 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2713
2714 ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2715
2716 return 0;
95c6e9cb
IM		 2717}
2718
2719static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2720 struct hda_codec *codec,
2721 struct snd_pcm_substream *substream)
2722{
2723 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2724
2725 if (spec->dsp_state == DSP_DOWNLOADING)
2726 return 0;
2727
2728 /*If Playback effects are on, allow stream some time to flush
2729 *effects tail*/
2730 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2731 msleep(50);
2732
2733 ca0132_cleanup_stream(codec, spec->dacs[0]);
2734
2735 return 0;
95c6e9cb
IM		 2736}
2737
2738/*
2739 * Digital out
2740 */
27ebeb0b
TI		 2741static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2742 struct hda_codec *codec,
2743 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2744{
2745 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2746 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2747}
2748
27ebeb0b 2749static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2750 struct hda_codec *codec,
2751 unsigned int stream_tag,
2752 unsigned int format,
2753 struct snd_pcm_substream *substream)
2754{
2755 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2756 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2757 stream_tag, format, substream);
95c6e9cb
IM		 2758}
2759
27ebeb0b 2760static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2761 struct hda_codec *codec,
95c6e9cb
IM		 2762 struct snd_pcm_substream *substream)
2763{
2764 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2765 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2766}
2767
27ebeb0b
TI		 2768static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2769 struct hda_codec *codec,
2770 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2771{
2772 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2773 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2774}
2775
825315bc
IM		 2776/*
2777 * Analog capture
2778 */
2779static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2780 struct hda_codec *codec,
2781 unsigned int stream_tag,
2782 unsigned int format,
2783 struct snd_pcm_substream *substream)
2784{
2785 struct ca0132_spec *spec = codec->spec;
2786
2787 ca0132_setup_stream(codec, spec->adcs[substream->number],
2788 stream_tag, 0, format);
2789
2790 return 0;
2791}
2792
2793static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2794 struct hda_codec *codec,
2795 struct snd_pcm_substream *substream)
2796{
2797 struct ca0132_spec *spec = codec->spec;
2798
2799 if (spec->dsp_state == DSP_DOWNLOADING)
2800 return 0;
2801
2802 ca0132_cleanup_stream(codec, hinfo->nid);
2803 return 0;
2804}
2805
e90f29e4
IM		 2806/*
2807 * Controls stuffs.
2808 */
2809
2810/*
2811 * Mixer controls helpers.
2812 */
2813#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2814 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2815 .name = xname, \
2816 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2817 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2818 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2819 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2820 .info = ca0132_volume_info, \
2821 .get = ca0132_volume_get, \
2822 .put = ca0132_volume_put, \
2823 .tlv = { .c = ca0132_volume_tlv }, \
2824 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2825
2826#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2827 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2828 .name = xname, \
2829 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2830 .info = snd_hda_mixer_amp_switch_info, \
2831 .get = ca0132_switch_get, \
2832 .put = ca0132_switch_put, \
2833 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2834
2835/* stereo */
2836#define CA0132_CODEC_VOL(xname, nid, dir) \
2837 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2838#define CA0132_CODEC_MUTE(xname, nid, dir) \
2839 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2840
44f0c978
IM		 2841/* The followings are for tuning of products */
2842#ifdef ENABLE_TUNING_CONTROLS
2843
2844static unsigned int voice_focus_vals_lookup[] = {
28450x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
28460x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
28470x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
28480x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
28490x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
28500x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
28510x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
28520x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
28530x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
28540x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
28550x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
28560x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
28570x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
28580x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
28590x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
28600x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
28610x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
28620x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
28630x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
28640x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
28650x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
28660x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
28670x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
28680x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
28690x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
28700x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
28710x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2872};
2873
2874static unsigned int mic_svm_vals_lookup[] = {
28750x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
28760x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
28770x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
28780x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
28790x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
28800x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
28810x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
28820x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
28830x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
28840x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
28850x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
28860x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
28870x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
28880x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
28890x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
28900x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
28910x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2892};
2893
2894static unsigned int equalizer_vals_lookup[] = {
28950xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
28960xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
28970xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
28980xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
28990x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
29000x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
29010x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
29020x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
29030x41C00000
2904};
2905
2906static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2907 unsigned int *lookup, int idx)
2908{
2909 int i = 0;
2910
2911 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2912 if (nid == ca0132_tuning_ctls[i].nid)
2913 break;
2914
2915 snd_hda_power_up(codec);
2916 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2917 ca0132_tuning_ctls[i].req,
2918 &(lookup[idx]), sizeof(unsigned int));
2919 snd_hda_power_down(codec);
2920
2921 return 1;
2922}
2923
2924static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2925 struct snd_ctl_elem_value *ucontrol)
2926{
2927 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2928 struct ca0132_spec *spec = codec->spec;
2929 hda_nid_t nid = get_amp_nid(kcontrol);
2930 long *valp = ucontrol->value.integer.value;
2931 int idx = nid - TUNING_CTL_START_NID;
2932
2933 *valp = spec->cur_ctl_vals[idx];
2934 return 0;
2935}
2936
2937static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2938 struct snd_ctl_elem_info *uinfo)
2939{
2940 int chs = get_amp_channels(kcontrol);
2941 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2942 uinfo->count = chs == 3 ? 2 : 1;
2943 uinfo->value.integer.min = 20;
2944 uinfo->value.integer.max = 180;
2945 uinfo->value.integer.step = 1;
2946
2947 return 0;
2948}
2949
2950static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2951 struct snd_ctl_elem_value *ucontrol)
2952{
2953 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2954 struct ca0132_spec *spec = codec->spec;
2955 hda_nid_t nid = get_amp_nid(kcontrol);
2956 long *valp = ucontrol->value.integer.value;
2957 int idx;
2958
2959 idx = nid - TUNING_CTL_START_NID;
2960 /* any change? */
2961 if (spec->cur_ctl_vals[idx] == *valp)
2962 return 0;
2963
2964 spec->cur_ctl_vals[idx] = *valp;
2965
2966 idx = *valp - 20;
2967 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2968
2969 return 1;
2970}
2971
2972static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2973 struct snd_ctl_elem_info *uinfo)
2974{
2975 int chs = get_amp_channels(kcontrol);
2976 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2977 uinfo->count = chs == 3 ? 2 : 1;
2978 uinfo->value.integer.min = 0;
2979 uinfo->value.integer.max = 100;
2980 uinfo->value.integer.step = 1;
2981
2982 return 0;
2983}
2984
2985static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2986 struct snd_ctl_elem_value *ucontrol)
2987{
2988 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2989 struct ca0132_spec *spec = codec->spec;
2990 hda_nid_t nid = get_amp_nid(kcontrol);
2991 long *valp = ucontrol->value.integer.value;
2992 int idx;
2993
2994 idx = nid - TUNING_CTL_START_NID;
2995 /* any change? */
2996 if (spec->cur_ctl_vals[idx] == *valp)
2997 return 0;
2998
2999 spec->cur_ctl_vals[idx] = *valp;
3000
3001 idx = *valp;
3002 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3003
3004 return 0;
3005}
3006
3007static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3008 struct snd_ctl_elem_info *uinfo)
3009{
3010 int chs = get_amp_channels(kcontrol);
3011 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3012 uinfo->count = chs == 3 ? 2 : 1;
3013 uinfo->value.integer.min = 0;
3014 uinfo->value.integer.max = 48;
3015 uinfo->value.integer.step = 1;
3016
3017 return 0;
3018}
3019
3020static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3021 struct snd_ctl_elem_value *ucontrol)
3022{
3023 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3024 struct ca0132_spec *spec = codec->spec;
3025 hda_nid_t nid = get_amp_nid(kcontrol);
3026 long *valp = ucontrol->value.integer.value;
3027 int idx;
3028
3029 idx = nid - TUNING_CTL_START_NID;
3030 /* any change? */
3031 if (spec->cur_ctl_vals[idx] == *valp)
3032 return 0;
3033
3034 spec->cur_ctl_vals[idx] = *valp;
3035
3036 idx = *valp;
3037 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3038
3039 return 1;
3040}
3041
3042static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3043static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3044
3045static int add_tuning_control(struct hda_codec *codec,
3046 hda_nid_t pnid, hda_nid_t nid,
3047 const char *name, int dir)
3048{
3049 char namestr[44];
3050 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3051 struct snd_kcontrol_new knew =
3052 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3053
3054 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3055 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3056 knew.tlv.c = 0;
3057 knew.tlv.p = 0;
3058 switch (pnid) {
3059 case VOICE_FOCUS:
3060 knew.info = voice_focus_ctl_info;
3061 knew.get = tuning_ctl_get;
3062 knew.put = voice_focus_ctl_put;
3063 knew.tlv.p = voice_focus_db_scale;
3064 break;
3065 case MIC_SVM:
3066 knew.info = mic_svm_ctl_info;
3067 knew.get = tuning_ctl_get;
3068 knew.put = mic_svm_ctl_put;
3069 break;
3070 case EQUALIZER:
3071 knew.info = equalizer_ctl_info;
3072 knew.get = tuning_ctl_get;
3073 knew.put = equalizer_ctl_put;
3074 knew.tlv.p = eq_db_scale;
3075 break;
3076 default:
3077 return 0;
3078 }
3079 knew.private_value =
3080 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3081 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3082 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3083}
3084
3085static int add_tuning_ctls(struct hda_codec *codec)
3086{
3087 int i;
3088 int err;
3089
3090 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3091 err = add_tuning_control(codec,
3092 ca0132_tuning_ctls[i].parent_nid,
3093 ca0132_tuning_ctls[i].nid,
3094 ca0132_tuning_ctls[i].name,
3095 ca0132_tuning_ctls[i].direct);
3096 if (err < 0)
3097 return err;
3098 }
3099
3100 return 0;
3101}
3102
3103static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3104{
3105 struct ca0132_spec *spec = codec->spec;
3106 int i;
3107
3108 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3109 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3110 /* SVM level defaults to 0.74. */
3111 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3112
3113 /* EQ defaults to 0dB. */
3114 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3115 spec->cur_ctl_vals[i] = 24;
3116}
3117#endif /*ENABLE_TUNING_CONTROLS*/
3118
5aaca44d
IM		 3119/*
3120 * Select the active output.
3121 * If autodetect is enabled, output will be selected based on jack detection.
3122 * If jack inserted, headphone will be selected, else built-in speakers
3123 * If autodetect is disabled, output will be selected based on selection.
3124 */
3125static int ca0132_select_out(struct hda_codec *codec)
3126{
3127 struct ca0132_spec *spec = codec->spec;
3128 unsigned int pin_ctl;
3129 int jack_present;
3130 int auto_jack;
3131 unsigned int tmp;
3132 int err;
3133
3134 snd_printdd(KERN_INFO "ca0132_select_out\n");
3135
3136 snd_hda_power_up(codec);
3137
3138 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3139
3140 if (auto_jack)
3141 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3142 else
3143 jack_present =
3144 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3145
3146 if (jack_present)
3147 spec->cur_out_type = HEADPHONE_OUT;
3148 else
3149 spec->cur_out_type = SPEAKER_OUT;
3150
3151 if (spec->cur_out_type == SPEAKER_OUT) {
3152 snd_printdd(KERN_INFO "ca0132_select_out speaker\n");
3153 /*speaker out config*/
3154 tmp = FLOAT_ONE;
3155 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3156 if (err < 0)
3157 goto exit;
3158 /*enable speaker EQ*/
3159 tmp = FLOAT_ONE;
3160 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3161 if (err < 0)
3162 goto exit;
3163
3164 /* Setup EAPD */
3165 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3166 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3167 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3168 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3169 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3170 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3171 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3172 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3173
3174 /* disable headphone node */
3175 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3176 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3177 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3178 AC_VERB_SET_PIN_WIDGET_CONTROL,
3179 pin_ctl & 0xBF);
3180 /* enable speaker node */
3181 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3182 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3183 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3184 AC_VERB_SET_PIN_WIDGET_CONTROL,
3185 pin_ctl | 0x40);
3186 } else {
3187 snd_printdd(KERN_INFO "ca0132_select_out hp\n");
3188 /*headphone out config*/
3189 tmp = FLOAT_ZERO;
3190 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3191 if (err < 0)
3192 goto exit;
3193 /*disable speaker EQ*/
3194 tmp = FLOAT_ZERO;
3195 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3196 if (err < 0)
3197 goto exit;
3198
3199 /* Setup EAPD */
3200 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3201 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3202 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3203 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3204 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3205 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3206 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3207 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3208
3209 /* disable speaker*/
3210 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3211 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3212 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3213 AC_VERB_SET_PIN_WIDGET_CONTROL,
3214 pin_ctl & 0xBF);
3215 /* enable headphone*/
3216 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3217 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3218 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3219 AC_VERB_SET_PIN_WIDGET_CONTROL,
3220 pin_ctl | 0x40);
3221 }
3222
3223exit:
3224 snd_hda_power_down(codec);
3225
3226 return err < 0 ? err : 0;
3227}
3228
3229static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3230static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3231static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3232
3233/*
3234 * Select the active VIP source
3235 */
3236static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3237{
3238 struct ca0132_spec *spec = codec->spec;
3239 unsigned int tmp;
3240
3241 if (!dspload_is_loaded(codec))
3242 return 0;
3243
3244 /* if CrystalVoice if off, vipsource should be 0 */
3245 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3246 (val == 0)) {
3247 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3248 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3249 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3250 if (spec->cur_mic_type == DIGITAL_MIC)
3251 tmp = FLOAT_TWO;
3252 else
3253 tmp = FLOAT_ONE;
3254 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3255 tmp = FLOAT_ZERO;
3256 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3257 } else {
3258 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3259 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3260 if (spec->cur_mic_type == DIGITAL_MIC)
3261 tmp = FLOAT_TWO;
3262 else
3263 tmp = FLOAT_ONE;
3264 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3265 tmp = FLOAT_ONE;
3266 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3267 msleep(20);
3268 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3269 }
3270
3271 return 1;
3272}
3273
3274/*
3275 * Select the active microphone.
3276 * If autodetect is enabled, mic will be selected based on jack detection.
3277 * If jack inserted, ext.mic will be selected, else built-in mic
3278 * If autodetect is disabled, mic will be selected based on selection.
3279 */
3280static int ca0132_select_mic(struct hda_codec *codec)
3281{
3282 struct ca0132_spec *spec = codec->spec;
3283 int jack_present;
3284 int auto_jack;
3285
3286 snd_printdd(KERN_INFO "ca0132_select_mic\n");
3287
3288 snd_hda_power_up(codec);
3289
3290 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3291
3292 if (auto_jack)
3293 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3294 else
3295 jack_present =
3296 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3297
3298 if (jack_present)
3299 spec->cur_mic_type = LINE_MIC_IN;
3300 else
3301 spec->cur_mic_type = DIGITAL_MIC;
3302
3303 if (spec->cur_mic_type == DIGITAL_MIC) {
3304 /* enable digital Mic */
3305 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3306 ca0132_set_dmic(codec, 1);
3307 ca0132_mic_boost_set(codec, 0);
3308 /* set voice focus */
3309 ca0132_effects_set(codec, VOICE_FOCUS,
3310 spec->effects_switch
3311 [VOICE_FOCUS - EFFECT_START_NID]);
3312 } else {
3313 /* disable digital Mic */
3314 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3315 ca0132_set_dmic(codec, 0);
3316 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3317 /* disable voice focus */
3318 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3319 }
3320
3321 snd_hda_power_down(codec);
3322
3323 return 0;
3324}
3325
a7e76271
IM		 3326/*
3327 * Check if VNODE settings take effect immediately.
3328 */
3329static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3330 hda_nid_t vnid,
3331 hda_nid_t *shared_nid)
3332{
3333 struct ca0132_spec *spec = codec->spec;
3334 hda_nid_t nid;
3335 bool effective = false;
3336
3337 switch (vnid) {
3338 case VNID_SPK:
3339 nid = spec->shared_out_nid;
3340 effective = true;
3341 break;
3342 case VNID_MIC:
3343 nid = spec->shared_mic_nid;
3344 effective = true;
3345 break;
3346 default:
3347 break;
3348 }
3349
3350 if (effective && shared_nid)
3351 *shared_nid = nid;
3352
3353 return effective;
3354}
3355
3356/*
3357* The following functions are control change helpers.
3358* They return 0 if no changed. Return 1 if changed.
3359*/
3360static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3361{
3362 struct ca0132_spec *spec = codec->spec;
3363 unsigned int tmp;
3364
3365 /* based on CrystalVoice state to enable VoiceFX. */
3366 if (enable) {
3367 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3368 FLOAT_ONE : FLOAT_ZERO;
3369 } else {
3370 tmp = FLOAT_ZERO;
3371 }
3372
3373 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3374 ca0132_voicefx.reqs[0], tmp);
3375
3376 return 1;
3377}
3378
5aaca44d
IM		 3379/*
3380 * Set the effects parameters
3381 */
3382static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3383{
3384 struct ca0132_spec *spec = codec->spec;
3385 unsigned int on;
3386 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3387 int err = 0;
3388 int idx = nid - EFFECT_START_NID;
3389
3390 if ((idx < 0) || (idx >= num_fx))
3391 return 0; /* no changed */
3392
3393 /* for out effect, qualify with PE */
3394 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3395 /* if PE if off, turn off out effects. */
3396 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3397 val = 0;
3398 }
3399
3400 /* for in effect, qualify with CrystalVoice */
3401 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3402 /* if CrystalVoice if off, turn off in effects. */
3403 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3404 val = 0;
3405
3406 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3407 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3408 val = 0;
3409 }
3410
3411 snd_printdd(KERN_INFO, "ca0132_effect_set: nid=0x%x, val=%ld\n",
3412 nid, val);
3413
3414 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3415 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3416 ca0132_effects[idx].reqs[0], on);
3417
3418 if (err < 0)
3419 return 0; /* no changed */
3420
3421 return 1;
3422}
3423
a7e76271
IM		 3424/*
3425 * Turn on/off Playback Enhancements
3426 */
3427static int ca0132_pe_switch_set(struct hda_codec *codec)
3428{
3429 struct ca0132_spec *spec = codec->spec;
3430 hda_nid_t nid;
3431 int i, ret = 0;
3432
3433 snd_printdd(KERN_INFO "ca0132_pe_switch_set: val=%ld\n",
3434 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3435
3436 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3437 nid = OUT_EFFECT_START_NID;
3438 /* PE affects all out effects */
3439 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3440 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3441
3442 return ret;
3443}
3444
5aaca44d
IM		 3445/* Check if Mic1 is streaming, if so, stop streaming */
3446static int stop_mic1(struct hda_codec *codec)
3447{
3448 struct ca0132_spec *spec = codec->spec;
3449 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3450 AC_VERB_GET_CONV, 0);
3451 if (oldval != 0)
3452 snd_hda_codec_write(codec, spec->adcs[0], 0,
3453 AC_VERB_SET_CHANNEL_STREAMID,
3454 0);
3455 return oldval;
3456}
3457
3458/* Resume Mic1 streaming if it was stopped. */
3459static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3460{
3461 struct ca0132_spec *spec = codec->spec;
3462 /* Restore the previous stream and channel */
3463 if (oldval != 0)
3464 snd_hda_codec_write(codec, spec->adcs[0], 0,
3465 AC_VERB_SET_CHANNEL_STREAMID,
3466 oldval);
3467}
3468
3469/*
a7e76271 3470 * Turn on/off CrystalVoice
5aaca44d 3471 */
a7e76271
IM		 3472static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3473{
3474 struct ca0132_spec *spec = codec->spec;
3475 hda_nid_t nid;
3476 int i, ret = 0;
3477 unsigned int oldval;
3478
3479 snd_printdd(KERN_INFO "ca0132_cvoice_switch_set: val=%ld\n",
3480 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3481
3482 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3483 nid = IN_EFFECT_START_NID;
3484 /* CrystalVoice affects all in effects */
3485 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3486 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3487
3488 /* including VoiceFX */
3489 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3490
3491 /* set correct vipsource */
3492 oldval = stop_mic1(codec);
3493 ret |= ca0132_set_vipsource(codec, 1);
3494 resume_mic1(codec, oldval);
3495 return ret;
3496}
3497
5aaca44d
IM		 3498static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3499{
3500 struct ca0132_spec *spec = codec->spec;
3501 int ret = 0;
3502
3503 if (val) /* on */
3504 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3505 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3506 else /* off */
3507 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3508 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3509
3510 return ret;
3511}
3512
a7e76271
IM		 3513static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3514 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3515{
a7e76271
IM		 3516 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3517 hda_nid_t nid = get_amp_nid(kcontrol);
3518 hda_nid_t shared_nid = 0;
3519 bool effective;
3520 int ret = 0;
95c6e9cb 3521 struct ca0132_spec *spec = codec->spec;
a7e76271 3522 int auto_jack;
95c6e9cb 3523
a7e76271
IM		 3524 if (nid == VNID_HP_SEL) {
3525 auto_jack =
3526 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3527 if (!auto_jack)
3528 ca0132_select_out(codec);
3529 return 1;
3530 }
95c6e9cb 3531
a7e76271
IM		 3532 if (nid == VNID_AMIC1_SEL) {
3533 auto_jack =
3534 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3535 if (!auto_jack)
3536 ca0132_select_mic(codec);
3537 return 1;
3538 }
95c6e9cb 3539
a7e76271
IM		 3540 if (nid == VNID_HP_ASEL) {
3541 ca0132_select_out(codec);
3542 return 1;
3543 }
95c6e9cb 3544
a7e76271
IM		 3545 if (nid == VNID_AMIC1_ASEL) {
3546 ca0132_select_mic(codec);
3547 return 1;
95c6e9cb 3548 }
a7e76271
IM		 3549
3550 /* if effective conditions, then update hw immediately. */
3551 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3552 if (effective) {
3553 int dir = get_amp_direction(kcontrol);
3554 int ch = get_amp_channels(kcontrol);
3555 unsigned long pval;
3556
3557 mutex_lock(&codec->control_mutex);
3558 pval = kcontrol->private_value;
3559 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3560 0, dir);
3561 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3562 kcontrol->private_value = pval;
3563 mutex_unlock(&codec->control_mutex);
95c6e9cb 3564 }
95c6e9cb 3565
a7e76271 3566 return ret;
95c6e9cb 3567}
a7e76271 3568/* End of control change helpers. */
95c6e9cb 3569
a7e76271
IM		 3570static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3571 struct snd_ctl_elem_info *uinfo)
3572{
3573 unsigned int items = sizeof(ca0132_voicefx_presets)
3574 / sizeof(struct ct_voicefx_preset);
3575
3576 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3577 uinfo->count = 1;
3578 uinfo->value.enumerated.items = items;
3579 if (uinfo->value.enumerated.item >= items)
3580 uinfo->value.enumerated.item = items - 1;
3581 strcpy(uinfo->value.enumerated.name,
3582 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3583 return 0;
3584}
95c6e9cb 3585
a7e76271 3586static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3587 struct snd_ctl_elem_value *ucontrol)
3588{
3589 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3590 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3591
a7e76271 3592 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3593 return 0;
3594}
3595
a7e76271 3596static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3597 struct snd_ctl_elem_value *ucontrol)
3598{
3599 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3600 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3601 int i, err = 0;
3602 int sel = ucontrol->value.enumerated.item[0];
3603 unsigned int items = sizeof(ca0132_voicefx_presets)
3604 / sizeof(struct ct_voicefx_preset);
95c6e9cb 3605
a7e76271 3606 if (sel >= items)
95c6e9cb
IM		 3607 return 0;
3608
a7e76271
IM		 3609 snd_printdd(KERN_INFO "ca0132_voicefx_put: sel=%d, preset=%s\n",
3610 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3611
a7e76271
IM		 3612 /*
3613 * Idx 0 is default.
3614 * Default needs to qualify with CrystalVoice state.
3615 */
3616 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3617 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3618 ca0132_voicefx.reqs[i],
3619 ca0132_voicefx_presets[sel].vals[i]);
3620 if (err < 0)
3621 break;
3622 }
95c6e9cb 3623
a7e76271
IM		 3624 if (err >= 0) {
3625 spec->voicefx_val = sel;
3626 /* enable voice fx */
3627 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3628 }
95c6e9cb 3629
a7e76271 3630 return 1;
95c6e9cb
IM		 3631}
3632
a7e76271
IM		 3633static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3634 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3635{
3636 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3637 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3638 hda_nid_t nid = get_amp_nid(kcontrol);
3639 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3640 long *valp = ucontrol->value.integer.value;
3641
a7e76271
IM		 3642 /* vnode */
3643 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3644 if (ch & 1) {
3645 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3646 valp++;
3647 }
3648 if (ch & 2) {
3649 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3650 valp++;
3651 }
3652 return 0;
3653 }
3654
3655 /* effects, include PE and CrystalVoice */
3656 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3657 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3658 return 0;
3659 }
3660
3661 /* mic boost */
3662 if (nid == spec->input_pins[0]) {
3663 *valp = spec->cur_mic_boost;
3664 return 0;
3665 }
3666
95c6e9cb
IM		 3667 return 0;
3668}
3669
a7e76271
IM		 3670static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3671 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3672{
3673 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3674 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3675 hda_nid_t nid = get_amp_nid(kcontrol);
3676 int ch = get_amp_channels(kcontrol);
95c6e9cb 3677 long *valp = ucontrol->value.integer.value;
a7e76271 3678 int changed = 1;
95c6e9cb 3679
a7e76271
IM		 3680 snd_printdd(KERN_INFO "ca0132_switch_put: nid=0x%x, val=%ld\n",
3681 nid, *valp);
95c6e9cb
IM		 3682
3683 snd_hda_power_up(codec);
a7e76271
IM		 3684 /* vnode */
3685 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3686 if (ch & 1) {
3687 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3688 valp++;
3689 }
3690 if (ch & 2) {
3691 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3692 valp++;
3693 }
3694 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3695 goto exit;
3696 }
95c6e9cb 3697
a7e76271
IM		 3698 /* PE */
3699 if (nid == PLAY_ENHANCEMENT) {
3700 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3701 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3702 goto exit;
a7e76271 3703 }
95c6e9cb 3704
a7e76271
IM		 3705 /* CrystalVoice */
3706 if (nid == CRYSTAL_VOICE) {
3707 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3708 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3709 goto exit;
a7e76271 3710 }
95c6e9cb 3711
a7e76271
IM		 3712 /* out and in effects */
3713 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3714 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3715 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3716 changed = ca0132_effects_set(codec, nid, *valp);
3717 goto exit;
3718 }
3719
3720 /* mic boost */
3721 if (nid == spec->input_pins[0]) {
3722 spec->cur_mic_boost = *valp;
3723
3724 /* Mic boost does not apply to Digital Mic */
3725 if (spec->cur_mic_type != DIGITAL_MIC)
3726 changed = ca0132_mic_boost_set(codec, *valp);
3727 goto exit;
3728 }
95c6e9cb 3729
a7e76271 3730exit:
95c6e9cb 3731 snd_hda_power_down(codec);
a7e76271 3732 return changed;
95c6e9cb
IM		 3733}
3734
a7e76271
IM		 3735/*
3736 * Volume related
3737 */
3738static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3739 struct snd_ctl_elem_info *uinfo)
3740{
3741 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3742 struct ca0132_spec *spec = codec->spec;
3743 hda_nid_t nid = get_amp_nid(kcontrol);
3744 int ch = get_amp_channels(kcontrol);
3745 int dir = get_amp_direction(kcontrol);
3746 unsigned long pval;
3747 int err;
3748
3749 switch (nid) {
3750 case VNID_SPK:
3751 /* follow shared_out info */
3752 nid = spec->shared_out_nid;
3753 mutex_lock(&codec->control_mutex);
3754 pval = kcontrol->private_value;
3755 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3756 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3757 kcontrol->private_value = pval;
3758 mutex_unlock(&codec->control_mutex);
3759 break;
3760 case VNID_MIC:
3761 /* follow shared_mic info */
3762 nid = spec->shared_mic_nid;
3763 mutex_lock(&codec->control_mutex);
3764 pval = kcontrol->private_value;
3765 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3766 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3767 kcontrol->private_value = pval;
3768 mutex_unlock(&codec->control_mutex);
3769 break;
3770 default:
3771 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3772 }
3773 return err;
3774}
3775
3776static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3777 struct snd_ctl_elem_value *ucontrol)
3778{
3779 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3780 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3781 hda_nid_t nid = get_amp_nid(kcontrol);
3782 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3783 long *valp = ucontrol->value.integer.value;
3784
a7e76271
IM		 3785 /* store the left and right volume */
3786 if (ch & 1) {
3787 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3788 valp++;
3789 }
3790 if (ch & 2) {
3791 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3792 valp++;
3793 }
95c6e9cb
IM		 3794 return 0;
3795}
3796
a7e76271 3797static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3798 struct snd_ctl_elem_value *ucontrol)
3799{
3800 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3801 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3802 hda_nid_t nid = get_amp_nid(kcontrol);
3803 int ch = get_amp_channels(kcontrol);
95c6e9cb 3804 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3805 hda_nid_t shared_nid = 0;
3806 bool effective;
3807 int changed = 1;
3808
3809 /* store the left and right volume */
3810 if (ch & 1) {
3811 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3812 valp++;
3813 }
3814 if (ch & 2) {
3815 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3816 valp++;
3817 }
95c6e9cb 3818
a7e76271
IM		 3819 /* if effective conditions, then update hw immediately. */
3820 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3821 if (effective) {
3822 int dir = get_amp_direction(kcontrol);
3823 unsigned long pval;
3824
3825 snd_hda_power_up(codec);
3826 mutex_lock(&codec->control_mutex);
3827 pval = kcontrol->private_value;
3828 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3829 0, dir);
3830 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3831 kcontrol->private_value = pval;
3832 mutex_unlock(&codec->control_mutex);
3833 snd_hda_power_down(codec);
3834 }
95c6e9cb 3835
a7e76271 3836 return changed;
95c6e9cb
IM		 3837}
3838
a7e76271
IM		 3839static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3840 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3841{
a7e76271
IM		 3842 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3843 struct ca0132_spec *spec = codec->spec;
3844 hda_nid_t nid = get_amp_nid(kcontrol);
3845 int ch = get_amp_channels(kcontrol);
3846 int dir = get_amp_direction(kcontrol);
3847 unsigned long pval;
3848 int err;
3849
3850 switch (nid) {
3851 case VNID_SPK:
3852 /* follow shared_out tlv */
3853 nid = spec->shared_out_nid;
3854 mutex_lock(&codec->control_mutex);
3855 pval = kcontrol->private_value;
3856 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3857 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3858 kcontrol->private_value = pval;
3859 mutex_unlock(&codec->control_mutex);
3860 break;
3861 case VNID_MIC:
3862 /* follow shared_mic tlv */
3863 nid = spec->shared_mic_nid;
3864 mutex_lock(&codec->control_mutex);
3865 pval = kcontrol->private_value;
3866 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3867 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3868 kcontrol->private_value = pval;
3869 mutex_unlock(&codec->control_mutex);
3870 break;
3871 default:
3872 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3873 }
3874 return err;
95c6e9cb
IM		 3875}
3876
a7e76271
IM		 3877static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3878 const char *pfx, int dir)
95c6e9cb 3879{
a7e76271
IM		 3880 char namestr[44];
3881 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3882 struct snd_kcontrol_new knew =
a7e76271
IM		 3883 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3884 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3885 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3886}
3887
a7e76271 3888static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3889{
3890 struct snd_kcontrol_new knew =
a7e76271
IM		 3891 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3892 VOICEFX, 1, 0, HDA_INPUT);
3893 knew.info = ca0132_voicefx_info;
3894 knew.get = ca0132_voicefx_get;
3895 knew.put = ca0132_voicefx_put;
3896 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3897}
3898
a7e76271
IM		 3899/*
3900 * When changing Node IDs for Mixer Controls below, make sure to update
3901 * Node IDs in ca0132_config() as well.
3902 */
3903static struct snd_kcontrol_new ca0132_mixer[] = {
3904 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3905 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3906 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3907 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3908 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3909 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3910 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3911 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3912 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3913 0x12, 1, HDA_INPUT),
3914 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3915 VNID_HP_SEL, 1, HDA_OUTPUT),
3916 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3917 VNID_AMIC1_SEL, 1, HDA_INPUT),
3918 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3919 VNID_HP_ASEL, 1, HDA_OUTPUT),
3920 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3921 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3922 { } /* end */
3923};
3924
e90f29e4
IM		 3925static int ca0132_build_controls(struct hda_codec *codec)
3926{
3927 struct ca0132_spec *spec = codec->spec;
3928 int i, num_fx;
3929 int err = 0;
3930
3931 /* Add Mixer controls */
3932 for (i = 0; i < spec->num_mixers; i++) {
3933 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3934 if (err < 0)
3935 return err;
3936 }
3937
3938 /* Add in and out effects controls.
3939 * VoiceFX, PE and CrystalVoice are added separately.
3940 */
3941 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3942 for (i = 0; i < num_fx; i++) {
3943 err = add_fx_switch(codec, ca0132_effects[i].nid,
3944 ca0132_effects[i].name,
3945 ca0132_effects[i].direct);
3946 if (err < 0)
3947 return err;
3948 }
3949
3950 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3951 if (err < 0)
3952 return err;
3953
3954 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3955 if (err < 0)
3956 return err;
3957
3958 add_voicefx(codec);
3959
3960#ifdef ENABLE_TUNING_CONTROLS
3961 add_tuning_ctls(codec);
3962#endif
3963
3964 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3965 if (err < 0)
3966 return err;
3967
3968 if (spec->dig_out) {
3969 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3970 spec->dig_out);
3971 if (err < 0)
3972 return err;
3973 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
3974 if (err < 0)
3975 return err;
3976 /* spec->multiout.share_spdif = 1; */
3977 }
3978
3979 if (spec->dig_in) {
3980 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
3981 if (err < 0)
3982 return err;
3983 }
3984 return 0;
3985}
3986
a7e76271 3987/*
e90f29e4 3988 * PCM
a7e76271
IM		 3989 */
3990static struct hda_pcm_stream ca0132_pcm_analog_playback = {
3991 .substreams = 1,
3992 .channels_min = 2,
825315bc 3993 .channels_max = 6,
a7e76271 3994 .ops = {
a7e76271
IM		 3995 .prepare = ca0132_playback_pcm_prepare,
3996 .cleanup = ca0132_playback_pcm_cleanup
3997 },
3998};
3999
4000static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4001 .substreams = 1,
4002 .channels_min = 2,
4003 .channels_max = 2,
825315bc
IM		 4004 .ops = {
4005 .prepare = ca0132_capture_pcm_prepare,
4006 .cleanup = ca0132_capture_pcm_cleanup
4007 },
a7e76271
IM		 4008};
4009
4010static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4011 .substreams = 1,
4012 .channels_min = 2,
4013 .channels_max = 2,
4014 .ops = {
4015 .open = ca0132_dig_playback_pcm_open,
4016 .close = ca0132_dig_playback_pcm_close,
4017 .prepare = ca0132_dig_playback_pcm_prepare,
4018 .cleanup = ca0132_dig_playback_pcm_cleanup
4019 },
4020};
4021
4022static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4023 .substreams = 1,
4024 .channels_min = 2,
4025 .channels_max = 2,
4026};
4027
4028static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4029{
4030 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 4031 struct hda_pcm *info = spec->pcm_rec;
4032
4033 codec->pcm_info = info;
4034 codec->num_pcms = 0;
4035
4036 info->name = "CA0132 Analog";
4037 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4038 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4039 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4040 spec->multiout.max_channels;
4041 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4042 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271
IM		 4043 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4044 codec->num_pcms++;
4045
825315bc
IM		 4046 info++;
4047 info->name = "CA0132 Analog Mic-In2";
4048 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4049 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4050 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4051 codec->num_pcms++;
4052
4053 info++;
4054 info->name = "CA0132 What U Hear";
4055 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4056 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4057 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4058 codec->num_pcms++;
4059
a7e76271
IM		 4060 if (!spec->dig_out && !spec->dig_in)
4061 return 0;
4062
4063 info++;
4064 info->name = "CA0132 Digital";
4065 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4066 if (spec->dig_out) {
4067 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4068 ca0132_pcm_digital_playback;
4069 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4070 }
4071 if (spec->dig_in) {
4072 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4073 ca0132_pcm_digital_capture;
4074 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4075 }
4076 codec->num_pcms++;
95c6e9cb 4077
a7e76271 4078 return 0;
95c6e9cb
IM		 4079}
4080
441aa6a0
IM		 4081static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4082{
4083 if (pin) {
4084 snd_hda_codec_write(codec, pin, 0,
4085 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP);
4086 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4087 snd_hda_codec_write(codec, pin, 0,
4088 AC_VERB_SET_AMP_GAIN_MUTE,
4089 AMP_OUT_UNMUTE);
4090 }
4091 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4092 snd_hda_codec_write(codec, dac, 0,
4093 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4094}
4095
4096static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4097{
4098 if (pin) {
4099 snd_hda_codec_write(codec, pin, 0,
4100 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80);
4101 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4102 snd_hda_codec_write(codec, pin, 0,
4103 AC_VERB_SET_AMP_GAIN_MUTE,
4104 AMP_IN_UNMUTE(0));
4105 }
4106 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4107 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4108 AMP_IN_UNMUTE(0));
4109
4110 /* init to 0 dB and unmute. */
4111 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4112 HDA_AMP_VOLMASK, 0x5a);
4113 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4114 HDA_AMP_MUTE, 0);
4115 }
4116}
4117
a73d511c
IM		 4118static void ca0132_init_unsol(struct hda_codec *codec)
4119{
4120 snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP);
4121 snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1);
4122}
4123
5aaca44d
IM		 4124static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4125{
4126 unsigned int caps;
4127
4128 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4129 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4130 snd_hda_override_amp_caps(codec, nid, dir, caps);
4131}
4132
4133/*
4134 * Switch between Digital built-in mic and analog mic.
4135 */
4136static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4137{
4138 struct ca0132_spec *spec = codec->spec;
4139 unsigned int tmp;
4140 u8 val;
4141 unsigned int oldval;
4142
4143 snd_printdd(KERN_INFO "ca0132_set_dmic: enable=%d\n", enable);
4144
4145 oldval = stop_mic1(codec);
4146 ca0132_set_vipsource(codec, 0);
4147 if (enable) {
4148 /* set DMic input as 2-ch */
4149 tmp = FLOAT_TWO;
4150 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4151
4152 val = spec->dmic_ctl;
4153 val |= 0x80;
4154 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4155 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4156
4157 if (!(spec->dmic_ctl & 0x20))
4158 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4159 } else {
4160 /* set AMic input as mono */
4161 tmp = FLOAT_ONE;
4162 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4163
4164 val = spec->dmic_ctl;
4165 /* clear bit7 and bit5 to disable dmic */
4166 val &= 0x5f;
4167 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4168 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4169
4170 if (!(spec->dmic_ctl & 0x20))
4171 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4172 }
4173 ca0132_set_vipsource(codec, 1);
4174 resume_mic1(codec, oldval);
4175}
4176
4177/*
4178 * Initialization for Digital Mic.
4179 */
4180static void ca0132_init_dmic(struct hda_codec *codec)
4181{
4182 struct ca0132_spec *spec = codec->spec;
4183 u8 val;
4184
4185 /* Setup Digital Mic here, but don't enable.
4186 * Enable based on jack detect.
4187 */
4188
4189 /* MCLK uses MPIO1, set to enable.
4190 * Bit 2-0: MPIO select
4191 * Bit 3: set to disable
4192 * Bit 7-4: reserved
4193 */
4194 val = 0x01;
4195 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4196 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4197
4198 /* Data1 uses MPIO3. Data2 not use
4199 * Bit 2-0: Data1 MPIO select
4200 * Bit 3: set disable Data1
4201 * Bit 6-4: Data2 MPIO select
4202 * Bit 7: set disable Data2
4203 */
4204 val = 0x83;
4205 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4206 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4207
4208 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4209 * Bit 3-0: Channel mask
4210 * Bit 4: set for 48KHz, clear for 32KHz
4211 * Bit 5: mode
4212 * Bit 6: set to select Data2, clear for Data1
4213 * Bit 7: set to enable DMic, clear for AMic
4214 */
4215 val = 0x23;
4216 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4217 spec->dmic_ctl = val;
4218 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4219 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4220}
4221
4222/*
4223 * Initialization for Analog Mic 2
4224 */
4225static void ca0132_init_analog_mic2(struct hda_codec *codec)
4226{
4227 struct ca0132_spec *spec = codec->spec;
4228
4229 mutex_lock(&spec->chipio_mutex);
4230 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4231 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4232 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4233 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4234 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4235 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4236 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4237 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4238 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4239 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4240 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4241 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4242 mutex_unlock(&spec->chipio_mutex);
4243}
4244
4245static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4246{
4247 struct ca0132_spec *spec = codec->spec;
4248 int i;
4249 hda_nid_t nid;
4250
4251 snd_printdd(KERN_INFO "ca0132_refresh_widget_caps.\n");
4252 nid = codec->start_nid;
4253 for (i = 0; i < codec->num_nodes; i++, nid++)
4254 codec->wcaps[i] = snd_hda_param_read(codec, nid,
4255 AC_PAR_AUDIO_WIDGET_CAP);
4256
4257 for (i = 0; i < spec->multiout.num_dacs; i++)
4258 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4259
4260 for (i = 0; i < spec->num_outputs; i++)
4261 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4262
4263 for (i = 0; i < spec->num_inputs; i++) {
4264 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4265 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4266 }
4267}
4268
4269/*
4270 * Setup default parameters for DSP
4271 */
4272static void ca0132_setup_defaults(struct hda_codec *codec)
4273{
4274 unsigned int tmp;
4275 int num_fx;
4276 int idx, i;
4277
4278 if (!dspload_is_loaded(codec))
4279 return;
4280
4281 /* out, in effects + voicefx */
4282 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4283 for (idx = 0; idx < num_fx; idx++) {
4284 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4285 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4286 ca0132_effects[idx].reqs[i],
4287 ca0132_effects[idx].def_vals[i]);
4288 }
4289 }
4290
4291 /*remove DSP headroom*/
4292 tmp = FLOAT_ZERO;
4293 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4294
4295 /*set speaker EQ bypass attenuation*/
4296 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4297
4298 /* set AMic1 and AMic2 as mono mic */
4299 tmp = FLOAT_ONE;
4300 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4301 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4302
4303 /* set AMic1 as CrystalVoice input */
4304 tmp = FLOAT_ONE;
4305 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4306
4307 /* set WUH source */
4308 tmp = FLOAT_TWO;
4309 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4310}
4311
4312/*
4313 * Initialization of flags in chip
4314 */
4315static void ca0132_init_flags(struct hda_codec *codec)
4316{
4317 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4318 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4319 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4320 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4321 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4322 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4323}
4324
4325/*
4326 * Initialization of parameters in chip
4327 */
4328static void ca0132_init_params(struct hda_codec *codec)
4329{
4330 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4331 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4332}
95c6e9cb 4333
e90f29e4
IM		 4334static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4335{
4336 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4337 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4338 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4339 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4340 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4341 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4342
4343 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4344 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4345 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4346}
4347
4348static bool ca0132_download_dsp_images(struct hda_codec *codec)
4349{
4350 bool dsp_loaded = false;
4351 const struct dsp_image_seg *dsp_os_image;
4352
4353 if (request_firmware_cached(&fw_efx, EFX_FILE,
4354 codec->bus->card->dev) != 0)
4355 return false;
4356
4357 dsp_os_image = (struct dsp_image_seg *)(fw_efx->data);
4358 dspload_image(codec, dsp_os_image, 0, 0, true, 0);
4359 dsp_loaded = dspload_wait_loaded(codec);
4360
4361 return dsp_loaded;
4362}
4363
4364static void ca0132_download_dsp(struct hda_codec *codec)
4365{
4366 struct ca0132_spec *spec = codec->spec;
4367
4368 spec->dsp_state = DSP_DOWNLOAD_INIT;
4369
4370 if (spec->dsp_state == DSP_DOWNLOAD_INIT) {
4371 chipio_enable_clocks(codec);
4372 spec->dsp_state = DSP_DOWNLOADING;
4373 if (!ca0132_download_dsp_images(codec))
4374 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4375 else
4376 spec->dsp_state = DSP_DOWNLOADED;
4377 }
4378
4379 if (spec->dsp_state == DSP_DOWNLOADED)
4380 ca0132_set_dsp_msr(codec, true);
4381}
4382
e90f29e4
IM		 4383static void ca0132_process_dsp_response(struct hda_codec *codec)
4384{
4385 struct ca0132_spec *spec = codec->spec;
4386
4387 snd_printdd(KERN_INFO "ca0132_process_dsp_response\n");
4388 if (spec->wait_scp) {
4389 if (dspio_get_response_data(codec) >= 0)
4390 spec->wait_scp = 0;
4391 }
4392
4393 dspio_clear_response_queue(codec);
4394}
4395
4396static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res)
4397{
4398 snd_printdd(KERN_INFO "ca0132_unsol_event: 0x%x\n", res);
4399
4400
4401 if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) {
4402 ca0132_process_dsp_response(codec);
4403 } else {
4404 res = snd_hda_jack_get_action(codec,
4405 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f);
4406
4407 snd_printdd(KERN_INFO "snd_hda_jack_get_action: 0x%x\n", res);
4408
4409 switch (res) {
4410 case UNSOL_TAG_HP:
4411 ca0132_select_out(codec);
4412 snd_hda_jack_report_sync(codec);
4413 break;
4414 case UNSOL_TAG_AMIC1:
4415 ca0132_select_mic(codec);
4416 snd_hda_jack_report_sync(codec);
4417 break;
4418 default:
4419 break;
4420 }
4421 }
4422}
4423
5aaca44d
IM		 4424/*
4425 * Verbs tables.
4426 */
4427
4428/* Sends before DSP download. */
4429static struct hda_verb ca0132_base_init_verbs[] = {
4430 /*enable ct extension*/
4431 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4432 /*enable DSP node unsol, needed for DSP download*/
4433 {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
4434 {}
4435};
4436
4437/* Send at exit. */
4438static struct hda_verb ca0132_base_exit_verbs[] = {
4439 /*set afg to D3*/
4440 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4441 /*disable ct extension*/
4442 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4443 {}
4444};
4445
4446/* Other verbs tables. Sends after DSP download. */
4447static struct hda_verb ca0132_init_verbs0[] = {
4448 /* chip init verbs */
4449 {0x15, 0x70D, 0xF0},
4450 {0x15, 0x70E, 0xFE},
4451 {0x15, 0x707, 0x75},
4452 {0x15, 0x707, 0xD3},
4453 {0x15, 0x707, 0x09},
4454 {0x15, 0x707, 0x53},
4455 {0x15, 0x707, 0xD4},
4456 {0x15, 0x707, 0xEF},
4457 {0x15, 0x707, 0x75},
4458 {0x15, 0x707, 0xD3},
4459 {0x15, 0x707, 0x09},
4460 {0x15, 0x707, 0x02},
4461 {0x15, 0x707, 0x37},
4462 {0x15, 0x707, 0x78},
4463 {0x15, 0x53C, 0xCE},
4464 {0x15, 0x575, 0xC9},
4465 {0x15, 0x53D, 0xCE},
4466 {0x15, 0x5B7, 0xC9},
4467 {0x15, 0x70D, 0xE8},
4468 {0x15, 0x70E, 0xFE},
4469 {0x15, 0x707, 0x02},
4470 {0x15, 0x707, 0x68},
4471 {0x15, 0x707, 0x62},
4472 {0x15, 0x53A, 0xCE},
4473 {0x15, 0x546, 0xC9},
4474 {0x15, 0x53B, 0xCE},
4475 {0x15, 0x5E8, 0xC9},
4476 {0x15, 0x717, 0x0D},
4477 {0x15, 0x718, 0x20},
4478 {}
4479};
4480
4481static struct hda_verb ca0132_init_verbs1[] = {
4482 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4483 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4484 /* config EAPD */
4485 {0x0b, 0x78D, 0x00},
4486 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4487 /*{0x10, 0x78D, 0x02},*/
4488 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4489 {}
4490};
4491
95c6e9cb
IM		 4492static void ca0132_init_chip(struct hda_codec *codec)
4493{
4494 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4495 int num_fx;
4496 int i;
4497 unsigned int on;
95c6e9cb
IM		 4498
4499 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 4500
4501 spec->cur_out_type = SPEAKER_OUT;
4502 spec->cur_mic_type = DIGITAL_MIC;
4503 spec->cur_mic_boost = 0;
4504
4505 for (i = 0; i < VNODES_COUNT; i++) {
4506 spec->vnode_lvol[i] = 0x5a;
4507 spec->vnode_rvol[i] = 0x5a;
4508 spec->vnode_lswitch[i] = 0;
4509 spec->vnode_rswitch[i] = 0;
4510 }
4511
4512 /*
4513 * Default states for effects are in ca0132_effects[].
4514 */
4515 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4516 for (i = 0; i < num_fx; i++) {
4517 on = (unsigned int)ca0132_effects[i].reqs[0];
4518 spec->effects_switch[i] = on ? 1 : 0;
4519 }
4520
4521 spec->voicefx_val = 0;
4522 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4523 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4524
44f0c978
IM		 4525#ifdef ENABLE_TUNING_CONTROLS
4526 ca0132_init_tuning_defaults(codec);
4527#endif
95c6e9cb
IM		 4528}
4529
4530static void ca0132_exit_chip(struct hda_codec *codec)
4531{
4532 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 4533
4534 if (dspload_is_loaded(codec))
4535 dsp_reset(codec);
95c6e9cb
IM		 4536}
4537
4538static int ca0132_init(struct hda_codec *codec)
4539{
4540 struct ca0132_spec *spec = codec->spec;
4541 struct auto_pin_cfg *cfg = &spec->autocfg;
4542 int i;
4543
5aaca44d
IM		 4544 spec->dsp_state = DSP_DOWNLOAD_INIT;
4545 spec->curr_chip_addx = (unsigned int)INVALID_CHIP_ADDRESS;
4546
4547 snd_hda_power_up(codec);
4548
4549 ca0132_init_params(codec);
4550 ca0132_init_flags(codec);
4551 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf
IM		 4552#ifdef CONFIG_SND_HDA_DSP_LOADER
4553 ca0132_download_dsp(codec);
4554#endif
5aaca44d
IM		 4555 ca0132_refresh_widget_caps(codec);
4556 ca0132_setup_defaults(codec);
4557 ca0132_init_analog_mic2(codec);
4558 ca0132_init_dmic(codec);
4559
4560 for (i = 0; i < spec->num_outputs; i++)
4561 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4562
95c6e9cb
IM		 4563 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4564
4565 for (i = 0; i < spec->num_inputs; i++)
4566 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4567
4568 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4569
5aaca44d
IM		 4570 for (i = 0; i < spec->num_init_verbs; i++)
4571 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4572
a73d511c
IM		 4573 ca0132_init_unsol(codec);
4574
5aaca44d
IM		 4575 ca0132_select_out(codec);
4576 ca0132_select_mic(codec);
4577
a73d511c
IM		 4578 snd_hda_jack_report_sync(codec);
4579
5aaca44d 4580 snd_hda_power_down(codec);
95c6e9cb
IM		 4581
4582 return 0;
4583}
4584
95c6e9cb
IM		 4585static void ca0132_free(struct hda_codec *codec)
4586{
5aaca44d
IM		 4587 struct ca0132_spec *spec = codec->spec;
4588
4589 snd_hda_power_up(codec);
4590 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4591 ca0132_exit_chip(codec);
5aaca44d 4592 snd_hda_power_down(codec);
95c6e9cb
IM		 4593 kfree(codec->spec);
4594}
4595
4596static struct hda_codec_ops ca0132_patch_ops = {
4597 .build_controls = ca0132_build_controls,
4598 .build_pcms = ca0132_build_pcms,
4599 .init = ca0132_init,
4600 .free = ca0132_free,
a73d511c 4601 .unsol_event = ca0132_unsol_event,
95c6e9cb
IM		 4602};
4603
441aa6a0
IM		 4604static void ca0132_config(struct hda_codec *codec)
4605{
4606 struct ca0132_spec *spec = codec->spec;
4607 struct auto_pin_cfg *cfg = &spec->autocfg;
4608
4609 spec->dacs[0] = 0x2;
4610 spec->dacs[1] = 0x3;
4611 spec->dacs[2] = 0x4;
4612
4613 spec->multiout.dac_nids = spec->dacs;
4614 spec->multiout.num_dacs = 3;
4615 spec->multiout.max_channels = 2;
4616
4617 spec->num_outputs = 2;
4618 spec->out_pins[0] = 0x0b; /* speaker out */
4619 spec->out_pins[1] = 0x10; /* headphone out */
4620 spec->shared_out_nid = 0x2;
4621
4622 spec->num_inputs = 3;
4623 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4624 spec->adcs[1] = 0x8; /* analog mic2 */
4625 spec->adcs[2] = 0xa; /* what u hear */
4626 spec->shared_mic_nid = 0x7;
4627
4628 spec->input_pins[0] = 0x12;
4629 spec->input_pins[1] = 0x11;
4630 spec->input_pins[2] = 0x13;
4631
4632 /* SPDIF I/O */
4633 spec->dig_out = 0x05;
4634 spec->multiout.dig_out_nid = spec->dig_out;
4635 cfg->dig_out_pins[0] = 0x0c;
4636 cfg->dig_outs = 1;
4637 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4638 spec->dig_in = 0x09;
4639 cfg->dig_in_pin = 0x0e;
4640 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4641}
4642
95c6e9cb
IM		 4643static int patch_ca0132(struct hda_codec *codec)
4644{
4645 struct ca0132_spec *spec;
a73d511c 4646 int err;
95c6e9cb
IM		 4647
4648 snd_printdd("patch_ca0132\n");
4649
4650 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4651 if (!spec)
4652 return -ENOMEM;
4653 codec->spec = spec;
4654
a7e76271
IM		 4655 spec->num_mixers = 1;
4656 spec->mixers[0] = ca0132_mixer;
4657
5aaca44d
IM		 4658 spec->base_init_verbs = ca0132_base_init_verbs;
4659 spec->base_exit_verbs = ca0132_base_exit_verbs;
4660 spec->init_verbs[0] = ca0132_init_verbs0;
4661 spec->init_verbs[1] = ca0132_init_verbs1;
4662 spec->num_init_verbs = 2;
4663
95c6e9cb
IM		 4664 ca0132_init_chip(codec);
4665
4666 ca0132_config(codec);
4667
a73d511c
IM		 4668 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4669 if (err < 0)
4670 return err;
4671
95c6e9cb
IM		 4672 codec->patch_ops = ca0132_patch_ops;
4673
4674 return 0;
4675}
4676
4677/*
4678 * patch entries
4679 */
4680static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4681 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4682 {} /* terminator */
4683};
4684
4685MODULE_ALIAS("snd-hda-codec-id:11020011");
4686
4687MODULE_LICENSE("GPL");
4688MODULE_DESCRIPTION("Creative CA0132, CA0132 HD-audio codec");
4689
4690static struct hda_codec_preset_list ca0132_list = {
4691 .preset = snd_hda_preset_ca0132,
4692 .owner = THIS_MODULE,
4693};
4694
4695static int __init patch_ca0132_init(void)
4696{
4697 return snd_hda_add_codec_preset(&ca0132_list);
4698}
4699
4700static void __exit patch_ca0132_exit(void)
4701{
c3b4eea2 4702 release_cached_firmware();
95c6e9cb
IM		 4703 snd_hda_delete_codec_preset(&ca0132_list);
4704}
4705
4706module_init(patch_ca0132_init)
4707module_exit(patch_ca0132_exit)
Linux 6.x block layer and io_uring tree(s)