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ALSA: hda/ca0132 - Add AE-5 specific controls
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb 34#include <sound/core.h>
be57bfff 35#include <sound/hda_codec.h>
95c6e9cb 36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
38ba69ff 52#define FLOAT_THREE 0x40400000
7cb9d94c 53#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 54#define FLOAT_MINUS_5 0xc0a00000
55
ef6b2ead
IM		 56#define UNSOL_TAG_DSP 0x16
57
4aa3bb0c
IM		 58#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
ef6b2ead
IM		 66#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 68
95c6e9cb
IM		 69#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
4aa3bb0c
IM		 72#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
01ef7dbf 83#define EFX_FILE "ctefx.bin"
7a928186 84#define DESKTOP_EFX_FILE "ctefx-desktop.bin"
8a19bcee 85#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 86
24f3cede 87#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 88MODULE_FIRMWARE(EFX_FILE);
7a928186 89MODULE_FIRMWARE(DESKTOP_EFX_FILE);
8a19bcee 90MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 91#endif
01ef7dbf 92
3a03f83b 93static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 94
7cb9d94c 95#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 96enum {
97 SPEAKER_OUT,
7cb9d94c
CM		 98 HEADPHONE_OUT,
99 SURROUND_OUT
ef6b2ead
IM		 100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
7cb9d94c 107/* Strings for Input Source Enum Control */
3a03f83b 108static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
ef6b2ead
IM		 116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
7cb9d94c
CM		 149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
212de2e7
CM		 155 MIC_BOOST_ENUM,
156 AE5_HEADPHONE_GAIN_ENUM,
157 AE5_SOUND_FILTER_ENUM
ef6b2ead
IM		 158#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
159};
160
161/* Effects values size*/
162#define EFFECT_VALS_MAX_COUNT 12
163
47cdf76e
CM		 164/*
165 * Default values for the effect slider controls, they are in order of their
166 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
167 * X-bass.
168 */
169static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
170/* Amount of effect level sliders for ca0132_alt controls. */
171#define EFFECT_LEVEL_SLIDERS 5
172
e8412ca4
DR		 173/* Latency introduced by DSP blocks in milliseconds. */
174#define DSP_CAPTURE_INIT_LATENCY 0
175#define DSP_CRYSTAL_VOICE_LATENCY 124
176#define DSP_PLAYBACK_INIT_LATENCY 13
177#define DSP_PLAY_ENHANCEMENT_LATENCY 30
178#define DSP_SPEAKER_OUT_LATENCY 7
179
ef6b2ead 180struct ct_effect {
975cc02a 181 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 182 hda_nid_t nid;
183 int mid; /*effect module ID*/
184 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
185 int direct; /* 0:output; 1:input*/
186 int params; /* number of default non-on/off params */
187 /*effect default values, 1st is on/off. */
188 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
189};
190
191#define EFX_DIR_OUT 0
192#define EFX_DIR_IN 1
193
862154bb 194static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 195 { .name = "Surround",
196 .nid = SURROUND,
197 .mid = 0x96,
198 .reqs = {0, 1},
199 .direct = EFX_DIR_OUT,
200 .params = 1,
201 .def_vals = {0x3F800000, 0x3F2B851F}
202 },
203 { .name = "Crystalizer",
204 .nid = CRYSTALIZER,
205 .mid = 0x96,
206 .reqs = {7, 8},
207 .direct = EFX_DIR_OUT,
208 .params = 1,
209 .def_vals = {0x3F800000, 0x3F266666}
210 },
211 { .name = "Dialog Plus",
212 .nid = DIALOG_PLUS,
213 .mid = 0x96,
214 .reqs = {2, 3},
215 .direct = EFX_DIR_OUT,
216 .params = 1,
217 .def_vals = {0x00000000, 0x3F000000}
218 },
219 { .name = "Smart Volume",
220 .nid = SMART_VOLUME,
221 .mid = 0x96,
222 .reqs = {4, 5, 6},
223 .direct = EFX_DIR_OUT,
224 .params = 2,
225 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
226 },
227 { .name = "X-Bass",
228 .nid = X_BASS,
229 .mid = 0x96,
230 .reqs = {24, 23, 25},
231 .direct = EFX_DIR_OUT,
232 .params = 2,
233 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
234 },
235 { .name = "Equalizer",
236 .nid = EQUALIZER,
237 .mid = 0x96,
238 .reqs = {9, 10, 11, 12, 13, 14,
239 15, 16, 17, 18, 19, 20},
240 .direct = EFX_DIR_OUT,
241 .params = 11,
242 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
243 0x00000000, 0x00000000, 0x00000000, 0x00000000,
244 0x00000000, 0x00000000, 0x00000000, 0x00000000}
245 },
246 { .name = "Echo Cancellation",
247 .nid = ECHO_CANCELLATION,
248 .mid = 0x95,
249 .reqs = {0, 1, 2, 3},
250 .direct = EFX_DIR_IN,
251 .params = 3,
252 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
253 },
254 { .name = "Voice Focus",
255 .nid = VOICE_FOCUS,
256 .mid = 0x95,
257 .reqs = {6, 7, 8, 9},
258 .direct = EFX_DIR_IN,
259 .params = 3,
260 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
261 },
262 { .name = "Mic SVM",
263 .nid = MIC_SVM,
264 .mid = 0x95,
265 .reqs = {44, 45},
266 .direct = EFX_DIR_IN,
267 .params = 1,
268 .def_vals = {0x00000000, 0x3F3D70A4}
269 },
270 { .name = "Noise Reduction",
271 .nid = NOISE_REDUCTION,
272 .mid = 0x95,
273 .reqs = {4, 5},
274 .direct = EFX_DIR_IN,
275 .params = 1,
276 .def_vals = {0x3F800000, 0x3F000000}
277 },
278 { .name = "VoiceFX",
279 .nid = VOICEFX,
280 .mid = 0x95,
281 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
282 .direct = EFX_DIR_IN,
283 .params = 8,
284 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
285 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
286 0x00000000}
287 }
288};
289
290/* Tuning controls */
291#ifdef ENABLE_TUNING_CONTROLS
292
293enum {
294#define TUNING_CTL_START_NID 0xC0
295 WEDGE_ANGLE = TUNING_CTL_START_NID,
296 SVM_LEVEL,
297 EQUALIZER_BAND_0,
298 EQUALIZER_BAND_1,
299 EQUALIZER_BAND_2,
300 EQUALIZER_BAND_3,
301 EQUALIZER_BAND_4,
302 EQUALIZER_BAND_5,
303 EQUALIZER_BAND_6,
304 EQUALIZER_BAND_7,
305 EQUALIZER_BAND_8,
306 EQUALIZER_BAND_9,
307 TUNING_CTL_END_NID
308#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
309};
310
311struct ct_tuning_ctl {
975cc02a 312 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 313 hda_nid_t parent_nid;
314 hda_nid_t nid;
315 int mid; /*effect module ID*/
316 int req; /*effect module request*/
317 int direct; /* 0:output; 1:input*/
318 unsigned int def_val;/*effect default values*/
319};
320
862154bb 321static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 322 { .name = "Wedge Angle",
323 .parent_nid = VOICE_FOCUS,
324 .nid = WEDGE_ANGLE,
325 .mid = 0x95,
326 .req = 8,
327 .direct = EFX_DIR_IN,
328 .def_val = 0x41F00000
329 },
330 { .name = "SVM Level",
331 .parent_nid = MIC_SVM,
332 .nid = SVM_LEVEL,
333 .mid = 0x95,
334 .req = 45,
335 .direct = EFX_DIR_IN,
336 .def_val = 0x3F3D70A4
337 },
338 { .name = "EQ Band0",
339 .parent_nid = EQUALIZER,
340 .nid = EQUALIZER_BAND_0,
341 .mid = 0x96,
342 .req = 11,
343 .direct = EFX_DIR_OUT,
344 .def_val = 0x00000000
345 },
346 { .name = "EQ Band1",
347 .parent_nid = EQUALIZER,
348 .nid = EQUALIZER_BAND_1,
349 .mid = 0x96,
350 .req = 12,
351 .direct = EFX_DIR_OUT,
352 .def_val = 0x00000000
353 },
354 { .name = "EQ Band2",
355 .parent_nid = EQUALIZER,
356 .nid = EQUALIZER_BAND_2,
357 .mid = 0x96,
358 .req = 13,
359 .direct = EFX_DIR_OUT,
360 .def_val = 0x00000000
361 },
362 { .name = "EQ Band3",
363 .parent_nid = EQUALIZER,
364 .nid = EQUALIZER_BAND_3,
365 .mid = 0x96,
366 .req = 14,
367 .direct = EFX_DIR_OUT,
368 .def_val = 0x00000000
369 },
370 { .name = "EQ Band4",
371 .parent_nid = EQUALIZER,
372 .nid = EQUALIZER_BAND_4,
373 .mid = 0x96,
374 .req = 15,
375 .direct = EFX_DIR_OUT,
376 .def_val = 0x00000000
377 },
378 { .name = "EQ Band5",
379 .parent_nid = EQUALIZER,
380 .nid = EQUALIZER_BAND_5,
381 .mid = 0x96,
382 .req = 16,
383 .direct = EFX_DIR_OUT,
384 .def_val = 0x00000000
385 },
386 { .name = "EQ Band6",
387 .parent_nid = EQUALIZER,
388 .nid = EQUALIZER_BAND_6,
389 .mid = 0x96,
390 .req = 17,
391 .direct = EFX_DIR_OUT,
392 .def_val = 0x00000000
393 },
394 { .name = "EQ Band7",
395 .parent_nid = EQUALIZER,
396 .nid = EQUALIZER_BAND_7,
397 .mid = 0x96,
398 .req = 18,
399 .direct = EFX_DIR_OUT,
400 .def_val = 0x00000000
401 },
402 { .name = "EQ Band8",
403 .parent_nid = EQUALIZER,
404 .nid = EQUALIZER_BAND_8,
405 .mid = 0x96,
406 .req = 19,
407 .direct = EFX_DIR_OUT,
408 .def_val = 0x00000000
409 },
410 { .name = "EQ Band9",
411 .parent_nid = EQUALIZER,
412 .nid = EQUALIZER_BAND_9,
413 .mid = 0x96,
414 .req = 20,
415 .direct = EFX_DIR_OUT,
416 .def_val = 0x00000000
417 }
418};
419#endif
420
421/* Voice FX Presets */
422#define VOICEFX_MAX_PARAM_COUNT 9
423
424struct ct_voicefx {
425 char *name;
426 hda_nid_t nid;
427 int mid;
428 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
429};
430
431struct ct_voicefx_preset {
432 char *name; /*preset name*/
433 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
434};
435
862154bb 436static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 437 .name = "VoiceFX Capture Switch",
438 .nid = VOICEFX,
439 .mid = 0x95,
440 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
441};
442
862154bb 443static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 444 { .name = "Neutral",
445 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
446 0x44FA0000, 0x3F800000, 0x3F800000,
447 0x3F800000, 0x00000000, 0x00000000 }
448 },
449 { .name = "Female2Male",
450 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
451 0x44FA0000, 0x3F19999A, 0x3F866666,
452 0x3F800000, 0x00000000, 0x00000000 }
453 },
454 { .name = "Male2Female",
455 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
456 0x450AC000, 0x4017AE14, 0x3F6B851F,
457 0x3F800000, 0x00000000, 0x00000000 }
458 },
459 { .name = "ScrappyKid",
460 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
461 0x44FA0000, 0x40400000, 0x3F28F5C3,
462 0x3F800000, 0x00000000, 0x00000000 }
463 },
464 { .name = "Elderly",
465 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
466 0x44E10000, 0x3FB33333, 0x3FB9999A,
467 0x3F800000, 0x3E3A2E43, 0x00000000 }
468 },
469 { .name = "Orc",
470 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
471 0x45098000, 0x3F266666, 0x3FC00000,
472 0x3F800000, 0x00000000, 0x00000000 }
473 },
474 { .name = "Elf",
475 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
476 0x45193000, 0x3F8E147B, 0x3F75C28F,
477 0x3F800000, 0x00000000, 0x00000000 }
478 },
479 { .name = "Dwarf",
480 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
481 0x45007000, 0x3F451EB8, 0x3F7851EC,
482 0x3F800000, 0x00000000, 0x00000000 }
483 },
484 { .name = "AlienBrute",
485 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
486 0x451F6000, 0x3F266666, 0x3FA7D945,
487 0x3F800000, 0x3CF5C28F, 0x00000000 }
488 },
489 { .name = "Robot",
490 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
491 0x44FA0000, 0x3FB2718B, 0x3F800000,
492 0xBC07010E, 0x00000000, 0x00000000 }
493 },
494 { .name = "Marine",
495 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
496 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
497 0x3F0A3D71, 0x00000000, 0x00000000 }
498 },
499 { .name = "Emo",
500 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
501 0x44FA0000, 0x3F800000, 0x3F800000,
502 0x3E4CCCCD, 0x00000000, 0x00000000 }
503 },
504 { .name = "DeepVoice",
505 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
506 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
507 0x3F800000, 0x00000000, 0x00000000 }
508 },
509 { .name = "Munchkin",
510 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
511 0x44FA0000, 0x3F800000, 0x3F1A043C,
512 0x3F800000, 0x00000000, 0x00000000 }
513 }
514};
515
47cdf76e
CM		 516/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
517
518#define EQ_PRESET_MAX_PARAM_COUNT 11
519
520struct ct_eq {
521 char *name;
522 hda_nid_t nid;
523 int mid;
524 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
525};
526
527struct ct_eq_preset {
528 char *name; /*preset name*/
529 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
530};
531
862154bb 532static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 533 .name = "FX: Equalizer Preset Switch",
534 .nid = EQ_PRESET_ENUM,
535 .mid = 0x96,
536 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
537};
538
539
862154bb 540static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 541 { .name = "Flat",
542 .vals = { 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000, 0x00000000,
544 0x00000000, 0x00000000, 0x00000000,
545 0x00000000, 0x00000000 }
546 },
547 { .name = "Acoustic",
548 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
549 0x40000000, 0x00000000, 0x00000000,
550 0x00000000, 0x00000000, 0x40000000,
551 0x40000000, 0x40000000 }
552 },
553 { .name = "Classical",
554 .vals = { 0x00000000, 0x00000000, 0x40C00000,
555 0x40C00000, 0x40466666, 0x00000000,
556 0x00000000, 0x00000000, 0x00000000,
557 0x40466666, 0x40466666 }
558 },
559 { .name = "Country",
560 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
561 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
562 0x00000000, 0x00000000, 0x40000000,
563 0x40466666, 0x40800000 }
564 },
565 { .name = "Dance",
566 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
567 0x40466666, 0x40866666, 0xBF99999A,
568 0xBF99999A, 0x00000000, 0x00000000,
569 0x40800000, 0x40800000 }
570 },
571 { .name = "Jazz",
572 .vals = { 0x00000000, 0x00000000, 0x00000000,
573 0x3F8CCCCD, 0x40800000, 0x40800000,
574 0x40800000, 0x00000000, 0x3F8CCCCD,
575 0x40466666, 0x40466666 }
576 },
577 { .name = "New Age",
578 .vals = { 0x00000000, 0x00000000, 0x40000000,
579 0x40000000, 0x00000000, 0x00000000,
580 0x00000000, 0x3F8CCCCD, 0x40000000,
581 0x40000000, 0x40000000 }
582 },
583 { .name = "Pop",
584 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
585 0x40000000, 0x40000000, 0x00000000,
586 0xBF99999A, 0xBF99999A, 0x00000000,
587 0x40466666, 0x40C00000 }
588 },
589 { .name = "Rock",
590 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
591 0x3F8CCCCD, 0x40000000, 0xBF99999A,
592 0xBF99999A, 0x00000000, 0x00000000,
593 0x40800000, 0x40800000 }
594 },
595 { .name = "Vocal",
596 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
597 0xBF99999A, 0x00000000, 0x40466666,
598 0x40800000, 0x40466666, 0x00000000,
599 0x00000000, 0x3F8CCCCD }
600 }
601};
602
7cb9d94c
CM		 603/* DSP command sequences for ca0132_alt_select_out */
604#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
605struct ca0132_alt_out_set {
606 char *name; /*preset name*/
607 unsigned char commands;
608 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
609 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
610 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
611};
612
613static const struct ca0132_alt_out_set alt_out_presets[] = {
614 { .name = "Line Out",
615 .commands = 7,
616 .mids = { 0x96, 0x96, 0x96, 0x8F,
617 0x96, 0x96, 0x96 },
618 .reqs = { 0x19, 0x17, 0x18, 0x01,
619 0x1F, 0x15, 0x3A },
620 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
621 0x00000000, 0x00000000, 0x00000000,
622 0x00000000 }
623 },
624 { .name = "Headphone",
625 .commands = 7,
626 .mids = { 0x96, 0x96, 0x96, 0x8F,
627 0x96, 0x96, 0x96 },
628 .reqs = { 0x19, 0x17, 0x18, 0x01,
629 0x1F, 0x15, 0x3A },
630 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
631 0x00000000, 0x00000000, 0x00000000,
632 0x00000000 }
633 },
634 { .name = "Surround",
635 .commands = 8,
636 .mids = { 0x96, 0x8F, 0x96, 0x96,
637 0x96, 0x96, 0x96, 0x96 },
638 .reqs = { 0x18, 0x01, 0x1F, 0x15,
639 0x3A, 0x1A, 0x1B, 0x1C },
640 .vals = { 0x00000000, 0x00000000, 0x00000000,
641 0x00000000, 0x00000000, 0x00000000,
642 0x00000000, 0x00000000 }
643 }
644};
645
017310fb
CM		 646/*
647 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
648 * and I don't know what the third req is, but it's always zero. I assume it's
649 * some sort of update or set command to tell the DSP there's new volume info.
650 */
651#define DSP_VOL_OUT 0
652#define DSP_VOL_IN 1
653
654struct ct_dsp_volume_ctl {
655 hda_nid_t vnid;
656 int mid; /* module ID*/
657 unsigned int reqs[3]; /* scp req ID */
658};
659
862154bb 660static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 661 { .vnid = VNID_SPK,
662 .mid = 0x32,
663 .reqs = {3, 4, 2}
664 },
665 { .vnid = VNID_MIC,
666 .mid = 0x37,
667 .reqs = {2, 3, 1}
668 }
669};
670
2283c85b
CM		 671/* Values for ca0113_mmio_command_set for selecting output. */
672#define AE5_CA0113_OUT_SET_COMMANDS 6
673struct ae5_ca0113_output_set {
674 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS];
675 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS];
676 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS];
677};
678
679static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = {
680 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
681 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
682 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
683 },
684 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
685 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
686 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 }
687 },
688 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
689 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
690 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
691 }
692};
693
212de2e7
CM		 694/* ae5 ca0113 command sequences to set headphone gain levels. */
695#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
696struct ae5_headphone_gain_set {
697 char *name;
698 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
699};
700
701static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
702 { .name = "Low (16-31",
703 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
704 },
705 { .name = "Medium (32-149",
706 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
707 },
708 { .name = "High (150-600",
709 .vals = { 0xff, 0xff, 0xff, 0x7f }
710 }
711};
712
713struct ae5_filter_set {
714 char *name;
715 unsigned int val;
716};
717
718static const struct ae5_filter_set ae5_filter_presets[] = {
719 { .name = "Slow Roll Off",
720 .val = 0xa0
721 },
722 { .name = "Minimum Phase",
723 .val = 0xc0
724 },
725 { .name = "Fast Roll Off",
726 .val = 0x80
727 }
728};
729
95c6e9cb
IM		 730enum hda_cmd_vendor_io {
731 /* for DspIO node */
732 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
733 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
734
735 VENDOR_DSPIO_STATUS = 0xF01,
736 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
737 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
738 VENDOR_DSPIO_DSP_INIT = 0x703,
739 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
740 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
741
742 /* for ChipIO node */
743 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
744 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
745 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
746 VENDOR_CHIPIO_DATA_LOW = 0x300,
747 VENDOR_CHIPIO_DATA_HIGH = 0x400,
748
bf85a91c
CM		 749 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
750 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
751
95c6e9cb
IM		 752 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
753 VENDOR_CHIPIO_STATUS = 0xF01,
754 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
755 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
756
4aa3bb0c
IM		 757 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
758 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
bf85a91c
CM		 759 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
760 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
761 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
4aa3bb0c 762
95c6e9cb 763 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 764 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 765
766 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
767 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
768 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
769 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
770 VENDOR_CHIPIO_FLAG_SET = 0x70F,
771 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 772 VENDOR_CHIPIO_PARAM_SET = 0x710,
773 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 774
775 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
776 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
777 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
778 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
779
4aa3bb0c
IM		 780 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
781 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
782 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
783 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
784
785 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
786 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
787 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
788 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
789 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
790 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
791
792 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 793};
794
795/*
796 * Control flag IDs
797 */
798enum control_flag_id {
799 /* Connection manager stream setup is bypassed/enabled */
800 CONTROL_FLAG_C_MGR = 0,
801 /* DSP DMA is bypassed/enabled */
802 CONTROL_FLAG_DMA = 1,
803 /* 8051 'idle' mode is disabled/enabled */
804 CONTROL_FLAG_IDLE_ENABLE = 2,
805 /* Tracker for the SPDIF-in path is bypassed/enabled */
806 CONTROL_FLAG_TRACKER = 3,
807 /* DigitalOut to Spdif2Out connection is disabled/enabled */
808 CONTROL_FLAG_SPDIF2OUT = 4,
809 /* Digital Microphone is disabled/enabled */
810 CONTROL_FLAG_DMIC = 5,
811 /* ADC_B rate is 48 kHz/96 kHz */
812 CONTROL_FLAG_ADC_B_96KHZ = 6,
813 /* ADC_C rate is 48 kHz/96 kHz */
814 CONTROL_FLAG_ADC_C_96KHZ = 7,
815 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
816 CONTROL_FLAG_DAC_96KHZ = 8,
817 /* DSP rate is 48 kHz/96 kHz */
818 CONTROL_FLAG_DSP_96KHZ = 9,
819 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
820 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
821 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
822 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
823 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
824 CONTROL_FLAG_DECODE_LOOP = 12,
825 /* De-emphasis filter on DAC-1 disabled/enabled */
826 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
827 /* De-emphasis filter on DAC-2 disabled/enabled */
828 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
829 /* De-emphasis filter on DAC-3 disabled/enabled */
830 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
831 /* High-pass filter on ADC_B disabled/enabled */
832 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
833 /* High-pass filter on ADC_C disabled/enabled */
834 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
835 /* Common mode on Port_A disabled/enabled */
836 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
837 /* Common mode on Port_D disabled/enabled */
838 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
839 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
840 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
841 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 842 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 843 /* ASI rate is 48kHz/96kHz */
844 CONTROL_FLAG_ASI_96KHZ = 22,
845 /* DAC power settings able to control attached ports no/yes */
846 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
847 /* Clock Stop OK reporting is disabled/enabled */
848 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
849 /* Number of control flags */
850 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
851};
852
853/*
854 * Control parameter IDs
855 */
4aa3bb0c 856enum control_param_id {
ef6b2ead
IM		 857 /* 0: None, 1: Mic1In*/
858 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 859 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
860 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 861 /* Port A output stage gain setting to use when 16 Ohm output
862 * impedance is selected*/
863 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
864 /* Port D output stage gain setting to use when 16 Ohm output
865 * impedance is selected*/
866 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb 867
bf85a91c
CM		 868 /*
869 * This control param name was found in the 8051 memory, and makes
870 * sense given the fact the AE-5 uses it and has the ASI flag set.
871 */
872 CONTROL_PARAM_ASI = 23,
873
95c6e9cb
IM		 874 /* Stream Control */
875
876 /* Select stream with the given ID */
877 CONTROL_PARAM_STREAM_ID = 24,
878 /* Source connection point for the selected stream */
879 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
880 /* Destination connection point for the selected stream */
881 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
882 /* Number of audio channels in the selected stream */
883 CONTROL_PARAM_STREAMS_CHANNELS = 27,
884 /*Enable control for the selected stream */
885 CONTROL_PARAM_STREAM_CONTROL = 28,
886
887 /* Connection Point Control */
888
889 /* Select connection point with the given ID */
890 CONTROL_PARAM_CONN_POINT_ID = 29,
891 /* Connection point sample rate */
892 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
893
894 /* Node Control */
895
896 /* Select HDA node with the given ID */
897 CONTROL_PARAM_NODE_ID = 31
898};
899
900/*
901 * Dsp Io Status codes
902 */
903enum hda_vendor_status_dspio {
904 /* Success */
905 VENDOR_STATUS_DSPIO_OK = 0x00,
906 /* Busy, unable to accept new command, the host must retry */
907 VENDOR_STATUS_DSPIO_BUSY = 0x01,
908 /* SCP command queue is full */
909 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
910 /* SCP response queue is empty */
911 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
912};
913
914/*
915 * Chip Io Status codes
916 */
917enum hda_vendor_status_chipio {
918 /* Success */
919 VENDOR_STATUS_CHIPIO_OK = 0x00,
920 /* Busy, unable to accept new command, the host must retry */
921 VENDOR_STATUS_CHIPIO_BUSY = 0x01
922};
923
924/*
925 * CA0132 sample rate
926 */
927enum ca0132_sample_rate {
928 SR_6_000 = 0x00,
929 SR_8_000 = 0x01,
930 SR_9_600 = 0x02,
931 SR_11_025 = 0x03,
932 SR_16_000 = 0x04,
933 SR_22_050 = 0x05,
934 SR_24_000 = 0x06,
935 SR_32_000 = 0x07,
936 SR_44_100 = 0x08,
937 SR_48_000 = 0x09,
938 SR_88_200 = 0x0A,
939 SR_96_000 = 0x0B,
940 SR_144_000 = 0x0C,
941 SR_176_400 = 0x0D,
942 SR_192_000 = 0x0E,
943 SR_384_000 = 0x0F,
944
945 SR_COUNT = 0x10,
946
947 SR_RATE_UNKNOWN = 0x1F
948};
949
01ef7dbf
IM		 950enum dsp_download_state {
951 DSP_DOWNLOAD_FAILED = -1,
952 DSP_DOWNLOAD_INIT = 0,
953 DSP_DOWNLOADING = 1,
954 DSP_DOWNLOADED = 2
955};
956
01ef7dbf
IM		 957/* retrieve parameters from hda format */
958#define get_hdafmt_chs(fmt) (fmt & 0xf)
959#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
960#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
961#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
962
963/*
964 * CA0132 specific
965 */
966
967struct ca0132_spec {
b0eaa072 968 const struct snd_kcontrol_new *mixers[5];
a7e76271 969 unsigned int num_mixers;
5aaca44d
IM		 970 const struct hda_verb *base_init_verbs;
971 const struct hda_verb *base_exit_verbs;
d5c016b5 972 const struct hda_verb *chip_init_verbs;
e42c7c73 973 const struct hda_verb *desktop_init_verbs;
d5c016b5 974 struct hda_verb *spec_init_verbs;
01ef7dbf 975 struct auto_pin_cfg autocfg;
5aaca44d
IM		 976
977 /* Nodes configurations */
01ef7dbf
IM		 978 struct hda_multi_out multiout;
979 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
980 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 981 unsigned int num_outputs;
01ef7dbf
IM		 982 hda_nid_t input_pins[AUTO_PIN_LAST];
983 hda_nid_t adcs[AUTO_PIN_LAST];
984 hda_nid_t dig_out;
985 hda_nid_t dig_in;
986 unsigned int num_inputs;
a7e76271
IM		 987 hda_nid_t shared_mic_nid;
988 hda_nid_t shared_out_nid;
d5c016b5 989 hda_nid_t unsol_tag_hp;
63177afc 990 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 991 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 992
993 /* chip access */
994 struct mutex chipio_mutex; /* chip access mutex */
995 u32 curr_chip_addx;
996
997 /* DSP download related */
998 enum dsp_download_state dsp_state;
999 unsigned int dsp_stream_id;
1000 unsigned int wait_scp;
1001 unsigned int wait_scp_header;
1002 unsigned int wait_num_data;
1003 unsigned int scp_resp_header;
1004 unsigned int scp_resp_data[4];
1005 unsigned int scp_resp_count;
8a19bcee 1006 bool alt_firmware_present;
38ba69ff 1007 bool startup_check_entered;
e93ac30a 1008 bool dsp_reload;
5aaca44d
IM		 1009
1010 /* mixer and effects related */
1011 unsigned char dmic_ctl;
1012 int cur_out_type;
1013 int cur_mic_type;
1014 long vnode_lvol[VNODES_COUNT];
1015 long vnode_rvol[VNODES_COUNT];
1016 long vnode_lswitch[VNODES_COUNT];
1017 long vnode_rswitch[VNODES_COUNT];
1018 long effects_switch[EFFECTS_COUNT];
1019 long voicefx_val;
1020 long cur_mic_boost;
7cb9d94c
CM		 1021 /* ca0132_alt control related values */
1022 unsigned char in_enum_val;
1023 unsigned char out_enum_val;
47cdf76e
CM		 1024 unsigned char mic_boost_enum_val;
1025 unsigned char smart_volume_setting;
1026 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1027 long xbass_xover_freq;
1028 long eq_preset_val;
1029 unsigned int tlv[4];
1030 struct hda_vmaster_mute_hook vmaster_mute;
212de2e7
CM		 1031 /* AE-5 Control values */
1032 unsigned char ae5_headphone_gain_val;
1033 unsigned char ae5_filter_val;
47cdf76e 1034
44f0c978 1035
993884f6
CCC		 1036 struct hda_codec *codec;
1037 struct delayed_work unsol_hp_work;
d5c016b5 1038 int quirk;
993884f6 1039
44f0c978
IM		 1040#ifdef ENABLE_TUNING_CONTROLS
1041 long cur_ctl_vals[TUNING_CTLS_COUNT];
1042#endif
aa31704f 1043 /*
08eca6b1
CM		 1044 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1045 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1046 * things.
aa31704f 1047 */
08eca6b1 1048 bool use_pci_mmio;
aa31704f 1049 void __iomem *mem_base;
009b8f97
CM		 1050
1051 /*
1052 * Whether or not to use the alt functions like alt_select_out,
1053 * alt_select_in, etc. Only used on desktop codecs for now, because of
1054 * surround sound support.
1055 */
1056 bool use_alt_functions;
47cdf76e
CM		 1057
1058 /*
1059 * Whether or not to use alt controls: volume effect sliders, EQ
1060 * presets, smart volume presets, and new control names with FX prefix.
1061 * Renames PlayEnhancement and CrystalVoice too.
1062 */
1063 bool use_alt_controls;
01ef7dbf
IM		 1064};
1065
d5c016b5
GM		 1066/*
1067 * CA0132 quirks table
1068 */
1069enum {
1070 QUIRK_NONE,
1071 QUIRK_ALIENWARE,
a57a46b9 1072 QUIRK_ALIENWARE_M17XR4,
8a19bcee
CM		 1073 QUIRK_SBZ,
1074 QUIRK_R3DI,
8f8c523c 1075 QUIRK_R3D,
f6276463 1076 QUIRK_AE5,
d5c016b5
GM		 1077};
1078
fe14f39e
TI		 1079static const struct hda_pintbl alienware_pincfgs[] = {
1080 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1081 { 0x0c, 0x411111f0 }, /* N/A */
1082 { 0x0d, 0x411111f0 }, /* N/A */
1083 { 0x0e, 0x411111f0 }, /* N/A */
1084 { 0x0f, 0x0321101f }, /* HP */
1085 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1086 { 0x11, 0x03a11021 }, /* Mic */
1087 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1088 { 0x13, 0x411111f0 }, /* N/A */
1089 { 0x18, 0x411111f0 }, /* N/A */
1090 {}
1091};
1092
63177afc
CM		 1093/* Sound Blaster Z pin configs taken from Windows Driver */
1094static const struct hda_pintbl sbz_pincfgs[] = {
1095 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1096 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1097 { 0x0d, 0x014510f0 }, /* Digital Out */
1098 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1099 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1100 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1101 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1102 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1103 { 0x13, 0x908700f0 }, /* What U Hear In*/
1104 { 0x18, 0x50d000f0 }, /* N/A */
1105 {}
1106};
1107
7f73df95
CM		 1108/* Recon3D pin configs taken from Windows Driver */
1109static const struct hda_pintbl r3d_pincfgs[] = {
1110 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1111 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1112 { 0x0d, 0x014510f0 }, /* Digital Out */
1113 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1114 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1115 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1116 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1117 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1118 { 0x13, 0x908700f0 }, /* What U Hear In*/
1119 { 0x18, 0x50d000f0 }, /* N/A */
1120 {}
1121};
1122
d06feaf0
CM		 1123/* Sound Blaster AE-5 pin configs taken from Windows Driver */
1124static const struct hda_pintbl ae5_pincfgs[] = {
1125 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1126 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1127 { 0x0d, 0x014510f0 }, /* Digital Out */
1128 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1129 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1130 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1131 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1132 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1133 { 0x13, 0x908700f0 }, /* What U Hear In*/
1134 { 0x18, 0x50d000f0 }, /* N/A */
1135 {}
1136};
1137
63177afc
CM		 1138/* Recon3D integrated pin configs taken from Windows Driver */
1139static const struct hda_pintbl r3di_pincfgs[] = {
1140 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1141 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1142 { 0x0d, 0x014510f0 }, /* Digital Out */
1143 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1144 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1145 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1146 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1147 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1148 { 0x13, 0x908700f0 }, /* What U Hear In*/
1149 { 0x18, 0x500000f0 }, /* N/A */
1150 {}
1151};
1152
d5c016b5 1153static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1154 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1155 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1156 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1157 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1158 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1159 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1160 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1161 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1162 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
8f8c523c 1163 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
f6276463 1164 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
d5c016b5
GM		 1165 {}
1166};
1167
01ef7dbf
IM		 1168/*
1169 * CA0132 codec access
1170 */
399ae725 1171static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1172 unsigned int verb, unsigned int parm, unsigned int *res)
1173{
1174 unsigned int response;
1175 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1176 *res = response;
1177
1178 return ((response == -1) ? -1 : 0);
1179}
1180
1181static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1182 unsigned short converter_format, unsigned int *res)
1183{
1184 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1185 converter_format & 0xffff, res);
1186}
1187
1188static int codec_set_converter_stream_channel(struct hda_codec *codec,
1189 hda_nid_t nid, unsigned char stream,
1190 unsigned char channel, unsigned int *res)
1191{
1192 unsigned char converter_stream_channel = 0;
1193
1194 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1195 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1196 converter_stream_channel, res);
1197}
1198
1199/* Chip access helper function */
1200static int chipio_send(struct hda_codec *codec,
1201 unsigned int reg,
1202 unsigned int data)
1203{
1204 unsigned int res;
6d67530e 1205 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1206
1207 /* send bits of data specified by reg */
1208 do {
1209 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1210 reg, data);
1211 if (res == VENDOR_STATUS_CHIPIO_OK)
1212 return 0;
6d67530e
IM		 1213 msleep(20);
1214 } while (time_before(jiffies, timeout));
1215
01ef7dbf
IM		 1216 return -EIO;
1217}
1218
1219/*
1220 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1221 */
1222static int chipio_write_address(struct hda_codec *codec,
1223 unsigned int chip_addx)
1224{
4861af80 1225 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1226 int res;
1227
4861af80
IM		 1228 if (spec->curr_chip_addx == chip_addx)
1229 return 0;
1230
01ef7dbf
IM		 1231 /* send low 16 bits of the address */
1232 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1233 chip_addx & 0xffff);
1234
1235 if (res != -EIO) {
1236 /* send high 16 bits of the address */
1237 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1238 chip_addx >> 16);
1239 }
1240
d1600401 1241 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1242
4861af80 1243 return res;
01ef7dbf
IM		 1244}
1245
1246/*
1247 * Write data through the vendor widget -- NOT protected by the Mutex!
1248 */
01ef7dbf
IM		 1249static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1250{
5aaca44d 1251 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1252 int res;
1253
1254 /* send low 16 bits of the data */
1255 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1256
1257 if (res != -EIO) {
1258 /* send high 16 bits of the data */
1259 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1260 data >> 16);
1261 }
1262
5aaca44d
IM		 1263 /*If no error encountered, automatically increment the address
1264 as per chip behaviour*/
1265 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1266 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1267 return res;
1268}
1269
d5c21b88
IM		 1270/*
1271 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1272 */
01ef7dbf
IM		 1273static int chipio_write_data_multiple(struct hda_codec *codec,
1274 const u32 *data,
1275 unsigned int count)
1276{
1277 int status = 0;
1278
1279 if (data == NULL) {
4e76a883 1280 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1281 return -EINVAL;
1282 }
1283
1284 while ((count-- != 0) && (status == 0))
1285 status = chipio_write_data(codec, *data++);
1286
1287 return status;
1288}
1289
1290
1291/*
1292 * Read data through the vendor widget -- NOT protected by the Mutex!
1293 */
1294static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1295{
5aaca44d 1296 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1297 int res;
1298
1299 /* post read */
1300 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1301
1302 if (res != -EIO) {
1303 /* read status */
1304 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1305 }
1306
1307 if (res != -EIO) {
1308 /* read data */
1309 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1310 VENDOR_CHIPIO_HIC_READ_DATA,
1311 0);
1312 }
1313
5aaca44d
IM		 1314 /*If no error encountered, automatically increment the address
1315 as per chip behaviour*/
1316 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1317 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1318 return res;
1319}
1320
1321/*
1322 * Write given value to the given address through the chip I/O widget.
1323 * protected by the Mutex
1324 */
1325static int chipio_write(struct hda_codec *codec,
1326 unsigned int chip_addx, const unsigned int data)
1327{
1328 struct ca0132_spec *spec = codec->spec;
1329 int err;
1330
1331 mutex_lock(&spec->chipio_mutex);
1332
1333 /* write the address, and if successful proceed to write data */
1334 err = chipio_write_address(codec, chip_addx);
1335 if (err < 0)
1336 goto exit;
1337
1338 err = chipio_write_data(codec, data);
1339 if (err < 0)
1340 goto exit;
1341
1342exit:
1343 mutex_unlock(&spec->chipio_mutex);
1344 return err;
1345}
1346
38ba69ff
CM		 1347/*
1348 * Write given value to the given address through the chip I/O widget.
1349 * not protected by the Mutex
1350 */
1351static int chipio_write_no_mutex(struct hda_codec *codec,
1352 unsigned int chip_addx, const unsigned int data)
1353{
1354 int err;
1355
1356
1357 /* write the address, and if successful proceed to write data */
1358 err = chipio_write_address(codec, chip_addx);
1359 if (err < 0)
1360 goto exit;
1361
1362 err = chipio_write_data(codec, data);
1363 if (err < 0)
1364 goto exit;
1365
1366exit:
1367 return err;
1368}
1369
d5c21b88
IM		 1370/*
1371 * Write multiple values to the given address through the chip I/O widget.
1372 * protected by the Mutex
1373 */
01ef7dbf
IM		 1374static int chipio_write_multiple(struct hda_codec *codec,
1375 u32 chip_addx,
1376 const u32 *data,
1377 unsigned int count)
1378{
1379 struct ca0132_spec *spec = codec->spec;
1380 int status;
1381
1382 mutex_lock(&spec->chipio_mutex);
4861af80 1383 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1384 if (status < 0)
1385 goto error;
1386
1387 status = chipio_write_data_multiple(codec, data, count);
1388error:
1389 mutex_unlock(&spec->chipio_mutex);
1390
1391 return status;
1392}
1393
1394/*
1395 * Read the given address through the chip I/O widget
1396 * protected by the Mutex
1397 */
1398static int chipio_read(struct hda_codec *codec,
1399 unsigned int chip_addx, unsigned int *data)
1400{
1401 struct ca0132_spec *spec = codec->spec;
1402 int err;
1403
1404 mutex_lock(&spec->chipio_mutex);
1405
1406 /* write the address, and if successful proceed to write data */
1407 err = chipio_write_address(codec, chip_addx);
1408 if (err < 0)
1409 goto exit;
1410
1411 err = chipio_read_data(codec, data);
1412 if (err < 0)
1413 goto exit;
1414
1415exit:
1416 mutex_unlock(&spec->chipio_mutex);
1417 return err;
1418}
1419
d5c21b88
IM		 1420/*
1421 * Set chip control flags through the chip I/O widget.
1422 */
01ef7dbf
IM		 1423static void chipio_set_control_flag(struct hda_codec *codec,
1424 enum control_flag_id flag_id,
1425 bool flag_state)
1426{
1427 unsigned int val;
1428 unsigned int flag_bit;
1429
1430 flag_bit = (flag_state ? 1 : 0);
1431 val = (flag_bit << 7) | (flag_id);
1432 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1433 VENDOR_CHIPIO_FLAG_SET, val);
1434}
1435
d5c21b88
IM		 1436/*
1437 * Set chip parameters through the chip I/O widget.
1438 */
01ef7dbf
IM		 1439static void chipio_set_control_param(struct hda_codec *codec,
1440 enum control_param_id param_id, int param_val)
1441{
1442 struct ca0132_spec *spec = codec->spec;
1443 int val;
1444
1445 if ((param_id < 32) && (param_val < 8)) {
1446 val = (param_val << 5) | (param_id);
1447 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1448 VENDOR_CHIPIO_PARAM_SET, val);
1449 } else {
1450 mutex_lock(&spec->chipio_mutex);
1451 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1452 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1453 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1454 param_id);
1455 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1456 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1457 param_val);
1458 }
1459 mutex_unlock(&spec->chipio_mutex);
1460 }
1461}
1462
009b8f97
CM		 1463/*
1464 * Set chip parameters through the chip I/O widget. NO MUTEX.
1465 */
1466static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1467 enum control_param_id param_id, int param_val)
1468{
1469 int val;
1470
1471 if ((param_id < 32) && (param_val < 8)) {
1472 val = (param_val << 5) | (param_id);
1473 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1474 VENDOR_CHIPIO_PARAM_SET, val);
1475 } else {
1476 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1477 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1478 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1479 param_id);
1480 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1481 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1482 param_val);
1483 }
1484 }
1485}
38ba69ff
CM		 1486/*
1487 * Connect stream to a source point, and then connect
1488 * that source point to a destination point.
1489 */
1490static void chipio_set_stream_source_dest(struct hda_codec *codec,
1491 int streamid, int source_point, int dest_point)
1492{
1493 chipio_set_control_param_no_mutex(codec,
1494 CONTROL_PARAM_STREAM_ID, streamid);
1495 chipio_set_control_param_no_mutex(codec,
1496 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1497 chipio_set_control_param_no_mutex(codec,
1498 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1499}
1500
1501/*
1502 * Set number of channels in the selected stream.
1503 */
1504static void chipio_set_stream_channels(struct hda_codec *codec,
1505 int streamid, unsigned int channels)
1506{
1507 chipio_set_control_param_no_mutex(codec,
1508 CONTROL_PARAM_STREAM_ID, streamid);
1509 chipio_set_control_param_no_mutex(codec,
1510 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1511}
009b8f97
CM		 1512
1513/*
1514 * Enable/Disable audio stream.
1515 */
1516static void chipio_set_stream_control(struct hda_codec *codec,
1517 int streamid, int enable)
1518{
1519 chipio_set_control_param_no_mutex(codec,
1520 CONTROL_PARAM_STREAM_ID, streamid);
1521 chipio_set_control_param_no_mutex(codec,
1522 CONTROL_PARAM_STREAM_CONTROL, enable);
1523}
1524
38ba69ff
CM		 1525
1526/*
1527 * Set sampling rate of the connection point. NO MUTEX.
1528 */
1529static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1530 int connid, enum ca0132_sample_rate rate)
1531{
1532 chipio_set_control_param_no_mutex(codec,
1533 CONTROL_PARAM_CONN_POINT_ID, connid);
1534 chipio_set_control_param_no_mutex(codec,
1535 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1536}
1537
d5c21b88
IM		 1538/*
1539 * Set sampling rate of the connection point.
1540 */
01ef7dbf
IM		 1541static void chipio_set_conn_rate(struct hda_codec *codec,
1542 int connid, enum ca0132_sample_rate rate)
1543{
1544 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1545 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1546 rate);
1547}
1548
b9b41345
CM		 1549/*
1550 * Writes to the 8051's internal address space directly instead of indirectly,
1551 * giving access to the special function registers located at addresses
1552 * 0x80-0xFF.
1553 */
1554static void chipio_8051_write_direct(struct hda_codec *codec,
1555 unsigned int addr, unsigned int data)
1556{
1557 unsigned int verb;
1558
1559 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1560 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1561}
1562
d5c21b88
IM		 1563/*
1564 * Enable clocks.
1565 */
01ef7dbf
IM		 1566static void chipio_enable_clocks(struct hda_codec *codec)
1567{
1568 struct ca0132_spec *spec = codec->spec;
1569
1570 mutex_lock(&spec->chipio_mutex);
1571 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1572 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1573 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1574 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1575 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1576 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1577 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1578 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1579 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1580 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1581 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1582 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1583 mutex_unlock(&spec->chipio_mutex);
1584}
1585
1586/*
1587 * CA0132 DSP IO stuffs
1588 */
1589static int dspio_send(struct hda_codec *codec, unsigned int reg,
1590 unsigned int data)
1591{
b645d796 1592 int res;
6d67530e 1593 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1594
1595 /* send bits of data specified by reg to dsp */
1596 do {
1597 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1598 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1599 return res;
6d67530e
IM		 1600 msleep(20);
1601 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1602
1603 return -EIO;
1604}
1605
d5c21b88
IM		 1606/*
1607 * Wait for DSP to be ready for commands
1608 */
01ef7dbf
IM		 1609static void dspio_write_wait(struct hda_codec *codec)
1610{
4861af80
IM		 1611 int status;
1612 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1613
01ef7dbf 1614 do {
4861af80
IM		 1615 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1616 VENDOR_DSPIO_STATUS, 0);
1617 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1618 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1619 break;
1620 msleep(1);
1621 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1622}
1623
d5c21b88
IM		 1624/*
1625 * Write SCP data to DSP
1626 */
01ef7dbf
IM		 1627static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1628{
1629 struct ca0132_spec *spec = codec->spec;
1630 int status;
1631
1632 dspio_write_wait(codec);
1633
1634 mutex_lock(&spec->chipio_mutex);
1635 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1636 scp_data & 0xffff);
1637 if (status < 0)
1638 goto error;
1639
1640 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1641 scp_data >> 16);
1642 if (status < 0)
1643 goto error;
1644
1645 /* OK, now check if the write itself has executed*/
1646 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1647 VENDOR_DSPIO_STATUS, 0);
1648error:
1649 mutex_unlock(&spec->chipio_mutex);
1650
1651 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1652 -EIO : 0;
1653}
1654
d5c21b88
IM		 1655/*
1656 * Write multiple SCP data to DSP
1657 */
01ef7dbf
IM		 1658static int dspio_write_multiple(struct hda_codec *codec,
1659 unsigned int *buffer, unsigned int size)
1660{
1661 int status = 0;
1662 unsigned int count;
1663
a16fbb85 1664 if (buffer == NULL)
01ef7dbf
IM		 1665 return -EINVAL;
1666
1667 count = 0;
1668 while (count < size) {
1669 status = dspio_write(codec, *buffer++);
1670 if (status != 0)
1671 break;
1672 count++;
1673 }
1674
1675 return status;
1676}
1677
a73d511c
IM		 1678static int dspio_read(struct hda_codec *codec, unsigned int *data)
1679{
1680 int status;
1681
1682 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1683 if (status == -EIO)
1684 return status;
1685
1686 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1687 if (status == -EIO ||
1688 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1689 return -EIO;
1690
1691 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1692 VENDOR_DSPIO_SCP_READ_DATA, 0);
1693
1694 return 0;
1695}
1696
1697static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1698 unsigned int *buf_size, unsigned int size_count)
1699{
1700 int status = 0;
1701 unsigned int size = *buf_size;
1702 unsigned int count;
1703 unsigned int skip_count;
1704 unsigned int dummy;
1705
a16fbb85 1706 if (buffer == NULL)
a73d511c
IM		 1707 return -1;
1708
1709 count = 0;
1710 while (count < size && count < size_count) {
1711 status = dspio_read(codec, buffer++);
1712 if (status != 0)
1713 break;
1714 count++;
1715 }
1716
1717 skip_count = count;
1718 if (status == 0) {
1719 while (skip_count < size) {
1720 status = dspio_read(codec, &dummy);
1721 if (status != 0)
1722 break;
1723 skip_count++;
1724 }
1725 }
1726 *buf_size = count;
1727
1728 return status;
1729}
1730
d5c21b88
IM		 1731/*
1732 * Construct the SCP header using corresponding fields
1733 */
01ef7dbf
IM		 1734static inline unsigned int
1735make_scp_header(unsigned int target_id, unsigned int source_id,
1736 unsigned int get_flag, unsigned int req,
1737 unsigned int device_flag, unsigned int resp_flag,
1738 unsigned int error_flag, unsigned int data_size)
1739{
1740 unsigned int header = 0;
1741
1742 header = (data_size & 0x1f) << 27;
1743 header |= (error_flag & 0x01) << 26;
1744 header |= (resp_flag & 0x01) << 25;
1745 header |= (device_flag & 0x01) << 24;
1746 header |= (req & 0x7f) << 17;
1747 header |= (get_flag & 0x01) << 16;
1748 header |= (source_id & 0xff) << 8;
1749 header |= target_id & 0xff;
1750
1751 return header;
1752}
1753
d5c21b88
IM		 1754/*
1755 * Extract corresponding fields from SCP header
1756 */
01ef7dbf
IM		 1757static inline void
1758extract_scp_header(unsigned int header,
1759 unsigned int *target_id, unsigned int *source_id,
1760 unsigned int *get_flag, unsigned int *req,
1761 unsigned int *device_flag, unsigned int *resp_flag,
1762 unsigned int *error_flag, unsigned int *data_size)
1763{
1764 if (data_size)
1765 *data_size = (header >> 27) & 0x1f;
1766 if (error_flag)
1767 *error_flag = (header >> 26) & 0x01;
1768 if (resp_flag)
1769 *resp_flag = (header >> 25) & 0x01;
1770 if (device_flag)
1771 *device_flag = (header >> 24) & 0x01;
1772 if (req)
1773 *req = (header >> 17) & 0x7f;
1774 if (get_flag)
1775 *get_flag = (header >> 16) & 0x01;
1776 if (source_id)
1777 *source_id = (header >> 8) & 0xff;
1778 if (target_id)
1779 *target_id = header & 0xff;
1780}
1781
1782#define SCP_MAX_DATA_WORDS (16)
1783
1784/* Structure to contain any SCP message */
1785struct scp_msg {
1786 unsigned int hdr;
1787 unsigned int data[SCP_MAX_DATA_WORDS];
1788};
1789
a73d511c
IM		 1790static void dspio_clear_response_queue(struct hda_codec *codec)
1791{
1792 unsigned int dummy = 0;
1793 int status = -1;
1794
1795 /* clear all from the response queue */
1796 do {
1797 status = dspio_read(codec, &dummy);
1798 } while (status == 0);
1799}
1800
1801static int dspio_get_response_data(struct hda_codec *codec)
1802{
1803 struct ca0132_spec *spec = codec->spec;
1804 unsigned int data = 0;
1805 unsigned int count;
1806
1807 if (dspio_read(codec, &data) < 0)
1808 return -EIO;
1809
1810 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1811 spec->scp_resp_header = data;
1812 spec->scp_resp_count = data >> 27;
1813 count = spec->wait_num_data;
1814 dspio_read_multiple(codec, spec->scp_resp_data,
1815 &spec->scp_resp_count, count);
1816 return 0;
1817 }
1818
1819 return -EIO;
1820}
1821
d5c21b88
IM		 1822/*
1823 * Send SCP message to DSP
1824 */
01ef7dbf
IM		 1825static int dspio_send_scp_message(struct hda_codec *codec,
1826 unsigned char *send_buf,
1827 unsigned int send_buf_size,
1828 unsigned char *return_buf,
1829 unsigned int return_buf_size,
1830 unsigned int *bytes_returned)
1831{
1832 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1833 int status = -1;
1834 unsigned int scp_send_size = 0;
1835 unsigned int total_size;
1836 bool waiting_for_resp = false;
1837 unsigned int header;
1838 struct scp_msg *ret_msg;
1839 unsigned int resp_src_id, resp_target_id;
1840 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1841
1842 if (bytes_returned)
1843 *bytes_returned = 0;
1844
1845 /* get scp header from buffer */
1846 header = *((unsigned int *)send_buf);
1847 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1848 &device_flag, NULL, NULL, &data_size);
1849 scp_send_size = data_size + 1;
1850 total_size = (scp_send_size * 4);
1851
1852 if (send_buf_size < total_size)
1853 return -EINVAL;
1854
1855 if (get_flag || device_flag) {
1856 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1857 return -EINVAL;
1858
1859 spec->wait_scp_header = *((unsigned int *)send_buf);
1860
1861 /* swap source id with target id */
1862 resp_target_id = src_id;
1863 resp_src_id = target_id;
1864 spec->wait_scp_header &= 0xffff0000;
1865 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1866 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1867 spec->wait_scp = 1;
1868 waiting_for_resp = true;
1869 }
1870
1871 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1872 scp_send_size);
1873 if (status < 0) {
1874 spec->wait_scp = 0;
1875 return status;
1876 }
1877
1878 if (waiting_for_resp) {
6d67530e 1879 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1880 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1881 do {
1882 msleep(20);
6d67530e 1883 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1884 waiting_for_resp = false;
6d67530e 1885 if (!spec->wait_scp) {
01ef7dbf
IM		 1886 ret_msg = (struct scp_msg *)return_buf;
1887 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1888 memcpy(&ret_msg->data, spec->scp_resp_data,
1889 spec->wait_num_data);
1890 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1891 status = 0;
1892 } else {
1893 status = -EIO;
1894 }
1895 spec->wait_scp = 0;
1896 }
1897
1898 return status;
1899}
1900
d5c21b88
IM		 1901/**
1902 * Prepare and send the SCP message to DSP
1903 * @codec: the HDA codec
1904 * @mod_id: ID of the DSP module to send the command
1905 * @req: ID of request to send to the DSP module
1906 * @dir: SET or GET
1907 * @data: pointer to the data to send with the request, request specific
1908 * @len: length of the data, in bytes
1909 * @reply: point to the buffer to hold data returned for a reply
1910 * @reply_len: length of the reply buffer returned from GET
1911 *
1912 * Returns zero or a negative error code.
1913 */
01ef7dbf 1914static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1915 int mod_id, int src_id, int req, int dir, const void *data,
1916 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1917{
1918 int status = 0;
1919 struct scp_msg scp_send, scp_reply;
1920 unsigned int ret_bytes, send_size, ret_size;
1921 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1922 unsigned int reply_data_size;
1923
1924 memset(&scp_send, 0, sizeof(scp_send));
1925 memset(&scp_reply, 0, sizeof(scp_reply));
1926
1927 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1928 return -EINVAL;
1929
1930 if (dir == SCP_GET && reply == NULL) {
4e76a883 1931 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1932 return -EINVAL;
1933 }
1934
1935 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1936 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1937 return -EINVAL;
1938 }
1939
447fd8e9 1940 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1941 0, 0, 0, len/sizeof(unsigned int));
1942 if (data != NULL && len > 0) {
1943 len = min((unsigned int)(sizeof(scp_send.data)), len);
1944 memcpy(scp_send.data, data, len);
1945 }
1946
1947 ret_bytes = 0;
1948 send_size = sizeof(unsigned int) + len;
1949 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1950 send_size, (unsigned char *)&scp_reply,
1951 sizeof(scp_reply), &ret_bytes);
1952
1953 if (status < 0) {
4e76a883 1954 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1955 return status;
1956 }
1957
1958 /* extract send and reply headers members */
1959 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1960 NULL, NULL, NULL, NULL, NULL);
1961 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1962 &reply_resp_flag, &reply_error_flag,
1963 &reply_data_size);
1964
1965 if (!send_get_flag)
1966 return 0;
1967
1968 if (reply_resp_flag && !reply_error_flag) {
1969 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1970 / sizeof(unsigned int);
1971
1972 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1973 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1974 return -EINVAL;
1975 } else if (ret_size != reply_data_size) {
4e76a883 1976 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1977 return -EINVAL;
46a049da
AB		 1978 } else if (!reply) {
1979 codec_dbg(codec, "NULL reply\n");
1980 return -EINVAL;
01ef7dbf
IM		 1981 } else {
1982 *reply_len = ret_size*sizeof(unsigned int);
1983 memcpy(reply, scp_reply.data, *reply_len);
1984 }
1985 } else {
4e76a883 1986 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1987 return -EIO;
1988 }
1989
1990 return status;
1991}
1992
5aaca44d
IM		 1993/*
1994 * Set DSP parameters
1995 */
1996static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 1997 int src_id, int req, const void *data, unsigned int len)
5aaca44d 1998{
447fd8e9
CM		 1999 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2000 NULL);
5aaca44d
IM		 2001}
2002
2003static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 2004 int req, const unsigned int data)
5aaca44d 2005{
447fd8e9
CM		 2006 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2007 sizeof(unsigned int));
2008}
2009
2010static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2011 int req, const unsigned int data)
2012{
2013 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2014 sizeof(unsigned int));
5aaca44d
IM		 2015}
2016
d5c21b88
IM		 2017/*
2018 * Allocate a DSP DMA channel via an SCP message
2019 */
01ef7dbf
IM		 2020static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2021{
2022 int status = 0;
2023 unsigned int size = sizeof(dma_chan);
2024
4e76a883 2025 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 2026 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2027 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2028 dma_chan, &size);
01ef7dbf
IM		 2029
2030 if (status < 0) {
4e76a883 2031 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2032 return status;
2033 }
2034
2035 if ((*dma_chan + 1) == 0) {
4e76a883 2036 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 2037 return -EBUSY;
2038 }
2039
4e76a883
TI		 2040 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2041 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 2042
2043 return status;
2044}
2045
d5c21b88
IM		 2046/*
2047 * Free a DSP DMA via an SCP message
2048 */
01ef7dbf
IM		 2049static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2050{
2051 int status = 0;
2052 unsigned int dummy = 0;
2053
4e76a883
TI		 2054 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2055 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 2056
447fd8e9
CM		 2057 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2058 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2059 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 2060
2061 if (status < 0) {
4e76a883 2062 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2063 return status;
2064 }
2065
4e76a883 2066 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 2067
2068 return status;
2069}
2070
2071/*
d5c21b88 2072 * (Re)start the DSP
01ef7dbf
IM		 2073 */
2074static int dsp_set_run_state(struct hda_codec *codec)
2075{
2076 unsigned int dbg_ctrl_reg;
2077 unsigned int halt_state;
2078 int err;
2079
2080 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2081 if (err < 0)
2082 return err;
2083
2084 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2085 DSP_DBGCNTL_STATE_LOBIT;
2086
2087 if (halt_state != 0) {
2088 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2089 DSP_DBGCNTL_SS_MASK);
2090 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2091 dbg_ctrl_reg);
2092 if (err < 0)
2093 return err;
2094
2095 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2096 DSP_DBGCNTL_EXEC_MASK;
2097 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2098 dbg_ctrl_reg);
2099 if (err < 0)
2100 return err;
2101 }
2102
2103 return 0;
2104}
2105
d5c21b88
IM		 2106/*
2107 * Reset the DSP
2108 */
01ef7dbf
IM		 2109static int dsp_reset(struct hda_codec *codec)
2110{
2111 unsigned int res;
2112 int retry = 20;
2113
4e76a883 2114 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 2115 do {
2116 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2117 retry--;
2118 } while (res == -EIO && retry);
2119
2120 if (!retry) {
4e76a883 2121 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 2122 return -EIO;
2123 }
2124
2125 return 0;
2126}
2127
d5c21b88
IM		 2128/*
2129 * Convert chip address to DSP address
2130 */
01ef7dbf
IM		 2131static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2132 bool *code, bool *yram)
2133{
2134 *code = *yram = false;
2135
2136 if (UC_RANGE(chip_addx, 1)) {
2137 *code = true;
2138 return UC_OFF(chip_addx);
2139 } else if (X_RANGE_ALL(chip_addx, 1)) {
2140 return X_OFF(chip_addx);
2141 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2142 *yram = true;
2143 return Y_OFF(chip_addx);
2144 }
2145
4a8b89f9 2146 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2147}
2148
d5c21b88
IM		 2149/*
2150 * Check if the DSP DMA is active
2151 */
01ef7dbf
IM		 2152static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2153{
2154 unsigned int dma_chnlstart_reg;
2155
2156 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2157
2158 return ((dma_chnlstart_reg & (1 <<
2159 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2160}
2161
2162static int dsp_dma_setup_common(struct hda_codec *codec,
2163 unsigned int chip_addx,
2164 unsigned int dma_chan,
2165 unsigned int port_map_mask,
2166 bool ovly)
2167{
2168 int status = 0;
2169 unsigned int chnl_prop;
2170 unsigned int dsp_addx;
2171 unsigned int active;
2172 bool code, yram;
2173
4e76a883 2174 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2175
2176 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2177 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2178 return -EINVAL;
2179 }
2180
2181 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2182 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2183 return -EBUSY;
2184 }
2185
2186 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2187
2188 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2189 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2190 return -ENXIO;
2191 }
2192
2193 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2194 active = 0;
2195
4e76a883 2196 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2197
2198 if (ovly) {
2199 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2200 &chnl_prop);
2201
2202 if (status < 0) {
4e76a883 2203 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2204 return status;
2205 }
4e76a883 2206 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2207 }
2208
2209 if (!code)
2210 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2211 else
2212 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2213
2214 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2215
2216 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2217 if (status < 0) {
4e76a883 2218 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2219 return status;
2220 }
4e76a883 2221 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2222
2223 if (ovly) {
2224 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2225 &active);
2226
2227 if (status < 0) {
4e76a883 2228 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2229 return status;
2230 }
4e76a883 2231 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2232 }
2233
2234 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2235 DSPDMAC_ACTIVE_AAR_MASK;
2236
2237 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2238 if (status < 0) {
4e76a883 2239 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2240 return status;
2241 }
2242
4e76a883 2243 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2244
2245 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2246 port_map_mask);
2247 if (status < 0) {
4e76a883 2248 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2249 return status;
2250 }
4e76a883 2251 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2252
2253 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2254 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2255 if (status < 0) {
4e76a883 2256 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2257 return status;
2258 }
4e76a883 2259 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2260
4e76a883 2261 codec_dbg(codec,
01ef7dbf
IM		 2262 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2263 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2264 chip_addx, dsp_addx, dma_chan,
2265 port_map_mask, chnl_prop, active);
2266
4e76a883 2267 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2268
2269 return 0;
2270}
2271
d5c21b88
IM		 2272/*
2273 * Setup the DSP DMA per-transfer-specific registers
2274 */
01ef7dbf
IM		 2275static int dsp_dma_setup(struct hda_codec *codec,
2276 unsigned int chip_addx,
2277 unsigned int count,
2278 unsigned int dma_chan)
2279{
2280 int status = 0;
2281 bool code, yram;
2282 unsigned int dsp_addx;
2283 unsigned int addr_field;
2284 unsigned int incr_field;
2285 unsigned int base_cnt;
2286 unsigned int cur_cnt;
2287 unsigned int dma_cfg = 0;
2288 unsigned int adr_ofs = 0;
2289 unsigned int xfr_cnt = 0;
2290 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2291 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2292
4e76a883 2293 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2294
2295 if (count > max_dma_count) {
4e76a883 2296 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2297 return -EINVAL;
2298 }
2299
2300 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2301 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2302 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2303 return -ENXIO;
2304 }
2305
4e76a883 2306 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2307
2308 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2309 incr_field = 0;
2310
2311 if (!code) {
2312 addr_field <<= 1;
2313 if (yram)
2314 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2315
2316 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2317 }
2318
2319 dma_cfg = addr_field + incr_field;
2320 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2321 dma_cfg);
2322 if (status < 0) {
4e76a883 2323 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2324 return status;
2325 }
4e76a883 2326 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2327
2328 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2329 (code ? 0 : 1));
2330
2331 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2332 adr_ofs);
2333 if (status < 0) {
4e76a883 2334 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2335 return status;
2336 }
4e76a883 2337 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2338
2339 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2340
2341 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2342
2343 xfr_cnt = base_cnt | cur_cnt;
2344
2345 status = chipio_write(codec,
2346 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2347 if (status < 0) {
4e76a883 2348 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2349 return status;
2350 }
4e76a883 2351 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2352
4e76a883 2353 codec_dbg(codec,
01ef7dbf
IM		 2354 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2355 "ADROFS=0x%x, XFRCNT=0x%x\n",
2356 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2357
4e76a883 2358 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2359
2360 return 0;
2361}
2362
d5c21b88
IM		 2363/*
2364 * Start the DSP DMA
2365 */
01ef7dbf
IM		 2366static int dsp_dma_start(struct hda_codec *codec,
2367 unsigned int dma_chan, bool ovly)
2368{
2369 unsigned int reg = 0;
2370 int status = 0;
2371
4e76a883 2372 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2373
2374 if (ovly) {
2375 status = chipio_read(codec,
2376 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2377
2378 if (status < 0) {
4e76a883 2379 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2380 return status;
2381 }
4e76a883 2382 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2383
2384 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2385 DSPDMAC_CHNLSTART_DIS_MASK);
2386 }
2387
2388 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2389 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2390 if (status < 0) {
4e76a883 2391 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2392 return status;
2393 }
4e76a883 2394 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2395
2396 return status;
2397}
2398
d5c21b88
IM		 2399/*
2400 * Stop the DSP DMA
2401 */
01ef7dbf
IM		 2402static int dsp_dma_stop(struct hda_codec *codec,
2403 unsigned int dma_chan, bool ovly)
2404{
2405 unsigned int reg = 0;
2406 int status = 0;
2407
4e76a883 2408 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2409
2410 if (ovly) {
2411 status = chipio_read(codec,
2412 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2413
2414 if (status < 0) {
4e76a883 2415 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2416 return status;
2417 }
4e76a883 2418 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2419 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2420 DSPDMAC_CHNLSTART_DIS_MASK);
2421 }
2422
2423 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2424 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2425 if (status < 0) {
4e76a883 2426 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2427 return status;
2428 }
4e76a883 2429 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2430
2431 return status;
2432}
2433
d5c21b88
IM		 2434/**
2435 * Allocate router ports
2436 *
2437 * @codec: the HDA codec
2438 * @num_chans: number of channels in the stream
2439 * @ports_per_channel: number of ports per channel
2440 * @start_device: start device
2441 * @port_map: pointer to the port list to hold the allocated ports
2442 *
2443 * Returns zero or a negative error code.
2444 */
01ef7dbf
IM		 2445static int dsp_allocate_router_ports(struct hda_codec *codec,
2446 unsigned int num_chans,
2447 unsigned int ports_per_channel,
2448 unsigned int start_device,
2449 unsigned int *port_map)
2450{
2451 int status = 0;
2452 int res;
2453 u8 val;
2454
2455 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2456 if (status < 0)
2457 return status;
2458
2459 val = start_device << 6;
2460 val |= (ports_per_channel - 1) << 4;
2461 val |= num_chans - 1;
2462
2463 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2464 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2465 val);
2466
2467 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2468 VENDOR_CHIPIO_PORT_ALLOC_SET,
2469 MEM_CONNID_DSP);
2470
2471 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2472 if (status < 0)
2473 return status;
2474
2475 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2476 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2477
2478 *port_map = res;
2479
2480 return (res < 0) ? res : 0;
2481}
2482
d5c21b88
IM		 2483/*
2484 * Free router ports
2485 */
01ef7dbf
IM		 2486static int dsp_free_router_ports(struct hda_codec *codec)
2487{
2488 int status = 0;
2489
2490 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2491 if (status < 0)
2492 return status;
2493
2494 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2495 VENDOR_CHIPIO_PORT_FREE_SET,
2496 MEM_CONNID_DSP);
2497
2498 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2499
2500 return status;
2501}
2502
d5c21b88
IM		 2503/*
2504 * Allocate DSP ports for the download stream
2505 */
01ef7dbf
IM		 2506static int dsp_allocate_ports(struct hda_codec *codec,
2507 unsigned int num_chans,
2508 unsigned int rate_multi, unsigned int *port_map)
2509{
2510 int status;
2511
4e76a883 2512 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2513
2514 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2515 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2516 return -EINVAL;
2517 }
2518
2519 status = dsp_allocate_router_ports(codec, num_chans,
2520 rate_multi, 0, port_map);
2521
4e76a883 2522 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2523
2524 return status;
2525}
2526
01ef7dbf
IM		 2527static int dsp_allocate_ports_format(struct hda_codec *codec,
2528 const unsigned short fmt,
2529 unsigned int *port_map)
2530{
2531 int status;
2532 unsigned int num_chans;
2533
2534 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2535 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2536 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2537
2538 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2539 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2540 return -EINVAL;
2541 }
2542
2543 num_chans = get_hdafmt_chs(fmt) + 1;
2544
2545 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2546
2547 return status;
2548}
2549
d5c21b88
IM		 2550/*
2551 * free DSP ports
2552 */
2553static int dsp_free_ports(struct hda_codec *codec)
2554{
2555 int status;
2556
4e76a883 2557 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2558
2559 status = dsp_free_router_ports(codec);
2560 if (status < 0) {
4e76a883 2561 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2562 return status;
2563 }
4e76a883 2564 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2565
2566 return status;
2567}
2568
01ef7dbf
IM		 2569/*
2570 * HDA DMA engine stuffs for DSP code download
2571 */
2572struct dma_engine {
2573 struct hda_codec *codec;
2574 unsigned short m_converter_format;
2575 struct snd_dma_buffer *dmab;
2576 unsigned int buf_size;
2577};
2578
2579
2580enum dma_state {
2581 DMA_STATE_STOP = 0,
2582 DMA_STATE_RUN = 1
2583};
2584
6194b99d 2585static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2586 unsigned int sample_rate,
2587 unsigned short channels,
01ef7dbf
IM		 2588 unsigned short *hda_format)
2589{
2590 unsigned int format_val;
2591
b7d023e1
TI		 2592 format_val = snd_hdac_calc_stream_format(sample_rate,
2593 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2594
2595 if (hda_format)
2596 *hda_format = (unsigned short)format_val;
2597
2598 return 0;
2599}
2600
d5c21b88
IM		 2601/*
2602 * Reset DMA for DSP download
2603 */
01ef7dbf
IM		 2604static int dma_reset(struct dma_engine *dma)
2605{
2606 struct hda_codec *codec = dma->codec;
2607 struct ca0132_spec *spec = codec->spec;
2608 int status;
2609
b3667bd7 2610 if (dma->dmab->area)
01ef7dbf
IM		 2611 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2612
2613 status = snd_hda_codec_load_dsp_prepare(codec,
2614 dma->m_converter_format,
2615 dma->buf_size,
2616 dma->dmab);
2617 if (status < 0)
2618 return status;
2619 spec->dsp_stream_id = status;
2620 return 0;
2621}
2622
2623static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2624{
01ef7dbf
IM		 2625 bool cmd;
2626
01ef7dbf
IM		 2627 switch (state) {
2628 case DMA_STATE_STOP:
2629 cmd = false;
2630 break;
2631 case DMA_STATE_RUN:
2632 cmd = true;
2633 break;
2634 default:
c41999a2
DH		 2635 return 0;
2636 }
01ef7dbf
IM		 2637
2638 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2639 return 0;
95c6e9cb
IM		 2640}
2641
01ef7dbf
IM		 2642static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2643{
2644 return dma->dmab->bytes;
2645}
95c6e9cb 2646
01ef7dbf
IM		 2647static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2648{
2649 return dma->dmab->area;
2650}
95c6e9cb 2651
01ef7dbf
IM		 2652static int dma_xfer(struct dma_engine *dma,
2653 const unsigned int *data,
2654 unsigned int count)
2655{
2656 memcpy(dma->dmab->area, data, count);
2657 return 0;
2658}
95c6e9cb 2659
01ef7dbf
IM		 2660static void dma_get_converter_format(
2661 struct dma_engine *dma,
2662 unsigned short *format)
2663{
2664 if (format)
2665 *format = dma->m_converter_format;
2666}
95c6e9cb 2667
01ef7dbf 2668static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2669{
01ef7dbf 2670 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2671
01ef7dbf 2672 return spec->dsp_stream_id;
95c6e9cb
IM		 2673}
2674
01ef7dbf
IM		 2675struct dsp_image_seg {
2676 u32 magic;
2677 u32 chip_addr;
2678 u32 count;
2679 u32 data[0];
2680};
2681
2682static const u32 g_magic_value = 0x4c46584d;
2683static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2684
2685static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2686{
01ef7dbf
IM		 2687 return p->magic == g_magic_value;
2688}
95c6e9cb 2689
01ef7dbf
IM		 2690static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2691{
2692 return g_chip_addr_magic_value == p->chip_addr;
2693}
95c6e9cb 2694
01ef7dbf
IM		 2695static bool is_last(const struct dsp_image_seg *p)
2696{
2697 return p->count == 0;
2698}
95c6e9cb 2699
01ef7dbf
IM		 2700static size_t dsp_sizeof(const struct dsp_image_seg *p)
2701{
2702 return sizeof(*p) + p->count*sizeof(u32);
2703}
2704
2705static const struct dsp_image_seg *get_next_seg_ptr(
2706 const struct dsp_image_seg *p)
2707{
2708 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2709}
2710
2711/*
01ef7dbf 2712 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2713 */
8ae3124b 2714#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2715
d5c21b88
IM		 2716/*
2717 * Program a list of address/data pairs via the ChipIO widget.
2718 * The segment data is in the format of successive pairs of words.
2719 * These are repeated as indicated by the segment's count field.
2720 */
01ef7dbf
IM		 2721static int dspxfr_hci_write(struct hda_codec *codec,
2722 const struct dsp_image_seg *fls)
95c6e9cb 2723{
01ef7dbf
IM		 2724 int status;
2725 const u32 *data;
2726 unsigned int count;
95c6e9cb 2727
01ef7dbf 2728 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2729 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2730 return -EINVAL;
95c6e9cb
IM		 2731 }
2732
01ef7dbf
IM		 2733 count = fls->count;
2734 data = (u32 *)(fls->data);
2735 while (count >= 2) {
2736 status = chipio_write(codec, data[0], data[1]);
2737 if (status < 0) {
4e76a883 2738 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2739 return status;
2740 }
2741 count -= 2;
2742 data += 2;
2743 }
2744 return 0;
95c6e9cb
IM		 2745}
2746
d5c21b88
IM		 2747/**
2748 * Write a block of data into DSP code or data RAM using pre-allocated
2749 * DMA engine.
2750 *
2751 * @codec: the HDA codec
2752 * @fls: pointer to a fast load image
2753 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2754 * no relocation
2755 * @dma_engine: pointer to DMA engine to be used for DSP download
2756 * @dma_chan: The number of DMA channels used for DSP download
2757 * @port_map_mask: port mapping
2758 * @ovly: TRUE if overlay format is required
2759 *
2760 * Returns zero or a negative error code.
2761 */
01ef7dbf
IM		 2762static int dspxfr_one_seg(struct hda_codec *codec,
2763 const struct dsp_image_seg *fls,
2764 unsigned int reloc,
2765 struct dma_engine *dma_engine,
2766 unsigned int dma_chan,
2767 unsigned int port_map_mask,
2768 bool ovly)
95c6e9cb 2769{
406261ce 2770 int status = 0;
01ef7dbf
IM		 2771 bool comm_dma_setup_done = false;
2772 const unsigned int *data;
2773 unsigned int chip_addx;
2774 unsigned int words_to_write;
2775 unsigned int buffer_size_words;
2776 unsigned char *buffer_addx;
2777 unsigned short hda_format;
2778 unsigned int sample_rate_div;
2779 unsigned int sample_rate_mul;
2780 unsigned int num_chans;
2781 unsigned int hda_frame_size_words;
2782 unsigned int remainder_words;
2783 const u32 *data_remainder;
2784 u32 chip_addx_remainder;
2785 unsigned int run_size_words;
2786 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2787 unsigned long timeout;
2788 bool dma_active;
01ef7dbf
IM		 2789
2790 if (fls == NULL)
2791 return -EINVAL;
2792 if (is_hci_prog_list_seg(fls)) {
2793 hci_write = fls;
2794 fls = get_next_seg_ptr(fls);
2795 }
95c6e9cb 2796
01ef7dbf 2797 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2798 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2799 return dspxfr_hci_write(codec, hci_write);
2800 }
95c6e9cb 2801
01ef7dbf 2802 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2803 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2804 return -EINVAL;
95c6e9cb
IM		 2805 }
2806
01ef7dbf
IM		 2807 data = fls->data;
2808 chip_addx = fls->chip_addr,
2809 words_to_write = fls->count;
2810
2811 if (!words_to_write)
2812 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2813 if (reloc)
2814 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2815
2816 if (!UC_RANGE(chip_addx, words_to_write) &&
2817 !X_RANGE_ALL(chip_addx, words_to_write) &&
2818 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2819 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2820 return -EINVAL;
95c6e9cb
IM		 2821 }
2822
01ef7dbf
IM		 2823 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2824 sizeof(u32);
2825
2826 buffer_addx = dma_get_buffer_addr(dma_engine);
2827
2828 if (buffer_addx == NULL) {
4e76a883 2829 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2830 return -EINVAL;
2831 }
2832
2833 dma_get_converter_format(dma_engine, &hda_format);
2834 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2835 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2836 num_chans = get_hdafmt_chs(hda_format) + 1;
2837
2838 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2839 (num_chans * sample_rate_mul / sample_rate_div));
2840
3bc085a1 2841 if (hda_frame_size_words == 0) {
4e76a883 2842 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2843 return -EINVAL;
2844 }
2845
01ef7dbf
IM		 2846 buffer_size_words = min(buffer_size_words,
2847 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2848 65536 : 32768));
2849 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2850 codec_dbg(codec,
01ef7dbf
IM		 2851 "chpadr=0x%08x frmsz=%u nchan=%u "
2852 "rate_mul=%u div=%u bufsz=%u\n",
2853 chip_addx, hda_frame_size_words, num_chans,
2854 sample_rate_mul, sample_rate_div, buffer_size_words);
2855
3bc085a1 2856 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2857 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2858 return -EINVAL;
2859 }
2860
2861 remainder_words = words_to_write % hda_frame_size_words;
2862 data_remainder = data;
2863 chip_addx_remainder = chip_addx;
2864
2865 data += remainder_words;
2866 chip_addx += remainder_words*sizeof(u32);
2867 words_to_write -= remainder_words;
2868
2869 while (words_to_write != 0) {
2870 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2871 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2872 words_to_write, run_size_words, remainder_words);
2873 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2874 if (!comm_dma_setup_done) {
2875 status = dsp_dma_stop(codec, dma_chan, ovly);
2876 if (status < 0)
425a7880 2877 return status;
01ef7dbf
IM		 2878 status = dsp_dma_setup_common(codec, chip_addx,
2879 dma_chan, port_map_mask, ovly);
2880 if (status < 0)
2881 return status;
2882 comm_dma_setup_done = true;
2883 }
2884
2885 status = dsp_dma_setup(codec, chip_addx,
2886 run_size_words, dma_chan);
2887 if (status < 0)
2888 return status;
2889 status = dsp_dma_start(codec, dma_chan, ovly);
2890 if (status < 0)
2891 return status;
2892 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2893 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2894 return -EIO;
2895 }
2896 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2897 if (status < 0)
2898 return status;
2899 if (remainder_words != 0) {
2900 status = chipio_write_multiple(codec,
2901 chip_addx_remainder,
2902 data_remainder,
2903 remainder_words);
b3667bd7
TI		 2904 if (status < 0)
2905 return status;
01ef7dbf
IM		 2906 remainder_words = 0;
2907 }
2908 if (hci_write) {
2909 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2910 if (status < 0)
2911 return status;
01ef7dbf
IM		 2912 hci_write = NULL;
2913 }
6d67530e
IM		 2914
2915 timeout = jiffies + msecs_to_jiffies(2000);
2916 do {
2917 dma_active = dsp_is_dma_active(codec, dma_chan);
2918 if (!dma_active)
01ef7dbf 2919 break;
6d67530e
IM		 2920 msleep(20);
2921 } while (time_before(jiffies, timeout));
2922 if (dma_active)
2923 break;
2924
4e76a883 2925 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2926 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2927 status = dma_reset(dma_engine);
01ef7dbf
IM		 2928
2929 if (status < 0)
2930 return status;
2931
2932 data += run_size_words;
2933 chip_addx += run_size_words*sizeof(u32);
2934 words_to_write -= run_size_words;
2935 }
2936
2937 if (remainder_words != 0) {
2938 status = chipio_write_multiple(codec, chip_addx_remainder,
2939 data_remainder, remainder_words);
2940 }
2941
2942 return status;
95c6e9cb
IM		 2943}
2944
d5c21b88
IM		 2945/**
2946 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2947 *
2948 * @codec: the HDA codec
2949 * @fls_data: pointer to a fast load image
2950 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2951 * no relocation
e97249dd 2952 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2953 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2954 * @ovly: TRUE if overlay format is required
2955 *
2956 * Returns zero or a negative error code.
2957 */
01ef7dbf
IM		 2958static int dspxfr_image(struct hda_codec *codec,
2959 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2960 unsigned int reloc,
2961 unsigned int sample_rate,
2962 unsigned short channels,
01ef7dbf 2963 bool ovly)
95c6e9cb
IM		 2964{
2965 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2966 int status;
2967 unsigned short hda_format = 0;
2968 unsigned int response;
2969 unsigned char stream_id = 0;
2970 struct dma_engine *dma_engine;
2971 unsigned int dma_chan;
2972 unsigned int port_map_mask;
2973
2974 if (fls_data == NULL)
2975 return -EINVAL;
2976
2977 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2978 if (!dma_engine)
2979 return -ENOMEM;
95c6e9cb 2980
01ef7dbf
IM		 2981 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2982 if (!dma_engine->dmab) {
549e8292
TI		 2983 kfree(dma_engine);
2984 return -ENOMEM;
01ef7dbf 2985 }
95c6e9cb 2986
01ef7dbf 2987 dma_engine->codec = codec;
6194b99d 2988 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2989 dma_engine->m_converter_format = hda_format;
2990 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2991 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2992
8ae3124b 2993 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2994
2995 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2996 hda_format, &response);
2997
2998 if (status < 0) {
4e76a883 2999 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 3000 goto exit;
3001 }
3002
3003 status = snd_hda_codec_load_dsp_prepare(codec,
3004 dma_engine->m_converter_format,
3005 dma_engine->buf_size,
3006 dma_engine->dmab);
3007 if (status < 0)
95c6e9cb 3008 goto exit;
01ef7dbf
IM		 3009 spec->dsp_stream_id = status;
3010
3011 if (ovly) {
3012 status = dspio_alloc_dma_chan(codec, &dma_chan);
3013 if (status < 0) {
4e76a883 3014 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 3015 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 3016 goto exit;
3017 }
3018 }
95c6e9cb 3019
01ef7dbf
IM		 3020 port_map_mask = 0;
3021 status = dsp_allocate_ports_format(codec, hda_format,
3022 &port_map_mask);
3023 if (status < 0) {
4e76a883 3024 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 3025 goto exit;
3026 }
3027
3028 stream_id = dma_get_stream_id(dma_engine);
3029 status = codec_set_converter_stream_channel(codec,
3030 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3031 if (status < 0) {
4e76a883 3032 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 3033 goto exit;
3034 }
3035
3036 while ((fls_data != NULL) && !is_last(fls_data)) {
3037 if (!is_valid(fls_data)) {
4e76a883 3038 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 3039 status = -EINVAL;
3040 goto exit;
3041 }
3042 status = dspxfr_one_seg(codec, fls_data, reloc,
3043 dma_engine, dma_chan,
3044 port_map_mask, ovly);
3045 if (status < 0)
3046 break;
3047
3048 if (is_hci_prog_list_seg(fls_data))
3049 fls_data = get_next_seg_ptr(fls_data);
3050
3051 if ((fls_data != NULL) && !is_last(fls_data))
3052 fls_data = get_next_seg_ptr(fls_data);
3053 }
3054
3055 if (port_map_mask != 0)
3056 status = dsp_free_ports(codec);
3057
3058 if (status < 0)
95c6e9cb
IM		 3059 goto exit;
3060
01ef7dbf
IM		 3061 status = codec_set_converter_stream_channel(codec,
3062 WIDGET_CHIP_CTRL, 0, 0, &response);
3063
95c6e9cb 3064exit:
01ef7dbf
IM		 3065 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3066 dspio_free_dma_chan(codec, dma_chan);
3067
b3667bd7 3068 if (dma_engine->dmab->area)
01ef7dbf
IM		 3069 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3070 kfree(dma_engine->dmab);
3071 kfree(dma_engine);
3072
3073 return status;
95c6e9cb
IM		 3074}
3075
3076/*
01ef7dbf 3077 * CA0132 DSP download stuffs.
95c6e9cb 3078 */
01ef7dbf 3079static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 3080{
009b8f97 3081 struct ca0132_spec *spec = codec->spec;
4e76a883 3082 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 3083 if (!spec->use_alt_functions) {
3084 /*set DSP speaker to 2.0 configuration*/
3085 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3086 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 3087
009b8f97
CM		 3088 /*update write pointer*/
3089 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3090 }
01ef7dbf 3091}
95c6e9cb 3092
d5c21b88 3093/**
e60b2c7f 3094 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 3095 *
3096 * @codec: the HDA codec
3097 * @fls: pointer to a fast load image
3098 * @ovly: TRUE if overlay format is required
3099 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3100 * no relocation
3101 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3102 * @router_chans: number of audio router channels to be allocated (0 means use
3103 * internal defaults; max is 32)
3104 *
e60b2c7f
TI		 3105 * Download DSP from a DSP Image Fast Load structure. This structure is a
3106 * linear, non-constant sized element array of structures, each of which
3107 * contain the count of the data to be loaded, the data itself, and the
3108 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 3109 * Returns zero or a negative error code.
3110 */
01ef7dbf
IM		 3111static int dspload_image(struct hda_codec *codec,
3112 const struct dsp_image_seg *fls,
3113 bool ovly,
3114 unsigned int reloc,
3115 bool autostart,
3116 int router_chans)
3117{
3118 int status = 0;
e97249dd
IM		 3119 unsigned int sample_rate;
3120 unsigned short channels;
01ef7dbf 3121
4e76a883 3122 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 3123 if (router_chans == 0) {
3124 if (!ovly)
3125 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3126 else
3127 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3128 }
95c6e9cb 3129
e97249dd
IM		 3130 sample_rate = 48000;
3131 channels = (unsigned short)router_chans;
01ef7dbf 3132
e97249dd
IM		 3133 while (channels > 16) {
3134 sample_rate *= 2;
3135 channels /= 2;
01ef7dbf
IM		 3136 }
3137
01ef7dbf 3138 do {
4e76a883 3139 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3140 if (!ovly)
3141 status = dsp_reset(codec);
3142
3143 if (status < 0)
3144 break;
3145
4e76a883 3146 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3147 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3148 ovly);
01ef7dbf
IM		 3149
3150 if (status < 0)
3151 break;
3152
4e76a883 3153 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3154 if (autostart && !ovly) {
3155 dspload_post_setup(codec);
3156 status = dsp_set_run_state(codec);
3157 }
3158
4e76a883 3159 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3160 } while (0);
3161
3162 return status;
3163}
3164
f664417e 3165#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3166static bool dspload_is_loaded(struct hda_codec *codec)
3167{
3168 unsigned int data = 0;
3169 int status = 0;
3170
3171 status = chipio_read(codec, 0x40004, &data);
3172 if ((status < 0) || (data != 1))
3173 return false;
3174
3175 return true;
3176}
f664417e
TI		 3177#else
3178#define dspload_is_loaded(codec) false
3179#endif
01ef7dbf
IM		 3180
3181static bool dspload_wait_loaded(struct hda_codec *codec)
3182{
6d67530e 3183 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3184
3185 do {
01ef7dbf 3186 if (dspload_is_loaded(codec)) {
d9684bb5 3187 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3188 return true;
3189 }
6d67530e
IM		 3190 msleep(20);
3191 } while (time_before(jiffies, timeout));
01ef7dbf 3192
d9684bb5 3193 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3194 return false;
95c6e9cb
IM		 3195}
3196
e93ac30a 3197/*
b9b41345
CM		 3198 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3199 * based cards, and has a second mmio region, region2, that's used for special
3200 * commands.
e93ac30a
CM		 3201 */
3202
a62e4739
CM		 3203/*
3204 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3205 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3206 * The first eight bits are just the number of the pin. So far, I've only seen
3207 * this number go to 7.
b9b41345
CM		 3208 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3209 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3210 * then off to send that bit.
a62e4739 3211 */
b9b41345 3212static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
a62e4739
CM		 3213 bool enable)
3214{
3215 struct ca0132_spec *spec = codec->spec;
3216 unsigned short gpio_data;
3217
3218 gpio_data = gpio_pin & 0xF;
3219 gpio_data |= ((enable << 8) & 0x100);
3220
3221 writew(gpio_data, spec->mem_base + 0x320);
3222}
3223
b9b41345
CM		 3224/*
3225 * Special pci region2 commands that are only used by the AE-5. They follow
3226 * a set format, and require reads at certain points to seemingly 'clear'
3227 * the response data. My first tests didn't do these reads, and would cause
3228 * the card to get locked up until the memory was read. These commands
3229 * seem to work with three distinct values that I've taken to calling group,
3230 * target-id, and value.
3231 */
3232static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3233 unsigned int target, unsigned int value)
3234{
3235 struct ca0132_spec *spec = codec->spec;
3236 unsigned int write_val;
3237
3238 writel(0x0000007e, spec->mem_base + 0x210);
3239 readl(spec->mem_base + 0x210);
3240 writel(0x0000005a, spec->mem_base + 0x210);
3241 readl(spec->mem_base + 0x210);
3242 readl(spec->mem_base + 0x210);
3243
3244 writel(0x00800005, spec->mem_base + 0x20c);
3245 writel(group, spec->mem_base + 0x804);
3246
3247 writel(0x00800005, spec->mem_base + 0x20c);
3248 write_val = (target & 0xff);
3249 write_val |= (value << 8);
3250
3251
3252 writel(write_val, spec->mem_base + 0x204);
3253 /*
3254 * Need delay here or else it goes too fast and works inconsistently.
3255 */
3256 msleep(20);
3257
3258 readl(spec->mem_base + 0x860);
3259 readl(spec->mem_base + 0x854);
3260 readl(spec->mem_base + 0x840);
3261
3262 writel(0x00800004, spec->mem_base + 0x20c);
3263 writel(0x00000000, spec->mem_base + 0x210);
3264 readl(spec->mem_base + 0x210);
3265 readl(spec->mem_base + 0x210);
3266}
3267
212de2e7
CM		 3268/*
3269 * This second type of command is used for setting the sound filter type.
3270 */
3271static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3272 unsigned int group, unsigned int target, unsigned int value)
3273{
3274 struct ca0132_spec *spec = codec->spec;
3275 unsigned int write_val;
3276
3277 writel(0x0000007e, spec->mem_base + 0x210);
3278 readl(spec->mem_base + 0x210);
3279 writel(0x0000005a, spec->mem_base + 0x210);
3280 readl(spec->mem_base + 0x210);
3281 readl(spec->mem_base + 0x210);
3282
3283 writel(0x00800003, spec->mem_base + 0x20c);
3284 writel(group, spec->mem_base + 0x804);
3285
3286 writel(0x00800005, spec->mem_base + 0x20c);
3287 write_val = (target & 0xff);
3288 write_val |= (value << 8);
3289
3290
3291 writel(write_val, spec->mem_base + 0x204);
3292 msleep(20);
3293 readl(spec->mem_base + 0x860);
3294 readl(spec->mem_base + 0x854);
3295 readl(spec->mem_base + 0x840);
3296
3297 writel(0x00800004, spec->mem_base + 0x20c);
3298 writel(0x00000000, spec->mem_base + 0x210);
3299 readl(spec->mem_base + 0x210);
3300 readl(spec->mem_base + 0x210);
3301}
3302
b9b41345
CM		 3303/*
3304 * Setup GPIO for the other variants of Core3D.
3305 */
3306
e93ac30a
CM		 3307/*
3308 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3309 * the card shows as having no GPIO pins.
3310 */
3311static void ca0132_gpio_init(struct hda_codec *codec)
3312{
3313 struct ca0132_spec *spec = codec->spec;
3314
3315 switch (spec->quirk) {
3316 case QUIRK_SBZ:
03c9b6b1 3317 case QUIRK_AE5:
e93ac30a
CM		 3318 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3319 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3320 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3321 break;
3322 case QUIRK_R3DI:
3323 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3324 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3325 break;
3326 }
3327
3328}
3329
3330/* Sets the GPIO for audio output. */
3331static void ca0132_gpio_setup(struct hda_codec *codec)
3332{
3333 struct ca0132_spec *spec = codec->spec;
3334
3335 switch (spec->quirk) {
3336 case QUIRK_SBZ:
3337 snd_hda_codec_write(codec, 0x01, 0,
3338 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3339 snd_hda_codec_write(codec, 0x01, 0,
3340 AC_VERB_SET_GPIO_MASK, 0x07);
3341 snd_hda_codec_write(codec, 0x01, 0,
3342 AC_VERB_SET_GPIO_DATA, 0x04);
3343 snd_hda_codec_write(codec, 0x01, 0,
3344 AC_VERB_SET_GPIO_DATA, 0x06);
3345 break;
3346 case QUIRK_R3DI:
3347 snd_hda_codec_write(codec, 0x01, 0,
3348 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3349 snd_hda_codec_write(codec, 0x01, 0,
3350 AC_VERB_SET_GPIO_MASK, 0x1F);
3351 snd_hda_codec_write(codec, 0x01, 0,
3352 AC_VERB_SET_GPIO_DATA, 0x0C);
3353 break;
3354 }
3355}
3356
7e6ed62e
CM		 3357/*
3358 * GPIO control functions for the Recon3D integrated.
3359 */
3360
3361enum r3di_gpio_bit {
3362 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3363 R3DI_MIC_SELECT_BIT = 1,
3364 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3365 R3DI_OUT_SELECT_BIT = 2,
3366 /*
3367 * I dunno what this actually does, but it stays on until the dsp
3368 * is downloaded.
3369 */
3370 R3DI_GPIO_DSP_DOWNLOADING = 3,
3371 /*
3372 * Same as above, no clue what it does, but it comes on after the dsp
3373 * is downloaded.
3374 */
3375 R3DI_GPIO_DSP_DOWNLOADED = 4
3376};
3377
3378enum r3di_mic_select {
3379 /* Set GPIO bit 1 to 0 for rear mic */
3380 R3DI_REAR_MIC = 0,
3381 /* Set GPIO bit 1 to 1 for front microphone*/
3382 R3DI_FRONT_MIC = 1
3383};
3384
3385enum r3di_out_select {
3386 /* Set GPIO bit 2 to 0 for headphone */
3387 R3DI_HEADPHONE_OUT = 0,
3388 /* Set GPIO bit 2 to 1 for speaker */
3389 R3DI_LINE_OUT = 1
3390};
3391enum r3di_dsp_status {
3392 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3393 R3DI_DSP_DOWNLOADING = 0,
3394 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3395 R3DI_DSP_DOWNLOADED = 1
3396};
3397
7cb9d94c
CM		 3398
3399static void r3di_gpio_mic_set(struct hda_codec *codec,
3400 enum r3di_mic_select cur_mic)
3401{
3402 unsigned int cur_gpio;
3403
3404 /* Get the current GPIO Data setup */
3405 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3406
3407 switch (cur_mic) {
3408 case R3DI_REAR_MIC:
3409 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3410 break;
3411 case R3DI_FRONT_MIC:
3412 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3413 break;
3414 }
3415 snd_hda_codec_write(codec, codec->core.afg, 0,
3416 AC_VERB_SET_GPIO_DATA, cur_gpio);
3417}
3418
3419static void r3di_gpio_out_set(struct hda_codec *codec,
3420 enum r3di_out_select cur_out)
3421{
3422 unsigned int cur_gpio;
3423
3424 /* Get the current GPIO Data setup */
3425 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3426
3427 switch (cur_out) {
3428 case R3DI_HEADPHONE_OUT:
3429 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3430 break;
3431 case R3DI_LINE_OUT:
3432 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3433 break;
3434 }
3435 snd_hda_codec_write(codec, codec->core.afg, 0,
3436 AC_VERB_SET_GPIO_DATA, cur_gpio);
3437}
3438
7e6ed62e
CM		 3439static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3440 enum r3di_dsp_status dsp_status)
3441{
3442 unsigned int cur_gpio;
3443
3444 /* Get the current GPIO Data setup */
3445 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3446
3447 switch (dsp_status) {
3448 case R3DI_DSP_DOWNLOADING:
3449 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3450 snd_hda_codec_write(codec, codec->core.afg, 0,
3451 AC_VERB_SET_GPIO_DATA, cur_gpio);
3452 break;
3453 case R3DI_DSP_DOWNLOADED:
3454 /* Set DOWNLOADING bit to 0. */
3455 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3456
3457 snd_hda_codec_write(codec, codec->core.afg, 0,
3458 AC_VERB_SET_GPIO_DATA, cur_gpio);
3459
3460 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3461 break;
3462 }
3463
3464 snd_hda_codec_write(codec, codec->core.afg, 0,
3465 AC_VERB_SET_GPIO_DATA, cur_gpio);
3466}
3467
825315bc
IM		 3468/*
3469 * PCM callbacks
3470 */
95c6e9cb
IM		 3471static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3472 struct hda_codec *codec,
3473 unsigned int stream_tag,
3474 unsigned int format,
3475 struct snd_pcm_substream *substream)
3476{
3477 struct ca0132_spec *spec = codec->spec;
825315bc 3478
28fba950 3479 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3480
3481 return 0;
95c6e9cb
IM		 3482}
3483
3484static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3485 struct hda_codec *codec,
3486 struct snd_pcm_substream *substream)
3487{
3488 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3489
3490 if (spec->dsp_state == DSP_DOWNLOADING)
3491 return 0;
3492
3493 /*If Playback effects are on, allow stream some time to flush
3494 *effects tail*/
3495 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3496 msleep(50);
3497
28fba950 3498 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3499
3500 return 0;
95c6e9cb
IM		 3501}
3502
e8412ca4
DR		 3503static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3504 struct hda_codec *codec,
3505 struct snd_pcm_substream *substream)
3506{
3507 struct ca0132_spec *spec = codec->spec;
3508 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3509 struct snd_pcm_runtime *runtime = substream->runtime;
3510
3511 if (spec->dsp_state != DSP_DOWNLOADED)
3512 return 0;
3513
3514 /* Add latency if playback enhancement and either effect is enabled. */
3515 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3516 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3517 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3518 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3519 }
3520
3521 /* Applying Speaker EQ adds latency as well. */
3522 if (spec->cur_out_type == SPEAKER_OUT)
3523 latency += DSP_SPEAKER_OUT_LATENCY;
3524
3525 return (latency * runtime->rate) / 1000;
3526}
3527
95c6e9cb
IM		 3528/*
3529 * Digital out
3530 */
27ebeb0b
TI		 3531static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3532 struct hda_codec *codec,
3533 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3534{
3535 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3536 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3537}
3538
27ebeb0b 3539static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3540 struct hda_codec *codec,
3541 unsigned int stream_tag,
3542 unsigned int format,
3543 struct snd_pcm_substream *substream)
3544{
3545 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3546 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3547 stream_tag, format, substream);
95c6e9cb
IM		 3548}
3549
27ebeb0b 3550static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3551 struct hda_codec *codec,
95c6e9cb
IM		 3552 struct snd_pcm_substream *substream)
3553{
3554 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3555 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3556}
3557
27ebeb0b
TI		 3558static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3559 struct hda_codec *codec,
3560 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3561{
3562 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3563 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3564}
3565
825315bc
IM		 3566/*
3567 * Analog capture
3568 */
3569static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3570 struct hda_codec *codec,
3571 unsigned int stream_tag,
3572 unsigned int format,
3573 struct snd_pcm_substream *substream)
3574{
13c12dbe 3575 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3576 stream_tag, 0, format);
825315bc
IM		 3577
3578 return 0;
3579}
3580
3581static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3582 struct hda_codec *codec,
3583 struct snd_pcm_substream *substream)
3584{
3585 struct ca0132_spec *spec = codec->spec;
3586
3587 if (spec->dsp_state == DSP_DOWNLOADING)
3588 return 0;
3589
28fba950 3590 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3591 return 0;
3592}
3593
e8412ca4
DR		 3594static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3595 struct hda_codec *codec,
3596 struct snd_pcm_substream *substream)
3597{
3598 struct ca0132_spec *spec = codec->spec;
3599 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3600 struct snd_pcm_runtime *runtime = substream->runtime;
3601
3602 if (spec->dsp_state != DSP_DOWNLOADED)
3603 return 0;
3604
3605 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3606 latency += DSP_CRYSTAL_VOICE_LATENCY;
3607
3608 return (latency * runtime->rate) / 1000;
3609}
3610
e90f29e4
IM		 3611/*
3612 * Controls stuffs.
3613 */
3614
3615/*
3616 * Mixer controls helpers.
3617 */
3618#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3619 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3620 .name = xname, \
3621 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3622 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3623 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3624 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3625 .info = ca0132_volume_info, \
3626 .get = ca0132_volume_get, \
3627 .put = ca0132_volume_put, \
3628 .tlv = { .c = ca0132_volume_tlv }, \
3629 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3630
017310fb
CM		 3631/*
3632 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3633 * volume put, which is used for setting the DSP volume. This was done because
3634 * the ca0132 functions were taking too much time and causing lag.
3635 */
3636#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3637 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3638 .name = xname, \
3639 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3640 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3641 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3642 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3643 .info = snd_hda_mixer_amp_volume_info, \
3644 .get = snd_hda_mixer_amp_volume_get, \
3645 .put = ca0132_alt_volume_put, \
3646 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3647 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3648
e90f29e4
IM		 3649#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3650 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3651 .name = xname, \
3652 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3653 .info = snd_hda_mixer_amp_switch_info, \
3654 .get = ca0132_switch_get, \
3655 .put = ca0132_switch_put, \
3656 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3657
3658/* stereo */
3659#define CA0132_CODEC_VOL(xname, nid, dir) \
3660 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3661#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3662 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3663#define CA0132_CODEC_MUTE(xname, nid, dir) \
3664 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3665
017310fb
CM		 3666/* lookup tables */
3667/*
3668 * Lookup table with decibel values for the DSP. When volume is changed in
3669 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3670 * these values have decimal points, probably because the Windows driver
3671 * actually uses floating point. We can't here, so I made a lookup table of
3672 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3673 * DAC's, and 9 is the maximum.
3674 */
3675static const unsigned int float_vol_db_lookup[] = {
36760xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
36770xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
36780xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
36790xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
36800xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
36810xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
36820xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
36830xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
36840xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
36850xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
36860xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
36870xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
36880xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
36890xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
36900xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
36910x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
36920x40C00000, 0x40E00000, 0x41000000, 0x41100000
3693};
3694
47cdf76e
CM		 3695/*
3696 * This table counts from float 0 to 1 in increments of .01, which is
3697 * useful for a few different sliders.
3698 */
3699static const unsigned int float_zero_to_one_lookup[] = {
37000x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37010x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37020x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37030x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
37040x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
37050x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
37060x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
37070x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
37080x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
37090x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
37100x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
37110x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
37120x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
37130x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
37140x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
37150x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
37160x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3717};
3718
3719/*
3720 * This table counts from float 10 to 1000, which is the range of the x-bass
3721 * crossover slider in Windows.
3722 */
3723static const unsigned int float_xbass_xover_lookup[] = {
37240x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
37250x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
37260x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
37270x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
37280x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
37290x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
37300x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
37310x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
37320x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
37330x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
37340x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
37350x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
37360x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
37370x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
37380x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
37390x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
37400x44728000, 0x44750000, 0x44778000, 0x447A0000
3741};
3742
4091fb95 3743/* The following are for tuning of products */
44f0c978
IM		 3744#ifdef ENABLE_TUNING_CONTROLS
3745
3746static unsigned int voice_focus_vals_lookup[] = {
37470x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
37480x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
37490x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
37500x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
37510x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
37520x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
37530x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
37540x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
37550x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
37560x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
37570x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
37580x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
37590x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
37600x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
37610x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
37620x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
37630x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
37640x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
37650x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
37660x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
37670x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
37680x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
37690x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
37700x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
37710x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
37720x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
37730x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3774};
3775
3776static unsigned int mic_svm_vals_lookup[] = {
37770x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37780x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37790x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37800x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
37810x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
37820x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
37830x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
37840x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
37850x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
37860x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
37870x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
37880x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
37890x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
37900x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
37910x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
37920x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
37930x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3794};
3795
3796static unsigned int equalizer_vals_lookup[] = {
37970xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
37980xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
37990xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
38000xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
38010x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
38020x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
38030x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
38040x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
38050x41C00000
3806};
3807
3808static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3809 unsigned int *lookup, int idx)
3810{
3811 int i = 0;
3812
3813 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3814 if (nid == ca0132_tuning_ctls[i].nid)
3815 break;
3816
3817 snd_hda_power_up(codec);
447fd8e9 3818 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3819 ca0132_tuning_ctls[i].req,
3820 &(lookup[idx]), sizeof(unsigned int));
3821 snd_hda_power_down(codec);
3822
3823 return 1;
3824}
3825
3826static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3827 struct snd_ctl_elem_value *ucontrol)
3828{
3829 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3830 struct ca0132_spec *spec = codec->spec;
3831 hda_nid_t nid = get_amp_nid(kcontrol);
3832 long *valp = ucontrol->value.integer.value;
3833 int idx = nid - TUNING_CTL_START_NID;
3834
3835 *valp = spec->cur_ctl_vals[idx];
3836 return 0;
3837}
3838
3839static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3840 struct snd_ctl_elem_info *uinfo)
3841{
3842 int chs = get_amp_channels(kcontrol);
3843 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3844 uinfo->count = chs == 3 ? 2 : 1;
3845 uinfo->value.integer.min = 20;
3846 uinfo->value.integer.max = 180;
3847 uinfo->value.integer.step = 1;
3848
3849 return 0;
3850}
3851
3852static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3853 struct snd_ctl_elem_value *ucontrol)
3854{
3855 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3856 struct ca0132_spec *spec = codec->spec;
3857 hda_nid_t nid = get_amp_nid(kcontrol);
3858 long *valp = ucontrol->value.integer.value;
3859 int idx;
3860
3861 idx = nid - TUNING_CTL_START_NID;
3862 /* any change? */
3863 if (spec->cur_ctl_vals[idx] == *valp)
3864 return 0;
3865
3866 spec->cur_ctl_vals[idx] = *valp;
3867
3868 idx = *valp - 20;
3869 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3870
3871 return 1;
3872}
3873
3874static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3875 struct snd_ctl_elem_info *uinfo)
3876{
3877 int chs = get_amp_channels(kcontrol);
3878 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3879 uinfo->count = chs == 3 ? 2 : 1;
3880 uinfo->value.integer.min = 0;
3881 uinfo->value.integer.max = 100;
3882 uinfo->value.integer.step = 1;
3883
3884 return 0;
3885}
3886
3887static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3888 struct snd_ctl_elem_value *ucontrol)
3889{
3890 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3891 struct ca0132_spec *spec = codec->spec;
3892 hda_nid_t nid = get_amp_nid(kcontrol);
3893 long *valp = ucontrol->value.integer.value;
3894 int idx;
3895
3896 idx = nid - TUNING_CTL_START_NID;
3897 /* any change? */
3898 if (spec->cur_ctl_vals[idx] == *valp)
3899 return 0;
3900
3901 spec->cur_ctl_vals[idx] = *valp;
3902
3903 idx = *valp;
3904 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3905
3906 return 0;
3907}
3908
3909static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3910 struct snd_ctl_elem_info *uinfo)
3911{
3912 int chs = get_amp_channels(kcontrol);
3913 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3914 uinfo->count = chs == 3 ? 2 : 1;
3915 uinfo->value.integer.min = 0;
3916 uinfo->value.integer.max = 48;
3917 uinfo->value.integer.step = 1;
3918
3919 return 0;
3920}
3921
3922static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3923 struct snd_ctl_elem_value *ucontrol)
3924{
3925 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3926 struct ca0132_spec *spec = codec->spec;
3927 hda_nid_t nid = get_amp_nid(kcontrol);
3928 long *valp = ucontrol->value.integer.value;
3929 int idx;
3930
3931 idx = nid - TUNING_CTL_START_NID;
3932 /* any change? */
3933 if (spec->cur_ctl_vals[idx] == *valp)
3934 return 0;
3935
3936 spec->cur_ctl_vals[idx] = *valp;
3937
3938 idx = *valp;
3939 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3940
3941 return 1;
3942}
3943
8e142e9e
TS		 3944static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3945static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3946
3947static int add_tuning_control(struct hda_codec *codec,
3948 hda_nid_t pnid, hda_nid_t nid,
3949 const char *name, int dir)
3950{
975cc02a 3951 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3952 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3953 struct snd_kcontrol_new knew =
3954 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3955
3956 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3957 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3958 knew.tlv.c = 0;
3959 knew.tlv.p = 0;
3960 switch (pnid) {
3961 case VOICE_FOCUS:
3962 knew.info = voice_focus_ctl_info;
3963 knew.get = tuning_ctl_get;
3964 knew.put = voice_focus_ctl_put;
3965 knew.tlv.p = voice_focus_db_scale;
3966 break;
3967 case MIC_SVM:
3968 knew.info = mic_svm_ctl_info;
3969 knew.get = tuning_ctl_get;
3970 knew.put = mic_svm_ctl_put;
3971 break;
3972 case EQUALIZER:
3973 knew.info = equalizer_ctl_info;
3974 knew.get = tuning_ctl_get;
3975 knew.put = equalizer_ctl_put;
3976 knew.tlv.p = eq_db_scale;
3977 break;
3978 default:
3979 return 0;
3980 }
3981 knew.private_value =
3982 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3983 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3984 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3985}
3986
3987static int add_tuning_ctls(struct hda_codec *codec)
3988{
3989 int i;
3990 int err;
3991
3992 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3993 err = add_tuning_control(codec,
3994 ca0132_tuning_ctls[i].parent_nid,
3995 ca0132_tuning_ctls[i].nid,
3996 ca0132_tuning_ctls[i].name,
3997 ca0132_tuning_ctls[i].direct);
3998 if (err < 0)
3999 return err;
4000 }
4001
4002 return 0;
4003}
4004
4005static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4006{
4007 struct ca0132_spec *spec = codec->spec;
4008 int i;
4009
4010 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4011 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4012 /* SVM level defaults to 0.74. */
4013 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4014
4015 /* EQ defaults to 0dB. */
4016 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4017 spec->cur_ctl_vals[i] = 24;
4018}
4019#endif /*ENABLE_TUNING_CONTROLS*/
4020
5aaca44d
IM		 4021/*
4022 * Select the active output.
4023 * If autodetect is enabled, output will be selected based on jack detection.
4024 * If jack inserted, headphone will be selected, else built-in speakers
4025 * If autodetect is disabled, output will be selected based on selection.
4026 */
4027static int ca0132_select_out(struct hda_codec *codec)
4028{
4029 struct ca0132_spec *spec = codec->spec;
4030 unsigned int pin_ctl;
4031 int jack_present;
4032 int auto_jack;
4033 unsigned int tmp;
4034 int err;
4035
4e76a883 4036 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 4037
664c7155 4038 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4039
4040 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4041
4042 if (auto_jack)
fe14f39e 4043 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 4044 else
4045 jack_present =
4046 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4047
4048 if (jack_present)
4049 spec->cur_out_type = HEADPHONE_OUT;
4050 else
4051 spec->cur_out_type = SPEAKER_OUT;
4052
4053 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 4054 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 4055 /*speaker out config*/
4056 tmp = FLOAT_ONE;
4057 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4058 if (err < 0)
4059 goto exit;
4060 /*enable speaker EQ*/
4061 tmp = FLOAT_ONE;
4062 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4063 if (err < 0)
4064 goto exit;
4065
4066 /* Setup EAPD */
4067 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4068 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4069 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4070 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4071 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4072 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4073 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4074 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4075
4076 /* disable headphone node */
4077 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4078 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4079 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4080 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4081 /* enable speaker node */
4082 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 4083 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4084 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4085 pin_ctl | PIN_OUT);
5aaca44d 4086 } else {
4e76a883 4087 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 4088 /*headphone out config*/
4089 tmp = FLOAT_ZERO;
4090 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4091 if (err < 0)
4092 goto exit;
4093 /*disable speaker EQ*/
4094 tmp = FLOAT_ZERO;
4095 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4096 if (err < 0)
4097 goto exit;
4098
4099 /* Setup EAPD */
4100 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4101 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4102 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4103 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4104 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4105 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4106 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4107 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4108
4109 /* disable speaker*/
4110 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4111 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4112 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4113 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4114 /* enable headphone*/
4115 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4116 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4117 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4118 pin_ctl | PIN_HP);
5aaca44d
IM		 4119 }
4120
4121exit:
664c7155 4122 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4123
4124 return err < 0 ? err : 0;
4125}
4126
212de2e7
CM		 4127static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4128
2283c85b
CM		 4129static void ae5_mmio_select_out(struct hda_codec *codec)
4130{
4131 struct ca0132_spec *spec = codec->spec;
4132 unsigned int i;
4133
4134 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++)
4135 ca0113_mmio_command_set(codec,
4136 ae5_ca0113_output_presets[spec->cur_out_type].group[i],
4137 ae5_ca0113_output_presets[spec->cur_out_type].target[i],
4138 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]);
4139}
4140
746fc9de
CM		 4141/*
4142 * These are the commands needed to setup output on each of the different card
4143 * types.
4144 */
4145static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4146{
4147 struct ca0132_spec *spec = codec->spec;
2283c85b 4148 unsigned int tmp;
746fc9de
CM		 4149
4150 switch (spec->cur_out_type) {
4151 case SPEAKER_OUT:
4152 switch (spec->quirk) {
4153 case QUIRK_SBZ:
4154 ca0113_mmio_gpio_set(codec, 7, false);
4155 ca0113_mmio_gpio_set(codec, 4, true);
4156 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4157 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de
CM		 4158 break;
4159 case QUIRK_R3DI:
2283c85b 4160 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4161 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4162 break;
4163 case QUIRK_R3D:
2283c85b 4164 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4165 ca0113_mmio_gpio_set(codec, 1, true);
4166 break;
2283c85b
CM		 4167 case QUIRK_AE5:
4168 ae5_mmio_select_out(codec);
212de2e7 4169 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4170 tmp = FLOAT_ZERO;
4171 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4172 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4173 chipio_set_control_param(codec, 0x0d, 0xa4);
4174 chipio_write(codec, 0x18b03c, 0x00000012);
4175 break;
746fc9de
CM		 4176 }
4177 break;
4178 case HEADPHONE_OUT:
4179 switch (spec->quirk) {
4180 case QUIRK_SBZ:
4181 ca0113_mmio_gpio_set(codec, 7, true);
4182 ca0113_mmio_gpio_set(codec, 4, true);
4183 ca0113_mmio_gpio_set(codec, 1, false);
2283c85b 4184 chipio_set_control_param(codec, 0x0d, 0x12);
746fc9de
CM		 4185 break;
4186 case QUIRK_R3DI:
2283c85b 4187 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4188 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4189 break;
4190 case QUIRK_R3D:
2283c85b 4191 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4192 ca0113_mmio_gpio_set(codec, 0x1, false);
4193 break;
2283c85b
CM		 4194 case QUIRK_AE5:
4195 ae5_mmio_select_out(codec);
212de2e7
CM		 4196 ae5_headphone_gain_set(codec,
4197 spec->ae5_headphone_gain_val);
2283c85b
CM		 4198 tmp = FLOAT_ONE;
4199 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4200 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4201 chipio_set_control_param(codec, 0x0d, 0xa1);
4202 chipio_write(codec, 0x18b03c, 0x00000012);
4203 break;
746fc9de
CM		 4204 }
4205 break;
4206 case SURROUND_OUT:
4207 switch (spec->quirk) {
4208 case QUIRK_SBZ:
4209 ca0113_mmio_gpio_set(codec, 7, false);
4210 ca0113_mmio_gpio_set(codec, 4, true);
4211 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4212 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de
CM		 4213 break;
4214 case QUIRK_R3DI:
2283c85b 4215 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4216 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4217 break;
4218 case QUIRK_R3D:
4219 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b
CM		 4220 chipio_set_control_param(codec, 0x0d, 0x24);
4221 break;
4222 case QUIRK_AE5:
4223 ae5_mmio_select_out(codec);
212de2e7 4224 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4225 tmp = FLOAT_ZERO;
4226 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4227 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4228 chipio_set_control_param(codec, 0x0d, 0xa4);
4229 chipio_write(codec, 0x18b03c, 0x00000012);
746fc9de
CM		 4230 break;
4231 }
4232 break;
4233 }
4234}
4235
7cb9d94c
CM		 4236/*
4237 * This function behaves similarly to the ca0132_select_out funciton above,
4238 * except with a few differences. It adds the ability to select the current
4239 * output with an enumerated control "output source" if the auto detect
4240 * mute switch is set to off. If the auto detect mute switch is enabled, it
4241 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4242 * It also adds the ability to auto-detect the front headphone port. The only
4243 * way to select surround is to disable auto detect, and set Surround with the
4244 * enumerated control.
4245 */
4246static int ca0132_alt_select_out(struct hda_codec *codec)
4247{
4248 struct ca0132_spec *spec = codec->spec;
4249 unsigned int pin_ctl;
4250 int jack_present;
4251 int auto_jack;
4252 unsigned int i;
4253 unsigned int tmp;
4254 int err;
4255 /* Default Headphone is rear headphone */
4256 hda_nid_t headphone_nid = spec->out_pins[1];
4257
4258 codec_dbg(codec, "%s\n", __func__);
4259
4260 snd_hda_power_up_pm(codec);
4261
4262 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4263
4264 /*
4265 * If headphone rear or front is plugged in, set to headphone.
4266 * If neither is plugged in, set to rear line out. Only if
4267 * hp/speaker auto detect is enabled.
4268 */
4269 if (auto_jack) {
4270 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4271 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4272
4273 if (jack_present)
4274 spec->cur_out_type = HEADPHONE_OUT;
4275 else
4276 spec->cur_out_type = SPEAKER_OUT;
4277 } else
4278 spec->cur_out_type = spec->out_enum_val;
4279
4280 /* Begin DSP output switch */
4281 tmp = FLOAT_ONE;
4282 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4283 if (err < 0)
4284 goto exit;
4285
746fc9de
CM		 4286 ca0132_alt_select_out_quirk_handler(codec);
4287
7cb9d94c
CM		 4288 switch (spec->cur_out_type) {
4289 case SPEAKER_OUT:
4290 codec_dbg(codec, "%s speaker\n", __func__);
7cb9d94c
CM		 4291
4292 /* disable headphone node */
4293 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4294 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4295 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4296 pin_ctl & ~PIN_HP);
4297 /* enable line-out node */
4298 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4299 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4300 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4301 pin_ctl | PIN_OUT);
4302 /* Enable EAPD */
4303 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4304 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4305
4306 /* If PlayEnhancement is enabled, set different source */
4307 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4308 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4309 else
4310 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4311 break;
4312 case HEADPHONE_OUT:
4313 codec_dbg(codec, "%s hp\n", __func__);
7cb9d94c
CM		 4314
4315 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4316 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4317
4318 /* disable speaker*/
4319 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4320 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4321 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4322 pin_ctl & ~PIN_HP);
4323
4324 /* enable headphone, either front or rear */
4325
4326 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4327 headphone_nid = spec->out_pins[2];
4328 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4329 headphone_nid = spec->out_pins[1];
4330
4331 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4332 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4333 snd_hda_set_pin_ctl(codec, headphone_nid,
4334 pin_ctl | PIN_HP);
4335
4336 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4337 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4338 else
4339 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4340 break;
4341 case SURROUND_OUT:
4342 codec_dbg(codec, "%s surround\n", __func__);
746fc9de 4343
7cb9d94c
CM		 4344 /* enable line out node */
4345 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4346 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4347 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4348 pin_ctl | PIN_OUT);
4349 /* Disable headphone out */
4350 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4351 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4352 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4353 pin_ctl & ~PIN_HP);
4354 /* Enable EAPD on line out */
4355 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4356 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4357 /* enable center/lfe out node */
4358 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4359 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4360 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4361 pin_ctl | PIN_OUT);
4362 /* Now set rear surround node as out. */
4363 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4364 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4365 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4366 pin_ctl | PIN_OUT);
4367
4368 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4369 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4370 else
4371 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4372 break;
4373 }
4374
2283c85b 4375 /* run through the output dsp commands for the selected output. */
7cb9d94c
CM		 4376 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4377 err = dspio_set_uint_param(codec,
4378 alt_out_presets[spec->cur_out_type].mids[i],
4379 alt_out_presets[spec->cur_out_type].reqs[i],
4380 alt_out_presets[spec->cur_out_type].vals[i]);
4381
4382 if (err < 0)
4383 goto exit;
4384 }
4385
4386exit:
4387 snd_hda_power_down_pm(codec);
4388
4389 return err < 0 ? err : 0;
4390}
4391
993884f6
CCC		 4392static void ca0132_unsol_hp_delayed(struct work_struct *work)
4393{
4394 struct ca0132_spec *spec = container_of(
4395 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4396 struct hda_jack_tbl *jack;
4397
7cb9d94c
CM		 4398 if (spec->use_alt_functions)
4399 ca0132_alt_select_out(spec->codec);
4400 else
4401 ca0132_select_out(spec->codec);
4402
d5c016b5 4403 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4404 if (jack) {
4405 jack->block_report = 0;
4406 snd_hda_jack_report_sync(spec->codec);
4407 }
993884f6
CCC		 4408}
4409
5aaca44d
IM		 4410static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4411static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4412static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
e0026d03
CM		 4413static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4414static int stop_mic1(struct hda_codec *codec);
4415static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4416static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4417
4418/*
4419 * Select the active VIP source
4420 */
4421static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4422{
4423 struct ca0132_spec *spec = codec->spec;
4424 unsigned int tmp;
4425
e8f1bd5d 4426 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4427 return 0;
4428
4429 /* if CrystalVoice if off, vipsource should be 0 */
4430 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4431 (val == 0)) {
4432 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4433 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4434 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4435 if (spec->cur_mic_type == DIGITAL_MIC)
4436 tmp = FLOAT_TWO;
4437 else
4438 tmp = FLOAT_ONE;
4439 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4440 tmp = FLOAT_ZERO;
4441 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4442 } else {
4443 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4444 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4445 if (spec->cur_mic_type == DIGITAL_MIC)
4446 tmp = FLOAT_TWO;
4447 else
4448 tmp = FLOAT_ONE;
4449 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4450 tmp = FLOAT_ONE;
4451 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4452 msleep(20);
4453 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4454 }
4455
4456 return 1;
4457}
4458
e0026d03
CM		 4459static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4460{
4461 struct ca0132_spec *spec = codec->spec;
4462 unsigned int tmp;
4463
4464 if (spec->dsp_state != DSP_DOWNLOADED)
4465 return 0;
4466
4467 codec_dbg(codec, "%s\n", __func__);
4468
4469 chipio_set_stream_control(codec, 0x03, 0);
4470 chipio_set_stream_control(codec, 0x04, 0);
4471
4472 /* if CrystalVoice is off, vipsource should be 0 */
4473 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4474 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4475 codec_dbg(codec, "%s: off.", __func__);
4476 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4477
4478 tmp = FLOAT_ZERO;
4479 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4480
4481 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4482 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4483 if (spec->quirk == QUIRK_R3DI)
4484 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4485
4486
4487 if (spec->in_enum_val == REAR_LINE_IN)
4488 tmp = FLOAT_ZERO;
4489 else {
4490 if (spec->quirk == QUIRK_SBZ)
4491 tmp = FLOAT_THREE;
4492 else
4493 tmp = FLOAT_ONE;
4494 }
4495
4496 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4497
4498 } else {
4499 codec_dbg(codec, "%s: on.", __func__);
4500 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4501 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4502 if (spec->quirk == QUIRK_R3DI)
4503 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4504
4505 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4506 tmp = FLOAT_TWO;
4507 else
4508 tmp = FLOAT_ONE;
4509 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4510
4511 tmp = FLOAT_ONE;
4512 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4513
4514 msleep(20);
4515 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4516 }
4517
4518 chipio_set_stream_control(codec, 0x03, 1);
4519 chipio_set_stream_control(codec, 0x04, 1);
4520
4521 return 1;
4522}
4523
5aaca44d
IM		 4524/*
4525 * Select the active microphone.
4526 * If autodetect is enabled, mic will be selected based on jack detection.
4527 * If jack inserted, ext.mic will be selected, else built-in mic
4528 * If autodetect is disabled, mic will be selected based on selection.
4529 */
4530static int ca0132_select_mic(struct hda_codec *codec)
4531{
4532 struct ca0132_spec *spec = codec->spec;
4533 int jack_present;
4534 int auto_jack;
4535
4e76a883 4536 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4537
664c7155 4538 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4539
4540 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4541
4542 if (auto_jack)
fe14f39e 4543 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4544 else
4545 jack_present =
4546 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4547
4548 if (jack_present)
4549 spec->cur_mic_type = LINE_MIC_IN;
4550 else
4551 spec->cur_mic_type = DIGITAL_MIC;
4552
4553 if (spec->cur_mic_type == DIGITAL_MIC) {
4554 /* enable digital Mic */
4555 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4556 ca0132_set_dmic(codec, 1);
4557 ca0132_mic_boost_set(codec, 0);
4558 /* set voice focus */
4559 ca0132_effects_set(codec, VOICE_FOCUS,
4560 spec->effects_switch
4561 [VOICE_FOCUS - EFFECT_START_NID]);
4562 } else {
4563 /* disable digital Mic */
4564 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4565 ca0132_set_dmic(codec, 0);
4566 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4567 /* disable voice focus */
4568 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4569 }
4570
664c7155 4571 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4572
4573 return 0;
4574}
4575
7cb9d94c
CM		 4576/*
4577 * Select the active input.
4578 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4579 * The front mic has no jack-detection, so the only way to switch to it
4580 * is to do it manually in alsamixer.
4581 */
4582static int ca0132_alt_select_in(struct hda_codec *codec)
4583{
4584 struct ca0132_spec *spec = codec->spec;
4585 unsigned int tmp;
4586
4587 codec_dbg(codec, "%s\n", __func__);
4588
4589 snd_hda_power_up_pm(codec);
4590
4591 chipio_set_stream_control(codec, 0x03, 0);
4592 chipio_set_stream_control(codec, 0x04, 0);
4593
4594 spec->cur_mic_type = spec->in_enum_val;
4595
4596 switch (spec->cur_mic_type) {
4597 case REAR_MIC:
4598 switch (spec->quirk) {
4599 case QUIRK_SBZ:
42aa3a16 4600 case QUIRK_R3D:
b9b41345 4601 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4602 tmp = FLOAT_THREE;
4603 break;
4604 case QUIRK_R3DI:
4605 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4606 tmp = FLOAT_ONE;
4607 break;
f231daaf
CM		 4608 case QUIRK_AE5:
4609 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4610 tmp = FLOAT_THREE;
4611 break;
7cb9d94c
CM		 4612 default:
4613 tmp = FLOAT_ONE;
4614 break;
4615 }
4616
4617 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4618 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4619 if (spec->quirk == QUIRK_R3DI)
4620 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4621
4622 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4623
4624 chipio_set_stream_control(codec, 0x03, 1);
4625 chipio_set_stream_control(codec, 0x04, 1);
f231daaf
CM		 4626 switch (spec->quirk) {
4627 case QUIRK_SBZ:
7cb9d94c
CM		 4628 chipio_write(codec, 0x18B098, 0x0000000C);
4629 chipio_write(codec, 0x18B09C, 0x0000000C);
f231daaf
CM		 4630 break;
4631 case QUIRK_AE5:
4632 chipio_write(codec, 0x18B098, 0x0000000C);
4633 chipio_write(codec, 0x18B09C, 0x0000004C);
4634 break;
7cb9d94c 4635 }
47cdf76e 4636 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4637 break;
4638 case REAR_LINE_IN:
4639 ca0132_mic_boost_set(codec, 0);
4640 switch (spec->quirk) {
4641 case QUIRK_SBZ:
42aa3a16 4642 case QUIRK_R3D:
b9b41345 4643 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4644 break;
4645 case QUIRK_R3DI:
4646 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4647 break;
f231daaf
CM		 4648 case QUIRK_AE5:
4649 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4650 break;
7cb9d94c
CM		 4651 }
4652
4653 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4654 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4655 if (spec->quirk == QUIRK_R3DI)
4656 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4657
4658 tmp = FLOAT_ZERO;
4659 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4660
f231daaf
CM		 4661 switch (spec->quirk) {
4662 case QUIRK_SBZ:
4663 case QUIRK_AE5:
7cb9d94c
CM		 4664 chipio_write(codec, 0x18B098, 0x00000000);
4665 chipio_write(codec, 0x18B09C, 0x00000000);
f231daaf 4666 break;
7cb9d94c 4667 }
7cb9d94c
CM		 4668 chipio_set_stream_control(codec, 0x03, 1);
4669 chipio_set_stream_control(codec, 0x04, 1);
4670 break;
4671 case FRONT_MIC:
4672 switch (spec->quirk) {
4673 case QUIRK_SBZ:
42aa3a16 4674 case QUIRK_R3D:
b9b41345
CM		 4675 ca0113_mmio_gpio_set(codec, 0, true);
4676 ca0113_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4677 tmp = FLOAT_THREE;
4678 break;
4679 case QUIRK_R3DI:
4680 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4681 tmp = FLOAT_ONE;
4682 break;
f231daaf
CM		 4683 case QUIRK_AE5:
4684 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f);
4685 tmp = FLOAT_THREE;
4686 break;
7cb9d94c
CM		 4687 default:
4688 tmp = FLOAT_ONE;
4689 break;
4690 }
4691
4692 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4693 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4694 if (spec->quirk == QUIRK_R3DI)
4695 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4696
4697 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4698
4699 chipio_set_stream_control(codec, 0x03, 1);
4700 chipio_set_stream_control(codec, 0x04, 1);
4701
f231daaf
CM		 4702 switch (spec->quirk) {
4703 case QUIRK_SBZ:
7cb9d94c
CM		 4704 chipio_write(codec, 0x18B098, 0x0000000C);
4705 chipio_write(codec, 0x18B09C, 0x000000CC);
f231daaf
CM		 4706 break;
4707 case QUIRK_AE5:
4708 chipio_write(codec, 0x18B098, 0x0000000C);
4709 chipio_write(codec, 0x18B09C, 0x0000004C);
4710 break;
7cb9d94c 4711 }
47cdf76e 4712 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4713 break;
4714 }
e0026d03 4715 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4716
4717 snd_hda_power_down_pm(codec);
4718 return 0;
7cb9d94c
CM		 4719}
4720
a7e76271
IM		 4721/*
4722 * Check if VNODE settings take effect immediately.
4723 */
4724static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4725 hda_nid_t vnid,
4726 hda_nid_t *shared_nid)
4727{
4728 struct ca0132_spec *spec = codec->spec;
4729 hda_nid_t nid;
a7e76271
IM		 4730
4731 switch (vnid) {
4732 case VNID_SPK:
4733 nid = spec->shared_out_nid;
a7e76271
IM		 4734 break;
4735 case VNID_MIC:
4736 nid = spec->shared_mic_nid;
a7e76271
IM		 4737 break;
4738 default:
9a0869f4 4739 return false;
a7e76271
IM		 4740 }
4741
9a0869f4 4742 if (shared_nid)
a7e76271
IM		 4743 *shared_nid = nid;
4744
9a0869f4 4745 return true;
a7e76271
IM		 4746}
4747
4748/*
4749* The following functions are control change helpers.
4750* They return 0 if no changed. Return 1 if changed.
4751*/
4752static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4753{
4754 struct ca0132_spec *spec = codec->spec;
4755 unsigned int tmp;
4756
4757 /* based on CrystalVoice state to enable VoiceFX. */
4758 if (enable) {
4759 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4760 FLOAT_ONE : FLOAT_ZERO;
4761 } else {
4762 tmp = FLOAT_ZERO;
4763 }
4764
4765 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4766 ca0132_voicefx.reqs[0], tmp);
4767
4768 return 1;
4769}
4770
5aaca44d
IM		 4771/*
4772 * Set the effects parameters
4773 */
4774static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4775{
4776 struct ca0132_spec *spec = codec->spec;
009b8f97 4777 unsigned int on, tmp;
5aaca44d
IM		 4778 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4779 int err = 0;
4780 int idx = nid - EFFECT_START_NID;
4781
4782 if ((idx < 0) || (idx >= num_fx))
4783 return 0; /* no changed */
4784
4785 /* for out effect, qualify with PE */
4786 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4787 /* if PE if off, turn off out effects. */
4788 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4789 val = 0;
4790 }
4791
4792 /* for in effect, qualify with CrystalVoice */
4793 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4794 /* if CrystalVoice if off, turn off in effects. */
4795 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4796 val = 0;
4797
4798 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4799 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4800 val = 0;
009b8f97
CM		 4801
4802 /* If Voice Focus on SBZ, set to two channel. */
7cb9d94c
CM		 4803 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4804 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4805 if (spec->effects_switch[CRYSTAL_VOICE -
4806 EFFECT_START_NID]) {
4807
4808 if (spec->effects_switch[VOICE_FOCUS -
4809 EFFECT_START_NID]) {
4810 tmp = FLOAT_TWO;
4811 val = 1;
4812 } else
4813 tmp = FLOAT_ONE;
4814
4815 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4816 }
4817 }
4818 /*
4819 * For SBZ noise reduction, there's an extra command
4820 * to module ID 0x47. No clue why.
4821 */
7cb9d94c
CM		 4822 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4823 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4824 if (spec->effects_switch[CRYSTAL_VOICE -
4825 EFFECT_START_NID]) {
4826 if (spec->effects_switch[NOISE_REDUCTION -
4827 EFFECT_START_NID])
4828 tmp = FLOAT_ONE;
4829 else
4830 tmp = FLOAT_ZERO;
4831 } else
4832 tmp = FLOAT_ZERO;
4833
4834 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4835 }
7cb9d94c
CM		 4836
4837 /* If rear line in disable effects. */
4838 if (spec->use_alt_functions &&
4839 spec->in_enum_val == REAR_LINE_IN)
4840 val = 0;
5aaca44d
IM		 4841 }
4842
4e76a883 4843 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4844 nid, val);
4845
4846 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4847 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4848 ca0132_effects[idx].reqs[0], on);
4849
4850 if (err < 0)
4851 return 0; /* no changed */
4852
4853 return 1;
4854}
4855
a7e76271
IM		 4856/*
4857 * Turn on/off Playback Enhancements
4858 */
4859static int ca0132_pe_switch_set(struct hda_codec *codec)
4860{
4861 struct ca0132_spec *spec = codec->spec;
4862 hda_nid_t nid;
4863 int i, ret = 0;
4864
4e76a883 4865 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4866 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4867
7cb9d94c
CM		 4868 if (spec->use_alt_functions)
4869 ca0132_alt_select_out(codec);
4870
a7e76271
IM		 4871 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4872 nid = OUT_EFFECT_START_NID;
4873 /* PE affects all out effects */
4874 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4875 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4876
4877 return ret;
4878}
4879
5aaca44d
IM		 4880/* Check if Mic1 is streaming, if so, stop streaming */
4881static int stop_mic1(struct hda_codec *codec)
4882{
4883 struct ca0132_spec *spec = codec->spec;
4884 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4885 AC_VERB_GET_CONV, 0);
4886 if (oldval != 0)
4887 snd_hda_codec_write(codec, spec->adcs[0], 0,
4888 AC_VERB_SET_CHANNEL_STREAMID,
4889 0);
4890 return oldval;
4891}
4892
4893/* Resume Mic1 streaming if it was stopped. */
4894static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4895{
4896 struct ca0132_spec *spec = codec->spec;
4897 /* Restore the previous stream and channel */
4898 if (oldval != 0)
4899 snd_hda_codec_write(codec, spec->adcs[0], 0,
4900 AC_VERB_SET_CHANNEL_STREAMID,
4901 oldval);
4902}
4903
4904/*
a7e76271 4905 * Turn on/off CrystalVoice
5aaca44d 4906 */
a7e76271
IM		 4907static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4908{
4909 struct ca0132_spec *spec = codec->spec;
4910 hda_nid_t nid;
4911 int i, ret = 0;
4912 unsigned int oldval;
4913
4e76a883 4914 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4915 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4916
4917 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4918 nid = IN_EFFECT_START_NID;
4919 /* CrystalVoice affects all in effects */
4920 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4921 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4922
4923 /* including VoiceFX */
4924 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4925
4926 /* set correct vipsource */
4927 oldval = stop_mic1(codec);
e0026d03
CM		 4928 if (spec->use_alt_functions)
4929 ret |= ca0132_alt_set_vipsource(codec, 1);
4930 else
4931 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 4932 resume_mic1(codec, oldval);
4933 return ret;
4934}
4935
5aaca44d
IM		 4936static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4937{
4938 struct ca0132_spec *spec = codec->spec;
4939 int ret = 0;
4940
4941 if (val) /* on */
4942 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4943 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4944 else /* off */
4945 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4946 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4947
4948 return ret;
4949}
4950
47cdf76e
CM		 4951static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4952{
4953 struct ca0132_spec *spec = codec->spec;
4954 int ret = 0;
4955
4956 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4957 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4958 return ret;
4959}
4960
212de2e7
CM		 4961static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
4962{
4963 unsigned int i;
4964
4965 for (i = 0; i < 4; i++)
4966 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
4967 ae5_headphone_gain_presets[val].vals[i]);
4968 return 0;
4969}
4970
a7e76271
IM		 4971static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4972 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 4973{
a7e76271
IM		 4974 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4975 hda_nid_t nid = get_amp_nid(kcontrol);
4976 hda_nid_t shared_nid = 0;
4977 bool effective;
4978 int ret = 0;
95c6e9cb 4979 struct ca0132_spec *spec = codec->spec;
a7e76271 4980 int auto_jack;
95c6e9cb 4981
a7e76271
IM		 4982 if (nid == VNID_HP_SEL) {
4983 auto_jack =
4984 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 4985 if (!auto_jack) {
4986 if (spec->use_alt_functions)
4987 ca0132_alt_select_out(codec);
4988 else
4989 ca0132_select_out(codec);
4990 }
a7e76271
IM		 4991 return 1;
4992 }
95c6e9cb 4993
a7e76271
IM		 4994 if (nid == VNID_AMIC1_SEL) {
4995 auto_jack =
4996 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4997 if (!auto_jack)
4998 ca0132_select_mic(codec);
4999 return 1;
5000 }
95c6e9cb 5001
a7e76271 5002 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 5003 if (spec->use_alt_functions)
5004 ca0132_alt_select_out(codec);
5005 else
5006 ca0132_select_out(codec);
a7e76271
IM		 5007 return 1;
5008 }
95c6e9cb 5009
a7e76271
IM		 5010 if (nid == VNID_AMIC1_ASEL) {
5011 ca0132_select_mic(codec);
5012 return 1;
95c6e9cb 5013 }
a7e76271
IM		 5014
5015 /* if effective conditions, then update hw immediately. */
5016 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5017 if (effective) {
5018 int dir = get_amp_direction(kcontrol);
5019 int ch = get_amp_channels(kcontrol);
5020 unsigned long pval;
5021
5022 mutex_lock(&codec->control_mutex);
5023 pval = kcontrol->private_value;
5024 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5025 0, dir);
5026 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5027 kcontrol->private_value = pval;
5028 mutex_unlock(&codec->control_mutex);
95c6e9cb 5029 }
95c6e9cb 5030
a7e76271 5031 return ret;
95c6e9cb 5032}
a7e76271 5033/* End of control change helpers. */
47cdf76e
CM		 5034/*
5035 * Below I've added controls to mess with the effect levels, I've only enabled
5036 * them on the Sound Blaster Z, but they would probably also work on the
5037 * Chromebook. I figured they were probably tuned specifically for it, and left
5038 * out for a reason.
5039 */
5040
5041/* Sets DSP effect level from the sliders above the controls */
5042static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5043 const unsigned int *lookup, int idx)
5044{
5045 int i = 0;
5046 unsigned int y;
5047 /*
5048 * For X_BASS, req 2 is actually crossover freq instead of
5049 * effect level
5050 */
5051 if (nid == X_BASS)
5052 y = 2;
5053 else
5054 y = 1;
5055
5056 snd_hda_power_up(codec);
5057 if (nid == XBASS_XOVER) {
5058 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5059 if (ca0132_effects[i].nid == X_BASS)
5060 break;
5061
5062 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5063 ca0132_effects[i].reqs[1],
5064 &(lookup[idx - 1]), sizeof(unsigned int));
5065 } else {
5066 /* Find the actual effect structure */
5067 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5068 if (nid == ca0132_effects[i].nid)
5069 break;
5070
5071 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5072 ca0132_effects[i].reqs[y],
5073 &(lookup[idx]), sizeof(unsigned int));
5074 }
5075
5076 snd_hda_power_down(codec);
5077
5078 return 0;
5079}
5080
5081static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5082 struct snd_ctl_elem_value *ucontrol)
5083{
5084 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5085 struct ca0132_spec *spec = codec->spec;
5086 long *valp = ucontrol->value.integer.value;
5087
5088 *valp = spec->xbass_xover_freq;
5089 return 0;
5090}
5091
5092static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5093 struct snd_ctl_elem_value *ucontrol)
5094{
5095 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5096 struct ca0132_spec *spec = codec->spec;
5097 hda_nid_t nid = get_amp_nid(kcontrol);
5098 long *valp = ucontrol->value.integer.value;
5099 int idx = nid - OUT_EFFECT_START_NID;
5100
5101 *valp = spec->fx_ctl_val[idx];
5102 return 0;
5103}
5104
5105/*
5106 * The X-bass crossover starts at 10hz, so the min is 1. The
5107 * frequency is set in multiples of 10.
5108 */
5109static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5110 struct snd_ctl_elem_info *uinfo)
5111{
5112 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5113 uinfo->count = 1;
5114 uinfo->value.integer.min = 1;
5115 uinfo->value.integer.max = 100;
5116 uinfo->value.integer.step = 1;
5117
5118 return 0;
5119}
5120
5121static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5122 struct snd_ctl_elem_info *uinfo)
5123{
5124 int chs = get_amp_channels(kcontrol);
5125
5126 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5127 uinfo->count = chs == 3 ? 2 : 1;
5128 uinfo->value.integer.min = 0;
5129 uinfo->value.integer.max = 100;
5130 uinfo->value.integer.step = 1;
5131
5132 return 0;
5133}
5134
5135static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5136 struct snd_ctl_elem_value *ucontrol)
5137{
5138 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5139 struct ca0132_spec *spec = codec->spec;
5140 hda_nid_t nid = get_amp_nid(kcontrol);
5141 long *valp = ucontrol->value.integer.value;
5142 int idx;
5143
5144 /* any change? */
5145 if (spec->xbass_xover_freq == *valp)
5146 return 0;
5147
5148 spec->xbass_xover_freq = *valp;
5149
5150 idx = *valp;
5151 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5152
5153 return 0;
5154}
5155
5156static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5157 struct snd_ctl_elem_value *ucontrol)
5158{
5159 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5160 struct ca0132_spec *spec = codec->spec;
5161 hda_nid_t nid = get_amp_nid(kcontrol);
5162 long *valp = ucontrol->value.integer.value;
5163 int idx;
5164
5165 idx = nid - EFFECT_START_NID;
5166 /* any change? */
5167 if (spec->fx_ctl_val[idx] == *valp)
5168 return 0;
5169
5170 spec->fx_ctl_val[idx] = *valp;
5171
5172 idx = *valp;
5173 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5174
5175 return 0;
5176}
5177
5178
5179/*
5180 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5181 * only has off or full 30 dB, and didn't like making a volume slider that has
5182 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5183 */
5184#define MIC_BOOST_NUM_OF_STEPS 4
5185#define MIC_BOOST_ENUM_MAX_STRLEN 10
5186
5187static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5188 struct snd_ctl_elem_info *uinfo)
5189{
5190 char *sfx = "dB";
5191 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5192
5193 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5194 uinfo->count = 1;
5195 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5196 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5197 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5198 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5199 strcpy(uinfo->value.enumerated.name, namestr);
5200 return 0;
5201}
5202
5203static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5204 struct snd_ctl_elem_value *ucontrol)
5205{
5206 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5207 struct ca0132_spec *spec = codec->spec;
5208
5209 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5210 return 0;
5211}
5212
5213static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5214 struct snd_ctl_elem_value *ucontrol)
5215{
5216 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5217 struct ca0132_spec *spec = codec->spec;
5218 int sel = ucontrol->value.enumerated.item[0];
5219 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5220
5221 if (sel >= items)
5222 return 0;
5223
5224 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5225 sel);
5226
5227 spec->mic_boost_enum_val = sel;
5228
5229 if (spec->in_enum_val != REAR_LINE_IN)
5230 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5231
5232 return 1;
5233}
5234
212de2e7
CM		 5235/*
5236 * Sound BlasterX AE-5 Headphone Gain Controls.
5237 */
5238#define AE5_HEADPHONE_GAIN_MAX 3
5239static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5240 struct snd_ctl_elem_info *uinfo)
5241{
5242 char *sfx = " Ohms)";
5243 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5244
5245 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5246 uinfo->count = 1;
5247 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5248 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5249 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5250 sprintf(namestr, "%s %s",
5251 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5252 sfx);
5253 strcpy(uinfo->value.enumerated.name, namestr);
5254 return 0;
5255}
5256
5257static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5258 struct snd_ctl_elem_value *ucontrol)
5259{
5260 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5261 struct ca0132_spec *spec = codec->spec;
5262
5263 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5264 return 0;
5265}
5266
5267static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5268 struct snd_ctl_elem_value *ucontrol)
5269{
5270 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5271 struct ca0132_spec *spec = codec->spec;
5272 int sel = ucontrol->value.enumerated.item[0];
5273 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5274
5275 if (sel >= items)
5276 return 0;
5277
5278 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5279 sel);
5280
5281 spec->ae5_headphone_gain_val = sel;
5282
5283 if (spec->out_enum_val == HEADPHONE_OUT)
5284 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5285
5286 return 1;
5287}
5288
5289/*
5290 * Sound BlasterX AE-5 sound filter enumerated control.
5291 */
5292#define AE5_SOUND_FILTER_MAX 3
5293
5294static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5295 struct snd_ctl_elem_info *uinfo)
5296{
5297 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5298
5299 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5300 uinfo->count = 1;
5301 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5302 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5303 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5304 sprintf(namestr, "%s",
5305 ae5_filter_presets[uinfo->value.enumerated.item].name);
5306 strcpy(uinfo->value.enumerated.name, namestr);
5307 return 0;
5308}
5309
5310static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5311 struct snd_ctl_elem_value *ucontrol)
5312{
5313 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5314 struct ca0132_spec *spec = codec->spec;
5315
5316 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5317 return 0;
5318}
5319
5320static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5321 struct snd_ctl_elem_value *ucontrol)
5322{
5323 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5324 struct ca0132_spec *spec = codec->spec;
5325 int sel = ucontrol->value.enumerated.item[0];
5326 unsigned int items = AE5_SOUND_FILTER_MAX;
5327
5328 if (sel >= items)
5329 return 0;
5330
5331 codec_dbg(codec, "ae5_sound_filter: %s\n",
5332 ae5_filter_presets[sel].name);
5333
5334 spec->ae5_filter_val = sel;
5335
5336 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5337 ae5_filter_presets[sel].val);
5338
5339 return 1;
5340}
95c6e9cb 5341
7cb9d94c
CM		 5342/*
5343 * Input Select Control for alternative ca0132 codecs. This exists because
5344 * front microphone has no auto-detect, and we need a way to set the rear
5345 * as line-in
5346 */
5347static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5348 struct snd_ctl_elem_info *uinfo)
5349{
5350 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5351 uinfo->count = 1;
5352 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5353 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5354 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5355 strcpy(uinfo->value.enumerated.name,
5356 in_src_str[uinfo->value.enumerated.item]);
5357 return 0;
5358}
5359
5360static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5361 struct snd_ctl_elem_value *ucontrol)
5362{
5363 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5364 struct ca0132_spec *spec = codec->spec;
5365
5366 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5367 return 0;
5368}
5369
5370static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5371 struct snd_ctl_elem_value *ucontrol)
5372{
5373 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5374 struct ca0132_spec *spec = codec->spec;
5375 int sel = ucontrol->value.enumerated.item[0];
5376 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5377
5378 if (sel >= items)
5379 return 0;
5380
5381 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5382 sel, in_src_str[sel]);
5383
5384 spec->in_enum_val = sel;
5385
5386 ca0132_alt_select_in(codec);
5387
5388 return 1;
5389}
5390
5391/* Sound Blaster Z Output Select Control */
5392static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5393 struct snd_ctl_elem_info *uinfo)
5394{
5395 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5396 uinfo->count = 1;
5397 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5398 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5399 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5400 strcpy(uinfo->value.enumerated.name,
5401 alt_out_presets[uinfo->value.enumerated.item].name);
5402 return 0;
5403}
5404
5405static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5406 struct snd_ctl_elem_value *ucontrol)
5407{
5408 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5409 struct ca0132_spec *spec = codec->spec;
5410
5411 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5412 return 0;
5413}
5414
5415static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5416 struct snd_ctl_elem_value *ucontrol)
5417{
5418 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5419 struct ca0132_spec *spec = codec->spec;
5420 int sel = ucontrol->value.enumerated.item[0];
5421 unsigned int items = NUM_OF_OUTPUTS;
5422 unsigned int auto_jack;
5423
5424 if (sel >= items)
5425 return 0;
5426
5427 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5428 sel, alt_out_presets[sel].name);
5429
5430 spec->out_enum_val = sel;
5431
5432 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5433
5434 if (!auto_jack)
5435 ca0132_alt_select_out(codec);
5436
5437 return 1;
5438}
5439
47cdf76e
CM		 5440/*
5441 * Smart Volume output setting control. Three different settings, Normal,
5442 * which takes the value from the smart volume slider. The two others, loud
5443 * and night, disregard the slider value and have uneditable values.
5444 */
5445#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5446static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5447
5448static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5449 struct snd_ctl_elem_info *uinfo)
5450{
5451 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5452 uinfo->count = 1;
5453 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5454 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5455 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5456 strcpy(uinfo->value.enumerated.name,
5457 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5458 return 0;
5459}
5460
5461static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5462 struct snd_ctl_elem_value *ucontrol)
5463{
5464 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5465 struct ca0132_spec *spec = codec->spec;
5466
5467 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5468 return 0;
5469}
5470
5471static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5472 struct snd_ctl_elem_value *ucontrol)
5473{
5474 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5475 struct ca0132_spec *spec = codec->spec;
5476 int sel = ucontrol->value.enumerated.item[0];
5477 unsigned int items = NUM_OF_SVM_SETTINGS;
5478 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5479 unsigned int tmp;
5480
5481 if (sel >= items)
5482 return 0;
5483
5484 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5485 sel, out_svm_set_enum_str[sel]);
5486
5487 spec->smart_volume_setting = sel;
5488
5489 switch (sel) {
5490 case 0:
5491 tmp = FLOAT_ZERO;
5492 break;
5493 case 1:
5494 tmp = FLOAT_ONE;
5495 break;
5496 case 2:
5497 tmp = FLOAT_TWO;
5498 break;
5499 default:
5500 tmp = FLOAT_ZERO;
5501 break;
5502 }
5503 /* Req 2 is the Smart Volume Setting req. */
5504 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5505 ca0132_effects[idx].reqs[2], tmp);
5506 return 1;
5507}
5508
5509/* Sound Blaster Z EQ preset controls */
5510static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5511 struct snd_ctl_elem_info *uinfo)
5512{
c5f13d75 5513 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5514
5515 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5516 uinfo->count = 1;
5517 uinfo->value.enumerated.items = items;
5518 if (uinfo->value.enumerated.item >= items)
5519 uinfo->value.enumerated.item = items - 1;
5520 strcpy(uinfo->value.enumerated.name,
5521 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5522 return 0;
5523}
5524
5525static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5526 struct snd_ctl_elem_value *ucontrol)
5527{
5528 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5529 struct ca0132_spec *spec = codec->spec;
5530
5531 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5532 return 0;
5533}
5534
5535static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5536 struct snd_ctl_elem_value *ucontrol)
5537{
5538 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5539 struct ca0132_spec *spec = codec->spec;
5540 int i, err = 0;
5541 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5542 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5543
5544 if (sel >= items)
5545 return 0;
5546
5547 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5548 ca0132_alt_eq_presets[sel].name);
5549 /*
5550 * Idx 0 is default.
5551 * Default needs to qualify with CrystalVoice state.
5552 */
5553 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5554 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5555 ca0132_alt_eq_enum.reqs[i],
5556 ca0132_alt_eq_presets[sel].vals[i]);
5557 if (err < 0)
5558 break;
5559 }
5560
5561 if (err >= 0)
5562 spec->eq_preset_val = sel;
5563
5564 return 1;
5565}
5566
a7e76271
IM		 5567static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5568 struct snd_ctl_elem_info *uinfo)
5569{
a9291f46 5570 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5571
5572 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5573 uinfo->count = 1;
5574 uinfo->value.enumerated.items = items;
5575 if (uinfo->value.enumerated.item >= items)
5576 uinfo->value.enumerated.item = items - 1;
5577 strcpy(uinfo->value.enumerated.name,
5578 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5579 return 0;
5580}
95c6e9cb 5581
a7e76271 5582static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5583 struct snd_ctl_elem_value *ucontrol)
5584{
5585 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5586 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5587
a7e76271 5588 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5589 return 0;
5590}
5591
a7e76271 5592static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5593 struct snd_ctl_elem_value *ucontrol)
5594{
5595 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5596 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5597 int i, err = 0;
5598 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5599
a9291f46 5600 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5601 return 0;
5602
4e76a883 5603 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5604 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5605
a7e76271
IM		 5606 /*
5607 * Idx 0 is default.
5608 * Default needs to qualify with CrystalVoice state.
5609 */
5610 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5611 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5612 ca0132_voicefx.reqs[i],
5613 ca0132_voicefx_presets[sel].vals[i]);
5614 if (err < 0)
5615 break;
5616 }
95c6e9cb 5617
a7e76271
IM		 5618 if (err >= 0) {
5619 spec->voicefx_val = sel;
5620 /* enable voice fx */
5621 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5622 }
95c6e9cb 5623
a7e76271 5624 return 1;
95c6e9cb
IM		 5625}
5626
a7e76271
IM		 5627static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5628 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5629{
5630 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5631 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5632 hda_nid_t nid = get_amp_nid(kcontrol);
5633 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5634 long *valp = ucontrol->value.integer.value;
5635
a7e76271
IM		 5636 /* vnode */
5637 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5638 if (ch & 1) {
5639 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5640 valp++;
5641 }
5642 if (ch & 2) {
5643 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5644 valp++;
5645 }
5646 return 0;
5647 }
5648
5649 /* effects, include PE and CrystalVoice */
5650 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5651 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5652 return 0;
5653 }
5654
5655 /* mic boost */
5656 if (nid == spec->input_pins[0]) {
5657 *valp = spec->cur_mic_boost;
5658 return 0;
5659 }
5660
95c6e9cb
IM		 5661 return 0;
5662}
5663
a7e76271
IM		 5664static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5665 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5666{
5667 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5668 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5669 hda_nid_t nid = get_amp_nid(kcontrol);
5670 int ch = get_amp_channels(kcontrol);
95c6e9cb 5671 long *valp = ucontrol->value.integer.value;
a7e76271 5672 int changed = 1;
95c6e9cb 5673
4e76a883 5674 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5675 nid, *valp);
95c6e9cb
IM		 5676
5677 snd_hda_power_up(codec);
a7e76271
IM		 5678 /* vnode */
5679 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5680 if (ch & 1) {
5681 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5682 valp++;
5683 }
5684 if (ch & 2) {
5685 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5686 valp++;
5687 }
5688 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5689 goto exit;
5690 }
95c6e9cb 5691
a7e76271
IM		 5692 /* PE */
5693 if (nid == PLAY_ENHANCEMENT) {
5694 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5695 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5696 goto exit;
a7e76271 5697 }
95c6e9cb 5698
a7e76271
IM		 5699 /* CrystalVoice */
5700 if (nid == CRYSTAL_VOICE) {
5701 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5702 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5703 goto exit;
a7e76271 5704 }
95c6e9cb 5705
a7e76271
IM		 5706 /* out and in effects */
5707 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5708 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5709 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5710 changed = ca0132_effects_set(codec, nid, *valp);
5711 goto exit;
5712 }
5713
5714 /* mic boost */
5715 if (nid == spec->input_pins[0]) {
5716 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 5717 if (spec->use_alt_functions) {
5718 if (spec->in_enum_val != REAR_LINE_IN)
5719 changed = ca0132_mic_boost_set(codec, *valp);
5720 } else {
5721 /* Mic boost does not apply to Digital Mic */
5722 if (spec->cur_mic_type != DIGITAL_MIC)
5723 changed = ca0132_mic_boost_set(codec, *valp);
5724 }
a7e76271 5725
a7e76271
IM		 5726 goto exit;
5727 }
95c6e9cb 5728
a7e76271 5729exit:
95c6e9cb 5730 snd_hda_power_down(codec);
a7e76271 5731 return changed;
95c6e9cb
IM		 5732}
5733
a7e76271
IM		 5734/*
5735 * Volume related
5736 */
017310fb
CM		 5737/*
5738 * Sets the internal DSP decibel level to match the DAC for output, and the
5739 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5740 * all alternative codecs set DSP playback volume.
5741 */
5742static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5743{
5744 struct ca0132_spec *spec = codec->spec;
5745 unsigned int dsp_dir;
5746 unsigned int lookup_val;
5747
5748 if (nid == VNID_SPK)
5749 dsp_dir = DSP_VOL_OUT;
5750 else
5751 dsp_dir = DSP_VOL_IN;
5752
5753 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5754
5755 dspio_set_uint_param(codec,
5756 ca0132_alt_vol_ctls[dsp_dir].mid,
5757 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5758 float_vol_db_lookup[lookup_val]);
5759
5760 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5761
5762 dspio_set_uint_param(codec,
5763 ca0132_alt_vol_ctls[dsp_dir].mid,
5764 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5765 float_vol_db_lookup[lookup_val]);
5766
5767 dspio_set_uint_param(codec,
5768 ca0132_alt_vol_ctls[dsp_dir].mid,
5769 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5770}
5771
a7e76271
IM		 5772static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5773 struct snd_ctl_elem_info *uinfo)
5774{
5775 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5776 struct ca0132_spec *spec = codec->spec;
5777 hda_nid_t nid = get_amp_nid(kcontrol);
5778 int ch = get_amp_channels(kcontrol);
5779 int dir = get_amp_direction(kcontrol);
5780 unsigned long pval;
5781 int err;
5782
5783 switch (nid) {
5784 case VNID_SPK:
5785 /* follow shared_out info */
5786 nid = spec->shared_out_nid;
5787 mutex_lock(&codec->control_mutex);
5788 pval = kcontrol->private_value;
5789 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5790 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5791 kcontrol->private_value = pval;
5792 mutex_unlock(&codec->control_mutex);
5793 break;
5794 case VNID_MIC:
5795 /* follow shared_mic info */
5796 nid = spec->shared_mic_nid;
5797 mutex_lock(&codec->control_mutex);
5798 pval = kcontrol->private_value;
5799 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5800 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5801 kcontrol->private_value = pval;
5802 mutex_unlock(&codec->control_mutex);
5803 break;
5804 default:
5805 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5806 }
5807 return err;
5808}
5809
5810static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5811 struct snd_ctl_elem_value *ucontrol)
5812{
5813 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5814 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5815 hda_nid_t nid = get_amp_nid(kcontrol);
5816 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5817 long *valp = ucontrol->value.integer.value;
5818
a7e76271
IM		 5819 /* store the left and right volume */
5820 if (ch & 1) {
5821 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5822 valp++;
5823 }
5824 if (ch & 2) {
5825 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5826 valp++;
5827 }
95c6e9cb
IM		 5828 return 0;
5829}
5830
a7e76271 5831static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5832 struct snd_ctl_elem_value *ucontrol)
5833{
5834 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5835 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5836 hda_nid_t nid = get_amp_nid(kcontrol);
5837 int ch = get_amp_channels(kcontrol);
95c6e9cb 5838 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5839 hda_nid_t shared_nid = 0;
5840 bool effective;
5841 int changed = 1;
5842
5843 /* store the left and right volume */
5844 if (ch & 1) {
5845 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5846 valp++;
5847 }
5848 if (ch & 2) {
5849 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5850 valp++;
5851 }
95c6e9cb 5852
a7e76271
IM		 5853 /* if effective conditions, then update hw immediately. */
5854 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5855 if (effective) {
5856 int dir = get_amp_direction(kcontrol);
5857 unsigned long pval;
5858
5859 snd_hda_power_up(codec);
5860 mutex_lock(&codec->control_mutex);
5861 pval = kcontrol->private_value;
5862 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5863 0, dir);
5864 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5865 kcontrol->private_value = pval;
5866 mutex_unlock(&codec->control_mutex);
5867 snd_hda_power_down(codec);
5868 }
95c6e9cb 5869
a7e76271 5870 return changed;
95c6e9cb
IM		 5871}
5872
017310fb
CM		 5873/*
5874 * This function is the same as the one above, because using an if statement
5875 * inside of the above volume control for the DSP volume would cause too much
5876 * lag. This is a lot more smooth.
5877 */
5878static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5879 struct snd_ctl_elem_value *ucontrol)
5880{
5881 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5882 struct ca0132_spec *spec = codec->spec;
5883 hda_nid_t nid = get_amp_nid(kcontrol);
5884 int ch = get_amp_channels(kcontrol);
5885 long *valp = ucontrol->value.integer.value;
5886 hda_nid_t vnid = 0;
5887 int changed = 1;
5888
5889 switch (nid) {
5890 case 0x02:
5891 vnid = VNID_SPK;
5892 break;
5893 case 0x07:
5894 vnid = VNID_MIC;
5895 break;
5896 }
5897
5898 /* store the left and right volume */
5899 if (ch & 1) {
5900 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5901 valp++;
5902 }
5903 if (ch & 2) {
5904 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5905 valp++;
5906 }
5907
5908 snd_hda_power_up(codec);
5909 ca0132_alt_dsp_volume_put(codec, vnid);
5910 mutex_lock(&codec->control_mutex);
5911 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5912 mutex_unlock(&codec->control_mutex);
5913 snd_hda_power_down(codec);
5914
5915 return changed;
5916}
5917
a7e76271
IM		 5918static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5919 unsigned int size, unsigned int __user *tlv)
95c6e9cb 5920{
a7e76271
IM		 5921 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5922 struct ca0132_spec *spec = codec->spec;
5923 hda_nid_t nid = get_amp_nid(kcontrol);
5924 int ch = get_amp_channels(kcontrol);
5925 int dir = get_amp_direction(kcontrol);
5926 unsigned long pval;
5927 int err;
5928
5929 switch (nid) {
5930 case VNID_SPK:
5931 /* follow shared_out tlv */
5932 nid = spec->shared_out_nid;
5933 mutex_lock(&codec->control_mutex);
5934 pval = kcontrol->private_value;
5935 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5936 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5937 kcontrol->private_value = pval;
5938 mutex_unlock(&codec->control_mutex);
5939 break;
5940 case VNID_MIC:
5941 /* follow shared_mic tlv */
5942 nid = spec->shared_mic_nid;
5943 mutex_lock(&codec->control_mutex);
5944 pval = kcontrol->private_value;
5945 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5946 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5947 kcontrol->private_value = pval;
5948 mutex_unlock(&codec->control_mutex);
5949 break;
5950 default:
5951 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5952 }
5953 return err;
95c6e9cb
IM		 5954}
5955
47cdf76e
CM		 5956/* Add volume slider control for effect level */
5957static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5958 const char *pfx, int dir)
5959{
47cdf76e
CM		 5960 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5961 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5962 struct snd_kcontrol_new knew =
5963 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5964
0cc1aa71 5965 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 5966
bb86124c 5967 knew.tlv.c = NULL;
47cdf76e
CM		 5968
5969 switch (nid) {
5970 case XBASS_XOVER:
5971 knew.info = ca0132_alt_xbass_xover_slider_info;
5972 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5973 knew.put = ca0132_alt_xbass_xover_slider_put;
5974 break;
5975 default:
5976 knew.info = ca0132_alt_effect_slider_info;
5977 knew.get = ca0132_alt_slider_ctl_get;
5978 knew.put = ca0132_alt_effect_slider_put;
5979 knew.private_value =
5980 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5981 break;
5982 }
5983
5984 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5985}
5986
5987/*
5988 * Added FX: prefix for the alternative codecs, because otherwise the surround
5989 * effect would conflict with the Surround sound volume control. Also seems more
5990 * clear as to what the switches do. Left alone for others.
5991 */
a7e76271
IM		 5992static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5993 const char *pfx, int dir)
95c6e9cb 5994{
47cdf76e 5995 struct ca0132_spec *spec = codec->spec;
975cc02a 5996 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 5997 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 5998 struct snd_kcontrol_new knew =
a7e76271 5999 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 6000 /* If using alt_controls, add FX: prefix. But, don't add FX:
6001 * prefix to OutFX or InFX enable controls.
6002 */
6003 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 6004 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 6005 else
6006 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6007
95c6e9cb
IM		 6008 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6009}
6010
a7e76271 6011static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 6012{
6013 struct snd_kcontrol_new knew =
a7e76271
IM		 6014 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6015 VOICEFX, 1, 0, HDA_INPUT);
6016 knew.info = ca0132_voicefx_info;
6017 knew.get = ca0132_voicefx_get;
6018 knew.put = ca0132_voicefx_put;
6019 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 6020}
6021
47cdf76e
CM		 6022/* Create the EQ Preset control */
6023static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6024{
6025 struct snd_kcontrol_new knew =
6026 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6027 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6028 knew.info = ca0132_alt_eq_preset_info;
6029 knew.get = ca0132_alt_eq_preset_get;
6030 knew.put = ca0132_alt_eq_preset_put;
6031 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6032 snd_ctl_new1(&knew, codec));
6033}
6034
6035/*
6036 * Add enumerated control for the three different settings of the smart volume
6037 * output effect. Normal just uses the slider value, and loud and night are
6038 * their own things that ignore that value.
6039 */
6040static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6041{
6042 struct snd_kcontrol_new knew =
6043 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6044 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6045 knew.info = ca0132_alt_svm_setting_info;
6046 knew.get = ca0132_alt_svm_setting_get;
6047 knew.put = ca0132_alt_svm_setting_put;
6048 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6049 snd_ctl_new1(&knew, codec));
6050
6051}
6052
7cb9d94c
CM		 6053/*
6054 * Create an Output Select enumerated control for codecs with surround
6055 * out capabilities.
6056 */
6057static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6058{
6059 struct snd_kcontrol_new knew =
6060 HDA_CODEC_MUTE_MONO("Output Select",
6061 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6062 knew.info = ca0132_alt_output_select_get_info;
6063 knew.get = ca0132_alt_output_select_get;
6064 knew.put = ca0132_alt_output_select_put;
6065 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6066 snd_ctl_new1(&knew, codec));
6067}
6068
6069/*
6070 * Create an Input Source enumerated control for the alternate ca0132 codecs
6071 * because the front microphone has no auto-detect, and Line-in has to be set
6072 * somehow.
6073 */
6074static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6075{
6076 struct snd_kcontrol_new knew =
6077 HDA_CODEC_MUTE_MONO("Input Source",
6078 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6079 knew.info = ca0132_alt_input_source_info;
6080 knew.get = ca0132_alt_input_source_get;
6081 knew.put = ca0132_alt_input_source_put;
6082 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6083 snd_ctl_new1(&knew, codec));
6084}
6085
47cdf76e
CM		 6086/*
6087 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6088 * more control than the original mic boost, which is either full 30dB or off.
6089 */
6090static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6091{
6092 struct snd_kcontrol_new knew =
6093 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6094 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6095 knew.info = ca0132_alt_mic_boost_info;
6096 knew.get = ca0132_alt_mic_boost_get;
6097 knew.put = ca0132_alt_mic_boost_put;
6098 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6099 snd_ctl_new1(&knew, codec));
6100
6101}
6102
212de2e7
CM		 6103/*
6104 * Add headphone gain enumerated control for the AE-5. This switches between
6105 * three modes, low, medium, and high. When non-headphone outputs are selected,
6106 * it is automatically set to high. This is the same behavior as Windows.
6107 */
6108static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6109{
6110 struct snd_kcontrol_new knew =
6111 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6112 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_INPUT);
6113 knew.info = ae5_headphone_gain_info;
6114 knew.get = ae5_headphone_gain_get;
6115 knew.put = ae5_headphone_gain_put;
6116 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6117 snd_ctl_new1(&knew, codec));
6118}
6119
6120/*
6121 * Add sound filter enumerated control for the AE-5. This adds three different
6122 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6123 * read into it, it changes the DAC's interpolation filter.
6124 */
6125static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6126{
6127 struct snd_kcontrol_new knew =
6128 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6129 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_INPUT);
6130 knew.info = ae5_sound_filter_info;
6131 knew.get = ae5_sound_filter_get;
6132 knew.put = ae5_sound_filter_put;
6133 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6134 snd_ctl_new1(&knew, codec));
6135}
6136
47cdf76e
CM		 6137/*
6138 * Need to create slave controls for the alternate codecs that have surround
6139 * capabilities.
6140 */
6141static const char * const ca0132_alt_slave_pfxs[] = {
6142 "Front", "Surround", "Center", "LFE", NULL,
6143};
6144
6145/*
6146 * Also need special channel map, because the default one is incorrect.
6147 * I think this has to do with the pin for rear surround being 0x11,
6148 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6149 */
9c4a665e 6150static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 6151 { .channels = 2,
6152 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6153 { .channels = 4,
6154 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6155 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6156 { .channels = 6,
6157 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6158 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6159 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6160 { }
6161};
6162
6163/* Add the correct chmap for streams with 6 channels. */
6164static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6165{
6166 int err = 0;
6167 struct hda_pcm *pcm;
6168
6169 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6170 struct hda_pcm_stream *hinfo =
6171 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6172 struct snd_pcm_chmap *chmap;
6173 const struct snd_pcm_chmap_elem *elem;
6174
6175 elem = ca0132_alt_chmaps;
6176 if (hinfo->channels_max == 6) {
6177 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6178 SNDRV_PCM_STREAM_PLAYBACK,
6179 elem, hinfo->channels_max, 0, &chmap);
6180 if (err < 0)
6181 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6182 }
6183 }
6184}
6185
a7e76271
IM		 6186/*
6187 * When changing Node IDs for Mixer Controls below, make sure to update
6188 * Node IDs in ca0132_config() as well.
6189 */
b0eaa072 6190static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 6191 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6192 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6193 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6194 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6195 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6196 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6197 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6198 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6199 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6200 0x12, 1, HDA_INPUT),
6201 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6202 VNID_HP_SEL, 1, HDA_OUTPUT),
6203 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6204 VNID_AMIC1_SEL, 1, HDA_INPUT),
6205 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6206 VNID_HP_ASEL, 1, HDA_OUTPUT),
6207 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6208 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6209 { } /* end */
6210};
6211
017310fb 6212/*
e25e3445
CM		 6213 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6214 * surround controls. Also sets both the Front Playback and Capture Volume
6215 * controls to alt so they set the DSP's decibel level.
017310fb 6216 */
e25e3445 6217static const struct snd_kcontrol_new desktop_mixer[] = {
017310fb
CM		 6218 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6219 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6220 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6221 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6222 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6223 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6224 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6225 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6226 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6227 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6228 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6229 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6230 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6231 VNID_HP_ASEL, 1, HDA_OUTPUT),
6232 { } /* end */
6233};
6234
6235/*
6236 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6237 * because it doesn't set decibel levels for the DSP for capture.
6238 */
b0eaa072 6239static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 6240 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6241 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6242 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6243 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6244 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6245 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6246 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6247 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6248 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6249 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6250 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6251 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6252 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6253 VNID_HP_ASEL, 1, HDA_OUTPUT),
6254 { } /* end */
6255};
6256
e90f29e4
IM		 6257static int ca0132_build_controls(struct hda_codec *codec)
6258{
6259 struct ca0132_spec *spec = codec->spec;
47cdf76e 6260 int i, num_fx, num_sliders;
e90f29e4
IM		 6261 int err = 0;
6262
6263 /* Add Mixer controls */
6264 for (i = 0; i < spec->num_mixers; i++) {
6265 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6266 if (err < 0)
6267 return err;
6268 }
47cdf76e
CM		 6269 /* Setup vmaster with surround slaves for desktop ca0132 devices */
6270 if (spec->use_alt_functions) {
6271 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6272 spec->tlv);
6273 snd_hda_add_vmaster(codec, "Master Playback Volume",
6274 spec->tlv, ca0132_alt_slave_pfxs,
6275 "Playback Volume");
6276 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6277 NULL, ca0132_alt_slave_pfxs,
6278 "Playback Switch",
6279 true, &spec->vmaster_mute.sw_kctl);
6280
6281 }
e90f29e4
IM		 6282
6283 /* Add in and out effects controls.
6284 * VoiceFX, PE and CrystalVoice are added separately.
6285 */
6286 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6287 for (i = 0; i < num_fx; i++) {
e25e3445
CM		 6288 /* SBZ and R3D break if Echo Cancellation is used. */
6289 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D) {
47cdf76e
CM		 6290 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6291 OUT_EFFECTS_COUNT))
6292 continue;
6293 }
6294
e90f29e4
IM		 6295 err = add_fx_switch(codec, ca0132_effects[i].nid,
6296 ca0132_effects[i].name,
6297 ca0132_effects[i].direct);
6298 if (err < 0)
6299 return err;
6300 }
47cdf76e
CM		 6301 /*
6302 * If codec has use_alt_controls set to true, add effect level sliders,
6303 * EQ presets, and Smart Volume presets. Also, change names to add FX
6304 * prefix, and change PlayEnhancement and CrystalVoice to match.
6305 */
6306 if (spec->use_alt_controls) {
6307 ca0132_alt_add_svm_enum(codec);
6308 add_ca0132_alt_eq_presets(codec);
6309 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6310 "Enable OutFX", 0);
6311 if (err < 0)
6312 return err;
e90f29e4 6313
47cdf76e
CM		 6314 err = add_fx_switch(codec, CRYSTAL_VOICE,
6315 "Enable InFX", 1);
6316 if (err < 0)
6317 return err;
e90f29e4 6318
47cdf76e
CM		 6319 num_sliders = OUT_EFFECTS_COUNT - 1;
6320 for (i = 0; i < num_sliders; i++) {
6321 err = ca0132_alt_add_effect_slider(codec,
6322 ca0132_effects[i].nid,
6323 ca0132_effects[i].name,
6324 ca0132_effects[i].direct);
6325 if (err < 0)
6326 return err;
6327 }
6328
6329 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6330 "X-Bass Crossover", EFX_DIR_OUT);
6331
6332 if (err < 0)
6333 return err;
6334 } else {
6335 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6336 "PlayEnhancement", 0);
6337 if (err < 0)
6338 return err;
e90f29e4 6339
47cdf76e
CM		 6340 err = add_fx_switch(codec, CRYSTAL_VOICE,
6341 "CrystalVoice", 1);
6342 if (err < 0)
6343 return err;
6344 }
e90f29e4
IM		 6345 add_voicefx(codec);
6346
7cb9d94c
CM		 6347 /*
6348 * If the codec uses alt_functions, you need the enumerated controls
6349 * to select the new outputs and inputs, plus add the new mic boost
6350 * setting control.
6351 */
6352 if (spec->use_alt_functions) {
6353 ca0132_alt_add_output_enum(codec);
6354 ca0132_alt_add_input_enum(codec);
47cdf76e 6355 ca0132_alt_add_mic_boost_enum(codec);
7cb9d94c 6356 }
212de2e7
CM		 6357
6358 if (spec->quirk == QUIRK_AE5) {
6359 ae5_add_headphone_gain_enum(codec);
6360 ae5_add_sound_filter_enum(codec);
6361 }
e90f29e4
IM		 6362#ifdef ENABLE_TUNING_CONTROLS
6363 add_tuning_ctls(codec);
6364#endif
6365
6366 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6367 if (err < 0)
6368 return err;
6369
6370 if (spec->dig_out) {
6371 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6372 spec->dig_out);
6373 if (err < 0)
6374 return err;
6375 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6376 if (err < 0)
6377 return err;
6378 /* spec->multiout.share_spdif = 1; */
6379 }
6380
6381 if (spec->dig_in) {
6382 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6383 if (err < 0)
6384 return err;
6385 }
47cdf76e
CM		 6386
6387 if (spec->use_alt_functions)
6388 ca0132_alt_add_chmap_ctls(codec);
6389
e90f29e4
IM		 6390 return 0;
6391}
6392
a7e76271 6393/*
e90f29e4 6394 * PCM
a7e76271 6395 */
071f1344 6396static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 6397 .substreams = 1,
6398 .channels_min = 2,
825315bc 6399 .channels_max = 6,
a7e76271 6400 .ops = {
a7e76271 6401 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 6402 .cleanup = ca0132_playback_pcm_cleanup,
6403 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 6404 },
6405};
6406
071f1344 6407static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 6408 .substreams = 1,
6409 .channels_min = 2,
6410 .channels_max = 2,
825315bc
IM		 6411 .ops = {
6412 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 6413 .cleanup = ca0132_capture_pcm_cleanup,
6414 .get_delay = ca0132_capture_pcm_delay,
825315bc 6415 },
a7e76271
IM		 6416};
6417
071f1344 6418static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 6419 .substreams = 1,
6420 .channels_min = 2,
6421 .channels_max = 2,
6422 .ops = {
6423 .open = ca0132_dig_playback_pcm_open,
6424 .close = ca0132_dig_playback_pcm_close,
6425 .prepare = ca0132_dig_playback_pcm_prepare,
6426 .cleanup = ca0132_dig_playback_pcm_cleanup
6427 },
6428};
6429
071f1344 6430static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 6431 .substreams = 1,
6432 .channels_min = 2,
6433 .channels_max = 2,
6434};
6435
6436static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 6437{
6438 struct ca0132_spec *spec = codec->spec;
bbbc7e85 6439 struct hda_pcm *info;
a7e76271 6440
bbbc7e85
TI		 6441 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6442 if (!info)
6443 return -ENOMEM;
47cdf76e
CM		 6444 if (spec->use_alt_functions) {
6445 info->own_chmap = true;
6446 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6447 = ca0132_alt_chmaps;
6448 }
a7e76271
IM		 6449 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6450 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6451 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6452 spec->multiout.max_channels;
6453 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 6454 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 6455 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 6456
009b8f97 6457 /* With the DSP enabled, desktops don't use this ADC. */
5f8ddc6e 6458 if (!spec->use_alt_functions) {
009b8f97
CM		 6459 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6460 if (!info)
6461 return -ENOMEM;
6462 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6463 ca0132_pcm_analog_capture;
6464 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6465 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6466 }
825315bc 6467
bbbc7e85
TI		 6468 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6469 if (!info)
6470 return -ENOMEM;
825315bc
IM		 6471 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6472 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6473 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6474
a7e76271
IM		 6475 if (!spec->dig_out && !spec->dig_in)
6476 return 0;
6477
bbbc7e85
TI		 6478 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6479 if (!info)
6480 return -ENOMEM;
a7e76271
IM		 6481 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6482 if (spec->dig_out) {
6483 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6484 ca0132_pcm_digital_playback;
6485 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6486 }
6487 if (spec->dig_in) {
6488 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6489 ca0132_pcm_digital_capture;
6490 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6491 }
95c6e9cb 6492
a7e76271 6493 return 0;
95c6e9cb
IM		 6494}
6495
441aa6a0
IM		 6496static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6497{
6498 if (pin) {
a0c041cb 6499 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6500 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6501 snd_hda_codec_write(codec, pin, 0,
6502 AC_VERB_SET_AMP_GAIN_MUTE,
6503 AMP_OUT_UNMUTE);
6504 }
6505 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6506 snd_hda_codec_write(codec, dac, 0,
6507 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6508}
6509
6510static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6511{
6512 if (pin) {
a0c041cb 6513 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6514 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6515 snd_hda_codec_write(codec, pin, 0,
6516 AC_VERB_SET_AMP_GAIN_MUTE,
6517 AMP_IN_UNMUTE(0));
6518 }
6519 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6520 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6521 AMP_IN_UNMUTE(0));
6522
6523 /* init to 0 dB and unmute. */
6524 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6525 HDA_AMP_VOLMASK, 0x5a);
6526 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6527 HDA_AMP_MUTE, 0);
6528 }
6529}
6530
5aaca44d
IM		 6531static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6532{
6533 unsigned int caps;
6534
6535 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6536 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6537 snd_hda_override_amp_caps(codec, nid, dir, caps);
6538}
6539
6540/*
6541 * Switch between Digital built-in mic and analog mic.
6542 */
6543static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6544{
6545 struct ca0132_spec *spec = codec->spec;
6546 unsigned int tmp;
6547 u8 val;
6548 unsigned int oldval;
6549
4e76a883 6550 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6551
6552 oldval = stop_mic1(codec);
6553 ca0132_set_vipsource(codec, 0);
6554 if (enable) {
6555 /* set DMic input as 2-ch */
6556 tmp = FLOAT_TWO;
6557 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6558
6559 val = spec->dmic_ctl;
6560 val |= 0x80;
6561 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6562 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6563
6564 if (!(spec->dmic_ctl & 0x20))
6565 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6566 } else {
6567 /* set AMic input as mono */
6568 tmp = FLOAT_ONE;
6569 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6570
6571 val = spec->dmic_ctl;
6572 /* clear bit7 and bit5 to disable dmic */
6573 val &= 0x5f;
6574 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6575 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6576
6577 if (!(spec->dmic_ctl & 0x20))
6578 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6579 }
6580 ca0132_set_vipsource(codec, 1);
6581 resume_mic1(codec, oldval);
6582}
6583
6584/*
6585 * Initialization for Digital Mic.
6586 */
6587static void ca0132_init_dmic(struct hda_codec *codec)
6588{
6589 struct ca0132_spec *spec = codec->spec;
6590 u8 val;
6591
6592 /* Setup Digital Mic here, but don't enable.
6593 * Enable based on jack detect.
6594 */
6595
6596 /* MCLK uses MPIO1, set to enable.
6597 * Bit 2-0: MPIO select
6598 * Bit 3: set to disable
6599 * Bit 7-4: reserved
6600 */
6601 val = 0x01;
6602 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6603 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6604
6605 /* Data1 uses MPIO3. Data2 not use
6606 * Bit 2-0: Data1 MPIO select
6607 * Bit 3: set disable Data1
6608 * Bit 6-4: Data2 MPIO select
6609 * Bit 7: set disable Data2
6610 */
6611 val = 0x83;
6612 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6613 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6614
6615 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6616 * Bit 3-0: Channel mask
6617 * Bit 4: set for 48KHz, clear for 32KHz
6618 * Bit 5: mode
6619 * Bit 6: set to select Data2, clear for Data1
6620 * Bit 7: set to enable DMic, clear for AMic
6621 */
a57a46b9
AB		 6622 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6623 val = 0x33;
6624 else
6625 val = 0x23;
5aaca44d
IM		 6626 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6627 spec->dmic_ctl = val;
6628 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6629 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6630}
6631
6632/*
6633 * Initialization for Analog Mic 2
6634 */
6635static void ca0132_init_analog_mic2(struct hda_codec *codec)
6636{
6637 struct ca0132_spec *spec = codec->spec;
6638
6639 mutex_lock(&spec->chipio_mutex);
6640 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6641 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6642 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6643 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6644 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6645 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6646 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6647 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6648 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6649 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6650 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6651 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6652 mutex_unlock(&spec->chipio_mutex);
6653}
6654
6655static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6656{
6657 struct ca0132_spec *spec = codec->spec;
6658 int i;
5aaca44d 6659
4e76a883 6660 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6661 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6662
6663 for (i = 0; i < spec->multiout.num_dacs; i++)
6664 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6665
6666 for (i = 0; i < spec->num_outputs; i++)
6667 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6668
6669 for (i = 0; i < spec->num_inputs; i++) {
6670 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6671 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6672 }
6673}
6674
7e6ed62e 6675/*
6ef0e91e
CM		 6676 * Creates a dummy stream to bind the output to. This seems to have to be done
6677 * after changing the main outputs source and destination streams.
7e6ed62e 6678 */
6ef0e91e 6679static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
447fd8e9 6680{
6ef0e91e
CM		 6681 struct ca0132_spec *spec = codec->spec;
6682 unsigned int stream_format;
447fd8e9 6683
6ef0e91e
CM		 6684 stream_format = snd_hdac_calc_stream_format(48000, 2,
6685 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7e6ed62e 6686
6ef0e91e
CM		 6687 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6688 0, stream_format);
7e6ed62e 6689
6ef0e91e 6690 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7e6ed62e
CM		 6691}
6692
38ba69ff 6693/*
6ef0e91e 6694 * Initialize mic for non-chromebook ca0132 implementations.
38ba69ff 6695 */
6ef0e91e 6696static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
38ba69ff 6697{
6ef0e91e 6698 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6699 unsigned int tmp;
6700
6701 /* Mic 1 Setup */
6702 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6703 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6ef0e91e
CM		 6704 if (spec->quirk == QUIRK_R3DI) {
6705 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6706 tmp = FLOAT_ONE;
6707 } else
6708 tmp = FLOAT_THREE;
38ba69ff
CM		 6709 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6710
6ef0e91e 6711 /* Mic 2 setup (not present on desktop cards) */
38ba69ff
CM		 6712 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6713 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6ef0e91e
CM		 6714 if (spec->quirk == QUIRK_R3DI)
6715 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
38ba69ff
CM		 6716 tmp = FLOAT_ZERO;
6717 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
38ba69ff
CM		 6718}
6719
6720/*
6721 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6722 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6723 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6724 * having an updated DAC, which changes the destination to that DAC.
6725 */
6726static void sbz_connect_streams(struct hda_codec *codec)
6727{
6728 struct ca0132_spec *spec = codec->spec;
6729
6730 mutex_lock(&spec->chipio_mutex);
6731
6732 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6733
6734 chipio_set_stream_channels(codec, 0x0C, 6);
6735 chipio_set_stream_control(codec, 0x0C, 1);
6736
6737 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6738 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6739
6740 /* Setup stream 0x14 with it's source and destination points */
6741 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6742 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6743 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6744 chipio_set_stream_channels(codec, 0x14, 2);
6745 chipio_set_stream_control(codec, 0x14, 1);
6746
6747 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6748
6749 mutex_unlock(&spec->chipio_mutex);
38ba69ff
CM		 6750}
6751
6752/*
6753 * Write data through ChipIO to setup proper stream destinations.
6754 * Not sure how it exactly works, but it seems to direct data
6755 * to different destinations. Example is f8 to c0, e0 to c0.
6756 * All I know is, if you don't set these, you get no sound.
6757 */
6758static void sbz_chipio_startup_data(struct hda_codec *codec)
6759{
6760 struct ca0132_spec *spec = codec->spec;
6761
6762 mutex_lock(&spec->chipio_mutex);
6763 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6764
6765 /* These control audio output */
6766 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6767 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6768 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6769 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6770 /* Signal to update I think */
6771 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6772
6773 chipio_set_stream_channels(codec, 0x0C, 6);
6774 chipio_set_stream_control(codec, 0x0C, 1);
6775 /* No clue what these control */
6776 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6777 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6778 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6779 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6780 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6781 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6782 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6783 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6784 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6785 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6786 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6787 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6788
6789 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6790
6791 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6792 mutex_unlock(&spec->chipio_mutex);
6793}
6794
447fd8e9 6795/*
6ef0e91e
CM		 6796 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
6797 * done after the DSP is loaded.
447fd8e9 6798 */
6ef0e91e 6799static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
447fd8e9 6800{
6ef0e91e 6801 struct ca0132_spec *spec = codec->spec;
447fd8e9
CM		 6802 unsigned int tmp;
6803
6ef0e91e
CM		 6804 switch (spec->quirk) {
6805 case QUIRK_SBZ:
6806 case QUIRK_AE5:
6807 tmp = 0x00000003;
6808 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6809 tmp = 0x00000000;
6810 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6811 tmp = 0x00000001;
6812 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6813 tmp = 0x00000004;
6814 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6815 tmp = 0x00000005;
6816 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6817 tmp = 0x00000000;
6818 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6819 break;
6820 case QUIRK_R3D:
6821 case QUIRK_R3DI:
6822 tmp = 0x00000000;
6823 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6824 tmp = 0x00000001;
6825 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6826 tmp = 0x00000004;
6827 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6828 tmp = 0x00000005;
6829 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6830 tmp = 0x00000000;
6831 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6832 break;
6833 }
447fd8e9
CM		 6834}
6835
6ef0e91e 6836static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
38ba69ff 6837{
6ef0e91e 6838 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6839 unsigned int tmp;
6840
6841 chipio_set_stream_control(codec, 0x03, 0);
6842 chipio_set_stream_control(codec, 0x04, 0);
6843
6844 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6845 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6846
6847 tmp = FLOAT_THREE;
6848 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6849
6850 chipio_set_stream_control(codec, 0x03, 1);
6851 chipio_set_stream_control(codec, 0x04, 1);
6852
6ef0e91e
CM		 6853 switch (spec->quirk) {
6854 case QUIRK_SBZ:
6855 chipio_write(codec, 0x18b098, 0x0000000c);
6856 chipio_write(codec, 0x18b09C, 0x0000000c);
6857 break;
6858 case QUIRK_AE5:
6859 chipio_write(codec, 0x18b098, 0x0000000c);
6860 chipio_write(codec, 0x18b09c, 0x0000004c);
6861 break;
6862 }
38ba69ff
CM		 6863}
6864
415cd844
CM		 6865static void ae5_post_dsp_register_set(struct hda_codec *codec)
6866{
6867 struct ca0132_spec *spec = codec->spec;
6868
6869 chipio_8051_write_direct(codec, 0x93, 0x10);
6870 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6871 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
6872 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6873 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
6874
6875 writeb(0xff, spec->mem_base + 0x304);
6876 writeb(0xff, spec->mem_base + 0x304);
6877 writeb(0xff, spec->mem_base + 0x304);
6878 writeb(0xff, spec->mem_base + 0x304);
6879 writeb(0x00, spec->mem_base + 0x100);
6880 writeb(0xff, spec->mem_base + 0x304);
6881 writeb(0x00, spec->mem_base + 0x100);
6882 writeb(0xff, spec->mem_base + 0x304);
6883 writeb(0x00, spec->mem_base + 0x100);
6884 writeb(0xff, spec->mem_base + 0x304);
6885 writeb(0x00, spec->mem_base + 0x100);
6886 writeb(0xff, spec->mem_base + 0x304);
6887
6888 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
6889 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
6890 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
6891}
6892
6893static void ae5_post_dsp_param_setup(struct hda_codec *codec)
6894{
6895 /*
6896 * Param3 in the 8051's memory is represented by the ascii string 'mch'
6897 * which seems to be 'multichannel'. This is also mentioned in the
6898 * AE-5's registry values in Windows.
6899 */
6900 chipio_set_control_param(codec, 3, 0);
6901 /*
6902 * I believe ASI is 'audio serial interface' and that it's used to
6903 * change colors on the external LED strip connected to the AE-5.
6904 */
6905 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
6906
6907 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
6908 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
6909
6910 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6911 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
6912 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6913 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
6914 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6915 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
6916}
6917
6918static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
6919{
6920 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6921 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
6922 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6923 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
6924
6925 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6926 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
6927 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6928 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
6929
6930 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6931 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
6932 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6933 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
6934
6935 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6936 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
6937 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6938 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
6939
6940 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6941 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
6942 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6943 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
6944}
6945
6946static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
6947{
6948 struct ca0132_spec *spec = codec->spec;
6949
6950 mutex_lock(&spec->chipio_mutex);
6951
6952 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
6953
6954 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
6955
6956 chipio_set_stream_channels(codec, 0x0C, 6);
6957 chipio_set_stream_control(codec, 0x0C, 1);
6958
6959 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
6960
6961 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
6962 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
6963 chipio_set_stream_channels(codec, 0x18, 6);
6964 chipio_set_stream_control(codec, 0x18, 1);
6965
6966 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
6967
6968 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6969 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
6970 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6971 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
6972
6973 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
6974
6975 mutex_unlock(&spec->chipio_mutex);
6976}
6977
6978static void ae5_post_dsp_startup_data(struct hda_codec *codec)
6979{
6980 struct ca0132_spec *spec = codec->spec;
6981
6982 mutex_lock(&spec->chipio_mutex);
6983
6984 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
6985 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
6986 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
6987 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
6988
6989 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
6990 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
6991 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
6992 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
6993 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
6994 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
6995 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
6996 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
6997 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
6998 ca0113_mmio_gpio_set(codec, 0, true);
6999 ca0113_mmio_gpio_set(codec, 1, true);
7000 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7001
7002 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7003
7004 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7005 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7006
7007 mutex_unlock(&spec->chipio_mutex);
7008}
7009
5aaca44d
IM		 7010/*
7011 * Setup default parameters for DSP
7012 */
7013static void ca0132_setup_defaults(struct hda_codec *codec)
7014{
e8f1bd5d 7015 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7016 unsigned int tmp;
7017 int num_fx;
7018 int idx, i;
7019
e8f1bd5d 7020 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 7021 return;
7022
7023 /* out, in effects + voicefx */
7024 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7025 for (idx = 0; idx < num_fx; idx++) {
7026 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7027 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
7028 ca0132_effects[idx].reqs[i],
7029 ca0132_effects[idx].def_vals[i]);
7030 }
7031 }
7032
7033 /*remove DSP headroom*/
7034 tmp = FLOAT_ZERO;
7035 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7036
7037 /*set speaker EQ bypass attenuation*/
7038 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
7039
7040 /* set AMic1 and AMic2 as mono mic */
7041 tmp = FLOAT_ONE;
7042 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7043 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7044
7045 /* set AMic1 as CrystalVoice input */
7046 tmp = FLOAT_ONE;
7047 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
7048
7049 /* set WUH source */
7050 tmp = FLOAT_TWO;
7051 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7052}
7053
7e6ed62e 7054/*
c986f50c 7055 * Setup default parameters for Recon3D/Recon3Di DSP.
7e6ed62e
CM		 7056 */
7057
c986f50c 7058static void r3d_setup_defaults(struct hda_codec *codec)
7e6ed62e
CM		 7059{
7060 struct ca0132_spec *spec = codec->spec;
7061 unsigned int tmp;
7062 int num_fx;
7063 int idx, i;
7064
7065 if (spec->dsp_state != DSP_DOWNLOADED)
7066 return;
7067
6ef0e91e
CM		 7068 ca0132_alt_dsp_scp_startup(codec);
7069 ca0132_alt_init_analog_mics(codec);
7e6ed62e
CM		 7070
7071 /*remove DSP headroom*/
7072 tmp = FLOAT_ZERO;
7073 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7074
7075 /* set WUH source */
7076 tmp = FLOAT_TWO;
7077 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7078 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7079
7080 /* Set speaker source? */
7081 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7082
c986f50c
CM		 7083 if (spec->quirk == QUIRK_R3DI)
7084 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7e6ed62e
CM		 7085
7086 /* Setup effect defaults */
7087 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7088 for (idx = 0; idx < num_fx; idx++) {
7089 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7090 dspio_set_uint_param(codec,
7091 ca0132_effects[idx].mid,
7092 ca0132_effects[idx].reqs[i],
7093 ca0132_effects[idx].def_vals[i]);
7094 }
7095 }
7e6ed62e
CM		 7096}
7097
38ba69ff
CM		 7098/*
7099 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
7100 * than the Chromebook setup.
7101 */
7102static void sbz_setup_defaults(struct hda_codec *codec)
7103{
7104 struct ca0132_spec *spec = codec->spec;
6ef0e91e 7105 unsigned int tmp;
38ba69ff
CM		 7106 int num_fx;
7107 int idx, i;
7108
7109 if (spec->dsp_state != DSP_DOWNLOADED)
7110 return;
7111
6ef0e91e
CM		 7112 ca0132_alt_dsp_scp_startup(codec);
7113 ca0132_alt_init_analog_mics(codec);
38ba69ff 7114 sbz_connect_streams(codec);
38ba69ff
CM		 7115 sbz_chipio_startup_data(codec);
7116
7117 chipio_set_stream_control(codec, 0x03, 1);
7118 chipio_set_stream_control(codec, 0x04, 1);
7119
7120 /*
7121 * Sets internal input loopback to off, used to have a switch to
7122 * enable input loopback, but turned out to be way too buggy.
7123 */
7124 tmp = FLOAT_ONE;
7125 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7126 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7127
7128 /*remove DSP headroom*/
7129 tmp = FLOAT_ZERO;
7130 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7131
7132 /* set WUH source */
7133 tmp = FLOAT_TWO;
7134 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7135 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7136
7137 /* Set speaker source? */
7138 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7139
6ef0e91e 7140 ca0132_alt_dsp_initial_mic_setup(codec);
38ba69ff
CM		 7141
7142 /* out, in effects + voicefx */
7143 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7144 for (idx = 0; idx < num_fx; idx++) {
7145 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7146 dspio_set_uint_param(codec,
7147 ca0132_effects[idx].mid,
7148 ca0132_effects[idx].reqs[i],
7149 ca0132_effects[idx].def_vals[i]);
7150 }
7151 }
7152
6ef0e91e 7153 ca0132_alt_create_dummy_stream(codec);
38ba69ff
CM		 7154}
7155
415cd844
CM		 7156/*
7157 * Setup default parameters for the Sound BlasterX AE-5 DSP.
7158 */
7159static void ae5_setup_defaults(struct hda_codec *codec)
7160{
7161 struct ca0132_spec *spec = codec->spec;
7162 unsigned int tmp;
7163 int num_fx;
7164 int idx, i;
7165
7166 if (spec->dsp_state != DSP_DOWNLOADED)
7167 return;
7168
7169 ca0132_alt_dsp_scp_startup(codec);
7170 ca0132_alt_init_analog_mics(codec);
7171 chipio_set_stream_control(codec, 0x03, 1);
7172 chipio_set_stream_control(codec, 0x04, 1);
7173
7174 /* New, unknown SCP req's */
7175 tmp = FLOAT_ZERO;
7176 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
7177 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
7178 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
7179 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
7180
7181 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
7182 ca0113_mmio_gpio_set(codec, 0, false);
7183 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
7184
7185 /* Internal loopback off */
7186 tmp = FLOAT_ONE;
7187 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7188 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7189
7190 /*remove DSP headroom*/
7191 tmp = FLOAT_ZERO;
7192 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7193
7194 /* set WUH source */
7195 tmp = FLOAT_TWO;
7196 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7197 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7198
7199 /* Set speaker source? */
7200 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7201
7202 ca0132_alt_dsp_initial_mic_setup(codec);
7203 ae5_post_dsp_register_set(codec);
7204 ae5_post_dsp_param_setup(codec);
7205 ae5_post_dsp_pll_setup(codec);
7206 ae5_post_dsp_stream_setup(codec);
7207 ae5_post_dsp_startup_data(codec);
7208
7209 /* out, in effects + voicefx */
7210 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7211 for (idx = 0; idx < num_fx; idx++) {
7212 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7213 dspio_set_uint_param(codec,
7214 ca0132_effects[idx].mid,
7215 ca0132_effects[idx].reqs[i],
7216 ca0132_effects[idx].def_vals[i]);
7217 }
7218 }
7219
7220 ca0132_alt_create_dummy_stream(codec);
7221}
7222
5aaca44d
IM		 7223/*
7224 * Initialization of flags in chip
7225 */
7226static void ca0132_init_flags(struct hda_codec *codec)
7227{
009b8f97
CM		 7228 struct ca0132_spec *spec = codec->spec;
7229
7230 if (spec->use_alt_functions) {
7231 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
7232 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
7233 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
7234 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
7235 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
7236 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7237 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
7238 chipio_set_control_flag(codec,
7239 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7240 chipio_set_control_flag(codec,
7241 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
7242 } else {
7243 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7244 chipio_set_control_flag(codec,
7245 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
7246 chipio_set_control_flag(codec,
7247 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
7248 chipio_set_control_flag(codec,
7249 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
7250 chipio_set_control_flag(codec,
7251 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7252 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
7253 }
5aaca44d
IM		 7254}
7255
7256/*
7257 * Initialization of parameters in chip
7258 */
7259static void ca0132_init_params(struct hda_codec *codec)
7260{
009b8f97
CM		 7261 struct ca0132_spec *spec = codec->spec;
7262
7263 if (spec->use_alt_functions) {
7264 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7265 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
7266 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
7267 chipio_set_control_param(codec, 0, 0);
7268 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
7269 }
7270
5aaca44d
IM		 7271 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
7272 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
7273}
95c6e9cb 7274
e90f29e4
IM		 7275static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
7276{
7277 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
7278 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
7279 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
7280 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
7281 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
7282 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
7283
406261ce
IM		 7284 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7285 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 7286 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7287}
7288
7289static bool ca0132_download_dsp_images(struct hda_codec *codec)
7290{
7291 bool dsp_loaded = false;
8a19bcee 7292 struct ca0132_spec *spec = codec->spec;
e90f29e4 7293 const struct dsp_image_seg *dsp_os_image;
15e4ba66 7294 const struct firmware *fw_entry;
8a19bcee
CM		 7295 /*
7296 * Alternate firmwares for different variants. The Recon3Di apparently
7297 * can use the default firmware, but I'll leave the option in case
7298 * it needs it again.
7299 */
7300 switch (spec->quirk) {
7301 case QUIRK_SBZ:
7a928186
CM		 7302 case QUIRK_R3D:
7303 case QUIRK_AE5:
7304 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8a19bcee 7305 codec->card->dev) != 0) {
6ef0e91e 7306 codec_dbg(codec, "Desktop firmware not found.");
8a19bcee
CM		 7307 spec->alt_firmware_present = false;
7308 } else {
7a928186 7309 codec_dbg(codec, "Desktop firmware selected.");
8a19bcee
CM		 7310 spec->alt_firmware_present = true;
7311 }
7312 break;
7313 case QUIRK_R3DI:
7314 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
7315 codec->card->dev) != 0) {
7316 codec_dbg(codec, "Recon3Di alt firmware not detected.");
7317 spec->alt_firmware_present = false;
7318 } else {
7319 codec_dbg(codec, "Recon3Di firmware selected.");
7320 spec->alt_firmware_present = true;
7321 }
7322 break;
7323 default:
7324 spec->alt_firmware_present = false;
7325 break;
7326 }
7327 /*
7328 * Use default ctefx.bin if no alt firmware is detected, or if none
7329 * exists for your particular codec.
7330 */
7331 if (!spec->alt_firmware_present) {
7332 codec_dbg(codec, "Default firmware selected.");
7333 if (request_firmware(&fw_entry, EFX_FILE,
7334 codec->card->dev) != 0)
7335 return false;
7336 }
e90f29e4 7337
15e4ba66 7338 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 7339 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 7340 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 7341 goto exit_download;
7342 }
7343
e90f29e4
IM		 7344 dsp_loaded = dspload_wait_loaded(codec);
7345
d1d28500 7346exit_download:
15e4ba66
TI		 7347 release_firmware(fw_entry);
7348
e90f29e4
IM		 7349 return dsp_loaded;
7350}
7351
7352static void ca0132_download_dsp(struct hda_codec *codec)
7353{
7354 struct ca0132_spec *spec = codec->spec;
7355
9a0869f4
TI		 7356#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7357 return; /* NOP */
7358#endif
e90f29e4 7359
e24aa0a4
TI		 7360 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7361 return; /* don't retry failures */
7362
b714a710 7363 chipio_enable_clocks(codec);
e93ac30a
CM		 7364 if (spec->dsp_state != DSP_DOWNLOADED) {
7365 spec->dsp_state = DSP_DOWNLOADING;
7366
7367 if (!ca0132_download_dsp_images(codec))
7368 spec->dsp_state = DSP_DOWNLOAD_FAILED;
7369 else
7370 spec->dsp_state = DSP_DOWNLOADED;
7371 }
e90f29e4 7372
009b8f97
CM		 7373 /* For codecs using alt functions, this is already done earlier */
7374 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 7375 ca0132_set_dsp_msr(codec, true);
7376}
7377
f8fb1170
TI		 7378static void ca0132_process_dsp_response(struct hda_codec *codec,
7379 struct hda_jack_callback *callback)
e90f29e4
IM		 7380{
7381 struct ca0132_spec *spec = codec->spec;
7382
4e76a883 7383 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 7384 if (spec->wait_scp) {
7385 if (dspio_get_response_data(codec) >= 0)
7386 spec->wait_scp = 0;
7387 }
7388
7389 dspio_clear_response_queue(codec);
7390}
7391
f8fb1170 7392static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 7393{
993884f6 7394 struct ca0132_spec *spec = codec->spec;
2ebab40e 7395 struct hda_jack_tbl *tbl;
e90f29e4 7396
f8fb1170
TI		 7397 /* Delay enabling the HP amp, to let the mic-detection
7398 * state machine run.
7399 */
7400 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 7401 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 7402 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7403 if (tbl)
7404 tbl->block_report = 1;
f8fb1170
TI		 7405}
7406
7407static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7408{
a1b7f016
CM		 7409 struct ca0132_spec *spec = codec->spec;
7410
7411 if (spec->use_alt_functions)
7412 ca0132_alt_select_in(codec);
7413 else
7414 ca0132_select_mic(codec);
f8fb1170
TI		 7415}
7416
7417static void ca0132_init_unsol(struct hda_codec *codec)
7418{
d5c016b5
GM		 7419 struct ca0132_spec *spec = codec->spec;
7420 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7421 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 7422 amic_callback);
7423 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7424 ca0132_process_dsp_response);
63177afc 7425 /* Front headphone jack detection */
009b8f97 7426 if (spec->use_alt_functions)
63177afc
CM		 7427 snd_hda_jack_detect_enable_callback(codec,
7428 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 7429}
7430
5aaca44d
IM		 7431/*
7432 * Verbs tables.
7433 */
7434
7435/* Sends before DSP download. */
7436static struct hda_verb ca0132_base_init_verbs[] = {
7437 /*enable ct extension*/
7438 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 7439 {}
7440};
7441
7442/* Send at exit. */
7443static struct hda_verb ca0132_base_exit_verbs[] = {
7444 /*set afg to D3*/
7445 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7446 /*disable ct extension*/
7447 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7448 {}
7449};
7450
8a19bcee 7451/* Other verbs tables. Sends after DSP download. */
e93ac30a 7452
5aaca44d
IM		 7453static struct hda_verb ca0132_init_verbs0[] = {
7454 /* chip init verbs */
7455 {0x15, 0x70D, 0xF0},
7456 {0x15, 0x70E, 0xFE},
7457 {0x15, 0x707, 0x75},
7458 {0x15, 0x707, 0xD3},
7459 {0x15, 0x707, 0x09},
7460 {0x15, 0x707, 0x53},
7461 {0x15, 0x707, 0xD4},
7462 {0x15, 0x707, 0xEF},
7463 {0x15, 0x707, 0x75},
7464 {0x15, 0x707, 0xD3},
7465 {0x15, 0x707, 0x09},
7466 {0x15, 0x707, 0x02},
7467 {0x15, 0x707, 0x37},
7468 {0x15, 0x707, 0x78},
7469 {0x15, 0x53C, 0xCE},
7470 {0x15, 0x575, 0xC9},
7471 {0x15, 0x53D, 0xCE},
7472 {0x15, 0x5B7, 0xC9},
7473 {0x15, 0x70D, 0xE8},
7474 {0x15, 0x70E, 0xFE},
7475 {0x15, 0x707, 0x02},
7476 {0x15, 0x707, 0x68},
7477 {0x15, 0x707, 0x62},
7478 {0x15, 0x53A, 0xCE},
7479 {0x15, 0x546, 0xC9},
7480 {0x15, 0x53B, 0xCE},
7481 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 7482 {}
7483};
7484
e42c7c73
CM		 7485/* Extra init verbs for desktop cards. */
7486static struct hda_verb ca0132_init_verbs1[] = {
e93ac30a
CM		 7487 {0x15, 0x70D, 0x20},
7488 {0x15, 0x70E, 0x19},
7489 {0x15, 0x707, 0x00},
7490 {0x15, 0x539, 0xCE},
7491 {0x15, 0x546, 0xC9},
7492 {0x15, 0x70D, 0xB7},
7493 {0x15, 0x70E, 0x09},
7494 {0x15, 0x707, 0x10},
7495 {0x15, 0x70D, 0xAF},
7496 {0x15, 0x70E, 0x09},
7497 {0x15, 0x707, 0x01},
7498 {0x15, 0x707, 0x05},
7499 {0x15, 0x70D, 0x73},
7500 {0x15, 0x70E, 0x09},
7501 {0x15, 0x707, 0x14},
7502 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 7503 {}
7504};
7505
95c6e9cb
IM		 7506static void ca0132_init_chip(struct hda_codec *codec)
7507{
7508 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7509 int num_fx;
7510 int i;
7511 unsigned int on;
95c6e9cb
IM		 7512
7513 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 7514
7515 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 7516 if (!spec->use_alt_functions)
7517 spec->cur_mic_type = DIGITAL_MIC;
7518 else
7519 spec->cur_mic_type = REAR_MIC;
7520
5aaca44d
IM		 7521 spec->cur_mic_boost = 0;
7522
7523 for (i = 0; i < VNODES_COUNT; i++) {
7524 spec->vnode_lvol[i] = 0x5a;
7525 spec->vnode_rvol[i] = 0x5a;
7526 spec->vnode_lswitch[i] = 0;
7527 spec->vnode_rswitch[i] = 0;
7528 }
7529
7530 /*
7531 * Default states for effects are in ca0132_effects[].
7532 */
7533 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7534 for (i = 0; i < num_fx; i++) {
7535 on = (unsigned int)ca0132_effects[i].reqs[0];
7536 spec->effects_switch[i] = on ? 1 : 0;
7537 }
47cdf76e
CM		 7538 /*
7539 * Sets defaults for the effect slider controls, only for alternative
7540 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7541 */
7542 if (spec->use_alt_controls) {
7543 spec->xbass_xover_freq = 8;
7544 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7545 spec->fx_ctl_val[i] = effect_slider_defaults[i];
7546 }
5aaca44d
IM		 7547
7548 spec->voicefx_val = 0;
7549 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7550 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7551
44f0c978
IM		 7552#ifdef ENABLE_TUNING_CONTROLS
7553 ca0132_init_tuning_defaults(codec);
7554#endif
95c6e9cb
IM		 7555}
7556
2e48b2b7
CM		 7557/*
7558 * Recon3Di exit specific commands.
7559 */
7560/* prevents popping noise on shutdown */
7561static void r3di_gpio_shutdown(struct hda_codec *codec)
7562{
7563 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7564}
7565
7566/*
7567 * Sound Blaster Z exit specific commands.
7568 */
7569static void sbz_region2_exit(struct hda_codec *codec)
7570{
7571 struct ca0132_spec *spec = codec->spec;
7572 unsigned int i;
7573
7574 for (i = 0; i < 4; i++)
7575 writeb(0x0, spec->mem_base + 0x100);
7576 for (i = 0; i < 8; i++)
7577 writeb(0xb3, spec->mem_base + 0x304);
a62e4739 7578
b9b41345
CM		 7579 ca0113_mmio_gpio_set(codec, 0, false);
7580 ca0113_mmio_gpio_set(codec, 1, false);
7581 ca0113_mmio_gpio_set(codec, 4, true);
7582 ca0113_mmio_gpio_set(codec, 5, false);
7583 ca0113_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 7584}
7585
7586static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7587{
7588 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7589 unsigned int i;
7590
7591 snd_hda_codec_write(codec, 0x11, 0,
7592 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7593
7594 for (i = 0; i < 5; i++)
7595 snd_hda_codec_write(codec, pins[i], 0,
7596 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7597}
7598
2f295f91 7599static void ca0132_clear_unsolicited(struct hda_codec *codec)
2e48b2b7
CM		 7600{
7601 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7602 unsigned int i;
7603
7604 for (i = 0; i < 7; i++) {
7605 snd_hda_codec_write(codec, pins[i], 0,
7606 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7607 }
7608}
7609
7610/* On shutdown, sends commands in sets of three */
7611static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7612 int mask, int data)
7613{
7614 if (dir >= 0)
7615 snd_hda_codec_write(codec, 0x01, 0,
7616 AC_VERB_SET_GPIO_DIRECTION, dir);
7617 if (mask >= 0)
7618 snd_hda_codec_write(codec, 0x01, 0,
7619 AC_VERB_SET_GPIO_MASK, mask);
7620
7621 if (data >= 0)
7622 snd_hda_codec_write(codec, 0x01, 0,
7623 AC_VERB_SET_GPIO_DATA, data);
7624}
7625
7626static void sbz_exit_chip(struct hda_codec *codec)
7627{
009b8f97
CM		 7628 chipio_set_stream_control(codec, 0x03, 0);
7629 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 7630
7631 /* Mess with GPIO */
7632 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7633 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7634 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7635
009b8f97
CM		 7636 chipio_set_stream_control(codec, 0x14, 0);
7637 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7638
7639 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7640 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7641
7642 chipio_write(codec, 0x18a020, 0x00000083);
7643
7644 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7645 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7646 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7647
009b8f97 7648 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7649
7650 chipio_set_control_param(codec, 0x0D, 0x24);
7651
2f295f91 7652 ca0132_clear_unsolicited(codec);
2e48b2b7
CM		 7653 sbz_set_pin_ctl_default(codec);
7654
7655 snd_hda_codec_write(codec, 0x0B, 0,
7656 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7657
2e48b2b7
CM		 7658 sbz_region2_exit(codec);
7659}
7660
2f295f91
CM		 7661static void r3d_exit_chip(struct hda_codec *codec)
7662{
7663 ca0132_clear_unsolicited(codec);
7664 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7665 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7666}
7667
95c6e9cb
IM		 7668static void ca0132_exit_chip(struct hda_codec *codec)
7669{
7670 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7671
7672 if (dspload_is_loaded(codec))
7673 dsp_reset(codec);
95c6e9cb
IM		 7674}
7675
38ba69ff
CM		 7676/*
7677 * This fixes a problem that was hard to reproduce. Very rarely, I would
7678 * boot up, and there would be no sound, but the DSP indicated it had loaded
7679 * properly. I did a few memory dumps to see if anything was different, and
7680 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7681 * checks if those areas are uninitialized, and if they are, it'll attempt to
7682 * reload the card 3 times. Usually it fixes by the second.
7683 */
7684static void sbz_dsp_startup_check(struct hda_codec *codec)
7685{
7686 struct ca0132_spec *spec = codec->spec;
7687 unsigned int dsp_data_check[4];
7688 unsigned int cur_address = 0x390;
7689 unsigned int i;
7690 unsigned int failure = 0;
7691 unsigned int reload = 3;
7692
7693 if (spec->startup_check_entered)
7694 return;
7695
7696 spec->startup_check_entered = true;
7697
7698 for (i = 0; i < 4; i++) {
7699 chipio_read(codec, cur_address, &dsp_data_check[i]);
7700 cur_address += 0x4;
7701 }
7702 for (i = 0; i < 4; i++) {
7703 if (dsp_data_check[i] == 0xa1a2a3a4)
7704 failure = 1;
7705 }
7706
7707 codec_dbg(codec, "Startup Check: %d ", failure);
7708 if (failure)
7709 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7710 /*
7711 * While the failure condition is true, and we haven't reached our
7712 * three reload limit, continue trying to reload the driver and
7713 * fix the issue.
7714 */
7715 while (failure && (reload != 0)) {
7716 codec_info(codec, "Reloading... Tries left: %d", reload);
7717 sbz_exit_chip(codec);
7718 spec->dsp_state = DSP_DOWNLOAD_INIT;
7719 codec->patch_ops.init(codec);
7720 failure = 0;
7721 for (i = 0; i < 4; i++) {
7722 chipio_read(codec, cur_address, &dsp_data_check[i]);
7723 cur_address += 0x4;
7724 }
7725 for (i = 0; i < 4; i++) {
7726 if (dsp_data_check[i] == 0xa1a2a3a4)
7727 failure = 1;
7728 }
7729 reload--;
7730 }
7731
7732 if (!failure && reload < 3)
7733 codec_info(codec, "DSP fixed.");
7734
7735 if (!failure)
7736 return;
7737
7738 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7739}
7740
e93ac30a
CM		 7741/*
7742 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7743 * extra precision for decibel values. If you had the dB value in floating point
7744 * you would take the value after the decimal point, multiply by 64, and divide
7745 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7746 * implement fixed point or floating point dB volumes. For now, I'll set them
7747 * to 0 just incase a value has lingered from a boot into Windows.
7748 */
7749static void ca0132_alt_vol_setup(struct hda_codec *codec)
7750{
7751 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7752 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7753 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7754 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7755 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7756 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7757 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7758 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7759}
7760
7761/*
7762 * Extra commands that don't really fit anywhere else.
7763 */
7764static void sbz_pre_dsp_setup(struct hda_codec *codec)
7765{
7766 struct ca0132_spec *spec = codec->spec;
7767
7768 writel(0x00820680, spec->mem_base + 0x01C);
7769 writel(0x00820680, spec->mem_base + 0x01C);
7770
e93ac30a
CM		 7771 chipio_write(codec, 0x18b0a4, 0x000000c2);
7772
7773 snd_hda_codec_write(codec, 0x11, 0,
7774 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7775}
7776
e42c7c73
CM		 7777static void r3d_pre_dsp_setup(struct hda_codec *codec)
7778{
e42c7c73
CM		 7779 chipio_write(codec, 0x18b0a4, 0x000000c2);
7780
7781 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7782 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7783 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7784 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7785 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7786 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7787
7788 snd_hda_codec_write(codec, 0x11, 0,
7789 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7790}
7791
e93ac30a
CM		 7792static void r3di_pre_dsp_setup(struct hda_codec *codec)
7793{
7794 chipio_write(codec, 0x18b0a4, 0x000000c2);
7795
7796 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7797 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7798 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7799 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7800 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7801 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7802
7803 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7804 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7805 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7806 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7807 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7808 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7809 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7810 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7811
7812 snd_hda_codec_write(codec, 0x11, 0,
7813 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7814}
7815
e93ac30a
CM		 7816/*
7817 * These are sent before the DSP is downloaded. Not sure
7818 * what they do, or if they're necessary. Could possibly
7819 * be removed. Figure they're better to leave in.
7820 */
e42c7c73 7821static void ca0132_mmio_init(struct hda_codec *codec)
e93ac30a
CM		 7822{
7823 struct ca0132_spec *spec = codec->spec;
7824
ce715448
CM		 7825 if (spec->quirk == QUIRK_AE5)
7826 writel(0x00000001, spec->mem_base + 0x400);
7827 else
7828 writel(0x00000000, spec->mem_base + 0x400);
7829
7830 if (spec->quirk == QUIRK_AE5)
7831 writel(0x00000001, spec->mem_base + 0x408);
7832 else
7833 writel(0x00000000, spec->mem_base + 0x408);
7834
7835 if (spec->quirk == QUIRK_AE5)
7836 writel(0x00000001, spec->mem_base + 0x40c);
7837 else
7838 writel(0x00000000, spec->mem_base + 0x40C);
7839
e93ac30a 7840 writel(0x00880680, spec->mem_base + 0x01C);
ce715448
CM		 7841
7842 if (spec->quirk == QUIRK_AE5)
7843 writel(0x00000080, spec->mem_base + 0xC0C);
7844 else
7845 writel(0x00000083, spec->mem_base + 0xC0C);
7846
e93ac30a
CM		 7847 writel(0x00000030, spec->mem_base + 0xC00);
7848 writel(0x00000000, spec->mem_base + 0xC04);
ce715448
CM		 7849
7850 if (spec->quirk == QUIRK_AE5)
7851 writel(0x00000000, spec->mem_base + 0xC0C);
7852 else
7853 writel(0x00000003, spec->mem_base + 0xC0C);
7854
e93ac30a
CM		 7855 writel(0x00000003, spec->mem_base + 0xC0C);
7856 writel(0x00000003, spec->mem_base + 0xC0C);
7857 writel(0x00000003, spec->mem_base + 0xC0C);
ce715448
CM		 7858
7859 if (spec->quirk == QUIRK_AE5)
7860 writel(0x00000001, spec->mem_base + 0xC08);
7861 else
7862 writel(0x000000C1, spec->mem_base + 0xC08);
7863
e93ac30a
CM		 7864 writel(0x000000F1, spec->mem_base + 0xC08);
7865 writel(0x00000001, spec->mem_base + 0xC08);
7866 writel(0x000000C7, spec->mem_base + 0xC08);
7867 writel(0x000000C1, spec->mem_base + 0xC08);
7868 writel(0x00000080, spec->mem_base + 0xC04);
ce715448
CM		 7869
7870 if (spec->quirk == QUIRK_AE5) {
7871 writel(0x00000000, spec->mem_base + 0x42c);
7872 writel(0x00000000, spec->mem_base + 0x46c);
7873 writel(0x00000000, spec->mem_base + 0x4ac);
7874 writel(0x00000000, spec->mem_base + 0x4ec);
7875 writel(0x00000000, spec->mem_base + 0x43c);
7876 writel(0x00000000, spec->mem_base + 0x47c);
7877 writel(0x00000000, spec->mem_base + 0x4bc);
7878 writel(0x00000000, spec->mem_base + 0x4fc);
7879 writel(0x00000600, spec->mem_base + 0x100);
7880 writel(0x00000014, spec->mem_base + 0x410);
7881 writel(0x0000060f, spec->mem_base + 0x100);
7882 writel(0x0000070f, spec->mem_base + 0x100);
7883 writel(0x00000aff, spec->mem_base + 0x830);
7884 writel(0x00000000, spec->mem_base + 0x86c);
7885 writel(0x0000006b, spec->mem_base + 0x800);
7886 writel(0x00000001, spec->mem_base + 0x86c);
7887 writel(0x0000006b, spec->mem_base + 0x800);
7888 writel(0x00000057, spec->mem_base + 0x804);
7889 writel(0x00800000, spec->mem_base + 0x20c);
7890 }
e93ac30a
CM		 7891}
7892
b9b41345
CM		 7893/*
7894 * This function writes to some SFR's, does some region2 writes, and then
7895 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
7896 * what it does.
7897 */
7898static void ae5_register_set(struct hda_codec *codec)
7899{
7900 struct ca0132_spec *spec = codec->spec;
7901
7902 chipio_8051_write_direct(codec, 0x93, 0x10);
7903 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7904 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7905 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7906 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7907
7908 writeb(0x0f, spec->mem_base + 0x304);
7909 writeb(0x0f, spec->mem_base + 0x304);
7910 writeb(0x0f, spec->mem_base + 0x304);
7911 writeb(0x0f, spec->mem_base + 0x304);
7912 writeb(0x0e, spec->mem_base + 0x100);
7913 writeb(0x1f, spec->mem_base + 0x304);
7914 writeb(0x0c, spec->mem_base + 0x100);
7915 writeb(0x3f, spec->mem_base + 0x304);
7916 writeb(0x08, spec->mem_base + 0x100);
7917 writeb(0x7f, spec->mem_base + 0x304);
7918 writeb(0x00, spec->mem_base + 0x100);
7919 writeb(0xff, spec->mem_base + 0x304);
7920
7921 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7922
7923 chipio_8051_write_direct(codec, 0x90, 0x00);
7924 chipio_8051_write_direct(codec, 0x90, 0x10);
7925
7926 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7927
7928 chipio_write(codec, 0x18b0a4, 0x000000c2);
7929
7930 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
7931 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
7932}
7933
e93ac30a
CM		 7934/*
7935 * Extra init functions for alternative ca0132 codecs. Done
7936 * here so they don't clutter up the main ca0132_init function
7937 * anymore than they have to.
7938 */
7939static void ca0132_alt_init(struct hda_codec *codec)
7940{
7941 struct ca0132_spec *spec = codec->spec;
7942
7943 ca0132_alt_vol_setup(codec);
7944
7945 switch (spec->quirk) {
7946 case QUIRK_SBZ:
7947 codec_dbg(codec, "SBZ alt_init");
7948 ca0132_gpio_init(codec);
7949 sbz_pre_dsp_setup(codec);
7950 snd_hda_sequence_write(codec, spec->chip_init_verbs);
e42c7c73 7951 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
e93ac30a
CM		 7952 break;
7953 case QUIRK_R3DI:
7954 codec_dbg(codec, "R3DI alt_init");
7955 ca0132_gpio_init(codec);
7956 ca0132_gpio_setup(codec);
7e6ed62e 7957 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 7958 r3di_pre_dsp_setup(codec);
7959 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7960 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7961 break;
e42c7c73
CM		 7962 case QUIRK_R3D:
7963 r3d_pre_dsp_setup(codec);
7964 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7965 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7966 break;
03c9b6b1
CM		 7967 case QUIRK_AE5:
7968 ca0132_gpio_init(codec);
7969 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7970 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
7971 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7972 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
7973 chipio_write(codec, 0x18b030, 0x00000020);
7974 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7975 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7976 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7977 break;
e93ac30a
CM		 7978 }
7979}
7980
95c6e9cb
IM		 7981static int ca0132_init(struct hda_codec *codec)
7982{
7983 struct ca0132_spec *spec = codec->spec;
7984 struct auto_pin_cfg *cfg = &spec->autocfg;
7985 int i;
e93ac30a
CM		 7986 bool dsp_loaded;
7987
7988 /*
7989 * If the DSP is already downloaded, and init has been entered again,
7990 * there's only two reasons for it. One, the codec has awaken from a
7991 * suspended state, and in that case dspload_is_loaded will return
7992 * false, and the init will be ran again. The other reason it gets
7993 * re entered is on startup for some reason it triggers a suspend and
7994 * resume state. In this case, it will check if the DSP is downloaded,
7995 * and not run the init function again. For codecs using alt_functions,
7996 * it will check if the DSP is loaded properly.
7997 */
7998 if (spec->dsp_state == DSP_DOWNLOADED) {
7999 dsp_loaded = dspload_is_loaded(codec);
8000 if (!dsp_loaded) {
8001 spec->dsp_reload = true;
8002 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 8003 } else {
8004 if (spec->quirk == QUIRK_SBZ)
8005 sbz_dsp_startup_check(codec);
e93ac30a 8006 return 0;
38ba69ff 8007 }
e93ac30a 8008 }
95c6e9cb 8009
e24aa0a4
TI		 8010 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
8011 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 8012 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 8013
e42c7c73
CM		 8014 if (spec->use_pci_mmio)
8015 ca0132_mmio_init(codec);
e93ac30a 8016
664c7155 8017 snd_hda_power_up_pm(codec);
5aaca44d 8018
b9b41345
CM		 8019 if (spec->quirk == QUIRK_AE5)
8020 ae5_register_set(codec);
8021
f8fb1170 8022 ca0132_init_unsol(codec);
5aaca44d
IM		 8023 ca0132_init_params(codec);
8024 ca0132_init_flags(codec);
7e6ed62e 8025
5aaca44d 8026 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 8027
365c7f25 8028 if (spec->use_alt_functions)
e93ac30a
CM		 8029 ca0132_alt_init(codec);
8030
01ef7dbf 8031 ca0132_download_dsp(codec);
7e6ed62e 8032
5aaca44d 8033 ca0132_refresh_widget_caps(codec);
e93ac30a 8034
7e6ed62e
CM		 8035 switch (spec->quirk) {
8036 case QUIRK_R3DI:
c986f50c
CM		 8037 case QUIRK_R3D:
8038 r3d_setup_defaults(codec);
7e6ed62e 8039 break;
126b75e0 8040 case QUIRK_SBZ:
d97420d2 8041 sbz_setup_defaults(codec);
126b75e0 8042 break;
415cd844
CM		 8043 case QUIRK_AE5:
8044 ae5_setup_defaults(codec);
8045 break;
126b75e0 8046 default:
38ba69ff
CM		 8047 ca0132_setup_defaults(codec);
8048 ca0132_init_analog_mic2(codec);
8049 ca0132_init_dmic(codec);
7e6ed62e 8050 break;
38ba69ff 8051 }
5aaca44d
IM		 8052
8053 for (i = 0; i < spec->num_outputs; i++)
8054 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 8055
95c6e9cb
IM		 8056 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8057
8058 for (i = 0; i < spec->num_inputs; i++)
8059 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8060
8061 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8062
009b8f97 8063 if (!spec->use_alt_functions) {
e93ac30a
CM		 8064 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8065 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8066 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
8067 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8068 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
8069 }
8070
7cb9d94c 8071 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 8072 ca0132_gpio_setup(codec);
8073
d5c016b5 8074 snd_hda_sequence_write(codec, spec->spec_init_verbs);
d97420d2 8075 if (spec->use_alt_functions) {
7cb9d94c
CM		 8076 ca0132_alt_select_out(codec);
8077 ca0132_alt_select_in(codec);
d97420d2 8078 } else {
7cb9d94c
CM		 8079 ca0132_select_out(codec);
8080 ca0132_select_mic(codec);
7cb9d94c 8081 }
5aaca44d 8082
a73d511c
IM		 8083 snd_hda_jack_report_sync(codec);
8084
e93ac30a
CM		 8085 /*
8086 * Re set the PlayEnhancement switch on a resume event, because the
8087 * controls will not be reloaded.
8088 */
8089 if (spec->dsp_reload) {
8090 spec->dsp_reload = false;
8091 ca0132_pe_switch_set(codec);
8092 }
8093
664c7155 8094 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 8095
8096 return 0;
8097}
8098
95c6e9cb
IM		 8099static void ca0132_free(struct hda_codec *codec)
8100{
5aaca44d
IM		 8101 struct ca0132_spec *spec = codec->spec;
8102
993884f6 8103 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 8104 snd_hda_power_up(codec);
2e48b2b7
CM		 8105 switch (spec->quirk) {
8106 case QUIRK_SBZ:
8107 sbz_exit_chip(codec);
8108 break;
2f295f91
CM		 8109 case QUIRK_R3D:
8110 r3d_exit_chip(codec);
8111 break;
2e48b2b7
CM		 8112 case QUIRK_R3DI:
8113 r3di_gpio_shutdown(codec);
2e48b2b7
CM		 8114 break;
8115 }
2f295f91
CM		 8116
8117 snd_hda_sequence_write(codec, spec->base_exit_verbs);
8118 ca0132_exit_chip(codec);
8119
5aaca44d 8120 snd_hda_power_down(codec);
aa31704f
CM		 8121 if (spec->mem_base)
8122 iounmap(spec->mem_base);
d5c016b5 8123 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 8124 kfree(codec->spec);
8125}
8126
2e48b2b7
CM		 8127static void ca0132_reboot_notify(struct hda_codec *codec)
8128{
8129 codec->patch_ops.free(codec);
8130}
8131
071f1344 8132static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 8133 .build_controls = ca0132_build_controls,
8134 .build_pcms = ca0132_build_pcms,
8135 .init = ca0132_init,
8136 .free = ca0132_free,
f8fb1170 8137 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 8138 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 8139};
8140
441aa6a0
IM		 8141static void ca0132_config(struct hda_codec *codec)
8142{
8143 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 8144
8145 spec->dacs[0] = 0x2;
8146 spec->dacs[1] = 0x3;
8147 spec->dacs[2] = 0x4;
8148
8149 spec->multiout.dac_nids = spec->dacs;
8150 spec->multiout.num_dacs = 3;
441aa6a0 8151
009b8f97 8152 if (!spec->use_alt_functions)
63177afc
CM		 8153 spec->multiout.max_channels = 2;
8154 else
8155 spec->multiout.max_channels = 6;
8156
8157 switch (spec->quirk) {
8158 case QUIRK_ALIENWARE:
d06feaf0 8159 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
fe14f39e 8160 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
d06feaf0
CM		 8161 break;
8162 case QUIRK_SBZ:
8163 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
8164 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
8165 break;
8166 case QUIRK_R3D:
8167 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
8168 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
8169 break;
8170 case QUIRK_R3DI:
8171 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
8172 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8173 break;
8174 case QUIRK_AE5:
8175 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
8176 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8177 break;
8178 }
fe14f39e 8179
d06feaf0
CM		 8180 switch (spec->quirk) {
8181 case QUIRK_ALIENWARE:
fe14f39e
TI		 8182 spec->num_outputs = 2;
8183 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8184 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 8185 spec->shared_out_nid = 0x2;
8186 spec->unsol_tag_hp = 0x0f;
8187
8188 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8189 spec->adcs[1] = 0x8; /* analog mic2 */
8190 spec->adcs[2] = 0xa; /* what u hear */
8191
8192 spec->num_inputs = 3;
8193 spec->input_pins[0] = 0x12;
8194 spec->input_pins[1] = 0x11;
8195 spec->input_pins[2] = 0x13;
8196 spec->shared_mic_nid = 0x7;
8197 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 8198 break;
8199 case QUIRK_SBZ:
7f73df95 8200 case QUIRK_R3D:
63177afc
CM		 8201 spec->num_outputs = 2;
8202 spec->out_pins[0] = 0x0B; /* Line out */
8203 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8204 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8205 spec->out_pins[3] = 0x11; /* Rear surround */
8206 spec->shared_out_nid = 0x2;
8207 spec->unsol_tag_hp = spec->out_pins[1];
8208 spec->unsol_tag_front_hp = spec->out_pins[2];
8209
8210 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8211 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8212 spec->adcs[2] = 0xa; /* what u hear */
8213
8214 spec->num_inputs = 2;
8215 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8216 spec->input_pins[1] = 0x13; /* What U Hear */
8217 spec->shared_mic_nid = 0x7;
8218 spec->unsol_tag_amic1 = spec->input_pins[0];
8219
8220 /* SPDIF I/O */
8221 spec->dig_out = 0x05;
8222 spec->multiout.dig_out_nid = spec->dig_out;
63177afc 8223 spec->dig_in = 0x09;
63177afc 8224 break;
d06feaf0
CM		 8225 case QUIRK_AE5:
8226 spec->num_outputs = 2;
8227 spec->out_pins[0] = 0x0B; /* Line out */
8228 spec->out_pins[1] = 0x11; /* Rear headphone out */
8229 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8230 spec->out_pins[3] = 0x0F; /* Rear surround */
8231 spec->shared_out_nid = 0x2;
8232 spec->unsol_tag_hp = spec->out_pins[1];
8233 spec->unsol_tag_front_hp = spec->out_pins[2];
8234
8235 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8236 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8237 spec->adcs[2] = 0xa; /* what u hear */
63177afc 8238
d06feaf0
CM		 8239 spec->num_inputs = 2;
8240 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8241 spec->input_pins[1] = 0x13; /* What U Hear */
8242 spec->shared_mic_nid = 0x7;
8243 spec->unsol_tag_amic1 = spec->input_pins[0];
8244
8245 /* SPDIF I/O */
8246 spec->dig_out = 0x05;
8247 spec->multiout.dig_out_nid = spec->dig_out;
8248 break;
8249 case QUIRK_R3DI:
63177afc
CM		 8250 spec->num_outputs = 2;
8251 spec->out_pins[0] = 0x0B; /* Line out */
8252 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8253 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8254 spec->out_pins[3] = 0x11; /* Rear surround */
8255 spec->shared_out_nid = 0x2;
8256 spec->unsol_tag_hp = spec->out_pins[1];
8257 spec->unsol_tag_front_hp = spec->out_pins[2];
8258
8259 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
8260 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
8261 spec->adcs[2] = 0x0a; /* what u hear */
8262
8263 spec->num_inputs = 2;
8264 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8265 spec->input_pins[1] = 0x13; /* What U Hear */
8266 spec->shared_mic_nid = 0x7;
8267 spec->unsol_tag_amic1 = spec->input_pins[0];
8268
8269 /* SPDIF I/O */
8270 spec->dig_out = 0x05;
8271 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 8272 break;
8273 default:
fe14f39e
TI		 8274 spec->num_outputs = 2;
8275 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8276 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 8277 spec->shared_out_nid = 0x2;
8278 spec->unsol_tag_hp = spec->out_pins[1];
8279
8280 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8281 spec->adcs[1] = 0x8; /* analog mic2 */
8282 spec->adcs[2] = 0xa; /* what u hear */
8283
8284 spec->num_inputs = 3;
8285 spec->input_pins[0] = 0x12;
8286 spec->input_pins[1] = 0x11;
8287 spec->input_pins[2] = 0x13;
8288 spec->shared_mic_nid = 0x7;
8289 spec->unsol_tag_amic1 = spec->input_pins[0];
8290
8291 /* SPDIF I/O */
8292 spec->dig_out = 0x05;
8293 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 8294 spec->dig_in = 0x09;
63177afc 8295 break;
d5c016b5 8296 }
441aa6a0
IM		 8297}
8298
d5c016b5
GM		 8299static int ca0132_prepare_verbs(struct hda_codec *codec)
8300{
8301/* Verbs + terminator (an empty element) */
a3d90d67 8302#define NUM_SPEC_VERBS 2
d5c016b5
GM		 8303 struct ca0132_spec *spec = codec->spec;
8304
8305 spec->chip_init_verbs = ca0132_init_verbs0;
88268ce8
CM		 8306 /*
8307 * Since desktop cards use pci_mmio, this can be used to determine
8308 * whether or not to use these verbs instead of a separate bool.
8309 */
8310 if (spec->use_pci_mmio)
e42c7c73 8311 spec->desktop_init_verbs = ca0132_init_verbs1;
6396bb22
KC		 8312 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
8313 sizeof(struct hda_verb),
8314 GFP_KERNEL);
d5c016b5
GM		 8315 if (!spec->spec_init_verbs)
8316 return -ENOMEM;
8317
d5c016b5 8318 /* config EAPD */
a3d90d67
AB		 8319 spec->spec_init_verbs[0].nid = 0x0b;
8320 spec->spec_init_verbs[0].param = 0x78D;
8321 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 8322
8323 /* Previously commented configuration */
8324 /*
a3d90d67
AB		 8325 spec->spec_init_verbs[2].nid = 0x0b;
8326 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8327 spec->spec_init_verbs[2].verb = 0x02;
8328
8329 spec->spec_init_verbs[3].nid = 0x10;
8330 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 8331 spec->spec_init_verbs[3].verb = 0x02;
8332
8333 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 8334 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 8335 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 8336 */
8337
8338 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8339 return 0;
8340}
8341
95c6e9cb
IM		 8342static int patch_ca0132(struct hda_codec *codec)
8343{
8344 struct ca0132_spec *spec;
a73d511c 8345 int err;
d5c016b5 8346 const struct snd_pci_quirk *quirk;
95c6e9cb 8347
4e76a883 8348 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 8349
8350 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8351 if (!spec)
8352 return -ENOMEM;
8353 codec->spec = spec;
993884f6 8354 spec->codec = codec;
95c6e9cb 8355
225068ab
TI		 8356 codec->patch_ops = ca0132_patch_ops;
8357 codec->pcm_format_first = 1;
8358 codec->no_sticky_stream = 1;
8359
d5c016b5
GM		 8360 /* Detect codec quirk */
8361 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8362 if (quirk)
8363 spec->quirk = quirk->value;
8364 else
8365 spec->quirk = QUIRK_NONE;
8366
e24aa0a4 8367 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 8368 spec->num_mixers = 1;
017310fb
CM		 8369
8370 /* Set which mixers each quirk uses. */
8371 switch (spec->quirk) {
8372 case QUIRK_SBZ:
e25e3445 8373 spec->mixers[0] = desktop_mixer;
017310fb
CM		 8374 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8375 break;
e25e3445
CM		 8376 case QUIRK_R3D:
8377 spec->mixers[0] = desktop_mixer;
8378 snd_hda_codec_set_name(codec, "Recon3D");
8379 break;
017310fb
CM		 8380 case QUIRK_R3DI:
8381 spec->mixers[0] = r3di_mixer;
8382 snd_hda_codec_set_name(codec, "Recon3Di");
8383 break;
88268ce8
CM		 8384 case QUIRK_AE5:
8385 spec->mixers[0] = desktop_mixer;
8386 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8387 break;
017310fb
CM		 8388 default:
8389 spec->mixers[0] = ca0132_mixer;
8390 break;
8391 }
a7e76271 8392
08eca6b1 8393 /* Setup whether or not to use alt functions/controls/pci_mmio */
009b8f97
CM		 8394 switch (spec->quirk) {
8395 case QUIRK_SBZ:
e42c7c73 8396 case QUIRK_R3D:
88268ce8 8397 case QUIRK_AE5:
08eca6b1
CM		 8398 spec->use_alt_controls = true;
8399 spec->use_alt_functions = true;
8400 spec->use_pci_mmio = true;
8401 break;
009b8f97 8402 case QUIRK_R3DI:
47cdf76e 8403 spec->use_alt_controls = true;
009b8f97 8404 spec->use_alt_functions = true;
08eca6b1 8405 spec->use_pci_mmio = false;
009b8f97
CM		 8406 break;
8407 default:
47cdf76e 8408 spec->use_alt_controls = false;
009b8f97 8409 spec->use_alt_functions = false;
08eca6b1 8410 spec->use_pci_mmio = false;
009b8f97
CM		 8411 break;
8412 }
8413
08eca6b1
CM		 8414 if (spec->use_pci_mmio) {
8415 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8416 if (spec->mem_base == NULL) {
8417 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8418 spec->quirk = QUIRK_NONE;
8419 }
8420 }
8421
5aaca44d
IM		 8422 spec->base_init_verbs = ca0132_base_init_verbs;
8423 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 8424
993884f6
CCC		 8425 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8426
95c6e9cb
IM		 8427 ca0132_init_chip(codec);
8428
8429 ca0132_config(codec);
8430
d5c016b5
GM		 8431 err = ca0132_prepare_verbs(codec);
8432 if (err < 0)
cc91ceaf 8433 goto error;
d5c016b5 8434
a73d511c
IM		 8435 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8436 if (err < 0)
cc91ceaf 8437 goto error;
a73d511c 8438
95c6e9cb 8439 return 0;
cc91ceaf
TI		 8440
8441 error:
8442 ca0132_free(codec);
8443 return err;
95c6e9cb
IM		 8444}
8445
8446/*
8447 * patch entries
8448 */
b9a94a9c
TI		 8449static struct hda_device_id snd_hda_id_ca0132[] = {
8450 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 8451 {} /* terminator */
8452};
b9a94a9c 8453MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 8454
8455MODULE_LICENSE("GPL");
406261ce 8456MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 8457
d8a766a1 8458static struct hda_codec_driver ca0132_driver = {
b9a94a9c 8459 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 8460};
8461
d8a766a1 8462module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)