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ALSA: hda - Introduce get_delay codec PCM ops
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
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95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/pci.h>
28#include <linux/mutex.h>
da155d5b 29#include <linux/module.h>
4aa3bb0c 30#include <linux/firmware.h>
95c6e9cb
IM		 31#include <sound/core.h>
32#include "hda_codec.h"
33#include "hda_local.h"
128bc4ba 34#include "hda_auto_parser.h"
5aaca44d 35#include "hda_jack.h"
95c6e9cb 36
bcd109c0
IM		 37#include "ca0132_regs.h"
38
ef6b2ead
IM		 39/* Enable this to see controls for tuning purpose. */
40/*#define ENABLE_TUNING_CONTROLS*/
41
42#define FLOAT_ZERO 0x00000000
43#define FLOAT_ONE 0x3f800000
44#define FLOAT_TWO 0x40000000
45#define FLOAT_MINUS_5 0xc0a00000
46
47#define UNSOL_TAG_HP 0x10
48#define UNSOL_TAG_AMIC1 0x12
49#define UNSOL_TAG_DSP 0x16
50
4aa3bb0c
IM		 51#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
52#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
53
54#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
55#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
56#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
57
58#define MASTERCONTROL 0x80
ef6b2ead
IM		 59#define MASTERCONTROL_ALLOC_DMA_CHAN 10
60#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 61
95c6e9cb
IM		 62#define WIDGET_CHIP_CTRL 0x15
63#define WIDGET_DSP_CTRL 0x16
64
4aa3bb0c
IM		 65#define MEM_CONNID_MICIN1 3
66#define MEM_CONNID_MICIN2 5
67#define MEM_CONNID_MICOUT1 12
68#define MEM_CONNID_MICOUT2 14
69#define MEM_CONNID_WUH 10
70#define MEM_CONNID_DSP 16
71#define MEM_CONNID_DMIC 100
72
73#define SCP_SET 0
74#define SCP_GET 1
75
01ef7dbf
IM		 76#define EFX_FILE "ctefx.bin"
77
24f3cede 78#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 79MODULE_FIRMWARE(EFX_FILE);
7a527ede 80#endif
01ef7dbf 81
ef6b2ead
IM		 82static char *dirstr[2] = { "Playback", "Capture" };
83
84enum {
85 SPEAKER_OUT,
86 HEADPHONE_OUT
87};
88
89enum {
90 DIGITAL_MIC,
91 LINE_MIC_IN
92};
93
94enum {
95#define VNODE_START_NID 0x80
96 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
97 VNID_MIC,
98 VNID_HP_SEL,
99 VNID_AMIC1_SEL,
100 VNID_HP_ASEL,
101 VNID_AMIC1_ASEL,
102 VNODE_END_NID,
103#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
104
105#define EFFECT_START_NID 0x90
106#define OUT_EFFECT_START_NID EFFECT_START_NID
107 SURROUND = OUT_EFFECT_START_NID,
108 CRYSTALIZER,
109 DIALOG_PLUS,
110 SMART_VOLUME,
111 X_BASS,
112 EQUALIZER,
113 OUT_EFFECT_END_NID,
114#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
115
116#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
117 ECHO_CANCELLATION = IN_EFFECT_START_NID,
118 VOICE_FOCUS,
119 MIC_SVM,
120 NOISE_REDUCTION,
121 IN_EFFECT_END_NID,
122#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
123
124 VOICEFX = IN_EFFECT_END_NID,
125 PLAY_ENHANCEMENT,
126 CRYSTAL_VOICE,
127 EFFECT_END_NID
128#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
129};
130
131/* Effects values size*/
132#define EFFECT_VALS_MAX_COUNT 12
133
134struct ct_effect {
135 char name[44];
136 hda_nid_t nid;
137 int mid; /*effect module ID*/
138 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
139 int direct; /* 0:output; 1:input*/
140 int params; /* number of default non-on/off params */
141 /*effect default values, 1st is on/off. */
142 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
143};
144
145#define EFX_DIR_OUT 0
146#define EFX_DIR_IN 1
147
148static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
149 { .name = "Surround",
150 .nid = SURROUND,
151 .mid = 0x96,
152 .reqs = {0, 1},
153 .direct = EFX_DIR_OUT,
154 .params = 1,
155 .def_vals = {0x3F800000, 0x3F2B851F}
156 },
157 { .name = "Crystalizer",
158 .nid = CRYSTALIZER,
159 .mid = 0x96,
160 .reqs = {7, 8},
161 .direct = EFX_DIR_OUT,
162 .params = 1,
163 .def_vals = {0x3F800000, 0x3F266666}
164 },
165 { .name = "Dialog Plus",
166 .nid = DIALOG_PLUS,
167 .mid = 0x96,
168 .reqs = {2, 3},
169 .direct = EFX_DIR_OUT,
170 .params = 1,
171 .def_vals = {0x00000000, 0x3F000000}
172 },
173 { .name = "Smart Volume",
174 .nid = SMART_VOLUME,
175 .mid = 0x96,
176 .reqs = {4, 5, 6},
177 .direct = EFX_DIR_OUT,
178 .params = 2,
179 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
180 },
181 { .name = "X-Bass",
182 .nid = X_BASS,
183 .mid = 0x96,
184 .reqs = {24, 23, 25},
185 .direct = EFX_DIR_OUT,
186 .params = 2,
187 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
188 },
189 { .name = "Equalizer",
190 .nid = EQUALIZER,
191 .mid = 0x96,
192 .reqs = {9, 10, 11, 12, 13, 14,
193 15, 16, 17, 18, 19, 20},
194 .direct = EFX_DIR_OUT,
195 .params = 11,
196 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
197 0x00000000, 0x00000000, 0x00000000, 0x00000000,
198 0x00000000, 0x00000000, 0x00000000, 0x00000000}
199 },
200 { .name = "Echo Cancellation",
201 .nid = ECHO_CANCELLATION,
202 .mid = 0x95,
203 .reqs = {0, 1, 2, 3},
204 .direct = EFX_DIR_IN,
205 .params = 3,
206 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
207 },
208 { .name = "Voice Focus",
209 .nid = VOICE_FOCUS,
210 .mid = 0x95,
211 .reqs = {6, 7, 8, 9},
212 .direct = EFX_DIR_IN,
213 .params = 3,
214 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
215 },
216 { .name = "Mic SVM",
217 .nid = MIC_SVM,
218 .mid = 0x95,
219 .reqs = {44, 45},
220 .direct = EFX_DIR_IN,
221 .params = 1,
222 .def_vals = {0x00000000, 0x3F3D70A4}
223 },
224 { .name = "Noise Reduction",
225 .nid = NOISE_REDUCTION,
226 .mid = 0x95,
227 .reqs = {4, 5},
228 .direct = EFX_DIR_IN,
229 .params = 1,
230 .def_vals = {0x3F800000, 0x3F000000}
231 },
232 { .name = "VoiceFX",
233 .nid = VOICEFX,
234 .mid = 0x95,
235 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
236 .direct = EFX_DIR_IN,
237 .params = 8,
238 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
239 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
240 0x00000000}
241 }
242};
243
244/* Tuning controls */
245#ifdef ENABLE_TUNING_CONTROLS
246
247enum {
248#define TUNING_CTL_START_NID 0xC0
249 WEDGE_ANGLE = TUNING_CTL_START_NID,
250 SVM_LEVEL,
251 EQUALIZER_BAND_0,
252 EQUALIZER_BAND_1,
253 EQUALIZER_BAND_2,
254 EQUALIZER_BAND_3,
255 EQUALIZER_BAND_4,
256 EQUALIZER_BAND_5,
257 EQUALIZER_BAND_6,
258 EQUALIZER_BAND_7,
259 EQUALIZER_BAND_8,
260 EQUALIZER_BAND_9,
261 TUNING_CTL_END_NID
262#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
263};
264
265struct ct_tuning_ctl {
266 char name[44];
267 hda_nid_t parent_nid;
268 hda_nid_t nid;
269 int mid; /*effect module ID*/
270 int req; /*effect module request*/
271 int direct; /* 0:output; 1:input*/
272 unsigned int def_val;/*effect default values*/
273};
274
275static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
276 { .name = "Wedge Angle",
277 .parent_nid = VOICE_FOCUS,
278 .nid = WEDGE_ANGLE,
279 .mid = 0x95,
280 .req = 8,
281 .direct = EFX_DIR_IN,
282 .def_val = 0x41F00000
283 },
284 { .name = "SVM Level",
285 .parent_nid = MIC_SVM,
286 .nid = SVM_LEVEL,
287 .mid = 0x95,
288 .req = 45,
289 .direct = EFX_DIR_IN,
290 .def_val = 0x3F3D70A4
291 },
292 { .name = "EQ Band0",
293 .parent_nid = EQUALIZER,
294 .nid = EQUALIZER_BAND_0,
295 .mid = 0x96,
296 .req = 11,
297 .direct = EFX_DIR_OUT,
298 .def_val = 0x00000000
299 },
300 { .name = "EQ Band1",
301 .parent_nid = EQUALIZER,
302 .nid = EQUALIZER_BAND_1,
303 .mid = 0x96,
304 .req = 12,
305 .direct = EFX_DIR_OUT,
306 .def_val = 0x00000000
307 },
308 { .name = "EQ Band2",
309 .parent_nid = EQUALIZER,
310 .nid = EQUALIZER_BAND_2,
311 .mid = 0x96,
312 .req = 13,
313 .direct = EFX_DIR_OUT,
314 .def_val = 0x00000000
315 },
316 { .name = "EQ Band3",
317 .parent_nid = EQUALIZER,
318 .nid = EQUALIZER_BAND_3,
319 .mid = 0x96,
320 .req = 14,
321 .direct = EFX_DIR_OUT,
322 .def_val = 0x00000000
323 },
324 { .name = "EQ Band4",
325 .parent_nid = EQUALIZER,
326 .nid = EQUALIZER_BAND_4,
327 .mid = 0x96,
328 .req = 15,
329 .direct = EFX_DIR_OUT,
330 .def_val = 0x00000000
331 },
332 { .name = "EQ Band5",
333 .parent_nid = EQUALIZER,
334 .nid = EQUALIZER_BAND_5,
335 .mid = 0x96,
336 .req = 16,
337 .direct = EFX_DIR_OUT,
338 .def_val = 0x00000000
339 },
340 { .name = "EQ Band6",
341 .parent_nid = EQUALIZER,
342 .nid = EQUALIZER_BAND_6,
343 .mid = 0x96,
344 .req = 17,
345 .direct = EFX_DIR_OUT,
346 .def_val = 0x00000000
347 },
348 { .name = "EQ Band7",
349 .parent_nid = EQUALIZER,
350 .nid = EQUALIZER_BAND_7,
351 .mid = 0x96,
352 .req = 18,
353 .direct = EFX_DIR_OUT,
354 .def_val = 0x00000000
355 },
356 { .name = "EQ Band8",
357 .parent_nid = EQUALIZER,
358 .nid = EQUALIZER_BAND_8,
359 .mid = 0x96,
360 .req = 19,
361 .direct = EFX_DIR_OUT,
362 .def_val = 0x00000000
363 },
364 { .name = "EQ Band9",
365 .parent_nid = EQUALIZER,
366 .nid = EQUALIZER_BAND_9,
367 .mid = 0x96,
368 .req = 20,
369 .direct = EFX_DIR_OUT,
370 .def_val = 0x00000000
371 }
372};
373#endif
374
375/* Voice FX Presets */
376#define VOICEFX_MAX_PARAM_COUNT 9
377
378struct ct_voicefx {
379 char *name;
380 hda_nid_t nid;
381 int mid;
382 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
383};
384
385struct ct_voicefx_preset {
386 char *name; /*preset name*/
387 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
388};
389
ccd7bd3d 390static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 391 .name = "VoiceFX Capture Switch",
392 .nid = VOICEFX,
393 .mid = 0x95,
394 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
395};
396
ccd7bd3d 397static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 398 { .name = "Neutral",
399 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
400 0x44FA0000, 0x3F800000, 0x3F800000,
401 0x3F800000, 0x00000000, 0x00000000 }
402 },
403 { .name = "Female2Male",
404 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
405 0x44FA0000, 0x3F19999A, 0x3F866666,
406 0x3F800000, 0x00000000, 0x00000000 }
407 },
408 { .name = "Male2Female",
409 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
410 0x450AC000, 0x4017AE14, 0x3F6B851F,
411 0x3F800000, 0x00000000, 0x00000000 }
412 },
413 { .name = "ScrappyKid",
414 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
415 0x44FA0000, 0x40400000, 0x3F28F5C3,
416 0x3F800000, 0x00000000, 0x00000000 }
417 },
418 { .name = "Elderly",
419 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
420 0x44E10000, 0x3FB33333, 0x3FB9999A,
421 0x3F800000, 0x3E3A2E43, 0x00000000 }
422 },
423 { .name = "Orc",
424 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
425 0x45098000, 0x3F266666, 0x3FC00000,
426 0x3F800000, 0x00000000, 0x00000000 }
427 },
428 { .name = "Elf",
429 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
430 0x45193000, 0x3F8E147B, 0x3F75C28F,
431 0x3F800000, 0x00000000, 0x00000000 }
432 },
433 { .name = "Dwarf",
434 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
435 0x45007000, 0x3F451EB8, 0x3F7851EC,
436 0x3F800000, 0x00000000, 0x00000000 }
437 },
438 { .name = "AlienBrute",
439 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
440 0x451F6000, 0x3F266666, 0x3FA7D945,
441 0x3F800000, 0x3CF5C28F, 0x00000000 }
442 },
443 { .name = "Robot",
444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
445 0x44FA0000, 0x3FB2718B, 0x3F800000,
446 0xBC07010E, 0x00000000, 0x00000000 }
447 },
448 { .name = "Marine",
449 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
450 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
451 0x3F0A3D71, 0x00000000, 0x00000000 }
452 },
453 { .name = "Emo",
454 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
455 0x44FA0000, 0x3F800000, 0x3F800000,
456 0x3E4CCCCD, 0x00000000, 0x00000000 }
457 },
458 { .name = "DeepVoice",
459 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
460 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
461 0x3F800000, 0x00000000, 0x00000000 }
462 },
463 { .name = "Munchkin",
464 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
465 0x44FA0000, 0x3F800000, 0x3F1A043C,
466 0x3F800000, 0x00000000, 0x00000000 }
467 }
468};
469
95c6e9cb
IM		 470enum hda_cmd_vendor_io {
471 /* for DspIO node */
472 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
473 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
474
475 VENDOR_DSPIO_STATUS = 0xF01,
476 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
477 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
478 VENDOR_DSPIO_DSP_INIT = 0x703,
479 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
480 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
481
482 /* for ChipIO node */
483 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
484 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
485 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
486 VENDOR_CHIPIO_DATA_LOW = 0x300,
487 VENDOR_CHIPIO_DATA_HIGH = 0x400,
488
489 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
490 VENDOR_CHIPIO_STATUS = 0xF01,
491 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
492 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
493
4aa3bb0c
IM		 494 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
495 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
496
95c6e9cb 497 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 498 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 499
500 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
501 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
502 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
503 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
504 VENDOR_CHIPIO_FLAG_SET = 0x70F,
505 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 506 VENDOR_CHIPIO_PARAM_SET = 0x710,
507 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 508
509 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
510 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
511 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
512 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
513
4aa3bb0c
IM		 514 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
515 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
516 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
517 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
518
519 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
520 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
521 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
522 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
523 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
524 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
525
526 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 527};
528
529/*
530 * Control flag IDs
531 */
532enum control_flag_id {
533 /* Connection manager stream setup is bypassed/enabled */
534 CONTROL_FLAG_C_MGR = 0,
535 /* DSP DMA is bypassed/enabled */
536 CONTROL_FLAG_DMA = 1,
537 /* 8051 'idle' mode is disabled/enabled */
538 CONTROL_FLAG_IDLE_ENABLE = 2,
539 /* Tracker for the SPDIF-in path is bypassed/enabled */
540 CONTROL_FLAG_TRACKER = 3,
541 /* DigitalOut to Spdif2Out connection is disabled/enabled */
542 CONTROL_FLAG_SPDIF2OUT = 4,
543 /* Digital Microphone is disabled/enabled */
544 CONTROL_FLAG_DMIC = 5,
545 /* ADC_B rate is 48 kHz/96 kHz */
546 CONTROL_FLAG_ADC_B_96KHZ = 6,
547 /* ADC_C rate is 48 kHz/96 kHz */
548 CONTROL_FLAG_ADC_C_96KHZ = 7,
549 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
550 CONTROL_FLAG_DAC_96KHZ = 8,
551 /* DSP rate is 48 kHz/96 kHz */
552 CONTROL_FLAG_DSP_96KHZ = 9,
553 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
554 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
555 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
556 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
557 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
558 CONTROL_FLAG_DECODE_LOOP = 12,
559 /* De-emphasis filter on DAC-1 disabled/enabled */
560 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
561 /* De-emphasis filter on DAC-2 disabled/enabled */
562 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
563 /* De-emphasis filter on DAC-3 disabled/enabled */
564 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
565 /* High-pass filter on ADC_B disabled/enabled */
566 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
567 /* High-pass filter on ADC_C disabled/enabled */
568 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
569 /* Common mode on Port_A disabled/enabled */
570 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
571 /* Common mode on Port_D disabled/enabled */
572 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
573 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
574 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
575 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 576 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 577 /* ASI rate is 48kHz/96kHz */
578 CONTROL_FLAG_ASI_96KHZ = 22,
579 /* DAC power settings able to control attached ports no/yes */
580 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
581 /* Clock Stop OK reporting is disabled/enabled */
582 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
583 /* Number of control flags */
584 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
585};
586
587/*
588 * Control parameter IDs
589 */
4aa3bb0c 590enum control_param_id {
ef6b2ead
IM		 591 /* 0: None, 1: Mic1In*/
592 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 593 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
594 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 595 /* Port A output stage gain setting to use when 16 Ohm output
596 * impedance is selected*/
597 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
598 /* Port D output stage gain setting to use when 16 Ohm output
599 * impedance is selected*/
600 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 601
602 /* Stream Control */
603
604 /* Select stream with the given ID */
605 CONTROL_PARAM_STREAM_ID = 24,
606 /* Source connection point for the selected stream */
607 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
608 /* Destination connection point for the selected stream */
609 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
610 /* Number of audio channels in the selected stream */
611 CONTROL_PARAM_STREAMS_CHANNELS = 27,
612 /*Enable control for the selected stream */
613 CONTROL_PARAM_STREAM_CONTROL = 28,
614
615 /* Connection Point Control */
616
617 /* Select connection point with the given ID */
618 CONTROL_PARAM_CONN_POINT_ID = 29,
619 /* Connection point sample rate */
620 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
621
622 /* Node Control */
623
624 /* Select HDA node with the given ID */
625 CONTROL_PARAM_NODE_ID = 31
626};
627
628/*
629 * Dsp Io Status codes
630 */
631enum hda_vendor_status_dspio {
632 /* Success */
633 VENDOR_STATUS_DSPIO_OK = 0x00,
634 /* Busy, unable to accept new command, the host must retry */
635 VENDOR_STATUS_DSPIO_BUSY = 0x01,
636 /* SCP command queue is full */
637 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
638 /* SCP response queue is empty */
639 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
640};
641
642/*
643 * Chip Io Status codes
644 */
645enum hda_vendor_status_chipio {
646 /* Success */
647 VENDOR_STATUS_CHIPIO_OK = 0x00,
648 /* Busy, unable to accept new command, the host must retry */
649 VENDOR_STATUS_CHIPIO_BUSY = 0x01
650};
651
652/*
653 * CA0132 sample rate
654 */
655enum ca0132_sample_rate {
656 SR_6_000 = 0x00,
657 SR_8_000 = 0x01,
658 SR_9_600 = 0x02,
659 SR_11_025 = 0x03,
660 SR_16_000 = 0x04,
661 SR_22_050 = 0x05,
662 SR_24_000 = 0x06,
663 SR_32_000 = 0x07,
664 SR_44_100 = 0x08,
665 SR_48_000 = 0x09,
666 SR_88_200 = 0x0A,
667 SR_96_000 = 0x0B,
668 SR_144_000 = 0x0C,
669 SR_176_400 = 0x0D,
670 SR_192_000 = 0x0E,
671 SR_384_000 = 0x0F,
672
673 SR_COUNT = 0x10,
674
675 SR_RATE_UNKNOWN = 0x1F
676};
677
01ef7dbf
IM		 678enum dsp_download_state {
679 DSP_DOWNLOAD_FAILED = -1,
680 DSP_DOWNLOAD_INIT = 0,
681 DSP_DOWNLOADING = 1,
682 DSP_DOWNLOADED = 2
683};
684
01ef7dbf
IM		 685/* retrieve parameters from hda format */
686#define get_hdafmt_chs(fmt) (fmt & 0xf)
687#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
688#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
689#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
690
691/*
692 * CA0132 specific
693 */
694
695struct ca0132_spec {
a7e76271
IM		 696 struct snd_kcontrol_new *mixers[5];
697 unsigned int num_mixers;
5aaca44d
IM		 698 const struct hda_verb *base_init_verbs;
699 const struct hda_verb *base_exit_verbs;
700 const struct hda_verb *init_verbs[5];
701 unsigned int num_init_verbs; /* exclude base init verbs */
01ef7dbf 702 struct auto_pin_cfg autocfg;
5aaca44d
IM		 703
704 /* Nodes configurations */
01ef7dbf
IM		 705 struct hda_multi_out multiout;
706 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
707 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 708 unsigned int num_outputs;
01ef7dbf
IM		 709 hda_nid_t input_pins[AUTO_PIN_LAST];
710 hda_nid_t adcs[AUTO_PIN_LAST];
711 hda_nid_t dig_out;
712 hda_nid_t dig_in;
713 unsigned int num_inputs;
a7e76271
IM		 714 hda_nid_t shared_mic_nid;
715 hda_nid_t shared_out_nid;
5aaca44d 716 struct hda_pcm pcm_rec[5]; /* PCM information */
01ef7dbf
IM		 717
718 /* chip access */
719 struct mutex chipio_mutex; /* chip access mutex */
720 u32 curr_chip_addx;
721
722 /* DSP download related */
723 enum dsp_download_state dsp_state;
724 unsigned int dsp_stream_id;
725 unsigned int wait_scp;
726 unsigned int wait_scp_header;
727 unsigned int wait_num_data;
728 unsigned int scp_resp_header;
729 unsigned int scp_resp_data[4];
730 unsigned int scp_resp_count;
5aaca44d
IM		 731
732 /* mixer and effects related */
733 unsigned char dmic_ctl;
734 int cur_out_type;
735 int cur_mic_type;
736 long vnode_lvol[VNODES_COUNT];
737 long vnode_rvol[VNODES_COUNT];
738 long vnode_lswitch[VNODES_COUNT];
739 long vnode_rswitch[VNODES_COUNT];
740 long effects_switch[EFFECTS_COUNT];
741 long voicefx_val;
742 long cur_mic_boost;
44f0c978 743
993884f6
CCC		 744 struct hda_codec *codec;
745 struct delayed_work unsol_hp_work;
746
44f0c978
IM		 747#ifdef ENABLE_TUNING_CONTROLS
748 long cur_ctl_vals[TUNING_CTLS_COUNT];
749#endif
01ef7dbf
IM		 750};
751
752/*
753 * CA0132 codec access
754 */
755unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
756 unsigned int verb, unsigned int parm, unsigned int *res)
757{
758 unsigned int response;
759 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
760 *res = response;
761
762 return ((response == -1) ? -1 : 0);
763}
764
765static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
766 unsigned short converter_format, unsigned int *res)
767{
768 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
769 converter_format & 0xffff, res);
770}
771
772static int codec_set_converter_stream_channel(struct hda_codec *codec,
773 hda_nid_t nid, unsigned char stream,
774 unsigned char channel, unsigned int *res)
775{
776 unsigned char converter_stream_channel = 0;
777
778 converter_stream_channel = (stream << 4) | (channel & 0x0f);
779 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
780 converter_stream_channel, res);
781}
782
783/* Chip access helper function */
784static int chipio_send(struct hda_codec *codec,
785 unsigned int reg,
786 unsigned int data)
787{
788 unsigned int res;
6d67530e 789 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 790
791 /* send bits of data specified by reg */
792 do {
793 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
794 reg, data);
795 if (res == VENDOR_STATUS_CHIPIO_OK)
796 return 0;
6d67530e
IM		 797 msleep(20);
798 } while (time_before(jiffies, timeout));
799
01ef7dbf
IM		 800 return -EIO;
801}
802
803/*
804 * Write chip address through the vendor widget -- NOT protected by the Mutex!
805 */
806static int chipio_write_address(struct hda_codec *codec,
807 unsigned int chip_addx)
808{
4861af80 809 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 810 int res;
811
4861af80
IM		 812 if (spec->curr_chip_addx == chip_addx)
813 return 0;
814
01ef7dbf
IM		 815 /* send low 16 bits of the address */
816 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
817 chip_addx & 0xffff);
818
819 if (res != -EIO) {
820 /* send high 16 bits of the address */
821 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
822 chip_addx >> 16);
823 }
824
4861af80 825 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
01ef7dbf 826
4861af80 827 return res;
01ef7dbf
IM		 828}
829
830/*
831 * Write data through the vendor widget -- NOT protected by the Mutex!
832 */
01ef7dbf
IM		 833static int chipio_write_data(struct hda_codec *codec, unsigned int data)
834{
5aaca44d 835 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 836 int res;
837
838 /* send low 16 bits of the data */
839 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
840
841 if (res != -EIO) {
842 /* send high 16 bits of the data */
843 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
844 data >> 16);
845 }
846
5aaca44d
IM		 847 /*If no error encountered, automatically increment the address
848 as per chip behaviour*/
849 spec->curr_chip_addx = (res != -EIO) ?
850 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 851 return res;
852}
853
d5c21b88
IM		 854/*
855 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
856 */
01ef7dbf
IM		 857static int chipio_write_data_multiple(struct hda_codec *codec,
858 const u32 *data,
859 unsigned int count)
860{
861 int status = 0;
862
863 if (data == NULL) {
9958922a 864 snd_printdd(KERN_ERR "chipio_write_data null ptr\n");
01ef7dbf
IM		 865 return -EINVAL;
866 }
867
868 while ((count-- != 0) && (status == 0))
869 status = chipio_write_data(codec, *data++);
870
871 return status;
872}
873
874
875/*
876 * Read data through the vendor widget -- NOT protected by the Mutex!
877 */
878static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
879{
5aaca44d 880 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 881 int res;
882
883 /* post read */
884 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
885
886 if (res != -EIO) {
887 /* read status */
888 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
889 }
890
891 if (res != -EIO) {
892 /* read data */
893 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
894 VENDOR_CHIPIO_HIC_READ_DATA,
895 0);
896 }
897
5aaca44d
IM		 898 /*If no error encountered, automatically increment the address
899 as per chip behaviour*/
900 spec->curr_chip_addx = (res != -EIO) ?
901 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 902 return res;
903}
904
905/*
906 * Write given value to the given address through the chip I/O widget.
907 * protected by the Mutex
908 */
909static int chipio_write(struct hda_codec *codec,
910 unsigned int chip_addx, const unsigned int data)
911{
912 struct ca0132_spec *spec = codec->spec;
913 int err;
914
915 mutex_lock(&spec->chipio_mutex);
916
917 /* write the address, and if successful proceed to write data */
918 err = chipio_write_address(codec, chip_addx);
919 if (err < 0)
920 goto exit;
921
922 err = chipio_write_data(codec, data);
923 if (err < 0)
924 goto exit;
925
926exit:
927 mutex_unlock(&spec->chipio_mutex);
928 return err;
929}
930
d5c21b88
IM		 931/*
932 * Write multiple values to the given address through the chip I/O widget.
933 * protected by the Mutex
934 */
01ef7dbf
IM		 935static int chipio_write_multiple(struct hda_codec *codec,
936 u32 chip_addx,
937 const u32 *data,
938 unsigned int count)
939{
940 struct ca0132_spec *spec = codec->spec;
941 int status;
942
943 mutex_lock(&spec->chipio_mutex);
4861af80 944 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 945 if (status < 0)
946 goto error;
947
948 status = chipio_write_data_multiple(codec, data, count);
949error:
950 mutex_unlock(&spec->chipio_mutex);
951
952 return status;
953}
954
955/*
956 * Read the given address through the chip I/O widget
957 * protected by the Mutex
958 */
959static int chipio_read(struct hda_codec *codec,
960 unsigned int chip_addx, unsigned int *data)
961{
962 struct ca0132_spec *spec = codec->spec;
963 int err;
964
965 mutex_lock(&spec->chipio_mutex);
966
967 /* write the address, and if successful proceed to write data */
968 err = chipio_write_address(codec, chip_addx);
969 if (err < 0)
970 goto exit;
971
972 err = chipio_read_data(codec, data);
973 if (err < 0)
974 goto exit;
975
976exit:
977 mutex_unlock(&spec->chipio_mutex);
978 return err;
979}
980
d5c21b88
IM		 981/*
982 * Set chip control flags through the chip I/O widget.
983 */
01ef7dbf
IM		 984static void chipio_set_control_flag(struct hda_codec *codec,
985 enum control_flag_id flag_id,
986 bool flag_state)
987{
988 unsigned int val;
989 unsigned int flag_bit;
990
991 flag_bit = (flag_state ? 1 : 0);
992 val = (flag_bit << 7) | (flag_id);
993 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
994 VENDOR_CHIPIO_FLAG_SET, val);
995}
996
d5c21b88
IM		 997/*
998 * Set chip parameters through the chip I/O widget.
999 */
01ef7dbf
IM		 1000static void chipio_set_control_param(struct hda_codec *codec,
1001 enum control_param_id param_id, int param_val)
1002{
1003 struct ca0132_spec *spec = codec->spec;
1004 int val;
1005
1006 if ((param_id < 32) && (param_val < 8)) {
1007 val = (param_val << 5) | (param_id);
1008 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1009 VENDOR_CHIPIO_PARAM_SET, val);
1010 } else {
1011 mutex_lock(&spec->chipio_mutex);
1012 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1013 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1014 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1015 param_id);
1016 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1017 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1018 param_val);
1019 }
1020 mutex_unlock(&spec->chipio_mutex);
1021 }
1022}
1023
d5c21b88
IM		 1024/*
1025 * Set sampling rate of the connection point.
1026 */
01ef7dbf
IM		 1027static void chipio_set_conn_rate(struct hda_codec *codec,
1028 int connid, enum ca0132_sample_rate rate)
1029{
1030 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1031 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1032 rate);
1033}
1034
d5c21b88
IM		 1035/*
1036 * Enable clocks.
1037 */
01ef7dbf
IM		 1038static void chipio_enable_clocks(struct hda_codec *codec)
1039{
1040 struct ca0132_spec *spec = codec->spec;
1041
1042 mutex_lock(&spec->chipio_mutex);
1043 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1044 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1045 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1046 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1047 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1048 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1050 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1051 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1052 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1053 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1054 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1055 mutex_unlock(&spec->chipio_mutex);
1056}
1057
1058/*
1059 * CA0132 DSP IO stuffs
1060 */
1061static int dspio_send(struct hda_codec *codec, unsigned int reg,
1062 unsigned int data)
1063{
b645d796 1064 int res;
6d67530e 1065 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1066
1067 /* send bits of data specified by reg to dsp */
1068 do {
1069 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1070 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1071 return res;
6d67530e
IM		 1072 msleep(20);
1073 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1074
1075 return -EIO;
1076}
1077
d5c21b88
IM		 1078/*
1079 * Wait for DSP to be ready for commands
1080 */
01ef7dbf
IM		 1081static void dspio_write_wait(struct hda_codec *codec)
1082{
4861af80
IM		 1083 int status;
1084 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1085
01ef7dbf 1086 do {
4861af80
IM		 1087 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1088 VENDOR_DSPIO_STATUS, 0);
1089 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1090 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1091 break;
1092 msleep(1);
1093 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1094}
1095
d5c21b88
IM		 1096/*
1097 * Write SCP data to DSP
1098 */
01ef7dbf
IM		 1099static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1100{
1101 struct ca0132_spec *spec = codec->spec;
1102 int status;
1103
1104 dspio_write_wait(codec);
1105
1106 mutex_lock(&spec->chipio_mutex);
1107 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1108 scp_data & 0xffff);
1109 if (status < 0)
1110 goto error;
1111
1112 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1113 scp_data >> 16);
1114 if (status < 0)
1115 goto error;
1116
1117 /* OK, now check if the write itself has executed*/
1118 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1119 VENDOR_DSPIO_STATUS, 0);
1120error:
1121 mutex_unlock(&spec->chipio_mutex);
1122
1123 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1124 -EIO : 0;
1125}
1126
d5c21b88
IM		 1127/*
1128 * Write multiple SCP data to DSP
1129 */
01ef7dbf
IM		 1130static int dspio_write_multiple(struct hda_codec *codec,
1131 unsigned int *buffer, unsigned int size)
1132{
1133 int status = 0;
1134 unsigned int count;
1135
1136 if ((buffer == NULL))
1137 return -EINVAL;
1138
1139 count = 0;
1140 while (count < size) {
1141 status = dspio_write(codec, *buffer++);
1142 if (status != 0)
1143 break;
1144 count++;
1145 }
1146
1147 return status;
1148}
1149
a73d511c
IM		 1150static int dspio_read(struct hda_codec *codec, unsigned int *data)
1151{
1152 int status;
1153
1154 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1155 if (status == -EIO)
1156 return status;
1157
1158 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1159 if (status == -EIO ||
1160 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1161 return -EIO;
1162
1163 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1164 VENDOR_DSPIO_SCP_READ_DATA, 0);
1165
1166 return 0;
1167}
1168
1169static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1170 unsigned int *buf_size, unsigned int size_count)
1171{
1172 int status = 0;
1173 unsigned int size = *buf_size;
1174 unsigned int count;
1175 unsigned int skip_count;
1176 unsigned int dummy;
1177
1178 if ((buffer == NULL))
1179 return -1;
1180
1181 count = 0;
1182 while (count < size && count < size_count) {
1183 status = dspio_read(codec, buffer++);
1184 if (status != 0)
1185 break;
1186 count++;
1187 }
1188
1189 skip_count = count;
1190 if (status == 0) {
1191 while (skip_count < size) {
1192 status = dspio_read(codec, &dummy);
1193 if (status != 0)
1194 break;
1195 skip_count++;
1196 }
1197 }
1198 *buf_size = count;
1199
1200 return status;
1201}
1202
d5c21b88
IM		 1203/*
1204 * Construct the SCP header using corresponding fields
1205 */
01ef7dbf
IM		 1206static inline unsigned int
1207make_scp_header(unsigned int target_id, unsigned int source_id,
1208 unsigned int get_flag, unsigned int req,
1209 unsigned int device_flag, unsigned int resp_flag,
1210 unsigned int error_flag, unsigned int data_size)
1211{
1212 unsigned int header = 0;
1213
1214 header = (data_size & 0x1f) << 27;
1215 header |= (error_flag & 0x01) << 26;
1216 header |= (resp_flag & 0x01) << 25;
1217 header |= (device_flag & 0x01) << 24;
1218 header |= (req & 0x7f) << 17;
1219 header |= (get_flag & 0x01) << 16;
1220 header |= (source_id & 0xff) << 8;
1221 header |= target_id & 0xff;
1222
1223 return header;
1224}
1225
d5c21b88
IM		 1226/*
1227 * Extract corresponding fields from SCP header
1228 */
01ef7dbf
IM		 1229static inline void
1230extract_scp_header(unsigned int header,
1231 unsigned int *target_id, unsigned int *source_id,
1232 unsigned int *get_flag, unsigned int *req,
1233 unsigned int *device_flag, unsigned int *resp_flag,
1234 unsigned int *error_flag, unsigned int *data_size)
1235{
1236 if (data_size)
1237 *data_size = (header >> 27) & 0x1f;
1238 if (error_flag)
1239 *error_flag = (header >> 26) & 0x01;
1240 if (resp_flag)
1241 *resp_flag = (header >> 25) & 0x01;
1242 if (device_flag)
1243 *device_flag = (header >> 24) & 0x01;
1244 if (req)
1245 *req = (header >> 17) & 0x7f;
1246 if (get_flag)
1247 *get_flag = (header >> 16) & 0x01;
1248 if (source_id)
1249 *source_id = (header >> 8) & 0xff;
1250 if (target_id)
1251 *target_id = header & 0xff;
1252}
1253
1254#define SCP_MAX_DATA_WORDS (16)
1255
1256/* Structure to contain any SCP message */
1257struct scp_msg {
1258 unsigned int hdr;
1259 unsigned int data[SCP_MAX_DATA_WORDS];
1260};
1261
a73d511c
IM		 1262static void dspio_clear_response_queue(struct hda_codec *codec)
1263{
1264 unsigned int dummy = 0;
1265 int status = -1;
1266
1267 /* clear all from the response queue */
1268 do {
1269 status = dspio_read(codec, &dummy);
1270 } while (status == 0);
1271}
1272
1273static int dspio_get_response_data(struct hda_codec *codec)
1274{
1275 struct ca0132_spec *spec = codec->spec;
1276 unsigned int data = 0;
1277 unsigned int count;
1278
1279 if (dspio_read(codec, &data) < 0)
1280 return -EIO;
1281
1282 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1283 spec->scp_resp_header = data;
1284 spec->scp_resp_count = data >> 27;
1285 count = spec->wait_num_data;
1286 dspio_read_multiple(codec, spec->scp_resp_data,
1287 &spec->scp_resp_count, count);
1288 return 0;
1289 }
1290
1291 return -EIO;
1292}
1293
d5c21b88
IM		 1294/*
1295 * Send SCP message to DSP
1296 */
01ef7dbf
IM		 1297static int dspio_send_scp_message(struct hda_codec *codec,
1298 unsigned char *send_buf,
1299 unsigned int send_buf_size,
1300 unsigned char *return_buf,
1301 unsigned int return_buf_size,
1302 unsigned int *bytes_returned)
1303{
1304 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1305 int status = -1;
1306 unsigned int scp_send_size = 0;
1307 unsigned int total_size;
1308 bool waiting_for_resp = false;
1309 unsigned int header;
1310 struct scp_msg *ret_msg;
1311 unsigned int resp_src_id, resp_target_id;
1312 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1313
1314 if (bytes_returned)
1315 *bytes_returned = 0;
1316
1317 /* get scp header from buffer */
1318 header = *((unsigned int *)send_buf);
1319 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1320 &device_flag, NULL, NULL, &data_size);
1321 scp_send_size = data_size + 1;
1322 total_size = (scp_send_size * 4);
1323
1324 if (send_buf_size < total_size)
1325 return -EINVAL;
1326
1327 if (get_flag || device_flag) {
1328 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1329 return -EINVAL;
1330
1331 spec->wait_scp_header = *((unsigned int *)send_buf);
1332
1333 /* swap source id with target id */
1334 resp_target_id = src_id;
1335 resp_src_id = target_id;
1336 spec->wait_scp_header &= 0xffff0000;
1337 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1338 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1339 spec->wait_scp = 1;
1340 waiting_for_resp = true;
1341 }
1342
1343 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1344 scp_send_size);
1345 if (status < 0) {
1346 spec->wait_scp = 0;
1347 return status;
1348 }
1349
1350 if (waiting_for_resp) {
6d67530e 1351 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1352 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1353 do {
1354 msleep(20);
6d67530e 1355 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1356 waiting_for_resp = false;
6d67530e 1357 if (!spec->wait_scp) {
01ef7dbf
IM		 1358 ret_msg = (struct scp_msg *)return_buf;
1359 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1360 memcpy(&ret_msg->data, spec->scp_resp_data,
1361 spec->wait_num_data);
1362 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1363 status = 0;
1364 } else {
1365 status = -EIO;
1366 }
1367 spec->wait_scp = 0;
1368 }
1369
1370 return status;
1371}
1372
d5c21b88
IM		 1373/**
1374 * Prepare and send the SCP message to DSP
1375 * @codec: the HDA codec
1376 * @mod_id: ID of the DSP module to send the command
1377 * @req: ID of request to send to the DSP module
1378 * @dir: SET or GET
1379 * @data: pointer to the data to send with the request, request specific
1380 * @len: length of the data, in bytes
1381 * @reply: point to the buffer to hold data returned for a reply
1382 * @reply_len: length of the reply buffer returned from GET
1383 *
1384 * Returns zero or a negative error code.
1385 */
01ef7dbf
IM		 1386static int dspio_scp(struct hda_codec *codec,
1387 int mod_id, int req, int dir, void *data, unsigned int len,
1388 void *reply, unsigned int *reply_len)
1389{
1390 int status = 0;
1391 struct scp_msg scp_send, scp_reply;
1392 unsigned int ret_bytes, send_size, ret_size;
1393 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1394 unsigned int reply_data_size;
1395
1396 memset(&scp_send, 0, sizeof(scp_send));
1397 memset(&scp_reply, 0, sizeof(scp_reply));
1398
1399 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1400 return -EINVAL;
1401
1402 if (dir == SCP_GET && reply == NULL) {
9958922a 1403 snd_printdd(KERN_ERR "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1404 return -EINVAL;
1405 }
1406
1407 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
9958922a 1408 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1409 return -EINVAL;
1410 }
1411
1412 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1413 0, 0, 0, len/sizeof(unsigned int));
1414 if (data != NULL && len > 0) {
1415 len = min((unsigned int)(sizeof(scp_send.data)), len);
1416 memcpy(scp_send.data, data, len);
1417 }
1418
1419 ret_bytes = 0;
1420 send_size = sizeof(unsigned int) + len;
1421 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1422 send_size, (unsigned char *)&scp_reply,
1423 sizeof(scp_reply), &ret_bytes);
1424
1425 if (status < 0) {
9958922a 1426 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1427 return status;
1428 }
1429
1430 /* extract send and reply headers members */
1431 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1432 NULL, NULL, NULL, NULL, NULL);
1433 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1434 &reply_resp_flag, &reply_error_flag,
1435 &reply_data_size);
1436
1437 if (!send_get_flag)
1438 return 0;
1439
1440 if (reply_resp_flag && !reply_error_flag) {
1441 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1442 / sizeof(unsigned int);
1443
1444 if (*reply_len < ret_size*sizeof(unsigned int)) {
9958922a 1445 snd_printdd(KERN_ERR "reply too long for buf\n");
01ef7dbf
IM		 1446 return -EINVAL;
1447 } else if (ret_size != reply_data_size) {
9958922a 1448 snd_printdd(KERN_ERR "RetLen and HdrLen .NE.\n");
01ef7dbf
IM		 1449 return -EINVAL;
1450 } else {
1451 *reply_len = ret_size*sizeof(unsigned int);
1452 memcpy(reply, scp_reply.data, *reply_len);
1453 }
1454 } else {
9958922a 1455 snd_printdd(KERN_ERR "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1456 return -EIO;
1457 }
1458
1459 return status;
1460}
1461
5aaca44d
IM		 1462/*
1463 * Set DSP parameters
1464 */
1465static int dspio_set_param(struct hda_codec *codec, int mod_id,
1466 int req, void *data, unsigned int len)
1467{
1468 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1469}
1470
1471static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1472 int req, unsigned int data)
1473{
1474 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1475}
1476
d5c21b88
IM		 1477/*
1478 * Allocate a DSP DMA channel via an SCP message
1479 */
01ef7dbf
IM		 1480static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1481{
1482 int status = 0;
1483 unsigned int size = sizeof(dma_chan);
1484
9958922a 1485 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin\n");
01ef7dbf
IM		 1486 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1487 SCP_GET, NULL, 0, dma_chan, &size);
1488
1489 if (status < 0) {
9958922a 1490 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1491 return status;
1492 }
1493
1494 if ((*dma_chan + 1) == 0) {
9958922a 1495 snd_printdd(KERN_INFO "no free dma channels to allocate\n");
01ef7dbf
IM		 1496 return -EBUSY;
1497 }
1498
1499 snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
9958922a 1500 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1501
1502 return status;
1503}
1504
d5c21b88
IM		 1505/*
1506 * Free a DSP DMA via an SCP message
1507 */
01ef7dbf
IM		 1508static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1509{
1510 int status = 0;
1511 unsigned int dummy = 0;
1512
9958922a 1513 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin\n");
01ef7dbf
IM		 1514 snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan);
1515
1516 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1517 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1518
1519 if (status < 0) {
9958922a 1520 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1521 return status;
1522 }
1523
9958922a 1524 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1525
1526 return status;
1527}
1528
1529/*
d5c21b88 1530 * (Re)start the DSP
01ef7dbf
IM		 1531 */
1532static int dsp_set_run_state(struct hda_codec *codec)
1533{
1534 unsigned int dbg_ctrl_reg;
1535 unsigned int halt_state;
1536 int err;
1537
1538 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1539 if (err < 0)
1540 return err;
1541
1542 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1543 DSP_DBGCNTL_STATE_LOBIT;
1544
1545 if (halt_state != 0) {
1546 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1547 DSP_DBGCNTL_SS_MASK);
1548 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1549 dbg_ctrl_reg);
1550 if (err < 0)
1551 return err;
1552
1553 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1554 DSP_DBGCNTL_EXEC_MASK;
1555 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1556 dbg_ctrl_reg);
1557 if (err < 0)
1558 return err;
1559 }
1560
1561 return 0;
1562}
1563
d5c21b88
IM		 1564/*
1565 * Reset the DSP
1566 */
01ef7dbf
IM		 1567static int dsp_reset(struct hda_codec *codec)
1568{
1569 unsigned int res;
1570 int retry = 20;
1571
1572 snd_printdd("dsp_reset\n");
1573 do {
1574 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1575 retry--;
1576 } while (res == -EIO && retry);
1577
1578 if (!retry) {
1579 snd_printdd("dsp_reset timeout\n");
1580 return -EIO;
1581 }
1582
1583 return 0;
1584}
1585
d5c21b88
IM		 1586/*
1587 * Convert chip address to DSP address
1588 */
01ef7dbf
IM		 1589static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1590 bool *code, bool *yram)
1591{
1592 *code = *yram = false;
1593
1594 if (UC_RANGE(chip_addx, 1)) {
1595 *code = true;
1596 return UC_OFF(chip_addx);
1597 } else if (X_RANGE_ALL(chip_addx, 1)) {
1598 return X_OFF(chip_addx);
1599 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1600 *yram = true;
1601 return Y_OFF(chip_addx);
1602 }
1603
4a8b89f9 1604 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 1605}
1606
d5c21b88
IM		 1607/*
1608 * Check if the DSP DMA is active
1609 */
01ef7dbf
IM		 1610static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1611{
1612 unsigned int dma_chnlstart_reg;
1613
1614 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1615
1616 return ((dma_chnlstart_reg & (1 <<
1617 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1618}
1619
1620static int dsp_dma_setup_common(struct hda_codec *codec,
1621 unsigned int chip_addx,
1622 unsigned int dma_chan,
1623 unsigned int port_map_mask,
1624 bool ovly)
1625{
1626 int status = 0;
1627 unsigned int chnl_prop;
1628 unsigned int dsp_addx;
1629 unsigned int active;
1630 bool code, yram;
1631
9958922a 1632 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 1633
1634 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
9958922a 1635 snd_printdd(KERN_ERR "dma chan num invalid\n");
01ef7dbf
IM		 1636 return -EINVAL;
1637 }
1638
1639 if (dsp_is_dma_active(codec, dma_chan)) {
9958922a 1640 snd_printdd(KERN_ERR "dma already active\n");
01ef7dbf
IM		 1641 return -EBUSY;
1642 }
1643
1644 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1645
1646 if (dsp_addx == INVALID_CHIP_ADDRESS) {
9958922a 1647 snd_printdd(KERN_ERR "invalid chip addr\n");
01ef7dbf
IM		 1648 return -ENXIO;
1649 }
1650
1651 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1652 active = 0;
1653
9958922a 1654 snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 1655
1656 if (ovly) {
1657 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1658 &chnl_prop);
1659
1660 if (status < 0) {
9958922a 1661 snd_printdd(KERN_ERR "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 1662 return status;
1663 }
9958922a 1664 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 1665 }
1666
1667 if (!code)
1668 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1669 else
1670 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1671
1672 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1673
1674 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1675 if (status < 0) {
9958922a 1676 snd_printdd(KERN_ERR "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 1677 return status;
1678 }
9958922a 1679 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 1680
1681 if (ovly) {
1682 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1683 &active);
1684
1685 if (status < 0) {
9958922a 1686 snd_printdd(KERN_ERR "read ACTIVE Reg fail\n");
01ef7dbf
IM		 1687 return status;
1688 }
9958922a 1689 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 1690 }
1691
1692 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1693 DSPDMAC_ACTIVE_AAR_MASK;
1694
1695 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1696 if (status < 0) {
9958922a 1697 snd_printdd(KERN_ERR "write ACTIVE Reg fail\n");
01ef7dbf
IM		 1698 return status;
1699 }
1700
9958922a 1701 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 1702
1703 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1704 port_map_mask);
1705 if (status < 0) {
9958922a 1706 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 1707 return status;
1708 }
9958922a 1709 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 1710
1711 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1712 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1713 if (status < 0) {
9958922a 1714 snd_printdd(KERN_ERR "write IRQCNT Reg fail\n");
01ef7dbf
IM		 1715 return status;
1716 }
9958922a 1717 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf
IM		 1718
1719 snd_printdd(
1720 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1721 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1722 chip_addx, dsp_addx, dma_chan,
1723 port_map_mask, chnl_prop, active);
1724
9958922a 1725 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 1726
1727 return 0;
1728}
1729
d5c21b88
IM		 1730/*
1731 * Setup the DSP DMA per-transfer-specific registers
1732 */
01ef7dbf
IM		 1733static int dsp_dma_setup(struct hda_codec *codec,
1734 unsigned int chip_addx,
1735 unsigned int count,
1736 unsigned int dma_chan)
1737{
1738 int status = 0;
1739 bool code, yram;
1740 unsigned int dsp_addx;
1741 unsigned int addr_field;
1742 unsigned int incr_field;
1743 unsigned int base_cnt;
1744 unsigned int cur_cnt;
1745 unsigned int dma_cfg = 0;
1746 unsigned int adr_ofs = 0;
1747 unsigned int xfr_cnt = 0;
1748 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1749 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1750
9958922a 1751 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 1752
1753 if (count > max_dma_count) {
9958922a 1754 snd_printdd(KERN_ERR "count too big\n");
01ef7dbf
IM		 1755 return -EINVAL;
1756 }
1757
1758 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1759 if (dsp_addx == INVALID_CHIP_ADDRESS) {
9958922a 1760 snd_printdd(KERN_ERR "invalid chip addr\n");
01ef7dbf
IM		 1761 return -ENXIO;
1762 }
1763
9958922a 1764 snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 1765
1766 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1767 incr_field = 0;
1768
1769 if (!code) {
1770 addr_field <<= 1;
1771 if (yram)
1772 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1773
1774 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1775 }
1776
1777 dma_cfg = addr_field + incr_field;
1778 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1779 dma_cfg);
1780 if (status < 0) {
9958922a 1781 snd_printdd(KERN_ERR "write DMACFG Reg fail\n");
01ef7dbf
IM		 1782 return status;
1783 }
9958922a 1784 snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 1785
1786 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1787 (code ? 0 : 1));
1788
1789 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1790 adr_ofs);
1791 if (status < 0) {
9958922a 1792 snd_printdd(KERN_ERR "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 1793 return status;
1794 }
9958922a 1795 snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 1796
1797 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1798
1799 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1800
1801 xfr_cnt = base_cnt | cur_cnt;
1802
1803 status = chipio_write(codec,
1804 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1805 if (status < 0) {
9958922a 1806 snd_printdd(KERN_ERR "write XFRCNT Reg fail\n");
01ef7dbf
IM		 1807 return status;
1808 }
9958922a 1809 snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf
IM		 1810
1811 snd_printdd(
1812 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1813 "ADROFS=0x%x, XFRCNT=0x%x\n",
1814 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1815
9958922a 1816 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 1817
1818 return 0;
1819}
1820
d5c21b88
IM		 1821/*
1822 * Start the DSP DMA
1823 */
01ef7dbf
IM		 1824static int dsp_dma_start(struct hda_codec *codec,
1825 unsigned int dma_chan, bool ovly)
1826{
1827 unsigned int reg = 0;
1828 int status = 0;
1829
9958922a 1830 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 1831
1832 if (ovly) {
1833 status = chipio_read(codec,
1834 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1835
1836 if (status < 0) {
9958922a 1837 snd_printdd(KERN_ERR "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1838 return status;
1839 }
9958922a 1840 snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 1841
1842 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1843 DSPDMAC_CHNLSTART_DIS_MASK);
1844 }
1845
1846 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1847 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1848 if (status < 0) {
9958922a 1849 snd_printdd(KERN_ERR "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1850 return status;
1851 }
9958922a 1852 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 1853
1854 return status;
1855}
1856
d5c21b88
IM		 1857/*
1858 * Stop the DSP DMA
1859 */
01ef7dbf
IM		 1860static int dsp_dma_stop(struct hda_codec *codec,
1861 unsigned int dma_chan, bool ovly)
1862{
1863 unsigned int reg = 0;
1864 int status = 0;
1865
9958922a 1866 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 1867
1868 if (ovly) {
1869 status = chipio_read(codec,
1870 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1871
1872 if (status < 0) {
9958922a 1873 snd_printdd(KERN_ERR "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1874 return status;
1875 }
9958922a 1876 snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 1877 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1878 DSPDMAC_CHNLSTART_DIS_MASK);
1879 }
1880
1881 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1882 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1883 if (status < 0) {
9958922a 1884 snd_printdd(KERN_ERR "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1885 return status;
1886 }
9958922a 1887 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 1888
1889 return status;
1890}
1891
d5c21b88
IM		 1892/**
1893 * Allocate router ports
1894 *
1895 * @codec: the HDA codec
1896 * @num_chans: number of channels in the stream
1897 * @ports_per_channel: number of ports per channel
1898 * @start_device: start device
1899 * @port_map: pointer to the port list to hold the allocated ports
1900 *
1901 * Returns zero or a negative error code.
1902 */
01ef7dbf
IM		 1903static int dsp_allocate_router_ports(struct hda_codec *codec,
1904 unsigned int num_chans,
1905 unsigned int ports_per_channel,
1906 unsigned int start_device,
1907 unsigned int *port_map)
1908{
1909 int status = 0;
1910 int res;
1911 u8 val;
1912
1913 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1914 if (status < 0)
1915 return status;
1916
1917 val = start_device << 6;
1918 val |= (ports_per_channel - 1) << 4;
1919 val |= num_chans - 1;
1920
1921 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1922 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1923 val);
1924
1925 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1926 VENDOR_CHIPIO_PORT_ALLOC_SET,
1927 MEM_CONNID_DSP);
1928
1929 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1930 if (status < 0)
1931 return status;
1932
1933 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1934 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1935
1936 *port_map = res;
1937
1938 return (res < 0) ? res : 0;
1939}
1940
d5c21b88
IM		 1941/*
1942 * Free router ports
1943 */
01ef7dbf
IM		 1944static int dsp_free_router_ports(struct hda_codec *codec)
1945{
1946 int status = 0;
1947
1948 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1949 if (status < 0)
1950 return status;
1951
1952 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1953 VENDOR_CHIPIO_PORT_FREE_SET,
1954 MEM_CONNID_DSP);
1955
1956 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1957
1958 return status;
1959}
1960
d5c21b88
IM		 1961/*
1962 * Allocate DSP ports for the download stream
1963 */
01ef7dbf
IM		 1964static int dsp_allocate_ports(struct hda_codec *codec,
1965 unsigned int num_chans,
1966 unsigned int rate_multi, unsigned int *port_map)
1967{
1968 int status;
1969
9958922a 1970 snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 1971
1972 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
9958922a 1973 snd_printdd(KERN_ERR "bad rate multiple\n");
01ef7dbf
IM		 1974 return -EINVAL;
1975 }
1976
1977 status = dsp_allocate_router_ports(codec, num_chans,
1978 rate_multi, 0, port_map);
1979
9958922a 1980 snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 1981
1982 return status;
1983}
1984
01ef7dbf
IM		 1985static int dsp_allocate_ports_format(struct hda_codec *codec,
1986 const unsigned short fmt,
1987 unsigned int *port_map)
1988{
1989 int status;
1990 unsigned int num_chans;
1991
1992 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1993 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1994 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
1995
1996 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
9958922a 1997 snd_printdd(KERN_ERR "bad rate multiple\n");
01ef7dbf
IM		 1998 return -EINVAL;
1999 }
2000
2001 num_chans = get_hdafmt_chs(fmt) + 1;
2002
2003 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2004
2005 return status;
2006}
2007
d5c21b88
IM		 2008/*
2009 * free DSP ports
2010 */
2011static int dsp_free_ports(struct hda_codec *codec)
2012{
2013 int status;
2014
9958922a 2015 snd_printdd(KERN_INFO " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2016
2017 status = dsp_free_router_ports(codec);
2018 if (status < 0) {
9958922a 2019 snd_printdd(KERN_ERR "free router ports fail\n");
d5c21b88
IM		 2020 return status;
2021 }
9958922a 2022 snd_printdd(KERN_INFO " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2023
2024 return status;
2025}
2026
01ef7dbf
IM		 2027/*
2028 * HDA DMA engine stuffs for DSP code download
2029 */
2030struct dma_engine {
2031 struct hda_codec *codec;
2032 unsigned short m_converter_format;
2033 struct snd_dma_buffer *dmab;
2034 unsigned int buf_size;
2035};
2036
2037
2038enum dma_state {
2039 DMA_STATE_STOP = 0,
2040 DMA_STATE_RUN = 1
2041};
2042
2043static int dma_convert_to_hda_format(
e97249dd
IM		 2044 unsigned int sample_rate,
2045 unsigned short channels,
01ef7dbf
IM		 2046 unsigned short *hda_format)
2047{
2048 unsigned int format_val;
2049
2050 format_val = snd_hda_calc_stream_format(
e97249dd
IM		 2051 sample_rate,
2052 channels,
01ef7dbf 2053 SNDRV_PCM_FORMAT_S32_LE,
e97249dd 2054 32, 0);
01ef7dbf
IM		 2055
2056 if (hda_format)
2057 *hda_format = (unsigned short)format_val;
2058
2059 return 0;
2060}
2061
d5c21b88
IM		 2062/*
2063 * Reset DMA for DSP download
2064 */
01ef7dbf
IM		 2065static int dma_reset(struct dma_engine *dma)
2066{
2067 struct hda_codec *codec = dma->codec;
2068 struct ca0132_spec *spec = codec->spec;
2069 int status;
2070
b3667bd7 2071 if (dma->dmab->area)
01ef7dbf
IM		 2072 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2073
2074 status = snd_hda_codec_load_dsp_prepare(codec,
2075 dma->m_converter_format,
2076 dma->buf_size,
2077 dma->dmab);
2078 if (status < 0)
2079 return status;
2080 spec->dsp_stream_id = status;
2081 return 0;
2082}
2083
2084static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2085{
01ef7dbf
IM		 2086 bool cmd;
2087
2088 snd_printdd("dma_set_state state=%d\n", state);
2089
2090 switch (state) {
2091 case DMA_STATE_STOP:
2092 cmd = false;
2093 break;
2094 case DMA_STATE_RUN:
2095 cmd = true;
2096 break;
2097 default:
c41999a2
DH		 2098 return 0;
2099 }
01ef7dbf
IM		 2100
2101 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2102 return 0;
95c6e9cb
IM		 2103}
2104
01ef7dbf
IM		 2105static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2106{
2107 return dma->dmab->bytes;
2108}
95c6e9cb 2109
01ef7dbf
IM		 2110static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2111{
2112 return dma->dmab->area;
2113}
95c6e9cb 2114
01ef7dbf
IM		 2115static int dma_xfer(struct dma_engine *dma,
2116 const unsigned int *data,
2117 unsigned int count)
2118{
2119 memcpy(dma->dmab->area, data, count);
2120 return 0;
2121}
95c6e9cb 2122
01ef7dbf
IM		 2123static void dma_get_converter_format(
2124 struct dma_engine *dma,
2125 unsigned short *format)
2126{
2127 if (format)
2128 *format = dma->m_converter_format;
2129}
95c6e9cb 2130
01ef7dbf 2131static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2132{
01ef7dbf 2133 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2134
01ef7dbf 2135 return spec->dsp_stream_id;
95c6e9cb
IM		 2136}
2137
01ef7dbf
IM		 2138struct dsp_image_seg {
2139 u32 magic;
2140 u32 chip_addr;
2141 u32 count;
2142 u32 data[0];
2143};
2144
2145static const u32 g_magic_value = 0x4c46584d;
2146static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2147
2148static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2149{
01ef7dbf
IM		 2150 return p->magic == g_magic_value;
2151}
95c6e9cb 2152
01ef7dbf
IM		 2153static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2154{
2155 return g_chip_addr_magic_value == p->chip_addr;
2156}
95c6e9cb 2157
01ef7dbf
IM		 2158static bool is_last(const struct dsp_image_seg *p)
2159{
2160 return p->count == 0;
2161}
95c6e9cb 2162
01ef7dbf
IM		 2163static size_t dsp_sizeof(const struct dsp_image_seg *p)
2164{
2165 return sizeof(*p) + p->count*sizeof(u32);
2166}
2167
2168static const struct dsp_image_seg *get_next_seg_ptr(
2169 const struct dsp_image_seg *p)
2170{
2171 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2172}
2173
2174/*
01ef7dbf 2175 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2176 */
8ae3124b 2177#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2178
d5c21b88
IM		 2179/*
2180 * Program a list of address/data pairs via the ChipIO widget.
2181 * The segment data is in the format of successive pairs of words.
2182 * These are repeated as indicated by the segment's count field.
2183 */
01ef7dbf
IM		 2184static int dspxfr_hci_write(struct hda_codec *codec,
2185 const struct dsp_image_seg *fls)
95c6e9cb 2186{
01ef7dbf
IM		 2187 int status;
2188 const u32 *data;
2189 unsigned int count;
95c6e9cb 2190
01ef7dbf 2191 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
9958922a 2192 snd_printdd(KERN_ERR "hci_write invalid params\n");
01ef7dbf 2193 return -EINVAL;
95c6e9cb
IM		 2194 }
2195
01ef7dbf
IM		 2196 count = fls->count;
2197 data = (u32 *)(fls->data);
2198 while (count >= 2) {
2199 status = chipio_write(codec, data[0], data[1]);
2200 if (status < 0) {
9958922a 2201 snd_printdd(KERN_ERR "hci_write chipio failed\n");
01ef7dbf
IM		 2202 return status;
2203 }
2204 count -= 2;
2205 data += 2;
2206 }
2207 return 0;
95c6e9cb
IM		 2208}
2209
d5c21b88
IM		 2210/**
2211 * Write a block of data into DSP code or data RAM using pre-allocated
2212 * DMA engine.
2213 *
2214 * @codec: the HDA codec
2215 * @fls: pointer to a fast load image
2216 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2217 * no relocation
2218 * @dma_engine: pointer to DMA engine to be used for DSP download
2219 * @dma_chan: The number of DMA channels used for DSP download
2220 * @port_map_mask: port mapping
2221 * @ovly: TRUE if overlay format is required
2222 *
2223 * Returns zero or a negative error code.
2224 */
01ef7dbf
IM		 2225static int dspxfr_one_seg(struct hda_codec *codec,
2226 const struct dsp_image_seg *fls,
2227 unsigned int reloc,
2228 struct dma_engine *dma_engine,
2229 unsigned int dma_chan,
2230 unsigned int port_map_mask,
2231 bool ovly)
95c6e9cb 2232{
406261ce 2233 int status = 0;
01ef7dbf
IM		 2234 bool comm_dma_setup_done = false;
2235 const unsigned int *data;
2236 unsigned int chip_addx;
2237 unsigned int words_to_write;
2238 unsigned int buffer_size_words;
2239 unsigned char *buffer_addx;
2240 unsigned short hda_format;
2241 unsigned int sample_rate_div;
2242 unsigned int sample_rate_mul;
2243 unsigned int num_chans;
2244 unsigned int hda_frame_size_words;
2245 unsigned int remainder_words;
2246 const u32 *data_remainder;
2247 u32 chip_addx_remainder;
2248 unsigned int run_size_words;
2249 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2250 unsigned long timeout;
2251 bool dma_active;
01ef7dbf
IM		 2252
2253 if (fls == NULL)
2254 return -EINVAL;
2255 if (is_hci_prog_list_seg(fls)) {
2256 hci_write = fls;
2257 fls = get_next_seg_ptr(fls);
2258 }
95c6e9cb 2259
01ef7dbf
IM		 2260 if (hci_write && (!fls || is_last(fls))) {
2261 snd_printdd("hci_write\n");
2262 return dspxfr_hci_write(codec, hci_write);
2263 }
95c6e9cb 2264
01ef7dbf
IM		 2265 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2266 snd_printdd("Invalid Params\n");
2267 return -EINVAL;
95c6e9cb
IM		 2268 }
2269
01ef7dbf
IM		 2270 data = fls->data;
2271 chip_addx = fls->chip_addr,
2272 words_to_write = fls->count;
2273
2274 if (!words_to_write)
2275 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2276 if (reloc)
2277 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2278
2279 if (!UC_RANGE(chip_addx, words_to_write) &&
2280 !X_RANGE_ALL(chip_addx, words_to_write) &&
2281 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2282 snd_printdd("Invalid chip_addx Params\n");
2283 return -EINVAL;
95c6e9cb
IM		 2284 }
2285
01ef7dbf
IM		 2286 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2287 sizeof(u32);
2288
2289 buffer_addx = dma_get_buffer_addr(dma_engine);
2290
2291 if (buffer_addx == NULL) {
2292 snd_printdd(KERN_ERR "dma_engine buffer NULL\n");
2293 return -EINVAL;
2294 }
2295
2296 dma_get_converter_format(dma_engine, &hda_format);
2297 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2298 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2299 num_chans = get_hdafmt_chs(hda_format) + 1;
2300
2301 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2302 (num_chans * sample_rate_mul / sample_rate_div));
2303
3bc085a1
XW		 2304 if (hda_frame_size_words == 0) {
2305 snd_printdd(KERN_ERR "frmsz zero\n");
2306 return -EINVAL;
2307 }
2308
01ef7dbf
IM		 2309 buffer_size_words = min(buffer_size_words,
2310 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2311 65536 : 32768));
2312 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2313 snd_printdd(
2314 "chpadr=0x%08x frmsz=%u nchan=%u "
2315 "rate_mul=%u div=%u bufsz=%u\n",
2316 chip_addx, hda_frame_size_words, num_chans,
2317 sample_rate_mul, sample_rate_div, buffer_size_words);
2318
3bc085a1 2319 if (buffer_size_words < hda_frame_size_words) {
01ef7dbf
IM		 2320 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n");
2321 return -EINVAL;
2322 }
2323
2324 remainder_words = words_to_write % hda_frame_size_words;
2325 data_remainder = data;
2326 chip_addx_remainder = chip_addx;
2327
2328 data += remainder_words;
2329 chip_addx += remainder_words*sizeof(u32);
2330 words_to_write -= remainder_words;
2331
2332 while (words_to_write != 0) {
2333 run_size_words = min(buffer_size_words, words_to_write);
2334 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2335 words_to_write, run_size_words, remainder_words);
2336 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2337 if (!comm_dma_setup_done) {
2338 status = dsp_dma_stop(codec, dma_chan, ovly);
2339 if (status < 0)
425a7880 2340 return status;
01ef7dbf
IM		 2341 status = dsp_dma_setup_common(codec, chip_addx,
2342 dma_chan, port_map_mask, ovly);
2343 if (status < 0)
2344 return status;
2345 comm_dma_setup_done = true;
2346 }
2347
2348 status = dsp_dma_setup(codec, chip_addx,
2349 run_size_words, dma_chan);
2350 if (status < 0)
2351 return status;
2352 status = dsp_dma_start(codec, dma_chan, ovly);
2353 if (status < 0)
2354 return status;
2355 if (!dsp_is_dma_active(codec, dma_chan)) {
9958922a 2356 snd_printdd(KERN_ERR "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2357 return -EIO;
2358 }
2359 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2360 if (status < 0)
2361 return status;
2362 if (remainder_words != 0) {
2363 status = chipio_write_multiple(codec,
2364 chip_addx_remainder,
2365 data_remainder,
2366 remainder_words);
b3667bd7
TI		 2367 if (status < 0)
2368 return status;
01ef7dbf
IM		 2369 remainder_words = 0;
2370 }
2371 if (hci_write) {
2372 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2373 if (status < 0)
2374 return status;
01ef7dbf
IM		 2375 hci_write = NULL;
2376 }
6d67530e
IM		 2377
2378 timeout = jiffies + msecs_to_jiffies(2000);
2379 do {
2380 dma_active = dsp_is_dma_active(codec, dma_chan);
2381 if (!dma_active)
01ef7dbf 2382 break;
6d67530e
IM		 2383 msleep(20);
2384 } while (time_before(jiffies, timeout));
2385 if (dma_active)
2386 break;
2387
9958922a 2388 snd_printdd(KERN_INFO "+++++ DMA complete\n");
01ef7dbf 2389 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2390 status = dma_reset(dma_engine);
01ef7dbf
IM		 2391
2392 if (status < 0)
2393 return status;
2394
2395 data += run_size_words;
2396 chip_addx += run_size_words*sizeof(u32);
2397 words_to_write -= run_size_words;
2398 }
2399
2400 if (remainder_words != 0) {
2401 status = chipio_write_multiple(codec, chip_addx_remainder,
2402 data_remainder, remainder_words);
2403 }
2404
2405 return status;
95c6e9cb
IM		 2406}
2407
d5c21b88
IM		 2408/**
2409 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2410 *
2411 * @codec: the HDA codec
2412 * @fls_data: pointer to a fast load image
2413 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2414 * no relocation
e97249dd
IM		 2415 * @sample_rate: sampling rate of the stream used for DSP download
2416 * @number_channels: channels of the stream used for DSP download
d5c21b88
IM		 2417 * @ovly: TRUE if overlay format is required
2418 *
2419 * Returns zero or a negative error code.
2420 */
01ef7dbf
IM		 2421static int dspxfr_image(struct hda_codec *codec,
2422 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2423 unsigned int reloc,
2424 unsigned int sample_rate,
2425 unsigned short channels,
01ef7dbf 2426 bool ovly)
95c6e9cb
IM		 2427{
2428 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2429 int status;
2430 unsigned short hda_format = 0;
2431 unsigned int response;
2432 unsigned char stream_id = 0;
2433 struct dma_engine *dma_engine;
2434 unsigned int dma_chan;
2435 unsigned int port_map_mask;
2436
2437 if (fls_data == NULL)
2438 return -EINVAL;
2439
2440 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2441 if (!dma_engine)
2442 return -ENOMEM;
95c6e9cb 2443
01ef7dbf
IM		 2444 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2445 if (!dma_engine->dmab) {
549e8292
TI		 2446 kfree(dma_engine);
2447 return -ENOMEM;
01ef7dbf 2448 }
95c6e9cb 2449
01ef7dbf 2450 dma_engine->codec = codec;
e97249dd 2451 dma_convert_to_hda_format(sample_rate, channels, &hda_format);
01ef7dbf
IM		 2452 dma_engine->m_converter_format = hda_format;
2453 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2454 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2455
8ae3124b 2456 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2457
2458 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2459 hda_format, &response);
2460
2461 if (status < 0) {
9958922a 2462 snd_printdd(KERN_ERR "set converter format fail\n");
01ef7dbf
IM		 2463 goto exit;
2464 }
2465
2466 status = snd_hda_codec_load_dsp_prepare(codec,
2467 dma_engine->m_converter_format,
2468 dma_engine->buf_size,
2469 dma_engine->dmab);
2470 if (status < 0)
95c6e9cb 2471 goto exit;
01ef7dbf
IM		 2472 spec->dsp_stream_id = status;
2473
2474 if (ovly) {
2475 status = dspio_alloc_dma_chan(codec, &dma_chan);
2476 if (status < 0) {
9958922a 2477 snd_printdd(KERN_ERR "alloc dmachan fail\n");
8ae3124b 2478 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2479 goto exit;
2480 }
2481 }
95c6e9cb 2482
01ef7dbf
IM		 2483 port_map_mask = 0;
2484 status = dsp_allocate_ports_format(codec, hda_format,
2485 &port_map_mask);
2486 if (status < 0) {
9958922a 2487 snd_printdd(KERN_ERR "alloc ports fail\n");
01ef7dbf
IM		 2488 goto exit;
2489 }
2490
2491 stream_id = dma_get_stream_id(dma_engine);
2492 status = codec_set_converter_stream_channel(codec,
2493 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2494 if (status < 0) {
9958922a 2495 snd_printdd(KERN_ERR "set stream chan fail\n");
01ef7dbf
IM		 2496 goto exit;
2497 }
2498
2499 while ((fls_data != NULL) && !is_last(fls_data)) {
2500 if (!is_valid(fls_data)) {
9958922a 2501 snd_printdd(KERN_ERR "FLS check fail\n");
01ef7dbf
IM		 2502 status = -EINVAL;
2503 goto exit;
2504 }
2505 status = dspxfr_one_seg(codec, fls_data, reloc,
2506 dma_engine, dma_chan,
2507 port_map_mask, ovly);
2508 if (status < 0)
2509 break;
2510
2511 if (is_hci_prog_list_seg(fls_data))
2512 fls_data = get_next_seg_ptr(fls_data);
2513
2514 if ((fls_data != NULL) && !is_last(fls_data))
2515 fls_data = get_next_seg_ptr(fls_data);
2516 }
2517
2518 if (port_map_mask != 0)
2519 status = dsp_free_ports(codec);
2520
2521 if (status < 0)
95c6e9cb
IM		 2522 goto exit;
2523
01ef7dbf
IM		 2524 status = codec_set_converter_stream_channel(codec,
2525 WIDGET_CHIP_CTRL, 0, 0, &response);
2526
95c6e9cb 2527exit:
01ef7dbf
IM		 2528 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2529 dspio_free_dma_chan(codec, dma_chan);
2530
b3667bd7 2531 if (dma_engine->dmab->area)
01ef7dbf
IM		 2532 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2533 kfree(dma_engine->dmab);
2534 kfree(dma_engine);
2535
2536 return status;
95c6e9cb
IM		 2537}
2538
2539/*
01ef7dbf 2540 * CA0132 DSP download stuffs.
95c6e9cb 2541 */
01ef7dbf 2542static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2543{
9958922a 2544 snd_printdd(KERN_INFO "---- dspload_post_setup ------\n");
95c6e9cb 2545
01ef7dbf
IM		 2546 /*set DSP speaker to 2.0 configuration*/
2547 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2548 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2549
01ef7dbf
IM		 2550 /*update write pointer*/
2551 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2552}
95c6e9cb 2553
d5c21b88
IM		 2554/**
2555 * Download DSP from a DSP Image Fast Load structure. This structure is a
2556 * linear, non-constant sized element array of structures, each of which
2557 * contain the count of the data to be loaded, the data itself, and the
2558 * corresponding starting chip address of the starting data location.
2559 *
2560 * @codec: the HDA codec
2561 * @fls: pointer to a fast load image
2562 * @ovly: TRUE if overlay format is required
2563 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2564 * no relocation
2565 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2566 * @router_chans: number of audio router channels to be allocated (0 means use
2567 * internal defaults; max is 32)
2568 *
2569 * Returns zero or a negative error code.
2570 */
01ef7dbf
IM		 2571static int dspload_image(struct hda_codec *codec,
2572 const struct dsp_image_seg *fls,
2573 bool ovly,
2574 unsigned int reloc,
2575 bool autostart,
2576 int router_chans)
2577{
2578 int status = 0;
e97249dd
IM		 2579 unsigned int sample_rate;
2580 unsigned short channels;
01ef7dbf 2581
9958922a 2582 snd_printdd(KERN_INFO "---- dspload_image begin ------\n");
01ef7dbf
IM		 2583 if (router_chans == 0) {
2584 if (!ovly)
2585 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2586 else
2587 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2588 }
95c6e9cb 2589
e97249dd
IM		 2590 sample_rate = 48000;
2591 channels = (unsigned short)router_chans;
01ef7dbf 2592
e97249dd
IM		 2593 while (channels > 16) {
2594 sample_rate *= 2;
2595 channels /= 2;
01ef7dbf
IM		 2596 }
2597
01ef7dbf 2598 do {
9958922a 2599 snd_printdd(KERN_INFO "Ready to program DMA\n");
01ef7dbf
IM		 2600 if (!ovly)
2601 status = dsp_reset(codec);
2602
2603 if (status < 0)
2604 break;
2605
9958922a 2606 snd_printdd(KERN_INFO "dsp_reset() complete\n");
e97249dd
IM		 2607 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2608 ovly);
01ef7dbf
IM		 2609
2610 if (status < 0)
2611 break;
2612
9958922a 2613 snd_printdd(KERN_INFO "dspxfr_image() complete\n");
01ef7dbf
IM		 2614 if (autostart && !ovly) {
2615 dspload_post_setup(codec);
2616 status = dsp_set_run_state(codec);
2617 }
2618
9958922a 2619 snd_printdd(KERN_INFO "LOAD FINISHED\n");
01ef7dbf
IM		 2620 } while (0);
2621
2622 return status;
2623}
2624
f664417e 2625#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 2626static bool dspload_is_loaded(struct hda_codec *codec)
2627{
2628 unsigned int data = 0;
2629 int status = 0;
2630
2631 status = chipio_read(codec, 0x40004, &data);
2632 if ((status < 0) || (data != 1))
2633 return false;
2634
2635 return true;
2636}
f664417e
TI		 2637#else
2638#define dspload_is_loaded(codec) false
2639#endif
01ef7dbf
IM		 2640
2641static bool dspload_wait_loaded(struct hda_codec *codec)
2642{
6d67530e 2643 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 2644
2645 do {
01ef7dbf
IM		 2646 if (dspload_is_loaded(codec)) {
2647 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2648 return true;
2649 }
6d67530e
IM		 2650 msleep(20);
2651 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 2652
2653 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2654 return false;
95c6e9cb
IM		 2655}
2656
2657/*
825315bc 2658 * PCM stuffs
95c6e9cb 2659 */
825315bc
IM		 2660static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
2661 u32 stream_tag,
2662 int channel_id, int format)
95c6e9cb 2663{
825315bc
IM		 2664 unsigned int oldval, newval;
2665
2666 if (!nid)
2667 return;
2668
2669 snd_printdd(
2670 "ca0132_setup_stream: NID=0x%x, stream=0x%x, "
2671 "channel=%d, format=0x%x\n",
2672 nid, stream_tag, channel_id, format);
2673
2674 /* update the format-id if changed */
2675 oldval = snd_hda_codec_read(codec, nid, 0,
2676 AC_VERB_GET_STREAM_FORMAT,
2677 0);
2678 if (oldval != format) {
2679 msleep(20);
2680 snd_hda_codec_write(codec, nid, 0,
2681 AC_VERB_SET_STREAM_FORMAT,
2682 format);
2683 }
2684
2685 oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2686 newval = (stream_tag << 4) | channel_id;
2687 if (oldval != newval) {
2688 snd_hda_codec_write(codec, nid, 0,
2689 AC_VERB_SET_CHANNEL_STREAMID,
2690 newval);
2691 }
2692}
2693
2694static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
2695{
2696 unsigned int val;
2697
2698 if (!nid)
2699 return;
2700
2701 snd_printdd(KERN_INFO "ca0132_cleanup_stream: NID=0x%x\n", nid);
2702
2703 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2704 if (!val)
2705 return;
2706
2707 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
2708 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
95c6e9cb
IM		 2709}
2710
825315bc
IM		 2711/*
2712 * PCM callbacks
2713 */
95c6e9cb
IM		 2714static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2715 struct hda_codec *codec,
2716 unsigned int stream_tag,
2717 unsigned int format,
2718 struct snd_pcm_substream *substream)
2719{
2720 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2721
2722 ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2723
2724 return 0;
95c6e9cb
IM		 2725}
2726
2727static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2728 struct hda_codec *codec,
2729 struct snd_pcm_substream *substream)
2730{
2731 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2732
2733 if (spec->dsp_state == DSP_DOWNLOADING)
2734 return 0;
2735
2736 /*If Playback effects are on, allow stream some time to flush
2737 *effects tail*/
2738 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2739 msleep(50);
2740
2741 ca0132_cleanup_stream(codec, spec->dacs[0]);
2742
2743 return 0;
95c6e9cb
IM		 2744}
2745
2746/*
2747 * Digital out
2748 */
27ebeb0b
TI		 2749static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2750 struct hda_codec *codec,
2751 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2752{
2753 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2754 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2755}
2756
27ebeb0b 2757static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2758 struct hda_codec *codec,
2759 unsigned int stream_tag,
2760 unsigned int format,
2761 struct snd_pcm_substream *substream)
2762{
2763 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2764 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2765 stream_tag, format, substream);
95c6e9cb
IM		 2766}
2767
27ebeb0b 2768static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2769 struct hda_codec *codec,
95c6e9cb
IM		 2770 struct snd_pcm_substream *substream)
2771{
2772 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2773 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2774}
2775
27ebeb0b
TI		 2776static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2777 struct hda_codec *codec,
2778 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2779{
2780 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2781 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2782}
2783
825315bc
IM		 2784/*
2785 * Analog capture
2786 */
2787static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2788 struct hda_codec *codec,
2789 unsigned int stream_tag,
2790 unsigned int format,
2791 struct snd_pcm_substream *substream)
2792{
2793 struct ca0132_spec *spec = codec->spec;
2794
2795 ca0132_setup_stream(codec, spec->adcs[substream->number],
2796 stream_tag, 0, format);
2797
2798 return 0;
2799}
2800
2801static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2802 struct hda_codec *codec,
2803 struct snd_pcm_substream *substream)
2804{
2805 struct ca0132_spec *spec = codec->spec;
2806
2807 if (spec->dsp_state == DSP_DOWNLOADING)
2808 return 0;
2809
2810 ca0132_cleanup_stream(codec, hinfo->nid);
2811 return 0;
2812}
2813
e90f29e4
IM		 2814/*
2815 * Controls stuffs.
2816 */
2817
2818/*
2819 * Mixer controls helpers.
2820 */
2821#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2822 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2823 .name = xname, \
2824 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2825 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2826 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2827 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2828 .info = ca0132_volume_info, \
2829 .get = ca0132_volume_get, \
2830 .put = ca0132_volume_put, \
2831 .tlv = { .c = ca0132_volume_tlv }, \
2832 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2833
2834#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2835 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2836 .name = xname, \
2837 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2838 .info = snd_hda_mixer_amp_switch_info, \
2839 .get = ca0132_switch_get, \
2840 .put = ca0132_switch_put, \
2841 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2842
2843/* stereo */
2844#define CA0132_CODEC_VOL(xname, nid, dir) \
2845 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2846#define CA0132_CODEC_MUTE(xname, nid, dir) \
2847 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2848
44f0c978
IM		 2849/* The followings are for tuning of products */
2850#ifdef ENABLE_TUNING_CONTROLS
2851
2852static unsigned int voice_focus_vals_lookup[] = {
28530x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
28540x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
28550x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
28560x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
28570x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
28580x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
28590x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
28600x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
28610x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
28620x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
28630x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
28640x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
28650x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
28660x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
28670x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
28680x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
28690x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
28700x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
28710x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
28720x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
28730x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
28740x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
28750x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
28760x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
28770x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
28780x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
28790x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2880};
2881
2882static unsigned int mic_svm_vals_lookup[] = {
28830x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
28840x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
28850x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
28860x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
28870x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
28880x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
28890x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
28900x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
28910x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
28920x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
28930x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
28940x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
28950x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
28960x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
28970x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
28980x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
28990x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2900};
2901
2902static unsigned int equalizer_vals_lookup[] = {
29030xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
29040xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
29050xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
29060xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
29070x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
29080x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
29090x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
29100x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
29110x41C00000
2912};
2913
2914static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2915 unsigned int *lookup, int idx)
2916{
2917 int i = 0;
2918
2919 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2920 if (nid == ca0132_tuning_ctls[i].nid)
2921 break;
2922
2923 snd_hda_power_up(codec);
2924 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2925 ca0132_tuning_ctls[i].req,
2926 &(lookup[idx]), sizeof(unsigned int));
2927 snd_hda_power_down(codec);
2928
2929 return 1;
2930}
2931
2932static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2933 struct snd_ctl_elem_value *ucontrol)
2934{
2935 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2936 struct ca0132_spec *spec = codec->spec;
2937 hda_nid_t nid = get_amp_nid(kcontrol);
2938 long *valp = ucontrol->value.integer.value;
2939 int idx = nid - TUNING_CTL_START_NID;
2940
2941 *valp = spec->cur_ctl_vals[idx];
2942 return 0;
2943}
2944
2945static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2946 struct snd_ctl_elem_info *uinfo)
2947{
2948 int chs = get_amp_channels(kcontrol);
2949 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2950 uinfo->count = chs == 3 ? 2 : 1;
2951 uinfo->value.integer.min = 20;
2952 uinfo->value.integer.max = 180;
2953 uinfo->value.integer.step = 1;
2954
2955 return 0;
2956}
2957
2958static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2959 struct snd_ctl_elem_value *ucontrol)
2960{
2961 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2962 struct ca0132_spec *spec = codec->spec;
2963 hda_nid_t nid = get_amp_nid(kcontrol);
2964 long *valp = ucontrol->value.integer.value;
2965 int idx;
2966
2967 idx = nid - TUNING_CTL_START_NID;
2968 /* any change? */
2969 if (spec->cur_ctl_vals[idx] == *valp)
2970 return 0;
2971
2972 spec->cur_ctl_vals[idx] = *valp;
2973
2974 idx = *valp - 20;
2975 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2976
2977 return 1;
2978}
2979
2980static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2981 struct snd_ctl_elem_info *uinfo)
2982{
2983 int chs = get_amp_channels(kcontrol);
2984 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2985 uinfo->count = chs == 3 ? 2 : 1;
2986 uinfo->value.integer.min = 0;
2987 uinfo->value.integer.max = 100;
2988 uinfo->value.integer.step = 1;
2989
2990 return 0;
2991}
2992
2993static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2994 struct snd_ctl_elem_value *ucontrol)
2995{
2996 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2997 struct ca0132_spec *spec = codec->spec;
2998 hda_nid_t nid = get_amp_nid(kcontrol);
2999 long *valp = ucontrol->value.integer.value;
3000 int idx;
3001
3002 idx = nid - TUNING_CTL_START_NID;
3003 /* any change? */
3004 if (spec->cur_ctl_vals[idx] == *valp)
3005 return 0;
3006
3007 spec->cur_ctl_vals[idx] = *valp;
3008
3009 idx = *valp;
3010 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3011
3012 return 0;
3013}
3014
3015static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3016 struct snd_ctl_elem_info *uinfo)
3017{
3018 int chs = get_amp_channels(kcontrol);
3019 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3020 uinfo->count = chs == 3 ? 2 : 1;
3021 uinfo->value.integer.min = 0;
3022 uinfo->value.integer.max = 48;
3023 uinfo->value.integer.step = 1;
3024
3025 return 0;
3026}
3027
3028static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3029 struct snd_ctl_elem_value *ucontrol)
3030{
3031 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3032 struct ca0132_spec *spec = codec->spec;
3033 hda_nid_t nid = get_amp_nid(kcontrol);
3034 long *valp = ucontrol->value.integer.value;
3035 int idx;
3036
3037 idx = nid - TUNING_CTL_START_NID;
3038 /* any change? */
3039 if (spec->cur_ctl_vals[idx] == *valp)
3040 return 0;
3041
3042 spec->cur_ctl_vals[idx] = *valp;
3043
3044 idx = *valp;
3045 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3046
3047 return 1;
3048}
3049
3050static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3051static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3052
3053static int add_tuning_control(struct hda_codec *codec,
3054 hda_nid_t pnid, hda_nid_t nid,
3055 const char *name, int dir)
3056{
3057 char namestr[44];
3058 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3059 struct snd_kcontrol_new knew =
3060 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3061
3062 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3063 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3064 knew.tlv.c = 0;
3065 knew.tlv.p = 0;
3066 switch (pnid) {
3067 case VOICE_FOCUS:
3068 knew.info = voice_focus_ctl_info;
3069 knew.get = tuning_ctl_get;
3070 knew.put = voice_focus_ctl_put;
3071 knew.tlv.p = voice_focus_db_scale;
3072 break;
3073 case MIC_SVM:
3074 knew.info = mic_svm_ctl_info;
3075 knew.get = tuning_ctl_get;
3076 knew.put = mic_svm_ctl_put;
3077 break;
3078 case EQUALIZER:
3079 knew.info = equalizer_ctl_info;
3080 knew.get = tuning_ctl_get;
3081 knew.put = equalizer_ctl_put;
3082 knew.tlv.p = eq_db_scale;
3083 break;
3084 default:
3085 return 0;
3086 }
3087 knew.private_value =
3088 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3089 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3090 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3091}
3092
3093static int add_tuning_ctls(struct hda_codec *codec)
3094{
3095 int i;
3096 int err;
3097
3098 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3099 err = add_tuning_control(codec,
3100 ca0132_tuning_ctls[i].parent_nid,
3101 ca0132_tuning_ctls[i].nid,
3102 ca0132_tuning_ctls[i].name,
3103 ca0132_tuning_ctls[i].direct);
3104 if (err < 0)
3105 return err;
3106 }
3107
3108 return 0;
3109}
3110
3111static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3112{
3113 struct ca0132_spec *spec = codec->spec;
3114 int i;
3115
3116 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3117 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3118 /* SVM level defaults to 0.74. */
3119 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3120
3121 /* EQ defaults to 0dB. */
3122 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3123 spec->cur_ctl_vals[i] = 24;
3124}
3125#endif /*ENABLE_TUNING_CONTROLS*/
3126
5aaca44d
IM		 3127/*
3128 * Select the active output.
3129 * If autodetect is enabled, output will be selected based on jack detection.
3130 * If jack inserted, headphone will be selected, else built-in speakers
3131 * If autodetect is disabled, output will be selected based on selection.
3132 */
3133static int ca0132_select_out(struct hda_codec *codec)
3134{
3135 struct ca0132_spec *spec = codec->spec;
3136 unsigned int pin_ctl;
3137 int jack_present;
3138 int auto_jack;
3139 unsigned int tmp;
3140 int err;
3141
3142 snd_printdd(KERN_INFO "ca0132_select_out\n");
3143
3144 snd_hda_power_up(codec);
3145
3146 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3147
3148 if (auto_jack)
3149 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3150 else
3151 jack_present =
3152 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3153
3154 if (jack_present)
3155 spec->cur_out_type = HEADPHONE_OUT;
3156 else
3157 spec->cur_out_type = SPEAKER_OUT;
3158
3159 if (spec->cur_out_type == SPEAKER_OUT) {
3160 snd_printdd(KERN_INFO "ca0132_select_out speaker\n");
3161 /*speaker out config*/
3162 tmp = FLOAT_ONE;
3163 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3164 if (err < 0)
3165 goto exit;
3166 /*enable speaker EQ*/
3167 tmp = FLOAT_ONE;
3168 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3169 if (err < 0)
3170 goto exit;
3171
3172 /* Setup EAPD */
3173 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3174 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3175 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3176 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3177 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3178 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3179 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3180 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3181
3182 /* disable headphone node */
3183 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3184 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3185 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3186 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3187 /* enable speaker node */
3188 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3189 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3190 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3191 pin_ctl | PIN_OUT);
5aaca44d
IM		 3192 } else {
3193 snd_printdd(KERN_INFO "ca0132_select_out hp\n");
3194 /*headphone out config*/
3195 tmp = FLOAT_ZERO;
3196 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3197 if (err < 0)
3198 goto exit;
3199 /*disable speaker EQ*/
3200 tmp = FLOAT_ZERO;
3201 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3202 if (err < 0)
3203 goto exit;
3204
3205 /* Setup EAPD */
3206 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3207 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3208 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3209 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3210 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3211 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3212 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3213 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3214
3215 /* disable speaker*/
3216 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3217 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3218 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3219 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3220 /* enable headphone*/
3221 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3222 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3223 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3224 pin_ctl | PIN_HP);
5aaca44d
IM		 3225 }
3226
3227exit:
3228 snd_hda_power_down(codec);
3229
3230 return err < 0 ? err : 0;
3231}
3232
993884f6
CCC		 3233static void ca0132_unsol_hp_delayed(struct work_struct *work)
3234{
3235 struct ca0132_spec *spec = container_of(
3236 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3237 ca0132_select_out(spec->codec);
3238 snd_hda_jack_report_sync(spec->codec);
3239}
3240
5aaca44d
IM		 3241static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3242static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3243static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3244
3245/*
3246 * Select the active VIP source
3247 */
3248static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3249{
3250 struct ca0132_spec *spec = codec->spec;
3251 unsigned int tmp;
3252
e8f1bd5d 3253 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 3254 return 0;
3255
3256 /* if CrystalVoice if off, vipsource should be 0 */
3257 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3258 (val == 0)) {
3259 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3260 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3261 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3262 if (spec->cur_mic_type == DIGITAL_MIC)
3263 tmp = FLOAT_TWO;
3264 else
3265 tmp = FLOAT_ONE;
3266 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3267 tmp = FLOAT_ZERO;
3268 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3269 } else {
3270 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3271 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3272 if (spec->cur_mic_type == DIGITAL_MIC)
3273 tmp = FLOAT_TWO;
3274 else
3275 tmp = FLOAT_ONE;
3276 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3277 tmp = FLOAT_ONE;
3278 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3279 msleep(20);
3280 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3281 }
3282
3283 return 1;
3284}
3285
3286/*
3287 * Select the active microphone.
3288 * If autodetect is enabled, mic will be selected based on jack detection.
3289 * If jack inserted, ext.mic will be selected, else built-in mic
3290 * If autodetect is disabled, mic will be selected based on selection.
3291 */
3292static int ca0132_select_mic(struct hda_codec *codec)
3293{
3294 struct ca0132_spec *spec = codec->spec;
3295 int jack_present;
3296 int auto_jack;
3297
3298 snd_printdd(KERN_INFO "ca0132_select_mic\n");
3299
3300 snd_hda_power_up(codec);
3301
3302 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3303
3304 if (auto_jack)
3305 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3306 else
3307 jack_present =
3308 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3309
3310 if (jack_present)
3311 spec->cur_mic_type = LINE_MIC_IN;
3312 else
3313 spec->cur_mic_type = DIGITAL_MIC;
3314
3315 if (spec->cur_mic_type == DIGITAL_MIC) {
3316 /* enable digital Mic */
3317 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3318 ca0132_set_dmic(codec, 1);
3319 ca0132_mic_boost_set(codec, 0);
3320 /* set voice focus */
3321 ca0132_effects_set(codec, VOICE_FOCUS,
3322 spec->effects_switch
3323 [VOICE_FOCUS - EFFECT_START_NID]);
3324 } else {
3325 /* disable digital Mic */
3326 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3327 ca0132_set_dmic(codec, 0);
3328 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3329 /* disable voice focus */
3330 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3331 }
3332
3333 snd_hda_power_down(codec);
3334
3335 return 0;
3336}
3337
a7e76271
IM		 3338/*
3339 * Check if VNODE settings take effect immediately.
3340 */
3341static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3342 hda_nid_t vnid,
3343 hda_nid_t *shared_nid)
3344{
3345 struct ca0132_spec *spec = codec->spec;
3346 hda_nid_t nid;
a7e76271
IM		 3347
3348 switch (vnid) {
3349 case VNID_SPK:
3350 nid = spec->shared_out_nid;
a7e76271
IM		 3351 break;
3352 case VNID_MIC:
3353 nid = spec->shared_mic_nid;
a7e76271
IM		 3354 break;
3355 default:
9a0869f4 3356 return false;
a7e76271
IM		 3357 }
3358
9a0869f4 3359 if (shared_nid)
a7e76271
IM		 3360 *shared_nid = nid;
3361
9a0869f4 3362 return true;
a7e76271
IM		 3363}
3364
3365/*
3366* The following functions are control change helpers.
3367* They return 0 if no changed. Return 1 if changed.
3368*/
3369static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3370{
3371 struct ca0132_spec *spec = codec->spec;
3372 unsigned int tmp;
3373
3374 /* based on CrystalVoice state to enable VoiceFX. */
3375 if (enable) {
3376 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3377 FLOAT_ONE : FLOAT_ZERO;
3378 } else {
3379 tmp = FLOAT_ZERO;
3380 }
3381
3382 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3383 ca0132_voicefx.reqs[0], tmp);
3384
3385 return 1;
3386}
3387
5aaca44d
IM		 3388/*
3389 * Set the effects parameters
3390 */
3391static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3392{
3393 struct ca0132_spec *spec = codec->spec;
3394 unsigned int on;
3395 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3396 int err = 0;
3397 int idx = nid - EFFECT_START_NID;
3398
3399 if ((idx < 0) || (idx >= num_fx))
3400 return 0; /* no changed */
3401
3402 /* for out effect, qualify with PE */
3403 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3404 /* if PE if off, turn off out effects. */
3405 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3406 val = 0;
3407 }
3408
3409 /* for in effect, qualify with CrystalVoice */
3410 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3411 /* if CrystalVoice if off, turn off in effects. */
3412 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3413 val = 0;
3414
3415 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3416 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3417 val = 0;
3418 }
3419
dea500c7 3420 snd_printdd(KERN_INFO "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 3421 nid, val);
3422
3423 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3424 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3425 ca0132_effects[idx].reqs[0], on);
3426
3427 if (err < 0)
3428 return 0; /* no changed */
3429
3430 return 1;
3431}
3432
a7e76271
IM		 3433/*
3434 * Turn on/off Playback Enhancements
3435 */
3436static int ca0132_pe_switch_set(struct hda_codec *codec)
3437{
3438 struct ca0132_spec *spec = codec->spec;
3439 hda_nid_t nid;
3440 int i, ret = 0;
3441
3442 snd_printdd(KERN_INFO "ca0132_pe_switch_set: val=%ld\n",
3443 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3444
3445 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3446 nid = OUT_EFFECT_START_NID;
3447 /* PE affects all out effects */
3448 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3449 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3450
3451 return ret;
3452}
3453
5aaca44d
IM		 3454/* Check if Mic1 is streaming, if so, stop streaming */
3455static int stop_mic1(struct hda_codec *codec)
3456{
3457 struct ca0132_spec *spec = codec->spec;
3458 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3459 AC_VERB_GET_CONV, 0);
3460 if (oldval != 0)
3461 snd_hda_codec_write(codec, spec->adcs[0], 0,
3462 AC_VERB_SET_CHANNEL_STREAMID,
3463 0);
3464 return oldval;
3465}
3466
3467/* Resume Mic1 streaming if it was stopped. */
3468static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3469{
3470 struct ca0132_spec *spec = codec->spec;
3471 /* Restore the previous stream and channel */
3472 if (oldval != 0)
3473 snd_hda_codec_write(codec, spec->adcs[0], 0,
3474 AC_VERB_SET_CHANNEL_STREAMID,
3475 oldval);
3476}
3477
3478/*
a7e76271 3479 * Turn on/off CrystalVoice
5aaca44d 3480 */
a7e76271
IM		 3481static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3482{
3483 struct ca0132_spec *spec = codec->spec;
3484 hda_nid_t nid;
3485 int i, ret = 0;
3486 unsigned int oldval;
3487
3488 snd_printdd(KERN_INFO "ca0132_cvoice_switch_set: val=%ld\n",
3489 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3490
3491 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3492 nid = IN_EFFECT_START_NID;
3493 /* CrystalVoice affects all in effects */
3494 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3495 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3496
3497 /* including VoiceFX */
3498 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3499
3500 /* set correct vipsource */
3501 oldval = stop_mic1(codec);
3502 ret |= ca0132_set_vipsource(codec, 1);
3503 resume_mic1(codec, oldval);
3504 return ret;
3505}
3506
5aaca44d
IM		 3507static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3508{
3509 struct ca0132_spec *spec = codec->spec;
3510 int ret = 0;
3511
3512 if (val) /* on */
3513 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3514 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3515 else /* off */
3516 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3517 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3518
3519 return ret;
3520}
3521
a7e76271
IM		 3522static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3523 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3524{
a7e76271
IM		 3525 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3526 hda_nid_t nid = get_amp_nid(kcontrol);
3527 hda_nid_t shared_nid = 0;
3528 bool effective;
3529 int ret = 0;
95c6e9cb 3530 struct ca0132_spec *spec = codec->spec;
a7e76271 3531 int auto_jack;
95c6e9cb 3532
a7e76271
IM		 3533 if (nid == VNID_HP_SEL) {
3534 auto_jack =
3535 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3536 if (!auto_jack)
3537 ca0132_select_out(codec);
3538 return 1;
3539 }
95c6e9cb 3540
a7e76271
IM		 3541 if (nid == VNID_AMIC1_SEL) {
3542 auto_jack =
3543 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3544 if (!auto_jack)
3545 ca0132_select_mic(codec);
3546 return 1;
3547 }
95c6e9cb 3548
a7e76271
IM		 3549 if (nid == VNID_HP_ASEL) {
3550 ca0132_select_out(codec);
3551 return 1;
3552 }
95c6e9cb 3553
a7e76271
IM		 3554 if (nid == VNID_AMIC1_ASEL) {
3555 ca0132_select_mic(codec);
3556 return 1;
95c6e9cb 3557 }
a7e76271
IM		 3558
3559 /* if effective conditions, then update hw immediately. */
3560 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3561 if (effective) {
3562 int dir = get_amp_direction(kcontrol);
3563 int ch = get_amp_channels(kcontrol);
3564 unsigned long pval;
3565
3566 mutex_lock(&codec->control_mutex);
3567 pval = kcontrol->private_value;
3568 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3569 0, dir);
3570 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3571 kcontrol->private_value = pval;
3572 mutex_unlock(&codec->control_mutex);
95c6e9cb 3573 }
95c6e9cb 3574
a7e76271 3575 return ret;
95c6e9cb 3576}
a7e76271 3577/* End of control change helpers. */
95c6e9cb 3578
a7e76271
IM		 3579static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3580 struct snd_ctl_elem_info *uinfo)
3581{
3582 unsigned int items = sizeof(ca0132_voicefx_presets)
3583 / sizeof(struct ct_voicefx_preset);
3584
3585 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3586 uinfo->count = 1;
3587 uinfo->value.enumerated.items = items;
3588 if (uinfo->value.enumerated.item >= items)
3589 uinfo->value.enumerated.item = items - 1;
3590 strcpy(uinfo->value.enumerated.name,
3591 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3592 return 0;
3593}
95c6e9cb 3594
a7e76271 3595static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3596 struct snd_ctl_elem_value *ucontrol)
3597{
3598 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3599 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3600
a7e76271 3601 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3602 return 0;
3603}
3604
a7e76271 3605static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3606 struct snd_ctl_elem_value *ucontrol)
3607{
3608 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3609 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3610 int i, err = 0;
3611 int sel = ucontrol->value.enumerated.item[0];
3612 unsigned int items = sizeof(ca0132_voicefx_presets)
3613 / sizeof(struct ct_voicefx_preset);
95c6e9cb 3614
a7e76271 3615 if (sel >= items)
95c6e9cb
IM		 3616 return 0;
3617
a7e76271
IM		 3618 snd_printdd(KERN_INFO "ca0132_voicefx_put: sel=%d, preset=%s\n",
3619 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3620
a7e76271
IM		 3621 /*
3622 * Idx 0 is default.
3623 * Default needs to qualify with CrystalVoice state.
3624 */
3625 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3626 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3627 ca0132_voicefx.reqs[i],
3628 ca0132_voicefx_presets[sel].vals[i]);
3629 if (err < 0)
3630 break;
3631 }
95c6e9cb 3632
a7e76271
IM		 3633 if (err >= 0) {
3634 spec->voicefx_val = sel;
3635 /* enable voice fx */
3636 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3637 }
95c6e9cb 3638
a7e76271 3639 return 1;
95c6e9cb
IM		 3640}
3641
a7e76271
IM		 3642static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3643 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3644{
3645 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3646 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3647 hda_nid_t nid = get_amp_nid(kcontrol);
3648 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3649 long *valp = ucontrol->value.integer.value;
3650
a7e76271
IM		 3651 /* vnode */
3652 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3653 if (ch & 1) {
3654 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3655 valp++;
3656 }
3657 if (ch & 2) {
3658 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3659 valp++;
3660 }
3661 return 0;
3662 }
3663
3664 /* effects, include PE and CrystalVoice */
3665 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3666 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3667 return 0;
3668 }
3669
3670 /* mic boost */
3671 if (nid == spec->input_pins[0]) {
3672 *valp = spec->cur_mic_boost;
3673 return 0;
3674 }
3675
95c6e9cb
IM		 3676 return 0;
3677}
3678
a7e76271
IM		 3679static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3680 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3681{
3682 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3683 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3684 hda_nid_t nid = get_amp_nid(kcontrol);
3685 int ch = get_amp_channels(kcontrol);
95c6e9cb 3686 long *valp = ucontrol->value.integer.value;
a7e76271 3687 int changed = 1;
95c6e9cb 3688
a7e76271
IM		 3689 snd_printdd(KERN_INFO "ca0132_switch_put: nid=0x%x, val=%ld\n",
3690 nid, *valp);
95c6e9cb
IM		 3691
3692 snd_hda_power_up(codec);
a7e76271
IM		 3693 /* vnode */
3694 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3695 if (ch & 1) {
3696 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3697 valp++;
3698 }
3699 if (ch & 2) {
3700 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3701 valp++;
3702 }
3703 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3704 goto exit;
3705 }
95c6e9cb 3706
a7e76271
IM		 3707 /* PE */
3708 if (nid == PLAY_ENHANCEMENT) {
3709 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3710 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3711 goto exit;
a7e76271 3712 }
95c6e9cb 3713
a7e76271
IM		 3714 /* CrystalVoice */
3715 if (nid == CRYSTAL_VOICE) {
3716 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3717 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3718 goto exit;
a7e76271 3719 }
95c6e9cb 3720
a7e76271
IM		 3721 /* out and in effects */
3722 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3723 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3724 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3725 changed = ca0132_effects_set(codec, nid, *valp);
3726 goto exit;
3727 }
3728
3729 /* mic boost */
3730 if (nid == spec->input_pins[0]) {
3731 spec->cur_mic_boost = *valp;
3732
3733 /* Mic boost does not apply to Digital Mic */
3734 if (spec->cur_mic_type != DIGITAL_MIC)
3735 changed = ca0132_mic_boost_set(codec, *valp);
3736 goto exit;
3737 }
95c6e9cb 3738
a7e76271 3739exit:
95c6e9cb 3740 snd_hda_power_down(codec);
a7e76271 3741 return changed;
95c6e9cb
IM		 3742}
3743
a7e76271
IM		 3744/*
3745 * Volume related
3746 */
3747static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3748 struct snd_ctl_elem_info *uinfo)
3749{
3750 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3751 struct ca0132_spec *spec = codec->spec;
3752 hda_nid_t nid = get_amp_nid(kcontrol);
3753 int ch = get_amp_channels(kcontrol);
3754 int dir = get_amp_direction(kcontrol);
3755 unsigned long pval;
3756 int err;
3757
3758 switch (nid) {
3759 case VNID_SPK:
3760 /* follow shared_out info */
3761 nid = spec->shared_out_nid;
3762 mutex_lock(&codec->control_mutex);
3763 pval = kcontrol->private_value;
3764 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3765 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3766 kcontrol->private_value = pval;
3767 mutex_unlock(&codec->control_mutex);
3768 break;
3769 case VNID_MIC:
3770 /* follow shared_mic info */
3771 nid = spec->shared_mic_nid;
3772 mutex_lock(&codec->control_mutex);
3773 pval = kcontrol->private_value;
3774 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3775 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3776 kcontrol->private_value = pval;
3777 mutex_unlock(&codec->control_mutex);
3778 break;
3779 default:
3780 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3781 }
3782 return err;
3783}
3784
3785static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3786 struct snd_ctl_elem_value *ucontrol)
3787{
3788 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3789 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3790 hda_nid_t nid = get_amp_nid(kcontrol);
3791 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3792 long *valp = ucontrol->value.integer.value;
3793
a7e76271
IM		 3794 /* store the left and right volume */
3795 if (ch & 1) {
3796 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3797 valp++;
3798 }
3799 if (ch & 2) {
3800 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3801 valp++;
3802 }
95c6e9cb
IM		 3803 return 0;
3804}
3805
a7e76271 3806static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3807 struct snd_ctl_elem_value *ucontrol)
3808{
3809 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3810 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3811 hda_nid_t nid = get_amp_nid(kcontrol);
3812 int ch = get_amp_channels(kcontrol);
95c6e9cb 3813 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3814 hda_nid_t shared_nid = 0;
3815 bool effective;
3816 int changed = 1;
3817
3818 /* store the left and right volume */
3819 if (ch & 1) {
3820 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3821 valp++;
3822 }
3823 if (ch & 2) {
3824 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3825 valp++;
3826 }
95c6e9cb 3827
a7e76271
IM		 3828 /* if effective conditions, then update hw immediately. */
3829 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3830 if (effective) {
3831 int dir = get_amp_direction(kcontrol);
3832 unsigned long pval;
3833
3834 snd_hda_power_up(codec);
3835 mutex_lock(&codec->control_mutex);
3836 pval = kcontrol->private_value;
3837 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3838 0, dir);
3839 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3840 kcontrol->private_value = pval;
3841 mutex_unlock(&codec->control_mutex);
3842 snd_hda_power_down(codec);
3843 }
95c6e9cb 3844
a7e76271 3845 return changed;
95c6e9cb
IM		 3846}
3847
a7e76271
IM		 3848static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3849 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3850{
a7e76271
IM		 3851 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3852 struct ca0132_spec *spec = codec->spec;
3853 hda_nid_t nid = get_amp_nid(kcontrol);
3854 int ch = get_amp_channels(kcontrol);
3855 int dir = get_amp_direction(kcontrol);
3856 unsigned long pval;
3857 int err;
3858
3859 switch (nid) {
3860 case VNID_SPK:
3861 /* follow shared_out tlv */
3862 nid = spec->shared_out_nid;
3863 mutex_lock(&codec->control_mutex);
3864 pval = kcontrol->private_value;
3865 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3866 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3867 kcontrol->private_value = pval;
3868 mutex_unlock(&codec->control_mutex);
3869 break;
3870 case VNID_MIC:
3871 /* follow shared_mic tlv */
3872 nid = spec->shared_mic_nid;
3873 mutex_lock(&codec->control_mutex);
3874 pval = kcontrol->private_value;
3875 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3876 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3877 kcontrol->private_value = pval;
3878 mutex_unlock(&codec->control_mutex);
3879 break;
3880 default:
3881 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3882 }
3883 return err;
95c6e9cb
IM		 3884}
3885
a7e76271
IM		 3886static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3887 const char *pfx, int dir)
95c6e9cb 3888{
a7e76271
IM		 3889 char namestr[44];
3890 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3891 struct snd_kcontrol_new knew =
a7e76271
IM		 3892 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3893 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3894 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3895}
3896
a7e76271 3897static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3898{
3899 struct snd_kcontrol_new knew =
a7e76271
IM		 3900 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3901 VOICEFX, 1, 0, HDA_INPUT);
3902 knew.info = ca0132_voicefx_info;
3903 knew.get = ca0132_voicefx_get;
3904 knew.put = ca0132_voicefx_put;
3905 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3906}
3907
a7e76271
IM		 3908/*
3909 * When changing Node IDs for Mixer Controls below, make sure to update
3910 * Node IDs in ca0132_config() as well.
3911 */
3912static struct snd_kcontrol_new ca0132_mixer[] = {
3913 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3914 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3915 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3916 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3917 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3918 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3919 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3920 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3921 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3922 0x12, 1, HDA_INPUT),
3923 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3924 VNID_HP_SEL, 1, HDA_OUTPUT),
3925 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3926 VNID_AMIC1_SEL, 1, HDA_INPUT),
3927 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3928 VNID_HP_ASEL, 1, HDA_OUTPUT),
3929 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3930 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3931 { } /* end */
3932};
3933
e90f29e4
IM		 3934static int ca0132_build_controls(struct hda_codec *codec)
3935{
3936 struct ca0132_spec *spec = codec->spec;
3937 int i, num_fx;
3938 int err = 0;
3939
3940 /* Add Mixer controls */
3941 for (i = 0; i < spec->num_mixers; i++) {
3942 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3943 if (err < 0)
3944 return err;
3945 }
3946
3947 /* Add in and out effects controls.
3948 * VoiceFX, PE and CrystalVoice are added separately.
3949 */
3950 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3951 for (i = 0; i < num_fx; i++) {
3952 err = add_fx_switch(codec, ca0132_effects[i].nid,
3953 ca0132_effects[i].name,
3954 ca0132_effects[i].direct);
3955 if (err < 0)
3956 return err;
3957 }
3958
3959 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3960 if (err < 0)
3961 return err;
3962
3963 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3964 if (err < 0)
3965 return err;
3966
3967 add_voicefx(codec);
3968
3969#ifdef ENABLE_TUNING_CONTROLS
3970 add_tuning_ctls(codec);
3971#endif
3972
3973 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3974 if (err < 0)
3975 return err;
3976
3977 if (spec->dig_out) {
3978 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3979 spec->dig_out);
3980 if (err < 0)
3981 return err;
3982 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
3983 if (err < 0)
3984 return err;
3985 /* spec->multiout.share_spdif = 1; */
3986 }
3987
3988 if (spec->dig_in) {
3989 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
3990 if (err < 0)
3991 return err;
3992 }
3993 return 0;
3994}
3995
a7e76271 3996/*
e90f29e4 3997 * PCM
a7e76271
IM		 3998 */
3999static struct hda_pcm_stream ca0132_pcm_analog_playback = {
4000 .substreams = 1,
4001 .channels_min = 2,
825315bc 4002 .channels_max = 6,
a7e76271 4003 .ops = {
a7e76271
IM		 4004 .prepare = ca0132_playback_pcm_prepare,
4005 .cleanup = ca0132_playback_pcm_cleanup
4006 },
4007};
4008
4009static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4010 .substreams = 1,
4011 .channels_min = 2,
4012 .channels_max = 2,
825315bc
IM		 4013 .ops = {
4014 .prepare = ca0132_capture_pcm_prepare,
4015 .cleanup = ca0132_capture_pcm_cleanup
4016 },
a7e76271
IM		 4017};
4018
4019static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4020 .substreams = 1,
4021 .channels_min = 2,
4022 .channels_max = 2,
4023 .ops = {
4024 .open = ca0132_dig_playback_pcm_open,
4025 .close = ca0132_dig_playback_pcm_close,
4026 .prepare = ca0132_dig_playback_pcm_prepare,
4027 .cleanup = ca0132_dig_playback_pcm_cleanup
4028 },
4029};
4030
4031static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4032 .substreams = 1,
4033 .channels_min = 2,
4034 .channels_max = 2,
4035};
4036
4037static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4038{
4039 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 4040 struct hda_pcm *info = spec->pcm_rec;
4041
4042 codec->pcm_info = info;
4043 codec->num_pcms = 0;
4044
4045 info->name = "CA0132 Analog";
4046 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4047 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4048 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4049 spec->multiout.max_channels;
4050 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4051 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271
IM		 4052 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4053 codec->num_pcms++;
4054
825315bc
IM		 4055 info++;
4056 info->name = "CA0132 Analog Mic-In2";
4057 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4058 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4059 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4060 codec->num_pcms++;
4061
4062 info++;
4063 info->name = "CA0132 What U Hear";
4064 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4065 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4066 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4067 codec->num_pcms++;
4068
a7e76271
IM		 4069 if (!spec->dig_out && !spec->dig_in)
4070 return 0;
4071
4072 info++;
4073 info->name = "CA0132 Digital";
4074 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4075 if (spec->dig_out) {
4076 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4077 ca0132_pcm_digital_playback;
4078 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4079 }
4080 if (spec->dig_in) {
4081 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4082 ca0132_pcm_digital_capture;
4083 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4084 }
4085 codec->num_pcms++;
95c6e9cb 4086
a7e76271 4087 return 0;
95c6e9cb
IM		 4088}
4089
441aa6a0
IM		 4090static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4091{
4092 if (pin) {
a0c041cb 4093 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 4094 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4095 snd_hda_codec_write(codec, pin, 0,
4096 AC_VERB_SET_AMP_GAIN_MUTE,
4097 AMP_OUT_UNMUTE);
4098 }
4099 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4100 snd_hda_codec_write(codec, dac, 0,
4101 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4102}
4103
4104static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4105{
4106 if (pin) {
a0c041cb 4107 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 4108 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4109 snd_hda_codec_write(codec, pin, 0,
4110 AC_VERB_SET_AMP_GAIN_MUTE,
4111 AMP_IN_UNMUTE(0));
4112 }
4113 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4114 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4115 AMP_IN_UNMUTE(0));
4116
4117 /* init to 0 dB and unmute. */
4118 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4119 HDA_AMP_VOLMASK, 0x5a);
4120 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4121 HDA_AMP_MUTE, 0);
4122 }
4123}
4124
a73d511c
IM		 4125static void ca0132_init_unsol(struct hda_codec *codec)
4126{
4127 snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP);
4128 snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1);
4129}
4130
5aaca44d
IM		 4131static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4132{
4133 unsigned int caps;
4134
4135 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4136 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4137 snd_hda_override_amp_caps(codec, nid, dir, caps);
4138}
4139
4140/*
4141 * Switch between Digital built-in mic and analog mic.
4142 */
4143static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4144{
4145 struct ca0132_spec *spec = codec->spec;
4146 unsigned int tmp;
4147 u8 val;
4148 unsigned int oldval;
4149
4150 snd_printdd(KERN_INFO "ca0132_set_dmic: enable=%d\n", enable);
4151
4152 oldval = stop_mic1(codec);
4153 ca0132_set_vipsource(codec, 0);
4154 if (enable) {
4155 /* set DMic input as 2-ch */
4156 tmp = FLOAT_TWO;
4157 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4158
4159 val = spec->dmic_ctl;
4160 val |= 0x80;
4161 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4162 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4163
4164 if (!(spec->dmic_ctl & 0x20))
4165 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4166 } else {
4167 /* set AMic input as mono */
4168 tmp = FLOAT_ONE;
4169 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4170
4171 val = spec->dmic_ctl;
4172 /* clear bit7 and bit5 to disable dmic */
4173 val &= 0x5f;
4174 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4175 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4176
4177 if (!(spec->dmic_ctl & 0x20))
4178 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4179 }
4180 ca0132_set_vipsource(codec, 1);
4181 resume_mic1(codec, oldval);
4182}
4183
4184/*
4185 * Initialization for Digital Mic.
4186 */
4187static void ca0132_init_dmic(struct hda_codec *codec)
4188{
4189 struct ca0132_spec *spec = codec->spec;
4190 u8 val;
4191
4192 /* Setup Digital Mic here, but don't enable.
4193 * Enable based on jack detect.
4194 */
4195
4196 /* MCLK uses MPIO1, set to enable.
4197 * Bit 2-0: MPIO select
4198 * Bit 3: set to disable
4199 * Bit 7-4: reserved
4200 */
4201 val = 0x01;
4202 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4203 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4204
4205 /* Data1 uses MPIO3. Data2 not use
4206 * Bit 2-0: Data1 MPIO select
4207 * Bit 3: set disable Data1
4208 * Bit 6-4: Data2 MPIO select
4209 * Bit 7: set disable Data2
4210 */
4211 val = 0x83;
4212 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4213 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4214
4215 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4216 * Bit 3-0: Channel mask
4217 * Bit 4: set for 48KHz, clear for 32KHz
4218 * Bit 5: mode
4219 * Bit 6: set to select Data2, clear for Data1
4220 * Bit 7: set to enable DMic, clear for AMic
4221 */
4222 val = 0x23;
4223 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4224 spec->dmic_ctl = val;
4225 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4226 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4227}
4228
4229/*
4230 * Initialization for Analog Mic 2
4231 */
4232static void ca0132_init_analog_mic2(struct hda_codec *codec)
4233{
4234 struct ca0132_spec *spec = codec->spec;
4235
4236 mutex_lock(&spec->chipio_mutex);
4237 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4238 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4239 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4240 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4241 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4242 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4243 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4244 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4245 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4246 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4247 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4248 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4249 mutex_unlock(&spec->chipio_mutex);
4250}
4251
4252static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4253{
4254 struct ca0132_spec *spec = codec->spec;
4255 int i;
4256 hda_nid_t nid;
4257
4258 snd_printdd(KERN_INFO "ca0132_refresh_widget_caps.\n");
4259 nid = codec->start_nid;
4260 for (i = 0; i < codec->num_nodes; i++, nid++)
4261 codec->wcaps[i] = snd_hda_param_read(codec, nid,
4262 AC_PAR_AUDIO_WIDGET_CAP);
4263
4264 for (i = 0; i < spec->multiout.num_dacs; i++)
4265 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4266
4267 for (i = 0; i < spec->num_outputs; i++)
4268 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4269
4270 for (i = 0; i < spec->num_inputs; i++) {
4271 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4272 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4273 }
4274}
4275
4276/*
4277 * Setup default parameters for DSP
4278 */
4279static void ca0132_setup_defaults(struct hda_codec *codec)
4280{
e8f1bd5d 4281 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4282 unsigned int tmp;
4283 int num_fx;
4284 int idx, i;
4285
e8f1bd5d 4286 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4287 return;
4288
4289 /* out, in effects + voicefx */
4290 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4291 for (idx = 0; idx < num_fx; idx++) {
4292 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4293 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4294 ca0132_effects[idx].reqs[i],
4295 ca0132_effects[idx].def_vals[i]);
4296 }
4297 }
4298
4299 /*remove DSP headroom*/
4300 tmp = FLOAT_ZERO;
4301 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4302
4303 /*set speaker EQ bypass attenuation*/
4304 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4305
4306 /* set AMic1 and AMic2 as mono mic */
4307 tmp = FLOAT_ONE;
4308 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4309 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4310
4311 /* set AMic1 as CrystalVoice input */
4312 tmp = FLOAT_ONE;
4313 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4314
4315 /* set WUH source */
4316 tmp = FLOAT_TWO;
4317 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4318}
4319
4320/*
4321 * Initialization of flags in chip
4322 */
4323static void ca0132_init_flags(struct hda_codec *codec)
4324{
4325 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4326 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4327 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4328 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4329 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4330 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4331}
4332
4333/*
4334 * Initialization of parameters in chip
4335 */
4336static void ca0132_init_params(struct hda_codec *codec)
4337{
4338 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4339 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4340}
95c6e9cb 4341
e90f29e4
IM		 4342static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4343{
4344 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4345 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4346 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4347 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4348 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4349 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4350
406261ce
IM		 4351 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4352 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 4353 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4354}
4355
4356static bool ca0132_download_dsp_images(struct hda_codec *codec)
4357{
4358 bool dsp_loaded = false;
4359 const struct dsp_image_seg *dsp_os_image;
15e4ba66 4360 const struct firmware *fw_entry;
e90f29e4 4361
15e4ba66 4362 if (request_firmware(&fw_entry, EFX_FILE, codec->bus->card->dev) != 0)
e90f29e4
IM		 4363 return false;
4364
15e4ba66 4365 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500
DR		 4366 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4367 pr_err("ca0132 dspload_image failed.\n");
4368 goto exit_download;
4369 }
4370
e90f29e4
IM		 4371 dsp_loaded = dspload_wait_loaded(codec);
4372
d1d28500 4373exit_download:
15e4ba66
TI		 4374 release_firmware(fw_entry);
4375
e90f29e4
IM		 4376 return dsp_loaded;
4377}
4378
4379static void ca0132_download_dsp(struct hda_codec *codec)
4380{
4381 struct ca0132_spec *spec = codec->spec;
4382
9a0869f4
TI		 4383#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4384 return; /* NOP */
4385#endif
e90f29e4 4386
b714a710
DR		 4387 chipio_enable_clocks(codec);
4388 spec->dsp_state = DSP_DOWNLOADING;
4389 if (!ca0132_download_dsp_images(codec))
4390 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4391 else
4392 spec->dsp_state = DSP_DOWNLOADED;
e90f29e4
IM		 4393
4394 if (spec->dsp_state == DSP_DOWNLOADED)
4395 ca0132_set_dsp_msr(codec, true);
4396}
4397
e90f29e4
IM		 4398static void ca0132_process_dsp_response(struct hda_codec *codec)
4399{
4400 struct ca0132_spec *spec = codec->spec;
4401
4402 snd_printdd(KERN_INFO "ca0132_process_dsp_response\n");
4403 if (spec->wait_scp) {
4404 if (dspio_get_response_data(codec) >= 0)
4405 spec->wait_scp = 0;
4406 }
4407
4408 dspio_clear_response_queue(codec);
4409}
4410
4411static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res)
4412{
993884f6 4413 struct ca0132_spec *spec = codec->spec;
e90f29e4
IM		 4414
4415 if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) {
4416 ca0132_process_dsp_response(codec);
4417 } else {
4418 res = snd_hda_jack_get_action(codec,
4419 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f);
4420
4421 snd_printdd(KERN_INFO "snd_hda_jack_get_action: 0x%x\n", res);
4422
4423 switch (res) {
4424 case UNSOL_TAG_HP:
993884f6
CCC		 4425 /* Delay enabling the HP amp, to let the mic-detection
4426 * state machine run.
4427 */
4428 cancel_delayed_work_sync(&spec->unsol_hp_work);
4429 queue_delayed_work(codec->bus->workq,
4430 &spec->unsol_hp_work,
4431 msecs_to_jiffies(500));
e90f29e4
IM		 4432 break;
4433 case UNSOL_TAG_AMIC1:
4434 ca0132_select_mic(codec);
4435 snd_hda_jack_report_sync(codec);
4436 break;
4437 default:
4438 break;
4439 }
4440 }
4441}
4442
5aaca44d
IM		 4443/*
4444 * Verbs tables.
4445 */
4446
4447/* Sends before DSP download. */
4448static struct hda_verb ca0132_base_init_verbs[] = {
4449 /*enable ct extension*/
4450 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4451 /*enable DSP node unsol, needed for DSP download*/
4452 {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
4453 {}
4454};
4455
4456/* Send at exit. */
4457static struct hda_verb ca0132_base_exit_verbs[] = {
4458 /*set afg to D3*/
4459 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4460 /*disable ct extension*/
4461 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4462 {}
4463};
4464
4465/* Other verbs tables. Sends after DSP download. */
4466static struct hda_verb ca0132_init_verbs0[] = {
4467 /* chip init verbs */
4468 {0x15, 0x70D, 0xF0},
4469 {0x15, 0x70E, 0xFE},
4470 {0x15, 0x707, 0x75},
4471 {0x15, 0x707, 0xD3},
4472 {0x15, 0x707, 0x09},
4473 {0x15, 0x707, 0x53},
4474 {0x15, 0x707, 0xD4},
4475 {0x15, 0x707, 0xEF},
4476 {0x15, 0x707, 0x75},
4477 {0x15, 0x707, 0xD3},
4478 {0x15, 0x707, 0x09},
4479 {0x15, 0x707, 0x02},
4480 {0x15, 0x707, 0x37},
4481 {0x15, 0x707, 0x78},
4482 {0x15, 0x53C, 0xCE},
4483 {0x15, 0x575, 0xC9},
4484 {0x15, 0x53D, 0xCE},
4485 {0x15, 0x5B7, 0xC9},
4486 {0x15, 0x70D, 0xE8},
4487 {0x15, 0x70E, 0xFE},
4488 {0x15, 0x707, 0x02},
4489 {0x15, 0x707, 0x68},
4490 {0x15, 0x707, 0x62},
4491 {0x15, 0x53A, 0xCE},
4492 {0x15, 0x546, 0xC9},
4493 {0x15, 0x53B, 0xCE},
4494 {0x15, 0x5E8, 0xC9},
4495 {0x15, 0x717, 0x0D},
4496 {0x15, 0x718, 0x20},
4497 {}
4498};
4499
4500static struct hda_verb ca0132_init_verbs1[] = {
4501 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4502 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4503 /* config EAPD */
4504 {0x0b, 0x78D, 0x00},
4505 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4506 /*{0x10, 0x78D, 0x02},*/
4507 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4508 {}
4509};
4510
95c6e9cb
IM		 4511static void ca0132_init_chip(struct hda_codec *codec)
4512{
4513 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4514 int num_fx;
4515 int i;
4516 unsigned int on;
95c6e9cb
IM		 4517
4518 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 4519
4520 spec->cur_out_type = SPEAKER_OUT;
4521 spec->cur_mic_type = DIGITAL_MIC;
4522 spec->cur_mic_boost = 0;
4523
4524 for (i = 0; i < VNODES_COUNT; i++) {
4525 spec->vnode_lvol[i] = 0x5a;
4526 spec->vnode_rvol[i] = 0x5a;
4527 spec->vnode_lswitch[i] = 0;
4528 spec->vnode_rswitch[i] = 0;
4529 }
4530
4531 /*
4532 * Default states for effects are in ca0132_effects[].
4533 */
4534 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4535 for (i = 0; i < num_fx; i++) {
4536 on = (unsigned int)ca0132_effects[i].reqs[0];
4537 spec->effects_switch[i] = on ? 1 : 0;
4538 }
4539
4540 spec->voicefx_val = 0;
4541 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4542 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4543
44f0c978
IM		 4544#ifdef ENABLE_TUNING_CONTROLS
4545 ca0132_init_tuning_defaults(codec);
4546#endif
95c6e9cb
IM		 4547}
4548
4549static void ca0132_exit_chip(struct hda_codec *codec)
4550{
4551 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 4552
4553 if (dspload_is_loaded(codec))
4554 dsp_reset(codec);
95c6e9cb
IM		 4555}
4556
4557static int ca0132_init(struct hda_codec *codec)
4558{
4559 struct ca0132_spec *spec = codec->spec;
4560 struct auto_pin_cfg *cfg = &spec->autocfg;
4561 int i;
4562
5aaca44d 4563 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 4564 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d
IM		 4565
4566 snd_hda_power_up(codec);
4567
4568 ca0132_init_params(codec);
4569 ca0132_init_flags(codec);
4570 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf 4571 ca0132_download_dsp(codec);
5aaca44d
IM		 4572 ca0132_refresh_widget_caps(codec);
4573 ca0132_setup_defaults(codec);
4574 ca0132_init_analog_mic2(codec);
4575 ca0132_init_dmic(codec);
4576
4577 for (i = 0; i < spec->num_outputs; i++)
4578 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4579
95c6e9cb
IM		 4580 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4581
4582 for (i = 0; i < spec->num_inputs; i++)
4583 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4584
4585 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4586
5aaca44d
IM		 4587 for (i = 0; i < spec->num_init_verbs; i++)
4588 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4589
a73d511c
IM		 4590 ca0132_init_unsol(codec);
4591
5aaca44d
IM		 4592 ca0132_select_out(codec);
4593 ca0132_select_mic(codec);
4594
a73d511c
IM		 4595 snd_hda_jack_report_sync(codec);
4596
5aaca44d 4597 snd_hda_power_down(codec);
95c6e9cb
IM		 4598
4599 return 0;
4600}
4601
95c6e9cb
IM		 4602static void ca0132_free(struct hda_codec *codec)
4603{
5aaca44d
IM		 4604 struct ca0132_spec *spec = codec->spec;
4605
993884f6 4606 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d
IM		 4607 snd_hda_power_up(codec);
4608 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4609 ca0132_exit_chip(codec);
5aaca44d 4610 snd_hda_power_down(codec);
95c6e9cb
IM		 4611 kfree(codec->spec);
4612}
4613
4614static struct hda_codec_ops ca0132_patch_ops = {
4615 .build_controls = ca0132_build_controls,
4616 .build_pcms = ca0132_build_pcms,
4617 .init = ca0132_init,
4618 .free = ca0132_free,
a73d511c 4619 .unsol_event = ca0132_unsol_event,
95c6e9cb
IM		 4620};
4621
441aa6a0
IM		 4622static void ca0132_config(struct hda_codec *codec)
4623{
4624 struct ca0132_spec *spec = codec->spec;
4625 struct auto_pin_cfg *cfg = &spec->autocfg;
4626
4627 spec->dacs[0] = 0x2;
4628 spec->dacs[1] = 0x3;
4629 spec->dacs[2] = 0x4;
4630
4631 spec->multiout.dac_nids = spec->dacs;
4632 spec->multiout.num_dacs = 3;
4633 spec->multiout.max_channels = 2;
4634
4635 spec->num_outputs = 2;
4636 spec->out_pins[0] = 0x0b; /* speaker out */
4637 spec->out_pins[1] = 0x10; /* headphone out */
4638 spec->shared_out_nid = 0x2;
4639
4640 spec->num_inputs = 3;
4641 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4642 spec->adcs[1] = 0x8; /* analog mic2 */
4643 spec->adcs[2] = 0xa; /* what u hear */
4644 spec->shared_mic_nid = 0x7;
4645
4646 spec->input_pins[0] = 0x12;
4647 spec->input_pins[1] = 0x11;
4648 spec->input_pins[2] = 0x13;
4649
4650 /* SPDIF I/O */
4651 spec->dig_out = 0x05;
4652 spec->multiout.dig_out_nid = spec->dig_out;
4653 cfg->dig_out_pins[0] = 0x0c;
4654 cfg->dig_outs = 1;
4655 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4656 spec->dig_in = 0x09;
4657 cfg->dig_in_pin = 0x0e;
4658 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4659}
4660
95c6e9cb
IM		 4661static int patch_ca0132(struct hda_codec *codec)
4662{
4663 struct ca0132_spec *spec;
a73d511c 4664 int err;
95c6e9cb
IM		 4665
4666 snd_printdd("patch_ca0132\n");
4667
4668 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4669 if (!spec)
4670 return -ENOMEM;
4671 codec->spec = spec;
993884f6 4672 spec->codec = codec;
95c6e9cb 4673
a7e76271
IM		 4674 spec->num_mixers = 1;
4675 spec->mixers[0] = ca0132_mixer;
4676
5aaca44d
IM		 4677 spec->base_init_verbs = ca0132_base_init_verbs;
4678 spec->base_exit_verbs = ca0132_base_exit_verbs;
4679 spec->init_verbs[0] = ca0132_init_verbs0;
4680 spec->init_verbs[1] = ca0132_init_verbs1;
4681 spec->num_init_verbs = 2;
4682
993884f6
CCC		 4683 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4684
95c6e9cb
IM		 4685 ca0132_init_chip(codec);
4686
4687 ca0132_config(codec);
4688
a73d511c
IM		 4689 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4690 if (err < 0)
4691 return err;
4692
95c6e9cb
IM		 4693 codec->patch_ops = ca0132_patch_ops;
4694
4695 return 0;
4696}
4697
4698/*
4699 * patch entries
4700 */
4701static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4702 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4703 {} /* terminator */
4704};
4705
4706MODULE_ALIAS("snd-hda-codec-id:11020011");
4707
4708MODULE_LICENSE("GPL");
406261ce 4709MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb
IM		 4710
4711static struct hda_codec_preset_list ca0132_list = {
4712 .preset = snd_hda_preset_ca0132,
4713 .owner = THIS_MODULE,
4714};
4715
4716static int __init patch_ca0132_init(void)
4717{
4718 return snd_hda_add_codec_preset(&ca0132_list);
4719}
4720
4721static void __exit patch_ca0132_exit(void)
4722{
4723 snd_hda_delete_codec_preset(&ca0132_list);
4724}
4725
4726module_init(patch_ca0132_init)
4727module_exit(patch_ca0132_exit)
Linux 6.x block layer and io_uring tree(s)