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ALSA: usb: add UAC3 BADD profiles support
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
95c6e9cb
IM		 31#include <sound/core.h>
32#include "hda_codec.h"
33#include "hda_local.h"
128bc4ba 34#include "hda_auto_parser.h"
5aaca44d 35#include "hda_jack.h"
95c6e9cb 36
bcd109c0
IM		 37#include "ca0132_regs.h"
38
ef6b2ead
IM		 39/* Enable this to see controls for tuning purpose. */
40/*#define ENABLE_TUNING_CONTROLS*/
41
8e142e9e
TS		 42#ifdef ENABLE_TUNING_CONTROLS
43#include <sound/tlv.h>
44#endif
45
ef6b2ead
IM		 46#define FLOAT_ZERO 0x00000000
47#define FLOAT_ONE 0x3f800000
48#define FLOAT_TWO 0x40000000
49#define FLOAT_MINUS_5 0xc0a00000
50
ef6b2ead
IM		 51#define UNSOL_TAG_DSP 0x16
52
4aa3bb0c
IM		 53#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
54#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
55
56#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
57#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
58#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
59
60#define MASTERCONTROL 0x80
ef6b2ead
IM		 61#define MASTERCONTROL_ALLOC_DMA_CHAN 10
62#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 63
95c6e9cb
IM		 64#define WIDGET_CHIP_CTRL 0x15
65#define WIDGET_DSP_CTRL 0x16
66
4aa3bb0c
IM		 67#define MEM_CONNID_MICIN1 3
68#define MEM_CONNID_MICIN2 5
69#define MEM_CONNID_MICOUT1 12
70#define MEM_CONNID_MICOUT2 14
71#define MEM_CONNID_WUH 10
72#define MEM_CONNID_DSP 16
73#define MEM_CONNID_DMIC 100
74
75#define SCP_SET 0
76#define SCP_GET 1
77
01ef7dbf
IM		 78#define EFX_FILE "ctefx.bin"
79
24f3cede 80#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 81MODULE_FIRMWARE(EFX_FILE);
7a527ede 82#endif
01ef7dbf 83
ef6b2ead
IM		 84static char *dirstr[2] = { "Playback", "Capture" };
85
86enum {
87 SPEAKER_OUT,
88 HEADPHONE_OUT
89};
90
91enum {
92 DIGITAL_MIC,
93 LINE_MIC_IN
94};
95
96enum {
97#define VNODE_START_NID 0x80
98 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
99 VNID_MIC,
100 VNID_HP_SEL,
101 VNID_AMIC1_SEL,
102 VNID_HP_ASEL,
103 VNID_AMIC1_ASEL,
104 VNODE_END_NID,
105#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
106
107#define EFFECT_START_NID 0x90
108#define OUT_EFFECT_START_NID EFFECT_START_NID
109 SURROUND = OUT_EFFECT_START_NID,
110 CRYSTALIZER,
111 DIALOG_PLUS,
112 SMART_VOLUME,
113 X_BASS,
114 EQUALIZER,
115 OUT_EFFECT_END_NID,
116#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
117
118#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
119 ECHO_CANCELLATION = IN_EFFECT_START_NID,
120 VOICE_FOCUS,
121 MIC_SVM,
122 NOISE_REDUCTION,
123 IN_EFFECT_END_NID,
124#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
125
126 VOICEFX = IN_EFFECT_END_NID,
127 PLAY_ENHANCEMENT,
128 CRYSTAL_VOICE,
129 EFFECT_END_NID
130#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
131};
132
133/* Effects values size*/
134#define EFFECT_VALS_MAX_COUNT 12
135
e8412ca4
DR		 136/* Latency introduced by DSP blocks in milliseconds. */
137#define DSP_CAPTURE_INIT_LATENCY 0
138#define DSP_CRYSTAL_VOICE_LATENCY 124
139#define DSP_PLAYBACK_INIT_LATENCY 13
140#define DSP_PLAY_ENHANCEMENT_LATENCY 30
141#define DSP_SPEAKER_OUT_LATENCY 7
142
ef6b2ead 143struct ct_effect {
975cc02a 144 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 145 hda_nid_t nid;
146 int mid; /*effect module ID*/
147 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
148 int direct; /* 0:output; 1:input*/
149 int params; /* number of default non-on/off params */
150 /*effect default values, 1st is on/off. */
151 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
152};
153
154#define EFX_DIR_OUT 0
155#define EFX_DIR_IN 1
156
157static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
158 { .name = "Surround",
159 .nid = SURROUND,
160 .mid = 0x96,
161 .reqs = {0, 1},
162 .direct = EFX_DIR_OUT,
163 .params = 1,
164 .def_vals = {0x3F800000, 0x3F2B851F}
165 },
166 { .name = "Crystalizer",
167 .nid = CRYSTALIZER,
168 .mid = 0x96,
169 .reqs = {7, 8},
170 .direct = EFX_DIR_OUT,
171 .params = 1,
172 .def_vals = {0x3F800000, 0x3F266666}
173 },
174 { .name = "Dialog Plus",
175 .nid = DIALOG_PLUS,
176 .mid = 0x96,
177 .reqs = {2, 3},
178 .direct = EFX_DIR_OUT,
179 .params = 1,
180 .def_vals = {0x00000000, 0x3F000000}
181 },
182 { .name = "Smart Volume",
183 .nid = SMART_VOLUME,
184 .mid = 0x96,
185 .reqs = {4, 5, 6},
186 .direct = EFX_DIR_OUT,
187 .params = 2,
188 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
189 },
190 { .name = "X-Bass",
191 .nid = X_BASS,
192 .mid = 0x96,
193 .reqs = {24, 23, 25},
194 .direct = EFX_DIR_OUT,
195 .params = 2,
196 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
197 },
198 { .name = "Equalizer",
199 .nid = EQUALIZER,
200 .mid = 0x96,
201 .reqs = {9, 10, 11, 12, 13, 14,
202 15, 16, 17, 18, 19, 20},
203 .direct = EFX_DIR_OUT,
204 .params = 11,
205 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
206 0x00000000, 0x00000000, 0x00000000, 0x00000000,
207 0x00000000, 0x00000000, 0x00000000, 0x00000000}
208 },
209 { .name = "Echo Cancellation",
210 .nid = ECHO_CANCELLATION,
211 .mid = 0x95,
212 .reqs = {0, 1, 2, 3},
213 .direct = EFX_DIR_IN,
214 .params = 3,
215 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
216 },
217 { .name = "Voice Focus",
218 .nid = VOICE_FOCUS,
219 .mid = 0x95,
220 .reqs = {6, 7, 8, 9},
221 .direct = EFX_DIR_IN,
222 .params = 3,
223 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
224 },
225 { .name = "Mic SVM",
226 .nid = MIC_SVM,
227 .mid = 0x95,
228 .reqs = {44, 45},
229 .direct = EFX_DIR_IN,
230 .params = 1,
231 .def_vals = {0x00000000, 0x3F3D70A4}
232 },
233 { .name = "Noise Reduction",
234 .nid = NOISE_REDUCTION,
235 .mid = 0x95,
236 .reqs = {4, 5},
237 .direct = EFX_DIR_IN,
238 .params = 1,
239 .def_vals = {0x3F800000, 0x3F000000}
240 },
241 { .name = "VoiceFX",
242 .nid = VOICEFX,
243 .mid = 0x95,
244 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
245 .direct = EFX_DIR_IN,
246 .params = 8,
247 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
248 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
249 0x00000000}
250 }
251};
252
253/* Tuning controls */
254#ifdef ENABLE_TUNING_CONTROLS
255
256enum {
257#define TUNING_CTL_START_NID 0xC0
258 WEDGE_ANGLE = TUNING_CTL_START_NID,
259 SVM_LEVEL,
260 EQUALIZER_BAND_0,
261 EQUALIZER_BAND_1,
262 EQUALIZER_BAND_2,
263 EQUALIZER_BAND_3,
264 EQUALIZER_BAND_4,
265 EQUALIZER_BAND_5,
266 EQUALIZER_BAND_6,
267 EQUALIZER_BAND_7,
268 EQUALIZER_BAND_8,
269 EQUALIZER_BAND_9,
270 TUNING_CTL_END_NID
271#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
272};
273
274struct ct_tuning_ctl {
975cc02a 275 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 276 hda_nid_t parent_nid;
277 hda_nid_t nid;
278 int mid; /*effect module ID*/
279 int req; /*effect module request*/
280 int direct; /* 0:output; 1:input*/
281 unsigned int def_val;/*effect default values*/
282};
283
284static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
285 { .name = "Wedge Angle",
286 .parent_nid = VOICE_FOCUS,
287 .nid = WEDGE_ANGLE,
288 .mid = 0x95,
289 .req = 8,
290 .direct = EFX_DIR_IN,
291 .def_val = 0x41F00000
292 },
293 { .name = "SVM Level",
294 .parent_nid = MIC_SVM,
295 .nid = SVM_LEVEL,
296 .mid = 0x95,
297 .req = 45,
298 .direct = EFX_DIR_IN,
299 .def_val = 0x3F3D70A4
300 },
301 { .name = "EQ Band0",
302 .parent_nid = EQUALIZER,
303 .nid = EQUALIZER_BAND_0,
304 .mid = 0x96,
305 .req = 11,
306 .direct = EFX_DIR_OUT,
307 .def_val = 0x00000000
308 },
309 { .name = "EQ Band1",
310 .parent_nid = EQUALIZER,
311 .nid = EQUALIZER_BAND_1,
312 .mid = 0x96,
313 .req = 12,
314 .direct = EFX_DIR_OUT,
315 .def_val = 0x00000000
316 },
317 { .name = "EQ Band2",
318 .parent_nid = EQUALIZER,
319 .nid = EQUALIZER_BAND_2,
320 .mid = 0x96,
321 .req = 13,
322 .direct = EFX_DIR_OUT,
323 .def_val = 0x00000000
324 },
325 { .name = "EQ Band3",
326 .parent_nid = EQUALIZER,
327 .nid = EQUALIZER_BAND_3,
328 .mid = 0x96,
329 .req = 14,
330 .direct = EFX_DIR_OUT,
331 .def_val = 0x00000000
332 },
333 { .name = "EQ Band4",
334 .parent_nid = EQUALIZER,
335 .nid = EQUALIZER_BAND_4,
336 .mid = 0x96,
337 .req = 15,
338 .direct = EFX_DIR_OUT,
339 .def_val = 0x00000000
340 },
341 { .name = "EQ Band5",
342 .parent_nid = EQUALIZER,
343 .nid = EQUALIZER_BAND_5,
344 .mid = 0x96,
345 .req = 16,
346 .direct = EFX_DIR_OUT,
347 .def_val = 0x00000000
348 },
349 { .name = "EQ Band6",
350 .parent_nid = EQUALIZER,
351 .nid = EQUALIZER_BAND_6,
352 .mid = 0x96,
353 .req = 17,
354 .direct = EFX_DIR_OUT,
355 .def_val = 0x00000000
356 },
357 { .name = "EQ Band7",
358 .parent_nid = EQUALIZER,
359 .nid = EQUALIZER_BAND_7,
360 .mid = 0x96,
361 .req = 18,
362 .direct = EFX_DIR_OUT,
363 .def_val = 0x00000000
364 },
365 { .name = "EQ Band8",
366 .parent_nid = EQUALIZER,
367 .nid = EQUALIZER_BAND_8,
368 .mid = 0x96,
369 .req = 19,
370 .direct = EFX_DIR_OUT,
371 .def_val = 0x00000000
372 },
373 { .name = "EQ Band9",
374 .parent_nid = EQUALIZER,
375 .nid = EQUALIZER_BAND_9,
376 .mid = 0x96,
377 .req = 20,
378 .direct = EFX_DIR_OUT,
379 .def_val = 0x00000000
380 }
381};
382#endif
383
384/* Voice FX Presets */
385#define VOICEFX_MAX_PARAM_COUNT 9
386
387struct ct_voicefx {
388 char *name;
389 hda_nid_t nid;
390 int mid;
391 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
392};
393
394struct ct_voicefx_preset {
395 char *name; /*preset name*/
396 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
397};
398
ccd7bd3d 399static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 400 .name = "VoiceFX Capture Switch",
401 .nid = VOICEFX,
402 .mid = 0x95,
403 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
404};
405
ccd7bd3d 406static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 407 { .name = "Neutral",
408 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
409 0x44FA0000, 0x3F800000, 0x3F800000,
410 0x3F800000, 0x00000000, 0x00000000 }
411 },
412 { .name = "Female2Male",
413 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
414 0x44FA0000, 0x3F19999A, 0x3F866666,
415 0x3F800000, 0x00000000, 0x00000000 }
416 },
417 { .name = "Male2Female",
418 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
419 0x450AC000, 0x4017AE14, 0x3F6B851F,
420 0x3F800000, 0x00000000, 0x00000000 }
421 },
422 { .name = "ScrappyKid",
423 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
424 0x44FA0000, 0x40400000, 0x3F28F5C3,
425 0x3F800000, 0x00000000, 0x00000000 }
426 },
427 { .name = "Elderly",
428 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
429 0x44E10000, 0x3FB33333, 0x3FB9999A,
430 0x3F800000, 0x3E3A2E43, 0x00000000 }
431 },
432 { .name = "Orc",
433 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
434 0x45098000, 0x3F266666, 0x3FC00000,
435 0x3F800000, 0x00000000, 0x00000000 }
436 },
437 { .name = "Elf",
438 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
439 0x45193000, 0x3F8E147B, 0x3F75C28F,
440 0x3F800000, 0x00000000, 0x00000000 }
441 },
442 { .name = "Dwarf",
443 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
444 0x45007000, 0x3F451EB8, 0x3F7851EC,
445 0x3F800000, 0x00000000, 0x00000000 }
446 },
447 { .name = "AlienBrute",
448 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
449 0x451F6000, 0x3F266666, 0x3FA7D945,
450 0x3F800000, 0x3CF5C28F, 0x00000000 }
451 },
452 { .name = "Robot",
453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
454 0x44FA0000, 0x3FB2718B, 0x3F800000,
455 0xBC07010E, 0x00000000, 0x00000000 }
456 },
457 { .name = "Marine",
458 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
459 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
460 0x3F0A3D71, 0x00000000, 0x00000000 }
461 },
462 { .name = "Emo",
463 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
464 0x44FA0000, 0x3F800000, 0x3F800000,
465 0x3E4CCCCD, 0x00000000, 0x00000000 }
466 },
467 { .name = "DeepVoice",
468 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
469 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
470 0x3F800000, 0x00000000, 0x00000000 }
471 },
472 { .name = "Munchkin",
473 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
474 0x44FA0000, 0x3F800000, 0x3F1A043C,
475 0x3F800000, 0x00000000, 0x00000000 }
476 }
477};
478
95c6e9cb
IM		 479enum hda_cmd_vendor_io {
480 /* for DspIO node */
481 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
482 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
483
484 VENDOR_DSPIO_STATUS = 0xF01,
485 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
486 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
487 VENDOR_DSPIO_DSP_INIT = 0x703,
488 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
489 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
490
491 /* for ChipIO node */
492 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
493 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
494 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
495 VENDOR_CHIPIO_DATA_LOW = 0x300,
496 VENDOR_CHIPIO_DATA_HIGH = 0x400,
497
498 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
499 VENDOR_CHIPIO_STATUS = 0xF01,
500 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
501 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
502
4aa3bb0c
IM		 503 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
504 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
505
95c6e9cb 506 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 507 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 508
509 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
510 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
511 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
512 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
513 VENDOR_CHIPIO_FLAG_SET = 0x70F,
514 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 515 VENDOR_CHIPIO_PARAM_SET = 0x710,
516 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 517
518 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
519 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
520 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
521 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
522
4aa3bb0c
IM		 523 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
524 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
525 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
526 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
527
528 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
529 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
530 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
531 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
532 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
533 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
534
535 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 536};
537
538/*
539 * Control flag IDs
540 */
541enum control_flag_id {
542 /* Connection manager stream setup is bypassed/enabled */
543 CONTROL_FLAG_C_MGR = 0,
544 /* DSP DMA is bypassed/enabled */
545 CONTROL_FLAG_DMA = 1,
546 /* 8051 'idle' mode is disabled/enabled */
547 CONTROL_FLAG_IDLE_ENABLE = 2,
548 /* Tracker for the SPDIF-in path is bypassed/enabled */
549 CONTROL_FLAG_TRACKER = 3,
550 /* DigitalOut to Spdif2Out connection is disabled/enabled */
551 CONTROL_FLAG_SPDIF2OUT = 4,
552 /* Digital Microphone is disabled/enabled */
553 CONTROL_FLAG_DMIC = 5,
554 /* ADC_B rate is 48 kHz/96 kHz */
555 CONTROL_FLAG_ADC_B_96KHZ = 6,
556 /* ADC_C rate is 48 kHz/96 kHz */
557 CONTROL_FLAG_ADC_C_96KHZ = 7,
558 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
559 CONTROL_FLAG_DAC_96KHZ = 8,
560 /* DSP rate is 48 kHz/96 kHz */
561 CONTROL_FLAG_DSP_96KHZ = 9,
562 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
563 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
564 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
565 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
566 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
567 CONTROL_FLAG_DECODE_LOOP = 12,
568 /* De-emphasis filter on DAC-1 disabled/enabled */
569 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
570 /* De-emphasis filter on DAC-2 disabled/enabled */
571 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
572 /* De-emphasis filter on DAC-3 disabled/enabled */
573 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
574 /* High-pass filter on ADC_B disabled/enabled */
575 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
576 /* High-pass filter on ADC_C disabled/enabled */
577 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
578 /* Common mode on Port_A disabled/enabled */
579 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
580 /* Common mode on Port_D disabled/enabled */
581 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
582 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
583 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
584 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 585 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 586 /* ASI rate is 48kHz/96kHz */
587 CONTROL_FLAG_ASI_96KHZ = 22,
588 /* DAC power settings able to control attached ports no/yes */
589 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
590 /* Clock Stop OK reporting is disabled/enabled */
591 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
592 /* Number of control flags */
593 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
594};
595
596/*
597 * Control parameter IDs
598 */
4aa3bb0c 599enum control_param_id {
ef6b2ead
IM		 600 /* 0: None, 1: Mic1In*/
601 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 602 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
603 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 604 /* Port A output stage gain setting to use when 16 Ohm output
605 * impedance is selected*/
606 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
607 /* Port D output stage gain setting to use when 16 Ohm output
608 * impedance is selected*/
609 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 610
611 /* Stream Control */
612
613 /* Select stream with the given ID */
614 CONTROL_PARAM_STREAM_ID = 24,
615 /* Source connection point for the selected stream */
616 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
617 /* Destination connection point for the selected stream */
618 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
619 /* Number of audio channels in the selected stream */
620 CONTROL_PARAM_STREAMS_CHANNELS = 27,
621 /*Enable control for the selected stream */
622 CONTROL_PARAM_STREAM_CONTROL = 28,
623
624 /* Connection Point Control */
625
626 /* Select connection point with the given ID */
627 CONTROL_PARAM_CONN_POINT_ID = 29,
628 /* Connection point sample rate */
629 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
630
631 /* Node Control */
632
633 /* Select HDA node with the given ID */
634 CONTROL_PARAM_NODE_ID = 31
635};
636
637/*
638 * Dsp Io Status codes
639 */
640enum hda_vendor_status_dspio {
641 /* Success */
642 VENDOR_STATUS_DSPIO_OK = 0x00,
643 /* Busy, unable to accept new command, the host must retry */
644 VENDOR_STATUS_DSPIO_BUSY = 0x01,
645 /* SCP command queue is full */
646 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
647 /* SCP response queue is empty */
648 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
649};
650
651/*
652 * Chip Io Status codes
653 */
654enum hda_vendor_status_chipio {
655 /* Success */
656 VENDOR_STATUS_CHIPIO_OK = 0x00,
657 /* Busy, unable to accept new command, the host must retry */
658 VENDOR_STATUS_CHIPIO_BUSY = 0x01
659};
660
661/*
662 * CA0132 sample rate
663 */
664enum ca0132_sample_rate {
665 SR_6_000 = 0x00,
666 SR_8_000 = 0x01,
667 SR_9_600 = 0x02,
668 SR_11_025 = 0x03,
669 SR_16_000 = 0x04,
670 SR_22_050 = 0x05,
671 SR_24_000 = 0x06,
672 SR_32_000 = 0x07,
673 SR_44_100 = 0x08,
674 SR_48_000 = 0x09,
675 SR_88_200 = 0x0A,
676 SR_96_000 = 0x0B,
677 SR_144_000 = 0x0C,
678 SR_176_400 = 0x0D,
679 SR_192_000 = 0x0E,
680 SR_384_000 = 0x0F,
681
682 SR_COUNT = 0x10,
683
684 SR_RATE_UNKNOWN = 0x1F
685};
686
01ef7dbf
IM		 687enum dsp_download_state {
688 DSP_DOWNLOAD_FAILED = -1,
689 DSP_DOWNLOAD_INIT = 0,
690 DSP_DOWNLOADING = 1,
691 DSP_DOWNLOADED = 2
692};
693
01ef7dbf
IM		 694/* retrieve parameters from hda format */
695#define get_hdafmt_chs(fmt) (fmt & 0xf)
696#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
697#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
698#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
699
700/*
701 * CA0132 specific
702 */
703
704struct ca0132_spec {
a7e76271
IM		 705 struct snd_kcontrol_new *mixers[5];
706 unsigned int num_mixers;
5aaca44d
IM		 707 const struct hda_verb *base_init_verbs;
708 const struct hda_verb *base_exit_verbs;
d5c016b5
GM		 709 const struct hda_verb *chip_init_verbs;
710 struct hda_verb *spec_init_verbs;
01ef7dbf 711 struct auto_pin_cfg autocfg;
5aaca44d
IM		 712
713 /* Nodes configurations */
01ef7dbf
IM		 714 struct hda_multi_out multiout;
715 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
716 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 717 unsigned int num_outputs;
01ef7dbf
IM		 718 hda_nid_t input_pins[AUTO_PIN_LAST];
719 hda_nid_t adcs[AUTO_PIN_LAST];
720 hda_nid_t dig_out;
721 hda_nid_t dig_in;
722 unsigned int num_inputs;
a7e76271
IM		 723 hda_nid_t shared_mic_nid;
724 hda_nid_t shared_out_nid;
d5c016b5
GM		 725 hda_nid_t unsol_tag_hp;
726 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 727
728 /* chip access */
729 struct mutex chipio_mutex; /* chip access mutex */
730 u32 curr_chip_addx;
731
732 /* DSP download related */
733 enum dsp_download_state dsp_state;
734 unsigned int dsp_stream_id;
735 unsigned int wait_scp;
736 unsigned int wait_scp_header;
737 unsigned int wait_num_data;
738 unsigned int scp_resp_header;
739 unsigned int scp_resp_data[4];
740 unsigned int scp_resp_count;
5aaca44d
IM		 741
742 /* mixer and effects related */
743 unsigned char dmic_ctl;
744 int cur_out_type;
745 int cur_mic_type;
746 long vnode_lvol[VNODES_COUNT];
747 long vnode_rvol[VNODES_COUNT];
748 long vnode_lswitch[VNODES_COUNT];
749 long vnode_rswitch[VNODES_COUNT];
750 long effects_switch[EFFECTS_COUNT];
751 long voicefx_val;
752 long cur_mic_boost;
44f0c978 753
993884f6
CCC		 754 struct hda_codec *codec;
755 struct delayed_work unsol_hp_work;
d5c016b5 756 int quirk;
993884f6 757
44f0c978
IM		 758#ifdef ENABLE_TUNING_CONTROLS
759 long cur_ctl_vals[TUNING_CTLS_COUNT];
760#endif
01ef7dbf
IM		 761};
762
d5c016b5
GM		 763/*
764 * CA0132 quirks table
765 */
766enum {
767 QUIRK_NONE,
768 QUIRK_ALIENWARE,
769};
770
fe14f39e
TI		 771static const struct hda_pintbl alienware_pincfgs[] = {
772 { 0x0b, 0x90170110 }, /* Builtin Speaker */
773 { 0x0c, 0x411111f0 }, /* N/A */
774 { 0x0d, 0x411111f0 }, /* N/A */
775 { 0x0e, 0x411111f0 }, /* N/A */
776 { 0x0f, 0x0321101f }, /* HP */
777 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
778 { 0x11, 0x03a11021 }, /* Mic */
779 { 0x12, 0xd5a30140 }, /* Builtin Mic */
780 { 0x13, 0x411111f0 }, /* N/A */
781 { 0x18, 0x411111f0 }, /* N/A */
782 {}
783};
784
d5c016b5 785static const struct snd_pci_quirk ca0132_quirks[] = {
5328e1ea
GM		 786 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
787 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 788 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
d5c016b5
GM		 789 {}
790};
791
01ef7dbf
IM		 792/*
793 * CA0132 codec access
794 */
399ae725 795static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 796 unsigned int verb, unsigned int parm, unsigned int *res)
797{
798 unsigned int response;
799 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
800 *res = response;
801
802 return ((response == -1) ? -1 : 0);
803}
804
805static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
806 unsigned short converter_format, unsigned int *res)
807{
808 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
809 converter_format & 0xffff, res);
810}
811
812static int codec_set_converter_stream_channel(struct hda_codec *codec,
813 hda_nid_t nid, unsigned char stream,
814 unsigned char channel, unsigned int *res)
815{
816 unsigned char converter_stream_channel = 0;
817
818 converter_stream_channel = (stream << 4) | (channel & 0x0f);
819 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
820 converter_stream_channel, res);
821}
822
823/* Chip access helper function */
824static int chipio_send(struct hda_codec *codec,
825 unsigned int reg,
826 unsigned int data)
827{
828 unsigned int res;
6d67530e 829 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 830
831 /* send bits of data specified by reg */
832 do {
833 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
834 reg, data);
835 if (res == VENDOR_STATUS_CHIPIO_OK)
836 return 0;
6d67530e
IM		 837 msleep(20);
838 } while (time_before(jiffies, timeout));
839
01ef7dbf
IM		 840 return -EIO;
841}
842
843/*
844 * Write chip address through the vendor widget -- NOT protected by the Mutex!
845 */
846static int chipio_write_address(struct hda_codec *codec,
847 unsigned int chip_addx)
848{
4861af80 849 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 850 int res;
851
4861af80
IM		 852 if (spec->curr_chip_addx == chip_addx)
853 return 0;
854
01ef7dbf
IM		 855 /* send low 16 bits of the address */
856 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
857 chip_addx & 0xffff);
858
859 if (res != -EIO) {
860 /* send high 16 bits of the address */
861 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
862 chip_addx >> 16);
863 }
864
d1600401 865 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 866
4861af80 867 return res;
01ef7dbf
IM		 868}
869
870/*
871 * Write data through the vendor widget -- NOT protected by the Mutex!
872 */
01ef7dbf
IM		 873static int chipio_write_data(struct hda_codec *codec, unsigned int data)
874{
5aaca44d 875 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 876 int res;
877
878 /* send low 16 bits of the data */
879 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
880
881 if (res != -EIO) {
882 /* send high 16 bits of the data */
883 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
884 data >> 16);
885 }
886
5aaca44d
IM		 887 /*If no error encountered, automatically increment the address
888 as per chip behaviour*/
889 spec->curr_chip_addx = (res != -EIO) ?
d1600401 890 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 891 return res;
892}
893
d5c21b88
IM		 894/*
895 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
896 */
01ef7dbf
IM		 897static int chipio_write_data_multiple(struct hda_codec *codec,
898 const u32 *data,
899 unsigned int count)
900{
901 int status = 0;
902
903 if (data == NULL) {
4e76a883 904 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 905 return -EINVAL;
906 }
907
908 while ((count-- != 0) && (status == 0))
909 status = chipio_write_data(codec, *data++);
910
911 return status;
912}
913
914
915/*
916 * Read data through the vendor widget -- NOT protected by the Mutex!
917 */
918static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
919{
5aaca44d 920 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 921 int res;
922
923 /* post read */
924 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
925
926 if (res != -EIO) {
927 /* read status */
928 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
929 }
930
931 if (res != -EIO) {
932 /* read data */
933 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
934 VENDOR_CHIPIO_HIC_READ_DATA,
935 0);
936 }
937
5aaca44d
IM		 938 /*If no error encountered, automatically increment the address
939 as per chip behaviour*/
940 spec->curr_chip_addx = (res != -EIO) ?
d1600401 941 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 942 return res;
943}
944
945/*
946 * Write given value to the given address through the chip I/O widget.
947 * protected by the Mutex
948 */
949static int chipio_write(struct hda_codec *codec,
950 unsigned int chip_addx, const unsigned int data)
951{
952 struct ca0132_spec *spec = codec->spec;
953 int err;
954
955 mutex_lock(&spec->chipio_mutex);
956
957 /* write the address, and if successful proceed to write data */
958 err = chipio_write_address(codec, chip_addx);
959 if (err < 0)
960 goto exit;
961
962 err = chipio_write_data(codec, data);
963 if (err < 0)
964 goto exit;
965
966exit:
967 mutex_unlock(&spec->chipio_mutex);
968 return err;
969}
970
d5c21b88
IM		 971/*
972 * Write multiple values to the given address through the chip I/O widget.
973 * protected by the Mutex
974 */
01ef7dbf
IM		 975static int chipio_write_multiple(struct hda_codec *codec,
976 u32 chip_addx,
977 const u32 *data,
978 unsigned int count)
979{
980 struct ca0132_spec *spec = codec->spec;
981 int status;
982
983 mutex_lock(&spec->chipio_mutex);
4861af80 984 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 985 if (status < 0)
986 goto error;
987
988 status = chipio_write_data_multiple(codec, data, count);
989error:
990 mutex_unlock(&spec->chipio_mutex);
991
992 return status;
993}
994
995/*
996 * Read the given address through the chip I/O widget
997 * protected by the Mutex
998 */
999static int chipio_read(struct hda_codec *codec,
1000 unsigned int chip_addx, unsigned int *data)
1001{
1002 struct ca0132_spec *spec = codec->spec;
1003 int err;
1004
1005 mutex_lock(&spec->chipio_mutex);
1006
1007 /* write the address, and if successful proceed to write data */
1008 err = chipio_write_address(codec, chip_addx);
1009 if (err < 0)
1010 goto exit;
1011
1012 err = chipio_read_data(codec, data);
1013 if (err < 0)
1014 goto exit;
1015
1016exit:
1017 mutex_unlock(&spec->chipio_mutex);
1018 return err;
1019}
1020
d5c21b88
IM		 1021/*
1022 * Set chip control flags through the chip I/O widget.
1023 */
01ef7dbf
IM		 1024static void chipio_set_control_flag(struct hda_codec *codec,
1025 enum control_flag_id flag_id,
1026 bool flag_state)
1027{
1028 unsigned int val;
1029 unsigned int flag_bit;
1030
1031 flag_bit = (flag_state ? 1 : 0);
1032 val = (flag_bit << 7) | (flag_id);
1033 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1034 VENDOR_CHIPIO_FLAG_SET, val);
1035}
1036
d5c21b88
IM		 1037/*
1038 * Set chip parameters through the chip I/O widget.
1039 */
01ef7dbf
IM		 1040static void chipio_set_control_param(struct hda_codec *codec,
1041 enum control_param_id param_id, int param_val)
1042{
1043 struct ca0132_spec *spec = codec->spec;
1044 int val;
1045
1046 if ((param_id < 32) && (param_val < 8)) {
1047 val = (param_val << 5) | (param_id);
1048 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1049 VENDOR_CHIPIO_PARAM_SET, val);
1050 } else {
1051 mutex_lock(&spec->chipio_mutex);
1052 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1053 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1054 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1055 param_id);
1056 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1057 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1058 param_val);
1059 }
1060 mutex_unlock(&spec->chipio_mutex);
1061 }
1062}
1063
d5c21b88
IM		 1064/*
1065 * Set sampling rate of the connection point.
1066 */
01ef7dbf
IM		 1067static void chipio_set_conn_rate(struct hda_codec *codec,
1068 int connid, enum ca0132_sample_rate rate)
1069{
1070 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1071 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1072 rate);
1073}
1074
d5c21b88
IM		 1075/*
1076 * Enable clocks.
1077 */
01ef7dbf
IM		 1078static void chipio_enable_clocks(struct hda_codec *codec)
1079{
1080 struct ca0132_spec *spec = codec->spec;
1081
1082 mutex_lock(&spec->chipio_mutex);
1083 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1084 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1085 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1086 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1087 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1088 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1089 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1090 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1091 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1092 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1093 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1094 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1095 mutex_unlock(&spec->chipio_mutex);
1096}
1097
1098/*
1099 * CA0132 DSP IO stuffs
1100 */
1101static int dspio_send(struct hda_codec *codec, unsigned int reg,
1102 unsigned int data)
1103{
b645d796 1104 int res;
6d67530e 1105 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1106
1107 /* send bits of data specified by reg to dsp */
1108 do {
1109 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1110 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1111 return res;
6d67530e
IM		 1112 msleep(20);
1113 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1114
1115 return -EIO;
1116}
1117
d5c21b88
IM		 1118/*
1119 * Wait for DSP to be ready for commands
1120 */
01ef7dbf
IM		 1121static void dspio_write_wait(struct hda_codec *codec)
1122{
4861af80
IM		 1123 int status;
1124 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1125
01ef7dbf 1126 do {
4861af80
IM		 1127 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1128 VENDOR_DSPIO_STATUS, 0);
1129 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1130 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1131 break;
1132 msleep(1);
1133 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1134}
1135
d5c21b88
IM		 1136/*
1137 * Write SCP data to DSP
1138 */
01ef7dbf
IM		 1139static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1140{
1141 struct ca0132_spec *spec = codec->spec;
1142 int status;
1143
1144 dspio_write_wait(codec);
1145
1146 mutex_lock(&spec->chipio_mutex);
1147 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1148 scp_data & 0xffff);
1149 if (status < 0)
1150 goto error;
1151
1152 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1153 scp_data >> 16);
1154 if (status < 0)
1155 goto error;
1156
1157 /* OK, now check if the write itself has executed*/
1158 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1159 VENDOR_DSPIO_STATUS, 0);
1160error:
1161 mutex_unlock(&spec->chipio_mutex);
1162
1163 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1164 -EIO : 0;
1165}
1166
d5c21b88
IM		 1167/*
1168 * Write multiple SCP data to DSP
1169 */
01ef7dbf
IM		 1170static int dspio_write_multiple(struct hda_codec *codec,
1171 unsigned int *buffer, unsigned int size)
1172{
1173 int status = 0;
1174 unsigned int count;
1175
a16fbb85 1176 if (buffer == NULL)
01ef7dbf
IM		 1177 return -EINVAL;
1178
1179 count = 0;
1180 while (count < size) {
1181 status = dspio_write(codec, *buffer++);
1182 if (status != 0)
1183 break;
1184 count++;
1185 }
1186
1187 return status;
1188}
1189
a73d511c
IM		 1190static int dspio_read(struct hda_codec *codec, unsigned int *data)
1191{
1192 int status;
1193
1194 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1195 if (status == -EIO)
1196 return status;
1197
1198 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1199 if (status == -EIO ||
1200 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1201 return -EIO;
1202
1203 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1204 VENDOR_DSPIO_SCP_READ_DATA, 0);
1205
1206 return 0;
1207}
1208
1209static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1210 unsigned int *buf_size, unsigned int size_count)
1211{
1212 int status = 0;
1213 unsigned int size = *buf_size;
1214 unsigned int count;
1215 unsigned int skip_count;
1216 unsigned int dummy;
1217
a16fbb85 1218 if (buffer == NULL)
a73d511c
IM		 1219 return -1;
1220
1221 count = 0;
1222 while (count < size && count < size_count) {
1223 status = dspio_read(codec, buffer++);
1224 if (status != 0)
1225 break;
1226 count++;
1227 }
1228
1229 skip_count = count;
1230 if (status == 0) {
1231 while (skip_count < size) {
1232 status = dspio_read(codec, &dummy);
1233 if (status != 0)
1234 break;
1235 skip_count++;
1236 }
1237 }
1238 *buf_size = count;
1239
1240 return status;
1241}
1242
d5c21b88
IM		 1243/*
1244 * Construct the SCP header using corresponding fields
1245 */
01ef7dbf
IM		 1246static inline unsigned int
1247make_scp_header(unsigned int target_id, unsigned int source_id,
1248 unsigned int get_flag, unsigned int req,
1249 unsigned int device_flag, unsigned int resp_flag,
1250 unsigned int error_flag, unsigned int data_size)
1251{
1252 unsigned int header = 0;
1253
1254 header = (data_size & 0x1f) << 27;
1255 header |= (error_flag & 0x01) << 26;
1256 header |= (resp_flag & 0x01) << 25;
1257 header |= (device_flag & 0x01) << 24;
1258 header |= (req & 0x7f) << 17;
1259 header |= (get_flag & 0x01) << 16;
1260 header |= (source_id & 0xff) << 8;
1261 header |= target_id & 0xff;
1262
1263 return header;
1264}
1265
d5c21b88
IM		 1266/*
1267 * Extract corresponding fields from SCP header
1268 */
01ef7dbf
IM		 1269static inline void
1270extract_scp_header(unsigned int header,
1271 unsigned int *target_id, unsigned int *source_id,
1272 unsigned int *get_flag, unsigned int *req,
1273 unsigned int *device_flag, unsigned int *resp_flag,
1274 unsigned int *error_flag, unsigned int *data_size)
1275{
1276 if (data_size)
1277 *data_size = (header >> 27) & 0x1f;
1278 if (error_flag)
1279 *error_flag = (header >> 26) & 0x01;
1280 if (resp_flag)
1281 *resp_flag = (header >> 25) & 0x01;
1282 if (device_flag)
1283 *device_flag = (header >> 24) & 0x01;
1284 if (req)
1285 *req = (header >> 17) & 0x7f;
1286 if (get_flag)
1287 *get_flag = (header >> 16) & 0x01;
1288 if (source_id)
1289 *source_id = (header >> 8) & 0xff;
1290 if (target_id)
1291 *target_id = header & 0xff;
1292}
1293
1294#define SCP_MAX_DATA_WORDS (16)
1295
1296/* Structure to contain any SCP message */
1297struct scp_msg {
1298 unsigned int hdr;
1299 unsigned int data[SCP_MAX_DATA_WORDS];
1300};
1301
a73d511c
IM		 1302static void dspio_clear_response_queue(struct hda_codec *codec)
1303{
1304 unsigned int dummy = 0;
1305 int status = -1;
1306
1307 /* clear all from the response queue */
1308 do {
1309 status = dspio_read(codec, &dummy);
1310 } while (status == 0);
1311}
1312
1313static int dspio_get_response_data(struct hda_codec *codec)
1314{
1315 struct ca0132_spec *spec = codec->spec;
1316 unsigned int data = 0;
1317 unsigned int count;
1318
1319 if (dspio_read(codec, &data) < 0)
1320 return -EIO;
1321
1322 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1323 spec->scp_resp_header = data;
1324 spec->scp_resp_count = data >> 27;
1325 count = spec->wait_num_data;
1326 dspio_read_multiple(codec, spec->scp_resp_data,
1327 &spec->scp_resp_count, count);
1328 return 0;
1329 }
1330
1331 return -EIO;
1332}
1333
d5c21b88
IM		 1334/*
1335 * Send SCP message to DSP
1336 */
01ef7dbf
IM		 1337static int dspio_send_scp_message(struct hda_codec *codec,
1338 unsigned char *send_buf,
1339 unsigned int send_buf_size,
1340 unsigned char *return_buf,
1341 unsigned int return_buf_size,
1342 unsigned int *bytes_returned)
1343{
1344 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1345 int status = -1;
1346 unsigned int scp_send_size = 0;
1347 unsigned int total_size;
1348 bool waiting_for_resp = false;
1349 unsigned int header;
1350 struct scp_msg *ret_msg;
1351 unsigned int resp_src_id, resp_target_id;
1352 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1353
1354 if (bytes_returned)
1355 *bytes_returned = 0;
1356
1357 /* get scp header from buffer */
1358 header = *((unsigned int *)send_buf);
1359 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1360 &device_flag, NULL, NULL, &data_size);
1361 scp_send_size = data_size + 1;
1362 total_size = (scp_send_size * 4);
1363
1364 if (send_buf_size < total_size)
1365 return -EINVAL;
1366
1367 if (get_flag || device_flag) {
1368 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1369 return -EINVAL;
1370
1371 spec->wait_scp_header = *((unsigned int *)send_buf);
1372
1373 /* swap source id with target id */
1374 resp_target_id = src_id;
1375 resp_src_id = target_id;
1376 spec->wait_scp_header &= 0xffff0000;
1377 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1378 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1379 spec->wait_scp = 1;
1380 waiting_for_resp = true;
1381 }
1382
1383 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1384 scp_send_size);
1385 if (status < 0) {
1386 spec->wait_scp = 0;
1387 return status;
1388 }
1389
1390 if (waiting_for_resp) {
6d67530e 1391 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1392 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1393 do {
1394 msleep(20);
6d67530e 1395 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1396 waiting_for_resp = false;
6d67530e 1397 if (!spec->wait_scp) {
01ef7dbf
IM		 1398 ret_msg = (struct scp_msg *)return_buf;
1399 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1400 memcpy(&ret_msg->data, spec->scp_resp_data,
1401 spec->wait_num_data);
1402 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1403 status = 0;
1404 } else {
1405 status = -EIO;
1406 }
1407 spec->wait_scp = 0;
1408 }
1409
1410 return status;
1411}
1412
d5c21b88
IM		 1413/**
1414 * Prepare and send the SCP message to DSP
1415 * @codec: the HDA codec
1416 * @mod_id: ID of the DSP module to send the command
1417 * @req: ID of request to send to the DSP module
1418 * @dir: SET or GET
1419 * @data: pointer to the data to send with the request, request specific
1420 * @len: length of the data, in bytes
1421 * @reply: point to the buffer to hold data returned for a reply
1422 * @reply_len: length of the reply buffer returned from GET
1423 *
1424 * Returns zero or a negative error code.
1425 */
01ef7dbf
IM		 1426static int dspio_scp(struct hda_codec *codec,
1427 int mod_id, int req, int dir, void *data, unsigned int len,
1428 void *reply, unsigned int *reply_len)
1429{
1430 int status = 0;
1431 struct scp_msg scp_send, scp_reply;
1432 unsigned int ret_bytes, send_size, ret_size;
1433 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1434 unsigned int reply_data_size;
1435
1436 memset(&scp_send, 0, sizeof(scp_send));
1437 memset(&scp_reply, 0, sizeof(scp_reply));
1438
1439 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1440 return -EINVAL;
1441
1442 if (dir == SCP_GET && reply == NULL) {
4e76a883 1443 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1444 return -EINVAL;
1445 }
1446
1447 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1448 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1449 return -EINVAL;
1450 }
1451
1452 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1453 0, 0, 0, len/sizeof(unsigned int));
1454 if (data != NULL && len > 0) {
1455 len = min((unsigned int)(sizeof(scp_send.data)), len);
1456 memcpy(scp_send.data, data, len);
1457 }
1458
1459 ret_bytes = 0;
1460 send_size = sizeof(unsigned int) + len;
1461 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1462 send_size, (unsigned char *)&scp_reply,
1463 sizeof(scp_reply), &ret_bytes);
1464
1465 if (status < 0) {
4e76a883 1466 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1467 return status;
1468 }
1469
1470 /* extract send and reply headers members */
1471 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1472 NULL, NULL, NULL, NULL, NULL);
1473 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1474 &reply_resp_flag, &reply_error_flag,
1475 &reply_data_size);
1476
1477 if (!send_get_flag)
1478 return 0;
1479
1480 if (reply_resp_flag && !reply_error_flag) {
1481 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1482 / sizeof(unsigned int);
1483
1484 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1485 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1486 return -EINVAL;
1487 } else if (ret_size != reply_data_size) {
4e76a883 1488 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1489 return -EINVAL;
46a049da
AB		 1490 } else if (!reply) {
1491 codec_dbg(codec, "NULL reply\n");
1492 return -EINVAL;
01ef7dbf
IM		 1493 } else {
1494 *reply_len = ret_size*sizeof(unsigned int);
1495 memcpy(reply, scp_reply.data, *reply_len);
1496 }
1497 } else {
4e76a883 1498 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1499 return -EIO;
1500 }
1501
1502 return status;
1503}
1504
5aaca44d
IM		 1505/*
1506 * Set DSP parameters
1507 */
1508static int dspio_set_param(struct hda_codec *codec, int mod_id,
1509 int req, void *data, unsigned int len)
1510{
1511 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1512}
1513
1514static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1515 int req, unsigned int data)
1516{
1517 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1518}
1519
d5c21b88
IM		 1520/*
1521 * Allocate a DSP DMA channel via an SCP message
1522 */
01ef7dbf
IM		 1523static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1524{
1525 int status = 0;
1526 unsigned int size = sizeof(dma_chan);
1527
4e76a883 1528 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
01ef7dbf
IM		 1529 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1530 SCP_GET, NULL, 0, dma_chan, &size);
1531
1532 if (status < 0) {
4e76a883 1533 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1534 return status;
1535 }
1536
1537 if ((*dma_chan + 1) == 0) {
4e76a883 1538 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1539 return -EBUSY;
1540 }
1541
4e76a883
TI		 1542 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1543 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1544
1545 return status;
1546}
1547
d5c21b88
IM		 1548/*
1549 * Free a DSP DMA via an SCP message
1550 */
01ef7dbf
IM		 1551static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1552{
1553 int status = 0;
1554 unsigned int dummy = 0;
1555
4e76a883
TI		 1556 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1557 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf
IM		 1558
1559 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1560 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1561
1562 if (status < 0) {
4e76a883 1563 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1564 return status;
1565 }
1566
4e76a883 1567 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1568
1569 return status;
1570}
1571
1572/*
d5c21b88 1573 * (Re)start the DSP
01ef7dbf
IM		 1574 */
1575static int dsp_set_run_state(struct hda_codec *codec)
1576{
1577 unsigned int dbg_ctrl_reg;
1578 unsigned int halt_state;
1579 int err;
1580
1581 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1582 if (err < 0)
1583 return err;
1584
1585 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1586 DSP_DBGCNTL_STATE_LOBIT;
1587
1588 if (halt_state != 0) {
1589 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1590 DSP_DBGCNTL_SS_MASK);
1591 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1592 dbg_ctrl_reg);
1593 if (err < 0)
1594 return err;
1595
1596 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1597 DSP_DBGCNTL_EXEC_MASK;
1598 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1599 dbg_ctrl_reg);
1600 if (err < 0)
1601 return err;
1602 }
1603
1604 return 0;
1605}
1606
d5c21b88
IM		 1607/*
1608 * Reset the DSP
1609 */
01ef7dbf
IM		 1610static int dsp_reset(struct hda_codec *codec)
1611{
1612 unsigned int res;
1613 int retry = 20;
1614
4e76a883 1615 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1616 do {
1617 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1618 retry--;
1619 } while (res == -EIO && retry);
1620
1621 if (!retry) {
4e76a883 1622 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1623 return -EIO;
1624 }
1625
1626 return 0;
1627}
1628
d5c21b88
IM		 1629/*
1630 * Convert chip address to DSP address
1631 */
01ef7dbf
IM		 1632static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1633 bool *code, bool *yram)
1634{
1635 *code = *yram = false;
1636
1637 if (UC_RANGE(chip_addx, 1)) {
1638 *code = true;
1639 return UC_OFF(chip_addx);
1640 } else if (X_RANGE_ALL(chip_addx, 1)) {
1641 return X_OFF(chip_addx);
1642 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1643 *yram = true;
1644 return Y_OFF(chip_addx);
1645 }
1646
4a8b89f9 1647 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 1648}
1649
d5c21b88
IM		 1650/*
1651 * Check if the DSP DMA is active
1652 */
01ef7dbf
IM		 1653static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1654{
1655 unsigned int dma_chnlstart_reg;
1656
1657 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1658
1659 return ((dma_chnlstart_reg & (1 <<
1660 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1661}
1662
1663static int dsp_dma_setup_common(struct hda_codec *codec,
1664 unsigned int chip_addx,
1665 unsigned int dma_chan,
1666 unsigned int port_map_mask,
1667 bool ovly)
1668{
1669 int status = 0;
1670 unsigned int chnl_prop;
1671 unsigned int dsp_addx;
1672 unsigned int active;
1673 bool code, yram;
1674
4e76a883 1675 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 1676
1677 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 1678 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 1679 return -EINVAL;
1680 }
1681
1682 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 1683 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 1684 return -EBUSY;
1685 }
1686
1687 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1688
1689 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1690 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1691 return -ENXIO;
1692 }
1693
1694 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1695 active = 0;
1696
4e76a883 1697 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 1698
1699 if (ovly) {
1700 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1701 &chnl_prop);
1702
1703 if (status < 0) {
4e76a883 1704 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 1705 return status;
1706 }
4e76a883 1707 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 1708 }
1709
1710 if (!code)
1711 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1712 else
1713 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1714
1715 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1716
1717 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1718 if (status < 0) {
4e76a883 1719 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 1720 return status;
1721 }
4e76a883 1722 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 1723
1724 if (ovly) {
1725 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1726 &active);
1727
1728 if (status < 0) {
4e76a883 1729 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 1730 return status;
1731 }
4e76a883 1732 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 1733 }
1734
1735 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1736 DSPDMAC_ACTIVE_AAR_MASK;
1737
1738 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1739 if (status < 0) {
4e76a883 1740 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 1741 return status;
1742 }
1743
4e76a883 1744 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 1745
1746 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1747 port_map_mask);
1748 if (status < 0) {
4e76a883 1749 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 1750 return status;
1751 }
4e76a883 1752 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 1753
1754 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1755 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1756 if (status < 0) {
4e76a883 1757 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 1758 return status;
1759 }
4e76a883 1760 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 1761
4e76a883 1762 codec_dbg(codec,
01ef7dbf
IM		 1763 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1764 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1765 chip_addx, dsp_addx, dma_chan,
1766 port_map_mask, chnl_prop, active);
1767
4e76a883 1768 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 1769
1770 return 0;
1771}
1772
d5c21b88
IM		 1773/*
1774 * Setup the DSP DMA per-transfer-specific registers
1775 */
01ef7dbf
IM		 1776static int dsp_dma_setup(struct hda_codec *codec,
1777 unsigned int chip_addx,
1778 unsigned int count,
1779 unsigned int dma_chan)
1780{
1781 int status = 0;
1782 bool code, yram;
1783 unsigned int dsp_addx;
1784 unsigned int addr_field;
1785 unsigned int incr_field;
1786 unsigned int base_cnt;
1787 unsigned int cur_cnt;
1788 unsigned int dma_cfg = 0;
1789 unsigned int adr_ofs = 0;
1790 unsigned int xfr_cnt = 0;
1791 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1792 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1793
4e76a883 1794 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 1795
1796 if (count > max_dma_count) {
4e76a883 1797 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 1798 return -EINVAL;
1799 }
1800
1801 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1802 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1803 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1804 return -ENXIO;
1805 }
1806
4e76a883 1807 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 1808
1809 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1810 incr_field = 0;
1811
1812 if (!code) {
1813 addr_field <<= 1;
1814 if (yram)
1815 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1816
1817 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1818 }
1819
1820 dma_cfg = addr_field + incr_field;
1821 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1822 dma_cfg);
1823 if (status < 0) {
4e76a883 1824 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 1825 return status;
1826 }
4e76a883 1827 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 1828
1829 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1830 (code ? 0 : 1));
1831
1832 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1833 adr_ofs);
1834 if (status < 0) {
4e76a883 1835 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 1836 return status;
1837 }
4e76a883 1838 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 1839
1840 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1841
1842 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1843
1844 xfr_cnt = base_cnt | cur_cnt;
1845
1846 status = chipio_write(codec,
1847 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1848 if (status < 0) {
4e76a883 1849 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 1850 return status;
1851 }
4e76a883 1852 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 1853
4e76a883 1854 codec_dbg(codec,
01ef7dbf
IM		 1855 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1856 "ADROFS=0x%x, XFRCNT=0x%x\n",
1857 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1858
4e76a883 1859 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 1860
1861 return 0;
1862}
1863
d5c21b88
IM		 1864/*
1865 * Start the DSP DMA
1866 */
01ef7dbf
IM		 1867static int dsp_dma_start(struct hda_codec *codec,
1868 unsigned int dma_chan, bool ovly)
1869{
1870 unsigned int reg = 0;
1871 int status = 0;
1872
4e76a883 1873 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 1874
1875 if (ovly) {
1876 status = chipio_read(codec,
1877 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1878
1879 if (status < 0) {
4e76a883 1880 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1881 return status;
1882 }
4e76a883 1883 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 1884
1885 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1886 DSPDMAC_CHNLSTART_DIS_MASK);
1887 }
1888
1889 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1890 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1891 if (status < 0) {
4e76a883 1892 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1893 return status;
1894 }
4e76a883 1895 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 1896
1897 return status;
1898}
1899
d5c21b88
IM		 1900/*
1901 * Stop the DSP DMA
1902 */
01ef7dbf
IM		 1903static int dsp_dma_stop(struct hda_codec *codec,
1904 unsigned int dma_chan, bool ovly)
1905{
1906 unsigned int reg = 0;
1907 int status = 0;
1908
4e76a883 1909 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 1910
1911 if (ovly) {
1912 status = chipio_read(codec,
1913 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1914
1915 if (status < 0) {
4e76a883 1916 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1917 return status;
1918 }
4e76a883 1919 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 1920 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1921 DSPDMAC_CHNLSTART_DIS_MASK);
1922 }
1923
1924 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1925 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1926 if (status < 0) {
4e76a883 1927 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1928 return status;
1929 }
4e76a883 1930 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 1931
1932 return status;
1933}
1934
d5c21b88
IM		 1935/**
1936 * Allocate router ports
1937 *
1938 * @codec: the HDA codec
1939 * @num_chans: number of channels in the stream
1940 * @ports_per_channel: number of ports per channel
1941 * @start_device: start device
1942 * @port_map: pointer to the port list to hold the allocated ports
1943 *
1944 * Returns zero or a negative error code.
1945 */
01ef7dbf
IM		 1946static int dsp_allocate_router_ports(struct hda_codec *codec,
1947 unsigned int num_chans,
1948 unsigned int ports_per_channel,
1949 unsigned int start_device,
1950 unsigned int *port_map)
1951{
1952 int status = 0;
1953 int res;
1954 u8 val;
1955
1956 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1957 if (status < 0)
1958 return status;
1959
1960 val = start_device << 6;
1961 val |= (ports_per_channel - 1) << 4;
1962 val |= num_chans - 1;
1963
1964 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1965 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1966 val);
1967
1968 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1969 VENDOR_CHIPIO_PORT_ALLOC_SET,
1970 MEM_CONNID_DSP);
1971
1972 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1973 if (status < 0)
1974 return status;
1975
1976 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1977 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1978
1979 *port_map = res;
1980
1981 return (res < 0) ? res : 0;
1982}
1983
d5c21b88
IM		 1984/*
1985 * Free router ports
1986 */
01ef7dbf
IM		 1987static int dsp_free_router_ports(struct hda_codec *codec)
1988{
1989 int status = 0;
1990
1991 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1992 if (status < 0)
1993 return status;
1994
1995 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1996 VENDOR_CHIPIO_PORT_FREE_SET,
1997 MEM_CONNID_DSP);
1998
1999 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2000
2001 return status;
2002}
2003
d5c21b88
IM		 2004/*
2005 * Allocate DSP ports for the download stream
2006 */
01ef7dbf
IM		 2007static int dsp_allocate_ports(struct hda_codec *codec,
2008 unsigned int num_chans,
2009 unsigned int rate_multi, unsigned int *port_map)
2010{
2011 int status;
2012
4e76a883 2013 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2014
2015 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2016 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2017 return -EINVAL;
2018 }
2019
2020 status = dsp_allocate_router_ports(codec, num_chans,
2021 rate_multi, 0, port_map);
2022
4e76a883 2023 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2024
2025 return status;
2026}
2027
01ef7dbf
IM		 2028static int dsp_allocate_ports_format(struct hda_codec *codec,
2029 const unsigned short fmt,
2030 unsigned int *port_map)
2031{
2032 int status;
2033 unsigned int num_chans;
2034
2035 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2036 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2037 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2038
2039 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2040 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2041 return -EINVAL;
2042 }
2043
2044 num_chans = get_hdafmt_chs(fmt) + 1;
2045
2046 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2047
2048 return status;
2049}
2050
d5c21b88
IM		 2051/*
2052 * free DSP ports
2053 */
2054static int dsp_free_ports(struct hda_codec *codec)
2055{
2056 int status;
2057
4e76a883 2058 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2059
2060 status = dsp_free_router_ports(codec);
2061 if (status < 0) {
4e76a883 2062 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2063 return status;
2064 }
4e76a883 2065 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2066
2067 return status;
2068}
2069
01ef7dbf
IM		 2070/*
2071 * HDA DMA engine stuffs for DSP code download
2072 */
2073struct dma_engine {
2074 struct hda_codec *codec;
2075 unsigned short m_converter_format;
2076 struct snd_dma_buffer *dmab;
2077 unsigned int buf_size;
2078};
2079
2080
2081enum dma_state {
2082 DMA_STATE_STOP = 0,
2083 DMA_STATE_RUN = 1
2084};
2085
6194b99d 2086static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2087 unsigned int sample_rate,
2088 unsigned short channels,
01ef7dbf
IM		 2089 unsigned short *hda_format)
2090{
2091 unsigned int format_val;
2092
b7d023e1
TI		 2093 format_val = snd_hdac_calc_stream_format(sample_rate,
2094 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2095
2096 if (hda_format)
2097 *hda_format = (unsigned short)format_val;
2098
2099 return 0;
2100}
2101
d5c21b88
IM		 2102/*
2103 * Reset DMA for DSP download
2104 */
01ef7dbf
IM		 2105static int dma_reset(struct dma_engine *dma)
2106{
2107 struct hda_codec *codec = dma->codec;
2108 struct ca0132_spec *spec = codec->spec;
2109 int status;
2110
b3667bd7 2111 if (dma->dmab->area)
01ef7dbf
IM		 2112 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2113
2114 status = snd_hda_codec_load_dsp_prepare(codec,
2115 dma->m_converter_format,
2116 dma->buf_size,
2117 dma->dmab);
2118 if (status < 0)
2119 return status;
2120 spec->dsp_stream_id = status;
2121 return 0;
2122}
2123
2124static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2125{
01ef7dbf
IM		 2126 bool cmd;
2127
01ef7dbf
IM		 2128 switch (state) {
2129 case DMA_STATE_STOP:
2130 cmd = false;
2131 break;
2132 case DMA_STATE_RUN:
2133 cmd = true;
2134 break;
2135 default:
c41999a2
DH		 2136 return 0;
2137 }
01ef7dbf
IM		 2138
2139 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2140 return 0;
95c6e9cb
IM		 2141}
2142
01ef7dbf
IM		 2143static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2144{
2145 return dma->dmab->bytes;
2146}
95c6e9cb 2147
01ef7dbf
IM		 2148static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2149{
2150 return dma->dmab->area;
2151}
95c6e9cb 2152
01ef7dbf
IM		 2153static int dma_xfer(struct dma_engine *dma,
2154 const unsigned int *data,
2155 unsigned int count)
2156{
2157 memcpy(dma->dmab->area, data, count);
2158 return 0;
2159}
95c6e9cb 2160
01ef7dbf
IM		 2161static void dma_get_converter_format(
2162 struct dma_engine *dma,
2163 unsigned short *format)
2164{
2165 if (format)
2166 *format = dma->m_converter_format;
2167}
95c6e9cb 2168
01ef7dbf 2169static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2170{
01ef7dbf 2171 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2172
01ef7dbf 2173 return spec->dsp_stream_id;
95c6e9cb
IM		 2174}
2175
01ef7dbf
IM		 2176struct dsp_image_seg {
2177 u32 magic;
2178 u32 chip_addr;
2179 u32 count;
2180 u32 data[0];
2181};
2182
2183static const u32 g_magic_value = 0x4c46584d;
2184static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2185
2186static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2187{
01ef7dbf
IM		 2188 return p->magic == g_magic_value;
2189}
95c6e9cb 2190
01ef7dbf
IM		 2191static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2192{
2193 return g_chip_addr_magic_value == p->chip_addr;
2194}
95c6e9cb 2195
01ef7dbf
IM		 2196static bool is_last(const struct dsp_image_seg *p)
2197{
2198 return p->count == 0;
2199}
95c6e9cb 2200
01ef7dbf
IM		 2201static size_t dsp_sizeof(const struct dsp_image_seg *p)
2202{
2203 return sizeof(*p) + p->count*sizeof(u32);
2204}
2205
2206static const struct dsp_image_seg *get_next_seg_ptr(
2207 const struct dsp_image_seg *p)
2208{
2209 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2210}
2211
2212/*
01ef7dbf 2213 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2214 */
8ae3124b 2215#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2216
d5c21b88
IM		 2217/*
2218 * Program a list of address/data pairs via the ChipIO widget.
2219 * The segment data is in the format of successive pairs of words.
2220 * These are repeated as indicated by the segment's count field.
2221 */
01ef7dbf
IM		 2222static int dspxfr_hci_write(struct hda_codec *codec,
2223 const struct dsp_image_seg *fls)
95c6e9cb 2224{
01ef7dbf
IM		 2225 int status;
2226 const u32 *data;
2227 unsigned int count;
95c6e9cb 2228
01ef7dbf 2229 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2230 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2231 return -EINVAL;
95c6e9cb
IM		 2232 }
2233
01ef7dbf
IM		 2234 count = fls->count;
2235 data = (u32 *)(fls->data);
2236 while (count >= 2) {
2237 status = chipio_write(codec, data[0], data[1]);
2238 if (status < 0) {
4e76a883 2239 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2240 return status;
2241 }
2242 count -= 2;
2243 data += 2;
2244 }
2245 return 0;
95c6e9cb
IM		 2246}
2247
d5c21b88
IM		 2248/**
2249 * Write a block of data into DSP code or data RAM using pre-allocated
2250 * DMA engine.
2251 *
2252 * @codec: the HDA codec
2253 * @fls: pointer to a fast load image
2254 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2255 * no relocation
2256 * @dma_engine: pointer to DMA engine to be used for DSP download
2257 * @dma_chan: The number of DMA channels used for DSP download
2258 * @port_map_mask: port mapping
2259 * @ovly: TRUE if overlay format is required
2260 *
2261 * Returns zero or a negative error code.
2262 */
01ef7dbf
IM		 2263static int dspxfr_one_seg(struct hda_codec *codec,
2264 const struct dsp_image_seg *fls,
2265 unsigned int reloc,
2266 struct dma_engine *dma_engine,
2267 unsigned int dma_chan,
2268 unsigned int port_map_mask,
2269 bool ovly)
95c6e9cb 2270{
406261ce 2271 int status = 0;
01ef7dbf
IM		 2272 bool comm_dma_setup_done = false;
2273 const unsigned int *data;
2274 unsigned int chip_addx;
2275 unsigned int words_to_write;
2276 unsigned int buffer_size_words;
2277 unsigned char *buffer_addx;
2278 unsigned short hda_format;
2279 unsigned int sample_rate_div;
2280 unsigned int sample_rate_mul;
2281 unsigned int num_chans;
2282 unsigned int hda_frame_size_words;
2283 unsigned int remainder_words;
2284 const u32 *data_remainder;
2285 u32 chip_addx_remainder;
2286 unsigned int run_size_words;
2287 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2288 unsigned long timeout;
2289 bool dma_active;
01ef7dbf
IM		 2290
2291 if (fls == NULL)
2292 return -EINVAL;
2293 if (is_hci_prog_list_seg(fls)) {
2294 hci_write = fls;
2295 fls = get_next_seg_ptr(fls);
2296 }
95c6e9cb 2297
01ef7dbf 2298 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2299 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2300 return dspxfr_hci_write(codec, hci_write);
2301 }
95c6e9cb 2302
01ef7dbf 2303 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2304 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2305 return -EINVAL;
95c6e9cb
IM		 2306 }
2307
01ef7dbf
IM		 2308 data = fls->data;
2309 chip_addx = fls->chip_addr,
2310 words_to_write = fls->count;
2311
2312 if (!words_to_write)
2313 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2314 if (reloc)
2315 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2316
2317 if (!UC_RANGE(chip_addx, words_to_write) &&
2318 !X_RANGE_ALL(chip_addx, words_to_write) &&
2319 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2320 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2321 return -EINVAL;
95c6e9cb
IM		 2322 }
2323
01ef7dbf
IM		 2324 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2325 sizeof(u32);
2326
2327 buffer_addx = dma_get_buffer_addr(dma_engine);
2328
2329 if (buffer_addx == NULL) {
4e76a883 2330 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2331 return -EINVAL;
2332 }
2333
2334 dma_get_converter_format(dma_engine, &hda_format);
2335 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2336 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2337 num_chans = get_hdafmt_chs(hda_format) + 1;
2338
2339 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2340 (num_chans * sample_rate_mul / sample_rate_div));
2341
3bc085a1 2342 if (hda_frame_size_words == 0) {
4e76a883 2343 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2344 return -EINVAL;
2345 }
2346
01ef7dbf
IM		 2347 buffer_size_words = min(buffer_size_words,
2348 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2349 65536 : 32768));
2350 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2351 codec_dbg(codec,
01ef7dbf
IM		 2352 "chpadr=0x%08x frmsz=%u nchan=%u "
2353 "rate_mul=%u div=%u bufsz=%u\n",
2354 chip_addx, hda_frame_size_words, num_chans,
2355 sample_rate_mul, sample_rate_div, buffer_size_words);
2356
3bc085a1 2357 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2358 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2359 return -EINVAL;
2360 }
2361
2362 remainder_words = words_to_write % hda_frame_size_words;
2363 data_remainder = data;
2364 chip_addx_remainder = chip_addx;
2365
2366 data += remainder_words;
2367 chip_addx += remainder_words*sizeof(u32);
2368 words_to_write -= remainder_words;
2369
2370 while (words_to_write != 0) {
2371 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2372 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2373 words_to_write, run_size_words, remainder_words);
2374 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2375 if (!comm_dma_setup_done) {
2376 status = dsp_dma_stop(codec, dma_chan, ovly);
2377 if (status < 0)
425a7880 2378 return status;
01ef7dbf
IM		 2379 status = dsp_dma_setup_common(codec, chip_addx,
2380 dma_chan, port_map_mask, ovly);
2381 if (status < 0)
2382 return status;
2383 comm_dma_setup_done = true;
2384 }
2385
2386 status = dsp_dma_setup(codec, chip_addx,
2387 run_size_words, dma_chan);
2388 if (status < 0)
2389 return status;
2390 status = dsp_dma_start(codec, dma_chan, ovly);
2391 if (status < 0)
2392 return status;
2393 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2394 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2395 return -EIO;
2396 }
2397 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2398 if (status < 0)
2399 return status;
2400 if (remainder_words != 0) {
2401 status = chipio_write_multiple(codec,
2402 chip_addx_remainder,
2403 data_remainder,
2404 remainder_words);
b3667bd7
TI		 2405 if (status < 0)
2406 return status;
01ef7dbf
IM		 2407 remainder_words = 0;
2408 }
2409 if (hci_write) {
2410 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2411 if (status < 0)
2412 return status;
01ef7dbf
IM		 2413 hci_write = NULL;
2414 }
6d67530e
IM		 2415
2416 timeout = jiffies + msecs_to_jiffies(2000);
2417 do {
2418 dma_active = dsp_is_dma_active(codec, dma_chan);
2419 if (!dma_active)
01ef7dbf 2420 break;
6d67530e
IM		 2421 msleep(20);
2422 } while (time_before(jiffies, timeout));
2423 if (dma_active)
2424 break;
2425
4e76a883 2426 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2427 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2428 status = dma_reset(dma_engine);
01ef7dbf
IM		 2429
2430 if (status < 0)
2431 return status;
2432
2433 data += run_size_words;
2434 chip_addx += run_size_words*sizeof(u32);
2435 words_to_write -= run_size_words;
2436 }
2437
2438 if (remainder_words != 0) {
2439 status = chipio_write_multiple(codec, chip_addx_remainder,
2440 data_remainder, remainder_words);
2441 }
2442
2443 return status;
95c6e9cb
IM		 2444}
2445
d5c21b88
IM		 2446/**
2447 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2448 *
2449 * @codec: the HDA codec
2450 * @fls_data: pointer to a fast load image
2451 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2452 * no relocation
e97249dd 2453 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2454 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2455 * @ovly: TRUE if overlay format is required
2456 *
2457 * Returns zero or a negative error code.
2458 */
01ef7dbf
IM		 2459static int dspxfr_image(struct hda_codec *codec,
2460 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2461 unsigned int reloc,
2462 unsigned int sample_rate,
2463 unsigned short channels,
01ef7dbf 2464 bool ovly)
95c6e9cb
IM		 2465{
2466 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2467 int status;
2468 unsigned short hda_format = 0;
2469 unsigned int response;
2470 unsigned char stream_id = 0;
2471 struct dma_engine *dma_engine;
2472 unsigned int dma_chan;
2473 unsigned int port_map_mask;
2474
2475 if (fls_data == NULL)
2476 return -EINVAL;
2477
2478 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2479 if (!dma_engine)
2480 return -ENOMEM;
95c6e9cb 2481
01ef7dbf
IM		 2482 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2483 if (!dma_engine->dmab) {
549e8292
TI		 2484 kfree(dma_engine);
2485 return -ENOMEM;
01ef7dbf 2486 }
95c6e9cb 2487
01ef7dbf 2488 dma_engine->codec = codec;
6194b99d 2489 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2490 dma_engine->m_converter_format = hda_format;
2491 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2492 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2493
8ae3124b 2494 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2495
2496 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2497 hda_format, &response);
2498
2499 if (status < 0) {
4e76a883 2500 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2501 goto exit;
2502 }
2503
2504 status = snd_hda_codec_load_dsp_prepare(codec,
2505 dma_engine->m_converter_format,
2506 dma_engine->buf_size,
2507 dma_engine->dmab);
2508 if (status < 0)
95c6e9cb 2509 goto exit;
01ef7dbf
IM		 2510 spec->dsp_stream_id = status;
2511
2512 if (ovly) {
2513 status = dspio_alloc_dma_chan(codec, &dma_chan);
2514 if (status < 0) {
4e76a883 2515 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2516 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2517 goto exit;
2518 }
2519 }
95c6e9cb 2520
01ef7dbf
IM		 2521 port_map_mask = 0;
2522 status = dsp_allocate_ports_format(codec, hda_format,
2523 &port_map_mask);
2524 if (status < 0) {
4e76a883 2525 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2526 goto exit;
2527 }
2528
2529 stream_id = dma_get_stream_id(dma_engine);
2530 status = codec_set_converter_stream_channel(codec,
2531 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2532 if (status < 0) {
4e76a883 2533 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2534 goto exit;
2535 }
2536
2537 while ((fls_data != NULL) && !is_last(fls_data)) {
2538 if (!is_valid(fls_data)) {
4e76a883 2539 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2540 status = -EINVAL;
2541 goto exit;
2542 }
2543 status = dspxfr_one_seg(codec, fls_data, reloc,
2544 dma_engine, dma_chan,
2545 port_map_mask, ovly);
2546 if (status < 0)
2547 break;
2548
2549 if (is_hci_prog_list_seg(fls_data))
2550 fls_data = get_next_seg_ptr(fls_data);
2551
2552 if ((fls_data != NULL) && !is_last(fls_data))
2553 fls_data = get_next_seg_ptr(fls_data);
2554 }
2555
2556 if (port_map_mask != 0)
2557 status = dsp_free_ports(codec);
2558
2559 if (status < 0)
95c6e9cb
IM		 2560 goto exit;
2561
01ef7dbf
IM		 2562 status = codec_set_converter_stream_channel(codec,
2563 WIDGET_CHIP_CTRL, 0, 0, &response);
2564
95c6e9cb 2565exit:
01ef7dbf
IM		 2566 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2567 dspio_free_dma_chan(codec, dma_chan);
2568
b3667bd7 2569 if (dma_engine->dmab->area)
01ef7dbf
IM		 2570 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2571 kfree(dma_engine->dmab);
2572 kfree(dma_engine);
2573
2574 return status;
95c6e9cb
IM		 2575}
2576
2577/*
01ef7dbf 2578 * CA0132 DSP download stuffs.
95c6e9cb 2579 */
01ef7dbf 2580static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2581{
4e76a883 2582 codec_dbg(codec, "---- dspload_post_setup ------\n");
95c6e9cb 2583
01ef7dbf
IM		 2584 /*set DSP speaker to 2.0 configuration*/
2585 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2586 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2587
01ef7dbf
IM		 2588 /*update write pointer*/
2589 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2590}
95c6e9cb 2591
d5c21b88 2592/**
e60b2c7f 2593 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2594 *
2595 * @codec: the HDA codec
2596 * @fls: pointer to a fast load image
2597 * @ovly: TRUE if overlay format is required
2598 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2599 * no relocation
2600 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2601 * @router_chans: number of audio router channels to be allocated (0 means use
2602 * internal defaults; max is 32)
2603 *
e60b2c7f
TI		 2604 * Download DSP from a DSP Image Fast Load structure. This structure is a
2605 * linear, non-constant sized element array of structures, each of which
2606 * contain the count of the data to be loaded, the data itself, and the
2607 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2608 * Returns zero or a negative error code.
2609 */
01ef7dbf
IM		 2610static int dspload_image(struct hda_codec *codec,
2611 const struct dsp_image_seg *fls,
2612 bool ovly,
2613 unsigned int reloc,
2614 bool autostart,
2615 int router_chans)
2616{
2617 int status = 0;
e97249dd
IM		 2618 unsigned int sample_rate;
2619 unsigned short channels;
01ef7dbf 2620
4e76a883 2621 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2622 if (router_chans == 0) {
2623 if (!ovly)
2624 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2625 else
2626 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2627 }
95c6e9cb 2628
e97249dd
IM		 2629 sample_rate = 48000;
2630 channels = (unsigned short)router_chans;
01ef7dbf 2631
e97249dd
IM		 2632 while (channels > 16) {
2633 sample_rate *= 2;
2634 channels /= 2;
01ef7dbf
IM		 2635 }
2636
01ef7dbf 2637 do {
4e76a883 2638 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 2639 if (!ovly)
2640 status = dsp_reset(codec);
2641
2642 if (status < 0)
2643 break;
2644
4e76a883 2645 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 2646 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2647 ovly);
01ef7dbf
IM		 2648
2649 if (status < 0)
2650 break;
2651
4e76a883 2652 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 2653 if (autostart && !ovly) {
2654 dspload_post_setup(codec);
2655 status = dsp_set_run_state(codec);
2656 }
2657
4e76a883 2658 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 2659 } while (0);
2660
2661 return status;
2662}
2663
f664417e 2664#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 2665static bool dspload_is_loaded(struct hda_codec *codec)
2666{
2667 unsigned int data = 0;
2668 int status = 0;
2669
2670 status = chipio_read(codec, 0x40004, &data);
2671 if ((status < 0) || (data != 1))
2672 return false;
2673
2674 return true;
2675}
f664417e
TI		 2676#else
2677#define dspload_is_loaded(codec) false
2678#endif
01ef7dbf
IM		 2679
2680static bool dspload_wait_loaded(struct hda_codec *codec)
2681{
6d67530e 2682 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 2683
2684 do {
01ef7dbf 2685 if (dspload_is_loaded(codec)) {
d9684bb5 2686 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 2687 return true;
2688 }
6d67530e
IM		 2689 msleep(20);
2690 } while (time_before(jiffies, timeout));
01ef7dbf 2691
d9684bb5 2692 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 2693 return false;
95c6e9cb
IM		 2694}
2695
825315bc
IM		 2696/*
2697 * PCM callbacks
2698 */
95c6e9cb
IM		 2699static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2700 struct hda_codec *codec,
2701 unsigned int stream_tag,
2702 unsigned int format,
2703 struct snd_pcm_substream *substream)
2704{
2705 struct ca0132_spec *spec = codec->spec;
825315bc 2706
28fba950 2707 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 2708
2709 return 0;
95c6e9cb
IM		 2710}
2711
2712static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2713 struct hda_codec *codec,
2714 struct snd_pcm_substream *substream)
2715{
2716 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2717
2718 if (spec->dsp_state == DSP_DOWNLOADING)
2719 return 0;
2720
2721 /*If Playback effects are on, allow stream some time to flush
2722 *effects tail*/
2723 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2724 msleep(50);
2725
28fba950 2726 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 2727
2728 return 0;
95c6e9cb
IM		 2729}
2730
e8412ca4
DR		 2731static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2732 struct hda_codec *codec,
2733 struct snd_pcm_substream *substream)
2734{
2735 struct ca0132_spec *spec = codec->spec;
2736 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2737 struct snd_pcm_runtime *runtime = substream->runtime;
2738
2739 if (spec->dsp_state != DSP_DOWNLOADED)
2740 return 0;
2741
2742 /* Add latency if playback enhancement and either effect is enabled. */
2743 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2744 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2745 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2746 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2747 }
2748
2749 /* Applying Speaker EQ adds latency as well. */
2750 if (spec->cur_out_type == SPEAKER_OUT)
2751 latency += DSP_SPEAKER_OUT_LATENCY;
2752
2753 return (latency * runtime->rate) / 1000;
2754}
2755
95c6e9cb
IM		 2756/*
2757 * Digital out
2758 */
27ebeb0b
TI		 2759static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2760 struct hda_codec *codec,
2761 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2762{
2763 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2764 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2765}
2766
27ebeb0b 2767static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2768 struct hda_codec *codec,
2769 unsigned int stream_tag,
2770 unsigned int format,
2771 struct snd_pcm_substream *substream)
2772{
2773 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2774 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2775 stream_tag, format, substream);
95c6e9cb
IM		 2776}
2777
27ebeb0b 2778static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2779 struct hda_codec *codec,
95c6e9cb
IM		 2780 struct snd_pcm_substream *substream)
2781{
2782 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2783 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2784}
2785
27ebeb0b
TI		 2786static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2787 struct hda_codec *codec,
2788 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2789{
2790 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2791 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2792}
2793
825315bc
IM		 2794/*
2795 * Analog capture
2796 */
2797static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2798 struct hda_codec *codec,
2799 unsigned int stream_tag,
2800 unsigned int format,
2801 struct snd_pcm_substream *substream)
2802{
13c12dbe 2803 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 2804 stream_tag, 0, format);
825315bc
IM		 2805
2806 return 0;
2807}
2808
2809static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2810 struct hda_codec *codec,
2811 struct snd_pcm_substream *substream)
2812{
2813 struct ca0132_spec *spec = codec->spec;
2814
2815 if (spec->dsp_state == DSP_DOWNLOADING)
2816 return 0;
2817
28fba950 2818 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 2819 return 0;
2820}
2821
e8412ca4
DR		 2822static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2823 struct hda_codec *codec,
2824 struct snd_pcm_substream *substream)
2825{
2826 struct ca0132_spec *spec = codec->spec;
2827 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2828 struct snd_pcm_runtime *runtime = substream->runtime;
2829
2830 if (spec->dsp_state != DSP_DOWNLOADED)
2831 return 0;
2832
2833 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2834 latency += DSP_CRYSTAL_VOICE_LATENCY;
2835
2836 return (latency * runtime->rate) / 1000;
2837}
2838
e90f29e4
IM		 2839/*
2840 * Controls stuffs.
2841 */
2842
2843/*
2844 * Mixer controls helpers.
2845 */
2846#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2847 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2848 .name = xname, \
2849 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2850 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2851 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2852 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2853 .info = ca0132_volume_info, \
2854 .get = ca0132_volume_get, \
2855 .put = ca0132_volume_put, \
2856 .tlv = { .c = ca0132_volume_tlv }, \
2857 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2858
2859#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2860 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2861 .name = xname, \
2862 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2863 .info = snd_hda_mixer_amp_switch_info, \
2864 .get = ca0132_switch_get, \
2865 .put = ca0132_switch_put, \
2866 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2867
2868/* stereo */
2869#define CA0132_CODEC_VOL(xname, nid, dir) \
2870 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2871#define CA0132_CODEC_MUTE(xname, nid, dir) \
2872 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2873
4091fb95 2874/* The following are for tuning of products */
44f0c978
IM		 2875#ifdef ENABLE_TUNING_CONTROLS
2876
2877static unsigned int voice_focus_vals_lookup[] = {
28780x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
28790x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
28800x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
28810x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
28820x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
28830x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
28840x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
28850x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
28860x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
28870x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
28880x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
28890x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
28900x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
28910x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
28920x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
28930x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
28940x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
28950x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
28960x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
28970x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
28980x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
28990x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
29000x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
29010x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
29020x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
29030x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
29040x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2905};
2906
2907static unsigned int mic_svm_vals_lookup[] = {
29080x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
29090x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
29100x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
29110x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
29120x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
29130x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
29140x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
29150x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
29160x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
29170x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
29180x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
29190x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
29200x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
29210x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
29220x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
29230x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
29240x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2925};
2926
2927static unsigned int equalizer_vals_lookup[] = {
29280xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
29290xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
29300xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
29310xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
29320x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
29330x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
29340x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
29350x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
29360x41C00000
2937};
2938
2939static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2940 unsigned int *lookup, int idx)
2941{
2942 int i = 0;
2943
2944 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2945 if (nid == ca0132_tuning_ctls[i].nid)
2946 break;
2947
2948 snd_hda_power_up(codec);
2949 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2950 ca0132_tuning_ctls[i].req,
2951 &(lookup[idx]), sizeof(unsigned int));
2952 snd_hda_power_down(codec);
2953
2954 return 1;
2955}
2956
2957static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2958 struct snd_ctl_elem_value *ucontrol)
2959{
2960 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2961 struct ca0132_spec *spec = codec->spec;
2962 hda_nid_t nid = get_amp_nid(kcontrol);
2963 long *valp = ucontrol->value.integer.value;
2964 int idx = nid - TUNING_CTL_START_NID;
2965
2966 *valp = spec->cur_ctl_vals[idx];
2967 return 0;
2968}
2969
2970static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2971 struct snd_ctl_elem_info *uinfo)
2972{
2973 int chs = get_amp_channels(kcontrol);
2974 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2975 uinfo->count = chs == 3 ? 2 : 1;
2976 uinfo->value.integer.min = 20;
2977 uinfo->value.integer.max = 180;
2978 uinfo->value.integer.step = 1;
2979
2980 return 0;
2981}
2982
2983static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2984 struct snd_ctl_elem_value *ucontrol)
2985{
2986 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2987 struct ca0132_spec *spec = codec->spec;
2988 hda_nid_t nid = get_amp_nid(kcontrol);
2989 long *valp = ucontrol->value.integer.value;
2990 int idx;
2991
2992 idx = nid - TUNING_CTL_START_NID;
2993 /* any change? */
2994 if (spec->cur_ctl_vals[idx] == *valp)
2995 return 0;
2996
2997 spec->cur_ctl_vals[idx] = *valp;
2998
2999 idx = *valp - 20;
3000 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3001
3002 return 1;
3003}
3004
3005static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3006 struct snd_ctl_elem_info *uinfo)
3007{
3008 int chs = get_amp_channels(kcontrol);
3009 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3010 uinfo->count = chs == 3 ? 2 : 1;
3011 uinfo->value.integer.min = 0;
3012 uinfo->value.integer.max = 100;
3013 uinfo->value.integer.step = 1;
3014
3015 return 0;
3016}
3017
3018static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3019 struct snd_ctl_elem_value *ucontrol)
3020{
3021 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3022 struct ca0132_spec *spec = codec->spec;
3023 hda_nid_t nid = get_amp_nid(kcontrol);
3024 long *valp = ucontrol->value.integer.value;
3025 int idx;
3026
3027 idx = nid - TUNING_CTL_START_NID;
3028 /* any change? */
3029 if (spec->cur_ctl_vals[idx] == *valp)
3030 return 0;
3031
3032 spec->cur_ctl_vals[idx] = *valp;
3033
3034 idx = *valp;
3035 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3036
3037 return 0;
3038}
3039
3040static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3041 struct snd_ctl_elem_info *uinfo)
3042{
3043 int chs = get_amp_channels(kcontrol);
3044 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3045 uinfo->count = chs == 3 ? 2 : 1;
3046 uinfo->value.integer.min = 0;
3047 uinfo->value.integer.max = 48;
3048 uinfo->value.integer.step = 1;
3049
3050 return 0;
3051}
3052
3053static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3054 struct snd_ctl_elem_value *ucontrol)
3055{
3056 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3057 struct ca0132_spec *spec = codec->spec;
3058 hda_nid_t nid = get_amp_nid(kcontrol);
3059 long *valp = ucontrol->value.integer.value;
3060 int idx;
3061
3062 idx = nid - TUNING_CTL_START_NID;
3063 /* any change? */
3064 if (spec->cur_ctl_vals[idx] == *valp)
3065 return 0;
3066
3067 spec->cur_ctl_vals[idx] = *valp;
3068
3069 idx = *valp;
3070 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3071
3072 return 1;
3073}
3074
8e142e9e
TS		 3075static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3076static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3077
3078static int add_tuning_control(struct hda_codec *codec,
3079 hda_nid_t pnid, hda_nid_t nid,
3080 const char *name, int dir)
3081{
975cc02a 3082 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3083 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3084 struct snd_kcontrol_new knew =
3085 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3086
3087 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3088 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3089 knew.tlv.c = 0;
3090 knew.tlv.p = 0;
3091 switch (pnid) {
3092 case VOICE_FOCUS:
3093 knew.info = voice_focus_ctl_info;
3094 knew.get = tuning_ctl_get;
3095 knew.put = voice_focus_ctl_put;
3096 knew.tlv.p = voice_focus_db_scale;
3097 break;
3098 case MIC_SVM:
3099 knew.info = mic_svm_ctl_info;
3100 knew.get = tuning_ctl_get;
3101 knew.put = mic_svm_ctl_put;
3102 break;
3103 case EQUALIZER:
3104 knew.info = equalizer_ctl_info;
3105 knew.get = tuning_ctl_get;
3106 knew.put = equalizer_ctl_put;
3107 knew.tlv.p = eq_db_scale;
3108 break;
3109 default:
3110 return 0;
3111 }
3112 knew.private_value =
3113 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3114 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3115 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3116}
3117
3118static int add_tuning_ctls(struct hda_codec *codec)
3119{
3120 int i;
3121 int err;
3122
3123 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3124 err = add_tuning_control(codec,
3125 ca0132_tuning_ctls[i].parent_nid,
3126 ca0132_tuning_ctls[i].nid,
3127 ca0132_tuning_ctls[i].name,
3128 ca0132_tuning_ctls[i].direct);
3129 if (err < 0)
3130 return err;
3131 }
3132
3133 return 0;
3134}
3135
3136static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3137{
3138 struct ca0132_spec *spec = codec->spec;
3139 int i;
3140
3141 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3142 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3143 /* SVM level defaults to 0.74. */
3144 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3145
3146 /* EQ defaults to 0dB. */
3147 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3148 spec->cur_ctl_vals[i] = 24;
3149}
3150#endif /*ENABLE_TUNING_CONTROLS*/
3151
5aaca44d
IM		 3152/*
3153 * Select the active output.
3154 * If autodetect is enabled, output will be selected based on jack detection.
3155 * If jack inserted, headphone will be selected, else built-in speakers
3156 * If autodetect is disabled, output will be selected based on selection.
3157 */
3158static int ca0132_select_out(struct hda_codec *codec)
3159{
3160 struct ca0132_spec *spec = codec->spec;
3161 unsigned int pin_ctl;
3162 int jack_present;
3163 int auto_jack;
3164 unsigned int tmp;
3165 int err;
3166
4e76a883 3167 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3168
664c7155 3169 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3170
3171 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3172
3173 if (auto_jack)
fe14f39e 3174 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3175 else
3176 jack_present =
3177 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3178
3179 if (jack_present)
3180 spec->cur_out_type = HEADPHONE_OUT;
3181 else
3182 spec->cur_out_type = SPEAKER_OUT;
3183
3184 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3185 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3186 /*speaker out config*/
3187 tmp = FLOAT_ONE;
3188 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3189 if (err < 0)
3190 goto exit;
3191 /*enable speaker EQ*/
3192 tmp = FLOAT_ONE;
3193 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3194 if (err < 0)
3195 goto exit;
3196
3197 /* Setup EAPD */
3198 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3199 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3200 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3201 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3202 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3203 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3204 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3205 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3206
3207 /* disable headphone node */
3208 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3209 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3210 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3211 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3212 /* enable speaker node */
3213 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3214 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3215 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3216 pin_ctl | PIN_OUT);
5aaca44d 3217 } else {
4e76a883 3218 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3219 /*headphone out config*/
3220 tmp = FLOAT_ZERO;
3221 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3222 if (err < 0)
3223 goto exit;
3224 /*disable speaker EQ*/
3225 tmp = FLOAT_ZERO;
3226 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3227 if (err < 0)
3228 goto exit;
3229
3230 /* Setup EAPD */
3231 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3232 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3233 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3234 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3235 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3236 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3237 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3238 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3239
3240 /* disable speaker*/
3241 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3242 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3243 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3244 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3245 /* enable headphone*/
3246 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3247 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3248 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3249 pin_ctl | PIN_HP);
5aaca44d
IM		 3250 }
3251
3252exit:
664c7155 3253 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3254
3255 return err < 0 ? err : 0;
3256}
3257
993884f6
CCC		 3258static void ca0132_unsol_hp_delayed(struct work_struct *work)
3259{
3260 struct ca0132_spec *spec = container_of(
3261 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 3262 struct hda_jack_tbl *jack;
3263
993884f6 3264 ca0132_select_out(spec->codec);
d5c016b5 3265 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 3266 if (jack) {
3267 jack->block_report = 0;
3268 snd_hda_jack_report_sync(spec->codec);
3269 }
993884f6
CCC		 3270}
3271
5aaca44d
IM		 3272static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3273static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3274static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3275
3276/*
3277 * Select the active VIP source
3278 */
3279static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3280{
3281 struct ca0132_spec *spec = codec->spec;
3282 unsigned int tmp;
3283
e8f1bd5d 3284 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 3285 return 0;
3286
3287 /* if CrystalVoice if off, vipsource should be 0 */
3288 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3289 (val == 0)) {
3290 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3291 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3292 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3293 if (spec->cur_mic_type == DIGITAL_MIC)
3294 tmp = FLOAT_TWO;
3295 else
3296 tmp = FLOAT_ONE;
3297 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3298 tmp = FLOAT_ZERO;
3299 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3300 } else {
3301 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3302 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3303 if (spec->cur_mic_type == DIGITAL_MIC)
3304 tmp = FLOAT_TWO;
3305 else
3306 tmp = FLOAT_ONE;
3307 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3308 tmp = FLOAT_ONE;
3309 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3310 msleep(20);
3311 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3312 }
3313
3314 return 1;
3315}
3316
3317/*
3318 * Select the active microphone.
3319 * If autodetect is enabled, mic will be selected based on jack detection.
3320 * If jack inserted, ext.mic will be selected, else built-in mic
3321 * If autodetect is disabled, mic will be selected based on selection.
3322 */
3323static int ca0132_select_mic(struct hda_codec *codec)
3324{
3325 struct ca0132_spec *spec = codec->spec;
3326 int jack_present;
3327 int auto_jack;
3328
4e76a883 3329 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 3330
664c7155 3331 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3332
3333 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3334
3335 if (auto_jack)
fe14f39e 3336 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 3337 else
3338 jack_present =
3339 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3340
3341 if (jack_present)
3342 spec->cur_mic_type = LINE_MIC_IN;
3343 else
3344 spec->cur_mic_type = DIGITAL_MIC;
3345
3346 if (spec->cur_mic_type == DIGITAL_MIC) {
3347 /* enable digital Mic */
3348 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3349 ca0132_set_dmic(codec, 1);
3350 ca0132_mic_boost_set(codec, 0);
3351 /* set voice focus */
3352 ca0132_effects_set(codec, VOICE_FOCUS,
3353 spec->effects_switch
3354 [VOICE_FOCUS - EFFECT_START_NID]);
3355 } else {
3356 /* disable digital Mic */
3357 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3358 ca0132_set_dmic(codec, 0);
3359 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3360 /* disable voice focus */
3361 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3362 }
3363
664c7155 3364 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3365
3366 return 0;
3367}
3368
a7e76271
IM		 3369/*
3370 * Check if VNODE settings take effect immediately.
3371 */
3372static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3373 hda_nid_t vnid,
3374 hda_nid_t *shared_nid)
3375{
3376 struct ca0132_spec *spec = codec->spec;
3377 hda_nid_t nid;
a7e76271
IM		 3378
3379 switch (vnid) {
3380 case VNID_SPK:
3381 nid = spec->shared_out_nid;
a7e76271
IM		 3382 break;
3383 case VNID_MIC:
3384 nid = spec->shared_mic_nid;
a7e76271
IM		 3385 break;
3386 default:
9a0869f4 3387 return false;
a7e76271
IM		 3388 }
3389
9a0869f4 3390 if (shared_nid)
a7e76271
IM		 3391 *shared_nid = nid;
3392
9a0869f4 3393 return true;
a7e76271
IM		 3394}
3395
3396/*
3397* The following functions are control change helpers.
3398* They return 0 if no changed. Return 1 if changed.
3399*/
3400static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3401{
3402 struct ca0132_spec *spec = codec->spec;
3403 unsigned int tmp;
3404
3405 /* based on CrystalVoice state to enable VoiceFX. */
3406 if (enable) {
3407 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3408 FLOAT_ONE : FLOAT_ZERO;
3409 } else {
3410 tmp = FLOAT_ZERO;
3411 }
3412
3413 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3414 ca0132_voicefx.reqs[0], tmp);
3415
3416 return 1;
3417}
3418
5aaca44d
IM		 3419/*
3420 * Set the effects parameters
3421 */
3422static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3423{
3424 struct ca0132_spec *spec = codec->spec;
3425 unsigned int on;
3426 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3427 int err = 0;
3428 int idx = nid - EFFECT_START_NID;
3429
3430 if ((idx < 0) || (idx >= num_fx))
3431 return 0; /* no changed */
3432
3433 /* for out effect, qualify with PE */
3434 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3435 /* if PE if off, turn off out effects. */
3436 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3437 val = 0;
3438 }
3439
3440 /* for in effect, qualify with CrystalVoice */
3441 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3442 /* if CrystalVoice if off, turn off in effects. */
3443 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3444 val = 0;
3445
3446 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3447 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3448 val = 0;
3449 }
3450
4e76a883 3451 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 3452 nid, val);
3453
3454 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3455 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3456 ca0132_effects[idx].reqs[0], on);
3457
3458 if (err < 0)
3459 return 0; /* no changed */
3460
3461 return 1;
3462}
3463
a7e76271
IM		 3464/*
3465 * Turn on/off Playback Enhancements
3466 */
3467static int ca0132_pe_switch_set(struct hda_codec *codec)
3468{
3469 struct ca0132_spec *spec = codec->spec;
3470 hda_nid_t nid;
3471 int i, ret = 0;
3472
4e76a883 3473 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 3474 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3475
3476 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3477 nid = OUT_EFFECT_START_NID;
3478 /* PE affects all out effects */
3479 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3480 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3481
3482 return ret;
3483}
3484
5aaca44d
IM		 3485/* Check if Mic1 is streaming, if so, stop streaming */
3486static int stop_mic1(struct hda_codec *codec)
3487{
3488 struct ca0132_spec *spec = codec->spec;
3489 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3490 AC_VERB_GET_CONV, 0);
3491 if (oldval != 0)
3492 snd_hda_codec_write(codec, spec->adcs[0], 0,
3493 AC_VERB_SET_CHANNEL_STREAMID,
3494 0);
3495 return oldval;
3496}
3497
3498/* Resume Mic1 streaming if it was stopped. */
3499static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3500{
3501 struct ca0132_spec *spec = codec->spec;
3502 /* Restore the previous stream and channel */
3503 if (oldval != 0)
3504 snd_hda_codec_write(codec, spec->adcs[0], 0,
3505 AC_VERB_SET_CHANNEL_STREAMID,
3506 oldval);
3507}
3508
3509/*
a7e76271 3510 * Turn on/off CrystalVoice
5aaca44d 3511 */
a7e76271
IM		 3512static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3513{
3514 struct ca0132_spec *spec = codec->spec;
3515 hda_nid_t nid;
3516 int i, ret = 0;
3517 unsigned int oldval;
3518
4e76a883 3519 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 3520 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3521
3522 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3523 nid = IN_EFFECT_START_NID;
3524 /* CrystalVoice affects all in effects */
3525 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3526 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3527
3528 /* including VoiceFX */
3529 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3530
3531 /* set correct vipsource */
3532 oldval = stop_mic1(codec);
3533 ret |= ca0132_set_vipsource(codec, 1);
3534 resume_mic1(codec, oldval);
3535 return ret;
3536}
3537
5aaca44d
IM		 3538static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3539{
3540 struct ca0132_spec *spec = codec->spec;
3541 int ret = 0;
3542
3543 if (val) /* on */
3544 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3545 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3546 else /* off */
3547 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3548 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3549
3550 return ret;
3551}
3552
a7e76271
IM		 3553static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3554 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3555{
a7e76271
IM		 3556 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3557 hda_nid_t nid = get_amp_nid(kcontrol);
3558 hda_nid_t shared_nid = 0;
3559 bool effective;
3560 int ret = 0;
95c6e9cb 3561 struct ca0132_spec *spec = codec->spec;
a7e76271 3562 int auto_jack;
95c6e9cb 3563
a7e76271
IM		 3564 if (nid == VNID_HP_SEL) {
3565 auto_jack =
3566 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3567 if (!auto_jack)
3568 ca0132_select_out(codec);
3569 return 1;
3570 }
95c6e9cb 3571
a7e76271
IM		 3572 if (nid == VNID_AMIC1_SEL) {
3573 auto_jack =
3574 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3575 if (!auto_jack)
3576 ca0132_select_mic(codec);
3577 return 1;
3578 }
95c6e9cb 3579
a7e76271
IM		 3580 if (nid == VNID_HP_ASEL) {
3581 ca0132_select_out(codec);
3582 return 1;
3583 }
95c6e9cb 3584
a7e76271
IM		 3585 if (nid == VNID_AMIC1_ASEL) {
3586 ca0132_select_mic(codec);
3587 return 1;
95c6e9cb 3588 }
a7e76271
IM		 3589
3590 /* if effective conditions, then update hw immediately. */
3591 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3592 if (effective) {
3593 int dir = get_amp_direction(kcontrol);
3594 int ch = get_amp_channels(kcontrol);
3595 unsigned long pval;
3596
3597 mutex_lock(&codec->control_mutex);
3598 pval = kcontrol->private_value;
3599 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3600 0, dir);
3601 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3602 kcontrol->private_value = pval;
3603 mutex_unlock(&codec->control_mutex);
95c6e9cb 3604 }
95c6e9cb 3605
a7e76271 3606 return ret;
95c6e9cb 3607}
a7e76271 3608/* End of control change helpers. */
95c6e9cb 3609
a7e76271
IM		 3610static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3611 struct snd_ctl_elem_info *uinfo)
3612{
a9291f46 3613 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 3614
3615 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3616 uinfo->count = 1;
3617 uinfo->value.enumerated.items = items;
3618 if (uinfo->value.enumerated.item >= items)
3619 uinfo->value.enumerated.item = items - 1;
3620 strcpy(uinfo->value.enumerated.name,
3621 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3622 return 0;
3623}
95c6e9cb 3624
a7e76271 3625static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3626 struct snd_ctl_elem_value *ucontrol)
3627{
3628 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3629 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3630
a7e76271 3631 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3632 return 0;
3633}
3634
a7e76271 3635static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3636 struct snd_ctl_elem_value *ucontrol)
3637{
3638 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3639 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3640 int i, err = 0;
3641 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 3642
a9291f46 3643 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 3644 return 0;
3645
4e76a883 3646 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 3647 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3648
a7e76271
IM		 3649 /*
3650 * Idx 0 is default.
3651 * Default needs to qualify with CrystalVoice state.
3652 */
3653 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3654 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3655 ca0132_voicefx.reqs[i],
3656 ca0132_voicefx_presets[sel].vals[i]);
3657 if (err < 0)
3658 break;
3659 }
95c6e9cb 3660
a7e76271
IM		 3661 if (err >= 0) {
3662 spec->voicefx_val = sel;
3663 /* enable voice fx */
3664 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3665 }
95c6e9cb 3666
a7e76271 3667 return 1;
95c6e9cb
IM		 3668}
3669
a7e76271
IM		 3670static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3671 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3672{
3673 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3674 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3675 hda_nid_t nid = get_amp_nid(kcontrol);
3676 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3677 long *valp = ucontrol->value.integer.value;
3678
a7e76271
IM		 3679 /* vnode */
3680 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3681 if (ch & 1) {
3682 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3683 valp++;
3684 }
3685 if (ch & 2) {
3686 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3687 valp++;
3688 }
3689 return 0;
3690 }
3691
3692 /* effects, include PE and CrystalVoice */
3693 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3694 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3695 return 0;
3696 }
3697
3698 /* mic boost */
3699 if (nid == spec->input_pins[0]) {
3700 *valp = spec->cur_mic_boost;
3701 return 0;
3702 }
3703
95c6e9cb
IM		 3704 return 0;
3705}
3706
a7e76271
IM		 3707static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3708 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3709{
3710 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3711 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3712 hda_nid_t nid = get_amp_nid(kcontrol);
3713 int ch = get_amp_channels(kcontrol);
95c6e9cb 3714 long *valp = ucontrol->value.integer.value;
a7e76271 3715 int changed = 1;
95c6e9cb 3716
4e76a883 3717 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 3718 nid, *valp);
95c6e9cb
IM		 3719
3720 snd_hda_power_up(codec);
a7e76271
IM		 3721 /* vnode */
3722 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3723 if (ch & 1) {
3724 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3725 valp++;
3726 }
3727 if (ch & 2) {
3728 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3729 valp++;
3730 }
3731 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3732 goto exit;
3733 }
95c6e9cb 3734
a7e76271
IM		 3735 /* PE */
3736 if (nid == PLAY_ENHANCEMENT) {
3737 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3738 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3739 goto exit;
a7e76271 3740 }
95c6e9cb 3741
a7e76271
IM		 3742 /* CrystalVoice */
3743 if (nid == CRYSTAL_VOICE) {
3744 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3745 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3746 goto exit;
a7e76271 3747 }
95c6e9cb 3748
a7e76271
IM		 3749 /* out and in effects */
3750 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3751 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3752 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3753 changed = ca0132_effects_set(codec, nid, *valp);
3754 goto exit;
3755 }
3756
3757 /* mic boost */
3758 if (nid == spec->input_pins[0]) {
3759 spec->cur_mic_boost = *valp;
3760
3761 /* Mic boost does not apply to Digital Mic */
3762 if (spec->cur_mic_type != DIGITAL_MIC)
3763 changed = ca0132_mic_boost_set(codec, *valp);
3764 goto exit;
3765 }
95c6e9cb 3766
a7e76271 3767exit:
95c6e9cb 3768 snd_hda_power_down(codec);
a7e76271 3769 return changed;
95c6e9cb
IM		 3770}
3771
a7e76271
IM		 3772/*
3773 * Volume related
3774 */
3775static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3776 struct snd_ctl_elem_info *uinfo)
3777{
3778 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3779 struct ca0132_spec *spec = codec->spec;
3780 hda_nid_t nid = get_amp_nid(kcontrol);
3781 int ch = get_amp_channels(kcontrol);
3782 int dir = get_amp_direction(kcontrol);
3783 unsigned long pval;
3784 int err;
3785
3786 switch (nid) {
3787 case VNID_SPK:
3788 /* follow shared_out info */
3789 nid = spec->shared_out_nid;
3790 mutex_lock(&codec->control_mutex);
3791 pval = kcontrol->private_value;
3792 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3793 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3794 kcontrol->private_value = pval;
3795 mutex_unlock(&codec->control_mutex);
3796 break;
3797 case VNID_MIC:
3798 /* follow shared_mic info */
3799 nid = spec->shared_mic_nid;
3800 mutex_lock(&codec->control_mutex);
3801 pval = kcontrol->private_value;
3802 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3803 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3804 kcontrol->private_value = pval;
3805 mutex_unlock(&codec->control_mutex);
3806 break;
3807 default:
3808 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3809 }
3810 return err;
3811}
3812
3813static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3814 struct snd_ctl_elem_value *ucontrol)
3815{
3816 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3817 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3818 hda_nid_t nid = get_amp_nid(kcontrol);
3819 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3820 long *valp = ucontrol->value.integer.value;
3821
a7e76271
IM		 3822 /* store the left and right volume */
3823 if (ch & 1) {
3824 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3825 valp++;
3826 }
3827 if (ch & 2) {
3828 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3829 valp++;
3830 }
95c6e9cb
IM		 3831 return 0;
3832}
3833
a7e76271 3834static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3835 struct snd_ctl_elem_value *ucontrol)
3836{
3837 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3838 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3839 hda_nid_t nid = get_amp_nid(kcontrol);
3840 int ch = get_amp_channels(kcontrol);
95c6e9cb 3841 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3842 hda_nid_t shared_nid = 0;
3843 bool effective;
3844 int changed = 1;
3845
3846 /* store the left and right volume */
3847 if (ch & 1) {
3848 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3849 valp++;
3850 }
3851 if (ch & 2) {
3852 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3853 valp++;
3854 }
95c6e9cb 3855
a7e76271
IM		 3856 /* if effective conditions, then update hw immediately. */
3857 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3858 if (effective) {
3859 int dir = get_amp_direction(kcontrol);
3860 unsigned long pval;
3861
3862 snd_hda_power_up(codec);
3863 mutex_lock(&codec->control_mutex);
3864 pval = kcontrol->private_value;
3865 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3866 0, dir);
3867 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3868 kcontrol->private_value = pval;
3869 mutex_unlock(&codec->control_mutex);
3870 snd_hda_power_down(codec);
3871 }
95c6e9cb 3872
a7e76271 3873 return changed;
95c6e9cb
IM		 3874}
3875
a7e76271
IM		 3876static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3877 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3878{
a7e76271
IM		 3879 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3880 struct ca0132_spec *spec = codec->spec;
3881 hda_nid_t nid = get_amp_nid(kcontrol);
3882 int ch = get_amp_channels(kcontrol);
3883 int dir = get_amp_direction(kcontrol);
3884 unsigned long pval;
3885 int err;
3886
3887 switch (nid) {
3888 case VNID_SPK:
3889 /* follow shared_out tlv */
3890 nid = spec->shared_out_nid;
3891 mutex_lock(&codec->control_mutex);
3892 pval = kcontrol->private_value;
3893 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3894 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3895 kcontrol->private_value = pval;
3896 mutex_unlock(&codec->control_mutex);
3897 break;
3898 case VNID_MIC:
3899 /* follow shared_mic tlv */
3900 nid = spec->shared_mic_nid;
3901 mutex_lock(&codec->control_mutex);
3902 pval = kcontrol->private_value;
3903 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3904 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3905 kcontrol->private_value = pval;
3906 mutex_unlock(&codec->control_mutex);
3907 break;
3908 default:
3909 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3910 }
3911 return err;
95c6e9cb
IM		 3912}
3913
a7e76271
IM		 3914static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3915 const char *pfx, int dir)
95c6e9cb 3916{
975cc02a 3917 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 3918 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3919 struct snd_kcontrol_new knew =
a7e76271
IM		 3920 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3921 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3922 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3923}
3924
a7e76271 3925static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3926{
3927 struct snd_kcontrol_new knew =
a7e76271
IM		 3928 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3929 VOICEFX, 1, 0, HDA_INPUT);
3930 knew.info = ca0132_voicefx_info;
3931 knew.get = ca0132_voicefx_get;
3932 knew.put = ca0132_voicefx_put;
3933 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3934}
3935
a7e76271
IM		 3936/*
3937 * When changing Node IDs for Mixer Controls below, make sure to update
3938 * Node IDs in ca0132_config() as well.
3939 */
3940static struct snd_kcontrol_new ca0132_mixer[] = {
3941 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3942 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3943 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3944 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3945 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3946 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3947 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3948 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3949 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3950 0x12, 1, HDA_INPUT),
3951 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3952 VNID_HP_SEL, 1, HDA_OUTPUT),
3953 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3954 VNID_AMIC1_SEL, 1, HDA_INPUT),
3955 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3956 VNID_HP_ASEL, 1, HDA_OUTPUT),
3957 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3958 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3959 { } /* end */
3960};
3961
e90f29e4
IM		 3962static int ca0132_build_controls(struct hda_codec *codec)
3963{
3964 struct ca0132_spec *spec = codec->spec;
3965 int i, num_fx;
3966 int err = 0;
3967
3968 /* Add Mixer controls */
3969 for (i = 0; i < spec->num_mixers; i++) {
3970 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3971 if (err < 0)
3972 return err;
3973 }
3974
3975 /* Add in and out effects controls.
3976 * VoiceFX, PE and CrystalVoice are added separately.
3977 */
3978 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3979 for (i = 0; i < num_fx; i++) {
3980 err = add_fx_switch(codec, ca0132_effects[i].nid,
3981 ca0132_effects[i].name,
3982 ca0132_effects[i].direct);
3983 if (err < 0)
3984 return err;
3985 }
3986
3987 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3988 if (err < 0)
3989 return err;
3990
3991 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3992 if (err < 0)
3993 return err;
3994
3995 add_voicefx(codec);
3996
3997#ifdef ENABLE_TUNING_CONTROLS
3998 add_tuning_ctls(codec);
3999#endif
4000
4001 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
4002 if (err < 0)
4003 return err;
4004
4005 if (spec->dig_out) {
4006 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4007 spec->dig_out);
4008 if (err < 0)
4009 return err;
4010 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4011 if (err < 0)
4012 return err;
4013 /* spec->multiout.share_spdif = 1; */
4014 }
4015
4016 if (spec->dig_in) {
4017 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4018 if (err < 0)
4019 return err;
4020 }
4021 return 0;
4022}
4023
a7e76271 4024/*
e90f29e4 4025 * PCM
a7e76271 4026 */
071f1344 4027static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 4028 .substreams = 1,
4029 .channels_min = 2,
825315bc 4030 .channels_max = 6,
a7e76271 4031 .ops = {
a7e76271 4032 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 4033 .cleanup = ca0132_playback_pcm_cleanup,
4034 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 4035 },
4036};
4037
071f1344 4038static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 4039 .substreams = 1,
4040 .channels_min = 2,
4041 .channels_max = 2,
825315bc
IM		 4042 .ops = {
4043 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 4044 .cleanup = ca0132_capture_pcm_cleanup,
4045 .get_delay = ca0132_capture_pcm_delay,
825315bc 4046 },
a7e76271
IM		 4047};
4048
071f1344 4049static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 4050 .substreams = 1,
4051 .channels_min = 2,
4052 .channels_max = 2,
4053 .ops = {
4054 .open = ca0132_dig_playback_pcm_open,
4055 .close = ca0132_dig_playback_pcm_close,
4056 .prepare = ca0132_dig_playback_pcm_prepare,
4057 .cleanup = ca0132_dig_playback_pcm_cleanup
4058 },
4059};
4060
071f1344 4061static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 4062 .substreams = 1,
4063 .channels_min = 2,
4064 .channels_max = 2,
4065};
4066
4067static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4068{
4069 struct ca0132_spec *spec = codec->spec;
bbbc7e85 4070 struct hda_pcm *info;
a7e76271 4071
bbbc7e85
TI		 4072 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4073 if (!info)
4074 return -ENOMEM;
a7e76271
IM		 4075 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4076 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4077 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4078 spec->multiout.max_channels;
4079 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4080 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 4081 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 4082
bbbc7e85
TI		 4083 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4084 if (!info)
4085 return -ENOMEM;
825315bc
IM		 4086 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4087 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4088 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
825315bc 4089
bbbc7e85
TI		 4090 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4091 if (!info)
4092 return -ENOMEM;
825315bc
IM		 4093 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4094 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4095 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 4096
a7e76271
IM		 4097 if (!spec->dig_out && !spec->dig_in)
4098 return 0;
4099
bbbc7e85
TI		 4100 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4101 if (!info)
4102 return -ENOMEM;
a7e76271
IM		 4103 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4104 if (spec->dig_out) {
4105 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4106 ca0132_pcm_digital_playback;
4107 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4108 }
4109 if (spec->dig_in) {
4110 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4111 ca0132_pcm_digital_capture;
4112 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4113 }
95c6e9cb 4114
a7e76271 4115 return 0;
95c6e9cb
IM		 4116}
4117
441aa6a0
IM		 4118static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4119{
4120 if (pin) {
a0c041cb 4121 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 4122 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4123 snd_hda_codec_write(codec, pin, 0,
4124 AC_VERB_SET_AMP_GAIN_MUTE,
4125 AMP_OUT_UNMUTE);
4126 }
4127 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4128 snd_hda_codec_write(codec, dac, 0,
4129 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4130}
4131
4132static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4133{
4134 if (pin) {
a0c041cb 4135 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 4136 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4137 snd_hda_codec_write(codec, pin, 0,
4138 AC_VERB_SET_AMP_GAIN_MUTE,
4139 AMP_IN_UNMUTE(0));
4140 }
4141 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4142 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4143 AMP_IN_UNMUTE(0));
4144
4145 /* init to 0 dB and unmute. */
4146 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4147 HDA_AMP_VOLMASK, 0x5a);
4148 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4149 HDA_AMP_MUTE, 0);
4150 }
4151}
4152
5aaca44d
IM		 4153static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4154{
4155 unsigned int caps;
4156
4157 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4158 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4159 snd_hda_override_amp_caps(codec, nid, dir, caps);
4160}
4161
4162/*
4163 * Switch between Digital built-in mic and analog mic.
4164 */
4165static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4166{
4167 struct ca0132_spec *spec = codec->spec;
4168 unsigned int tmp;
4169 u8 val;
4170 unsigned int oldval;
4171
4e76a883 4172 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 4173
4174 oldval = stop_mic1(codec);
4175 ca0132_set_vipsource(codec, 0);
4176 if (enable) {
4177 /* set DMic input as 2-ch */
4178 tmp = FLOAT_TWO;
4179 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4180
4181 val = spec->dmic_ctl;
4182 val |= 0x80;
4183 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4184 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4185
4186 if (!(spec->dmic_ctl & 0x20))
4187 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4188 } else {
4189 /* set AMic input as mono */
4190 tmp = FLOAT_ONE;
4191 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4192
4193 val = spec->dmic_ctl;
4194 /* clear bit7 and bit5 to disable dmic */
4195 val &= 0x5f;
4196 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4197 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4198
4199 if (!(spec->dmic_ctl & 0x20))
4200 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4201 }
4202 ca0132_set_vipsource(codec, 1);
4203 resume_mic1(codec, oldval);
4204}
4205
4206/*
4207 * Initialization for Digital Mic.
4208 */
4209static void ca0132_init_dmic(struct hda_codec *codec)
4210{
4211 struct ca0132_spec *spec = codec->spec;
4212 u8 val;
4213
4214 /* Setup Digital Mic here, but don't enable.
4215 * Enable based on jack detect.
4216 */
4217
4218 /* MCLK uses MPIO1, set to enable.
4219 * Bit 2-0: MPIO select
4220 * Bit 3: set to disable
4221 * Bit 7-4: reserved
4222 */
4223 val = 0x01;
4224 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4225 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4226
4227 /* Data1 uses MPIO3. Data2 not use
4228 * Bit 2-0: Data1 MPIO select
4229 * Bit 3: set disable Data1
4230 * Bit 6-4: Data2 MPIO select
4231 * Bit 7: set disable Data2
4232 */
4233 val = 0x83;
4234 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4235 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4236
4237 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4238 * Bit 3-0: Channel mask
4239 * Bit 4: set for 48KHz, clear for 32KHz
4240 * Bit 5: mode
4241 * Bit 6: set to select Data2, clear for Data1
4242 * Bit 7: set to enable DMic, clear for AMic
4243 */
4244 val = 0x23;
4245 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4246 spec->dmic_ctl = val;
4247 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4248 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4249}
4250
4251/*
4252 * Initialization for Analog Mic 2
4253 */
4254static void ca0132_init_analog_mic2(struct hda_codec *codec)
4255{
4256 struct ca0132_spec *spec = codec->spec;
4257
4258 mutex_lock(&spec->chipio_mutex);
4259 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4260 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4261 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4262 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4263 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4264 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4265 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4266 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4267 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4268 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4269 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4270 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4271 mutex_unlock(&spec->chipio_mutex);
4272}
4273
4274static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4275{
4276 struct ca0132_spec *spec = codec->spec;
4277 int i;
5aaca44d 4278
4e76a883 4279 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 4280 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 4281
4282 for (i = 0; i < spec->multiout.num_dacs; i++)
4283 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4284
4285 for (i = 0; i < spec->num_outputs; i++)
4286 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4287
4288 for (i = 0; i < spec->num_inputs; i++) {
4289 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4290 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4291 }
4292}
4293
4294/*
4295 * Setup default parameters for DSP
4296 */
4297static void ca0132_setup_defaults(struct hda_codec *codec)
4298{
e8f1bd5d 4299 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4300 unsigned int tmp;
4301 int num_fx;
4302 int idx, i;
4303
e8f1bd5d 4304 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4305 return;
4306
4307 /* out, in effects + voicefx */
4308 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4309 for (idx = 0; idx < num_fx; idx++) {
4310 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4311 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4312 ca0132_effects[idx].reqs[i],
4313 ca0132_effects[idx].def_vals[i]);
4314 }
4315 }
4316
4317 /*remove DSP headroom*/
4318 tmp = FLOAT_ZERO;
4319 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4320
4321 /*set speaker EQ bypass attenuation*/
4322 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4323
4324 /* set AMic1 and AMic2 as mono mic */
4325 tmp = FLOAT_ONE;
4326 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4327 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4328
4329 /* set AMic1 as CrystalVoice input */
4330 tmp = FLOAT_ONE;
4331 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4332
4333 /* set WUH source */
4334 tmp = FLOAT_TWO;
4335 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4336}
4337
4338/*
4339 * Initialization of flags in chip
4340 */
4341static void ca0132_init_flags(struct hda_codec *codec)
4342{
4343 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4344 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4345 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4346 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4347 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4348 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4349}
4350
4351/*
4352 * Initialization of parameters in chip
4353 */
4354static void ca0132_init_params(struct hda_codec *codec)
4355{
4356 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4357 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4358}
95c6e9cb 4359
e90f29e4
IM		 4360static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4361{
4362 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4363 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4364 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4365 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4366 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4367 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4368
406261ce
IM		 4369 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4370 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 4371 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4372}
4373
4374static bool ca0132_download_dsp_images(struct hda_codec *codec)
4375{
4376 bool dsp_loaded = false;
4377 const struct dsp_image_seg *dsp_os_image;
15e4ba66 4378 const struct firmware *fw_entry;
e90f29e4 4379
6efdd851 4380 if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
e90f29e4
IM		 4381 return false;
4382
15e4ba66 4383 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 4384 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 4385 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 4386 goto exit_download;
4387 }
4388
e90f29e4
IM		 4389 dsp_loaded = dspload_wait_loaded(codec);
4390
d1d28500 4391exit_download:
15e4ba66
TI		 4392 release_firmware(fw_entry);
4393
e90f29e4
IM		 4394 return dsp_loaded;
4395}
4396
4397static void ca0132_download_dsp(struct hda_codec *codec)
4398{
4399 struct ca0132_spec *spec = codec->spec;
4400
9a0869f4
TI		 4401#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4402 return; /* NOP */
4403#endif
e90f29e4 4404
e24aa0a4
TI		 4405 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4406 return; /* don't retry failures */
4407
b714a710
DR		 4408 chipio_enable_clocks(codec);
4409 spec->dsp_state = DSP_DOWNLOADING;
4410 if (!ca0132_download_dsp_images(codec))
4411 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4412 else
4413 spec->dsp_state = DSP_DOWNLOADED;
e90f29e4
IM		 4414
4415 if (spec->dsp_state == DSP_DOWNLOADED)
4416 ca0132_set_dsp_msr(codec, true);
4417}
4418
f8fb1170
TI		 4419static void ca0132_process_dsp_response(struct hda_codec *codec,
4420 struct hda_jack_callback *callback)
e90f29e4
IM		 4421{
4422 struct ca0132_spec *spec = codec->spec;
4423
4e76a883 4424 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 4425 if (spec->wait_scp) {
4426 if (dspio_get_response_data(codec) >= 0)
4427 spec->wait_scp = 0;
4428 }
4429
4430 dspio_clear_response_queue(codec);
4431}
4432
f8fb1170 4433static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 4434{
993884f6 4435 struct ca0132_spec *spec = codec->spec;
2ebab40e 4436 struct hda_jack_tbl *tbl;
e90f29e4 4437
f8fb1170
TI		 4438 /* Delay enabling the HP amp, to let the mic-detection
4439 * state machine run.
4440 */
4441 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 4442 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 4443 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4444 if (tbl)
4445 tbl->block_report = 1;
f8fb1170
TI		 4446}
4447
4448static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4449{
4450 ca0132_select_mic(codec);
4451}
4452
4453static void ca0132_init_unsol(struct hda_codec *codec)
4454{
d5c016b5
GM		 4455 struct ca0132_spec *spec = codec->spec;
4456 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4457 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 4458 amic_callback);
4459 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4460 ca0132_process_dsp_response);
e90f29e4
IM		 4461}
4462
5aaca44d
IM		 4463/*
4464 * Verbs tables.
4465 */
4466
4467/* Sends before DSP download. */
4468static struct hda_verb ca0132_base_init_verbs[] = {
4469 /*enable ct extension*/
4470 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 4471 {}
4472};
4473
4474/* Send at exit. */
4475static struct hda_verb ca0132_base_exit_verbs[] = {
4476 /*set afg to D3*/
4477 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4478 /*disable ct extension*/
4479 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4480 {}
4481};
4482
4483/* Other verbs tables. Sends after DSP download. */
4484static struct hda_verb ca0132_init_verbs0[] = {
4485 /* chip init verbs */
4486 {0x15, 0x70D, 0xF0},
4487 {0x15, 0x70E, 0xFE},
4488 {0x15, 0x707, 0x75},
4489 {0x15, 0x707, 0xD3},
4490 {0x15, 0x707, 0x09},
4491 {0x15, 0x707, 0x53},
4492 {0x15, 0x707, 0xD4},
4493 {0x15, 0x707, 0xEF},
4494 {0x15, 0x707, 0x75},
4495 {0x15, 0x707, 0xD3},
4496 {0x15, 0x707, 0x09},
4497 {0x15, 0x707, 0x02},
4498 {0x15, 0x707, 0x37},
4499 {0x15, 0x707, 0x78},
4500 {0x15, 0x53C, 0xCE},
4501 {0x15, 0x575, 0xC9},
4502 {0x15, 0x53D, 0xCE},
4503 {0x15, 0x5B7, 0xC9},
4504 {0x15, 0x70D, 0xE8},
4505 {0x15, 0x70E, 0xFE},
4506 {0x15, 0x707, 0x02},
4507 {0x15, 0x707, 0x68},
4508 {0x15, 0x707, 0x62},
4509 {0x15, 0x53A, 0xCE},
4510 {0x15, 0x546, 0xC9},
4511 {0x15, 0x53B, 0xCE},
4512 {0x15, 0x5E8, 0xC9},
4513 {0x15, 0x717, 0x0D},
4514 {0x15, 0x718, 0x20},
4515 {}
4516};
4517
95c6e9cb
IM		 4518static void ca0132_init_chip(struct hda_codec *codec)
4519{
4520 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4521 int num_fx;
4522 int i;
4523 unsigned int on;
95c6e9cb
IM		 4524
4525 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 4526
4527 spec->cur_out_type = SPEAKER_OUT;
4528 spec->cur_mic_type = DIGITAL_MIC;
4529 spec->cur_mic_boost = 0;
4530
4531 for (i = 0; i < VNODES_COUNT; i++) {
4532 spec->vnode_lvol[i] = 0x5a;
4533 spec->vnode_rvol[i] = 0x5a;
4534 spec->vnode_lswitch[i] = 0;
4535 spec->vnode_rswitch[i] = 0;
4536 }
4537
4538 /*
4539 * Default states for effects are in ca0132_effects[].
4540 */
4541 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4542 for (i = 0; i < num_fx; i++) {
4543 on = (unsigned int)ca0132_effects[i].reqs[0];
4544 spec->effects_switch[i] = on ? 1 : 0;
4545 }
4546
4547 spec->voicefx_val = 0;
4548 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4549 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4550
44f0c978
IM		 4551#ifdef ENABLE_TUNING_CONTROLS
4552 ca0132_init_tuning_defaults(codec);
4553#endif
95c6e9cb
IM		 4554}
4555
4556static void ca0132_exit_chip(struct hda_codec *codec)
4557{
4558 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 4559
4560 if (dspload_is_loaded(codec))
4561 dsp_reset(codec);
95c6e9cb
IM		 4562}
4563
4564static int ca0132_init(struct hda_codec *codec)
4565{
4566 struct ca0132_spec *spec = codec->spec;
4567 struct auto_pin_cfg *cfg = &spec->autocfg;
4568 int i;
4569
e24aa0a4
TI		 4570 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4571 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 4572 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 4573
664c7155 4574 snd_hda_power_up_pm(codec);
5aaca44d 4575
f8fb1170
TI		 4576 ca0132_init_unsol(codec);
4577
5aaca44d
IM		 4578 ca0132_init_params(codec);
4579 ca0132_init_flags(codec);
4580 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf 4581 ca0132_download_dsp(codec);
5aaca44d
IM		 4582 ca0132_refresh_widget_caps(codec);
4583 ca0132_setup_defaults(codec);
4584 ca0132_init_analog_mic2(codec);
4585 ca0132_init_dmic(codec);
4586
4587 for (i = 0; i < spec->num_outputs; i++)
4588 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4589
95c6e9cb
IM		 4590 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4591
4592 for (i = 0; i < spec->num_inputs; i++)
4593 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4594
4595 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4596
d5c016b5
GM		 4597 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4598 snd_hda_sequence_write(codec, spec->spec_init_verbs);
5aaca44d
IM		 4599
4600 ca0132_select_out(codec);
4601 ca0132_select_mic(codec);
4602
a73d511c
IM		 4603 snd_hda_jack_report_sync(codec);
4604
664c7155 4605 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 4606
4607 return 0;
4608}
4609
95c6e9cb
IM		 4610static void ca0132_free(struct hda_codec *codec)
4611{
5aaca44d
IM		 4612 struct ca0132_spec *spec = codec->spec;
4613
993884f6 4614 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d
IM		 4615 snd_hda_power_up(codec);
4616 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4617 ca0132_exit_chip(codec);
5aaca44d 4618 snd_hda_power_down(codec);
d5c016b5 4619 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 4620 kfree(codec->spec);
4621}
4622
071f1344 4623static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 4624 .build_controls = ca0132_build_controls,
4625 .build_pcms = ca0132_build_pcms,
4626 .init = ca0132_init,
4627 .free = ca0132_free,
f8fb1170 4628 .unsol_event = snd_hda_jack_unsol_event,
95c6e9cb
IM		 4629};
4630
441aa6a0
IM		 4631static void ca0132_config(struct hda_codec *codec)
4632{
4633 struct ca0132_spec *spec = codec->spec;
4634 struct auto_pin_cfg *cfg = &spec->autocfg;
4635
4636 spec->dacs[0] = 0x2;
4637 spec->dacs[1] = 0x3;
4638 spec->dacs[2] = 0x4;
4639
4640 spec->multiout.dac_nids = spec->dacs;
4641 spec->multiout.num_dacs = 3;
4642 spec->multiout.max_channels = 2;
4643
d5c016b5
GM		 4644 if (spec->quirk == QUIRK_ALIENWARE) {
4645 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 4646 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4647
4648 spec->num_outputs = 2;
4649 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4650 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 4651 spec->shared_out_nid = 0x2;
4652 spec->unsol_tag_hp = 0x0f;
4653
4654 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4655 spec->adcs[1] = 0x8; /* analog mic2 */
4656 spec->adcs[2] = 0xa; /* what u hear */
4657
4658 spec->num_inputs = 3;
4659 spec->input_pins[0] = 0x12;
4660 spec->input_pins[1] = 0x11;
4661 spec->input_pins[2] = 0x13;
4662 spec->shared_mic_nid = 0x7;
4663 spec->unsol_tag_amic1 = 0x11;
4664 } else {
4665 spec->num_outputs = 2;
4666 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4667 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 4668 spec->shared_out_nid = 0x2;
4669 spec->unsol_tag_hp = spec->out_pins[1];
4670
4671 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4672 spec->adcs[1] = 0x8; /* analog mic2 */
4673 spec->adcs[2] = 0xa; /* what u hear */
4674
4675 spec->num_inputs = 3;
4676 spec->input_pins[0] = 0x12;
4677 spec->input_pins[1] = 0x11;
4678 spec->input_pins[2] = 0x13;
4679 spec->shared_mic_nid = 0x7;
4680 spec->unsol_tag_amic1 = spec->input_pins[0];
4681
4682 /* SPDIF I/O */
4683 spec->dig_out = 0x05;
4684 spec->multiout.dig_out_nid = spec->dig_out;
4685 cfg->dig_out_pins[0] = 0x0c;
4686 cfg->dig_outs = 1;
4687 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4688 spec->dig_in = 0x09;
4689 cfg->dig_in_pin = 0x0e;
4690 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
d5c016b5 4691 }
441aa6a0
IM		 4692}
4693
d5c016b5
GM		 4694static int ca0132_prepare_verbs(struct hda_codec *codec)
4695{
4696/* Verbs + terminator (an empty element) */
4697#define NUM_SPEC_VERBS 4
4698 struct ca0132_spec *spec = codec->spec;
4699
4700 spec->chip_init_verbs = ca0132_init_verbs0;
4701 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4702 if (!spec->spec_init_verbs)
4703 return -ENOMEM;
4704
4705 /* HP jack autodetection */
4706 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4707 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4708 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4709
4710 /* MIC1 jack autodetection */
4711 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4712 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4713 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4714
4715 /* config EAPD */
4716 spec->spec_init_verbs[2].nid = 0x0b;
4717 spec->spec_init_verbs[2].param = 0x78D;
4718 spec->spec_init_verbs[2].verb = 0x00;
4719
4720 /* Previously commented configuration */
4721 /*
4722 spec->spec_init_verbs[3].nid = 0x0b;
4723 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4724 spec->spec_init_verbs[3].verb = 0x02;
4725
4726 spec->spec_init_verbs[4].nid = 0x10;
4727 spec->spec_init_verbs[4].param = 0x78D;
4728 spec->spec_init_verbs[4].verb = 0x02;
4729
4730 spec->spec_init_verbs[5].nid = 0x10;
4731 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4732 spec->spec_init_verbs[5].verb = 0x02;
4733 */
4734
4735 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4736 return 0;
4737}
4738
95c6e9cb
IM		 4739static int patch_ca0132(struct hda_codec *codec)
4740{
4741 struct ca0132_spec *spec;
a73d511c 4742 int err;
d5c016b5 4743 const struct snd_pci_quirk *quirk;
95c6e9cb 4744
4e76a883 4745 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 4746
4747 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4748 if (!spec)
4749 return -ENOMEM;
4750 codec->spec = spec;
993884f6 4751 spec->codec = codec;
95c6e9cb 4752
225068ab
TI		 4753 codec->patch_ops = ca0132_patch_ops;
4754 codec->pcm_format_first = 1;
4755 codec->no_sticky_stream = 1;
4756
d5c016b5
GM		 4757 /* Detect codec quirk */
4758 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4759 if (quirk)
4760 spec->quirk = quirk->value;
4761 else
4762 spec->quirk = QUIRK_NONE;
4763
e24aa0a4 4764 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271
IM		 4765 spec->num_mixers = 1;
4766 spec->mixers[0] = ca0132_mixer;
4767
5aaca44d
IM		 4768 spec->base_init_verbs = ca0132_base_init_verbs;
4769 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 4770
993884f6
CCC		 4771 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4772
95c6e9cb
IM		 4773 ca0132_init_chip(codec);
4774
4775 ca0132_config(codec);
4776
d5c016b5
GM		 4777 err = ca0132_prepare_verbs(codec);
4778 if (err < 0)
cc91ceaf 4779 goto error;
d5c016b5 4780
a73d511c
IM		 4781 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4782 if (err < 0)
cc91ceaf 4783 goto error;
a73d511c 4784
95c6e9cb 4785 return 0;
cc91ceaf
TI		 4786
4787 error:
4788 ca0132_free(codec);
4789 return err;
95c6e9cb
IM		 4790}
4791
4792/*
4793 * patch entries
4794 */
b9a94a9c
TI		 4795static struct hda_device_id snd_hda_id_ca0132[] = {
4796 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 4797 {} /* terminator */
4798};
b9a94a9c 4799MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 4800
4801MODULE_LICENSE("GPL");
406261ce 4802MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 4803
d8a766a1 4804static struct hda_codec_driver ca0132_driver = {
b9a94a9c 4805 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 4806};
4807
d8a766a1 4808module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)