[linux-2.6-block.git] / sound / pci / hda / hda_tegra.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *
 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
 */

#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mutex.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/string.h>
#include <linux/pm_runtime.h>

#include <sound/core.h>
#include <sound/initval.h>

#include <sound/hda_codec.h>
#include "hda_controller.h"

/* Defines for Nvidia Tegra HDA support */
#define HDA_BAR0           0x8000

#define HDA_CFG_CMD        0x1004
#define HDA_CFG_BAR0       0x1010

#define HDA_ENABLE_IO_SPACE       (1 << 0)
#define HDA_ENABLE_MEM_SPACE      (1 << 1)
#define HDA_ENABLE_BUS_MASTER     (1 << 2)
#define HDA_ENABLE_SERR           (1 << 8)
#define HDA_DISABLE_INTR          (1 << 10)
#define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
#define HDA_BAR0_FINAL_PROGRAM    (1 << 14)

/* IPFS */
#define HDA_IPFS_CONFIG           0x180
#define HDA_IPFS_EN_FPCI          0x1

#define HDA_IPFS_FPCI_BAR0        0x80
#define HDA_FPCI_BAR0_START       0x40

#define HDA_IPFS_INTR_MASK        0x188
#define HDA_IPFS_EN_INTR          (1 << 16)

/* max number of SDs */
#define NUM_CAPTURE_SD 1
#define NUM_PLAYBACK_SD 1

struct hda_tegra {
	struct azx chip;
	struct device *dev;
	struct clk *hda_clk;
	struct clk *hda2codec_2x_clk;
	struct clk *hda2hdmi_clk;
	void __iomem *regs;
	struct work_struct probe_work;
};

#ifdef CONFIG_PM
static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
module_param(power_save, bint, 0644);
MODULE_PARM_DESC(power_save,
		 "Automatic power-saving timeout (in seconds, 0 = disable).");
#else
#define power_save	0
#endif

static const struct hda_controller_ops hda_tegra_ops; /* nothing special */

static void hda_tegra_init(struct hda_tegra *hda)
{
	u32 v;

	/* Enable PCI access */
	v = readl(hda->regs + HDA_IPFS_CONFIG);
	v |= HDA_IPFS_EN_FPCI;
	writel(v, hda->regs + HDA_IPFS_CONFIG);

	/* Enable MEM/IO space and bus master */
	v = readl(hda->regs + HDA_CFG_CMD);
	v &= ~HDA_DISABLE_INTR;
	v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
		HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
	writel(v, hda->regs + HDA_CFG_CMD);

	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);

	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
	v |= HDA_IPFS_EN_INTR;
	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
}

static int hda_tegra_enable_clocks(struct hda_tegra *data)
{
	int rc;

	rc = clk_prepare_enable(data->hda_clk);
	if (rc)
		return rc;
	rc = clk_prepare_enable(data->hda2codec_2x_clk);
	if (rc)
		goto disable_hda;
	rc = clk_prepare_enable(data->hda2hdmi_clk);
	if (rc)
		goto disable_codec_2x;

	return 0;

disable_codec_2x:
	clk_disable_unprepare(data->hda2codec_2x_clk);
disable_hda:
	clk_disable_unprepare(data->hda_clk);
	return rc;
}

static void hda_tegra_disable_clocks(struct hda_tegra *data)
{
	clk_disable_unprepare(data->hda2hdmi_clk);
	clk_disable_unprepare(data->hda2codec_2x_clk);
	clk_disable_unprepare(data->hda_clk);
}

/*
 * power management
 */
static int __maybe_unused hda_tegra_suspend(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	int rc;

	rc = pm_runtime_force_suspend(dev);
	if (rc < 0)
		return rc;
	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);

	return 0;
}

static int __maybe_unused hda_tegra_resume(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	int rc;

	rc = pm_runtime_force_resume(dev);
	if (rc < 0)
		return rc;
	snd_power_change_state(card, SNDRV_CTL_POWER_D0);

	return 0;
}

static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	struct hdac_bus *bus = azx_bus(chip);

	if (chip && chip->running) {
		azx_stop_chip(chip);
		synchronize_irq(bus->irq);
		azx_enter_link_reset(chip);
	}
	hda_tegra_disable_clocks(hda);

	return 0;
}

static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	int rc;

	rc = hda_tegra_enable_clocks(hda);
	if (rc != 0)
		return rc;
	if (chip && chip->running) {
		hda_tegra_init(hda);
		azx_init_chip(chip, 1);
	}

	return 0;
}

static const struct dev_pm_ops hda_tegra_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
	SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
			   hda_tegra_runtime_resume,
			   NULL)
};

static int hda_tegra_dev_disconnect(struct snd_device *device)
{
	struct azx *chip = device->device_data;

	chip->bus.shutdown = 1;
	return 0;
}

/*
 * destructor
 */
static int hda_tegra_dev_free(struct snd_device *device)
{
	struct azx *chip = device->device_data;
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);

	cancel_work_sync(&hda->probe_work);
	if (azx_bus(chip)->chip_init) {
		azx_stop_all_streams(chip);
		azx_stop_chip(chip);
	}

	azx_free_stream_pages(chip);
	azx_free_streams(chip);
	snd_hdac_bus_exit(azx_bus(chip));

	return 0;
}

static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
{
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	struct hdac_bus *bus = azx_bus(chip);
	struct device *dev = hda->dev;
	struct resource *res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	hda->regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(hda->regs))
		return PTR_ERR(hda->regs);

	bus->remap_addr = hda->regs + HDA_BAR0;
	bus->addr = res->start + HDA_BAR0;

	hda_tegra_init(hda);

	return 0;
}

static int hda_tegra_init_clk(struct hda_tegra *hda)
{
	struct device *dev = hda->dev;

	hda->hda_clk = devm_clk_get(dev, "hda");
	if (IS_ERR(hda->hda_clk)) {
		dev_err(dev, "failed to get hda clock\n");
		return PTR_ERR(hda->hda_clk);
	}
	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
	if (IS_ERR(hda->hda2codec_2x_clk)) {
		dev_err(dev, "failed to get hda2codec_2x clock\n");
		return PTR_ERR(hda->hda2codec_2x_clk);
	}
	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
	if (IS_ERR(hda->hda2hdmi_clk)) {
		dev_err(dev, "failed to get hda2hdmi clock\n");
		return PTR_ERR(hda->hda2hdmi_clk);
	}

	return 0;
}

static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
{
	struct hdac_bus *bus = azx_bus(chip);
	struct snd_card *card = chip->card;
	int err;
	unsigned short gcap;
	int irq_id = platform_get_irq(pdev, 0);
	const char *sname, *drv_name = "tegra-hda";
	struct device_node *np = pdev->dev.of_node;

	err = hda_tegra_init_chip(chip, pdev);
	if (err)
		return err;

	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
			     IRQF_SHARED, KBUILD_MODNAME, chip);
	if (err) {
		dev_err(chip->card->dev,
			"unable to request IRQ %d, disabling device\n",
			irq_id);
		return err;
	}
	bus->irq = irq_id;

	synchronize_irq(bus->irq);

	gcap = azx_readw(chip, GCAP);
	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);

	/* read number of streams from GCAP register instead of using
	 * hardcoded value
	 */
	chip->capture_streams = (gcap >> 8) & 0x0f;
	chip->playback_streams = (gcap >> 12) & 0x0f;
	if (!chip->playback_streams && !chip->capture_streams) {
		/* gcap didn't give any info, switching to old method */
		chip->playback_streams = NUM_PLAYBACK_SD;
		chip->capture_streams = NUM_CAPTURE_SD;
	}
	chip->capture_index_offset = 0;
	chip->playback_index_offset = chip->capture_streams;
	chip->num_streams = chip->playback_streams + chip->capture_streams;

	/* initialize streams */
	err = azx_init_streams(chip);
	if (err < 0) {
		dev_err(card->dev, "failed to initialize streams: %d\n", err);
		return err;
	}

	err = azx_alloc_stream_pages(chip);
	if (err < 0) {
		dev_err(card->dev, "failed to allocate stream pages: %d\n",
			err);
		return err;
	}

	/* initialize chip */
	azx_init_chip(chip, 1);

	/* codec detection */
	if (!bus->codec_mask) {
		dev_err(card->dev, "no codecs found!\n");
		return -ENODEV;
	}

	/* driver name */
	strncpy(card->driver, drv_name, sizeof(card->driver));
	/* shortname for card */
	sname = of_get_property(np, "nvidia,model", NULL);
	if (!sname)
		sname = drv_name;
	if (strlen(sname) > sizeof(card->shortname))
		dev_info(card->dev, "truncating shortname for card\n");
	strncpy(card->shortname, sname, sizeof(card->shortname));

	/* longname for card */
	snprintf(card->longname, sizeof(card->longname),
		 "%s at 0x%lx irq %i",
		 card->shortname, bus->addr, bus->irq);

	return 0;
}

/*
 * constructor
 */

static void hda_tegra_probe_work(struct work_struct *work);

static int hda_tegra_create(struct snd_card *card,
			    unsigned int driver_caps,
			    struct hda_tegra *hda)
{
	static struct snd_device_ops ops = {
		.dev_disconnect = hda_tegra_dev_disconnect,
		.dev_free = hda_tegra_dev_free,
	};
	struct azx *chip;
	int err;

	chip = &hda->chip;

	mutex_init(&chip->open_mutex);
	chip->card = card;
	chip->ops = &hda_tegra_ops;
	chip->driver_caps = driver_caps;
	chip->driver_type = driver_caps & 0xff;
	chip->dev_index = 0;
	INIT_LIST_HEAD(&chip->pcm_list);

	chip->codec_probe_mask = -1;

	chip->single_cmd = false;
	chip->snoop = true;

	INIT_WORK(&hda->probe_work, hda_tegra_probe_work);

	err = azx_bus_init(chip, NULL);
	if (err < 0)
		return err;

	chip->bus.needs_damn_long_delay = 1;

	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
	if (err < 0) {
		dev_err(card->dev, "Error creating device\n");
		return err;
	}

	return 0;
}

static const struct of_device_id hda_tegra_match[] = {
	{ .compatible = "nvidia,tegra30-hda" },
	{},
};
MODULE_DEVICE_TABLE(of, hda_tegra_match);

static int hda_tegra_probe(struct platform_device *pdev)
{
	const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
					  AZX_DCAPS_PM_RUNTIME;
	struct snd_card *card;
	struct azx *chip;
	struct hda_tegra *hda;
	int err;

	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
	if (!hda)
		return -ENOMEM;
	hda->dev = &pdev->dev;
	chip = &hda->chip;

	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
			   THIS_MODULE, 0, &card);
	if (err < 0) {
		dev_err(&pdev->dev, "Error creating card!\n");
		return err;
	}

	err = hda_tegra_init_clk(hda);
	if (err < 0)
		goto out_free;

	err = hda_tegra_create(card, driver_flags, hda);
	if (err < 0)
		goto out_free;
	card->private_data = chip;

	dev_set_drvdata(&pdev->dev, card);

	pm_runtime_enable(hda->dev);
	if (!azx_has_pm_runtime(chip))
		pm_runtime_forbid(hda->dev);

	schedule_work(&hda->probe_work);

	return 0;

out_free:
	snd_card_free(card);
	return err;
}

static void hda_tegra_probe_work(struct work_struct *work)
{
	struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
	struct azx *chip = &hda->chip;
	struct platform_device *pdev = to_platform_device(hda->dev);
	int err;

	pm_runtime_get_sync(hda->dev);
	err = hda_tegra_first_init(chip, pdev);
	if (err < 0)
		goto out_free;

	/* create codec instances */
	err = azx_probe_codecs(chip, 8);
	if (err < 0)
		goto out_free;

	err = azx_codec_configure(chip);
	if (err < 0)
		goto out_free;

	err = snd_card_register(chip->card);
	if (err < 0)
		goto out_free;

	chip->running = 1;
	snd_hda_set_power_save(&chip->bus, power_save * 1000);

 out_free:
	pm_runtime_put(hda->dev);
	return; /* no error return from async probe */
}

static int hda_tegra_remove(struct platform_device *pdev)
{
	int ret;

	ret = snd_card_free(dev_get_drvdata(&pdev->dev));
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static void hda_tegra_shutdown(struct platform_device *pdev)
{
	struct snd_card *card = dev_get_drvdata(&pdev->dev);
	struct azx *chip;

	if (!card)
		return;
	chip = card->private_data;
	if (chip && chip->running)
		azx_stop_chip(chip);
}

static struct platform_driver tegra_platform_hda = {
	.driver = {
		.name = "tegra-hda",
		.pm = &hda_tegra_pm,
		.of_match_table = hda_tegra_match,
	},
	.probe = hda_tegra_probe,
	.remove = hda_tegra_remove,
	.shutdown = hda_tegra_shutdown,
};
module_platform_driver(tegra_platform_hda);

MODULE_DESCRIPTION("Tegra HDA bus driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9952f691	1	// SPDX-License-Identifier: GPL-2.0-only
3c320f3f DR	2	/*
	3	*
	4	* Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
3c320f3f DR	5	*/
	6
	7	#include <linux/clk.h>
	8	#include <linux/clocksource.h>
	9	#include <linux/completion.h>
	10	#include <linux/delay.h>
	11	#include <linux/dma-mapping.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/io.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/moduleparam.h>
	18	#include <linux/mutex.h>
	19	#include <linux/of_device.h>
3c320f3f DR	20	#include <linux/slab.h>
3c320f3f DR	21	#include <linux/time.h>
c94800a3	22	#include <linux/string.h>
3f7e94e6	23	#include <linux/pm_runtime.h>
3c320f3f DR	24
	25	#include <sound/core.h>
	26	#include <sound/initval.h>
	27
be57bfff	28	#include <sound/hda_codec.h>
3c320f3f	29	#include "hda_controller.h"
3c320f3f DR	30
	31	/* Defines for Nvidia Tegra HDA support */
	32	#define HDA_BAR0 0x8000
	33
	34	#define HDA_CFG_CMD 0x1004
	35	#define HDA_CFG_BAR0 0x1010
	36
	37	#define HDA_ENABLE_IO_SPACE (1 << 0)
	38	#define HDA_ENABLE_MEM_SPACE (1 << 1)
	39	#define HDA_ENABLE_BUS_MASTER (1 << 2)
	40	#define HDA_ENABLE_SERR (1 << 8)
	41	#define HDA_DISABLE_INTR (1 << 10)
	42	#define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
	43	#define HDA_BAR0_FINAL_PROGRAM (1 << 14)
	44
	45	/* IPFS */
	46	#define HDA_IPFS_CONFIG 0x180
	47	#define HDA_IPFS_EN_FPCI 0x1
	48
	49	#define HDA_IPFS_FPCI_BAR0 0x80
	50	#define HDA_FPCI_BAR0_START 0x40
	51
	52	#define HDA_IPFS_INTR_MASK 0x188
	53	#define HDA_IPFS_EN_INTR (1 << 16)
	54
	55	/* max number of SDs */
	56	#define NUM_CAPTURE_SD 1
	57	#define NUM_PLAYBACK_SD 1
	58
	59	struct hda_tegra {
	60	struct azx chip;
	61	struct device *dev;
	62	struct clk *hda_clk;
	63	struct clk *hda2codec_2x_clk;
	64	struct clk *hda2hdmi_clk;
	65	void __iomem *regs;
83510441	66	struct work_struct probe_work;
3c320f3f DR	67	};
3c320f3f DR	68
16c23952	69	#ifdef CONFIG_PM
3c320f3f DR	70	static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
	71	module_param(power_save, bint, 0644);
	72	MODULE_PARM_DESC(power_save,
	73	"Automatic power-saving timeout (in seconds, 0 = disable).");
16c23952	74	#else
bb573928	75	#define power_save 0
16c23952	76	#endif
3c320f3f	77
193c7e14	78	static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
3c320f3f DR	79
	80	static void hda_tegra_init(struct hda_tegra *hda)
	81	{
	82	u32 v;
	83
	84	/* Enable PCI access */
	85	v = readl(hda->regs + HDA_IPFS_CONFIG);
	86	v \|= HDA_IPFS_EN_FPCI;
	87	writel(v, hda->regs + HDA_IPFS_CONFIG);
	88
	89	/* Enable MEM/IO space and bus master */
	90	v = readl(hda->regs + HDA_CFG_CMD);
	91	v &= ~HDA_DISABLE_INTR;
	92	v \|= HDA_ENABLE_MEM_SPACE \| HDA_ENABLE_IO_SPACE \|
	93	HDA_ENABLE_BUS_MASTER \| HDA_ENABLE_SERR;
	94	writel(v, hda->regs + HDA_CFG_CMD);
	95
	96	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
	97	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
	98	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
	99
	100	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
	101	v \|= HDA_IPFS_EN_INTR;
	102	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
	103	}
	104
	105	static int hda_tegra_enable_clocks(struct hda_tegra *data)
	106	{
	107	int rc;
	108
	109	rc = clk_prepare_enable(data->hda_clk);
	110	if (rc)
	111	return rc;
	112	rc = clk_prepare_enable(data->hda2codec_2x_clk);
	113	if (rc)
	114	goto disable_hda;
	115	rc = clk_prepare_enable(data->hda2hdmi_clk);
	116	if (rc)
	117	goto disable_codec_2x;
	118
	119	return 0;
	120
	121	disable_codec_2x:
	122	clk_disable_unprepare(data->hda2codec_2x_clk);
	123	disable_hda:
	124	clk_disable_unprepare(data->hda_clk);
	125	return rc;
	126	}
	127
	128	static void hda_tegra_disable_clocks(struct hda_tegra *data)
	129	{
	130	clk_disable_unprepare(data->hda2hdmi_clk);
	131	clk_disable_unprepare(data->hda2codec_2x_clk);
	132	clk_disable_unprepare(data->hda_clk);
	133	}
	134
3c320f3f DR	135	/*
	136	* power management
	137	*/
74729469	138	static int __maybe_unused hda_tegra_suspend(struct device *dev)
3c320f3f DR	139	{
3c320f3f DR	140	struct snd_card *card = dev_get_drvdata(dev);
707e0759	141	int rc;
3c320f3f	142
707e0759 SP	143	rc = pm_runtime_force_suspend(dev);
	144	if (rc < 0)
	145	return rc;
3c320f3f	146	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3c320f3f	147
3c320f3f DR	148	return 0;
	149	}
	150
74729469	151	static int __maybe_unused hda_tegra_resume(struct device *dev)
3c320f3f DR	152	{
3c320f3f DR	153	struct snd_card *card = dev_get_drvdata(dev);
707e0759	154	int rc;
3c320f3f	155
707e0759 SP	156	rc = pm_runtime_force_resume(dev);
	157	if (rc < 0)
	158	return rc;
3c320f3f DR	159	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
	160
	161	return 0;
	162	}
3c320f3f	163
74729469	164	static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
f2974aa2	165	{
707e0759 SP	166	struct snd_card *card = dev_get_drvdata(dev);
	167	struct azx *chip = card->private_data;
	168	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	169	struct hdac_bus *bus = azx_bus(chip);
	170
	171	if (chip && chip->running) {
	172	azx_stop_chip(chip);
	173	synchronize_irq(bus->irq);
	174	azx_enter_link_reset(chip);
	175	}
	176	hda_tegra_disable_clocks(hda);
	177
f2974aa2 SP	178	return 0;
	179	}
	180
74729469	181	static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
f2974aa2	182	{
707e0759 SP	183	struct snd_card *card = dev_get_drvdata(dev);
	184	struct azx *chip = card->private_data;
	185	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	186	int rc;
	187
	188	rc = hda_tegra_enable_clocks(hda);
	189	if (rc != 0)
	190	return rc;
	191	if (chip && chip->running) {
	192	hda_tegra_init(hda);
	193	azx_init_chip(chip, 1);
	194	}
	195
f2974aa2 SP	196	return 0;
f2974aa2 SP	197	}
f2974aa2	198
3c320f3f DR	199	static const struct dev_pm_ops hda_tegra_pm = {
3c320f3f DR	200	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
f2974aa2 SP	201	SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
	202	hda_tegra_runtime_resume,
	203	NULL)
3c320f3f DR	204	};
3c320f3f DR	205
a41d1224 TI	206	static int hda_tegra_dev_disconnect(struct snd_device *device)
	207	{
	208	struct azx *chip = device->device_data;
	209
	210	chip->bus.shutdown = 1;
	211	return 0;
	212	}
	213
3c320f3f DR	214	/*
	215	* destructor
	216	*/
	217	static int hda_tegra_dev_free(struct snd_device *device)
	218	{
3c320f3f	219	struct azx *chip = device->device_data;
83510441	220	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
3c320f3f	221
83510441	222	cancel_work_sync(&hda->probe_work);
a41d1224	223	if (azx_bus(chip)->chip_init) {
7833c3f8	224	azx_stop_all_streams(chip);
3c320f3f DR	225	azx_stop_chip(chip);
	226	}
	227
	228	azx_free_stream_pages(chip);
a41d1224	229	azx_free_streams(chip);
4cfe99c7	230	snd_hdac_bus_exit(azx_bus(chip));
3c320f3f DR	231
	232	return 0;
	233	}
	234
	235	static int hda_tegra_init_chip(struct azx chip, struct platform_device pdev)
	236	{
	237	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
a41d1224	238	struct hdac_bus *bus = azx_bus(chip);
3c320f3f DR	239	struct device *dev = hda->dev;
3c320f3f DR	240	struct resource *res;
3c320f3f	241
3c320f3f DR	242	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3c320f3f DR	243	hda->regs = devm_ioremap_resource(dev, res);
93ceaa30 EB	244	if (IS_ERR(hda->regs))
93ceaa30 EB	245	return PTR_ERR(hda->regs);
3c320f3f	246
a41d1224 TI	247	bus->remap_addr = hda->regs + HDA_BAR0;
a41d1224 TI	248	bus->addr = res->start + HDA_BAR0;
3c320f3f	249
3c320f3f DR	250	hda_tegra_init(hda);
	251
	252	return 0;
	253	}
	254
65af2122 SP	255	static int hda_tegra_init_clk(struct hda_tegra *hda)
	256	{
	257	struct device *dev = hda->dev;
	258
	259	hda->hda_clk = devm_clk_get(dev, "hda");
	260	if (IS_ERR(hda->hda_clk)) {
	261	dev_err(dev, "failed to get hda clock\n");
	262	return PTR_ERR(hda->hda_clk);
	263	}
	264	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
	265	if (IS_ERR(hda->hda2codec_2x_clk)) {
	266	dev_err(dev, "failed to get hda2codec_2x clock\n");
	267	return PTR_ERR(hda->hda2codec_2x_clk);
	268	}
	269	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
	270	if (IS_ERR(hda->hda2hdmi_clk)) {
	271	dev_err(dev, "failed to get hda2hdmi clock\n");
	272	return PTR_ERR(hda->hda2hdmi_clk);
	273	}
	274
	275	return 0;
	276	}
	277
3c320f3f DR	278	static int hda_tegra_first_init(struct azx chip, struct platform_device pdev)
3c320f3f DR	279	{
a41d1224	280	struct hdac_bus *bus = azx_bus(chip);
3c320f3f DR	281	struct snd_card *card = chip->card;
	282	int err;
	283	unsigned short gcap;
	284	int irq_id = platform_get_irq(pdev, 0);
c0bde003 SP	285	const char sname, drv_name = "tegra-hda";
c0bde003 SP	286	struct device_node *np = pdev->dev.of_node;
3c320f3f DR	287
	288	err = hda_tegra_init_chip(chip, pdev);
	289	if (err)
	290	return err;
	291
	292	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
	293	IRQF_SHARED, KBUILD_MODNAME, chip);
	294	if (err) {
	295	dev_err(chip->card->dev,
	296	"unable to request IRQ %d, disabling device\n",
	297	irq_id);
	298	return err;
	299	}
a41d1224	300	bus->irq = irq_id;
3c320f3f	301
a41d1224	302	synchronize_irq(bus->irq);
3c320f3f DR	303
	304	gcap = azx_readw(chip, GCAP);
	305	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
	306
	307	/* read number of streams from GCAP register instead of using
	308	* hardcoded value
	309	*/
	310	chip->capture_streams = (gcap >> 8) & 0x0f;
	311	chip->playback_streams = (gcap >> 12) & 0x0f;
	312	if (!chip->playback_streams && !chip->capture_streams) {
	313	/* gcap didn't give any info, switching to old method */
	314	chip->playback_streams = NUM_PLAYBACK_SD;
	315	chip->capture_streams = NUM_CAPTURE_SD;
	316	}
	317	chip->capture_index_offset = 0;
	318	chip->playback_index_offset = chip->capture_streams;
	319	chip->num_streams = chip->playback_streams + chip->capture_streams;
3c320f3f	320
a41d1224 TI	321	/* initialize streams */
a41d1224 TI	322	err = azx_init_streams(chip);
6a464a4c TR	323	if (err < 0) {
6a464a4c TR	324	dev_err(card->dev, "failed to initialize streams: %d\n", err);
3c320f3f	325	return err;
6a464a4c	326	}
3c320f3f	327
a41d1224	328	err = azx_alloc_stream_pages(chip);
6a464a4c TR	329	if (err < 0) {
	330	dev_err(card->dev, "failed to allocate stream pages: %d\n",
	331	err);
a41d1224	332	return err;
6a464a4c	333	}
3c320f3f DR	334
	335	/* initialize chip */
	336	azx_init_chip(chip, 1);
	337
	338	/* codec detection */
a41d1224	339	if (!bus->codec_mask) {
3c320f3f DR	340	dev_err(card->dev, "no codecs found!\n");
	341	return -ENODEV;
	342	}
	343
c94800a3	344	/* driver name */
c0bde003	345	strncpy(card->driver, drv_name, sizeof(card->driver));
c94800a3	346	/* shortname for card */
c0bde003 SP	347	sname = of_get_property(np, "nvidia,model", NULL);
	348	if (!sname)
	349	sname = drv_name;
c94800a3 SP	350	if (strlen(sname) > sizeof(card->shortname))
	351	dev_info(card->dev, "truncating shortname for card\n");
	352	strncpy(card->shortname, sname, sizeof(card->shortname));
	353
	354	/* longname for card */
3c320f3f DR	355	snprintf(card->longname, sizeof(card->longname),
3c320f3f DR	356	"%s at 0x%lx irq %i",
a41d1224	357	card->shortname, bus->addr, bus->irq);
3c320f3f DR	358
	359	return 0;
	360	}
	361
	362	/*
	363	* constructor
	364	*/
83510441 TI	365
	366	static void hda_tegra_probe_work(struct work_struct *work);
	367
3c320f3f DR	368	static int hda_tegra_create(struct snd_card *card,
3c320f3f DR	369	unsigned int driver_caps,
3c320f3f DR	370	struct hda_tegra *hda)
	371	{
	372	static struct snd_device_ops ops = {
a41d1224	373	.dev_disconnect = hda_tegra_dev_disconnect,
3c320f3f DR	374	.dev_free = hda_tegra_dev_free,
	375	};
	376	struct azx *chip;
	377	int err;
	378
	379	chip = &hda->chip;
	380
3c320f3f DR	381	mutex_init(&chip->open_mutex);
3c320f3f DR	382	chip->card = card;
a43ff5ba	383	chip->ops = &hda_tegra_ops;
3c320f3f DR	384	chip->driver_caps = driver_caps;
	385	chip->driver_type = driver_caps & 0xff;
	386	chip->dev_index = 0;
	387	INIT_LIST_HEAD(&chip->pcm_list);
3c320f3f	388
3c320f3f DR	389	chip->codec_probe_mask = -1;
	390
	391	chip->single_cmd = false;
	392	chip->snoop = true;
	393
83510441 TI	394	INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
83510441 TI	395
19abfefd	396	err = azx_bus_init(chip, NULL);
3b90f407 TR	397	if (err < 0)
	398	return err;
	399
7d9a1808 TI	400	chip->bus.needs_damn_long_delay = 1;
7d9a1808 TI	401
3c320f3f DR	402	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
	403	if (err < 0) {
	404	dev_err(card->dev, "Error creating device\n");
	405	return err;
	406	}
	407
	408	return 0;
	409	}
	410
	411	static const struct of_device_id hda_tegra_match[] = {
	412	{ .compatible = "nvidia,tegra30-hda" },
	413	{},
	414	};
f73387cb	415	MODULE_DEVICE_TABLE(of, hda_tegra_match);
3c320f3f DR	416
	417	static int hda_tegra_probe(struct platform_device *pdev)
	418	{
9935d55b SP	419	const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR \|
9935d55b SP	420	AZX_DCAPS_PM_RUNTIME;
3c320f3f DR	421	struct snd_card *card;
	422	struct azx *chip;
	423	struct hda_tegra *hda;
	424	int err;
3c320f3f DR	425
	426	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
	427	if (!hda)
	428	return -ENOMEM;
	429	hda->dev = &pdev->dev;
	430	chip = &hda->chip;
	431
	432	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
	433	THIS_MODULE, 0, &card);
	434	if (err < 0) {
	435	dev_err(&pdev->dev, "Error creating card!\n");
	436	return err;
	437	}
	438
65af2122 SP	439	err = hda_tegra_init_clk(hda);
	440	if (err < 0)
	441	goto out_free;
	442
a43ff5ba	443	err = hda_tegra_create(card, driver_flags, hda);
3c320f3f DR	444	if (err < 0)
	445	goto out_free;
	446	card->private_data = chip;
	447
	448	dev_set_drvdata(&pdev->dev, card);
3f7e94e6 SP	449
	450	pm_runtime_enable(hda->dev);
	451	if (!azx_has_pm_runtime(chip))
	452	pm_runtime_forbid(hda->dev);
	453
83510441 TI	454	schedule_work(&hda->probe_work);
	455
	456	return 0;
	457
	458	out_free:
	459	snd_card_free(card);
	460	return err;
	461	}
	462
	463	static void hda_tegra_probe_work(struct work_struct *work)
	464	{
	465	struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
	466	struct azx *chip = &hda->chip;
	467	struct platform_device *pdev = to_platform_device(hda->dev);
	468	int err;
3c320f3f	469
3f7e94e6	470	pm_runtime_get_sync(hda->dev);
3c320f3f DR	471	err = hda_tegra_first_init(chip, pdev);
	472	if (err < 0)
	473	goto out_free;
	474
	475	/* create codec instances */
350355e3	476	err = azx_probe_codecs(chip, 8);
3c320f3f DR	477	if (err < 0)
	478	goto out_free;
	479
	480	err = azx_codec_configure(chip);
	481	if (err < 0)
	482	goto out_free;
	483
3c320f3f DR	484	err = snd_card_register(chip->card);
	485	if (err < 0)
	486	goto out_free;
	487
	488	chip->running = 1;
a41d1224	489	snd_hda_set_power_save(&chip->bus, power_save * 1000);
3c320f3f	490
83510441	491	out_free:
3f7e94e6	492	pm_runtime_put(hda->dev);
83510441	493	return; /* no error return from async probe */
3c320f3f DR	494	}
	495
	496	static int hda_tegra_remove(struct platform_device *pdev)
	497	{
3f7e94e6 SP	498	int ret;
	499
	500	ret = snd_card_free(dev_get_drvdata(&pdev->dev));
	501	pm_runtime_disable(&pdev->dev);
	502
	503	return ret;
3c320f3f DR	504	}
3c320f3f DR	505
b2a0bafa TI	506	static void hda_tegra_shutdown(struct platform_device *pdev)
	507	{
	508	struct snd_card *card = dev_get_drvdata(&pdev->dev);
	509	struct azx *chip;
	510
	511	if (!card)
	512	return;
	513	chip = card->private_data;
	514	if (chip && chip->running)
	515	azx_stop_chip(chip);
	516	}
	517
3c320f3f DR	518	static struct platform_driver tegra_platform_hda = {
	519	.driver = {
	520	.name = "tegra-hda",
	521	.pm = &hda_tegra_pm,
	522	.of_match_table = hda_tegra_match,
	523	},
	524	.probe = hda_tegra_probe,
	525	.remove = hda_tegra_remove,
b2a0bafa	526	.shutdown = hda_tegra_shutdown,
3c320f3f DR	527	};
	528	module_platform_driver(tegra_platform_hda);
	529
	530	MODULE_DESCRIPTION("Tegra HDA bus driver");
	531	MODULE_LICENSE("GPL v2");