[linux-2.6-block.git] / sound / pci / hda / hda_tegra.c

/*
 *
 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mutex.h>
#include <linux/of_device.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/time.h>

#include <sound/core.h>
#include <sound/initval.h>

#include "hda_codec.h"
#include "hda_controller.h"
#include "hda_priv.h"

/* Defines for Nvidia Tegra HDA support */
#define HDA_BAR0           0x8000

#define HDA_CFG_CMD        0x1004
#define HDA_CFG_BAR0       0x1010

#define HDA_ENABLE_IO_SPACE       (1 << 0)
#define HDA_ENABLE_MEM_SPACE      (1 << 1)
#define HDA_ENABLE_BUS_MASTER     (1 << 2)
#define HDA_ENABLE_SERR           (1 << 8)
#define HDA_DISABLE_INTR          (1 << 10)
#define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
#define HDA_BAR0_FINAL_PROGRAM    (1 << 14)

/* IPFS */
#define HDA_IPFS_CONFIG           0x180
#define HDA_IPFS_EN_FPCI          0x1

#define HDA_IPFS_FPCI_BAR0        0x80
#define HDA_FPCI_BAR0_START       0x40

#define HDA_IPFS_INTR_MASK        0x188
#define HDA_IPFS_EN_INTR          (1 << 16)

/* max number of SDs */
#define NUM_CAPTURE_SD 1
#define NUM_PLAYBACK_SD 1

struct hda_tegra {
	struct azx chip;
	struct device *dev;
	struct clk *hda_clk;
	struct clk *hda2codec_2x_clk;
	struct clk *hda2hdmi_clk;
	void __iomem *regs;
};

static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
module_param(power_save, bint, 0644);
MODULE_PARM_DESC(power_save,
		 "Automatic power-saving timeout (in seconds, 0 = disable).");

/*
 * DMA page allocation ops.
 */
static int dma_alloc_pages(struct azx *chip, int type, size_t size,
			   struct snd_dma_buffer *buf)
{
	return snd_dma_alloc_pages(type, chip->card->dev, size, buf);
}

static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
{
	snd_dma_free_pages(buf);
}

static int substream_alloc_pages(struct azx *chip,
				 struct snd_pcm_substream *substream,
				 size_t size)
{
	struct azx_dev *azx_dev = get_azx_dev(substream);

	azx_dev->bufsize = 0;
	azx_dev->period_bytes = 0;
	azx_dev->format_val = 0;
	return snd_pcm_lib_malloc_pages(substream, size);
}

static int substream_free_pages(struct azx *chip,
				struct snd_pcm_substream *substream)
{
	return snd_pcm_lib_free_pages(substream);
}

/*
 * Register access ops. Tegra HDA register access is DWORD only.
 */
static void hda_tegra_writel(u32 value, u32 *addr)
{
	writel(value, addr);
}

static u32 hda_tegra_readl(u32 *addr)
{
	return readl(addr);
}

static void hda_tegra_writew(u16 value, u16 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	v &= ~(0xffff << shift);
	v |= value << shift;
	writel(v, dword_addr);
}

static u16 hda_tegra_readw(u16 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	return (v >> shift) & 0xffff;
}

static void hda_tegra_writeb(u8 value, u8 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	v &= ~(0xff << shift);
	v |= value << shift;
	writel(v, dword_addr);
}

static u8 hda_tegra_readb(u8 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	return (v >> shift) & 0xff;
}

static const struct hda_controller_ops hda_tegra_ops = {
	.reg_writel = hda_tegra_writel,
	.reg_readl = hda_tegra_readl,
	.reg_writew = hda_tegra_writew,
	.reg_readw = hda_tegra_readw,
	.reg_writeb = hda_tegra_writeb,
	.reg_readb = hda_tegra_readb,
	.dma_alloc_pages = dma_alloc_pages,
	.dma_free_pages = dma_free_pages,
	.substream_alloc_pages = substream_alloc_pages,
	.substream_free_pages = substream_free_pages,
};

static void hda_tegra_init(struct hda_tegra *hda)
{
	u32 v;

	/* Enable PCI access */
	v = readl(hda->regs + HDA_IPFS_CONFIG);
	v |= HDA_IPFS_EN_FPCI;
	writel(v, hda->regs + HDA_IPFS_CONFIG);

	/* Enable MEM/IO space and bus master */
	v = readl(hda->regs + HDA_CFG_CMD);
	v &= ~HDA_DISABLE_INTR;
	v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
		HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
	writel(v, hda->regs + HDA_CFG_CMD);

	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);

	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
	v |= HDA_IPFS_EN_INTR;
	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
}

static int hda_tegra_enable_clocks(struct hda_tegra *data)
{
	int rc;

	rc = clk_prepare_enable(data->hda_clk);
	if (rc)
		return rc;
	rc = clk_prepare_enable(data->hda2codec_2x_clk);
	if (rc)
		goto disable_hda;
	rc = clk_prepare_enable(data->hda2hdmi_clk);
	if (rc)
		goto disable_codec_2x;

	return 0;

disable_codec_2x:
	clk_disable_unprepare(data->hda2codec_2x_clk);
disable_hda:
	clk_disable_unprepare(data->hda_clk);
	return rc;
}

static void hda_tegra_disable_clocks(struct hda_tegra *data)
{
	clk_disable_unprepare(data->hda2hdmi_clk);
	clk_disable_unprepare(data->hda2codec_2x_clk);
	clk_disable_unprepare(data->hda_clk);
}

#ifdef CONFIG_PM_SLEEP
/*
 * power management
 */
static int hda_tegra_suspend(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;
	struct azx_pcm *p;
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);

	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
	list_for_each_entry(p, &chip->pcm_list, list)
		snd_pcm_suspend_all(p->pcm);
	if (chip->initialized)
		snd_hda_suspend(chip->bus);

	azx_stop_chip(chip);
	azx_enter_link_reset(chip);
	hda_tegra_disable_clocks(hda);

	return 0;
}

static int hda_tegra_resume(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	int status;

	hda_tegra_enable_clocks(hda);

	/* Read STATESTS before controller reset */
	status = azx_readw(chip, STATESTS);

	hda_tegra_init(hda);

	azx_init_chip(chip, 1);

	snd_hda_resume(chip->bus);
	snd_power_change_state(card, SNDRV_CTL_POWER_D0);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

static const struct dev_pm_ops hda_tegra_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
};

/*
 * reboot notifier for hang-up problem at power-down
 */
static int hda_tegra_halt(struct notifier_block *nb, unsigned long event,
			  void *buf)
{
	struct azx *chip = container_of(nb, struct azx, reboot_notifier);
	snd_hda_bus_reboot_notify(chip->bus);
	azx_stop_chip(chip);
	return NOTIFY_OK;
}

static void hda_tegra_notifier_register(struct azx *chip)
{
	chip->reboot_notifier.notifier_call = hda_tegra_halt;
	register_reboot_notifier(&chip->reboot_notifier);
}

static void hda_tegra_notifier_unregister(struct azx *chip)
{
	if (chip->reboot_notifier.notifier_call)
		unregister_reboot_notifier(&chip->reboot_notifier);
}

/*
 * destructor
 */
static int hda_tegra_dev_free(struct snd_device *device)
{
	int i;
	struct azx *chip = device->device_data;

	hda_tegra_notifier_unregister(chip);

	if (chip->initialized) {
		for (i = 0; i < chip->num_streams; i++)
			azx_stream_stop(chip, &chip->azx_dev[i]);
		azx_stop_chip(chip);
	}

	azx_free_stream_pages(chip);

	return 0;
}

static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
{
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	struct device *dev = hda->dev;
	struct resource *res;
	int err;

	hda->hda_clk = devm_clk_get(dev, "hda");
	if (IS_ERR(hda->hda_clk))
		return PTR_ERR(hda->hda_clk);
	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
	if (IS_ERR(hda->hda2codec_2x_clk))
		return PTR_ERR(hda->hda2codec_2x_clk);
	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
	if (IS_ERR(hda->hda2hdmi_clk))
		return PTR_ERR(hda->hda2hdmi_clk);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	hda->regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(chip->remap_addr))
		return PTR_ERR(chip->remap_addr);

	chip->remap_addr = hda->regs + HDA_BAR0;
	chip->addr = res->start + HDA_BAR0;

	err = hda_tegra_enable_clocks(hda);
	if (err)
		return err;

	hda_tegra_init(hda);

	return 0;
}

/*
 * The codecs were powered up in snd_hda_codec_new().
 * Now all initialization done, so turn them down if possible
 */
static void power_down_all_codecs(struct azx *chip)
{
	struct hda_codec *codec;
	list_for_each_entry(codec, &chip->bus->codec_list, list)
		snd_hda_power_down(codec);
}

static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
{
	struct snd_card *card = chip->card;
	int err;
	unsigned short gcap;
	int irq_id = platform_get_irq(pdev, 0);

	err = hda_tegra_init_chip(chip, pdev);
	if (err)
		return err;

	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
			     IRQF_SHARED, KBUILD_MODNAME, chip);
	if (err) {
		dev_err(chip->card->dev,
			"unable to request IRQ %d, disabling device\n",
			irq_id);
		return err;
	}
	chip->irq = irq_id;

	synchronize_irq(chip->irq);

	gcap = azx_readw(chip, GCAP);
	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);

	/* read number of streams from GCAP register instead of using
	 * hardcoded value
	 */
	chip->capture_streams = (gcap >> 8) & 0x0f;
	chip->playback_streams = (gcap >> 12) & 0x0f;
	if (!chip->playback_streams && !chip->capture_streams) {
		/* gcap didn't give any info, switching to old method */
		chip->playback_streams = NUM_PLAYBACK_SD;
		chip->capture_streams = NUM_CAPTURE_SD;
	}
	chip->capture_index_offset = 0;
	chip->playback_index_offset = chip->capture_streams;
	chip->num_streams = chip->playback_streams + chip->capture_streams;
	chip->azx_dev = devm_kcalloc(card->dev, chip->num_streams,
				     sizeof(*chip->azx_dev), GFP_KERNEL);
	if (!chip->azx_dev)
		return -ENOMEM;

	err = azx_alloc_stream_pages(chip);
	if (err < 0)
		return err;

	/* initialize streams */
	azx_init_stream(chip);

	/* initialize chip */
	azx_init_chip(chip, 1);

	/* codec detection */
	if (!chip->codec_mask) {
		dev_err(card->dev, "no codecs found!\n");
		return -ENODEV;
	}

	strcpy(card->driver, "tegra-hda");
	strcpy(card->shortname, "tegra-hda");
	snprintf(card->longname, sizeof(card->longname),
		 "%s at 0x%lx irq %i",
		 card->shortname, chip->addr, chip->irq);

	return 0;
}

/*
 * constructor
 */
static int hda_tegra_create(struct snd_card *card,
			    unsigned int driver_caps,
			    const struct hda_controller_ops *hda_ops,
			    struct hda_tegra *hda)
{
	static struct snd_device_ops ops = {
		.dev_free = hda_tegra_dev_free,
	};
	struct azx *chip;
	int err;

	chip = &hda->chip;

	spin_lock_init(&chip->reg_lock);
	mutex_init(&chip->open_mutex);
	chip->card = card;
	chip->ops = hda_ops;
	chip->irq = -1;
	chip->driver_caps = driver_caps;
	chip->driver_type = driver_caps & 0xff;
	chip->dev_index = 0;
	INIT_LIST_HEAD(&chip->pcm_list);
	INIT_LIST_HEAD(&chip->list);

	chip->position_fix[0] = POS_FIX_AUTO;
	chip->position_fix[1] = POS_FIX_AUTO;
	chip->codec_probe_mask = -1;

	chip->single_cmd = false;
	chip->snoop = true;

	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
	if (err < 0) {
		dev_err(card->dev, "Error creating device\n");
		return err;
	}

	return 0;
}

static const struct of_device_id hda_tegra_match[] = {
	{ .compatible = "nvidia,tegra30-hda" },
	{},
};
MODULE_DEVICE_TABLE(of, hda_tegra_match);

static int hda_tegra_probe(struct platform_device *pdev)
{
	struct snd_card *card;
	struct azx *chip;
	struct hda_tegra *hda;
	int err;
	const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY;

	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
	if (!hda)
		return -ENOMEM;
	hda->dev = &pdev->dev;
	chip = &hda->chip;

	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
			   THIS_MODULE, 0, &card);
	if (err < 0) {
		dev_err(&pdev->dev, "Error creating card!\n");
		return err;
	}

	err = hda_tegra_create(card, driver_flags, &hda_tegra_ops, hda);
	if (err < 0)
		goto out_free;
	card->private_data = chip;

	dev_set_drvdata(&pdev->dev, card);

	err = hda_tegra_first_init(chip, pdev);
	if (err < 0)
		goto out_free;

	/* create codec instances */
	err = azx_codec_create(chip, NULL, 0, &power_save);
	if (err < 0)
		goto out_free;

	err = azx_codec_configure(chip);
	if (err < 0)
		goto out_free;

	/* create PCM streams */
	err = snd_hda_build_pcms(chip->bus);
	if (err < 0)
		goto out_free;

	/* create mixer controls */
	err = azx_mixer_create(chip);
	if (err < 0)
		goto out_free;

	err = snd_card_register(chip->card);
	if (err < 0)
		goto out_free;

	chip->running = 1;
	power_down_all_codecs(chip);
	hda_tegra_notifier_register(chip);

	return 0;

out_free:
	snd_card_free(card);
	return err;
}

static int hda_tegra_remove(struct platform_device *pdev)
{
	return snd_card_free(dev_get_drvdata(&pdev->dev));
}

static struct platform_driver tegra_platform_hda = {
	.driver = {
		.name = "tegra-hda",
		.pm = &hda_tegra_pm,
		.of_match_table = hda_tegra_match,
	},
	.probe = hda_tegra_probe,
	.remove = hda_tegra_remove,
};
module_platform_driver(tegra_platform_hda);

MODULE_DESCRIPTION("Tegra HDA bus driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
3c320f3f DR	1	/*
	2	*
	3	* Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*
	17	*/
	18
	19	#include <linux/clk.h>
	20	#include <linux/clocksource.h>
	21	#include <linux/completion.h>
	22	#include <linux/delay.h>
	23	#include <linux/dma-mapping.h>
	24	#include <linux/init.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/io.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
	29	#include <linux/moduleparam.h>
	30	#include <linux/mutex.h>
	31	#include <linux/of_device.h>
	32	#include <linux/reboot.h>
	33	#include <linux/slab.h>
	34	#include <linux/time.h>
	35
	36	#include <sound/core.h>
	37	#include <sound/initval.h>
	38
	39	#include "hda_codec.h"
	40	#include "hda_controller.h"
	41	#include "hda_priv.h"
	42
	43	/* Defines for Nvidia Tegra HDA support */
	44	#define HDA_BAR0 0x8000
	45
	46	#define HDA_CFG_CMD 0x1004
	47	#define HDA_CFG_BAR0 0x1010
	48
	49	#define HDA_ENABLE_IO_SPACE (1 << 0)
	50	#define HDA_ENABLE_MEM_SPACE (1 << 1)
	51	#define HDA_ENABLE_BUS_MASTER (1 << 2)
	52	#define HDA_ENABLE_SERR (1 << 8)
	53	#define HDA_DISABLE_INTR (1 << 10)
	54	#define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
	55	#define HDA_BAR0_FINAL_PROGRAM (1 << 14)
	56
	57	/* IPFS */
	58	#define HDA_IPFS_CONFIG 0x180
	59	#define HDA_IPFS_EN_FPCI 0x1
	60
	61	#define HDA_IPFS_FPCI_BAR0 0x80
	62	#define HDA_FPCI_BAR0_START 0x40
	63
	64	#define HDA_IPFS_INTR_MASK 0x188
65	#define HDA_IPFS_EN_INTR (1 << 16)
66
67	/* max number of SDs */
68	#define NUM_CAPTURE_SD 1
69	#define NUM_PLAYBACK_SD 1
70
71	struct hda_tegra {
72	struct azx chip;
73	struct device *dev;
74	struct clk *hda_clk;
75	struct clk *hda2codec_2x_clk;
76	struct clk *hda2hdmi_clk;
77	void __iomem *regs;
78	};
79
80	static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
81	module_param(power_save, bint, 0644);
82	MODULE_PARM_DESC(power_save,
83	"Automatic power-saving timeout (in seconds, 0 = disable).");
84
85	/*
86	* DMA page allocation ops.
87	*/
88	static int dma_alloc_pages(struct azx *chip, int type, size_t size,
89	struct snd_dma_buffer *buf)
90	{
91	return snd_dma_alloc_pages(type, chip->card->dev, size, buf);
92	}
93
94	static void dma_free_pages(struct azx chip, struct snd_dma_buffer buf)
95	{
96	snd_dma_free_pages(buf);
97	}
98
99	static int substream_alloc_pages(struct azx *chip,
100	struct snd_pcm_substream *substream,
101	size_t size)
102	{
103	struct azx_dev *azx_dev = get_azx_dev(substream);
104
105	azx_dev->bufsize = 0;
106	azx_dev->period_bytes = 0;
107	azx_dev->format_val = 0;
108	return snd_pcm_lib_malloc_pages(substream, size);
109	}
110
111	static int substream_free_pages(struct azx *chip,
112	struct snd_pcm_substream *substream)
113	{
114	return snd_pcm_lib_free_pages(substream);
115	}
116
117	/*
118	* Register access ops. Tegra HDA register access is DWORD only.
119	*/
120	static void hda_tegra_writel(u32 value, u32 *addr)
121	{
122	writel(value, addr);
123	}
124
125	static u32 hda_tegra_readl(u32 *addr)
126	{
127	return readl(addr);
128	}
129
130	static void hda_tegra_writew(u16 value, u16 *addr)
131	{
132	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
133	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
134	u32 v;
135
136	v = readl(dword_addr);
137	v &= ~(0xffff << shift);
138	v \|= value << shift;
139	writel(v, dword_addr);
140	}
141
142	static u16 hda_tegra_readw(u16 *addr)
143	{
144	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
145	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
146	u32 v;
147
148	v = readl(dword_addr);
149	return (v >> shift) & 0xffff;
150	}
151
152	static void hda_tegra_writeb(u8 value, u8 *addr)
153	{
154	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
155	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
156	u32 v;
157
158	v = readl(dword_addr);
159	v &= ~(0xff << shift);
160	v \|= value << shift;
161	writel(v, dword_addr);
162	}
163
164	static u8 hda_tegra_readb(u8 *addr)
165	{
166	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
167	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
168	u32 v;
169
170	v = readl(dword_addr);
171	return (v >> shift) & 0xff;
172	}
173
174	static const struct hda_controller_ops hda_tegra_ops = {
175	.reg_writel = hda_tegra_writel,
176	.reg_readl = hda_tegra_readl,
177	.reg_writew = hda_tegra_writew,
178	.reg_readw = hda_tegra_readw,
179	.reg_writeb = hda_tegra_writeb,
180	.reg_readb = hda_tegra_readb,
181	.dma_alloc_pages = dma_alloc_pages,
182	.dma_free_pages = dma_free_pages,
183	.substream_alloc_pages = substream_alloc_pages,
184	.substream_free_pages = substream_free_pages,
185	};
186
187	static void hda_tegra_init(struct hda_tegra *hda)
188	{
189	u32 v;
190
191	/* Enable PCI access */
192	v = readl(hda->regs + HDA_IPFS_CONFIG);
193	v \|= HDA_IPFS_EN_FPCI;
194	writel(v, hda->regs + HDA_IPFS_CONFIG);
195
196	/* Enable MEM/IO space and bus master */
197	v = readl(hda->regs + HDA_CFG_CMD);
198	v &= ~HDA_DISABLE_INTR;
199	v \|= HDA_ENABLE_MEM_SPACE \| HDA_ENABLE_IO_SPACE \|
200	HDA_ENABLE_BUS_MASTER \| HDA_ENABLE_SERR;
201	writel(v, hda->regs + HDA_CFG_CMD);
202
203	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
204	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
205	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
206
207	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
208	v \|= HDA_IPFS_EN_INTR;
209	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
210	}
211
212	static int hda_tegra_enable_clocks(struct hda_tegra *data)
213	{
214	int rc;
215
216	rc = clk_prepare_enable(data->hda_clk);
217	if (rc)
218	return rc;
219	rc = clk_prepare_enable(data->hda2codec_2x_clk);
220	if (rc)
221	goto disable_hda;
222	rc = clk_prepare_enable(data->hda2hdmi_clk);
223	if (rc)
224	goto disable_codec_2x;
225
226	return 0;
227
228	disable_codec_2x:
229	clk_disable_unprepare(data->hda2codec_2x_clk);
230	disable_hda:
231	clk_disable_unprepare(data->hda_clk);
232	return rc;
233	}
234
235	static void hda_tegra_disable_clocks(struct hda_tegra *data)
236	{
237	clk_disable_unprepare(data->hda2hdmi_clk);
238	clk_disable_unprepare(data->hda2codec_2x_clk);
239	clk_disable_unprepare(data->hda_clk);
240	}
241
242	#ifdef CONFIG_PM_SLEEP
243	/*
244	* power management
245	*/
246	static int hda_tegra_suspend(struct device *dev)
247	{
248	struct snd_card *card = dev_get_drvdata(dev);
249	struct azx *chip = card->private_data;
250	struct azx_pcm *p;
251	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
252
253	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
254	list_for_each_entry(p, &chip->pcm_list, list)
255	snd_pcm_suspend_all(p->pcm);
256	if (chip->initialized)
257	snd_hda_suspend(chip->bus);
258
259	azx_stop_chip(chip);
260	azx_enter_link_reset(chip);
261	hda_tegra_disable_clocks(hda);
262
263	return 0;
264	}
265
266	static int hda_tegra_resume(struct device *dev)
267	{
268	struct snd_card *card = dev_get_drvdata(dev);
269	struct azx *chip = card->private_data;
270	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
271	int status;
272
273	hda_tegra_enable_clocks(hda);
274
275	/* Read STATESTS before controller reset */
276	status = azx_readw(chip, STATESTS);
277
278	hda_tegra_init(hda);
279
280	azx_init_chip(chip, 1);
281
282	snd_hda_resume(chip->bus);
283	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
284
285	return 0;
286	}
287	#endif /* CONFIG_PM_SLEEP */
288
289	static const struct dev_pm_ops hda_tegra_pm = {
290	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
291	};
292
293	/*
294	* reboot notifier for hang-up problem at power-down
295	*/
296	static int hda_tegra_halt(struct notifier_block *nb, unsigned long event,
297	void *buf)
298	{
299	struct azx *chip = container_of(nb, struct azx, reboot_notifier);
300	snd_hda_bus_reboot_notify(chip->bus);
301	azx_stop_chip(chip);
302	return NOTIFY_OK;
303	}
304
305	static void hda_tegra_notifier_register(struct azx *chip)
306	{
307	chip->reboot_notifier.notifier_call = hda_tegra_halt;
308	register_reboot_notifier(&chip->reboot_notifier);
309	}
310
311	static void hda_tegra_notifier_unregister(struct azx *chip)
312	{
313	if (chip->reboot_notifier.notifier_call)
314	unregister_reboot_notifier(&chip->reboot_notifier);
315	}
316
317	/*
318	* destructor
319	*/
320	static int hda_tegra_dev_free(struct snd_device *device)
321	{
322	int i;
323	struct azx *chip = device->device_data;
324
325	hda_tegra_notifier_unregister(chip);
326
327	if (chip->initialized) {
328	for (i = 0; i < chip->num_streams; i++)
329	azx_stream_stop(chip, &chip->azx_dev[i]);
330	azx_stop_chip(chip);
331	}
332
333	azx_free_stream_pages(chip);
334
335	return 0;
336	}
337
338	static int hda_tegra_init_chip(struct azx chip, struct platform_device pdev)
339	{
340	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
341	struct device *dev = hda->dev;
342	struct resource *res;
343	int err;
344
345	hda->hda_clk = devm_clk_get(dev, "hda");
346	if (IS_ERR(hda->hda_clk))
347	return PTR_ERR(hda->hda_clk);
348	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
349	if (IS_ERR(hda->hda2codec_2x_clk))
350	return PTR_ERR(hda->hda2codec_2x_clk);
351	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
352	if (IS_ERR(hda->hda2hdmi_clk))
353	return PTR_ERR(hda->hda2hdmi_clk);
354
355	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
356	hda->regs = devm_ioremap_resource(dev, res);
357	if (IS_ERR(chip->remap_addr))
358	return PTR_ERR(chip->remap_addr);
359
360	chip->remap_addr = hda->regs + HDA_BAR0;
361	chip->addr = res->start + HDA_BAR0;
362
363	err = hda_tegra_enable_clocks(hda);
364	if (err)
365	return err;
366
367	hda_tegra_init(hda);
368
369	return 0;
370	}
371
372	/*
373	* The codecs were powered up in snd_hda_codec_new().
374	* Now all initialization done, so turn them down if possible
375	*/
376	static void power_down_all_codecs(struct azx *chip)
377	{
378	struct hda_codec *codec;
379	list_for_each_entry(codec, &chip->bus->codec_list, list)
380	snd_hda_power_down(codec);
381	}
382
383	static int hda_tegra_first_init(struct azx chip, struct platform_device pdev)
384	{
385	struct snd_card *card = chip->card;
386	int err;
387	unsigned short gcap;
388	int irq_id = platform_get_irq(pdev, 0);
389
390	err = hda_tegra_init_chip(chip, pdev);
391	if (err)
392	return err;
393
394	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
395	IRQF_SHARED, KBUILD_MODNAME, chip);
396	if (err) {
397	dev_err(chip->card->dev,
398	"unable to request IRQ %d, disabling device\n",
399	irq_id);
400	return err;
401	}
402	chip->irq = irq_id;
403
404	synchronize_irq(chip->irq);
405
406	gcap = azx_readw(chip, GCAP);
407	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
408
409	/* read number of streams from GCAP register instead of using
410	* hardcoded value
411	*/
412	chip->capture_streams = (gcap >> 8) & 0x0f;
413	chip->playback_streams = (gcap >> 12) & 0x0f;
414	if (!chip->playback_streams && !chip->capture_streams) {
415	/* gcap didn't give any info, switching to old method */
416	chip->playback_streams = NUM_PLAYBACK_SD;
417	chip->capture_streams = NUM_CAPTURE_SD;
418	}
419	chip->capture_index_offset = 0;
420	chip->playback_index_offset = chip->capture_streams;
421	chip->num_streams = chip->playback_streams + chip->capture_streams;
422	chip->azx_dev = devm_kcalloc(card->dev, chip->num_streams,
423	sizeof(*chip->azx_dev), GFP_KERNEL);
424	if (!chip->azx_dev)
425	return -ENOMEM;
426
427	err = azx_alloc_stream_pages(chip);
428	if (err < 0)
429	return err;
430
431	/* initialize streams */
432	azx_init_stream(chip);
433
434	/* initialize chip */
435	azx_init_chip(chip, 1);
436
437	/* codec detection */
438	if (!chip->codec_mask) {
439	dev_err(card->dev, "no codecs found!\n");
440	return -ENODEV;
441	}
442
443	strcpy(card->driver, "tegra-hda");
444	strcpy(card->shortname, "tegra-hda");
445	snprintf(card->longname, sizeof(card->longname),
446	"%s at 0x%lx irq %i",
447	card->shortname, chip->addr, chip->irq);
448
449	return 0;
450	}
451
452	/*
453	* constructor
454	*/
455	static int hda_tegra_create(struct snd_card *card,
456	unsigned int driver_caps,
457	const struct hda_controller_ops *hda_ops,
458	struct hda_tegra *hda)
459	{
460	static struct snd_device_ops ops = {
461	.dev_free = hda_tegra_dev_free,
462	};
463	struct azx *chip;
464	int err;
465
466	chip = &hda->chip;
467
468	spin_lock_init(&chip->reg_lock);
469	mutex_init(&chip->open_mutex);
470	chip->card = card;
471	chip->ops = hda_ops;
472	chip->irq = -1;
473	chip->driver_caps = driver_caps;
474	chip->driver_type = driver_caps & 0xff;
475	chip->dev_index = 0;
476	INIT_LIST_HEAD(&chip->pcm_list);
477	INIT_LIST_HEAD(&chip->list);
478
479	chip->position_fix[0] = POS_FIX_AUTO;
480	chip->position_fix[1] = POS_FIX_AUTO;
481	chip->codec_probe_mask = -1;
482
483	chip->single_cmd = false;
484	chip->snoop = true;
485
486	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
487	if (err < 0) {
488	dev_err(card->dev, "Error creating device\n");
489	return err;
490	}
491
492	return 0;
493	}
494
495	static const struct of_device_id hda_tegra_match[] = {
496	{ .compatible = "nvidia,tegra30-hda" },
497	{},
498	};
f73387cb	499	MODULE_DEVICE_TABLE(of, hda_tegra_match);
3c320f3f DR	500
	501	static int hda_tegra_probe(struct platform_device *pdev)
	502	{
	503	struct snd_card *card;
	504	struct azx *chip;
	505	struct hda_tegra *hda;
	506	int err;
	507	const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY;
	508
	509	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
	510	if (!hda)
	511	return -ENOMEM;
	512	hda->dev = &pdev->dev;
	513	chip = &hda->chip;
	514
	515	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
	516	THIS_MODULE, 0, &card);
	517	if (err < 0) {
	518	dev_err(&pdev->dev, "Error creating card!\n");
	519	return err;
	520	}
	521
	522	err = hda_tegra_create(card, driver_flags, &hda_tegra_ops, hda);
	523	if (err < 0)
	524	goto out_free;
	525	card->private_data = chip;
	526
	527	dev_set_drvdata(&pdev->dev, card);
	528
	529	err = hda_tegra_first_init(chip, pdev);
	530	if (err < 0)
	531	goto out_free;
	532
	533	/* create codec instances */
	534	err = azx_codec_create(chip, NULL, 0, &power_save);
	535	if (err < 0)
	536	goto out_free;
	537
	538	err = azx_codec_configure(chip);
	539	if (err < 0)
	540	goto out_free;
	541
	542	/* create PCM streams */
	543	err = snd_hda_build_pcms(chip->bus);
	544	if (err < 0)
	545	goto out_free;
	546
	547	/* create mixer controls */
	548	err = azx_mixer_create(chip);
	549	if (err < 0)
	550	goto out_free;
	551
	552	err = snd_card_register(chip->card);
	553	if (err < 0)
	554	goto out_free;
	555
	556	chip->running = 1;
	557	power_down_all_codecs(chip);
	558	hda_tegra_notifier_register(chip);
	559
	560	return 0;
	561
	562	out_free:
	563	snd_card_free(card);
564	return err;
565	}
566
567	static int hda_tegra_remove(struct platform_device *pdev)
568	{
569	return snd_card_free(dev_get_drvdata(&pdev->dev));
570	}
571
572	static struct platform_driver tegra_platform_hda = {
573	.driver = {
574	.name = "tegra-hda",
575	.pm = &hda_tegra_pm,
576	.of_match_table = hda_tegra_match,
577	},
578	.probe = hda_tegra_probe,
579	.remove = hda_tegra_remove,
580	};
581	module_platform_driver(tegra_platform_hda);
582
583	MODULE_DESCRIPTION("Tegra HDA bus driver");
584	MODULE_LICENSE("GPL v2");