projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda: Intel: Select AZX_DCAPS_PIO_COMMANDS for Lunar Lake
[linux-2.6-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
586bc4aa 38#include <linux/acpi.h>
65fddcfc 39#include <linux/pgtable.h>
5d890f59 40
27fe48d9
TI		 41#ifdef CONFIG_X86
42/* for snoop control */
7f80f513 43#include <asm/set_memory.h>
50279d9b 44#include <asm/cpufeature.h>
27fe48d9 45#endif
1da177e4
LT		 46#include <sound/core.h>
47#include <sound/initval.h>
98d8fc6c
ML		 48#include <sound/hdaudio.h>
49#include <sound/hda_i915.h>
82d9d54a 50#include <sound/intel-dsp-config.h>
9121947d 51#include <linux/vgaarb.h>
a82d51ed 52#include <linux/vga_switcheroo.h>
5beb5627 53#include <linux/apple-gmux.h>
4918cdab 54#include <linux/firmware.h>
be57bfff 55#include <sound/hda_codec.h>
05e84878 56#include "hda_controller.h"
347de1f8 57#include "hda_intel.h"
1da177e4 58
785d8c4b
LY		 59#define CREATE_TRACE_POINTS
60#include "hda_intel_trace.h"
61
b6050ef6
TI		 62/* position fix mode */
63enum {
64 POS_FIX_AUTO,
65 POS_FIX_LPIB,
66 POS_FIX_POSBUF,
67 POS_FIX_VIACOMBO,
68 POS_FIX_COMBO,
f87e7f25 69 POS_FIX_SKL,
c02f77d3 70 POS_FIX_FIFO,
b6050ef6
TI		 71};
72
9a34af4a
TI		 73/* Defines for ATI HD Audio support in SB450 south bridge */
74#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
75#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
76
77/* Defines for Nvidia HDA support */
78#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
79#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
80#define NVIDIA_HDA_ISTRM_COH 0x4d
81#define NVIDIA_HDA_OSTRM_COH 0x4c
82#define NVIDIA_HDA_ENABLE_COHBIT 0x01
83
84/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 85#define INTEL_HDA_CGCTL 0x48
86#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 87#define INTEL_SCH_HDA_DEVC 0x78
88#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
89
33124929
TI		 90/* max number of SDs */
91/* ICH, ATI and VIA have 4 playback and 4 capture */
92#define ICH6_NUM_CAPTURE 4
93#define ICH6_NUM_PLAYBACK 4
94
95/* ULI has 6 playback and 5 capture */
96#define ULI_NUM_CAPTURE 5
97#define ULI_NUM_PLAYBACK 6
98
99/* ATI HDMI may have up to 8 playbacks and 0 capture */
100#define ATIHDMI_NUM_CAPTURE 0
101#define ATIHDMI_NUM_PLAYBACK 8
102
1da177e4 103
5aba4f8e
TI		 104static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
105static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 106static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 107static char *model[SNDRV_CARDS];
1dac6695 108static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 109static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 110static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 111static int probe_only[SNDRV_CARDS];
26a6cb6c 112static int jackpoll_ms[SNDRV_CARDS];
41438f13 113static int single_cmd = -1;
71623855 114static int enable_msi = -1;
4ea6fbc8
TI		 115#ifdef CONFIG_SND_HDA_PATCH_LOADER
116static char *patch[SNDRV_CARDS];
117#endif
2dca0bba 118#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 119static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 120 CONFIG_SND_HDA_INPUT_BEEP_MODE};
121#endif
7fba6aea 122static bool dmic_detect = 1;
d045bcef 123static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
1da177e4 124
5aba4f8e 125module_param_array(index, int, NULL, 0444);
1da177e4 126MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 127module_param_array(id, charp, NULL, 0444);
1da177e4 128MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 129module_param_array(enable, bool, NULL, 0444);
130MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
131module_param_array(model, charp, NULL, 0444);
1da177e4 132MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 133module_param_array(position_fix, int, NULL, 0444);
4cb36310 134MODULE_PARM_DESC(position_fix, "DMA pointer read method."
c02f77d3 135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
555e219f
TI		 136module_param_array(bdl_pos_adj, int, NULL, 0644);
137MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 138module_param_array(probe_mask, int, NULL, 0444);
606ad75f 139MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 140module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 141MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 142module_param_array(jackpoll_ms, int, NULL, 0444);
143MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 144module_param(single_cmd, bint, 0444);
d01ce99f
TI		 145MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
146 "(for debugging only).");
ac9ef6cf 147module_param(enable_msi, bint, 0444);
134a11f0 148MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 149#ifdef CONFIG_SND_HDA_PATCH_LOADER
150module_param_array(patch, charp, NULL, 0444);
151MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
152#endif
2dca0bba 153#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 154module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 155MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 156 "(0=off, 1=on) (default=1).");
2dca0bba 157#endif
7fba6aea
TI		 158module_param(dmic_detect, bool, 0444);
159MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
160 "(0=off, 1=on) (default=1); "
161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
d045bcef
JK		 162module_param(ctl_dev_id, bool, 0444);
163MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
606ad75f 164
83012a7c 165#ifdef CONFIG_PM
65fcd41d 166static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 167static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 168 .set = param_set_xint,
169 .get = param_get_int,
170};
171#define param_check_xint param_check_int
172
fee2fba3 173static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 174module_param(power_save, xint, 0644);
fee2fba3
TI		 175MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
176 "(in second, 0 = disable).");
1da177e4 177
40088dc4
TI		 178static bool pm_blacklist = true;
179module_param(pm_blacklist, bool, 0644);
6317e5eb 180MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
40088dc4 181
dee1b66c
TI		 182/* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
8fc24426
TI		 186static bool power_save_controller = 1;
187module_param(power_save_controller, bool, 0644);
dee1b66c 188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 189#else
bb573928 190#define power_save 0
83012a7c 191#endif /* CONFIG_PM */
dee1b66c 192
7bfe059e
TI		 193static int align_buffer_size = -1;
194module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 195MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
27fe48d9 198#ifdef CONFIG_X86
7c732015
TI		 199static int hda_snoop = -1;
200module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 201MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 202#else
203#define hda_snoop true
27fe48d9
TI		 204#endif
205
206
1da177e4 207MODULE_LICENSE("GPL");
1da177e4
LT		 208MODULE_DESCRIPTION("Intel HDA driver");
209
a82d51ed 210#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 211#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 212#define SUPPORT_VGA_SWITCHEROO
213#endif
214#endif
215
216
1da177e4 217/*
1da177e4 218 */
1da177e4 219
07e4ca50
TI		 220/* driver types */
221enum {
222 AZX_DRIVER_ICH,
32679f95 223 AZX_DRIVER_PCH,
4979bca9 224 AZX_DRIVER_SCH,
a4b4793f 225 AZX_DRIVER_SKL,
fab1285a 226 AZX_DRIVER_HDMI,
07e4ca50 227 AZX_DRIVER_ATI,
778b6e1b 228 AZX_DRIVER_ATIHDMI,
1815b34a 229 AZX_DRIVER_ATIHDMI_NS,
c51e4310 230 AZX_DRIVER_GFHDMI,
07e4ca50
TI		 231 AZX_DRIVER_VIA,
232 AZX_DRIVER_SIS,
233 AZX_DRIVER_ULI,
da3fca21 234 AZX_DRIVER_NVIDIA,
f269002e 235 AZX_DRIVER_TERA,
14d34f16 236 AZX_DRIVER_CTX,
5ae763b1 237 AZX_DRIVER_CTHDA,
c563f473 238 AZX_DRIVER_CMEDIA,
b6fcab14 239 AZX_DRIVER_ZHAOXIN,
28bd137a 240 AZX_DRIVER_LOONGSON,
c4da29ca 241 AZX_DRIVER_GENERIC,
2f5983f2 242 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 243};
244
37e661ee
TI		 245#define azx_get_snoop_type(chip) \
246 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
247#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
248
b42b4afb
TI		 249/* quirks for old Intel chipsets */
250#define AZX_DCAPS_INTEL_ICH \
f34a4c9d 251 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 252
2ea3c6a2 253/* quirks for Intel PCH */
6603249d 254#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 255 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
f34a4c9d 256 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 257
dba9b7b6 258/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 259#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 260 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 261
55913110 262/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 263/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 264#define AZX_DCAPS_INTEL_PCH \
f5dac54d 265 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 266
6603249d 267/* HSW HDMI */
33499a15 268#define AZX_DCAPS_INTEL_HASWELL \
103884a3 269 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 270 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
f34a4c9d 271 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 272
54a0405d
LY		 273/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
274#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 275 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 276 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
f34a4c9d 277 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 278
40cc2392 279#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 280 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 281
2d846c74 282#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 284 AZX_DCAPS_I915_COMPONENT)
2d846c74 285
d6795827 286#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 287 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 288 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 289
2756d914 290#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
c87693da 291
f20bee38
PU		 292#define AZX_DCAPS_INTEL_LNL \
293 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS)
294
9477c58e
TI		 295/* quirks for ATI SB / AMD Hudson */
296#define AZX_DCAPS_PRESET_ATI_SB \
f34a4c9d 297 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
37e661ee 298 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 299
300/* quirks for ATI/AMD HDMI */
301#define AZX_DCAPS_PRESET_ATI_HDMI \
f34a4c9d 302 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
db79afa1 303 AZX_DCAPS_NO_MSI64)
9477c58e 304
37e661ee
TI		 305/* quirks for ATI HDMI with snoop off */
306#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
307 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
308
c02f77d3
TI		 309/* quirks for AMD SB */
310#define AZX_DCAPS_PRESET_AMD_SB \
f34a4c9d 311 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
c0f1886d
TI		 312 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
313 AZX_DCAPS_RETRY_PROBE)
c02f77d3 314
9477c58e
TI		 315/* quirks for Nvidia */
316#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 317 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 318 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 319
5ae763b1 320#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 321 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 322 AZX_DCAPS_NO_64BIT |\
37e661ee 323 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 324
a82d51ed 325/*
2b760d88 326 * vga_switcheroo support
a82d51ed
TI		 327 */
328#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 329#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
dd23e1d5 330#define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
5cb543db
TI		 331#else
332#define use_vga_switcheroo(chip) 0
37a3a98e 333#define needs_eld_notify_link(chip) false
5cb543db
TI		 334#endif
335
bf82326f 336static const char * const driver_short_names[] = {
07e4ca50 337 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 338 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 339 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 340 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 341 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 342 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 343 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 344 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
c51e4310 345 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
07e4ca50
TI		 346 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
347 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 348 [AZX_DRIVER_ULI] = "HDA ULI M5461",
349 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 350 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 351 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 352 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 353 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
b6fcab14 354 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
28bd137a 355 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
c4da29ca 356 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 357};
358
68e7fffc 359static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 360static void set_default_power_save(struct azx *chip);
111d3af5 361
cb53c626
TI		 362/*
363 * initialize the PCI registers
364 */
365/* update bits in a PCI register byte */
366static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
367 unsigned char mask, unsigned char val)
368{
369 unsigned char data;
370
371 pci_read_config_byte(pci, reg, &data);
372 data &= ~mask;
373 data |= (val & mask);
374 pci_write_config_byte(pci, reg, data);
375}
376
377static void azx_init_pci(struct azx *chip)
378{
37e661ee
TI		 379 int snoop_type = azx_get_snoop_type(chip);
380
cb53c626
TI		 381 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
382 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
383 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 384 * codecs.
385 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 386 */
46f2cc80 387 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 388 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 389 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 390 }
cb53c626 391
9477c58e
TI		 392 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
393 * we need to enable snoop.
394 */
37e661ee 395 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 396 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
397 azx_snoop(chip));
cb53c626 398 update_pci_byte(chip->pci,
27fe48d9
TI		 399 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
400 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 401 }
402
403 /* For NVIDIA HDA, enable snoop */
37e661ee 404 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 405 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
406 azx_snoop(chip));
cb53c626
TI		 407 update_pci_byte(chip->pci,
408 NVIDIA_HDA_TRANSREG_ADDR,
409 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 410 update_pci_byte(chip->pci,
411 NVIDIA_HDA_ISTRM_COH,
412 0x01, NVIDIA_HDA_ENABLE_COHBIT);
413 update_pci_byte(chip->pci,
414 NVIDIA_HDA_OSTRM_COH,
415 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 416 }
417
418 /* Enable SCH/PCH snoop if needed */
37e661ee 419 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 420 unsigned short snoop;
90a5ad52 421 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 422 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
423 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
424 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
425 if (!azx_snoop(chip))
426 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
427 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 428 pci_read_config_word(chip->pci,
429 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 430 }
4e76a883
TI		 431 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
432 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
433 "Disabled" : "Enabled");
da3fca21 434 }
1da177e4
LT		 435}
436
7c23b7c1
LH		 437/*
438 * In BXT-P A0, HD-Audio DMA requests is later than expected,
439 * and makes an audio stream sensitive to system latencies when
440 * 24/32 bits are playing.
441 * Adjusting threshold of DMA fifo to force the DMA request
442 * sooner to improve latency tolerance at the expense of power.
443 */
444static void bxt_reduce_dma_latency(struct azx *chip)
445{
446 u32 val;
447
70eafad8 448 val = azx_readl(chip, VS_EM4L);
7c23b7c1 449 val &= (0x3 << 20);
70eafad8 450 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 451}
452
1f9d3d98
LY		 453/*
454 * ML_LCAP bits:
455 * bit 0: 6 MHz Supported
456 * bit 1: 12 MHz Supported
457 * bit 2: 24 MHz Supported
458 * bit 3: 48 MHz Supported
459 * bit 4: 96 MHz Supported
460 * bit 5: 192 MHz Supported
461 */
462static int intel_get_lctl_scf(struct azx *chip)
463{
464 struct hdac_bus *bus = azx_bus(chip);
bf82326f 465 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
1f9d3d98
LY		 466 u32 val, t;
467 int i;
468
469 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
470
471 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
472 t = preferred_bits[i];
473 if (val & (1 << t))
474 return t;
475 }
476
477 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
478 return 0;
479}
480
481static int intel_ml_lctl_set_power(struct azx *chip, int state)
482{
483 struct hdac_bus *bus = azx_bus(chip);
484 u32 val;
485 int timeout;
486
487 /*
10e794bd
PLB		 488 * Changes to LCTL.SCF are only needed for the first multi-link dealing
489 * with external codecs
1f9d3d98
LY		 490 */
491 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
18afcf90
PLB		 492 val &= ~AZX_ML_LCTL_SPA;
493 val |= state << AZX_ML_LCTL_SPA_SHIFT;
1f9d3d98
LY		 494 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
495 /* wait for CPA */
496 timeout = 50;
497 while (timeout) {
498 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
18afcf90 499 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
1f9d3d98
LY		 500 return 0;
501 timeout--;
502 udelay(10);
503 }
504
505 return -1;
506}
507
508static void intel_init_lctl(struct azx *chip)
509{
510 struct hdac_bus *bus = azx_bus(chip);
511 u32 val;
512 int ret;
513
514 /* 0. check lctl register value is correct or not */
515 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
10e794bd 516 /* only perform additional configurations if the SCF is initially based on 6MHz */
18afcf90 517 if ((val & AZX_ML_LCTL_SCF) != 0)
1f9d3d98
LY		 518 return;
519
520 /*
521 * Before operating on SPA, CPA must match SPA.
522 * Any deviation may result in undefined behavior.
523 */
18afcf90
PLB		 524 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
525 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
1f9d3d98
LY		 526 return;
527
528 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
529 ret = intel_ml_lctl_set_power(chip, 0);
530 udelay(100);
531 if (ret)
532 goto set_spa;
533
10e794bd 534 /* 2. update SCF to select an audio clock different from 6MHz */
18afcf90 535 val &= ~AZX_ML_LCTL_SCF;
1f9d3d98
LY		 536 val |= intel_get_lctl_scf(chip);
537 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
538
539set_spa:
540 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
541 intel_ml_lctl_set_power(chip, 1);
542 udelay(100);
543}
544
0a673521
LH		 545static void hda_intel_init_chip(struct azx *chip, bool full_reset)
546{
98d8fc6c 547 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 548 struct pci_dev *pci = chip->pci;
6639484d 549 u32 val;
0a673521 550
e454ff8e 551 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 552 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 553 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
554 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
555 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
556 }
0a673521 557 azx_init_chip(chip, full_reset);
a4b4793f 558 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 559 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
560 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
561 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
562 }
e454ff8e
TI		 563
564 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 565
566 /* reduce dma latency to avoid noise */
1b21bd7a 567 if (HDA_CONTROLLER_IS_APL(pci))
7c23b7c1 568 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 569
570 if (bus->mlcap != NULL)
571 intel_init_lctl(chip);
0a673521
LH		 572}
573
b6050ef6
TI		 574/* calculate runtime delay from LPIB */
575static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
576 unsigned int pos)
577{
7833c3f8 578 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 579 int stream = substream->stream;
580 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
581 int delay;
582
583 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
584 delay = pos - lpib_pos;
585 else
586 delay = lpib_pos - pos;
587 if (delay < 0) {
7833c3f8 588 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 589 delay = 0;
590 else
7833c3f8 591 delay += azx_dev->core.bufsize;
b6050ef6
TI		 592 }
593
7833c3f8 594 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 595 dev_info(chip->card->dev,
596 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 597 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 598 delay = 0;
599 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
600 chip->get_delay[stream] = NULL;
601 }
602
603 return bytes_to_frames(substream->runtime, delay);
604}
605
9ad593f6
TI		 606static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
607
7ca954a8
DR		 608/* called from IRQ */
609static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
610{
9a34af4a 611 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 612 int ok;
613
614 ok = azx_position_ok(chip, azx_dev);
615 if (ok == 1) {
616 azx_dev->irq_pending = 0;
617 return ok;
2f35c630 618 } else if (ok == 0) {
7ca954a8
DR		 619 /* bogus IRQ, process it later */
620 azx_dev->irq_pending = 1;
2f35c630 621 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 622 }
623 return 0;
624}
625
029d92c2
TI		 626#define display_power(chip, enable) \
627 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 628
9ad593f6
TI		 629/*
630 * Check whether the current DMA position is acceptable for updating
631 * periods. Returns non-zero if it's OK.
632 *
633 * Many HD-audio controllers appear pretty inaccurate about
634 * the update-IRQ timing. The IRQ is issued before actually the
635 * data is processed. So, we need to process it afterwords in a
636 * workqueue.
46243b85
TI		 637 *
638 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
9ad593f6
TI		 639 */
640static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
641{
7833c3f8 642 struct snd_pcm_substream *substream = azx_dev->core.substream;
46243b85 643 struct snd_pcm_runtime *runtime = substream->runtime;
b6050ef6 644 int stream = substream->stream;
e5463720 645 u32 wallclk;
9ad593f6 646 unsigned int pos;
46243b85 647 snd_pcm_uframes_t hwptr, target;
9ad593f6 648
a4d2b853
YS		 649 /*
650 * The value of the WALLCLK register is always 0
651 * on the Loongson controller, so we return directly.
652 */
653 if (chip->driver_type == AZX_DRIVER_LOONGSON)
654 return 1;
655
7833c3f8
TI		 656 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
657 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 658 return -1; /* bogus (too early) interrupt */
fa00e046 659
b6050ef6
TI		 660 if (chip->get_position[stream])
661 pos = chip->get_position[stream](chip, azx_dev);
662 else { /* use the position buffer as default */
663 pos = azx_get_pos_posbuf(chip, azx_dev);
664 if (!pos || pos == (u32)-1) {
665 dev_info(chip->card->dev,
666 "Invalid position buffer, using LPIB read method instead.\n");
667 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 668 if (chip->get_position[0] == azx_get_pos_lpib &&
669 chip->get_position[1] == azx_get_pos_lpib)
670 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 671 pos = azx_get_pos_lpib(chip, azx_dev);
672 chip->get_delay[stream] = NULL;
673 } else {
674 chip->get_position[stream] = azx_get_pos_posbuf;
675 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
676 chip->get_delay[stream] = azx_get_delay_from_lpib;
677 }
678 }
679
7833c3f8 680 if (pos >= azx_dev->core.bufsize)
b6050ef6 681 pos = 0;
9ad593f6 682
7833c3f8 683 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 684 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 685 return -1; /* this shouldn't happen! */
7833c3f8
TI		 686 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
687 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 688 /* NG - it's below the first next period boundary */
4f0189be 689 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 690 azx_dev->core.start_wallclk += wallclk;
46243b85
TI		 691
692 if (azx_dev->core.no_period_wakeup)
693 return 1; /* OK, no need to check period boundary */
694
695 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
696 return 1; /* OK, already in hwptr updating process */
697
698 /* check whether the period gets really elapsed */
699 pos = bytes_to_frames(runtime, pos);
700 hwptr = runtime->hw_ptr_base + pos;
701 if (hwptr < runtime->status->hw_ptr)
702 hwptr += runtime->buffer_size;
703 target = runtime->hw_ptr_interrupt + runtime->period_size;
704 if (hwptr < target) {
705 /* too early wakeup, process it later */
706 return chip->bdl_pos_adj ? 0 : -1;
707 }
708
9ad593f6
TI		 709 return 1; /* OK, it's fine */
710}
711
712/*
713 * The work for pending PCM period updates.
714 */
715static void azx_irq_pending_work(struct work_struct *work)
716{
9a34af4a
TI		 717 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
718 struct azx *chip = &hda->chip;
7833c3f8
TI		 719 struct hdac_bus *bus = azx_bus(chip);
720 struct hdac_stream *s;
721 int pending, ok;
9ad593f6 722
9a34af4a 723 if (!hda->irq_pending_warned) {
4e76a883
TI		 724 dev_info(chip->card->dev,
725 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
726 chip->card->number);
9a34af4a 727 hda->irq_pending_warned = 1;
a6a950a8
TI		 728 }
729
9ad593f6
TI		 730 for (;;) {
731 pending = 0;
a41d1224 732 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 733 list_for_each_entry(s, &bus->stream_list, list) {
734 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 735 if (!azx_dev->irq_pending ||
7833c3f8
TI		 736 !s->substream ||
737 !s->running)
9ad593f6 738 continue;
e5463720
JK		 739 ok = azx_position_ok(chip, azx_dev);
740 if (ok > 0) {
9ad593f6 741 azx_dev->irq_pending = 0;
a41d1224 742 spin_unlock(&bus->reg_lock);
7833c3f8 743 snd_pcm_period_elapsed(s->substream);
a41d1224 744 spin_lock(&bus->reg_lock);
e5463720
JK		 745 } else if (ok < 0) {
746 pending = 0; /* too early */
9ad593f6
TI		 747 } else
748 pending++;
749 }
a41d1224 750 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 751 if (!pending)
752 return;
08af495f 753 msleep(1);
9ad593f6
TI		 754 }
755}
756
757/* clear irq_pending flags and assure no on-going workq */
758static void azx_clear_irq_pending(struct azx *chip)
759{
7833c3f8
TI		 760 struct hdac_bus *bus = azx_bus(chip);
761 struct hdac_stream *s;
9ad593f6 762
a41d1224 763 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 764 list_for_each_entry(s, &bus->stream_list, list) {
765 struct azx_dev *azx_dev = stream_to_azx_dev(s);
766 azx_dev->irq_pending = 0;
767 }
a41d1224 768 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 769}
770
68e7fffc
TI		 771static int azx_acquire_irq(struct azx *chip, int do_disconnect)
772{
a41d1224
TI		 773 struct hdac_bus *bus = azx_bus(chip);
774
437a5a46
TI		 775 if (request_irq(chip->pci->irq, azx_interrupt,
776 chip->msi ? 0 : IRQF_SHARED,
de65360b 777 chip->card->irq_descr, chip)) {
4e76a883
TI		 778 dev_err(chip->card->dev,
779 "unable to grab IRQ %d, disabling device\n",
780 chip->pci->irq);
68e7fffc
TI		 781 if (do_disconnect)
782 snd_card_disconnect(chip->card);
783 return -1;
784 }
a41d1224 785 bus->irq = chip->pci->irq;
f36da940 786 chip->card->sync_irq = bus->irq;
69e13418 787 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 788 return 0;
789}
790
b6050ef6
TI		 791/* get the current DMA position with correction on VIA chips */
792static unsigned int azx_via_get_position(struct azx *chip,
793 struct azx_dev *azx_dev)
794{
795 unsigned int link_pos, mini_pos, bound_pos;
796 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
797 unsigned int fifo_size;
798
1604eeee 799 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 800 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 801 /* Playback, no problem using link position */
802 return link_pos;
803 }
804
805 /* Capture */
806 /* For new chipset,
807 * use mod to get the DMA position just like old chipset
808 */
7833c3f8
TI		 809 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
810 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6 811
956b610c 812 fifo_size = azx_stream(azx_dev)->fifo_size;
b6050ef6
TI		 813
814 if (azx_dev->insufficient) {
815 /* Link position never gather than FIFO size */
816 if (link_pos <= fifo_size)
817 return 0;
818
819 azx_dev->insufficient = 0;
820 }
821
822 if (link_pos <= fifo_size)
7833c3f8 823 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 824 else
825 mini_pos = link_pos - fifo_size;
826
827 /* Find nearest previous boudary */
7833c3f8
TI		 828 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
829 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 830 if (mod_link_pos >= fifo_size)
831 bound_pos = link_pos - mod_link_pos;
832 else if (mod_dma_pos >= mod_mini_pos)
833 bound_pos = mini_pos - mod_mini_pos;
834 else {
7833c3f8
TI		 835 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
836 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 837 bound_pos = 0;
838 }
839
840 /* Calculate real DMA position we want */
841 return bound_pos + mod_dma_pos;
842}
843
c02f77d3
TI		 844#define AMD_FIFO_SIZE 32
845
846/* get the current DMA position with FIFO size correction */
847static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
848{
849 struct snd_pcm_substream *substream = azx_dev->core.substream;
850 struct snd_pcm_runtime *runtime = substream->runtime;
851 unsigned int pos, delay;
852
853 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
854 if (!runtime)
855 return pos;
856
857 runtime->delay = AMD_FIFO_SIZE;
858 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
859 if (azx_dev->insufficient) {
860 if (pos < delay) {
861 delay = pos;
862 runtime->delay = bytes_to_frames(runtime, pos);
863 } else {
864 azx_dev->insufficient = 0;
865 }
866 }
867
868 /* correct the DMA position for capture stream */
869 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
870 if (pos < delay)
871 pos += azx_dev->core.bufsize;
872 pos -= delay;
873 }
874
875 return pos;
876}
877
878static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
879 unsigned int pos)
880{
881 struct snd_pcm_substream *substream = azx_dev->core.substream;
882
883 /* just read back the calculated value in the above */
884 return substream->runtime->delay;
885}
886
6f445784 887static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
472e18f6
ID		 888{
889 azx_stop_chip(chip);
6f445784
TI		 890 if (!skip_link_reset)
891 azx_enter_link_reset(chip);
472e18f6
ID		 892 azx_clear_irq_pending(chip);
893 display_power(chip, false);
894}
895
83012a7c 896#ifdef CONFIG_PM
65fcd41d
TI		 897static DEFINE_MUTEX(card_list_lock);
898static LIST_HEAD(card_list);
899
6f445784
TI		 900static void azx_shutdown_chip(struct azx *chip)
901{
902 __azx_shutdown_chip(chip, false);
903}
904
65fcd41d
TI		 905static void azx_add_card_list(struct azx *chip)
906{
9a34af4a 907 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 908 mutex_lock(&card_list_lock);
9a34af4a 909 list_add(&hda->list, &card_list);
65fcd41d
TI		 910 mutex_unlock(&card_list_lock);
911}
912
913static void azx_del_card_list(struct azx *chip)
914{
9a34af4a 915 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 916 mutex_lock(&card_list_lock);
9a34af4a 917 list_del_init(&hda->list);
65fcd41d
TI		 918 mutex_unlock(&card_list_lock);
919}
920
921/* trigger power-save check at writing parameter */
922static int param_set_xint(const char *val, const struct kernel_param *kp)
923{
9a34af4a 924 struct hda_intel *hda;
65fcd41d 925 struct azx *chip;
65fcd41d
TI		 926 int prev = power_save;
927 int ret = param_set_int(val, kp);
928
929 if (ret || prev == power_save)
930 return ret;
931
932 mutex_lock(&card_list_lock);
9a34af4a
TI		 933 list_for_each_entry(hda, &card_list, list) {
934 chip = &hda->chip;
a41d1224 935 if (!hda->probe_continued || chip->disabled)
65fcd41d 936 continue;
a41d1224 937 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 938 }
939 mutex_unlock(&card_list_lock);
940 return 0;
941}
5c0b9bec 942
5c0b9bec
TI		 943/*
944 * power management
945 */
3baffc4a 946static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 947{
2d9772ef
TI		 948 struct azx *chip;
949 struct hda_intel *hda;
1da177e4 950
2d9772ef 951 if (!card)
3baffc4a 952 return false;
2d9772ef
TI		 953 chip = card->private_data;
954 hda = container_of(chip, struct hda_intel, chip);
342e8449 955 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 956 return false;
957 return true;
958}
959
f5dac54d 960static void __azx_runtime_resume(struct azx *chip)
3baffc4a
TI		 961{
962 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
963 struct hdac_bus *bus = azx_bus(chip);
964 struct hda_codec *codec;
965 int status;
966
e454ff8e
TI		 967 display_power(chip, true);
968 if (hda->need_i915_power)
969 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 970
971 /* Read STATESTS before controller reset */
972 status = azx_readw(chip, STATESTS);
973
974 azx_init_pci(chip);
975 hda_intel_init_chip(chip, true);
976
f5dac54d
KHF		 977 /* Avoid codec resume if runtime resume is for system suspend */
978 if (!chip->pm_prepared) {
a6e7d0a4
KV		 979 list_for_each_codec(codec, &chip->bus) {
980 if (codec->relaxed_resume)
981 continue;
982
983 if (codec->forced_resume || (status & (1 << codec->addr)))
984 pm_request_resume(hda_codec_dev(codec));
985 }
3baffc4a
TI		 986 }
987
988 /* power down again for link-controlled chips */
e454ff8e 989 if (!hda->need_i915_power)
029d92c2 990 display_power(chip, false);
3baffc4a
TI		 991}
992
993#ifdef CONFIG_PM_SLEEP
f5dac54d
KHF		 994static int azx_prepare(struct device *dev)
995{
996 struct snd_card *card = dev_get_drvdata(dev);
997 struct azx *chip;
998
66affb7b
TI		 999 if (!azx_is_pm_ready(card))
1000 return 0;
1001
f5dac54d
KHF		 1002 chip = card->private_data;
1003 chip->pm_prepared = 1;
c8f79808 1004 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
f5dac54d 1005
13661fc4
TI		 1006 flush_work(&azx_bus(chip)->unsol_work);
1007
f5dac54d
KHF		 1008 /* HDA controller always requires different WAKEEN for runtime suspend
1009 * and system suspend, so don't use direct-complete here.
1010 */
1011 return 0;
1012}
1013
1014static void azx_complete(struct device *dev)
1015{
1016 struct snd_card *card = dev_get_drvdata(dev);
1017 struct azx *chip;
1018
66affb7b
TI		 1019 if (!azx_is_pm_ready(card))
1020 return;
1021
f5dac54d 1022 chip = card->private_data;
c8f79808 1023 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
f5dac54d
KHF		 1024 chip->pm_prepared = 0;
1025}
1026
3baffc4a
TI		 1027static int azx_suspend(struct device *dev)
1028{
1029 struct snd_card *card = dev_get_drvdata(dev);
1030 struct azx *chip;
1031 struct hdac_bus *bus;
1032
1033 if (!azx_is_pm_ready(card))
c5c21523
TI		 1034 return 0;
1035
3baffc4a 1036 chip = card->private_data;
a41d1224 1037 bus = azx_bus(chip);
472e18f6 1038 azx_shutdown_chip(chip);
a41d1224
TI		 1039 if (bus->irq >= 0) {
1040 free_irq(bus->irq, chip);
1041 bus->irq = -1;
f36da940 1042 chip->card->sync_irq = -1;
30b35399 1043 }
a07187c9 1044
68e7fffc 1045 if (chip->msi)
43001c95 1046 pci_disable_msi(chip->pci);
785d8c4b
LY		 1047
1048 trace_azx_suspend(chip);
1da177e4
LT		 1049 return 0;
1050}
1051
68cb2b55 1052static int azx_resume(struct device *dev)
1da177e4 1053{
68cb2b55 1054 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1055 struct azx *chip;
2d9772ef 1056
3baffc4a 1057 if (!azx_is_pm_ready(card))
2d9772ef 1058 return 0;
1da177e4 1059
2d9772ef 1060 chip = card->private_data;
68e7fffc 1061 if (chip->msi)
3baffc4a 1062 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1063 chip->msi = 0;
1064 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1065 return -EIO;
c4c8dd6e 1066
f5dac54d 1067 __azx_runtime_resume(chip);
785d8c4b
LY		 1068
1069 trace_azx_resume(chip);
1da177e4
LT		 1070 return 0;
1071}
b8dfc462 1072
3e6db33a
XZ		 1073/* put codec down to D3 at hibernation for Intel SKL+;
1074 * otherwise BIOS may still access the codec and screw up the driver
1075 */
3e6db33a
XZ		 1076static int azx_freeze_noirq(struct device *dev)
1077{
a4b4793f
TI		 1078 struct snd_card *card = dev_get_drvdata(dev);
1079 struct azx *chip = card->private_data;
3e6db33a
XZ		 1080 struct pci_dev *pci = to_pci_dev(dev);
1081
10db5bcc
TI		 1082 if (!azx_is_pm_ready(card))
1083 return 0;
a4b4793f 1084 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1085 pci_set_power_state(pci, PCI_D3hot);
1086
1087 return 0;
1088}
1089
1090static int azx_thaw_noirq(struct device *dev)
1091{
a4b4793f
TI		 1092 struct snd_card *card = dev_get_drvdata(dev);
1093 struct azx *chip = card->private_data;
3e6db33a
XZ		 1094 struct pci_dev *pci = to_pci_dev(dev);
1095
10db5bcc
TI		 1096 if (!azx_is_pm_ready(card))
1097 return 0;
a4b4793f 1098 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1099 pci_set_power_state(pci, PCI_D0);
1100
1101 return 0;
1102}
1103#endif /* CONFIG_PM_SLEEP */
1104
b8dfc462
ML		 1105static int azx_runtime_suspend(struct device *dev)
1106{
1107 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1108 struct azx *chip;
b8dfc462 1109
3baffc4a 1110 if (!azx_is_pm_ready(card))
2d9772ef 1111 return 0;
2d9772ef 1112 chip = card->private_data;
246efa4a 1113
7d4f606c 1114 /* enable controller wake up event */
f5dac54d 1115 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
7d4f606c 1116
472e18f6 1117 azx_shutdown_chip(chip);
785d8c4b 1118 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1119 return 0;
1120}
1121
1122static int azx_runtime_resume(struct device *dev)
1123{
1124 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1125 struct azx *chip;
b8dfc462 1126
3baffc4a 1127 if (!azx_is_pm_ready(card))
2d9772ef 1128 return 0;
2d9772ef 1129 chip = card->private_data;
f5dac54d 1130 __azx_runtime_resume(chip);
7d4f606c
WX		 1131
1132 /* disable controller Wake Up event*/
f5dac54d 1133 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
7d4f606c 1134
785d8c4b 1135 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1136 return 0;
1137}
6eb827d2
TI		 1138
1139static int azx_runtime_idle(struct device *dev)
1140{
1141 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1142 struct azx *chip;
1143 struct hda_intel *hda;
1144
1145 if (!card)
1146 return 0;
6eb827d2 1147
2d9772ef
TI		 1148 chip = card->private_data;
1149 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1150 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1151 return 0;
1152
55ed9cd1 1153 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1154 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1155 return -EBUSY;
1156
37a3a98e 1157 /* ELD notification gets broken when HD-audio bus is off */
dd23e1d5 1158 if (needs_eld_notify_link(chip))
37a3a98e
TI		 1159 return -EBUSY;
1160
6eb827d2
TI		 1161 return 0;
1162}
1163
b8dfc462
ML		 1164static const struct dev_pm_ops azx_pm = {
1165 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a 1166#ifdef CONFIG_PM_SLEEP
f5dac54d
KHF		 1167 .prepare = azx_prepare,
1168 .complete = azx_complete,
3e6db33a
XZ		 1169 .freeze_noirq = azx_freeze_noirq,
1170 .thaw_noirq = azx_thaw_noirq,
1171#endif
6eb827d2 1172 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1173};
1174
68cb2b55
TI		 1175#define AZX_PM_OPS &azx_pm
1176#else
3baffc4a
TI		 1177#define azx_add_card_list(chip) /* NOP */
1178#define azx_del_card_list(chip) /* NOP */
68cb2b55 1179#define AZX_PM_OPS NULL
b8dfc462 1180#endif /* CONFIG_PM */
1da177e4
LT		 1181
1182
48c8b0eb 1183static int azx_probe_continue(struct azx *chip);
a82d51ed 1184
8393ec4a 1185#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1186static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1187
a82d51ed
TI		 1188static void azx_vs_set_state(struct pci_dev *pci,
1189 enum vga_switcheroo_state state)
1190{
1191 struct snd_card *card = pci_get_drvdata(pci);
1192 struct azx *chip = card->private_data;
9a34af4a 1193 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1194 struct hda_codec *codec;
a82d51ed
TI		 1195 bool disabled;
1196
9a34af4a
TI		 1197 wait_for_completion(&hda->probe_wait);
1198 if (hda->init_failed)
a82d51ed
TI		 1199 return;
1200
1201 disabled = (state == VGA_SWITCHEROO_OFF);
1202 if (chip->disabled == disabled)
1203 return;
1204
a41d1224 1205 if (!hda->probe_continued) {
a82d51ed
TI		 1206 chip->disabled = disabled;
1207 if (!disabled) {
4e76a883
TI		 1208 dev_info(chip->card->dev,
1209 "Start delayed initialization\n");
2393e755 1210 if (azx_probe_continue(chip) < 0)
4e76a883 1211 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 1212 }
1213 } else {
2b760d88 1214 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1215 disabled ? "Disabling" : "Enabling");
a82d51ed 1216 if (disabled) {
07f4f97d
LW		 1217 list_for_each_codec(codec, &chip->bus) {
1218 pm_runtime_suspend(hda_codec_dev(codec));
1219 pm_runtime_disable(hda_codec_dev(codec));
1220 }
1221 pm_runtime_suspend(card->dev);
1222 pm_runtime_disable(card->dev);
2b760d88 1223 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1224 * however we have no ACPI handle, so pci/acpi can't put us there,
1225 * put ourselves there */
1226 pci->current_state = PCI_D3cold;
a82d51ed 1227 chip->disabled = true;
a41d1224 1228 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1229 dev_warn(chip->card->dev,
1230 "Cannot lock devices!\n");
a82d51ed 1231 } else {
a41d1224 1232 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1233 chip->disabled = false;
07f4f97d
LW		 1234 pm_runtime_enable(card->dev);
1235 list_for_each_codec(codec, &chip->bus) {
1236 pm_runtime_enable(hda_codec_dev(codec));
1237 pm_runtime_resume(hda_codec_dev(codec));
1238 }
a82d51ed
TI		 1239 }
1240 }
1241}
1242
1243static bool azx_vs_can_switch(struct pci_dev *pci)
1244{
1245 struct snd_card *card = pci_get_drvdata(pci);
1246 struct azx *chip = card->private_data;
9a34af4a 1247 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1248
9a34af4a
TI		 1249 wait_for_completion(&hda->probe_wait);
1250 if (hda->init_failed)
a82d51ed 1251 return false;
a41d1224 1252 if (chip->disabled || !hda->probe_continued)
a82d51ed 1253 return true;
a41d1224 1254 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1255 return false;
a41d1224 1256 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1257 return true;
1258}
1259
37a3a98e
TI		 1260/*
1261 * The discrete GPU cannot power down unless the HDA controller runtime
1262 * suspends, so activate runtime PM on codecs even if power_save == 0.
1263 */
1264static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1265{
1266 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1267 struct hda_codec *codec;
1268
dd23e1d5 1269 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
37a3a98e
TI		 1270 list_for_each_codec(codec, &chip->bus)
1271 codec->auto_runtime_pm = 1;
1272 /* reset the power save setup */
1273 if (chip->running)
1274 set_default_power_save(chip);
1275 }
1276}
1277
1278static void azx_vs_gpu_bound(struct pci_dev *pci,
1279 enum vga_switcheroo_client_id client_id)
1280{
1281 struct snd_card *card = pci_get_drvdata(pci);
1282 struct azx *chip = card->private_data;
37a3a98e
TI		 1283
1284 if (client_id == VGA_SWITCHEROO_DIS)
dd23e1d5 1285 chip->bus.keep_power = 0;
37a3a98e
TI		 1286 setup_vga_switcheroo_runtime_pm(chip);
1287}
1288
e23e7a14 1289static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1290{
9a34af4a 1291 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1292 struct pci_dev *p = get_bound_vga(chip->pci);
bacd8614 1293 struct pci_dev *parent;
a82d51ed 1294 if (p) {
4e76a883 1295 dev_info(chip->card->dev,
2b760d88 1296 "Handle vga_switcheroo audio client\n");
9a34af4a 1297 hda->use_vga_switcheroo = 1;
bacd8614
KHF		 1298
1299 /* cleared in either gpu_bound op or codec probe, or when its
1300 * upstream port has _PR3 (i.e. dGPU).
1301 */
1302 parent = pci_upstream_bridge(p);
1303 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
07f4f97d 1304 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1305 pci_dev_put(p);
1306 }
1307}
1308
1309static const struct vga_switcheroo_client_ops azx_vs_ops = {
1310 .set_gpu_state = azx_vs_set_state,
1311 .can_switch = azx_vs_can_switch,
37a3a98e 1312 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1313};
1314
e23e7a14 1315static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1316{
9a34af4a 1317 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1318 struct pci_dev *p;
128960a9
TI		 1319 int err;
1320
9a34af4a 1321 if (!hda->use_vga_switcheroo)
a82d51ed 1322 return 0;
4aaf448f
JQ		 1323
1324 p = get_bound_vga(chip->pci);
1325 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1326 pci_dev_put(p);
1327
128960a9
TI		 1328 if (err < 0)
1329 return err;
9a34af4a 1330 hda->vga_switcheroo_registered = 1;
246efa4a 1331
128960a9 1332 return 0;
a82d51ed
TI		 1333}
1334#else
1335#define init_vga_switcheroo(chip) /* NOP */
1336#define register_vga_switcheroo(chip) 0
8393ec4a 1337#define check_hdmi_disabled(pci) false
37a3a98e 1338#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1339#endif /* SUPPORT_VGA_SWITCHER */
1340
1da177e4
LT		 1341/*
1342 * destructor
1343 */
2393e755 1344static void azx_free(struct azx *chip)
1da177e4 1345{
c67e2228 1346 struct pci_dev *pci = chip->pci;
a07187c9 1347 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1348 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1349
2393e755
TI		 1350 if (hda->freed)
1351 return;
1352
4f66a9ef 1353 if (azx_has_pm_runtime(chip) && chip->running) {
c67e2228 1354 pm_runtime_get_noresume(&pci->dev);
4f66a9ef
TI		 1355 pm_runtime_forbid(&pci->dev);
1356 pm_runtime_dont_use_autosuspend(&pci->dev);
1357 }
1358
37a3a98e 1359 chip->running = 0;
c67e2228 1360
65fcd41d
TI		 1361 azx_del_card_list(chip);
1362
9a34af4a
TI		 1363 hda->init_failed = 1; /* to be sure */
1364 complete_all(&hda->probe_wait);
f4c482a4 1365
9a34af4a 1366 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1367 if (chip->disabled && hda->probe_continued)
1368 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1369 if (hda->vga_switcheroo_registered)
128960a9 1370 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1371 }
1372
a41d1224 1373 if (bus->chip_init) {
9ad593f6 1374 azx_clear_irq_pending(chip);
7833c3f8 1375 azx_stop_all_streams(chip);
1a7f60b9 1376 azx_stop_chip(chip);
1da177e4
LT		 1377 }
1378
a41d1224
TI		 1379 if (bus->irq >= 0)
1380 free_irq(bus->irq, (void*)chip);
1da177e4 1381
67908994 1382 azx_free_stream_pages(chip);
a41d1224
TI		 1383 azx_free_streams(chip);
1384 snd_hdac_bus_exit(bus);
1385
4918cdab 1386#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1387 release_firmware(chip->fw);
4918cdab 1388#endif
e454ff8e 1389 display_power(chip, false);
98d8fc6c 1390
fc18282c 1391 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1392 snd_hdac_i915_exit(bus);
1da177e4 1393
2393e755 1394 hda->freed = 1;
1da177e4
LT		 1395}
1396
a41d1224
TI		 1397static int azx_dev_disconnect(struct snd_device *device)
1398{
1399 struct azx *chip = device->device_data;
ca58f551 1400 struct hdac_bus *bus = azx_bus(chip);
a41d1224
TI		 1401
1402 chip->bus.shutdown = 1;
ca58f551
TI		 1403 cancel_work_sync(&bus->unsol_work);
1404
a41d1224
TI		 1405 return 0;
1406}
1407
a98f90fd 1408static int azx_dev_free(struct snd_device *device)
1da177e4 1409{
2393e755
TI		 1410 azx_free(device->device_data);
1411 return 0;
1da177e4
LT		 1412}
1413
8393ec4a 1414#ifdef SUPPORT_VGA_SWITCHEROO
586bc4aa
AD		 1415#ifdef CONFIG_ACPI
1416/* ATPX is in the integrated GPU's namespace */
1417static bool atpx_present(void)
1418{
1419 struct pci_dev *pdev = NULL;
1420 acpi_handle dhandle, atpx_handle;
1421 acpi_status status;
1422
9ed8fcfd
SJ		 1423 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
1424 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
1425 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
1426 continue;
1427
586bc4aa
AD		 1428 dhandle = ACPI_HANDLE(&pdev->dev);
1429 if (dhandle) {
1430 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
10e92724 1431 if (ACPI_SUCCESS(status)) {
586bc4aa
AD		 1432 pci_dev_put(pdev);
1433 return true;
1434 }
1435 }
586bc4aa
AD		 1436 }
1437 return false;
1438}
1439#else
1440static bool atpx_present(void)
1441{
1442 return false;
1443}
1444#endif
1445
9121947d 1446/*
2b760d88 1447 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1448 */
e23e7a14 1449static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1450{
1451 struct pci_dev *p;
1452
1453 /* check only discrete GPU */
1454 switch (pci->vendor) {
1455 case PCI_VENDOR_ID_ATI:
1456 case PCI_VENDOR_ID_AMD:
586bc4aa
AD		 1457 if (pci->devfn == 1) {
1458 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1459 pci->bus->number, 0);
1460 if (p) {
1461 /* ATPX is in the integrated GPU's ACPI namespace
1462 * rather than the dGPU's namespace. However,
1463 * the dGPU is the one who is involved in
1464 * vgaswitcheroo.
1465 */
1466 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
5beb5627 1467 (atpx_present() || apple_gmux_detect(NULL, NULL)))
586bc4aa
AD		 1468 return p;
1469 pci_dev_put(p);
1470 }
1471 }
1472 break;
9121947d
TI		 1473 case PCI_VENDOR_ID_NVIDIA:
1474 if (pci->devfn == 1) {
1475 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1476 pci->bus->number, 0);
1477 if (p) {
b6d7b362 1478 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1479 return p;
1480 pci_dev_put(p);
1481 }
1482 }
1483 break;
1484 }
1485 return NULL;
1486}
1487
e23e7a14 1488static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1489{
1490 bool vga_inactive = false;
1491 struct pci_dev *p = get_bound_vga(pci);
1492
1493 if (p) {
12b78a7f 1494 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1495 vga_inactive = true;
1496 pci_dev_put(p);
1497 }
1498 return vga_inactive;
1499}
8393ec4a 1500#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1501
3372a153 1502/*
6317e5eb 1503 * allow/deny-listing for position_fix
3372a153 1504 */
a5dc05e4 1505static const struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1506 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1507 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1508 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1509 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1510 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1511 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1512 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1513 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1514 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1515 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1516 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1517 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1518 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1519 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1520 {}
1521};
1522
e23e7a14 1523static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1524{
1525 const struct snd_pci_quirk *q;
1526
c673ba1c 1527 switch (fix) {
1dac6695 1528 case POS_FIX_AUTO:
c673ba1c
TI		 1529 case POS_FIX_LPIB:
1530 case POS_FIX_POSBUF:
4cb36310 1531 case POS_FIX_VIACOMBO:
a6f2fd55 1532 case POS_FIX_COMBO:
f87e7f25 1533 case POS_FIX_SKL:
c02f77d3 1534 case POS_FIX_FIFO:
c673ba1c
TI		 1535 return fix;
1536 }
1537
c673ba1c
TI		 1538 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1539 if (q) {
4e76a883
TI		 1540 dev_info(chip->card->dev,
1541 "position_fix set to %d for device %04x:%04x\n",
1542 q->value, q->subvendor, q->subdevice);
c673ba1c 1543 return q->value;
3372a153 1544 }
bdd9ef24
DH		 1545
1546 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1547 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1548 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1549 return POS_FIX_VIACOMBO;
9477c58e 1550 }
c02f77d3
TI		 1551 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1552 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1553 return POS_FIX_FIFO;
1554 }
9477c58e 1555 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1556 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1557 return POS_FIX_LPIB;
bdd9ef24 1558 }
a4b4793f 1559 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1560 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1561 return POS_FIX_SKL;
1562 }
c673ba1c 1563 return POS_FIX_AUTO;
3372a153
TI		 1564}
1565
b6050ef6
TI		 1566static void assign_position_fix(struct azx *chip, int fix)
1567{
bf82326f 1568 static const azx_get_pos_callback_t callbacks[] = {
b6050ef6
TI		 1569 [POS_FIX_AUTO] = NULL,
1570 [POS_FIX_LPIB] = azx_get_pos_lpib,
1571 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1572 [POS_FIX_VIACOMBO] = azx_via_get_position,
1573 [POS_FIX_COMBO] = azx_get_pos_lpib,
c4ca3871 1574 [POS_FIX_SKL] = azx_get_pos_posbuf,
c02f77d3 1575 [POS_FIX_FIFO] = azx_get_pos_fifo,
b6050ef6
TI		 1576 };
1577
1578 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1579
1580 /* combo mode uses LPIB only for playback */
1581 if (fix == POS_FIX_COMBO)
1582 chip->get_position[1] = NULL;
1583
f87e7f25 1584 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1585 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1586 chip->get_delay[0] = chip->get_delay[1] =
1587 azx_get_delay_from_lpib;
1588 }
1589
c02f77d3
TI		 1590 if (fix == POS_FIX_FIFO)
1591 chip->get_delay[0] = chip->get_delay[1] =
1592 azx_get_delay_from_fifo;
b6050ef6
TI		 1593}
1594
669ba27a 1595/*
6317e5eb 1596 * deny-lists for probe_mask
669ba27a 1597 */
a5dc05e4 1598static const struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1599 /* Thinkpad often breaks the controller communication when accessing
1600 * to the non-working (or non-existing) modem codec slot.
1601 */
1602 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1603 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1604 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1605 /* broken BIOS */
1606 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1607 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1608 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1609 /* forced codec slots */
93574844 1610 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1611 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
dd8e5b16 1612 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
f3af9051
JK		 1613 /* WinFast VP200 H (Teradici) user reported broken communication */
1614 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1615 {}
1616};
1617
f1eaaeec
TI		 1618#define AZX_FORCE_CODEC_MASK 0x100
1619
e23e7a14 1620static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1621{
1622 const struct snd_pci_quirk *q;
1623
f1eaaeec
TI		 1624 chip->codec_probe_mask = probe_mask[dev];
1625 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1626 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1627 if (q) {
4e76a883
TI		 1628 dev_info(chip->card->dev,
1629 "probe_mask set to 0x%x for device %04x:%04x\n",
1630 q->value, q->subvendor, q->subdevice);
f1eaaeec 1631 chip->codec_probe_mask = q->value;
669ba27a
TI		 1632 }
1633 }
f1eaaeec
TI		 1634
1635 /* check forced option */
1636 if (chip->codec_probe_mask != -1 &&
1637 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1638 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1639 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1640 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1641 }
669ba27a
TI		 1642}
1643
4d8e22e0 1644/*
6317e5eb 1645 * allow/deny-list for enable_msi
4d8e22e0 1646 */
6317e5eb 1647static const struct snd_pci_quirk msi_deny_list[] = {
693e0cb0
DH		 1648 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1649 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1650 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1651 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1652 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1653 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1654 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1655 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1656 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1657 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1658 {}
1659};
1660
e23e7a14 1661static void check_msi(struct azx *chip)
4d8e22e0
TI		 1662{
1663 const struct snd_pci_quirk *q;
1664
71623855
TI		 1665 if (enable_msi >= 0) {
1666 chip->msi = !!enable_msi;
4d8e22e0 1667 return;
71623855
TI		 1668 }
1669 chip->msi = 1; /* enable MSI as default */
6317e5eb 1670 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
4d8e22e0 1671 if (q) {
4e76a883
TI		 1672 dev_info(chip->card->dev,
1673 "msi for device %04x:%04x set to %d\n",
1674 q->subvendor, q->subdevice, q->value);
4d8e22e0 1675 chip->msi = q->value;
80c43ed7
TI		 1676 return;
1677 }
1678
1679 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1680 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1681 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1682 chip->msi = 0;
4d8e22e0
TI		 1683 }
1684}
1685
a1585d76 1686/* check the snoop mode availability */
e23e7a14 1687static void azx_check_snoop_available(struct azx *chip)
a1585d76 1688{
7c732015 1689 int snoop = hda_snoop;
a1585d76 1690
7c732015
TI		 1691 if (snoop >= 0) {
1692 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1693 snoop ? "snoop" : "non-snoop");
1694 chip->snoop = snoop;
78c9be61 1695 chip->uc_buffer = !snoop;
7c732015
TI		 1696 return;
1697 }
1698
1699 snoop = true;
37e661ee
TI		 1700 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1701 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1702 /* force to non-snoop mode for a new VIA controller
1703 * when BIOS is set
1704 */
7c732015
TI		 1705 u8 val;
1706 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1707 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1708 chip->pci->revision == 0x20))
7c732015 1709 snoop = false;
a1585d76
TI		 1710 }
1711
37e661ee
TI		 1712 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1713 snoop = false;
1714
7c732015 1715 chip->snoop = snoop;
78c9be61 1716 if (!snoop) {
7c732015 1717 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1718 /* C-Media requires non-cached pages only for CORB/RIRB */
1719 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1720 chip->uc_buffer = true;
1721 }
a1585d76 1722}
669ba27a 1723
99a2008d
WX		 1724static void azx_probe_work(struct work_struct *work)
1725{
c0f1886d 1726 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
9a34af4a 1727 azx_probe_continue(&hda->chip);
99a2008d 1728}
99a2008d 1729
4f0189be
TI		 1730static int default_bdl_pos_adj(struct azx *chip)
1731{
2cf721db
TI		 1732 /* some exceptions: Atoms seem problematic with value 1 */
1733 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1734 switch (chip->pci->device) {
3526860f
RS		 1735 case PCI_DEVICE_ID_INTEL_HDA_BYT:
1736 case PCI_DEVICE_ID_INTEL_HDA_BSW:
2cf721db 1737 return 32;
56beedc8
RS		 1738 case PCI_DEVICE_ID_INTEL_HDA_APL:
1739 return 64;
2cf721db
TI		 1740 }
1741 }
1742
4f0189be 1743 switch (chip->driver_type) {
c51e4310 1744 /*
1745 * increase the bdl size for Glenfly Gpus for hardware
1746 * limitation on hdac interrupt interval
1747 */
1748 case AZX_DRIVER_GFHDMI:
1749 return 128;
4f0189be
TI		 1750 case AZX_DRIVER_ICH:
1751 case AZX_DRIVER_PCH:
1752 return 1;
1753 default:
1754 return 32;
1755 }
1756}
1757
1da177e4
LT		 1758/*
1759 * constructor
1760 */
a43ff5ba
TI		 1761static const struct hda_controller_ops pci_hda_ops;
1762
e23e7a14
BP		 1763static int azx_create(struct snd_card *card, struct pci_dev *pci,
1764 int dev, unsigned int driver_caps,
1765 struct azx **rchip)
1da177e4 1766{
41f394a8 1767 static const struct snd_device_ops ops = {
a41d1224 1768 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1769 .dev_free = azx_dev_free,
1770 };
a07187c9 1771 struct hda_intel *hda;
a82d51ed
TI		 1772 struct azx *chip;
1773 int err;
1da177e4
LT		 1774
1775 *rchip = NULL;
bcd72003 1776
3fcaf24e 1777 err = pcim_enable_device(pci);
927fc866 1778 if (err < 0)
1da177e4
LT		 1779 return err;
1780
2393e755 1781 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
3fcaf24e 1782 if (!hda)
1da177e4 1783 return -ENOMEM;
1da177e4 1784
a07187c9 1785 chip = &hda->chip;
62932df8 1786 mutex_init(&chip->open_mutex);
1da177e4
LT		 1787 chip->card = card;
1788 chip->pci = pci;
a43ff5ba 1789 chip->ops = &pci_hda_ops;
9477c58e
TI		 1790 chip->driver_caps = driver_caps;
1791 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1792 check_msi(chip);
555e219f 1793 chip->dev_index = dev;
3a182c84
TI		 1794 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1795 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1796 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1797 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1798 INIT_LIST_HEAD(&hda->list);
a82d51ed 1799 init_vga_switcheroo(chip);
9a34af4a 1800 init_completion(&hda->probe_wait);
1da177e4 1801
b6050ef6 1802 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1803
41438f13
TI		 1804 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1805 chip->fallback_to_single_cmd = 1;
1806 else /* explicitly set to single_cmd or not */
1807 chip->single_cmd = single_cmd;
1808
a1585d76 1809 azx_check_snoop_available(chip);
c74db86b 1810
4f0189be
TI		 1811 if (bdl_pos_adj[dev] < 0)
1812 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1813 else
1814 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1815
19abfefd 1816 err = azx_bus_init(chip, model[dev]);
3fcaf24e 1817 if (err < 0)
a41d1224 1818 return err;
a41d1224 1819
619a1f19
TI		 1820 /* use the non-cached pages in non-snoop mode */
1821 if (!azx_snoop(chip))
37137ec2 1822 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
619a1f19 1823
7d9a1808
TI		 1824 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1825 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
5f2cb361 1826 chip->bus.core.needs_damn_long_delay = 1;
7d9a1808
TI		 1827 }
1828
6317f744
TI		 1829 check_probe_mask(chip, dev);
1830
a82d51ed
TI		 1831 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1832 if (err < 0) {
4e76a883 1833 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1834 azx_free(chip);
1835 return err;
1836 }
1837
99a2008d 1838 /* continue probing in work context as may trigger request module */
c0f1886d 1839 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1840
a82d51ed 1841 *rchip = chip;
99a2008d 1842
a82d51ed
TI		 1843 return 0;
1844}
1845
48c8b0eb 1846static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1847{
1848 int dev = chip->dev_index;
1849 struct pci_dev *pci = chip->pci;
1850 struct snd_card *card = chip->card;
a41d1224 1851 struct hdac_bus *bus = azx_bus(chip);
67908994 1852 int err;
a82d51ed 1853 unsigned short gcap;
413cbf46 1854 unsigned int dma_bits = 64;
a82d51ed 1855
07e4ca50
TI		 1856#if BITS_PER_LONG != 64
1857 /* Fix up base address on ULI M5461 */
1858 if (chip->driver_type == AZX_DRIVER_ULI) {
1859 u16 tmp3;
1860 pci_read_config_word(pci, 0x40, &tmp3);
1861 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1862 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1863 }
1864#endif
c51e4310 1865 /*
1866 * Fix response write request not synced to memory when handle
1867 * hdac interrupt on Glenfly Gpus
1868 */
1869 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1870 bus->polling_mode = 1;
07e4ca50 1871
cbc3e98a
YS		 1872 if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1873 bus->polling_mode = 1;
1874 bus->not_use_interrupts = 1;
942ccdd8 1875 bus->access_sdnctl_in_dword = 1;
cbc3e98a
YS		 1876 }
1877
3fcaf24e 1878 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
a82d51ed 1879 if (err < 0)
1da177e4 1880 return err;
1da177e4 1881
a41d1224 1882 bus->addr = pci_resource_start(pci, 0);
3fcaf24e 1883 bus->remap_addr = pcim_iomap_table(pci)[0];
1da177e4 1884
a4b4793f 1885 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1886 snd_hdac_bus_parse_capabilities(bus);
1887
1888 /*
1889 * Some Intel CPUs has always running timer (ART) feature and
1890 * controller may have Global time sync reporting capability, so
1891 * check both of these before declaring synchronized time reporting
1892 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1893 */
1894 chip->gts_present = false;
1895
1896#ifdef CONFIG_X86
1897 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1898 chip->gts_present = true;
1899#endif
1900
db79afa1
BH		 1901 if (chip->msi) {
1902 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1903 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1904 pci->no_64bit_msi = true;
1905 }
68e7fffc
TI		 1906 if (pci_enable_msi(pci) < 0)
1907 chip->msi = 0;
db79afa1 1908 }
7376d013 1909
1da177e4 1910 pci_set_master(pci);
1da177e4 1911
bcd72003 1912 gcap = azx_readw(chip, GCAP);
4e76a883 1913 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1914
413cbf46
TI		 1915 /* AMD devices support 40 or 48bit DMA, take the safe one */
1916 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1917 dma_bits = 40;
1918
dc4c2e6b 1919 /* disable SB600 64bit support for safety */
9477c58e 1920 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1921 struct pci_dev *p_smbus;
413cbf46 1922 dma_bits = 40;
dc4c2e6b
AB		 1923 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1924 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1925 NULL);
1926 if (p_smbus) {
1927 if (p_smbus->revision < 0x30)
fb1d8ac2 1928 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1929 pci_dev_put(p_smbus);
1930 }
1931 }
09240cf4 1932
3ab7511e
AB		 1933 /* NVidia hardware normally only supports up to 40 bits of DMA */
1934 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1935 dma_bits = 40;
1936
9477c58e
TI		 1937 /* disable 64bit DMA address on some devices */
1938 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1939 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1940 gcap &= ~AZX_GCAP_64OK;
9477c58e 1941 }
396087ea 1942
2ae66c26 1943 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1944 if (align_buffer_size >= 0)
1945 chip->align_buffer_size = !!align_buffer_size;
1946 else {
103884a3 1947 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1948 chip->align_buffer_size = 0;
7bfe059e
TI		 1949 else
1950 chip->align_buffer_size = 1;
1951 }
2ae66c26 1952
cf7aaca8 1953 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1954 if (!(gcap & AZX_GCAP_64OK))
1955 dma_bits = 32;
669f65ea
TI		 1956 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1957 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
acd289e0 1958 dma_set_max_seg_size(&pci->dev, UINT_MAX);
cf7aaca8 1959
8b6ed8e7
TI		 1960 /* read number of streams from GCAP register instead of using
1961 * hardcoded value
1962 */
1963 chip->capture_streams = (gcap >> 8) & 0x0f;
1964 chip->playback_streams = (gcap >> 12) & 0x0f;
1965 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1966 /* gcap didn't give any info, switching to old method */
1967
1968 switch (chip->driver_type) {
1969 case AZX_DRIVER_ULI:
1970 chip->playback_streams = ULI_NUM_PLAYBACK;
1971 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1972 break;
1973 case AZX_DRIVER_ATIHDMI:
1815b34a 1974 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1975 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1976 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1977 break;
c51e4310 1978 case AZX_DRIVER_GFHDMI:
c4da29ca 1979 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1980 default:
1981 chip->playback_streams = ICH6_NUM_PLAYBACK;
1982 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1983 break;
1984 }
07e4ca50 1985 }
8b6ed8e7
TI		 1986 chip->capture_index_offset = 0;
1987 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1988 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1989
df56c3db
JK		 1990 /* sanity check for the SDxCTL.STRM field overflow */
1991 if (chip->num_streams > 15 &&
1992 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1993 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1994 "forcing separate stream tags", chip->num_streams);
1995 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1996 }
1997
a41d1224
TI		 1998 /* initialize streams */
1999 err = azx_init_streams(chip);
81740861 2000 if (err < 0)
a82d51ed 2001 return err;
1da177e4 2002
a41d1224
TI		 2003 err = azx_alloc_stream_pages(chip);
2004 if (err < 0)
2005 return err;
1da177e4
LT		 2006
2007 /* initialize chip */
cb53c626 2008 azx_init_pci(chip);
e4d9e513 2009
e454ff8e 2010 snd_hdac_i915_set_bclk(bus);
e4d9e513 2011
0a673521 2012 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 2013
2014 /* codec detection */
a41d1224 2015 if (!azx_bus(chip)->codec_mask) {
4e76a883 2016 dev_err(card->dev, "no codecs found!\n");
9479e75f 2017 /* keep running the rest for the runtime PM */
1da177e4
LT		 2018 }
2019
f495222e
TI		 2020 if (azx_acquire_irq(chip, 0) < 0)
2021 return -EBUSY;
2022
07e4ca50 2023 strcpy(card->driver, "HDA-Intel");
75b1a8f9 2024 strscpy(card->shortname, driver_short_names[chip->driver_type],
18cb7109
TI		 2025 sizeof(card->shortname));
2026 snprintf(card->longname, sizeof(card->longname),
2027 "%s at 0x%lx irq %i",
a41d1224 2028 card->shortname, bus->addr, bus->irq);
07e4ca50 2029
1da177e4 2030 return 0;
1da177e4
LT		 2031}
2032
97c6a3d1 2033#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 2034/* callback from request_firmware_nowait() */
2035static void azx_firmware_cb(const struct firmware *fw, void *context)
2036{
2037 struct snd_card *card = context;
2038 struct azx *chip = card->private_data;
5cb543db 2039
25faa4bd
TI		 2040 if (fw)
2041 chip->fw = fw;
2042 else
2043 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
5cb543db
TI		 2044 if (!chip->disabled) {
2045 /* continue probing */
25faa4bd 2046 azx_probe_continue(chip);
5cb543db 2047 }
5cb543db 2048}
97c6a3d1 2049#endif
5cb543db 2050
f46ea609
DR		 2051static int disable_msi_reset_irq(struct azx *chip)
2052{
a41d1224 2053 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2054 int err;
2055
a41d1224
TI		 2056 free_irq(bus->irq, chip);
2057 bus->irq = -1;
f36da940 2058 chip->card->sync_irq = -1;
f46ea609
DR		 2059 pci_disable_msi(chip->pci);
2060 chip->msi = 0;
2061 err = azx_acquire_irq(chip, 1);
2062 if (err < 0)
2063 return err;
2064
2065 return 0;
2066}
2067
6317e5eb 2068/* Denylist for skipping the whole probe:
3c6fd1f0
TI		 2069 * some HD-audio PCI entries are exposed without any codecs, and such devices
2070 * should be ignored from the beginning.
2071 */
6317e5eb 2072static const struct pci_device_id driver_denylist[] = {
977dfef4
TI		 2073 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2074 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2075 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
df42ee7e 2076 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */
3c6fd1f0
TI		 2077 {}
2078};
2079
a43ff5ba
TI		 2080static const struct hda_controller_ops pci_hda_ops = {
2081 .disable_msi_reset_irq = disable_msi_reset_irq,
7ca954a8 2082 .position_check = azx_position_check,
40830813
DR		 2083};
2084
69458e2c
TI		 2085static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2086
e23e7a14
BP		 2087static int azx_probe(struct pci_dev *pci,
2088 const struct pci_device_id *pci_id)
1da177e4 2089{
a98f90fd 2090 struct snd_card *card;
9a34af4a 2091 struct hda_intel *hda;
a98f90fd 2092 struct azx *chip;
aad730d0 2093 bool schedule_probe;
69458e2c 2094 int dev;
927fc866 2095 int err;
1da177e4 2096
6317e5eb
TI		 2097 if (pci_match_id(driver_denylist, pci)) {
2098 dev_info(&pci->dev, "Skipping the device on the denylist\n");
3c6fd1f0
TI		 2099 return -ENODEV;
2100 }
2101
69458e2c 2102 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
5aba4f8e
TI		 2103 if (dev >= SNDRV_CARDS)
2104 return -ENODEV;
2105 if (!enable[dev]) {
69458e2c 2106 set_bit(dev, probed_devs);
5aba4f8e
TI		 2107 return -ENOENT;
2108 }
2109
82d9d54a
JK		 2110 /*
2111 * stop probe if another Intel's DSP driver should be activated
2112 */
7fba6aea 2113 if (dmic_detect) {
82d9d54a 2114 err = snd_intel_dsp_driver_probe(pci);
ae035947
PLB		 2115 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2116 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
82d9d54a 2117 return -ENODEV;
ae035947 2118 }
7fba6aea
TI		 2119 } else {
2120 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
82d9d54a
JK		 2121 }
2122
60c5772b
TI		 2123 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2124 0, &card);
e58de7ba 2125 if (err < 0) {
4e76a883 2126 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2127 return err;
1da177e4
LT		 2128 }
2129
a43ff5ba 2130 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2131 if (err < 0)
2132 goto out_free;
421a1252 2133 card->private_data = chip;
9a34af4a 2134 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2135
2136 pci_set_drvdata(pci, card);
2137
65cbbfa4
ML		 2138#ifdef CONFIG_SND_HDA_I915
2139 /* bind with i915 if needed */
2140 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
e6d0c13e 2141 err = snd_hdac_i915_init(azx_bus(chip));
65cbbfa4 2142 if (err < 0) {
9e88b493
ML		 2143 if (err == -EPROBE_DEFER)
2144 goto out_free;
2145
65cbbfa4
ML		 2146 /* if the controller is bound only with HDMI/DP
2147 * (for HSW and BDW), we need to abort the probe;
2148 * for other chips, still continue probing as other
2149 * codecs can be on the same link.
2150 */
2151 if (HDA_CONTROLLER_IN_GPU(pci)) {
2152 dev_err_probe(card->dev, err,
2153 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2154
2155 goto out_free;
2156 } else {
2157 /* don't bother any longer */
2158 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2159 }
2160 }
2161
2162 /* HSW/BDW controllers need this power */
2163 if (HDA_CONTROLLER_IN_GPU(pci))
2164 hda->need_i915_power = true;
2165 }
2166#else
2167 if (HDA_CONTROLLER_IN_GPU(pci))
2168 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2169#endif
2170
f4c482a4
TI		 2171 err = register_vga_switcheroo(chip);
2172 if (err < 0) {
2b760d88 2173 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2174 goto out_free;
2175 }
2176
2177 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2178 dev_info(card->dev, "VGA controller is disabled\n");
2179 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2180 chip->disabled = true;
2181 }
2182
aad730d0 2183 schedule_probe = !chip->disabled;
1da177e4 2184
4918cdab
TI		 2185#ifdef CONFIG_SND_HDA_PATCH_LOADER
2186 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2187 dev_info(card->dev, "Applying patch firmware '%s'\n",
2188 patch[dev]);
5cb543db
TI		 2189 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2190 &pci->dev, GFP_KERNEL, card,
2191 azx_firmware_cb);
4918cdab
TI		 2192 if (err < 0)
2193 goto out_free;
aad730d0 2194 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2195 }
2196#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2197
aad730d0 2198 if (schedule_probe)
c0f1886d 2199 schedule_delayed_work(&hda->probe_work, 0);
a82d51ed 2200
69458e2c 2201 set_bit(dev, probed_devs);
88d071fc 2202 if (chip->disabled)
9a34af4a 2203 complete_all(&hda->probe_wait);
a82d51ed
TI		 2204 return 0;
2205
2206out_free:
ad6413bc 2207 pci_set_drvdata(pci, NULL);
a82d51ed
TI		 2208 snd_card_free(card);
2209 return err;
2210}
2211
1ba8f9d3
HG		 2212#ifdef CONFIG_PM
2213/* On some boards setting power_save to a non 0 value leads to clicking /
2214 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2215 * figure out how to avoid these sounds, but that is not always feasible.
2216 * So we keep a list of devices where we disable powersaving as its known
2217 * to causes problems on these devices.
2218 */
6317e5eb 2219static const struct snd_pci_quirk power_save_denylist[] = {
1ba8f9d3 2220 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2221 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2222 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2223 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2224 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2225 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2226 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2227 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
38d9c12c 2228 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2229 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2230 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2231 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2232 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2233 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2234 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2235 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2236 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2237 /* https://bugs.launchpad.net/bugs/1821663 */
2238 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2239 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2240 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2241 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2242 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
057a28ef 2243 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
721f1e6c
JK		 2244 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2245 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2246 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2247 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2248 /* https://bugs.launchpad.net/bugs/1821663 */
2249 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
a337c355
TI		 2250 /* KONTRON SinglePC may cause a stall at runtime resume */
2251 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
1ba8f9d3
HG		 2252 {}
2253};
2254#endif /* CONFIG_PM */
2255
37a3a98e
TI		 2256static void set_default_power_save(struct azx *chip)
2257{
2258 int val = power_save;
2259
2260#ifdef CONFIG_PM
2261 if (pm_blacklist) {
2262 const struct snd_pci_quirk *q;
2263
6317e5eb 2264 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
37a3a98e 2265 if (q && val) {
6317e5eb 2266 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
37a3a98e
TI		 2267 q->subvendor, q->subdevice);
2268 val = 0;
2269 }
2270 }
2271#endif /* CONFIG_PM */
2272 snd_hda_set_power_save(&chip->bus, val * 1000);
2273}
2274
e62a42ae 2275/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
bf82326f 2276static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
e62a42ae
DR		 2277 [AZX_DRIVER_NVIDIA] = 8,
2278 [AZX_DRIVER_TERA] = 1,
2279};
2280
48c8b0eb 2281static int azx_probe_continue(struct azx *chip)
a82d51ed 2282{
9a34af4a 2283 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2284 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2285 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2286 int dev = chip->dev_index;
2287 int err;
2288
c0f1886d
TI		 2289 if (chip->disabled || hda->init_failed)
2290 return -EIO;
2291 if (hda->probe_retry)
2292 goto probe_retry;
2293
305a0ade 2294 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2295 hda->probe_continued = 1;
795614dd 2296
fcc88d91
TI		 2297 /* Request display power well for the HDA controller or codec. For
2298 * Haswell/Broadwell, both the display HDA controller and codec need
2299 * this power. For other platforms, like Baytrail/Braswell, only the
2300 * display codec needs the power and it can be released after probe.
2301 */
4f799e73 2302 display_power(chip, true);
99a2008d 2303
5c90680e
TI		 2304 err = azx_first_init(chip);
2305 if (err < 0)
2306 goto out_free;
2307
2dca0bba
JK		 2308#ifdef CONFIG_SND_HDA_INPUT_BEEP
2309 chip->beep_mode = beep_mode[dev];
2310#endif
2311
d045bcef
JK		 2312 chip->ctl_dev_id = ctl_dev_id;
2313
1da177e4 2314 /* create codec instances */
9479e75f
TI		 2315 if (bus->codec_mask) {
2316 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2317 if (err < 0)
2318 goto out_free;
2319 }
96d2bd6e 2320
4ea6fbc8 2321#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2322 if (chip->fw) {
a41d1224 2323 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2324 chip->fw->data);
4ea6fbc8
TI		 2325 if (err < 0)
2326 goto out_free;
e39ae856 2327#ifndef CONFIG_PM
4918cdab
TI		 2328 release_firmware(chip->fw); /* no longer needed */
2329 chip->fw = NULL;
e39ae856 2330#endif
4ea6fbc8
TI		 2331 }
2332#endif
c0f1886d
TI		 2333
2334 probe_retry:
9479e75f 2335 if (bus->codec_mask && !(probe_only[dev] & 1)) {
a1e21c90 2336 err = azx_codec_configure(chip);
c0f1886d
TI		 2337 if (err) {
2338 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2339 ++hda->probe_retry < 60) {
2340 schedule_delayed_work(&hda->probe_work,
2341 msecs_to_jiffies(1000));
2342 return 0; /* keep things up */
2343 }
2344 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
a1e21c90 2345 goto out_free;
c0f1886d 2346 }
a1e21c90 2347 }
1da177e4 2348
a82d51ed 2349 err = snd_card_register(chip->card);
41dda0fd
WF		 2350 if (err < 0)
2351 goto out_free;
1da177e4 2352
37a3a98e
TI		 2353 setup_vga_switcheroo_runtime_pm(chip);
2354
cb53c626 2355 chip->running = 1;
65fcd41d 2356 azx_add_card_list(chip);
07f4f97d 2357
37a3a98e 2358 set_default_power_save(chip);
07f4f97d 2359
3ba21113
RS		 2360 if (azx_has_pm_runtime(chip)) {
2361 pm_runtime_use_autosuspend(&pci->dev);
9fc149c3 2362 pm_runtime_allow(&pci->dev);
30ff5957 2363 pm_runtime_put_autosuspend(&pci->dev);
3ba21113 2364 }
1da177e4 2365
41dda0fd 2366out_free:
2393e755 2367 if (err < 0) {
39173303
TI		 2368 pci_set_drvdata(pci, NULL);
2369 snd_card_free(chip->card);
2393e755
TI		 2370 return err;
2371 }
2372
2373 if (!hda->need_i915_power)
029d92c2 2374 display_power(chip, false);
9a34af4a 2375 complete_all(&hda->probe_wait);
305a0ade 2376 to_hda_bus(bus)->bus_probing = 0;
c0f1886d 2377 hda->probe_retry = 0;
2393e755 2378 return 0;
1da177e4
LT		 2379}
2380
e23e7a14 2381static void azx_remove(struct pci_dev *pci)
1da177e4 2382{
9121947d 2383 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2384 struct azx *chip;
2385 struct hda_intel *hda;
2386
2387 if (card) {
0b8c8219 2388 /* cancel the pending probing work */
991f86d7
TI		 2389 chip = card->private_data;
2390 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2391 /* FIXME: below is an ugly workaround.
2392 * Both device_release_driver() and driver_probe_device()
2393 * take *both* the device's and its parent's lock before
2394 * calling the remove() and probe() callbacks. The codec
2395 * probe takes the locks of both the codec itself and its
2396 * parent, i.e. the PCI controller dev. Meanwhile, when
2397 * the PCI controller is unbound, it takes its lock, too
2398 * ==> ouch, a deadlock!
2399 * As a workaround, we unlock temporarily here the controller
2400 * device during cancel_work_sync() call.
2401 */
2402 device_unlock(&pci->dev);
c0f1886d 2403 cancel_delayed_work_sync(&hda->probe_work);
ab949d51 2404 device_lock(&pci->dev);
b8dfc462 2405
69458e2c 2406 clear_bit(chip->dev_index, probed_devs);
e81478bb 2407 pci_set_drvdata(pci, NULL);
9121947d 2408 snd_card_free(card);
991f86d7 2409 }
1da177e4
LT		 2410}
2411
b2a0bafa
TI		 2412static void azx_shutdown(struct pci_dev *pci)
2413{
2414 struct snd_card *card = pci_get_drvdata(pci);
2415 struct azx *chip;
2416
2417 if (!card)
2418 return;
2419 chip = card->private_data;
2420 if (chip && chip->running)
6f445784 2421 __azx_shutdown_chip(chip, true);
b2a0bafa
TI		 2422}
2423
1da177e4 2424/* PCI IDs */
6f51f6cf 2425static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2426 /* CPT */
e6232c80 2427 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
cea310e8 2428 /* PBG */
e6232c80 2429 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
d2edeb7c 2430 /* Panther Point */
e6232c80 2431 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
8bc039a1 2432 /* Lynx Point */
e6232c80 2433 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
77f07800 2434 /* 9 Series */
e6232c80 2435 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
884b088f 2436 /* Wellsburg */
e6232c80
AS		 2437 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2438 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
5cf92c8b 2439 /* Lewisburg */
e6232c80
AS		 2440 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2441 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
144dad99 2442 /* Lynx Point-LP */
e6232c80 2443 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
144dad99 2444 /* Lynx Point-LP */
e6232c80 2445 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
4eeca499 2446 /* Wildcat Point-LP */
e6232c80
AS		 2447 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2448 /* Skylake (Sunrise Point) */
2449 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2450 /* Skylake-LP (Sunrise Point-LP) */
2451 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
35639a0e 2452 /* Kabylake */
e6232c80 2453 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
35639a0e 2454 /* Kabylake-LP */
e6232c80 2455 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
6858107e 2456 /* Kabylake-H */
e6232c80 2457 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
e79b0006 2458 /* Coffelake */
e6232c80 2459 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2357f6f0 2460 /* Cannonlake */
e6232c80 2461 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d4c2ccdb 2462 /* CometLake-LP */
e6232c80 2463 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d4c2ccdb 2464 /* CometLake-H */
e6232c80
AS		 2465 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2466 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
b73a5854 2467 /* CometLake-S */
e6232c80 2468 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
f84d3a1e 2469 /* CometLake-R */
e6232c80 2470 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
491f8331 2471 /* Icelake */
e6232c80 2472 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d50313a5 2473 /* Icelake-H */
e6232c80 2474 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4750c212 2475 /* Jasperlake */
e6232c80
AS		 2476 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2477 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4750c212 2478 /* Tigerlake */
e6232c80 2479 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d50313a5 2480 /* Tigerlake-H */
e6232c80 2481 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
69b08bdf 2482 /* DG1 */
e6232c80 2483 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d85ffff5 2484 /* DG2 */
e6232c80
AS		 2485 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2486 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2487 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d78359b2 2488 /* Alderlake-S */
e6232c80 2489 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
5e941fc0 2490 /* Alderlake-P */
e6232c80
AS		 2491 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2492 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2493 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4ad7935d 2494 /* Alderlake-M */
e6232c80 2495 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4d5a628d 2496 /* Alderlake-N */
e6232c80 2497 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
f94287b6 2498 /* Elkhart Lake */
e6232c80
AS		 2499 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2500 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
a531caa5 2501 /* Raptor Lake */
e6232c80
AS		 2502 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2503 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2504 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2505 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2506 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2507 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
714b2f02 2508 /* Lunarlake-P */
f20bee38 2509 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
3bef0681
KV		 2510 /* Arrow Lake-S */
2511 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
a31014eb
PLB		 2512 /* Arrow Lake */
2513 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
e6232c80
AS		 2514 /* Apollolake (Broxton-P) */
2515 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
44b46d73 2516 /* Gemini-Lake */
e6232c80 2517 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
e926f2c8 2518 /* Haswell */
e6232c80
AS		 2519 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2520 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2521 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
862d7618 2522 /* Broadwell */
e6232c80 2523 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },
99df18b3 2524 /* 5 Series/3400 */
e6232c80
AS		 2525 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2526 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
f748abcc 2527 /* Poulsbo */
e6232c80
AS		 2528 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2529 AZX_DCAPS_POSFIX_LPIB) },
f748abcc 2530 /* Oaktrail */
e6232c80 2531 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },
e44007e0 2532 /* BayTrail */
e6232c80 2533 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },
f31b2ffc 2534 /* Braswell */
e6232c80 2535 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },
b42b4afb 2536 /* ICH6 */
e6232c80 2537 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2538 /* ICH7 */
e6232c80 2539 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2540 /* ESB2 */
e6232c80 2541 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2542 /* ICH8 */
e6232c80 2543 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2544 /* ICH9 */
e6232c80 2545 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2546 /* ICH9 */
e6232c80 2547 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2548 /* ICH10 */
e6232c80 2549 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2550 /* ICH10 */
e6232c80 2551 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b6864535
TI		 2552 /* Generic Intel */
2553 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2554 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2555 .class_mask = 0xffffff,
103884a3 2556 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e 2557 /* ATI SB 450/600/700/800/900 */
e6232c80 2558 { PCI_VDEVICE(ATI, 0x437b),
9477c58e 2559 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
e6232c80 2560 { PCI_VDEVICE(ATI, 0x4383),
9477c58e
TI		 2561 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2562 /* AMD Hudson */
e6232c80 2563 { PCI_VDEVICE(AMD, 0x780d),
9477c58e 2564 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
c02f77d3 2565 /* AMD, X370 & co */
e6232c80 2566 { PCI_VDEVICE(AMD, 0x1457),
c02f77d3 2567 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
de768ce4 2568 /* AMD, X570 & co */
e6232c80 2569 { PCI_VDEVICE(AMD, 0x1487),
de768ce4 2570 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
3deef52c 2571 /* AMD Stoney */
e6232c80 2572 { PCI_VDEVICE(AMD, 0x157a),
3deef52c
KHF		 2573 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2574 AZX_DCAPS_PM_RUNTIME },
9ceace3c 2575 /* AMD Raven */
e6232c80 2576 { PCI_VDEVICE(AMD, 0x15e3),
d2c63b7d 2577 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
87218e9c 2578 /* ATI HDMI */
e6232c80 2579 { PCI_VDEVICE(ATI, 0x0002),
20c7842e
AD		 2580 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2581 AZX_DCAPS_PM_RUNTIME },
e6232c80 2582 { PCI_VDEVICE(ATI, 0x1308),
650474fb 2583 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2584 { PCI_VDEVICE(ATI, 0x157a),
5022813d 2585 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2586 { PCI_VDEVICE(ATI, 0x15b3),
d716fb03 2587 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2588 { PCI_VDEVICE(ATI, 0x793b),
9477c58e 2589 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2590 { PCI_VDEVICE(ATI, 0x7919),
9477c58e 2591 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2592 { PCI_VDEVICE(ATI, 0x960f),
9477c58e 2593 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2594 { PCI_VDEVICE(ATI, 0x970f),
9477c58e 2595 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2596 { PCI_VDEVICE(ATI, 0x9840),
650474fb 2597 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2598 { PCI_VDEVICE(ATI, 0xaa00),
9477c58e 2599 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2600 { PCI_VDEVICE(ATI, 0xaa08),
9477c58e 2601 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2602 { PCI_VDEVICE(ATI, 0xaa10),
9477c58e 2603 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2604 { PCI_VDEVICE(ATI, 0xaa18),
9477c58e 2605 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2606 { PCI_VDEVICE(ATI, 0xaa20),
9477c58e 2607 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2608 { PCI_VDEVICE(ATI, 0xaa28),
9477c58e 2609 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2610 { PCI_VDEVICE(ATI, 0xaa30),
9477c58e 2611 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2612 { PCI_VDEVICE(ATI, 0xaa38),
9477c58e 2613 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2614 { PCI_VDEVICE(ATI, 0xaa40),
9477c58e 2615 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2616 { PCI_VDEVICE(ATI, 0xaa48),
9477c58e 2617 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2618 { PCI_VDEVICE(ATI, 0xaa50),
bbaa0d66 2619 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2620 { PCI_VDEVICE(ATI, 0xaa58),
bbaa0d66 2621 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2622 { PCI_VDEVICE(ATI, 0xaa60),
bbaa0d66 2623 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2624 { PCI_VDEVICE(ATI, 0xaa68),
bbaa0d66 2625 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2626 { PCI_VDEVICE(ATI, 0xaa80),
bbaa0d66 2627 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2628 { PCI_VDEVICE(ATI, 0xaa88),
bbaa0d66 2629 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2630 { PCI_VDEVICE(ATI, 0xaa90),
bbaa0d66 2631 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2632 { PCI_VDEVICE(ATI, 0xaa98),
bbaa0d66 2633 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2634 { PCI_VDEVICE(ATI, 0x9902),
37e661ee 2635 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2636 { PCI_VDEVICE(ATI, 0xaaa0),
37e661ee 2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2638 { PCI_VDEVICE(ATI, 0xaaa8),
37e661ee 2639 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2640 { PCI_VDEVICE(ATI, 0xaab0),
37e661ee 2641 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2642 { PCI_VDEVICE(ATI, 0xaac0),
20c7842e
AD		 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2644 AZX_DCAPS_PM_RUNTIME },
e6232c80 2645 { PCI_VDEVICE(ATI, 0xaac8),
20c7842e
AD		 2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2647 AZX_DCAPS_PM_RUNTIME },
e6232c80 2648 { PCI_VDEVICE(ATI, 0xaad8),
73b1422b
AD		 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2650 AZX_DCAPS_PM_RUNTIME },
e6232c80 2651 { PCI_VDEVICE(ATI, 0xaae0),
73b1422b
AD		 2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2653 AZX_DCAPS_PM_RUNTIME },
e6232c80 2654 { PCI_VDEVICE(ATI, 0xaae8),
73b1422b
AD		 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2656 AZX_DCAPS_PM_RUNTIME },
e6232c80 2657 { PCI_VDEVICE(ATI, 0xaaf0),
73b1422b
AD		 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2659 AZX_DCAPS_PM_RUNTIME },
e6232c80 2660 { PCI_VDEVICE(ATI, 0xaaf8),
73b1422b
AD		 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2662 AZX_DCAPS_PM_RUNTIME },
e6232c80 2663 { PCI_VDEVICE(ATI, 0xab00),
73b1422b
AD		 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2665 AZX_DCAPS_PM_RUNTIME },
e6232c80 2666 { PCI_VDEVICE(ATI, 0xab08),
73b1422b
AD		 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2668 AZX_DCAPS_PM_RUNTIME },
e6232c80 2669 { PCI_VDEVICE(ATI, 0xab10),
73b1422b
AD		 2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2671 AZX_DCAPS_PM_RUNTIME },
e6232c80 2672 { PCI_VDEVICE(ATI, 0xab18),
73b1422b
AD		 2673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2674 AZX_DCAPS_PM_RUNTIME },
e6232c80 2675 { PCI_VDEVICE(ATI, 0xab20),
73b1422b 2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
27a7c670 2677 AZX_DCAPS_PM_RUNTIME },
e6232c80 2678 { PCI_VDEVICE(ATI, 0xab28),
27a7c670 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
fdcc4c22 2680 AZX_DCAPS_PM_RUNTIME },
e6232c80 2681 { PCI_VDEVICE(ATI, 0xab30),
fdcc4c22 2682 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
73b1422b 2683 AZX_DCAPS_PM_RUNTIME },
e6232c80 2684 { PCI_VDEVICE(ATI, 0xab38),
73b1422b
AD		 2685 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2686 AZX_DCAPS_PM_RUNTIME },
c51e4310 2687 /* GLENFLY */
2688 { PCI_DEVICE(0x6766, PCI_ANY_ID),
2689 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2690 .class_mask = 0xffffff,
2691 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2692 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
87218e9c 2693 /* VIA VT8251/VT8237A */
e6232c80 2694 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8 2695 /* VIA GFX VT7122/VX900 */
e6232c80 2696 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
754fdff8 2697 /* VIA GFX VT6122/VX11 */
e6232c80 2698 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c 2699 /* SIS966 */
e6232c80 2700 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
87218e9c 2701 /* ULI M5461 */
e6232c80 2702 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },
87218e9c 2703 /* NVIDIA MCP */
0c2fd1bf
TI		 2704 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2705 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2706 .class_mask = 0xffffff,
9477c58e 2707 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2708 /* Teradici */
9477c58e
TI		 2709 { PCI_DEVICE(0x6549, 0x1200),
2710 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2711 { PCI_DEVICE(0x6549, 0x2200),
2712 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2713 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf 2714 /* CTHDA chips */
e6232c80 2715 { PCI_VDEVICE(CREATIVE, 0x0010),
f2a8ecaf 2716 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
e6232c80 2717 { PCI_VDEVICE(CREATIVE, 0x0012),
f2a8ecaf 2718 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2719#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2720 /* the following entry conflicts with snd-ctxfi driver,
2721 * as ctxfi driver mutates from HD-audio to native mode with
2722 * a special command sequence.
2723 */
4e01f54b
TI		 2724 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2725 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2726 .class_mask = 0xffffff,
9477c58e 2727 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2728 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2729#else
2730 /* this entry seems still valid -- i.e. without emu20kx chip */
e6232c80 2731 { PCI_VDEVICE(CREATIVE, 0x0009),
9477c58e 2732 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2733 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2734#endif
c563f473 2735 /* CM8888 */
e6232c80 2736 { PCI_VDEVICE(CMEDIA, 0x5011),
c563f473 2737 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2738 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11 2739 /* Vortex86MX */
e6232c80 2740 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5 2741 /* VMware HDAudio */
e6232c80 2742 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2743 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2744 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2745 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2746 .class_mask = 0xffffff,
9477c58e 2747 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2748 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2749 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2750 .class_mask = 0xffffff,
9477c58e 2751 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
b6fcab14 2752 /* Zhaoxin */
e6232c80 2753 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
28bd137a 2754 /* Loongson HDAudio*/
e6232c80 2755 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
28bd137a 2756 .driver_data = AZX_DRIVER_LOONGSON },
e6232c80 2757 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
28bd137a 2758 .driver_data = AZX_DRIVER_LOONGSON },
1da177e4
LT		 2759 { 0, }
2760};
2761MODULE_DEVICE_TABLE(pci, azx_ids);
2762
2763/* pci_driver definition */
e9f66d9b 2764static struct pci_driver azx_driver = {
3733e424 2765 .name = KBUILD_MODNAME,
1da177e4
LT		 2766 .id_table = azx_ids,
2767 .probe = azx_probe,
e23e7a14 2768 .remove = azx_remove,
b2a0bafa 2769 .shutdown = azx_shutdown,
68cb2b55
TI		 2770 .driver = {
2771 .pm = AZX_PM_OPS,
2772 },
1da177e4
LT		 2773};
2774
e9f66d9b 2775module_pci_driver(azx_driver);
Linux 6.x block layer and io_uring tree(s)