projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda - restore BCLK M/N value as per CDCLK for HSW/BDW display HDA controller
[linux-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
05e84878 65#include "hda_controller.h"
2538a4f5 66#include "hda_priv.h"
e4d9e513 67#include "hda_i915.h"
1da177e4
LT		 68
69
5aba4f8e
TI		 70static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 72static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 73static char *model[SNDRV_CARDS];
1dac6695 74static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 75static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 76static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 77static int probe_only[SNDRV_CARDS];
26a6cb6c 78static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 79static bool single_cmd;
71623855 80static int enable_msi = -1;
4ea6fbc8
TI		 81#ifdef CONFIG_SND_HDA_PATCH_LOADER
82static char *patch[SNDRV_CARDS];
83#endif
2dca0bba 84#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 85static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 86 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87#endif
1da177e4 88
5aba4f8e 89module_param_array(index, int, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 91module_param_array(id, charp, NULL, 0444);
1da177e4 92MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 93module_param_array(enable, bool, NULL, 0444);
94MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
95module_param_array(model, charp, NULL, 0444);
1da177e4 96MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 97module_param_array(position_fix, int, NULL, 0444);
4cb36310 98MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 99 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 100module_param_array(bdl_pos_adj, int, NULL, 0644);
101MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 102module_param_array(probe_mask, int, NULL, 0444);
606ad75f 103MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 104module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 105MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 106module_param_array(jackpoll_ms, int, NULL, 0444);
107MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 108module_param(single_cmd, bool, 0444);
d01ce99f
TI		 109MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
110 "(for debugging only).");
ac9ef6cf 111module_param(enable_msi, bint, 0444);
134a11f0 112MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 113#ifdef CONFIG_SND_HDA_PATCH_LOADER
114module_param_array(patch, charp, NULL, 0444);
115MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
116#endif
2dca0bba 117#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 118module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 119MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 120 "(0=off, 1=on) (default=1).");
2dca0bba 121#endif
606ad75f 122
83012a7c 123#ifdef CONFIG_PM
65fcd41d
TI		 124static int param_set_xint(const char *val, const struct kernel_param *kp);
125static struct kernel_param_ops param_ops_xint = {
126 .set = param_set_xint,
127 .get = param_get_int,
128};
129#define param_check_xint param_check_int
130
fee2fba3 131static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 132static int *power_save_addr = &power_save;
65fcd41d 133module_param(power_save, xint, 0644);
fee2fba3
TI		 134MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
135 "(in second, 0 = disable).");
1da177e4 136
dee1b66c
TI		 137/* reset the HD-audio controller in power save mode.
138 * this may give more power-saving, but will take longer time to
139 * wake up.
140 */
8fc24426
TI		 141static bool power_save_controller = 1;
142module_param(power_save_controller, bool, 0644);
dee1b66c 143MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 144#else
145static int *power_save_addr;
83012a7c 146#endif /* CONFIG_PM */
dee1b66c 147
7bfe059e
TI		 148static int align_buffer_size = -1;
149module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 150MODULE_PARM_DESC(align_buffer_size,
151 "Force buffer and period sizes to be multiple of 128 bytes.");
152
27fe48d9
TI		 153#ifdef CONFIG_X86
154static bool hda_snoop = true;
155module_param_named(snoop, hda_snoop, bool, 0444);
156MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 157#else
158#define hda_snoop true
27fe48d9
TI		 159#endif
160
161
1da177e4
LT		 162MODULE_LICENSE("GPL");
163MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
164 "{Intel, ICH6M},"
2f1b3818 165 "{Intel, ICH7},"
f5d40b30 166 "{Intel, ESB2},"
d2981393 167 "{Intel, ICH8},"
f9cc8a8b 168 "{Intel, ICH9},"
c34f5a04 169 "{Intel, ICH10},"
b29c2360 170 "{Intel, PCH},"
d2f2fcd2 171 "{Intel, CPT},"
d2edeb7c 172 "{Intel, PPT},"
8bc039a1 173 "{Intel, LPT},"
144dad99 174 "{Intel, LPT_LP},"
4eeca499 175 "{Intel, WPT_LP},"
e926f2c8 176 "{Intel, HPT},"
cea310e8 177 "{Intel, PBG},"
4979bca9 178 "{Intel, SCH},"
fc20a562 179 "{ATI, SB450},"
89be83f8 180 "{ATI, SB600},"
778b6e1b 181 "{ATI, RS600},"
5b15c95f 182 "{ATI, RS690},"
e6db1119
WL		 183 "{ATI, RS780},"
184 "{ATI, R600},"
2797f724
HRK		 185 "{ATI, RV630},"
186 "{ATI, RV610},"
27da1834
WL		 187 "{ATI, RV670},"
188 "{ATI, RV635},"
189 "{ATI, RV620},"
190 "{ATI, RV770},"
fc20a562 191 "{VIA, VT8251},"
47672310 192 "{VIA, VT8237A},"
07e4ca50
TI		 193 "{SiS, SIS966},"
194 "{ULI, M5461}}");
1da177e4
LT		 195MODULE_DESCRIPTION("Intel HDA driver");
196
a82d51ed 197#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 198#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 199#define SUPPORT_VGA_SWITCHEROO
200#endif
201#endif
202
203
1da177e4 204/*
1da177e4 205 */
1da177e4 206
07e4ca50
TI		 207/* driver types */
208enum {
209 AZX_DRIVER_ICH,
32679f95 210 AZX_DRIVER_PCH,
4979bca9 211 AZX_DRIVER_SCH,
fab1285a 212 AZX_DRIVER_HDMI,
07e4ca50 213 AZX_DRIVER_ATI,
778b6e1b 214 AZX_DRIVER_ATIHDMI,
1815b34a 215 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 216 AZX_DRIVER_VIA,
217 AZX_DRIVER_SIS,
218 AZX_DRIVER_ULI,
da3fca21 219 AZX_DRIVER_NVIDIA,
f269002e 220 AZX_DRIVER_TERA,
14d34f16 221 AZX_DRIVER_CTX,
5ae763b1 222 AZX_DRIVER_CTHDA,
c4da29ca 223 AZX_DRIVER_GENERIC,
2f5983f2 224 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 225};
226
2ea3c6a2 227/* quirks for Intel PCH */
d7dab4db 228#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 229 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 230 AZX_DCAPS_COUNT_LPIB_DELAY)
231
232#define AZX_DCAPS_INTEL_PCH \
233 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 234
33499a15
TI		 235#define AZX_DCAPS_INTEL_HASWELL \
236 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
237 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
238 AZX_DCAPS_I915_POWERWELL)
239
54a0405d
LY		 240/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
241#define AZX_DCAPS_INTEL_BROADWELL \
242 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
243 AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_PM_RUNTIME | \
244 AZX_DCAPS_I915_POWERWELL)
245
9477c58e
TI		 246/* quirks for ATI SB / AMD Hudson */
247#define AZX_DCAPS_PRESET_ATI_SB \
248 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
249 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
250
251/* quirks for ATI/AMD HDMI */
252#define AZX_DCAPS_PRESET_ATI_HDMI \
253 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
254
255/* quirks for Nvidia */
256#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 257 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
6ba736dd
TI		 258 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\
259 AZX_DCAPS_CORBRP_SELF_CLEAR)
9477c58e 260
5ae763b1
TI		 261#define AZX_DCAPS_PRESET_CTHDA \
262 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
263
a82d51ed
TI		 264/*
265 * VGA-switcher support
266 */
267#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 268#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
269#else
270#define use_vga_switcheroo(chip) 0
271#endif
272
48c8b0eb 273static char *driver_short_names[] = {
07e4ca50 274 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 275 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 276 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 277 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 278 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 279 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 280 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 281 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
282 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 283 [AZX_DRIVER_ULI] = "HDA ULI M5461",
284 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 285 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 286 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 287 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 288 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 289};
290
a07187c9
ML		 291struct hda_intel {
292 struct azx chip;
a07187c9
ML		 293};
294
295
27fe48d9 296#ifdef CONFIG_X86
9ddf1aeb 297static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 298{
9ddf1aeb
TI		 299 int pages;
300
27fe48d9
TI		 301 if (azx_snoop(chip))
302 return;
9ddf1aeb
TI		 303 if (!dmab || !dmab->area || !dmab->bytes)
304 return;
305
306#ifdef CONFIG_SND_DMA_SGBUF
307 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
308 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 309 if (on)
9ddf1aeb 310 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 311 else
9ddf1aeb
TI		 312 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
313 return;
27fe48d9 314 }
9ddf1aeb
TI		 315#endif
316
317 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
318 if (on)
319 set_memory_wc((unsigned long)dmab->area, pages);
320 else
321 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 322}
323
324static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
325 bool on)
326{
9ddf1aeb 327 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 328}
329static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 330 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 331{
332 if (azx_dev->wc_marked != on) {
9ddf1aeb 333 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 334 azx_dev->wc_marked = on;
335 }
336}
337#else
338/* NOP for other archs */
339static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
340 bool on)
341{
342}
343static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 344 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 345{
346}
347#endif
348
68e7fffc 349static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 350
cb53c626
TI		 351/*
352 * initialize the PCI registers
353 */
354/* update bits in a PCI register byte */
355static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
356 unsigned char mask, unsigned char val)
357{
358 unsigned char data;
359
360 pci_read_config_byte(pci, reg, &data);
361 data &= ~mask;
362 data |= (val & mask);
363 pci_write_config_byte(pci, reg, data);
364}
365
366static void azx_init_pci(struct azx *chip)
367{
368 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
369 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
370 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 371 * codecs.
372 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 373 */
46f2cc80 374 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 375 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
a09e89f6 376 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 377 }
cb53c626 378
9477c58e
TI		 379 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
380 * we need to enable snoop.
381 */
382 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
4e76a883
TI		 383 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
384 azx_snoop(chip));
cb53c626 385 update_pci_byte(chip->pci,
27fe48d9
TI		 386 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
387 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 388 }
389
390 /* For NVIDIA HDA, enable snoop */
391 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
4e76a883
TI		 392 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
393 azx_snoop(chip));
cb53c626
TI		 394 update_pci_byte(chip->pci,
395 NVIDIA_HDA_TRANSREG_ADDR,
396 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 397 update_pci_byte(chip->pci,
398 NVIDIA_HDA_ISTRM_COH,
399 0x01, NVIDIA_HDA_ENABLE_COHBIT);
400 update_pci_byte(chip->pci,
401 NVIDIA_HDA_OSTRM_COH,
402 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 403 }
404
405 /* Enable SCH/PCH snoop if needed */
406 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 407 unsigned short snoop;
90a5ad52 408 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 409 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
410 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
411 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
412 if (!azx_snoop(chip))
413 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
414 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 415 pci_read_config_word(chip->pci,
416 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 417 }
4e76a883
TI		 418 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
419 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
420 "Disabled" : "Enabled");
da3fca21 421 }
1da177e4
LT		 422}
423
9ad593f6
TI		 424static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
425
7ca954a8
DR		 426/* called from IRQ */
427static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
428{
429 int ok;
430
431 ok = azx_position_ok(chip, azx_dev);
432 if (ok == 1) {
433 azx_dev->irq_pending = 0;
434 return ok;
435 } else if (ok == 0 && chip->bus && chip->bus->workq) {
436 /* bogus IRQ, process it later */
437 azx_dev->irq_pending = 1;
438 queue_work(chip->bus->workq, &chip->irq_pending_work);
439 }
440 return 0;
441}
442
9ad593f6
TI		 443/*
444 * Check whether the current DMA position is acceptable for updating
445 * periods. Returns non-zero if it's OK.
446 *
447 * Many HD-audio controllers appear pretty inaccurate about
448 * the update-IRQ timing. The IRQ is issued before actually the
449 * data is processed. So, we need to process it afterwords in a
450 * workqueue.
451 */
452static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
453{
e5463720 454 u32 wallclk;
9ad593f6
TI		 455 unsigned int pos;
456
f48f606d
JK		 457 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
458 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 459 return -1; /* bogus (too early) interrupt */
fa00e046 460
798cb7e8 461 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 462
d6d8bf54
TI		 463 if (WARN_ONCE(!azx_dev->period_bytes,
464 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 465 return -1; /* this shouldn't happen! */
edb39935 466 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 467 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
468 /* NG - it's below the first next period boundary */
9cdc0115 469 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 470 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 471 return 1; /* OK, it's fine */
472}
473
474/*
475 * The work for pending PCM period updates.
476 */
477static void azx_irq_pending_work(struct work_struct *work)
478{
479 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 480 int i, pending, ok;
9ad593f6 481
a6a950a8 482 if (!chip->irq_pending_warned) {
4e76a883
TI		 483 dev_info(chip->card->dev,
484 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
485 chip->card->number);
a6a950a8
TI		 486 chip->irq_pending_warned = 1;
487 }
488
9ad593f6
TI		 489 for (;;) {
490 pending = 0;
491 spin_lock_irq(&chip->reg_lock);
492 for (i = 0; i < chip->num_streams; i++) {
493 struct azx_dev *azx_dev = &chip->azx_dev[i];
494 if (!azx_dev->irq_pending ||
495 !azx_dev->substream ||
496 !azx_dev->running)
497 continue;
e5463720
JK		 498 ok = azx_position_ok(chip, azx_dev);
499 if (ok > 0) {
9ad593f6
TI		 500 azx_dev->irq_pending = 0;
501 spin_unlock(&chip->reg_lock);
502 snd_pcm_period_elapsed(azx_dev->substream);
503 spin_lock(&chip->reg_lock);
e5463720
JK		 504 } else if (ok < 0) {
505 pending = 0; /* too early */
9ad593f6
TI		 506 } else
507 pending++;
508 }
509 spin_unlock_irq(&chip->reg_lock);
510 if (!pending)
511 return;
08af495f 512 msleep(1);
9ad593f6
TI		 513 }
514}
515
516/* clear irq_pending flags and assure no on-going workq */
517static void azx_clear_irq_pending(struct azx *chip)
518{
519 int i;
520
521 spin_lock_irq(&chip->reg_lock);
522 for (i = 0; i < chip->num_streams; i++)
523 chip->azx_dev[i].irq_pending = 0;
524 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 525}
526
68e7fffc
TI		 527static int azx_acquire_irq(struct azx *chip, int do_disconnect)
528{
437a5a46
TI		 529 if (request_irq(chip->pci->irq, azx_interrupt,
530 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 531 KBUILD_MODNAME, chip)) {
4e76a883
TI		 532 dev_err(chip->card->dev,
533 "unable to grab IRQ %d, disabling device\n",
534 chip->pci->irq);
68e7fffc
TI		 535 if (do_disconnect)
536 snd_card_disconnect(chip->card);
537 return -1;
538 }
539 chip->irq = chip->pci->irq;
69e13418 540 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 541 return 0;
542}
543
83012a7c 544#ifdef CONFIG_PM
65fcd41d
TI		 545static DEFINE_MUTEX(card_list_lock);
546static LIST_HEAD(card_list);
547
548static void azx_add_card_list(struct azx *chip)
549{
550 mutex_lock(&card_list_lock);
551 list_add(&chip->list, &card_list);
552 mutex_unlock(&card_list_lock);
553}
554
555static void azx_del_card_list(struct azx *chip)
556{
557 mutex_lock(&card_list_lock);
558 list_del_init(&chip->list);
559 mutex_unlock(&card_list_lock);
560}
561
562/* trigger power-save check at writing parameter */
563static int param_set_xint(const char *val, const struct kernel_param *kp)
564{
565 struct azx *chip;
566 struct hda_codec *c;
567 int prev = power_save;
568 int ret = param_set_int(val, kp);
569
570 if (ret || prev == power_save)
571 return ret;
572
573 mutex_lock(&card_list_lock);
574 list_for_each_entry(chip, &card_list, list) {
575 if (!chip->bus || chip->disabled)
576 continue;
577 list_for_each_entry(c, &chip->bus->codec_list, list)
578 snd_hda_power_sync(c);
579 }
580 mutex_unlock(&card_list_lock);
581 return 0;
582}
583#else
584#define azx_add_card_list(chip) /* NOP */
585#define azx_del_card_list(chip) /* NOP */
83012a7c 586#endif /* CONFIG_PM */
5c0b9bec 587
7ccbde57 588#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 589/*
590 * power management
591 */
68cb2b55 592static int azx_suspend(struct device *dev)
1da177e4 593{
68cb2b55
TI		 594 struct pci_dev *pci = to_pci_dev(dev);
595 struct snd_card *card = dev_get_drvdata(dev);
421a1252 596 struct azx *chip = card->private_data;
01b65bfb 597 struct azx_pcm *p;
1da177e4 598
c5c21523
TI		 599 if (chip->disabled)
600 return 0;
601
421a1252 602 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 603 azx_clear_irq_pending(chip);
01b65bfb
TI		 604 list_for_each_entry(p, &chip->pcm_list, list)
605 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 606 if (chip->initialized)
8dd78330 607 snd_hda_suspend(chip->bus);
cb53c626 608 azx_stop_chip(chip);
7295b264 609 azx_enter_link_reset(chip);
30b35399 610 if (chip->irq >= 0) {
43001c95 611 free_irq(chip->irq, chip);
30b35399
TI		 612 chip->irq = -1;
613 }
a07187c9 614
68e7fffc 615 if (chip->msi)
43001c95 616 pci_disable_msi(chip->pci);
421a1252
TI		 617 pci_disable_device(pci);
618 pci_save_state(pci);
68cb2b55 619 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 620 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
621 hda_display_power(false);
1da177e4
LT		 622 return 0;
623}
624
68cb2b55 625static int azx_resume(struct device *dev)
1da177e4 626{
68cb2b55
TI		 627 struct pci_dev *pci = to_pci_dev(dev);
628 struct snd_card *card = dev_get_drvdata(dev);
421a1252 629 struct azx *chip = card->private_data;
1da177e4 630
c5c21523
TI		 631 if (chip->disabled)
632 return 0;
633
a07187c9 634 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 635 hda_display_power(true);
e4d9e513 636 haswell_set_bclk(chip);
a07187c9 637 }
d14a7e0b
TI		 638 pci_set_power_state(pci, PCI_D0);
639 pci_restore_state(pci);
30b35399 640 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 641 dev_err(chip->card->dev,
642 "pci_enable_device failed, disabling device\n");
30b35399
TI		 643 snd_card_disconnect(card);
644 return -EIO;
645 }
646 pci_set_master(pci);
68e7fffc
TI		 647 if (chip->msi)
648 if (pci_enable_msi(pci) < 0)
649 chip->msi = 0;
650 if (azx_acquire_irq(chip, 1) < 0)
30b35399 651 return -EIO;
cb53c626 652 azx_init_pci(chip);
d804ad92 653
17c3ad03 654 azx_init_chip(chip, true);
d804ad92 655
1da177e4 656 snd_hda_resume(chip->bus);
421a1252 657 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 658 return 0;
659}
b8dfc462
ML		 660#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
661
662#ifdef CONFIG_PM_RUNTIME
663static int azx_runtime_suspend(struct device *dev)
664{
665 struct snd_card *card = dev_get_drvdata(dev);
666 struct azx *chip = card->private_data;
667
246efa4a
DA		 668 if (chip->disabled)
669 return 0;
670
671 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
672 return 0;
673
7d4f606c
WX		 674 /* enable controller wake up event */
675 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
676 STATESTS_INT_MASK);
677
b8dfc462 678 azx_stop_chip(chip);
873ce8ad 679 azx_enter_link_reset(chip);
b8dfc462 680 azx_clear_irq_pending(chip);
e4d9e513 681 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
99a2008d 682 hda_display_power(false);
e4d9e513 683
b8dfc462
ML		 684 return 0;
685}
686
687static int azx_runtime_resume(struct device *dev)
688{
689 struct snd_card *card = dev_get_drvdata(dev);
690 struct azx *chip = card->private_data;
7d4f606c
WX		 691 struct hda_bus *bus;
692 struct hda_codec *codec;
693 int status;
b8dfc462 694
246efa4a
DA		 695 if (chip->disabled)
696 return 0;
697
698 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
699 return 0;
700
a07187c9 701 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 702 hda_display_power(true);
e4d9e513 703 haswell_set_bclk(chip);
a07187c9 704 }
7d4f606c
WX		 705
706 /* Read STATESTS before controller reset */
707 status = azx_readw(chip, STATESTS);
708
b8dfc462 709 azx_init_pci(chip);
17c3ad03 710 azx_init_chip(chip, true);
7d4f606c
WX		 711
712 bus = chip->bus;
713 if (status && bus) {
714 list_for_each_entry(codec, &bus->codec_list, list)
715 if (status & (1 << codec->addr))
716 queue_delayed_work(codec->bus->workq,
717 &codec->jackpoll_work, codec->jackpoll_interval);
718 }
719
720 /* disable controller Wake Up event*/
721 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
722 ~STATESTS_INT_MASK);
723
b8dfc462
ML		 724 return 0;
725}
6eb827d2
TI		 726
727static int azx_runtime_idle(struct device *dev)
728{
729 struct snd_card *card = dev_get_drvdata(dev);
730 struct azx *chip = card->private_data;
731
246efa4a
DA		 732 if (chip->disabled)
733 return 0;
734
6eb827d2
TI		 735 if (!power_save_controller ||
736 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
737 return -EBUSY;
738
739 return 0;
740}
741
b8dfc462
ML		 742#endif /* CONFIG_PM_RUNTIME */
743
744#ifdef CONFIG_PM
745static const struct dev_pm_ops azx_pm = {
746 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 747 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 748};
749
68cb2b55
TI		 750#define AZX_PM_OPS &azx_pm
751#else
68cb2b55 752#define AZX_PM_OPS NULL
b8dfc462 753#endif /* CONFIG_PM */
1da177e4
LT		 754
755
0cbf0098
TI		 756/*
757 * reboot notifier for hang-up problem at power-down
758 */
759static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
760{
761 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 762 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 763 azx_stop_chip(chip);
764 return NOTIFY_OK;
765}
766
767static void azx_notifier_register(struct azx *chip)
768{
769 chip->reboot_notifier.notifier_call = azx_halt;
770 register_reboot_notifier(&chip->reboot_notifier);
771}
772
773static void azx_notifier_unregister(struct azx *chip)
774{
775 if (chip->reboot_notifier.notifier_call)
776 unregister_reboot_notifier(&chip->reboot_notifier);
777}
778
48c8b0eb 779static int azx_probe_continue(struct azx *chip);
a82d51ed 780
8393ec4a 781#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 782static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 783
a82d51ed
TI		 784static void azx_vs_set_state(struct pci_dev *pci,
785 enum vga_switcheroo_state state)
786{
787 struct snd_card *card = pci_get_drvdata(pci);
788 struct azx *chip = card->private_data;
789 bool disabled;
790
f4c482a4 791 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 792 if (chip->init_failed)
793 return;
794
795 disabled = (state == VGA_SWITCHEROO_OFF);
796 if (chip->disabled == disabled)
797 return;
798
799 if (!chip->bus) {
800 chip->disabled = disabled;
801 if (!disabled) {
4e76a883
TI		 802 dev_info(chip->card->dev,
803 "Start delayed initialization\n");
5c90680e 804 if (azx_probe_continue(chip) < 0) {
4e76a883 805 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 806 chip->init_failed = true;
807 }
808 }
809 } else {
4e76a883
TI		 810 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
811 disabled ? "Disabling" : "Enabling");
a82d51ed 812 if (disabled) {
8928756d
DR		 813 pm_runtime_put_sync_suspend(card->dev);
814 azx_suspend(card->dev);
246efa4a
DA		 815 /* when we get suspended by vga switcheroo we end up in D3cold,
816 * however we have no ACPI handle, so pci/acpi can't put us there,
817 * put ourselves there */
818 pci->current_state = PCI_D3cold;
a82d51ed 819 chip->disabled = true;
128960a9 820 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 821 dev_warn(chip->card->dev,
822 "Cannot lock devices!\n");
a82d51ed
TI		 823 } else {
824 snd_hda_unlock_devices(chip->bus);
8928756d 825 pm_runtime_get_noresume(card->dev);
a82d51ed 826 chip->disabled = false;
8928756d 827 azx_resume(card->dev);
a82d51ed
TI		 828 }
829 }
830}
831
832static bool azx_vs_can_switch(struct pci_dev *pci)
833{
834 struct snd_card *card = pci_get_drvdata(pci);
835 struct azx *chip = card->private_data;
836
f4c482a4 837 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 838 if (chip->init_failed)
839 return false;
840 if (chip->disabled || !chip->bus)
841 return true;
842 if (snd_hda_lock_devices(chip->bus))
843 return false;
844 snd_hda_unlock_devices(chip->bus);
845 return true;
846}
847
e23e7a14 848static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 849{
850 struct pci_dev *p = get_bound_vga(chip->pci);
851 if (p) {
4e76a883
TI		 852 dev_info(chip->card->dev,
853 "Handle VGA-switcheroo audio client\n");
a82d51ed
TI		 854 chip->use_vga_switcheroo = 1;
855 pci_dev_put(p);
856 }
857}
858
859static const struct vga_switcheroo_client_ops azx_vs_ops = {
860 .set_gpu_state = azx_vs_set_state,
861 .can_switch = azx_vs_can_switch,
862};
863
e23e7a14 864static int register_vga_switcheroo(struct azx *chip)
a82d51ed 865{
128960a9
TI		 866 int err;
867
a82d51ed
TI		 868 if (!chip->use_vga_switcheroo)
869 return 0;
870 /* FIXME: currently only handling DIS controller
871 * is there any machine with two switchable HDMI audio controllers?
872 */
128960a9 873 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 874 VGA_SWITCHEROO_DIS,
875 chip->bus != NULL);
128960a9
TI		 876 if (err < 0)
877 return err;
878 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 879
880 /* register as an optimus hdmi audio power domain */
8928756d
DR		 881 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
882 &chip->hdmi_pm_domain);
128960a9 883 return 0;
a82d51ed
TI		 884}
885#else
886#define init_vga_switcheroo(chip) /* NOP */
887#define register_vga_switcheroo(chip) 0
8393ec4a 888#define check_hdmi_disabled(pci) false
a82d51ed
TI		 889#endif /* SUPPORT_VGA_SWITCHER */
890
1da177e4
LT		 891/*
892 * destructor
893 */
a98f90fd 894static int azx_free(struct azx *chip)
1da177e4 895{
c67e2228 896 struct pci_dev *pci = chip->pci;
a07187c9
ML		 897 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
898
4ce107b9
TI		 899 int i;
900
c67e2228
WX		 901 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
902 && chip->running)
903 pm_runtime_get_noresume(&pci->dev);
904
65fcd41d
TI		 905 azx_del_card_list(chip);
906
0cbf0098
TI		 907 azx_notifier_unregister(chip);
908
f4c482a4 909 chip->init_failed = 1; /* to be sure */
44728e97 910 complete_all(&chip->probe_wait);
f4c482a4 911
a82d51ed
TI		 912 if (use_vga_switcheroo(chip)) {
913 if (chip->disabled && chip->bus)
914 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 915 if (chip->vga_switcheroo_registered)
916 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 917 }
918
ce43fbae 919 if (chip->initialized) {
9ad593f6 920 azx_clear_irq_pending(chip);
07e4ca50 921 for (i = 0; i < chip->num_streams; i++)
1da177e4 922 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 923 azx_stop_chip(chip);
1da177e4
LT		 924 }
925
f000fd80 926 if (chip->irq >= 0)
1da177e4 927 free_irq(chip->irq, (void*)chip);
68e7fffc 928 if (chip->msi)
30b35399 929 pci_disable_msi(chip->pci);
f079c25a
TI		 930 if (chip->remap_addr)
931 iounmap(chip->remap_addr);
1da177e4 932
67908994 933 azx_free_stream_pages(chip);
a82d51ed
TI		 934 if (chip->region_requested)
935 pci_release_regions(chip->pci);
1da177e4 936 pci_disable_device(chip->pci);
07e4ca50 937 kfree(chip->azx_dev);
4918cdab
TI		 938#ifdef CONFIG_SND_HDA_PATCH_LOADER
939 if (chip->fw)
940 release_firmware(chip->fw);
941#endif
99a2008d
WX		 942 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
943 hda_display_power(false);
944 hda_i915_exit();
945 }
a07187c9 946 kfree(hda);
1da177e4
LT		 947
948 return 0;
949}
950
a98f90fd 951static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 952{
953 return azx_free(device->device_data);
954}
955
8393ec4a 956#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 957/*
958 * Check of disabled HDMI controller by vga-switcheroo
959 */
e23e7a14 960static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 961{
962 struct pci_dev *p;
963
964 /* check only discrete GPU */
965 switch (pci->vendor) {
966 case PCI_VENDOR_ID_ATI:
967 case PCI_VENDOR_ID_AMD:
968 case PCI_VENDOR_ID_NVIDIA:
969 if (pci->devfn == 1) {
970 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
971 pci->bus->number, 0);
972 if (p) {
973 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
974 return p;
975 pci_dev_put(p);
976 }
977 }
978 break;
979 }
980 return NULL;
981}
982
e23e7a14 983static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 984{
985 bool vga_inactive = false;
986 struct pci_dev *p = get_bound_vga(pci);
987
988 if (p) {
12b78a7f 989 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 990 vga_inactive = true;
991 pci_dev_put(p);
992 }
993 return vga_inactive;
994}
8393ec4a 995#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 996
3372a153
TI		 997/*
998 * white/black-listing for position_fix
999 */
e23e7a14 1000static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1001 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1002 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1003 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1004 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1005 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1006 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1007 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1008 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1009 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1010 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1011 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1012 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1013 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1014 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1015 {}
1016};
1017
e23e7a14 1018static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1019{
1020 const struct snd_pci_quirk *q;
1021
c673ba1c 1022 switch (fix) {
1dac6695 1023 case POS_FIX_AUTO:
c673ba1c
TI		 1024 case POS_FIX_LPIB:
1025 case POS_FIX_POSBUF:
4cb36310 1026 case POS_FIX_VIACOMBO:
a6f2fd55 1027 case POS_FIX_COMBO:
c673ba1c
TI		 1028 return fix;
1029 }
1030
c673ba1c
TI		 1031 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1032 if (q) {
4e76a883
TI		 1033 dev_info(chip->card->dev,
1034 "position_fix set to %d for device %04x:%04x\n",
1035 q->value, q->subvendor, q->subdevice);
c673ba1c 1036 return q->value;
3372a153 1037 }
bdd9ef24
DH		 1038
1039 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1040 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1041 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1042 return POS_FIX_VIACOMBO;
9477c58e
TI		 1043 }
1044 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1045 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1046 return POS_FIX_LPIB;
bdd9ef24 1047 }
c673ba1c 1048 return POS_FIX_AUTO;
3372a153
TI		 1049}
1050
669ba27a
TI		 1051/*
1052 * black-lists for probe_mask
1053 */
e23e7a14 1054static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1055 /* Thinkpad often breaks the controller communication when accessing
1056 * to the non-working (or non-existing) modem codec slot.
1057 */
1058 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1059 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1060 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1061 /* broken BIOS */
1062 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1063 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1064 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1065 /* forced codec slots */
93574844 1066 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1067 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1068 /* WinFast VP200 H (Teradici) user reported broken communication */
1069 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1070 {}
1071};
1072
f1eaaeec
TI		 1073#define AZX_FORCE_CODEC_MASK 0x100
1074
e23e7a14 1075static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1076{
1077 const struct snd_pci_quirk *q;
1078
f1eaaeec
TI		 1079 chip->codec_probe_mask = probe_mask[dev];
1080 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1081 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1082 if (q) {
4e76a883
TI		 1083 dev_info(chip->card->dev,
1084 "probe_mask set to 0x%x for device %04x:%04x\n",
1085 q->value, q->subvendor, q->subdevice);
f1eaaeec 1086 chip->codec_probe_mask = q->value;
669ba27a
TI		 1087 }
1088 }
f1eaaeec
TI		 1089
1090 /* check forced option */
1091 if (chip->codec_probe_mask != -1 &&
1092 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1093 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1094 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1095 chip->codec_mask);
f1eaaeec 1096 }
669ba27a
TI		 1097}
1098
4d8e22e0 1099/*
71623855 1100 * white/black-list for enable_msi
4d8e22e0 1101 */
e23e7a14 1102static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1103 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1104 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1105 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1106 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1107 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1108 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1109 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1110 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1111 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1112 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1113 {}
1114};
1115
e23e7a14 1116static void check_msi(struct azx *chip)
4d8e22e0
TI		 1117{
1118 const struct snd_pci_quirk *q;
1119
71623855
TI		 1120 if (enable_msi >= 0) {
1121 chip->msi = !!enable_msi;
4d8e22e0 1122 return;
71623855
TI		 1123 }
1124 chip->msi = 1; /* enable MSI as default */
1125 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1126 if (q) {
4e76a883
TI		 1127 dev_info(chip->card->dev,
1128 "msi for device %04x:%04x set to %d\n",
1129 q->subvendor, q->subdevice, q->value);
4d8e22e0 1130 chip->msi = q->value;
80c43ed7
TI		 1131 return;
1132 }
1133
1134 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1135 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1136 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1137 chip->msi = 0;
4d8e22e0
TI		 1138 }
1139}
1140
a1585d76 1141/* check the snoop mode availability */
e23e7a14 1142static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 1143{
1144 bool snoop = chip->snoop;
1145
1146 switch (chip->driver_type) {
1147 case AZX_DRIVER_VIA:
1148 /* force to non-snoop mode for a new VIA controller
1149 * when BIOS is set
1150 */
1151 if (snoop) {
1152 u8 val;
1153 pci_read_config_byte(chip->pci, 0x42, &val);
1154 if (!(val & 0x80) && chip->pci->revision == 0x30)
1155 snoop = false;
1156 }
1157 break;
1158 case AZX_DRIVER_ATIHDMI_NS:
1159 /* new ATI HDMI requires non-snoop */
1160 snoop = false;
1161 break;
c1279f87
TI		 1162 case AZX_DRIVER_CTHDA:
1163 snoop = false;
1164 break;
a1585d76
TI		 1165 }
1166
1167 if (snoop != chip->snoop) {
4e76a883
TI		 1168 dev_info(chip->card->dev, "Force to %s mode\n",
1169 snoop ? "snoop" : "non-snoop");
a1585d76
TI		 1170 chip->snoop = snoop;
1171 }
1172}
669ba27a 1173
99a2008d
WX		 1174static void azx_probe_work(struct work_struct *work)
1175{
1176 azx_probe_continue(container_of(work, struct azx, probe_work));
1177}
99a2008d 1178
1da177e4
LT		 1179/*
1180 * constructor
1181 */
e23e7a14
BP		 1182static int azx_create(struct snd_card *card, struct pci_dev *pci,
1183 int dev, unsigned int driver_caps,
40830813 1184 const struct hda_controller_ops *hda_ops,
e23e7a14 1185 struct azx **rchip)
1da177e4 1186{
a98f90fd 1187 static struct snd_device_ops ops = {
1da177e4
LT		 1188 .dev_free = azx_dev_free,
1189 };
a07187c9 1190 struct hda_intel *hda;
a82d51ed
TI		 1191 struct azx *chip;
1192 int err;
1da177e4
LT		 1193
1194 *rchip = NULL;
bcd72003 1195
927fc866
PM		 1196 err = pci_enable_device(pci);
1197 if (err < 0)
1da177e4
LT		 1198 return err;
1199
a07187c9
ML		 1200 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1201 if (!hda) {
1202 dev_err(card->dev, "Cannot allocate hda\n");
1da177e4
LT		 1203 pci_disable_device(pci);
1204 return -ENOMEM;
1205 }
1206
a07187c9 1207 chip = &hda->chip;
1da177e4 1208 spin_lock_init(&chip->reg_lock);
62932df8 1209 mutex_init(&chip->open_mutex);
1da177e4
LT		 1210 chip->card = card;
1211 chip->pci = pci;
40830813 1212 chip->ops = hda_ops;
1da177e4 1213 chip->irq = -1;
9477c58e
TI		 1214 chip->driver_caps = driver_caps;
1215 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1216 check_msi(chip);
555e219f 1217 chip->dev_index = dev;
749ee287 1218 chip->jackpoll_ms = jackpoll_ms;
9ad593f6 1219 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 1220 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 1221 INIT_LIST_HEAD(&chip->list);
a82d51ed 1222 init_vga_switcheroo(chip);
f4c482a4 1223 init_completion(&chip->probe_wait);
1da177e4 1224
beaffc39
SG		 1225 chip->position_fix[0] = chip->position_fix[1] =
1226 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 1227 /* combo mode uses LPIB for playback */
1228 if (chip->position_fix[0] == POS_FIX_COMBO) {
1229 chip->position_fix[0] = POS_FIX_LPIB;
1230 chip->position_fix[1] = POS_FIX_AUTO;
1231 }
1232
5aba4f8e 1233 check_probe_mask(chip, dev);
3372a153 1234
27346166 1235 chip->single_cmd = single_cmd;
27fe48d9 1236 chip->snoop = hda_snoop;
a1585d76 1237 azx_check_snoop_available(chip);
c74db86b 1238
5c0d7bc1
TI		 1239 if (bdl_pos_adj[dev] < 0) {
1240 switch (chip->driver_type) {
0c6341ac 1241 case AZX_DRIVER_ICH:
32679f95 1242 case AZX_DRIVER_PCH:
0c6341ac 1243 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1244 break;
1245 default:
0c6341ac 1246 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1247 break;
1248 }
1249 }
9cdc0115 1250 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1251
a82d51ed
TI		 1252 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1253 if (err < 0) {
4e76a883 1254 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1255 azx_free(chip);
1256 return err;
1257 }
1258
99a2008d
WX		 1259 /* continue probing in work context as may trigger request module */
1260 INIT_WORK(&chip->probe_work, azx_probe_work);
99a2008d 1261
a82d51ed 1262 *rchip = chip;
99a2008d 1263
a82d51ed
TI		 1264 return 0;
1265}
1266
48c8b0eb 1267static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1268{
1269 int dev = chip->dev_index;
1270 struct pci_dev *pci = chip->pci;
1271 struct snd_card *card = chip->card;
67908994 1272 int err;
a82d51ed
TI		 1273 unsigned short gcap;
1274
07e4ca50
TI		 1275#if BITS_PER_LONG != 64
1276 /* Fix up base address on ULI M5461 */
1277 if (chip->driver_type == AZX_DRIVER_ULI) {
1278 u16 tmp3;
1279 pci_read_config_word(pci, 0x40, &tmp3);
1280 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1281 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1282 }
1283#endif
1284
927fc866 1285 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1286 if (err < 0)
1da177e4 1287 return err;
a82d51ed 1288 chip->region_requested = 1;
1da177e4 1289
927fc866 1290 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1291 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1292 if (chip->remap_addr == NULL) {
4e76a883 1293 dev_err(card->dev, "ioremap error\n");
a82d51ed 1294 return -ENXIO;
1da177e4
LT		 1295 }
1296
68e7fffc
TI		 1297 if (chip->msi)
1298 if (pci_enable_msi(pci) < 0)
1299 chip->msi = 0;
7376d013 1300
a82d51ed
TI		 1301 if (azx_acquire_irq(chip, 0) < 0)
1302 return -EBUSY;
1da177e4
LT		 1303
1304 pci_set_master(pci);
1305 synchronize_irq(chip->irq);
1306
bcd72003 1307 gcap = azx_readw(chip, GCAP);
4e76a883 1308 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1309
dc4c2e6b 1310 /* disable SB600 64bit support for safety */
9477c58e 1311 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 1312 struct pci_dev *p_smbus;
1313 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1314 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1315 NULL);
1316 if (p_smbus) {
1317 if (p_smbus->revision < 0x30)
1318 gcap &= ~ICH6_GCAP_64OK;
1319 pci_dev_put(p_smbus);
1320 }
1321 }
09240cf4 1322
9477c58e
TI		 1323 /* disable 64bit DMA address on some devices */
1324 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1325 dev_dbg(card->dev, "Disabling 64bit DMA\n");
396087ea 1326 gcap &= ~ICH6_GCAP_64OK;
9477c58e 1327 }
396087ea 1328
2ae66c26 1329 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1330 if (align_buffer_size >= 0)
1331 chip->align_buffer_size = !!align_buffer_size;
1332 else {
1333 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1334 chip->align_buffer_size = 0;
1335 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1336 chip->align_buffer_size = 1;
1337 else
1338 chip->align_buffer_size = 1;
1339 }
2ae66c26 1340
cf7aaca8 1341 /* allow 64bit DMA address if supported by H/W */
b21fadb9 1342 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 1343 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 1344 else {
e930438c
YH		 1345 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1346 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1347 }
cf7aaca8 1348
8b6ed8e7
TI		 1349 /* read number of streams from GCAP register instead of using
1350 * hardcoded value
1351 */
1352 chip->capture_streams = (gcap >> 8) & 0x0f;
1353 chip->playback_streams = (gcap >> 12) & 0x0f;
1354 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1355 /* gcap didn't give any info, switching to old method */
1356
1357 switch (chip->driver_type) {
1358 case AZX_DRIVER_ULI:
1359 chip->playback_streams = ULI_NUM_PLAYBACK;
1360 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1361 break;
1362 case AZX_DRIVER_ATIHDMI:
1815b34a 1363 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1364 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1365 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1366 break;
c4da29ca 1367 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1368 default:
1369 chip->playback_streams = ICH6_NUM_PLAYBACK;
1370 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1371 break;
1372 }
07e4ca50 1373 }
8b6ed8e7
TI		 1374 chip->capture_index_offset = 0;
1375 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1376 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1377 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1378 GFP_KERNEL);
927fc866 1379 if (!chip->azx_dev) {
4e76a883 1380 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1381 return -ENOMEM;
07e4ca50
TI		 1382 }
1383
67908994 1384 err = azx_alloc_stream_pages(chip);
81740861 1385 if (err < 0)
a82d51ed 1386 return err;
1da177e4
LT		 1387
1388 /* initialize streams */
1389 azx_init_stream(chip);
1390
1391 /* initialize chip */
cb53c626 1392 azx_init_pci(chip);
e4d9e513
ML		 1393
1394 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1395 haswell_set_bclk(chip);
1396
10e77dda 1397 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1398
1399 /* codec detection */
927fc866 1400 if (!chip->codec_mask) {
4e76a883 1401 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1402 return -ENODEV;
1da177e4
LT		 1403 }
1404
07e4ca50 1405 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1406 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1407 sizeof(card->shortname));
1408 snprintf(card->longname, sizeof(card->longname),
1409 "%s at 0x%lx irq %i",
1410 card->shortname, chip->addr, chip->irq);
07e4ca50 1411
1da177e4 1412 return 0;
1da177e4
LT		 1413}
1414
cb53c626
TI		 1415static void power_down_all_codecs(struct azx *chip)
1416{
83012a7c 1417#ifdef CONFIG_PM
cb53c626
TI		 1418 /* The codecs were powered up in snd_hda_codec_new().
1419 * Now all initialization done, so turn them down if possible
1420 */
1421 struct hda_codec *codec;
1422 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1423 snd_hda_power_down(codec);
1424 }
1425#endif
1426}
1427
97c6a3d1 1428#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1429/* callback from request_firmware_nowait() */
1430static void azx_firmware_cb(const struct firmware *fw, void *context)
1431{
1432 struct snd_card *card = context;
1433 struct azx *chip = card->private_data;
1434 struct pci_dev *pci = chip->pci;
1435
1436 if (!fw) {
4e76a883 1437 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1438 goto error;
1439 }
1440
1441 chip->fw = fw;
1442 if (!chip->disabled) {
1443 /* continue probing */
1444 if (azx_probe_continue(chip))
1445 goto error;
1446 }
1447 return; /* OK */
1448
1449 error:
1450 snd_card_free(card);
1451 pci_set_drvdata(pci, NULL);
1452}
97c6a3d1 1453#endif
5cb543db 1454
40830813
DR		 1455/*
1456 * HDA controller ops.
1457 */
1458
1459/* PCI register access. */
db291e36 1460static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1461{
1462 writel(value, addr);
1463}
1464
db291e36 1465static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1466{
1467 return readl(addr);
1468}
1469
db291e36 1470static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1471{
1472 writew(value, addr);
1473}
1474
db291e36 1475static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1476{
1477 return readw(addr);
1478}
1479
db291e36 1480static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1481{
1482 writeb(value, addr);
1483}
1484
db291e36 1485static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1486{
1487 return readb(addr);
1488}
1489
f46ea609
DR		 1490static int disable_msi_reset_irq(struct azx *chip)
1491{
1492 int err;
1493
1494 free_irq(chip->irq, chip);
1495 chip->irq = -1;
1496 pci_disable_msi(chip->pci);
1497 chip->msi = 0;
1498 err = azx_acquire_irq(chip, 1);
1499 if (err < 0)
1500 return err;
1501
1502 return 0;
1503}
1504
b419b35b
DR		 1505/* DMA page allocation helpers. */
1506static int dma_alloc_pages(struct azx *chip,
1507 int type,
1508 size_t size,
1509 struct snd_dma_buffer *buf)
1510{
1511 int err;
1512
1513 err = snd_dma_alloc_pages(type,
1514 chip->card->dev,
1515 size, buf);
1516 if (err < 0)
1517 return err;
1518 mark_pages_wc(chip, buf, true);
1519 return 0;
1520}
1521
1522static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1523{
1524 mark_pages_wc(chip, buf, false);
1525 snd_dma_free_pages(buf);
1526}
1527
1528static int substream_alloc_pages(struct azx *chip,
1529 struct snd_pcm_substream *substream,
1530 size_t size)
1531{
1532 struct azx_dev *azx_dev = get_azx_dev(substream);
1533 int ret;
1534
1535 mark_runtime_wc(chip, azx_dev, substream, false);
1536 azx_dev->bufsize = 0;
1537 azx_dev->period_bytes = 0;
1538 azx_dev->format_val = 0;
1539 ret = snd_pcm_lib_malloc_pages(substream, size);
1540 if (ret < 0)
1541 return ret;
1542 mark_runtime_wc(chip, azx_dev, substream, true);
1543 return 0;
1544}
1545
1546static int substream_free_pages(struct azx *chip,
1547 struct snd_pcm_substream *substream)
1548{
1549 struct azx_dev *azx_dev = get_azx_dev(substream);
1550 mark_runtime_wc(chip, azx_dev, substream, false);
1551 return snd_pcm_lib_free_pages(substream);
1552}
1553
8769b278
DR		 1554static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1555 struct vm_area_struct *area)
1556{
1557#ifdef CONFIG_X86
1558 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1559 struct azx *chip = apcm->chip;
1560 if (!azx_snoop(chip))
1561 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1562#endif
1563}
1564
40830813 1565static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1566 .reg_writel = pci_azx_writel,
1567 .reg_readl = pci_azx_readl,
1568 .reg_writew = pci_azx_writew,
1569 .reg_readw = pci_azx_readw,
1570 .reg_writeb = pci_azx_writeb,
1571 .reg_readb = pci_azx_readb,
f46ea609 1572 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1573 .dma_alloc_pages = dma_alloc_pages,
1574 .dma_free_pages = dma_free_pages,
1575 .substream_alloc_pages = substream_alloc_pages,
1576 .substream_free_pages = substream_free_pages,
8769b278 1577 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1578 .position_check = azx_position_check,
40830813
DR		 1579};
1580
e23e7a14
BP		 1581static int azx_probe(struct pci_dev *pci,
1582 const struct pci_device_id *pci_id)
1da177e4 1583{
5aba4f8e 1584 static int dev;
a98f90fd
TI		 1585 struct snd_card *card;
1586 struct azx *chip;
aad730d0 1587 bool schedule_probe;
927fc866 1588 int err;
1da177e4 1589
5aba4f8e
TI		 1590 if (dev >= SNDRV_CARDS)
1591 return -ENODEV;
1592 if (!enable[dev]) {
1593 dev++;
1594 return -ENOENT;
1595 }
1596
60c5772b
TI		 1597 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1598 0, &card);
e58de7ba 1599 if (err < 0) {
4e76a883 1600 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1601 return err;
1da177e4
LT		 1602 }
1603
40830813
DR		 1604 err = azx_create(card, pci, dev, pci_id->driver_data,
1605 &pci_hda_ops, &chip);
41dda0fd
WF		 1606 if (err < 0)
1607 goto out_free;
421a1252 1608 card->private_data = chip;
f4c482a4
TI		 1609
1610 pci_set_drvdata(pci, card);
1611
1612 err = register_vga_switcheroo(chip);
1613 if (err < 0) {
4e76a883 1614 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1615 goto out_free;
1616 }
1617
1618 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1619 dev_info(card->dev, "VGA controller is disabled\n");
1620 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1621 chip->disabled = true;
1622 }
1623
aad730d0 1624 schedule_probe = !chip->disabled;
1da177e4 1625
4918cdab
TI		 1626#ifdef CONFIG_SND_HDA_PATCH_LOADER
1627 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1628 dev_info(card->dev, "Applying patch firmware '%s'\n",
1629 patch[dev]);
5cb543db
TI		 1630 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1631 &pci->dev, GFP_KERNEL, card,
1632 azx_firmware_cb);
4918cdab
TI		 1633 if (err < 0)
1634 goto out_free;
aad730d0 1635 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1636 }
1637#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1638
aad730d0
TI		 1639#ifndef CONFIG_SND_HDA_I915
1640 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1641 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1642#endif
99a2008d 1643
aad730d0
TI		 1644 if (schedule_probe)
1645 schedule_work(&chip->probe_work);
a82d51ed 1646
a82d51ed 1647 dev++;
88d071fc
TI		 1648 if (chip->disabled)
1649 complete_all(&chip->probe_wait);
a82d51ed
TI		 1650 return 0;
1651
1652out_free:
1653 snd_card_free(card);
1654 return err;
1655}
1656
e62a42ae
DR		 1657/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1658static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1659 [AZX_DRIVER_NVIDIA] = 8,
1660 [AZX_DRIVER_TERA] = 1,
1661};
1662
48c8b0eb 1663static int azx_probe_continue(struct azx *chip)
a82d51ed 1664{
c67e2228 1665 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1666 int dev = chip->dev_index;
1667 int err;
1668
99a2008d
WX		 1669 /* Request power well for Haswell HDA controller and codec */
1670 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1671#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1672 err = hda_i915_init();
1673 if (err < 0) {
4e76a883
TI		 1674 dev_err(chip->card->dev,
1675 "Error request power-well from i915\n");
99a2008d
WX		 1676 goto out_free;
1677 }
74b0c2d7
TI		 1678 err = hda_display_power(true);
1679 if (err < 0) {
1680 dev_err(chip->card->dev,
1681 "Cannot turn on display power on i915\n");
1682 goto out_free;
1683 }
c841ad2a 1684#endif
99a2008d
WX		 1685 }
1686
5c90680e
TI		 1687 err = azx_first_init(chip);
1688 if (err < 0)
1689 goto out_free;
1690
2dca0bba
JK		 1691#ifdef CONFIG_SND_HDA_INPUT_BEEP
1692 chip->beep_mode = beep_mode[dev];
1693#endif
1694
1da177e4 1695 /* create codec instances */
e62a42ae
DR		 1696 err = azx_codec_create(chip, model[dev],
1697 azx_max_codecs[chip->driver_type],
1698 power_save_addr);
1699
41dda0fd
WF		 1700 if (err < 0)
1701 goto out_free;
4ea6fbc8 1702#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1703 if (chip->fw) {
1704 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1705 chip->fw->data);
4ea6fbc8
TI		 1706 if (err < 0)
1707 goto out_free;
e39ae856 1708#ifndef CONFIG_PM
4918cdab
TI		 1709 release_firmware(chip->fw); /* no longer needed */
1710 chip->fw = NULL;
e39ae856 1711#endif
4ea6fbc8
TI		 1712 }
1713#endif
10e77dda 1714 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1715 err = azx_codec_configure(chip);
1716 if (err < 0)
1717 goto out_free;
1718 }
1da177e4
LT		 1719
1720 /* create PCM streams */
176d5335 1721 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1722 if (err < 0)
1723 goto out_free;
1da177e4
LT		 1724
1725 /* create mixer controls */
d01ce99f 1726 err = azx_mixer_create(chip);
41dda0fd
WF		 1727 if (err < 0)
1728 goto out_free;
1da177e4 1729
a82d51ed 1730 err = snd_card_register(chip->card);
41dda0fd
WF		 1731 if (err < 0)
1732 goto out_free;
1da177e4 1733
cb53c626
TI		 1734 chip->running = 1;
1735 power_down_all_codecs(chip);
0cbf0098 1736 azx_notifier_register(chip);
65fcd41d 1737 azx_add_card_list(chip);
246efa4a 1738 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 1739 pm_runtime_put_noidle(&pci->dev);
1da177e4 1740
41dda0fd 1741out_free:
88d071fc
TI		 1742 if (err < 0)
1743 chip->init_failed = 1;
1744 complete_all(&chip->probe_wait);
41dda0fd 1745 return err;
1da177e4
LT		 1746}
1747
e23e7a14 1748static void azx_remove(struct pci_dev *pci)
1da177e4 1749{
9121947d 1750 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1751
9121947d
TI		 1752 if (card)
1753 snd_card_free(card);
1da177e4
LT		 1754}
1755
1756/* PCI IDs */
6f51f6cf 1757static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1758 /* CPT */
9477c58e 1759 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1760 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1761 /* PBG */
9477c58e 1762 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1763 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1764 /* Panther Point */
9477c58e 1765 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 1766 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 1767 /* Lynx Point */
1768 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1769 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 1770 /* 9 Series */
1771 { PCI_DEVICE(0x8086, 0x8ca0),
1772 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1773 /* Wellsburg */
1774 { PCI_DEVICE(0x8086, 0x8d20),
1775 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1776 { PCI_DEVICE(0x8086, 0x8d21),
1777 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1778 /* Lynx Point-LP */
1779 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1780 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1781 /* Lynx Point-LP */
1782 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 1783 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 1784 /* Wildcat Point-LP */
1785 { PCI_DEVICE(0x8086, 0x9ca0),
1786 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 1787 /* Haswell */
4a7c516b 1788 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 1789 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 1790 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 1791 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 1792 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 1793 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 1794 /* Broadwell */
1795 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 1796 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 1797 /* 5 Series/3400 */
1798 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 1799 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 1800 /* Poulsbo */
9477c58e 1801 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 1802 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1803 /* Oaktrail */
09904b95 1804 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 1805 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 1806 /* BayTrail */
1807 { PCI_DEVICE(0x8086, 0x0f04),
1808 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 1809 /* ICH */
8b0bd226 1810 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 1811 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1812 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 1813 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 1814 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1815 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 1816 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 1817 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1818 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 1819 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 1820 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1821 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 1822 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 1823 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1824 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1825 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 1826 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1827 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1828 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 1829 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1830 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 1831 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 1832 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1833 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 1834 /* Generic Intel */
1835 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
1836 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1837 .class_mask = 0xffffff,
2ae66c26 1838 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 1839 /* ATI SB 450/600/700/800/900 */
1840 { PCI_DEVICE(0x1002, 0x437b),
1841 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1842 { PCI_DEVICE(0x1002, 0x4383),
1843 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1844 /* AMD Hudson */
1845 { PCI_DEVICE(0x1022, 0x780d),
1846 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 1847 /* ATI HDMI */
9477c58e
TI		 1848 { PCI_DEVICE(0x1002, 0x793b),
1849 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1850 { PCI_DEVICE(0x1002, 0x7919),
1851 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1852 { PCI_DEVICE(0x1002, 0x960f),
1853 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1854 { PCI_DEVICE(0x1002, 0x970f),
1855 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1856 { PCI_DEVICE(0x1002, 0xaa00),
1857 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1858 { PCI_DEVICE(0x1002, 0xaa08),
1859 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1860 { PCI_DEVICE(0x1002, 0xaa10),
1861 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1862 { PCI_DEVICE(0x1002, 0xaa18),
1863 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1864 { PCI_DEVICE(0x1002, 0xaa20),
1865 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1866 { PCI_DEVICE(0x1002, 0xaa28),
1867 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1868 { PCI_DEVICE(0x1002, 0xaa30),
1869 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1870 { PCI_DEVICE(0x1002, 0xaa38),
1871 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1872 { PCI_DEVICE(0x1002, 0xaa40),
1873 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1874 { PCI_DEVICE(0x1002, 0xaa48),
1875 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 1876 { PCI_DEVICE(0x1002, 0xaa50),
1877 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1878 { PCI_DEVICE(0x1002, 0xaa58),
1879 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1880 { PCI_DEVICE(0x1002, 0xaa60),
1881 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1882 { PCI_DEVICE(0x1002, 0xaa68),
1883 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1884 { PCI_DEVICE(0x1002, 0xaa80),
1885 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1886 { PCI_DEVICE(0x1002, 0xaa88),
1887 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1888 { PCI_DEVICE(0x1002, 0xaa90),
1889 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1890 { PCI_DEVICE(0x1002, 0xaa98),
1891 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 1892 { PCI_DEVICE(0x1002, 0x9902),
1893 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1894 { PCI_DEVICE(0x1002, 0xaaa0),
1895 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1896 { PCI_DEVICE(0x1002, 0xaaa8),
1897 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1898 { PCI_DEVICE(0x1002, 0xaab0),
1899 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 1900 /* VIA VT8251/VT8237A */
9477c58e
TI		 1901 { PCI_DEVICE(0x1106, 0x3288),
1902 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 1903 /* VIA GFX VT7122/VX900 */
1904 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
1905 /* VIA GFX VT6122/VX11 */
1906 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 1907 /* SIS966 */
1908 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
1909 /* ULI M5461 */
1910 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
1911 /* NVIDIA MCP */
0c2fd1bf
TI		 1912 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1913 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1914 .class_mask = 0xffffff,
9477c58e 1915 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 1916 /* Teradici */
9477c58e
TI		 1917 { PCI_DEVICE(0x6549, 0x1200),
1918 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 1919 { PCI_DEVICE(0x6549, 0x2200),
1920 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 1921 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 1922 /* CTHDA chips */
1923 { PCI_DEVICE(0x1102, 0x0010),
1924 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
1925 { PCI_DEVICE(0x1102, 0x0012),
1926 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 1927#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 1928 /* the following entry conflicts with snd-ctxfi driver,
1929 * as ctxfi driver mutates from HD-audio to native mode with
1930 * a special command sequence.
1931 */
4e01f54b
TI		 1932 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
1933 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1934 .class_mask = 0xffffff,
9477c58e 1935 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1936 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 1937#else
1938 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 1939 { PCI_DEVICE(0x1102, 0x0009),
1940 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1941 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 1942#endif
e35d4b11
OS		 1943 /* Vortex86MX */
1944 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 1945 /* VMware HDAudio */
1946 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 1947 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 1948 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
1949 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1950 .class_mask = 0xffffff,
9477c58e 1951 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 1952 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
1953 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1954 .class_mask = 0xffffff,
9477c58e 1955 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 1956 { 0, }
1957};
1958MODULE_DEVICE_TABLE(pci, azx_ids);
1959
1960/* pci_driver definition */
e9f66d9b 1961static struct pci_driver azx_driver = {
3733e424 1962 .name = KBUILD_MODNAME,
1da177e4
LT		 1963 .id_table = azx_ids,
1964 .probe = azx_probe,
e23e7a14 1965 .remove = azx_remove,
68cb2b55
TI		 1966 .driver = {
1967 .pm = AZX_PM_OPS,
1968 },
1da177e4
LT		 1969};
1970
e9f66d9b 1971module_pci_driver(azx_driver);
Linux 6.x block layer and io_uring tree(s)