projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda - Fix pending unsol events at shutdown
[linux-2.6-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
5d890f59 38
27fe48d9
TI		 39#ifdef CONFIG_X86
40/* for snoop control */
41#include <asm/pgtable.h>
7f80f513 42#include <asm/set_memory.h>
50279d9b 43#include <asm/cpufeature.h>
27fe48d9 44#endif
1da177e4
LT		 45#include <sound/core.h>
46#include <sound/initval.h>
98d8fc6c
ML		 47#include <sound/hdaudio.h>
48#include <sound/hda_i915.h>
82d9d54a 49#include <sound/intel-dsp-config.h>
9121947d 50#include <linux/vgaarb.h>
a82d51ed 51#include <linux/vga_switcheroo.h>
4918cdab 52#include <linux/firmware.h>
be57bfff 53#include <sound/hda_codec.h>
05e84878 54#include "hda_controller.h"
347de1f8 55#include "hda_intel.h"
1da177e4 56
785d8c4b
LY		 57#define CREATE_TRACE_POINTS
58#include "hda_intel_trace.h"
59
b6050ef6
TI		 60/* position fix mode */
61enum {
62 POS_FIX_AUTO,
63 POS_FIX_LPIB,
64 POS_FIX_POSBUF,
65 POS_FIX_VIACOMBO,
66 POS_FIX_COMBO,
f87e7f25 67 POS_FIX_SKL,
c02f77d3 68 POS_FIX_FIFO,
b6050ef6
TI		 69};
70
9a34af4a
TI		 71/* Defines for ATI HD Audio support in SB450 south bridge */
72#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
73#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
74
75/* Defines for Nvidia HDA support */
76#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
77#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
78#define NVIDIA_HDA_ISTRM_COH 0x4d
79#define NVIDIA_HDA_OSTRM_COH 0x4c
80#define NVIDIA_HDA_ENABLE_COHBIT 0x01
81
82/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 83#define INTEL_HDA_CGCTL 0x48
84#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 85#define INTEL_SCH_HDA_DEVC 0x78
86#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
87
9a34af4a
TI		 88/* Define VIA HD Audio Device ID*/
89#define VIA_HDAC_DEVICE_ID 0x3288
90
33124929
TI		 91/* max number of SDs */
92/* ICH, ATI and VIA have 4 playback and 4 capture */
93#define ICH6_NUM_CAPTURE 4
94#define ICH6_NUM_PLAYBACK 4
95
96/* ULI has 6 playback and 5 capture */
97#define ULI_NUM_CAPTURE 5
98#define ULI_NUM_PLAYBACK 6
99
100/* ATI HDMI may have up to 8 playbacks and 0 capture */
101#define ATIHDMI_NUM_CAPTURE 0
102#define ATIHDMI_NUM_PLAYBACK 8
103
104/* TERA has 4 playback and 3 capture */
105#define TERA_NUM_CAPTURE 3
106#define TERA_NUM_PLAYBACK 4
107
1da177e4 108
5aba4f8e
TI		 109static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
110static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 111static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 112static char *model[SNDRV_CARDS];
1dac6695 113static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 114static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 115static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 116static int probe_only[SNDRV_CARDS];
26a6cb6c 117static int jackpoll_ms[SNDRV_CARDS];
41438f13 118static int single_cmd = -1;
71623855 119static int enable_msi = -1;
4ea6fbc8
TI		 120#ifdef CONFIG_SND_HDA_PATCH_LOADER
121static char *patch[SNDRV_CARDS];
122#endif
2dca0bba 123#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 124static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 125 CONFIG_SND_HDA_INPUT_BEEP_MODE};
126#endif
82d9d54a 127static bool dsp_driver = 1;
1da177e4 128
5aba4f8e 129module_param_array(index, int, NULL, 0444);
1da177e4 130MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 131module_param_array(id, charp, NULL, 0444);
1da177e4 132MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 133module_param_array(enable, bool, NULL, 0444);
134MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
135module_param_array(model, charp, NULL, 0444);
1da177e4 136MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 137module_param_array(position_fix, int, NULL, 0444);
4cb36310 138MODULE_PARM_DESC(position_fix, "DMA pointer read method."
c02f77d3 139 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
555e219f
TI		 140module_param_array(bdl_pos_adj, int, NULL, 0644);
141MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 142module_param_array(probe_mask, int, NULL, 0444);
606ad75f 143MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 144module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 145MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 146module_param_array(jackpoll_ms, int, NULL, 0444);
147MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 148module_param(single_cmd, bint, 0444);
d01ce99f
TI		 149MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
150 "(for debugging only).");
ac9ef6cf 151module_param(enable_msi, bint, 0444);
134a11f0 152MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 153#ifdef CONFIG_SND_HDA_PATCH_LOADER
154module_param_array(patch, charp, NULL, 0444);
155MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
156#endif
2dca0bba 157#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 158module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 159MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 160 "(0=off, 1=on) (default=1).");
2dca0bba 161#endif
82d9d54a
JK		 162module_param(dsp_driver, bool, 0444);
163MODULE_PARM_DESC(dsp_driver, "Allow DSP driver selection (bypass this driver) "
164 "(0=off, 1=on) (default=1)");
606ad75f 165
83012a7c 166#ifdef CONFIG_PM
65fcd41d 167static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 168static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 169 .set = param_set_xint,
170 .get = param_get_int,
171};
172#define param_check_xint param_check_int
173
fee2fba3 174static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 175module_param(power_save, xint, 0644);
fee2fba3
TI		 176MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
177 "(in second, 0 = disable).");
1da177e4 178
40088dc4
TI		 179static bool pm_blacklist = true;
180module_param(pm_blacklist, bool, 0644);
181MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
182
dee1b66c
TI		 183/* reset the HD-audio controller in power save mode.
184 * this may give more power-saving, but will take longer time to
185 * wake up.
186 */
8fc24426
TI		 187static bool power_save_controller = 1;
188module_param(power_save_controller, bool, 0644);
dee1b66c 189MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 190#else
bb573928 191#define power_save 0
83012a7c 192#endif /* CONFIG_PM */
dee1b66c 193
7bfe059e
TI		 194static int align_buffer_size = -1;
195module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 196MODULE_PARM_DESC(align_buffer_size,
197 "Force buffer and period sizes to be multiple of 128 bytes.");
198
27fe48d9 199#ifdef CONFIG_X86
7c732015
TI		 200static int hda_snoop = -1;
201module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 202MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 203#else
204#define hda_snoop true
27fe48d9
TI		 205#endif
206
207
1da177e4
LT		 208MODULE_LICENSE("GPL");
209MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
210 "{Intel, ICH6M},"
2f1b3818 211 "{Intel, ICH7},"
f5d40b30 212 "{Intel, ESB2},"
d2981393 213 "{Intel, ICH8},"
f9cc8a8b 214 "{Intel, ICH9},"
c34f5a04 215 "{Intel, ICH10},"
b29c2360 216 "{Intel, PCH},"
d2f2fcd2 217 "{Intel, CPT},"
d2edeb7c 218 "{Intel, PPT},"
8bc039a1 219 "{Intel, LPT},"
144dad99 220 "{Intel, LPT_LP},"
4eeca499 221 "{Intel, WPT_LP},"
c8b00fd2 222 "{Intel, SPT},"
b4565913 223 "{Intel, SPT_LP},"
e926f2c8 224 "{Intel, HPT},"
cea310e8 225 "{Intel, PBG},"
4979bca9 226 "{Intel, SCH},"
fc20a562 227 "{ATI, SB450},"
89be83f8 228 "{ATI, SB600},"
778b6e1b 229 "{ATI, RS600},"
5b15c95f 230 "{ATI, RS690},"
e6db1119
WL		 231 "{ATI, RS780},"
232 "{ATI, R600},"
2797f724
HRK		 233 "{ATI, RV630},"
234 "{ATI, RV610},"
27da1834
WL		 235 "{ATI, RV670},"
236 "{ATI, RV635},"
237 "{ATI, RV620},"
238 "{ATI, RV770},"
fc20a562 239 "{VIA, VT8251},"
47672310 240 "{VIA, VT8237A},"
07e4ca50
TI		 241 "{SiS, SIS966},"
242 "{ULI, M5461}}");
1da177e4
LT		 243MODULE_DESCRIPTION("Intel HDA driver");
244
a82d51ed 245#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 246#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 247#define SUPPORT_VGA_SWITCHEROO
248#endif
249#endif
250
251
1da177e4 252/*
1da177e4 253 */
1da177e4 254
07e4ca50
TI		 255/* driver types */
256enum {
257 AZX_DRIVER_ICH,
32679f95 258 AZX_DRIVER_PCH,
4979bca9 259 AZX_DRIVER_SCH,
a4b4793f 260 AZX_DRIVER_SKL,
fab1285a 261 AZX_DRIVER_HDMI,
07e4ca50 262 AZX_DRIVER_ATI,
778b6e1b 263 AZX_DRIVER_ATIHDMI,
1815b34a 264 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 265 AZX_DRIVER_VIA,
266 AZX_DRIVER_SIS,
267 AZX_DRIVER_ULI,
da3fca21 268 AZX_DRIVER_NVIDIA,
f269002e 269 AZX_DRIVER_TERA,
14d34f16 270 AZX_DRIVER_CTX,
5ae763b1 271 AZX_DRIVER_CTHDA,
c563f473 272 AZX_DRIVER_CMEDIA,
b6fcab14 273 AZX_DRIVER_ZHAOXIN,
c4da29ca 274 AZX_DRIVER_GENERIC,
2f5983f2 275 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 276};
277
37e661ee
TI		 278#define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
b42b4afb
TI		 282/* quirks for old Intel chipsets */
283#define AZX_DCAPS_INTEL_ICH \
103884a3 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 285
2ea3c6a2 286/* quirks for Intel PCH */
6603249d 287#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 289 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 290
dba9b7b6 291/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 292#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 293 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 294
55913110 295/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 296/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 297#define AZX_DCAPS_INTEL_PCH \
6603249d 298 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 299
6603249d 300/* HSW HDMI */
33499a15 301#define AZX_DCAPS_INTEL_HASWELL \
103884a3 302 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 303 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 304 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 305
54a0405d
LY		 306/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
307#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 308 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 309 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 310 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 311
40cc2392 312#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 313 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 314
2d846c74 315#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 316 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 317 AZX_DCAPS_I915_COMPONENT)
2d846c74 318
d6795827 319#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 320 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
2756d914 321 AZX_DCAPS_SYNC_WRITE |\
e454ff8e 322 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 323
2756d914 324#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
c87693da 325
9477c58e
TI		 326/* quirks for ATI SB / AMD Hudson */
327#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 328 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
329 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 330
331/* quirks for ATI/AMD HDMI */
332#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 333 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
334 AZX_DCAPS_NO_MSI64)
9477c58e 335
37e661ee
TI		 336/* quirks for ATI HDMI with snoop off */
337#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
338 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
339
c02f77d3
TI		 340/* quirks for AMD SB */
341#define AZX_DCAPS_PRESET_AMD_SB \
342 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
343 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
344
9477c58e
TI		 345/* quirks for Nvidia */
346#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 347 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 348 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 349
5ae763b1 350#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 351 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 352 AZX_DCAPS_NO_64BIT |\
37e661ee 353 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 354
a82d51ed 355/*
2b760d88 356 * vga_switcheroo support
a82d51ed
TI		 357 */
358#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 359#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
dd23e1d5 360#define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
5cb543db
TI		 361#else
362#define use_vga_switcheroo(chip) 0
37a3a98e 363#define needs_eld_notify_link(chip) false
5cb543db
TI		 364#endif
365
03b135ce
LY		 366#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
367 ((pci)->device == 0x0c0c) || \
368 ((pci)->device == 0x0d0c) || \
369 ((pci)->device == 0x160c))
370
7e31a015 371#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
a8d7bde2 372#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
fa763f1b 373#define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
7c23b7c1 374
48c8b0eb 375static char *driver_short_names[] = {
07e4ca50 376 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 377 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 378 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 379 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 380 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 381 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 382 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 383 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 384 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
385 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 386 [AZX_DRIVER_ULI] = "HDA ULI M5461",
387 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 388 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 389 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 390 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 391 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
b6fcab14 392 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
c4da29ca 393 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 394};
395
68e7fffc 396static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 397static void set_default_power_save(struct azx *chip);
111d3af5 398
cb53c626
TI		 399/*
400 * initialize the PCI registers
401 */
402/* update bits in a PCI register byte */
403static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
404 unsigned char mask, unsigned char val)
405{
406 unsigned char data;
407
408 pci_read_config_byte(pci, reg, &data);
409 data &= ~mask;
410 data |= (val & mask);
411 pci_write_config_byte(pci, reg, data);
412}
413
414static void azx_init_pci(struct azx *chip)
415{
37e661ee
TI		 416 int snoop_type = azx_get_snoop_type(chip);
417
cb53c626
TI		 418 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
419 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
420 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 421 * codecs.
422 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 423 */
46f2cc80 424 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 425 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 426 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 427 }
cb53c626 428
9477c58e
TI		 429 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
430 * we need to enable snoop.
431 */
37e661ee 432 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 433 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
434 azx_snoop(chip));
cb53c626 435 update_pci_byte(chip->pci,
27fe48d9
TI		 436 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
437 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 438 }
439
440 /* For NVIDIA HDA, enable snoop */
37e661ee 441 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 442 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
443 azx_snoop(chip));
cb53c626
TI		 444 update_pci_byte(chip->pci,
445 NVIDIA_HDA_TRANSREG_ADDR,
446 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 447 update_pci_byte(chip->pci,
448 NVIDIA_HDA_ISTRM_COH,
449 0x01, NVIDIA_HDA_ENABLE_COHBIT);
450 update_pci_byte(chip->pci,
451 NVIDIA_HDA_OSTRM_COH,
452 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 453 }
454
455 /* Enable SCH/PCH snoop if needed */
37e661ee 456 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 457 unsigned short snoop;
90a5ad52 458 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 459 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
460 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
461 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
462 if (!azx_snoop(chip))
463 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
464 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 465 pci_read_config_word(chip->pci,
466 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 467 }
4e76a883
TI		 468 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
469 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
470 "Disabled" : "Enabled");
da3fca21 471 }
1da177e4
LT		 472}
473
7c23b7c1
LH		 474/*
475 * In BXT-P A0, HD-Audio DMA requests is later than expected,
476 * and makes an audio stream sensitive to system latencies when
477 * 24/32 bits are playing.
478 * Adjusting threshold of DMA fifo to force the DMA request
479 * sooner to improve latency tolerance at the expense of power.
480 */
481static void bxt_reduce_dma_latency(struct azx *chip)
482{
483 u32 val;
484
70eafad8 485 val = azx_readl(chip, VS_EM4L);
7c23b7c1 486 val &= (0x3 << 20);
70eafad8 487 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 488}
489
1f9d3d98
LY		 490/*
491 * ML_LCAP bits:
492 * bit 0: 6 MHz Supported
493 * bit 1: 12 MHz Supported
494 * bit 2: 24 MHz Supported
495 * bit 3: 48 MHz Supported
496 * bit 4: 96 MHz Supported
497 * bit 5: 192 MHz Supported
498 */
499static int intel_get_lctl_scf(struct azx *chip)
500{
501 struct hdac_bus *bus = azx_bus(chip);
502 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
503 u32 val, t;
504 int i;
505
506 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
507
508 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
509 t = preferred_bits[i];
510 if (val & (1 << t))
511 return t;
512 }
513
514 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
515 return 0;
516}
517
518static int intel_ml_lctl_set_power(struct azx *chip, int state)
519{
520 struct hdac_bus *bus = azx_bus(chip);
521 u32 val;
522 int timeout;
523
524 /*
525 * the codecs are sharing the first link setting by default
526 * If other links are enabled for stream, they need similar fix
527 */
528 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
529 val &= ~AZX_MLCTL_SPA;
530 val |= state << AZX_MLCTL_SPA_SHIFT;
531 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
532 /* wait for CPA */
533 timeout = 50;
534 while (timeout) {
535 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
536 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
537 return 0;
538 timeout--;
539 udelay(10);
540 }
541
542 return -1;
543}
544
545static void intel_init_lctl(struct azx *chip)
546{
547 struct hdac_bus *bus = azx_bus(chip);
548 u32 val;
549 int ret;
550
551 /* 0. check lctl register value is correct or not */
552 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
553 /* if SCF is already set, let's use it */
554 if ((val & ML_LCTL_SCF_MASK) != 0)
555 return;
556
557 /*
558 * Before operating on SPA, CPA must match SPA.
559 * Any deviation may result in undefined behavior.
560 */
561 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
562 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
563 return;
564
565 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
566 ret = intel_ml_lctl_set_power(chip, 0);
567 udelay(100);
568 if (ret)
569 goto set_spa;
570
571 /* 2. update SCF to select a properly audio clock*/
572 val &= ~ML_LCTL_SCF_MASK;
573 val |= intel_get_lctl_scf(chip);
574 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
575
576set_spa:
577 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
578 intel_ml_lctl_set_power(chip, 1);
579 udelay(100);
580}
581
0a673521
LH		 582static void hda_intel_init_chip(struct azx *chip, bool full_reset)
583{
98d8fc6c 584 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 585 struct pci_dev *pci = chip->pci;
6639484d 586 u32 val;
0a673521 587
e454ff8e 588 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 589 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 590 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
591 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
592 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
593 }
0a673521 594 azx_init_chip(chip, full_reset);
a4b4793f 595 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 596 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
597 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
598 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
599 }
e454ff8e
TI		 600
601 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 602
603 /* reduce dma latency to avoid noise */
7e31a015 604 if (IS_BXT(pci))
7c23b7c1 605 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 606
607 if (bus->mlcap != NULL)
608 intel_init_lctl(chip);
0a673521
LH		 609}
610
b6050ef6
TI		 611/* calculate runtime delay from LPIB */
612static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
613 unsigned int pos)
614{
7833c3f8 615 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 616 int stream = substream->stream;
617 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
618 int delay;
619
620 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
621 delay = pos - lpib_pos;
622 else
623 delay = lpib_pos - pos;
624 if (delay < 0) {
7833c3f8 625 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 626 delay = 0;
627 else
7833c3f8 628 delay += azx_dev->core.bufsize;
b6050ef6
TI		 629 }
630
7833c3f8 631 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 632 dev_info(chip->card->dev,
633 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 634 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 635 delay = 0;
636 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
637 chip->get_delay[stream] = NULL;
638 }
639
640 return bytes_to_frames(substream->runtime, delay);
641}
642
9ad593f6
TI		 643static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
644
7ca954a8
DR		 645/* called from IRQ */
646static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
647{
9a34af4a 648 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 649 int ok;
650
651 ok = azx_position_ok(chip, azx_dev);
652 if (ok == 1) {
653 azx_dev->irq_pending = 0;
654 return ok;
2f35c630 655 } else if (ok == 0) {
7ca954a8
DR		 656 /* bogus IRQ, process it later */
657 azx_dev->irq_pending = 1;
2f35c630 658 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 659 }
660 return 0;
661}
662
029d92c2
TI		 663#define display_power(chip, enable) \
664 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 665
9ad593f6
TI		 666/*
667 * Check whether the current DMA position is acceptable for updating
668 * periods. Returns non-zero if it's OK.
669 *
670 * Many HD-audio controllers appear pretty inaccurate about
671 * the update-IRQ timing. The IRQ is issued before actually the
672 * data is processed. So, we need to process it afterwords in a
673 * workqueue.
674 */
675static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
676{
7833c3f8 677 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 678 int stream = substream->stream;
e5463720 679 u32 wallclk;
9ad593f6
TI		 680 unsigned int pos;
681
7833c3f8
TI		 682 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
683 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 684 return -1; /* bogus (too early) interrupt */
fa00e046 685
b6050ef6
TI		 686 if (chip->get_position[stream])
687 pos = chip->get_position[stream](chip, azx_dev);
688 else { /* use the position buffer as default */
689 pos = azx_get_pos_posbuf(chip, azx_dev);
690 if (!pos || pos == (u32)-1) {
691 dev_info(chip->card->dev,
692 "Invalid position buffer, using LPIB read method instead.\n");
693 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 694 if (chip->get_position[0] == azx_get_pos_lpib &&
695 chip->get_position[1] == azx_get_pos_lpib)
696 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 697 pos = azx_get_pos_lpib(chip, azx_dev);
698 chip->get_delay[stream] = NULL;
699 } else {
700 chip->get_position[stream] = azx_get_pos_posbuf;
701 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
702 chip->get_delay[stream] = azx_get_delay_from_lpib;
703 }
704 }
705
7833c3f8 706 if (pos >= azx_dev->core.bufsize)
b6050ef6 707 pos = 0;
9ad593f6 708
7833c3f8 709 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 710 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 711 return -1; /* this shouldn't happen! */
7833c3f8
TI		 712 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
713 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 714 /* NG - it's below the first next period boundary */
4f0189be 715 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 716 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 717 return 1; /* OK, it's fine */
718}
719
720/*
721 * The work for pending PCM period updates.
722 */
723static void azx_irq_pending_work(struct work_struct *work)
724{
9a34af4a
TI		 725 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
726 struct azx *chip = &hda->chip;
7833c3f8
TI		 727 struct hdac_bus *bus = azx_bus(chip);
728 struct hdac_stream *s;
729 int pending, ok;
9ad593f6 730
9a34af4a 731 if (!hda->irq_pending_warned) {
4e76a883
TI		 732 dev_info(chip->card->dev,
733 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
734 chip->card->number);
9a34af4a 735 hda->irq_pending_warned = 1;
a6a950a8
TI		 736 }
737
9ad593f6
TI		 738 for (;;) {
739 pending = 0;
a41d1224 740 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 741 list_for_each_entry(s, &bus->stream_list, list) {
742 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 743 if (!azx_dev->irq_pending ||
7833c3f8
TI		 744 !s->substream ||
745 !s->running)
9ad593f6 746 continue;
e5463720
JK		 747 ok = azx_position_ok(chip, azx_dev);
748 if (ok > 0) {
9ad593f6 749 azx_dev->irq_pending = 0;
a41d1224 750 spin_unlock(&bus->reg_lock);
7833c3f8 751 snd_pcm_period_elapsed(s->substream);
a41d1224 752 spin_lock(&bus->reg_lock);
e5463720
JK		 753 } else if (ok < 0) {
754 pending = 0; /* too early */
9ad593f6
TI		 755 } else
756 pending++;
757 }
a41d1224 758 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 759 if (!pending)
760 return;
08af495f 761 msleep(1);
9ad593f6
TI		 762 }
763}
764
765/* clear irq_pending flags and assure no on-going workq */
766static void azx_clear_irq_pending(struct azx *chip)
767{
7833c3f8
TI		 768 struct hdac_bus *bus = azx_bus(chip);
769 struct hdac_stream *s;
9ad593f6 770
a41d1224 771 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 772 list_for_each_entry(s, &bus->stream_list, list) {
773 struct azx_dev *azx_dev = stream_to_azx_dev(s);
774 azx_dev->irq_pending = 0;
775 }
a41d1224 776 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 777}
778
68e7fffc
TI		 779static int azx_acquire_irq(struct azx *chip, int do_disconnect)
780{
a41d1224
TI		 781 struct hdac_bus *bus = azx_bus(chip);
782
437a5a46
TI		 783 if (request_irq(chip->pci->irq, azx_interrupt,
784 chip->msi ? 0 : IRQF_SHARED,
de65360b 785 chip->card->irq_descr, chip)) {
4e76a883
TI		 786 dev_err(chip->card->dev,
787 "unable to grab IRQ %d, disabling device\n",
788 chip->pci->irq);
68e7fffc
TI		 789 if (do_disconnect)
790 snd_card_disconnect(chip->card);
791 return -1;
792 }
a41d1224 793 bus->irq = chip->pci->irq;
69e13418 794 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 795 return 0;
796}
797
b6050ef6
TI		 798/* get the current DMA position with correction on VIA chips */
799static unsigned int azx_via_get_position(struct azx *chip,
800 struct azx_dev *azx_dev)
801{
802 unsigned int link_pos, mini_pos, bound_pos;
803 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
804 unsigned int fifo_size;
805
1604eeee 806 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 807 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 808 /* Playback, no problem using link position */
809 return link_pos;
810 }
811
812 /* Capture */
813 /* For new chipset,
814 * use mod to get the DMA position just like old chipset
815 */
7833c3f8
TI		 816 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
817 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6 818
7da20788 819 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
b6050ef6
TI		 820
821 if (azx_dev->insufficient) {
822 /* Link position never gather than FIFO size */
823 if (link_pos <= fifo_size)
824 return 0;
825
826 azx_dev->insufficient = 0;
827 }
828
829 if (link_pos <= fifo_size)
7833c3f8 830 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 831 else
832 mini_pos = link_pos - fifo_size;
833
834 /* Find nearest previous boudary */
7833c3f8
TI		 835 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
836 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 837 if (mod_link_pos >= fifo_size)
838 bound_pos = link_pos - mod_link_pos;
839 else if (mod_dma_pos >= mod_mini_pos)
840 bound_pos = mini_pos - mod_mini_pos;
841 else {
7833c3f8
TI		 842 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
843 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 844 bound_pos = 0;
845 }
846
847 /* Calculate real DMA position we want */
848 return bound_pos + mod_dma_pos;
849}
850
c02f77d3
TI		 851#define AMD_FIFO_SIZE 32
852
853/* get the current DMA position with FIFO size correction */
854static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
855{
856 struct snd_pcm_substream *substream = azx_dev->core.substream;
857 struct snd_pcm_runtime *runtime = substream->runtime;
858 unsigned int pos, delay;
859
860 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
861 if (!runtime)
862 return pos;
863
864 runtime->delay = AMD_FIFO_SIZE;
865 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
866 if (azx_dev->insufficient) {
867 if (pos < delay) {
868 delay = pos;
869 runtime->delay = bytes_to_frames(runtime, pos);
870 } else {
871 azx_dev->insufficient = 0;
872 }
873 }
874
875 /* correct the DMA position for capture stream */
876 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
877 if (pos < delay)
878 pos += azx_dev->core.bufsize;
879 pos -= delay;
880 }
881
882 return pos;
883}
884
885static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
886 unsigned int pos)
887{
888 struct snd_pcm_substream *substream = azx_dev->core.substream;
889
890 /* just read back the calculated value in the above */
891 return substream->runtime->delay;
892}
893
f87e7f25
TI		 894static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
895 struct azx_dev *azx_dev)
896{
897 return _snd_hdac_chip_readl(azx_bus(chip),
898 AZX_REG_VS_SDXDPIB_XBASE +
899 (AZX_REG_VS_SDXDPIB_XINTERVAL *
900 azx_dev->core.index));
901}
902
903/* get the current DMA position with correction on SKL+ chips */
904static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
905{
906 /* DPIB register gives a more accurate position for playback */
907 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
908 return azx_skl_get_dpib_pos(chip, azx_dev);
909
910 /* For capture, we need to read posbuf, but it requires a delay
911 * for the possible boundary overlap; the read of DPIB fetches the
912 * actual posbuf
913 */
914 udelay(20);
915 azx_skl_get_dpib_pos(chip, azx_dev);
916 return azx_get_pos_posbuf(chip, azx_dev);
917}
918
83012a7c 919#ifdef CONFIG_PM
65fcd41d
TI		 920static DEFINE_MUTEX(card_list_lock);
921static LIST_HEAD(card_list);
922
923static void azx_add_card_list(struct azx *chip)
924{
9a34af4a 925 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 926 mutex_lock(&card_list_lock);
9a34af4a 927 list_add(&hda->list, &card_list);
65fcd41d
TI		 928 mutex_unlock(&card_list_lock);
929}
930
931static void azx_del_card_list(struct azx *chip)
932{
9a34af4a 933 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 934 mutex_lock(&card_list_lock);
9a34af4a 935 list_del_init(&hda->list);
65fcd41d
TI		 936 mutex_unlock(&card_list_lock);
937}
938
939/* trigger power-save check at writing parameter */
940static int param_set_xint(const char *val, const struct kernel_param *kp)
941{
9a34af4a 942 struct hda_intel *hda;
65fcd41d 943 struct azx *chip;
65fcd41d
TI		 944 int prev = power_save;
945 int ret = param_set_int(val, kp);
946
947 if (ret || prev == power_save)
948 return ret;
949
950 mutex_lock(&card_list_lock);
9a34af4a
TI		 951 list_for_each_entry(hda, &card_list, list) {
952 chip = &hda->chip;
a41d1224 953 if (!hda->probe_continued || chip->disabled)
65fcd41d 954 continue;
a41d1224 955 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 956 }
957 mutex_unlock(&card_list_lock);
958 return 0;
959}
5c0b9bec 960
5c0b9bec
TI		 961/*
962 * power management
963 */
3baffc4a 964static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 965{
2d9772ef
TI		 966 struct azx *chip;
967 struct hda_intel *hda;
1da177e4 968
2d9772ef 969 if (!card)
3baffc4a 970 return false;
2d9772ef
TI		 971 chip = card->private_data;
972 hda = container_of(chip, struct hda_intel, chip);
342e8449 973 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 974 return false;
975 return true;
976}
977
978static void __azx_runtime_suspend(struct azx *chip)
979{
3baffc4a
TI		 980 azx_stop_chip(chip);
981 azx_enter_link_reset(chip);
982 azx_clear_irq_pending(chip);
e454ff8e 983 display_power(chip, false);
3baffc4a
TI		 984}
985
744c67ff 986static void __azx_runtime_resume(struct azx *chip, bool from_rt)
3baffc4a
TI		 987{
988 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
989 struct hdac_bus *bus = azx_bus(chip);
990 struct hda_codec *codec;
991 int status;
992
e454ff8e
TI		 993 display_power(chip, true);
994 if (hda->need_i915_power)
995 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 996
997 /* Read STATESTS before controller reset */
998 status = azx_readw(chip, STATESTS);
999
1000 azx_init_pci(chip);
1001 hda_intel_init_chip(chip, true);
1002
744c67ff 1003 if (status && from_rt) {
3baffc4a
TI		 1004 list_for_each_codec(codec, &chip->bus)
1005 if (status & (1 << codec->addr))
1006 schedule_delayed_work(&codec->jackpoll_work,
1007 codec->jackpoll_interval);
1008 }
1009
1010 /* power down again for link-controlled chips */
e454ff8e 1011 if (!hda->need_i915_power)
029d92c2 1012 display_power(chip, false);
3baffc4a
TI		 1013}
1014
1015#ifdef CONFIG_PM_SLEEP
1016static int azx_suspend(struct device *dev)
1017{
1018 struct snd_card *card = dev_get_drvdata(dev);
1019 struct azx *chip;
1020 struct hdac_bus *bus;
1021
1022 if (!azx_is_pm_ready(card))
c5c21523
TI		 1023 return 0;
1024
3baffc4a 1025 chip = card->private_data;
a41d1224 1026 bus = azx_bus(chip);
421a1252 1027 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3baffc4a 1028 __azx_runtime_suspend(chip);
a41d1224
TI		 1029 if (bus->irq >= 0) {
1030 free_irq(bus->irq, chip);
1031 bus->irq = -1;
30b35399 1032 }
a07187c9 1033
68e7fffc 1034 if (chip->msi)
43001c95 1035 pci_disable_msi(chip->pci);
785d8c4b
LY		 1036
1037 trace_azx_suspend(chip);
1da177e4
LT		 1038 return 0;
1039}
1040
68cb2b55 1041static int azx_resume(struct device *dev)
1da177e4 1042{
68cb2b55 1043 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1044 struct azx *chip;
2d9772ef 1045
3baffc4a 1046 if (!azx_is_pm_ready(card))
2d9772ef 1047 return 0;
1da177e4 1048
2d9772ef 1049 chip = card->private_data;
68e7fffc 1050 if (chip->msi)
3baffc4a 1051 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1052 chip->msi = 0;
1053 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1054 return -EIO;
744c67ff 1055 __azx_runtime_resume(chip, false);
421a1252 1056 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1057
1058 trace_azx_resume(chip);
1da177e4
LT		 1059 return 0;
1060}
b8dfc462 1061
3e6db33a
XZ		 1062/* put codec down to D3 at hibernation for Intel SKL+;
1063 * otherwise BIOS may still access the codec and screw up the driver
1064 */
3e6db33a
XZ		 1065static int azx_freeze_noirq(struct device *dev)
1066{
a4b4793f
TI		 1067 struct snd_card *card = dev_get_drvdata(dev);
1068 struct azx *chip = card->private_data;
3e6db33a
XZ		 1069 struct pci_dev *pci = to_pci_dev(dev);
1070
a4b4793f 1071 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1072 pci_set_power_state(pci, PCI_D3hot);
1073
1074 return 0;
1075}
1076
1077static int azx_thaw_noirq(struct device *dev)
1078{
a4b4793f
TI		 1079 struct snd_card *card = dev_get_drvdata(dev);
1080 struct azx *chip = card->private_data;
3e6db33a
XZ		 1081 struct pci_dev *pci = to_pci_dev(dev);
1082
a4b4793f 1083 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1084 pci_set_power_state(pci, PCI_D0);
1085
1086 return 0;
1087}
1088#endif /* CONFIG_PM_SLEEP */
1089
b8dfc462
ML		 1090static int azx_runtime_suspend(struct device *dev)
1091{
1092 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1093 struct azx *chip;
b8dfc462 1094
3baffc4a 1095 if (!azx_is_pm_ready(card))
2d9772ef 1096 return 0;
2d9772ef 1097 chip = card->private_data;
364aa716 1098 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1099 return 0;
1100
7d4f606c
WX		 1101 /* enable controller wake up event */
1102 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1103 STATESTS_INT_MASK);
1104
3baffc4a 1105 __azx_runtime_suspend(chip);
785d8c4b 1106 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1107 return 0;
1108}
1109
1110static int azx_runtime_resume(struct device *dev)
1111{
1112 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1113 struct azx *chip;
b8dfc462 1114
3baffc4a 1115 if (!azx_is_pm_ready(card))
2d9772ef 1116 return 0;
2d9772ef 1117 chip = card->private_data;
364aa716 1118 if (!azx_has_pm_runtime(chip))
246efa4a 1119 return 0;
744c67ff 1120 __azx_runtime_resume(chip, true);
7d4f606c
WX		 1121
1122 /* disable controller Wake Up event*/
1123 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1124 ~STATESTS_INT_MASK);
1125
785d8c4b 1126 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1127 return 0;
1128}
6eb827d2
TI		 1129
1130static int azx_runtime_idle(struct device *dev)
1131{
1132 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1133 struct azx *chip;
1134 struct hda_intel *hda;
1135
1136 if (!card)
1137 return 0;
6eb827d2 1138
2d9772ef
TI		 1139 chip = card->private_data;
1140 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1141 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1142 return 0;
1143
55ed9cd1 1144 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1145 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1146 return -EBUSY;
1147
37a3a98e 1148 /* ELD notification gets broken when HD-audio bus is off */
dd23e1d5 1149 if (needs_eld_notify_link(chip))
37a3a98e
TI		 1150 return -EBUSY;
1151
6eb827d2
TI		 1152 return 0;
1153}
1154
b8dfc462
ML		 1155static const struct dev_pm_ops azx_pm = {
1156 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1157#ifdef CONFIG_PM_SLEEP
1158 .freeze_noirq = azx_freeze_noirq,
1159 .thaw_noirq = azx_thaw_noirq,
1160#endif
6eb827d2 1161 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1162};
1163
68cb2b55
TI		 1164#define AZX_PM_OPS &azx_pm
1165#else
3baffc4a
TI		 1166#define azx_add_card_list(chip) /* NOP */
1167#define azx_del_card_list(chip) /* NOP */
68cb2b55 1168#define AZX_PM_OPS NULL
b8dfc462 1169#endif /* CONFIG_PM */
1da177e4
LT		 1170
1171
48c8b0eb 1172static int azx_probe_continue(struct azx *chip);
a82d51ed 1173
8393ec4a 1174#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1175static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1176
a82d51ed
TI		 1177static void azx_vs_set_state(struct pci_dev *pci,
1178 enum vga_switcheroo_state state)
1179{
1180 struct snd_card *card = pci_get_drvdata(pci);
1181 struct azx *chip = card->private_data;
9a34af4a 1182 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1183 struct hda_codec *codec;
a82d51ed
TI		 1184 bool disabled;
1185
9a34af4a
TI		 1186 wait_for_completion(&hda->probe_wait);
1187 if (hda->init_failed)
a82d51ed
TI		 1188 return;
1189
1190 disabled = (state == VGA_SWITCHEROO_OFF);
1191 if (chip->disabled == disabled)
1192 return;
1193
a41d1224 1194 if (!hda->probe_continued) {
a82d51ed
TI		 1195 chip->disabled = disabled;
1196 if (!disabled) {
4e76a883
TI		 1197 dev_info(chip->card->dev,
1198 "Start delayed initialization\n");
5c90680e 1199 if (azx_probe_continue(chip) < 0) {
4e76a883 1200 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1201 hda->init_failed = true;
a82d51ed
TI		 1202 }
1203 }
1204 } else {
2b760d88 1205 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1206 disabled ? "Disabling" : "Enabling");
a82d51ed 1207 if (disabled) {
07f4f97d
LW		 1208 list_for_each_codec(codec, &chip->bus) {
1209 pm_runtime_suspend(hda_codec_dev(codec));
1210 pm_runtime_disable(hda_codec_dev(codec));
1211 }
1212 pm_runtime_suspend(card->dev);
1213 pm_runtime_disable(card->dev);
2b760d88 1214 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1215 * however we have no ACPI handle, so pci/acpi can't put us there,
1216 * put ourselves there */
1217 pci->current_state = PCI_D3cold;
a82d51ed 1218 chip->disabled = true;
a41d1224 1219 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1220 dev_warn(chip->card->dev,
1221 "Cannot lock devices!\n");
a82d51ed 1222 } else {
a41d1224 1223 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1224 chip->disabled = false;
07f4f97d
LW		 1225 pm_runtime_enable(card->dev);
1226 list_for_each_codec(codec, &chip->bus) {
1227 pm_runtime_enable(hda_codec_dev(codec));
1228 pm_runtime_resume(hda_codec_dev(codec));
1229 }
a82d51ed
TI		 1230 }
1231 }
1232}
1233
1234static bool azx_vs_can_switch(struct pci_dev *pci)
1235{
1236 struct snd_card *card = pci_get_drvdata(pci);
1237 struct azx *chip = card->private_data;
9a34af4a 1238 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1239
9a34af4a
TI		 1240 wait_for_completion(&hda->probe_wait);
1241 if (hda->init_failed)
a82d51ed 1242 return false;
a41d1224 1243 if (chip->disabled || !hda->probe_continued)
a82d51ed 1244 return true;
a41d1224 1245 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1246 return false;
a41d1224 1247 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1248 return true;
1249}
1250
37a3a98e
TI		 1251/*
1252 * The discrete GPU cannot power down unless the HDA controller runtime
1253 * suspends, so activate runtime PM on codecs even if power_save == 0.
1254 */
1255static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1256{
1257 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1258 struct hda_codec *codec;
1259
dd23e1d5 1260 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
37a3a98e
TI		 1261 list_for_each_codec(codec, &chip->bus)
1262 codec->auto_runtime_pm = 1;
1263 /* reset the power save setup */
1264 if (chip->running)
1265 set_default_power_save(chip);
1266 }
1267}
1268
1269static void azx_vs_gpu_bound(struct pci_dev *pci,
1270 enum vga_switcheroo_client_id client_id)
1271{
1272 struct snd_card *card = pci_get_drvdata(pci);
1273 struct azx *chip = card->private_data;
37a3a98e
TI		 1274
1275 if (client_id == VGA_SWITCHEROO_DIS)
dd23e1d5 1276 chip->bus.keep_power = 0;
37a3a98e
TI		 1277 setup_vga_switcheroo_runtime_pm(chip);
1278}
1279
e23e7a14 1280static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1281{
9a34af4a 1282 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1283 struct pci_dev *p = get_bound_vga(chip->pci);
bacd8614 1284 struct pci_dev *parent;
a82d51ed 1285 if (p) {
4e76a883 1286 dev_info(chip->card->dev,
2b760d88 1287 "Handle vga_switcheroo audio client\n");
9a34af4a 1288 hda->use_vga_switcheroo = 1;
bacd8614
KHF		 1289
1290 /* cleared in either gpu_bound op or codec probe, or when its
1291 * upstream port has _PR3 (i.e. dGPU).
1292 */
1293 parent = pci_upstream_bridge(p);
1294 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
07f4f97d 1295 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1296 pci_dev_put(p);
1297 }
1298}
1299
1300static const struct vga_switcheroo_client_ops azx_vs_ops = {
1301 .set_gpu_state = azx_vs_set_state,
1302 .can_switch = azx_vs_can_switch,
37a3a98e 1303 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1304};
1305
e23e7a14 1306static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1307{
9a34af4a 1308 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1309 struct pci_dev *p;
128960a9
TI		 1310 int err;
1311
9a34af4a 1312 if (!hda->use_vga_switcheroo)
a82d51ed 1313 return 0;
4aaf448f
JQ		 1314
1315 p = get_bound_vga(chip->pci);
1316 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1317 pci_dev_put(p);
1318
128960a9
TI		 1319 if (err < 0)
1320 return err;
9a34af4a 1321 hda->vga_switcheroo_registered = 1;
246efa4a 1322
128960a9 1323 return 0;
a82d51ed
TI		 1324}
1325#else
1326#define init_vga_switcheroo(chip) /* NOP */
1327#define register_vga_switcheroo(chip) 0
8393ec4a 1328#define check_hdmi_disabled(pci) false
37a3a98e 1329#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1330#endif /* SUPPORT_VGA_SWITCHER */
1331
1da177e4
LT		 1332/*
1333 * destructor
1334 */
a98f90fd 1335static int azx_free(struct azx *chip)
1da177e4 1336{
c67e2228 1337 struct pci_dev *pci = chip->pci;
a07187c9 1338 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1339 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1340
364aa716 1341 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228 1342 pm_runtime_get_noresume(&pci->dev);
37a3a98e 1343 chip->running = 0;
c67e2228 1344
65fcd41d
TI		 1345 azx_del_card_list(chip);
1346
9a34af4a
TI		 1347 hda->init_failed = 1; /* to be sure */
1348 complete_all(&hda->probe_wait);
f4c482a4 1349
9a34af4a 1350 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1351 if (chip->disabled && hda->probe_continued)
1352 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1353 if (hda->vga_switcheroo_registered)
128960a9 1354 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1355 }
1356
a41d1224 1357 if (bus->chip_init) {
9ad593f6 1358 azx_clear_irq_pending(chip);
7833c3f8 1359 azx_stop_all_streams(chip);
1a7f60b9 1360 azx_stop_chip(chip);
1da177e4
LT		 1361 }
1362
a41d1224
TI		 1363 if (bus->irq >= 0)
1364 free_irq(bus->irq, (void*)chip);
68e7fffc 1365 if (chip->msi)
30b35399 1366 pci_disable_msi(chip->pci);
a41d1224 1367 iounmap(bus->remap_addr);
1da177e4 1368
67908994 1369 azx_free_stream_pages(chip);
a41d1224
TI		 1370 azx_free_streams(chip);
1371 snd_hdac_bus_exit(bus);
1372
a82d51ed
TI		 1373 if (chip->region_requested)
1374 pci_release_regions(chip->pci);
a41d1224 1375
1da177e4 1376 pci_disable_device(chip->pci);
4918cdab 1377#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1378 release_firmware(chip->fw);
4918cdab 1379#endif
e454ff8e 1380 display_power(chip, false);
98d8fc6c 1381
fc18282c 1382 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1383 snd_hdac_i915_exit(bus);
a07187c9 1384 kfree(hda);
1da177e4
LT		 1385
1386 return 0;
1387}
1388
a41d1224
TI		 1389static int azx_dev_disconnect(struct snd_device *device)
1390{
1391 struct azx *chip = device->device_data;
ca58f551 1392 struct hdac_bus *bus = azx_bus(chip);
a41d1224
TI		 1393
1394 chip->bus.shutdown = 1;
ca58f551
TI		 1395 cancel_work_sync(&bus->unsol_work);
1396
a41d1224
TI		 1397 return 0;
1398}
1399
a98f90fd 1400static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1401{
1402 return azx_free(device->device_data);
1403}
1404
8393ec4a 1405#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1406/*
2b760d88 1407 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1408 */
e23e7a14 1409static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1410{
1411 struct pci_dev *p;
1412
1413 /* check only discrete GPU */
1414 switch (pci->vendor) {
1415 case PCI_VENDOR_ID_ATI:
1416 case PCI_VENDOR_ID_AMD:
1417 case PCI_VENDOR_ID_NVIDIA:
1418 if (pci->devfn == 1) {
1419 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1420 pci->bus->number, 0);
1421 if (p) {
b6d7b362 1422 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1423 return p;
1424 pci_dev_put(p);
1425 }
1426 }
1427 break;
1428 }
1429 return NULL;
1430}
1431
e23e7a14 1432static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1433{
1434 bool vga_inactive = false;
1435 struct pci_dev *p = get_bound_vga(pci);
1436
1437 if (p) {
12b78a7f 1438 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1439 vga_inactive = true;
1440 pci_dev_put(p);
1441 }
1442 return vga_inactive;
1443}
8393ec4a 1444#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1445
3372a153
TI		 1446/*
1447 * white/black-listing for position_fix
1448 */
e23e7a14 1449static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1450 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1451 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1452 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1453 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1454 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1455 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1456 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1457 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1458 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1459 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1460 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1461 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1462 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1463 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1464 {}
1465};
1466
e23e7a14 1467static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1468{
1469 const struct snd_pci_quirk *q;
1470
c673ba1c 1471 switch (fix) {
1dac6695 1472 case POS_FIX_AUTO:
c673ba1c
TI		 1473 case POS_FIX_LPIB:
1474 case POS_FIX_POSBUF:
4cb36310 1475 case POS_FIX_VIACOMBO:
a6f2fd55 1476 case POS_FIX_COMBO:
f87e7f25 1477 case POS_FIX_SKL:
c02f77d3 1478 case POS_FIX_FIFO:
c673ba1c
TI		 1479 return fix;
1480 }
1481
c673ba1c
TI		 1482 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1483 if (q) {
4e76a883
TI		 1484 dev_info(chip->card->dev,
1485 "position_fix set to %d for device %04x:%04x\n",
1486 q->value, q->subvendor, q->subdevice);
c673ba1c 1487 return q->value;
3372a153 1488 }
bdd9ef24
DH		 1489
1490 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1491 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1492 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1493 return POS_FIX_VIACOMBO;
9477c58e 1494 }
c02f77d3
TI		 1495 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1496 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1497 return POS_FIX_FIFO;
1498 }
9477c58e 1499 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1500 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1501 return POS_FIX_LPIB;
bdd9ef24 1502 }
a4b4793f 1503 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1504 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1505 return POS_FIX_SKL;
1506 }
c673ba1c 1507 return POS_FIX_AUTO;
3372a153
TI		 1508}
1509
b6050ef6
TI		 1510static void assign_position_fix(struct azx *chip, int fix)
1511{
1512 static azx_get_pos_callback_t callbacks[] = {
1513 [POS_FIX_AUTO] = NULL,
1514 [POS_FIX_LPIB] = azx_get_pos_lpib,
1515 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1516 [POS_FIX_VIACOMBO] = azx_via_get_position,
1517 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1518 [POS_FIX_SKL] = azx_get_pos_skl,
c02f77d3 1519 [POS_FIX_FIFO] = azx_get_pos_fifo,
b6050ef6
TI		 1520 };
1521
1522 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1523
1524 /* combo mode uses LPIB only for playback */
1525 if (fix == POS_FIX_COMBO)
1526 chip->get_position[1] = NULL;
1527
f87e7f25 1528 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1529 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1530 chip->get_delay[0] = chip->get_delay[1] =
1531 azx_get_delay_from_lpib;
1532 }
1533
c02f77d3
TI		 1534 if (fix == POS_FIX_FIFO)
1535 chip->get_delay[0] = chip->get_delay[1] =
1536 azx_get_delay_from_fifo;
b6050ef6
TI		 1537}
1538
669ba27a
TI		 1539/*
1540 * black-lists for probe_mask
1541 */
e23e7a14 1542static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1543 /* Thinkpad often breaks the controller communication when accessing
1544 * to the non-working (or non-existing) modem codec slot.
1545 */
1546 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1547 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1548 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1549 /* broken BIOS */
1550 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1551 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1552 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1553 /* forced codec slots */
93574844 1554 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1555 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1556 /* WinFast VP200 H (Teradici) user reported broken communication */
1557 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1558 {}
1559};
1560
f1eaaeec
TI		 1561#define AZX_FORCE_CODEC_MASK 0x100
1562
e23e7a14 1563static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1564{
1565 const struct snd_pci_quirk *q;
1566
f1eaaeec
TI		 1567 chip->codec_probe_mask = probe_mask[dev];
1568 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1569 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1570 if (q) {
4e76a883
TI		 1571 dev_info(chip->card->dev,
1572 "probe_mask set to 0x%x for device %04x:%04x\n",
1573 q->value, q->subvendor, q->subdevice);
f1eaaeec 1574 chip->codec_probe_mask = q->value;
669ba27a
TI		 1575 }
1576 }
f1eaaeec
TI		 1577
1578 /* check forced option */
1579 if (chip->codec_probe_mask != -1 &&
1580 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1581 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1582 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1583 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1584 }
669ba27a
TI		 1585}
1586
4d8e22e0 1587/*
71623855 1588 * white/black-list for enable_msi
4d8e22e0 1589 */
e23e7a14 1590static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1591 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1592 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1593 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1594 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1595 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1596 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1597 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1598 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1599 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1600 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1601 {}
1602};
1603
e23e7a14 1604static void check_msi(struct azx *chip)
4d8e22e0
TI		 1605{
1606 const struct snd_pci_quirk *q;
1607
71623855
TI		 1608 if (enable_msi >= 0) {
1609 chip->msi = !!enable_msi;
4d8e22e0 1610 return;
71623855
TI		 1611 }
1612 chip->msi = 1; /* enable MSI as default */
1613 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1614 if (q) {
4e76a883
TI		 1615 dev_info(chip->card->dev,
1616 "msi for device %04x:%04x set to %d\n",
1617 q->subvendor, q->subdevice, q->value);
4d8e22e0 1618 chip->msi = q->value;
80c43ed7
TI		 1619 return;
1620 }
1621
1622 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1623 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1624 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1625 chip->msi = 0;
4d8e22e0
TI		 1626 }
1627}
1628
a1585d76 1629/* check the snoop mode availability */
e23e7a14 1630static void azx_check_snoop_available(struct azx *chip)
a1585d76 1631{
7c732015 1632 int snoop = hda_snoop;
a1585d76 1633
7c732015
TI		 1634 if (snoop >= 0) {
1635 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1636 snoop ? "snoop" : "non-snoop");
1637 chip->snoop = snoop;
78c9be61 1638 chip->uc_buffer = !snoop;
7c732015
TI		 1639 return;
1640 }
1641
1642 snoop = true;
37e661ee
TI		 1643 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1644 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1645 /* force to non-snoop mode for a new VIA controller
1646 * when BIOS is set
1647 */
7c732015
TI		 1648 u8 val;
1649 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1650 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1651 chip->pci->revision == 0x20))
7c732015 1652 snoop = false;
a1585d76
TI		 1653 }
1654
37e661ee
TI		 1655 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1656 snoop = false;
1657
7c732015 1658 chip->snoop = snoop;
78c9be61 1659 if (!snoop) {
7c732015 1660 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1661 /* C-Media requires non-cached pages only for CORB/RIRB */
1662 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1663 chip->uc_buffer = true;
1664 }
a1585d76 1665}
669ba27a 1666
99a2008d
WX		 1667static void azx_probe_work(struct work_struct *work)
1668{
9a34af4a
TI		 1669 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1670 azx_probe_continue(&hda->chip);
99a2008d 1671}
99a2008d 1672
4f0189be
TI		 1673static int default_bdl_pos_adj(struct azx *chip)
1674{
2cf721db
TI		 1675 /* some exceptions: Atoms seem problematic with value 1 */
1676 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1677 switch (chip->pci->device) {
1678 case 0x0f04: /* Baytrail */
1679 case 0x2284: /* Braswell */
1680 return 32;
1681 }
1682 }
1683
4f0189be
TI		 1684 switch (chip->driver_type) {
1685 case AZX_DRIVER_ICH:
1686 case AZX_DRIVER_PCH:
1687 return 1;
1688 default:
1689 return 32;
1690 }
1691}
1692
1da177e4
LT		 1693/*
1694 * constructor
1695 */
a43ff5ba
TI		 1696static const struct hda_controller_ops pci_hda_ops;
1697
e23e7a14
BP		 1698static int azx_create(struct snd_card *card, struct pci_dev *pci,
1699 int dev, unsigned int driver_caps,
1700 struct azx **rchip)
1da177e4 1701{
a98f90fd 1702 static struct snd_device_ops ops = {
a41d1224 1703 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1704 .dev_free = azx_dev_free,
1705 };
a07187c9 1706 struct hda_intel *hda;
a82d51ed
TI		 1707 struct azx *chip;
1708 int err;
1da177e4
LT		 1709
1710 *rchip = NULL;
bcd72003 1711
927fc866
PM		 1712 err = pci_enable_device(pci);
1713 if (err < 0)
1da177e4
LT		 1714 return err;
1715
a07187c9
ML		 1716 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1717 if (!hda) {
1da177e4
LT		 1718 pci_disable_device(pci);
1719 return -ENOMEM;
1720 }
1721
a07187c9 1722 chip = &hda->chip;
62932df8 1723 mutex_init(&chip->open_mutex);
1da177e4
LT		 1724 chip->card = card;
1725 chip->pci = pci;
a43ff5ba 1726 chip->ops = &pci_hda_ops;
9477c58e
TI		 1727 chip->driver_caps = driver_caps;
1728 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1729 check_msi(chip);
555e219f 1730 chip->dev_index = dev;
3a182c84
TI		 1731 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1732 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1733 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1734 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1735 INIT_LIST_HEAD(&hda->list);
a82d51ed 1736 init_vga_switcheroo(chip);
9a34af4a 1737 init_completion(&hda->probe_wait);
1da177e4 1738
b6050ef6 1739 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1740
5aba4f8e 1741 check_probe_mask(chip, dev);
3372a153 1742
41438f13
TI		 1743 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1744 chip->fallback_to_single_cmd = 1;
1745 else /* explicitly set to single_cmd or not */
1746 chip->single_cmd = single_cmd;
1747
a1585d76 1748 azx_check_snoop_available(chip);
c74db86b 1749
4f0189be
TI		 1750 if (bdl_pos_adj[dev] < 0)
1751 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1752 else
1753 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1754
19abfefd 1755 err = azx_bus_init(chip, model[dev]);
a41d1224
TI		 1756 if (err < 0) {
1757 kfree(hda);
1758 pci_disable_device(pci);
1759 return err;
1760 }
1761
619a1f19
TI		 1762 /* use the non-cached pages in non-snoop mode */
1763 if (!azx_snoop(chip))
1764 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1765
bd2956e4
BL		 1766 /* Workaround for a communication error on CFL (bko#199007) and CNL */
1767 if (IS_CFL(pci) || IS_CNL(pci))
8af42130 1768 azx_bus(chip)->polling_mode = 1;
bd2956e4 1769
7d9a1808
TI		 1770 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1771 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1772 chip->bus.needs_damn_long_delay = 1;
1773 }
1774
a82d51ed
TI		 1775 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1776 if (err < 0) {
4e76a883 1777 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1778 azx_free(chip);
1779 return err;
1780 }
1781
99a2008d 1782 /* continue probing in work context as may trigger request module */
9a34af4a 1783 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1784
a82d51ed 1785 *rchip = chip;
99a2008d 1786
a82d51ed
TI		 1787 return 0;
1788}
1789
48c8b0eb 1790static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1791{
1792 int dev = chip->dev_index;
1793 struct pci_dev *pci = chip->pci;
1794 struct snd_card *card = chip->card;
a41d1224 1795 struct hdac_bus *bus = azx_bus(chip);
67908994 1796 int err;
a82d51ed 1797 unsigned short gcap;
413cbf46 1798 unsigned int dma_bits = 64;
a82d51ed 1799
07e4ca50
TI		 1800#if BITS_PER_LONG != 64
1801 /* Fix up base address on ULI M5461 */
1802 if (chip->driver_type == AZX_DRIVER_ULI) {
1803 u16 tmp3;
1804 pci_read_config_word(pci, 0x40, &tmp3);
1805 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1806 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1807 }
1808#endif
1809
927fc866 1810 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1811 if (err < 0)
1da177e4 1812 return err;
a82d51ed 1813 chip->region_requested = 1;
1da177e4 1814
a41d1224
TI		 1815 bus->addr = pci_resource_start(pci, 0);
1816 bus->remap_addr = pci_ioremap_bar(pci, 0);
1817 if (bus->remap_addr == NULL) {
4e76a883 1818 dev_err(card->dev, "ioremap error\n");
a82d51ed 1819 return -ENXIO;
1da177e4
LT		 1820 }
1821
a4b4793f 1822 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1823 snd_hdac_bus_parse_capabilities(bus);
1824
1825 /*
1826 * Some Intel CPUs has always running timer (ART) feature and
1827 * controller may have Global time sync reporting capability, so
1828 * check both of these before declaring synchronized time reporting
1829 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1830 */
1831 chip->gts_present = false;
1832
1833#ifdef CONFIG_X86
1834 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1835 chip->gts_present = true;
1836#endif
1837
db79afa1
BH		 1838 if (chip->msi) {
1839 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1840 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1841 pci->no_64bit_msi = true;
1842 }
68e7fffc
TI		 1843 if (pci_enable_msi(pci) < 0)
1844 chip->msi = 0;
db79afa1 1845 }
7376d013 1846
1da177e4 1847 pci_set_master(pci);
a41d1224 1848 synchronize_irq(bus->irq);
1da177e4 1849
bcd72003 1850 gcap = azx_readw(chip, GCAP);
4e76a883 1851 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1852
413cbf46
TI		 1853 /* AMD devices support 40 or 48bit DMA, take the safe one */
1854 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1855 dma_bits = 40;
1856
dc4c2e6b 1857 /* disable SB600 64bit support for safety */
9477c58e 1858 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1859 struct pci_dev *p_smbus;
413cbf46 1860 dma_bits = 40;
dc4c2e6b
AB		 1861 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1862 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1863 NULL);
1864 if (p_smbus) {
1865 if (p_smbus->revision < 0x30)
fb1d8ac2 1866 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1867 pci_dev_put(p_smbus);
1868 }
1869 }
09240cf4 1870
3ab7511e
AB		 1871 /* NVidia hardware normally only supports up to 40 bits of DMA */
1872 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1873 dma_bits = 40;
1874
9477c58e
TI		 1875 /* disable 64bit DMA address on some devices */
1876 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1877 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1878 gcap &= ~AZX_GCAP_64OK;
9477c58e 1879 }
396087ea 1880
2ae66c26 1881 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1882 if (align_buffer_size >= 0)
1883 chip->align_buffer_size = !!align_buffer_size;
1884 else {
103884a3 1885 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1886 chip->align_buffer_size = 0;
7bfe059e
TI		 1887 else
1888 chip->align_buffer_size = 1;
1889 }
2ae66c26 1890
cf7aaca8 1891 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1892 if (!(gcap & AZX_GCAP_64OK))
1893 dma_bits = 32;
412b979c
QL		 1894 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1895 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1896 } else {
412b979c
QL		 1897 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1898 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1899 }
cf7aaca8 1900
8b6ed8e7
TI		 1901 /* read number of streams from GCAP register instead of using
1902 * hardcoded value
1903 */
1904 chip->capture_streams = (gcap >> 8) & 0x0f;
1905 chip->playback_streams = (gcap >> 12) & 0x0f;
1906 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1907 /* gcap didn't give any info, switching to old method */
1908
1909 switch (chip->driver_type) {
1910 case AZX_DRIVER_ULI:
1911 chip->playback_streams = ULI_NUM_PLAYBACK;
1912 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1913 break;
1914 case AZX_DRIVER_ATIHDMI:
1815b34a 1915 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1916 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1917 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1918 break;
c4da29ca 1919 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1920 default:
1921 chip->playback_streams = ICH6_NUM_PLAYBACK;
1922 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1923 break;
1924 }
07e4ca50 1925 }
8b6ed8e7
TI		 1926 chip->capture_index_offset = 0;
1927 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1928 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1929
df56c3db
JK		 1930 /* sanity check for the SDxCTL.STRM field overflow */
1931 if (chip->num_streams > 15 &&
1932 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1933 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1934 "forcing separate stream tags", chip->num_streams);
1935 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1936 }
1937
a41d1224
TI		 1938 /* initialize streams */
1939 err = azx_init_streams(chip);
81740861 1940 if (err < 0)
a82d51ed 1941 return err;
1da177e4 1942
a41d1224
TI		 1943 err = azx_alloc_stream_pages(chip);
1944 if (err < 0)
1945 return err;
1da177e4
LT		 1946
1947 /* initialize chip */
cb53c626 1948 azx_init_pci(chip);
e4d9e513 1949
e454ff8e 1950 snd_hdac_i915_set_bclk(bus);
e4d9e513 1951
0a673521 1952 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1953
1954 /* codec detection */
a41d1224 1955 if (!azx_bus(chip)->codec_mask) {
4e76a883 1956 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1957 return -ENODEV;
1da177e4
LT		 1958 }
1959
f495222e
TI		 1960 if (azx_acquire_irq(chip, 0) < 0)
1961 return -EBUSY;
1962
07e4ca50 1963 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1964 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1965 sizeof(card->shortname));
1966 snprintf(card->longname, sizeof(card->longname),
1967 "%s at 0x%lx irq %i",
a41d1224 1968 card->shortname, bus->addr, bus->irq);
07e4ca50 1969
1da177e4 1970 return 0;
1da177e4
LT		 1971}
1972
97c6a3d1 1973#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1974/* callback from request_firmware_nowait() */
1975static void azx_firmware_cb(const struct firmware *fw, void *context)
1976{
1977 struct snd_card *card = context;
1978 struct azx *chip = card->private_data;
1979 struct pci_dev *pci = chip->pci;
1980
1981 if (!fw) {
4e76a883 1982 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1983 goto error;
1984 }
1985
1986 chip->fw = fw;
1987 if (!chip->disabled) {
1988 /* continue probing */
1989 if (azx_probe_continue(chip))
1990 goto error;
1991 }
1992 return; /* OK */
1993
1994 error:
1995 snd_card_free(card);
1996 pci_set_drvdata(pci, NULL);
1997}
97c6a3d1 1998#endif
5cb543db 1999
f46ea609
DR		 2000static int disable_msi_reset_irq(struct azx *chip)
2001{
a41d1224 2002 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2003 int err;
2004
a41d1224
TI		 2005 free_irq(bus->irq, chip);
2006 bus->irq = -1;
f46ea609
DR		 2007 pci_disable_msi(chip->pci);
2008 chip->msi = 0;
2009 err = azx_acquire_irq(chip, 1);
2010 if (err < 0)
2011 return err;
2012
2013 return 0;
2014}
2015
8769b278
DR		 2016static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2017 struct vm_area_struct *area)
2018{
2019#ifdef CONFIG_X86
2020 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2021 struct azx *chip = apcm->chip;
78c9be61 2022 if (chip->uc_buffer)
8769b278
DR		 2023 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2024#endif
2025}
2026
a43ff5ba
TI		 2027static const struct hda_controller_ops pci_hda_ops = {
2028 .disable_msi_reset_irq = disable_msi_reset_irq,
8769b278 2029 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2030 .position_check = azx_position_check,
40830813
DR		 2031};
2032
e23e7a14
BP		 2033static int azx_probe(struct pci_dev *pci,
2034 const struct pci_device_id *pci_id)
1da177e4 2035{
5aba4f8e 2036 static int dev;
a98f90fd 2037 struct snd_card *card;
9a34af4a 2038 struct hda_intel *hda;
a98f90fd 2039 struct azx *chip;
aad730d0 2040 bool schedule_probe;
927fc866 2041 int err;
1da177e4 2042
5aba4f8e
TI		 2043 if (dev >= SNDRV_CARDS)
2044 return -ENODEV;
2045 if (!enable[dev]) {
2046 dev++;
2047 return -ENOENT;
2048 }
2049
82d9d54a
JK		 2050 /*
2051 * stop probe if another Intel's DSP driver should be activated
2052 */
2053 if (dsp_driver) {
2054 err = snd_intel_dsp_driver_probe(pci);
2055 if (err != SND_INTEL_DSP_DRIVER_ANY &&
2056 err != SND_INTEL_DSP_DRIVER_LEGACY)
2057 return -ENODEV;
2058 }
2059
60c5772b
TI		 2060 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2061 0, &card);
e58de7ba 2062 if (err < 0) {
4e76a883 2063 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2064 return err;
1da177e4
LT		 2065 }
2066
a43ff5ba 2067 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2068 if (err < 0)
2069 goto out_free;
421a1252 2070 card->private_data = chip;
9a34af4a 2071 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2072
2073 pci_set_drvdata(pci, card);
2074
2075 err = register_vga_switcheroo(chip);
2076 if (err < 0) {
2b760d88 2077 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2078 goto out_free;
2079 }
2080
2081 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2082 dev_info(card->dev, "VGA controller is disabled\n");
2083 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2084 chip->disabled = true;
2085 }
2086
aad730d0 2087 schedule_probe = !chip->disabled;
1da177e4 2088
4918cdab
TI		 2089#ifdef CONFIG_SND_HDA_PATCH_LOADER
2090 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2091 dev_info(card->dev, "Applying patch firmware '%s'\n",
2092 patch[dev]);
5cb543db
TI		 2093 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2094 &pci->dev, GFP_KERNEL, card,
2095 azx_firmware_cb);
4918cdab
TI		 2096 if (err < 0)
2097 goto out_free;
aad730d0 2098 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2099 }
2100#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2101
aad730d0 2102#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2103 if (CONTROLLER_IN_GPU(pci))
2104 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2105#endif
99a2008d 2106
aad730d0 2107 if (schedule_probe)
9a34af4a 2108 schedule_work(&hda->probe_work);
a82d51ed 2109
a82d51ed 2110 dev++;
88d071fc 2111 if (chip->disabled)
9a34af4a 2112 complete_all(&hda->probe_wait);
a82d51ed
TI		 2113 return 0;
2114
2115out_free:
2116 snd_card_free(card);
2117 return err;
2118}
2119
1ba8f9d3
HG		 2120#ifdef CONFIG_PM
2121/* On some boards setting power_save to a non 0 value leads to clicking /
2122 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2123 * figure out how to avoid these sounds, but that is not always feasible.
2124 * So we keep a list of devices where we disable powersaving as its known
2125 * to causes problems on these devices.
2126 */
2127static struct snd_pci_quirk power_save_blacklist[] = {
2128 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2129 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2130 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2131 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2132 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2133 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2134 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2135 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
b529ef24
HG		 2136 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2137 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
38d9c12c 2138 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2139 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2140 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2141 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2142 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2143 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2144 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2145 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2146 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2147 /* https://bugs.launchpad.net/bugs/1821663 */
2148 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2149 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2150 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2151 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2152 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
721f1e6c
JK		 2153 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2154 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2155 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2156 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2157 /* https://bugs.launchpad.net/bugs/1821663 */
2158 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
1ba8f9d3
HG		 2159 {}
2160};
2161#endif /* CONFIG_PM */
2162
37a3a98e
TI		 2163static void set_default_power_save(struct azx *chip)
2164{
2165 int val = power_save;
2166
2167#ifdef CONFIG_PM
2168 if (pm_blacklist) {
2169 const struct snd_pci_quirk *q;
2170
2171 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2172 if (q && val) {
2173 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2174 q->subvendor, q->subdevice);
2175 val = 0;
2176 }
2177 }
2178#endif /* CONFIG_PM */
2179 snd_hda_set_power_save(&chip->bus, val * 1000);
2180}
2181
e62a42ae
DR		 2182/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2183static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2184 [AZX_DRIVER_NVIDIA] = 8,
2185 [AZX_DRIVER_TERA] = 1,
2186};
2187
48c8b0eb 2188static int azx_probe_continue(struct azx *chip)
a82d51ed 2189{
9a34af4a 2190 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2191 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2192 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2193 int dev = chip->dev_index;
2194 int err;
2195
305a0ade 2196 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2197 hda->probe_continued = 1;
795614dd 2198
fcc88d91 2199 /* bind with i915 if needed */
dba9b7b6 2200 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2201 err = snd_hdac_i915_init(bus);
535115b5
TI		 2202 if (err < 0) {
2203 /* if the controller is bound only with HDMI/DP
2204 * (for HSW and BDW), we need to abort the probe;
2205 * for other chips, still continue probing as other
2206 * codecs can be on the same link.
2207 */
bed2e98e
TI		 2208 if (CONTROLLER_IN_GPU(pci)) {
2209 dev_err(chip->card->dev,
2210 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2211 goto out_free;
fcc88d91
TI		 2212 } else {
2213 /* don't bother any longer */
e454ff8e 2214 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
fcc88d91 2215 }
535115b5 2216 }
e454ff8e
TI		 2217
2218 /* HSW/BDW controllers need this power */
2219 if (CONTROLLER_IN_GPU(pci))
2220 hda->need_i915_power = 1;
fcc88d91
TI		 2221 }
2222
2223 /* Request display power well for the HDA controller or codec. For
2224 * Haswell/Broadwell, both the display HDA controller and codec need
2225 * this power. For other platforms, like Baytrail/Braswell, only the
2226 * display codec needs the power and it can be released after probe.
2227 */
4f799e73 2228 display_power(chip, true);
99a2008d 2229
5c90680e
TI		 2230 err = azx_first_init(chip);
2231 if (err < 0)
2232 goto out_free;
2233
2dca0bba
JK		 2234#ifdef CONFIG_SND_HDA_INPUT_BEEP
2235 chip->beep_mode = beep_mode[dev];
2236#endif
2237
1da177e4 2238 /* create codec instances */
96d2bd6e 2239 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2240 if (err < 0)
2241 goto out_free;
96d2bd6e 2242
4ea6fbc8 2243#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2244 if (chip->fw) {
a41d1224 2245 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2246 chip->fw->data);
4ea6fbc8
TI		 2247 if (err < 0)
2248 goto out_free;
e39ae856 2249#ifndef CONFIG_PM
4918cdab
TI		 2250 release_firmware(chip->fw); /* no longer needed */
2251 chip->fw = NULL;
e39ae856 2252#endif
4ea6fbc8
TI		 2253 }
2254#endif
10e77dda 2255 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2256 err = azx_codec_configure(chip);
2257 if (err < 0)
2258 goto out_free;
2259 }
1da177e4 2260
a82d51ed 2261 err = snd_card_register(chip->card);
41dda0fd
WF		 2262 if (err < 0)
2263 goto out_free;
1da177e4 2264
37a3a98e
TI		 2265 setup_vga_switcheroo_runtime_pm(chip);
2266
cb53c626 2267 chip->running = 1;
65fcd41d 2268 azx_add_card_list(chip);
07f4f97d 2269
37a3a98e 2270 set_default_power_save(chip);
07f4f97d 2271
07f4f97d 2272 if (azx_has_pm_runtime(chip))
30ff5957 2273 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2274
41dda0fd 2275out_free:
457f3c86 2276 if (err < 0 || !hda->need_i915_power)
029d92c2 2277 display_power(chip, false);
88d071fc 2278 if (err < 0)
9a34af4a
TI		 2279 hda->init_failed = 1;
2280 complete_all(&hda->probe_wait);
305a0ade 2281 to_hda_bus(bus)->bus_probing = 0;
41dda0fd 2282 return err;
1da177e4
LT		 2283}
2284
e23e7a14 2285static void azx_remove(struct pci_dev *pci)
1da177e4 2286{
9121947d 2287 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2288 struct azx *chip;
2289 struct hda_intel *hda;
2290
2291 if (card) {
0b8c8219 2292 /* cancel the pending probing work */
991f86d7
TI		 2293 chip = card->private_data;
2294 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2295 /* FIXME: below is an ugly workaround.
2296 * Both device_release_driver() and driver_probe_device()
2297 * take *both* the device's and its parent's lock before
2298 * calling the remove() and probe() callbacks. The codec
2299 * probe takes the locks of both the codec itself and its
2300 * parent, i.e. the PCI controller dev. Meanwhile, when
2301 * the PCI controller is unbound, it takes its lock, too
2302 * ==> ouch, a deadlock!
2303 * As a workaround, we unlock temporarily here the controller
2304 * device during cancel_work_sync() call.
2305 */
2306 device_unlock(&pci->dev);
0b8c8219 2307 cancel_work_sync(&hda->probe_work);
ab949d51 2308 device_lock(&pci->dev);
b8dfc462 2309
9121947d 2310 snd_card_free(card);
991f86d7 2311 }
1da177e4
LT		 2312}
2313
b2a0bafa
TI		 2314static void azx_shutdown(struct pci_dev *pci)
2315{
2316 struct snd_card *card = pci_get_drvdata(pci);
2317 struct azx *chip;
2318
2319 if (!card)
2320 return;
2321 chip = card->private_data;
2322 if (chip && chip->running)
2323 azx_stop_chip(chip);
2324}
2325
1da177e4 2326/* PCI IDs */
6f51f6cf 2327static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2328 /* CPT */
9477c58e 2329 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2330 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2331 /* PBG */
9477c58e 2332 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2333 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2334 /* Panther Point */
9477c58e 2335 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2336 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2337 /* Lynx Point */
2338 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2339 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2340 /* 9 Series */
2341 { PCI_DEVICE(0x8086, 0x8ca0),
2342 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2343 /* Wellsburg */
2344 { PCI_DEVICE(0x8086, 0x8d20),
2345 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2346 { PCI_DEVICE(0x8086, 0x8d21),
2347 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2348 /* Lewisburg */
2349 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2350 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2351 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2352 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2353 /* Lynx Point-LP */
2354 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2355 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2356 /* Lynx Point-LP */
2357 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2358 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2359 /* Wildcat Point-LP */
2360 { PCI_DEVICE(0x8086, 0x9ca0),
2361 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2362 /* Sunrise Point */
2363 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2364 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2365 /* Sunrise Point-LP */
2366 { PCI_DEVICE(0x8086, 0x9d70),
3e9ad24b 2367 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2368 /* Kabylake */
2369 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2370 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2371 /* Kabylake-LP */
2372 { PCI_DEVICE(0x8086, 0x9d71),
3e9ad24b 2373 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2374 /* Kabylake-H */
2375 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2376 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2377 /* Coffelake */
2378 { PCI_DEVICE(0x8086, 0xa348),
3e9ad24b 2379 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2380 /* Cannonlake */
2381 { PCI_DEVICE(0x8086, 0x9dc8),
3e9ad24b 2382 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d4c2ccdb
PLB		 2383 /* CometLake-LP */
2384 { PCI_DEVICE(0x8086, 0x02C8),
2385 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2386 /* CometLake-H */
2387 { PCI_DEVICE(0x8086, 0x06C8),
2388 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
491f8331
GS		 2389 /* Icelake */
2390 { PCI_DEVICE(0x8086, 0x34c8),
3e9ad24b 2391 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
4750c212
PX		 2392 /* Jasperlake */
2393 { PCI_DEVICE(0x8086, 0x38c8),
2394 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2395 /* Tigerlake */
2396 { PCI_DEVICE(0x8086, 0xa0c8),
2397 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
f94287b6
LPS		 2398 /* Elkhart Lake */
2399 { PCI_DEVICE(0x8086, 0x4b55),
2400 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2401 /* Broxton-P(Apollolake) */
2402 { PCI_DEVICE(0x8086, 0x5a98),
3e9ad24b 2403 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2404 /* Broxton-T */
2405 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2406 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2407 /* Gemini-Lake */
2408 { PCI_DEVICE(0x8086, 0x3198),
3e9ad24b 2409 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2410 /* Haswell */
4a7c516b 2411 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2412 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2413 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2414 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2415 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2416 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2417 /* Broadwell */
2418 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2419 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2420 /* 5 Series/3400 */
2421 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2422 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2423 /* Poulsbo */
9477c58e 2424 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2425 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2426 /* Oaktrail */
09904b95 2427 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2428 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2429 /* BayTrail */
2430 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2431 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2432 /* Braswell */
2433 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2434 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2435 /* ICH6 */
8b0bd226 2436 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2437 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2438 /* ICH7 */
8b0bd226 2439 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2440 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2441 /* ESB2 */
8b0bd226 2442 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2443 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2444 /* ICH8 */
8b0bd226 2445 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2446 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2447 /* ICH9 */
8b0bd226 2448 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2449 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2450 /* ICH9 */
8b0bd226 2451 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2452 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2453 /* ICH10 */
8b0bd226 2454 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2455 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2456 /* ICH10 */
8b0bd226 2457 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2458 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2459 /* Generic Intel */
2460 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2461 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2462 .class_mask = 0xffffff,
103884a3 2463 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2464 /* ATI SB 450/600/700/800/900 */
2465 { PCI_DEVICE(0x1002, 0x437b),
2466 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2467 { PCI_DEVICE(0x1002, 0x4383),
2468 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2469 /* AMD Hudson */
2470 { PCI_DEVICE(0x1022, 0x780d),
2471 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
c02f77d3
TI		 2472 /* AMD, X370 & co */
2473 { PCI_DEVICE(0x1022, 0x1457),
2474 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
de768ce4
TI		 2475 /* AMD, X570 & co */
2476 { PCI_DEVICE(0x1022, 0x1487),
2477 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
3deef52c
KHF		 2478 /* AMD Stoney */
2479 { PCI_DEVICE(0x1022, 0x157a),
2480 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2481 AZX_DCAPS_PM_RUNTIME },
9ceace3c
VM		 2482 /* AMD Raven */
2483 { PCI_DEVICE(0x1022, 0x15e3),
d2c63b7d 2484 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
87218e9c 2485 /* ATI HDMI */
fd48331f
MSB		 2486 { PCI_DEVICE(0x1002, 0x0002),
2487 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2488 { PCI_DEVICE(0x1002, 0x1308),
2489 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2490 { PCI_DEVICE(0x1002, 0x157a),
2491 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2492 { PCI_DEVICE(0x1002, 0x15b3),
2493 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2494 { PCI_DEVICE(0x1002, 0x793b),
2495 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2496 { PCI_DEVICE(0x1002, 0x7919),
2497 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2498 { PCI_DEVICE(0x1002, 0x960f),
2499 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500 { PCI_DEVICE(0x1002, 0x970f),
2501 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2502 { PCI_DEVICE(0x1002, 0x9840),
2503 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2504 { PCI_DEVICE(0x1002, 0xaa00),
2505 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506 { PCI_DEVICE(0x1002, 0xaa08),
2507 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508 { PCI_DEVICE(0x1002, 0xaa10),
2509 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510 { PCI_DEVICE(0x1002, 0xaa18),
2511 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512 { PCI_DEVICE(0x1002, 0xaa20),
2513 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514 { PCI_DEVICE(0x1002, 0xaa28),
2515 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516 { PCI_DEVICE(0x1002, 0xaa30),
2517 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518 { PCI_DEVICE(0x1002, 0xaa38),
2519 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520 { PCI_DEVICE(0x1002, 0xaa40),
2521 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522 { PCI_DEVICE(0x1002, 0xaa48),
2523 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2524 { PCI_DEVICE(0x1002, 0xaa50),
2525 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526 { PCI_DEVICE(0x1002, 0xaa58),
2527 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2528 { PCI_DEVICE(0x1002, 0xaa60),
2529 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2530 { PCI_DEVICE(0x1002, 0xaa68),
2531 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2532 { PCI_DEVICE(0x1002, 0xaa80),
2533 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2534 { PCI_DEVICE(0x1002, 0xaa88),
2535 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536 { PCI_DEVICE(0x1002, 0xaa90),
2537 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538 { PCI_DEVICE(0x1002, 0xaa98),
2539 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2540 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2541 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2542 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2543 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2544 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2545 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2546 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2547 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2548 { PCI_DEVICE(0x1002, 0xaac0),
2549 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2550 { PCI_DEVICE(0x1002, 0xaac8),
2551 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2552 { PCI_DEVICE(0x1002, 0xaad8),
2553 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2554 { PCI_DEVICE(0x1002, 0xaae8),
2555 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2556 { PCI_DEVICE(0x1002, 0xaae0),
2557 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558 { PCI_DEVICE(0x1002, 0xaaf0),
2559 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2560 /* VIA VT8251/VT8237A */
26f05717 2561 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2562 /* VIA GFX VT7122/VX900 */
2563 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2564 /* VIA GFX VT6122/VX11 */
2565 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2566 /* SIS966 */
2567 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2568 /* ULI M5461 */
2569 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2570 /* NVIDIA MCP */
0c2fd1bf
TI		 2571 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2572 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2573 .class_mask = 0xffffff,
9477c58e 2574 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2575 /* Teradici */
9477c58e
TI		 2576 { PCI_DEVICE(0x6549, 0x1200),
2577 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2578 { PCI_DEVICE(0x6549, 0x2200),
2579 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2580 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2581 /* CTHDA chips */
2582 { PCI_DEVICE(0x1102, 0x0010),
2583 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2584 { PCI_DEVICE(0x1102, 0x0012),
2585 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2586#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2587 /* the following entry conflicts with snd-ctxfi driver,
2588 * as ctxfi driver mutates from HD-audio to native mode with
2589 * a special command sequence.
2590 */
4e01f54b
TI		 2591 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2592 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2593 .class_mask = 0xffffff,
9477c58e 2594 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2595 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2596#else
2597 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2598 { PCI_DEVICE(0x1102, 0x0009),
2599 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2600 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2601#endif
c563f473
TI		 2602 /* CM8888 */
2603 { PCI_DEVICE(0x13f6, 0x5011),
2604 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2605 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2606 /* Vortex86MX */
2607 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2608 /* VMware HDAudio */
2609 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2610 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2611 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2612 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2613 .class_mask = 0xffffff,
9477c58e 2614 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2615 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2616 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2617 .class_mask = 0xffffff,
9477c58e 2618 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
b6fcab14
TW		 2619 /* Zhaoxin */
2620 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
1da177e4
LT		 2621 { 0, }
2622};
2623MODULE_DEVICE_TABLE(pci, azx_ids);
2624
2625/* pci_driver definition */
e9f66d9b 2626static struct pci_driver azx_driver = {
3733e424 2627 .name = KBUILD_MODNAME,
1da177e4
LT		 2628 .id_table = azx_ids,
2629 .probe = azx_probe,
e23e7a14 2630 .remove = azx_remove,
b2a0bafa 2631 .shutdown = azx_shutdown,
68cb2b55
TI		 2632 .driver = {
2633 .pm = AZX_PM_OPS,
2634 },
1da177e4
LT		 2635};
2636
e9f66d9b 2637module_pci_driver(azx_driver);
Linux 6.x block layer and io_uring tree(s)