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ALSA: hda: read CORBWP inside reg_lock
[linux-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
134a11f0 63static int enable_msi;
1da177e4 64
5aba4f8e 65module_param_array(index, int, NULL, 0444);
1da177e4 66MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 67module_param_array(id, charp, NULL, 0444);
1da177e4 68MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 69module_param_array(enable, bool, NULL, 0444);
70MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71module_param_array(model, charp, NULL, 0444);
1da177e4 72MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 73module_param_array(position_fix, int, NULL, 0444);
d01ce99f 74MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 75 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 76module_param_array(bdl_pos_adj, int, NULL, 0644);
77MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 78module_param_array(probe_mask, int, NULL, 0444);
606ad75f 79MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
d4d9cd03
TI		 80module_param_array(probe_only, bool, NULL, 0444);
81MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 82module_param(single_cmd, bool, 0444);
d01ce99f
TI		 83MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84 "(for debugging only).");
5aba4f8e 85module_param(enable_msi, int, 0444);
134a11f0 86MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
606ad75f 87
dee1b66c 88#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 89static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90module_param(power_save, int, 0644);
91MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
1da177e4 93
dee1b66c
TI		 94/* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
96 * wake up.
97 */
98static int power_save_controller = 1;
99module_param(power_save_controller, bool, 0644);
100MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
101#endif
102
1da177e4
LT		 103MODULE_LICENSE("GPL");
104MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
105 "{Intel, ICH6M},"
2f1b3818 106 "{Intel, ICH7},"
f5d40b30 107 "{Intel, ESB2},"
d2981393 108 "{Intel, ICH8},"
f9cc8a8b 109 "{Intel, ICH9},"
c34f5a04 110 "{Intel, ICH10},"
b29c2360 111 "{Intel, PCH},"
4979bca9 112 "{Intel, SCH},"
fc20a562 113 "{ATI, SB450},"
89be83f8 114 "{ATI, SB600},"
778b6e1b 115 "{ATI, RS600},"
5b15c95f 116 "{ATI, RS690},"
e6db1119
WL		 117 "{ATI, RS780},"
118 "{ATI, R600},"
2797f724
HRK		 119 "{ATI, RV630},"
120 "{ATI, RV610},"
27da1834
WL		 121 "{ATI, RV670},"
122 "{ATI, RV635},"
123 "{ATI, RV620},"
124 "{ATI, RV770},"
fc20a562 125 "{VIA, VT8251},"
47672310 126 "{VIA, VT8237A},"
07e4ca50
TI		 127 "{SiS, SIS966},"
128 "{ULI, M5461}}");
1da177e4
LT		 129MODULE_DESCRIPTION("Intel HDA driver");
130
4abc1cc2
TI		 131#ifdef CONFIG_SND_VERBOSE_PRINTK
132#define SFX /* nop */
133#else
1da177e4 134#define SFX "hda-intel: "
4abc1cc2 135#endif
cb53c626 136
1da177e4
LT		 137/*
138 * registers
139 */
140#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 141#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
142#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
143#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
144#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
145#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 146#define ICH6_REG_VMIN 0x02
147#define ICH6_REG_VMAJ 0x03
148#define ICH6_REG_OUTPAY 0x04
149#define ICH6_REG_INPAY 0x06
150#define ICH6_REG_GCTL 0x08
8a933ece 151#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 152#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
153#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 154#define ICH6_REG_WAKEEN 0x0c
155#define ICH6_REG_STATESTS 0x0e
156#define ICH6_REG_GSTS 0x10
b21fadb9 157#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 158#define ICH6_REG_INTCTL 0x20
159#define ICH6_REG_INTSTS 0x24
160#define ICH6_REG_WALCLK 0x30
161#define ICH6_REG_SYNC 0x34
162#define ICH6_REG_CORBLBASE 0x40
163#define ICH6_REG_CORBUBASE 0x44
164#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 165#define ICH6_REG_CORBRP 0x4a
166#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 167#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 168#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
169#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 170#define ICH6_REG_CORBSTS 0x4d
b21fadb9 171#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 172#define ICH6_REG_CORBSIZE 0x4e
173
174#define ICH6_REG_RIRBLBASE 0x50
175#define ICH6_REG_RIRBUBASE 0x54
176#define ICH6_REG_RIRBWP 0x58
b21fadb9 177#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 178#define ICH6_REG_RINTCNT 0x5a
179#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 180#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
181#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
182#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 183#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 184#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
185#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 186#define ICH6_REG_RIRBSIZE 0x5e
187
188#define ICH6_REG_IC 0x60
189#define ICH6_REG_IR 0x64
190#define ICH6_REG_IRS 0x68
191#define ICH6_IRS_VALID (1<<1)
192#define ICH6_IRS_BUSY (1<<0)
193
194#define ICH6_REG_DPLBASE 0x70
195#define ICH6_REG_DPUBASE 0x74
196#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
197
198/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
199enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
200
201/* stream register offsets from stream base */
202#define ICH6_REG_SD_CTL 0x00
203#define ICH6_REG_SD_STS 0x03
204#define ICH6_REG_SD_LPIB 0x04
205#define ICH6_REG_SD_CBL 0x08
206#define ICH6_REG_SD_LVI 0x0c
207#define ICH6_REG_SD_FIFOW 0x0e
208#define ICH6_REG_SD_FIFOSIZE 0x10
209#define ICH6_REG_SD_FORMAT 0x12
210#define ICH6_REG_SD_BDLPL 0x18
211#define ICH6_REG_SD_BDLPU 0x1c
212
213/* PCI space */
214#define ICH6_PCIREG_TCSEL 0x44
215
216/*
217 * other constants
218 */
219
220/* max number of SDs */
07e4ca50 221/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 222#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 223#define ICH6_NUM_PLAYBACK 4
224
225/* ULI has 6 playback and 5 capture */
07e4ca50 226#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 227#define ULI_NUM_PLAYBACK 6
228
778b6e1b 229/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 230#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 231#define ATIHDMI_NUM_PLAYBACK 1
232
f269002e
KY		 233/* TERA has 4 playback and 3 capture */
234#define TERA_NUM_CAPTURE 3
235#define TERA_NUM_PLAYBACK 4
236
07e4ca50
TI		 237/* this number is statically defined for simplicity */
238#define MAX_AZX_DEV 16
239
1da177e4 240/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 241#define BDL_SIZE 4096
242#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
243#define AZX_MAX_FRAG 32
1da177e4
LT		 244/* max buffer size - no h/w limit, you can increase as you like */
245#define AZX_MAX_BUF_SIZE (1024*1024*1024)
246/* max number of PCM devics per card */
7ba72ba1 247#define AZX_MAX_PCMS 8
1da177e4
LT		 248
249/* RIRB int mask: overrun[2], response[0] */
250#define RIRB_INT_RESPONSE 0x01
251#define RIRB_INT_OVERRUN 0x04
252#define RIRB_INT_MASK 0x05
253
2f5983f2
TI		 254/* STATESTS int mask: S3,SD2,SD1,SD0 */
255#define AZX_MAX_CODECS 4
deadff16 256#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 257
258/* SD_CTL bits */
259#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
260#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 261#define SD_CTL_STRIPE (3 << 16) /* stripe control */
262#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
263#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 264#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
265#define SD_CTL_STREAM_TAG_SHIFT 20
266
267/* SD_CTL and SD_STS */
268#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
269#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
270#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 271#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
272 SD_INT_COMPLETE)
1da177e4
LT		 273
274/* SD_STS */
275#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
276
277/* INTCTL and INTSTS */
d01ce99f
TI		 278#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
279#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
280#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 281
1da177e4
LT		 282/* below are so far hardcoded - should read registers in future */
283#define ICH6_MAX_CORB_ENTRIES 256
284#define ICH6_MAX_RIRB_ENTRIES 256
285
c74db86b
TI		 286/* position fix mode */
287enum {
0be3b5d3 288 POS_FIX_AUTO,
d2e1c973 289 POS_FIX_LPIB,
0be3b5d3 290 POS_FIX_POSBUF,
c74db86b 291};
1da177e4 292
f5d40b30 293/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 294#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
295#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
296
da3fca21
V		 297/* Defines for Nvidia HDA support */
298#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
299#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 300#define NVIDIA_HDA_ISTRM_COH 0x4d
301#define NVIDIA_HDA_OSTRM_COH 0x4c
302#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 303
90a5ad52
TI		 304/* Defines for Intel SCH HDA snoop control */
305#define INTEL_SCH_HDA_DEVC 0x78
306#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
307
0e153474
JC		 308/* Define IN stream 0 FIFO size offset in VIA controller */
309#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
310/* Define VIA HD Audio Device ID*/
311#define VIA_HDAC_DEVICE_ID 0x3288
312
c4da29ca
YL		 313/* HD Audio class code */
314#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 315
1da177e4
LT		 316/*
317 */
318
a98f90fd 319struct azx_dev {
4ce107b9 320 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 321 u32 *posbuf; /* position buffer pointer */
1da177e4 322
d01ce99f 323 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 324 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 325 unsigned int frags; /* number for period in the play buffer */
326 unsigned int fifo_size; /* FIFO size */
fa00e046
JK		 327 unsigned long start_jiffies; /* start + minimum jiffies */
328 unsigned long min_jiffies; /* minimum jiffies before position is valid */
1da177e4 329
d01ce99f 330 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 331
d01ce99f 332 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 333
334 /* pcm support */
d01ce99f
TI		 335 struct snd_pcm_substream *substream; /* assigned substream,
336 * set in PCM open
337 */
338 unsigned int format_val; /* format value to be set in the
339 * controller and the codec
340 */
1da177e4
LT		 341 unsigned char stream_tag; /* assigned stream */
342 unsigned char index; /* stream index */
343
927fc866
PM		 344 unsigned int opened :1;
345 unsigned int running :1;
675f25d4 346 unsigned int irq_pending :1;
d523b0c8 347 unsigned int start_flag: 1; /* stream full start flag */
0e153474
JC		 348 /*
349 * For VIA:
350 * A flag to ensure DMA position is 0
351 * when link position is not greater than FIFO size
352 */
353 unsigned int insufficient :1;
1da177e4
LT		 354};
355
356/* CORB/RIRB */
a98f90fd 357struct azx_rb {
1da177e4
LT		 358 u32 *buf; /* CORB/RIRB buffer
359 * Each CORB entry is 4byte, RIRB is 8byte
360 */
361 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
362 /* for RIRB */
363 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 364 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
365 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 366};
367
a98f90fd
TI		 368struct azx {
369 struct snd_card *card;
1da177e4 370 struct pci_dev *pci;
555e219f 371 int dev_index;
1da177e4 372
07e4ca50
TI		 373 /* chip type specific */
374 int driver_type;
375 int playback_streams;
376 int playback_index_offset;
377 int capture_streams;
378 int capture_index_offset;
379 int num_streams;
380
1da177e4
LT		 381 /* pci resources */
382 unsigned long addr;
383 void __iomem *remap_addr;
384 int irq;
385
386 /* locks */
387 spinlock_t reg_lock;
62932df8 388 struct mutex open_mutex;
1da177e4 389
07e4ca50 390 /* streams (x num_streams) */
a98f90fd 391 struct azx_dev *azx_dev;
1da177e4
LT		 392
393 /* PCM */
a98f90fd 394 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT		 395
396 /* HD codec */
397 unsigned short codec_mask;
f1eaaeec 398 int codec_probe_mask; /* copied from probe_mask option */
1da177e4
LT		 399 struct hda_bus *bus;
400
401 /* CORB/RIRB */
a98f90fd
TI		 402 struct azx_rb corb;
403 struct azx_rb rirb;
1da177e4 404
4ce107b9 405 /* CORB/RIRB and position buffers */
1da177e4
LT		 406 struct snd_dma_buffer rb;
407 struct snd_dma_buffer posbuf;
c74db86b
TI		 408
409 /* flags */
410 int position_fix;
cb53c626 411 unsigned int running :1;
927fc866
PM		 412 unsigned int initialized :1;
413 unsigned int single_cmd :1;
414 unsigned int polling_mode :1;
68e7fffc 415 unsigned int msi :1;
a6a950a8 416 unsigned int irq_pending_warned :1;
0e153474 417 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
6ce4a3bc 418 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 419
420 /* for debugging */
421 unsigned int last_cmd; /* last issued command (to sync) */
9ad593f6
TI		 422
423 /* for pending irqs */
424 struct work_struct irq_pending_work;
0cbf0098
TI		 425
426 /* reboot notifier (for mysterious hangup problem at power-down) */
427 struct notifier_block reboot_notifier;
1da177e4
LT		 428};
429
07e4ca50
TI		 430/* driver types */
431enum {
432 AZX_DRIVER_ICH,
4979bca9 433 AZX_DRIVER_SCH,
07e4ca50 434 AZX_DRIVER_ATI,
778b6e1b 435 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 436 AZX_DRIVER_VIA,
437 AZX_DRIVER_SIS,
438 AZX_DRIVER_ULI,
da3fca21 439 AZX_DRIVER_NVIDIA,
f269002e 440 AZX_DRIVER_TERA,
c4da29ca 441 AZX_DRIVER_GENERIC,
2f5983f2 442 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 443};
444
445static char *driver_short_names[] __devinitdata = {
446 [AZX_DRIVER_ICH] = "HDA Intel",
4979bca9 447 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 448 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 449 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 450 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
451 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 452 [AZX_DRIVER_ULI] = "HDA ULI M5461",
453 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 454 [AZX_DRIVER_TERA] = "HDA Teradici",
c4da29ca 455 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 456};
457
1da177e4
LT		 458/*
459 * macros for easy use
460 */
461#define azx_writel(chip,reg,value) \
462 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
463#define azx_readl(chip,reg) \
464 readl((chip)->remap_addr + ICH6_REG_##reg)
465#define azx_writew(chip,reg,value) \
466 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
467#define azx_readw(chip,reg) \
468 readw((chip)->remap_addr + ICH6_REG_##reg)
469#define azx_writeb(chip,reg,value) \
470 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
471#define azx_readb(chip,reg) \
472 readb((chip)->remap_addr + ICH6_REG_##reg)
473
474#define azx_sd_writel(dev,reg,value) \
475 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
476#define azx_sd_readl(dev,reg) \
477 readl((dev)->sd_addr + ICH6_REG_##reg)
478#define azx_sd_writew(dev,reg,value) \
479 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
480#define azx_sd_readw(dev,reg) \
481 readw((dev)->sd_addr + ICH6_REG_##reg)
482#define azx_sd_writeb(dev,reg,value) \
483 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
484#define azx_sd_readb(dev,reg) \
485 readb((dev)->sd_addr + ICH6_REG_##reg)
486
487/* for pcm support */
a98f90fd 488#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 489
68e7fffc 490static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT		 491
492/*
493 * Interface for HD codec
494 */
495
1da177e4
LT		 496/*
497 * CORB / RIRB interface
498 */
a98f90fd 499static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 500{
501 int err;
502
503 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 504 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
505 snd_dma_pci_data(chip->pci),
1da177e4
LT		 506 PAGE_SIZE, &chip->rb);
507 if (err < 0) {
508 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
509 return err;
510 }
511 return 0;
512}
513
a98f90fd 514static void azx_init_cmd_io(struct azx *chip)
1da177e4 515{
cdb1fbf2 516 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 517 /* CORB set up */
518 chip->corb.addr = chip->rb.addr;
519 chip->corb.buf = (u32 *)chip->rb.area;
520 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 521 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 522
07e4ca50
TI		 523 /* set the corb size to 256 entries (ULI requires explicitly) */
524 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 525 /* set the corb write pointer to 0 */
526 azx_writew(chip, CORBWP, 0);
527 /* reset the corb hw read pointer */
b21fadb9 528 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 529 /* enable corb dma */
b21fadb9 530 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 531
532 /* RIRB set up */
533 chip->rirb.addr = chip->rb.addr + 2048;
534 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 535 chip->rirb.wp = chip->rirb.rp = 0;
536 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 537 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 538 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 539
07e4ca50
TI		 540 /* set the rirb size to 256 entries (ULI requires explicitly) */
541 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 542 /* reset the rirb hw write pointer */
b21fadb9 543 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4
LT		 544 /* set N=1, get RIRB response interrupt for new entry */
545 azx_writew(chip, RINTCNT, 1);
546 /* enable rirb dma and response irq */
1da177e4 547 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 548 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 549}
550
a98f90fd 551static void azx_free_cmd_io(struct azx *chip)
1da177e4 552{
cdb1fbf2 553 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 554 /* disable ringbuffer DMAs */
555 azx_writeb(chip, RIRBCTL, 0);
556 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 557 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 558}
559
deadff16
WF		 560static unsigned int azx_command_addr(u32 cmd)
561{
562 unsigned int addr = cmd >> 28;
563
564 if (addr >= AZX_MAX_CODECS) {
565 snd_BUG();
566 addr = 0;
567 }
568
569 return addr;
570}
571
572static unsigned int azx_response_addr(u32 res)
573{
574 unsigned int addr = res & 0xf;
575
576 if (addr >= AZX_MAX_CODECS) {
577 snd_BUG();
578 addr = 0;
579 }
580
581 return addr;
582}
583
1da177e4 584/* send a command */
33fa35ed 585static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 586{
33fa35ed 587 struct azx *chip = bus->private_data;
deadff16 588 unsigned int addr = azx_command_addr(val);
1da177e4 589 unsigned int wp;
1da177e4 590
c32649fe
WF		 591 spin_lock_irq(&chip->reg_lock);
592
1da177e4
LT		 593 /* add command to corb */
594 wp = azx_readb(chip, CORBWP);
595 wp++;
596 wp %= ICH6_MAX_CORB_ENTRIES;
597
deadff16 598 chip->rirb.cmds[addr]++;
1da177e4
LT		 599 chip->corb.buf[wp] = cpu_to_le32(val);
600 azx_writel(chip, CORBWP, wp);
c32649fe 601
1da177e4
LT		 602 spin_unlock_irq(&chip->reg_lock);
603
604 return 0;
605}
606
607#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
608
609/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 610static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 611{
612 unsigned int rp, wp;
deadff16 613 unsigned int addr;
1da177e4
LT		 614 u32 res, res_ex;
615
616 wp = azx_readb(chip, RIRBWP);
617 if (wp == chip->rirb.wp)
618 return;
619 chip->rirb.wp = wp;
deadff16 620
1da177e4
LT		 621 while (chip->rirb.rp != wp) {
622 chip->rirb.rp++;
623 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
624
625 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
626 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
627 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 628 addr = azx_response_addr(res_ex);
1da177e4
LT		 629 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
630 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 631 else if (chip->rirb.cmds[addr]) {
632 chip->rirb.res[addr] = res;
2add9b92 633 smp_wmb();
deadff16 634 chip->rirb.cmds[addr]--;
1da177e4
LT		 635 }
636 }
637}
638
639/* receive a response */
deadff16
WF		 640static unsigned int azx_rirb_get_response(struct hda_bus *bus,
641 unsigned int addr)
1da177e4 642{
33fa35ed 643 struct azx *chip = bus->private_data;
5c79b1f8 644 unsigned long timeout;
1da177e4 645
5c79b1f8
TI		 646 again:
647 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 648 for (;;) {
e96224ae
TI		 649 if (chip->polling_mode) {
650 spin_lock_irq(&chip->reg_lock);
651 azx_update_rirb(chip);
652 spin_unlock_irq(&chip->reg_lock);
653 }
deadff16 654 if (!chip->rirb.cmds[addr]) {
2add9b92 655 smp_rmb();
b613291f 656 bus->rirb_error = 0;
deadff16 657 return chip->rirb.res[addr]; /* the last value */
2add9b92 658 }
28a0d9df
TI		 659 if (time_after(jiffies, timeout))
660 break;
33fa35ed 661 if (bus->needs_damn_long_delay)
52987656
TI		 662 msleep(2); /* temporary workaround */
663 else {
664 udelay(10);
665 cond_resched();
666 }
28a0d9df 667 }
5c79b1f8 668
68e7fffc 669 if (chip->msi) {
4abc1cc2 670 snd_printk(KERN_WARNING SFX "No response from codec, "
43bbb6cc 671 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
68e7fffc
TI		 672 free_irq(chip->irq, chip);
673 chip->irq = -1;
674 pci_disable_msi(chip->pci);
675 chip->msi = 0;
b613291f
TI		 676 if (azx_acquire_irq(chip, 1) < 0) {
677 bus->rirb_error = 1;
68e7fffc 678 return -1;
b613291f 679 }
68e7fffc
TI		 680 goto again;
681 }
682
5c79b1f8 683 if (!chip->polling_mode) {
4abc1cc2 684 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
43bbb6cc
TI		 685 "switching to polling mode: last cmd=0x%08x\n",
686 chip->last_cmd);
5c79b1f8
TI		 687 chip->polling_mode = 1;
688 goto again;
1da177e4 689 }
5c79b1f8 690
6ce4a3bc
TI		 691 if (chip->probing) {
692 /* If this critical timeout happens during the codec probing
693 * phase, this is likely an access to a non-existing codec
694 * slot. Better to return an error and reset the system.
695 */
696 return -1;
697 }
698
8dd78330
TI		 699 /* a fatal communication error; need either to reset or to fallback
700 * to the single_cmd mode
701 */
b613291f 702 bus->rirb_error = 1;
b20f3b83 703 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 704 bus->response_reset = 1;
705 return -1; /* give a chance to retry */
706 }
707
708 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
709 "switching to single_cmd mode: last cmd=0x%08x\n",
710 chip->last_cmd);
711 chip->single_cmd = 1;
712 bus->response_reset = 0;
713 /* re-initialize CORB/RIRB */
4fcd3920
TI		 714 azx_free_cmd_io(chip);
715 azx_init_cmd_io(chip);
5c79b1f8 716 return -1;
1da177e4
LT		 717}
718
1da177e4
LT		 719/*
720 * Use the single immediate command instead of CORB/RIRB for simplicity
721 *
722 * Note: according to Intel, this is not preferred use. The command was
723 * intended for the BIOS only, and may get confused with unsolicited
724 * responses. So, we shouldn't use it for normal operation from the
725 * driver.
726 * I left the codes, however, for debugging/testing purposes.
727 */
728
b05a7d4f 729/* receive a response */
deadff16 730static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 731{
732 int timeout = 50;
733
734 while (timeout--) {
735 /* check IRV busy bit */
736 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
737 /* reuse rirb.res as the response return value */
deadff16 738 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 739 return 0;
740 }
741 udelay(1);
742 }
743 if (printk_ratelimit())
744 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
745 azx_readw(chip, IRS));
deadff16 746 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 747 return -EIO;
748}
749
1da177e4 750/* send a command */
33fa35ed 751static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 752{
33fa35ed 753 struct azx *chip = bus->private_data;
deadff16 754 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 755 int timeout = 50;
756
8dd78330 757 bus->rirb_error = 0;
1da177e4
LT		 758 while (timeout--) {
759 /* check ICB busy bit */
d01ce99f 760 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 761 /* Clear IRV valid bit */
d01ce99f
TI		 762 azx_writew(chip, IRS, azx_readw(chip, IRS) |
763 ICH6_IRS_VALID);
1da177e4 764 azx_writel(chip, IC, val);
d01ce99f
TI		 765 azx_writew(chip, IRS, azx_readw(chip, IRS) |
766 ICH6_IRS_BUSY);
deadff16 767 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 768 }
769 udelay(1);
770 }
1cfd52bc
MB		 771 if (printk_ratelimit())
772 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
773 azx_readw(chip, IRS), val);
1da177e4
LT		 774 return -EIO;
775}
776
777/* receive a response */
deadff16
WF		 778static unsigned int azx_single_get_response(struct hda_bus *bus,
779 unsigned int addr)
1da177e4 780{
33fa35ed 781 struct azx *chip = bus->private_data;
deadff16 782 return chip->rirb.res[addr];
1da177e4
LT		 783}
784
111d3af5
TI		 785/*
786 * The below are the main callbacks from hda_codec.
787 *
788 * They are just the skeleton to call sub-callbacks according to the
789 * current setting of chip->single_cmd.
790 */
791
792/* send a command */
33fa35ed 793static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 794{
33fa35ed 795 struct azx *chip = bus->private_data;
43bbb6cc 796
33fa35ed 797 chip->last_cmd = val;
111d3af5 798 if (chip->single_cmd)
33fa35ed 799 return azx_single_send_cmd(bus, val);
111d3af5 800 else
33fa35ed 801 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 802}
803
804/* get a response */
deadff16
WF		 805static unsigned int azx_get_response(struct hda_bus *bus,
806 unsigned int addr)
111d3af5 807{
33fa35ed 808 struct azx *chip = bus->private_data;
111d3af5 809 if (chip->single_cmd)
deadff16 810 return azx_single_get_response(bus, addr);
111d3af5 811 else
deadff16 812 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 813}
814
cb53c626 815#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 816static void azx_power_notify(struct hda_bus *bus);
cb53c626 817#endif
111d3af5 818
1da177e4 819/* reset codec link */
a98f90fd 820static int azx_reset(struct azx *chip)
1da177e4
LT		 821{
822 int count;
823
e8a7f136
DT		 824 /* clear STATESTS */
825 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
826
1da177e4
LT		 827 /* reset controller */
828 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
829
830 count = 50;
831 while (azx_readb(chip, GCTL) && --count)
832 msleep(1);
833
834 /* delay for >= 100us for codec PLL to settle per spec
835 * Rev 0.9 section 5.5.1
836 */
837 msleep(1);
838
839 /* Bring controller out of reset */
840 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
841
842 count = 50;
927fc866 843 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 844 msleep(1);
845
927fc866 846 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 847 msleep(1);
848
849 /* check to see if controller is ready */
927fc866 850 if (!azx_readb(chip, GCTL)) {
4abc1cc2 851 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 852 return -EBUSY;
853 }
854
41e2fce4 855 /* Accept unsolicited responses */
b21fadb9 856 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
41e2fce4 857
1da177e4 858 /* detect codecs */
927fc866 859 if (!chip->codec_mask) {
1da177e4 860 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 861 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 862 }
863
864 return 0;
865}
866
867
868/*
869 * Lowlevel interface
870 */
871
872/* enable interrupts */
a98f90fd 873static void azx_int_enable(struct azx *chip)
1da177e4
LT		 874{
875 /* enable controller CIE and GIE */
876 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
877 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
878}
879
880/* disable interrupts */
a98f90fd 881static void azx_int_disable(struct azx *chip)
1da177e4
LT		 882{
883 int i;
884
885 /* disable interrupts in stream descriptor */
07e4ca50 886 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 887 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 888 azx_sd_writeb(azx_dev, SD_CTL,
889 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
890 }
891
892 /* disable SIE for all streams */
893 azx_writeb(chip, INTCTL, 0);
894
895 /* disable controller CIE and GIE */
896 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
897 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
898}
899
900/* clear interrupts */
a98f90fd 901static void azx_int_clear(struct azx *chip)
1da177e4
LT		 902{
903 int i;
904
905 /* clear stream status */
07e4ca50 906 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 907 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 908 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
909 }
910
911 /* clear STATESTS */
912 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
913
914 /* clear rirb status */
915 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
916
917 /* clear int status */
918 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
919}
920
921/* start a stream */
a98f90fd 922static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 923{
0e153474
JC		 924 /*
925 * Before stream start, initialize parameter
926 */
927 azx_dev->insufficient = 1;
928
1da177e4
LT		 929 /* enable SIE */
930 azx_writeb(chip, INTCTL,
931 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
932 /* set DMA start and interrupt mask */
933 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
934 SD_CTL_DMA_START | SD_INT_MASK);
935}
936
1dddab40
TI		 937/* stop DMA */
938static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 939{
1da177e4
LT		 940 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
941 ~(SD_CTL_DMA_START | SD_INT_MASK));
942 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 943}
944
945/* stop a stream */
946static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
947{
948 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 949 /* disable SIE */
950 azx_writeb(chip, INTCTL,
951 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
952}
953
954
955/*
cb53c626 956 * reset and start the controller registers
1da177e4 957 */
a98f90fd 958static void azx_init_chip(struct azx *chip)
1da177e4 959{
cb53c626
TI		 960 if (chip->initialized)
961 return;
1da177e4
LT		 962
963 /* reset controller */
964 azx_reset(chip);
965
966 /* initialize interrupts */
967 azx_int_clear(chip);
968 azx_int_enable(chip);
969
970 /* initialize the codec command I/O */
81740861 971 azx_init_cmd_io(chip);
1da177e4 972
0be3b5d3
TI		 973 /* program the position buffer */
974 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 975 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 976
cb53c626
TI		 977 chip->initialized = 1;
978}
979
980/*
981 * initialize the PCI registers
982 */
983/* update bits in a PCI register byte */
984static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
985 unsigned char mask, unsigned char val)
986{
987 unsigned char data;
988
989 pci_read_config_byte(pci, reg, &data);
990 data &= ~mask;
991 data |= (val & mask);
992 pci_write_config_byte(pci, reg, data);
993}
994
995static void azx_init_pci(struct azx *chip)
996{
90a5ad52
TI		 997 unsigned short snoop;
998
cb53c626
TI		 999 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1000 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1001 * Ensuring these bits are 0 clears playback static on some HD Audio
1002 * codecs
1003 */
1004 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1005
da3fca21
V		 1006 switch (chip->driver_type) {
1007 case AZX_DRIVER_ATI:
1008 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 1009 update_pci_byte(chip->pci,
1010 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1011 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 1012 break;
1013 case AZX_DRIVER_NVIDIA:
1014 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 1015 update_pci_byte(chip->pci,
1016 NVIDIA_HDA_TRANSREG_ADDR,
1017 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1018 update_pci_byte(chip->pci,
1019 NVIDIA_HDA_ISTRM_COH,
1020 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1021 update_pci_byte(chip->pci,
1022 NVIDIA_HDA_OSTRM_COH,
1023 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 1024 break;
90a5ad52
TI		 1025 case AZX_DRIVER_SCH:
1026 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1027 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
4abc1cc2 1028 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
90a5ad52
TI		 1029 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1030 pci_read_config_word(chip->pci,
1031 INTEL_SCH_HDA_DEVC, &snoop);
4abc1cc2
TI		 1032 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1033 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
90a5ad52
TI		 1034 ? "Failed" : "OK");
1035 }
1036 break;
1037
da3fca21 1038 }
1da177e4
LT		 1039}
1040
1041
9ad593f6
TI		 1042static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1043
1da177e4
LT		 1044/*
1045 * interrupt handler
1046 */
7d12e780 1047static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1048{
a98f90fd
TI		 1049 struct azx *chip = dev_id;
1050 struct azx_dev *azx_dev;
1da177e4 1051 u32 status;
fa00e046 1052 int i, ok;
1da177e4
LT		 1053
1054 spin_lock(&chip->reg_lock);
1055
1056 status = azx_readl(chip, INTSTS);
1057 if (status == 0) {
1058 spin_unlock(&chip->reg_lock);
1059 return IRQ_NONE;
1060 }
1061
07e4ca50 1062 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1063 azx_dev = &chip->azx_dev[i];
1064 if (status & azx_dev->sd_int_sta_mask) {
1065 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 1066 if (!azx_dev->substream || !azx_dev->running)
1067 continue;
1068 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1069 ok = azx_position_ok(chip, azx_dev);
1070 if (ok == 1) {
9ad593f6 1071 azx_dev->irq_pending = 0;
1da177e4
LT		 1072 spin_unlock(&chip->reg_lock);
1073 snd_pcm_period_elapsed(azx_dev->substream);
1074 spin_lock(&chip->reg_lock);
fa00e046 1075 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1076 /* bogus IRQ, process it later */
1077 azx_dev->irq_pending = 1;
6acaed38
TI		 1078 queue_work(chip->bus->workq,
1079 &chip->irq_pending_work);
1da177e4
LT		 1080 }
1081 }
1082 }
1083
1084 /* clear rirb int */
1085 status = azx_readb(chip, RIRBSTS);
1086 if (status & RIRB_INT_MASK) {
81740861 1087 if (status & RIRB_INT_RESPONSE)
1da177e4
LT		 1088 azx_update_rirb(chip);
1089 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1090 }
1091
1092#if 0
1093 /* clear state status int */
1094 if (azx_readb(chip, STATESTS) & 0x04)
1095 azx_writeb(chip, STATESTS, 0x04);
1096#endif
1097 spin_unlock(&chip->reg_lock);
1098
1099 return IRQ_HANDLED;
1100}
1101
1102
675f25d4
TI		 1103/*
1104 * set up a BDL entry
1105 */
1106static int setup_bdle(struct snd_pcm_substream *substream,
1107 struct azx_dev *azx_dev, u32 **bdlp,
1108 int ofs, int size, int with_ioc)
1109{
675f25d4
TI		 1110 u32 *bdl = *bdlp;
1111
1112 while (size > 0) {
1113 dma_addr_t addr;
1114 int chunk;
1115
1116 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1117 return -EINVAL;
1118
77a23f26 1119 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1120 /* program the address field of the BDL entry */
1121 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1122 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1123 /* program the size field of the BDL entry */
fc4abee8 1124 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1125 bdl[2] = cpu_to_le32(chunk);
1126 /* program the IOC to enable interrupt
1127 * only when the whole fragment is processed
1128 */
1129 size -= chunk;
1130 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1131 bdl += 4;
1132 azx_dev->frags++;
1133 ofs += chunk;
1134 }
1135 *bdlp = bdl;
1136 return ofs;
1137}
1138
1da177e4
LT		 1139/*
1140 * set up BDL entries
1141 */
555e219f
TI		 1142static int azx_setup_periods(struct azx *chip,
1143 struct snd_pcm_substream *substream,
4ce107b9 1144 struct azx_dev *azx_dev)
1da177e4 1145{
4ce107b9
TI		 1146 u32 *bdl;
1147 int i, ofs, periods, period_bytes;
555e219f 1148 int pos_adj;
1da177e4
LT		 1149
1150 /* reset BDL address */
1151 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1152 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1153
97b71c94 1154 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1155 periods = azx_dev->bufsize / period_bytes;
1156
1da177e4 1157 /* program the initial BDL entries */
4ce107b9
TI		 1158 bdl = (u32 *)azx_dev->bdl.area;
1159 ofs = 0;
1160 azx_dev->frags = 0;
555e219f
TI		 1161 pos_adj = bdl_pos_adj[chip->dev_index];
1162 if (pos_adj > 0) {
675f25d4 1163 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1164 int pos_align = pos_adj;
555e219f 1165 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1166 if (!pos_adj)
e785d3d8
TI		 1167 pos_adj = pos_align;
1168 else
1169 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1170 pos_align;
675f25d4
TI		 1171 pos_adj = frames_to_bytes(runtime, pos_adj);
1172 if (pos_adj >= period_bytes) {
4abc1cc2 1173 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1174 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1175 pos_adj = 0;
1176 } else {
1177 ofs = setup_bdle(substream, azx_dev,
1178 &bdl, ofs, pos_adj, 1);
1179 if (ofs < 0)
1180 goto error;
4ce107b9 1181 }
555e219f
TI		 1182 } else
1183 pos_adj = 0;
675f25d4
TI		 1184 for (i = 0; i < periods; i++) {
1185 if (i == periods - 1 && pos_adj)
1186 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1187 period_bytes - pos_adj, 0);
1188 else
1189 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1190 period_bytes, 1);
1191 if (ofs < 0)
1192 goto error;
1da177e4 1193 }
4ce107b9 1194 return 0;
675f25d4
TI		 1195
1196 error:
4abc1cc2 1197 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1198 azx_dev->bufsize, period_bytes);
675f25d4 1199 return -EINVAL;
1da177e4
LT		 1200}
1201
1dddab40
TI		 1202/* reset stream */
1203static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1204{
1205 unsigned char val;
1206 int timeout;
1207
1dddab40
TI		 1208 azx_stream_clear(chip, azx_dev);
1209
d01ce99f
TI		 1210 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1211 SD_CTL_STREAM_RESET);
1da177e4
LT		 1212 udelay(3);
1213 timeout = 300;
1214 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1215 --timeout)
1216 ;
1217 val &= ~SD_CTL_STREAM_RESET;
1218 azx_sd_writeb(azx_dev, SD_CTL, val);
1219 udelay(3);
1220
1221 timeout = 300;
1222 /* waiting for hardware to report that the stream is out of reset */
1223 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1224 --timeout)
1225 ;
fa00e046
JK		 1226
1227 /* reset first position - may not be synced with hw at this time */
1228 *azx_dev->posbuf = 0;
1dddab40 1229}
1da177e4 1230
1dddab40
TI		 1231/*
1232 * set up the SD for streaming
1233 */
1234static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1235{
1236 /* make sure the run bit is zero for SD */
1237 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 1238 /* program the stream_tag */
1239 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1240 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1241 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1242
1243 /* program the length of samples in cyclic buffer */
1244 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1245
1246 /* program the stream format */
1247 /* this value needs to be the same as the one programmed */
1248 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1249
1250 /* program the stream LVI (last valid index) of the BDL */
1251 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1252
1253 /* program the BDL address */
1254 /* lower BDL address */
4ce107b9 1255 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1256 /* upper BDL address */
766979e0 1257 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1258
0be3b5d3 1259 /* enable the position buffer */
ee9d6b9a 1260 if (chip->position_fix == POS_FIX_POSBUF ||
0e153474
JC		 1261 chip->position_fix == POS_FIX_AUTO ||
1262 chip->via_dmapos_patch) {
ee9d6b9a
TI		 1263 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1264 azx_writel(chip, DPLBASE,
1265 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1266 }
c74db86b 1267
1da177e4 1268 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1269 azx_sd_writel(azx_dev, SD_CTL,
1270 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1271
1272 return 0;
1273}
1274
6ce4a3bc
TI		 1275/*
1276 * Probe the given codec address
1277 */
1278static int probe_codec(struct azx *chip, int addr)
1279{
1280 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1281 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1282 unsigned int res;
1283
a678cdee 1284 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1285 chip->probing = 1;
1286 azx_send_cmd(chip->bus, cmd);
deadff16 1287 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1288 chip->probing = 0;
a678cdee 1289 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1290 if (res == -1)
1291 return -EIO;
4abc1cc2 1292 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1293 return 0;
1294}
1295
33fa35ed
TI		 1296static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1297 struct hda_pcm *cpcm);
6ce4a3bc 1298static void azx_stop_chip(struct azx *chip);
1da177e4 1299
8dd78330
TI		 1300static void azx_bus_reset(struct hda_bus *bus)
1301{
1302 struct azx *chip = bus->private_data;
8dd78330
TI		 1303
1304 bus->in_reset = 1;
1305 azx_stop_chip(chip);
1306 azx_init_chip(chip);
65f75983 1307#ifdef CONFIG_PM
8dd78330 1308 if (chip->initialized) {
65f75983
AB		 1309 int i;
1310
8dd78330
TI		 1311 for (i = 0; i < AZX_MAX_PCMS; i++)
1312 snd_pcm_suspend_all(chip->pcm[i]);
1313 snd_hda_suspend(chip->bus);
1314 snd_hda_resume(chip->bus);
1315 }
65f75983 1316#endif
8dd78330
TI		 1317 bus->in_reset = 0;
1318}
1319
1da177e4
LT		 1320/*
1321 * Codec initialization
1322 */
1323
2f5983f2
TI		 1324/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1325static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
f269002e 1326 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1327};
1328
5aba4f8e 1329static int __devinit azx_codec_create(struct azx *chip, const char *model,
d4d9cd03 1330 int no_init)
1da177e4
LT		 1331{
1332 struct hda_bus_template bus_temp;
34c25350
TI		 1333 int c, codecs, err;
1334 int max_slots;
1da177e4
LT		 1335
1336 memset(&bus_temp, 0, sizeof(bus_temp));
1337 bus_temp.private_data = chip;
1338 bus_temp.modelname = model;
1339 bus_temp.pci = chip->pci;
111d3af5
TI		 1340 bus_temp.ops.command = azx_send_cmd;
1341 bus_temp.ops.get_response = azx_get_response;
176d5335 1342 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1343 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1344#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1345 bus_temp.power_save = &power_save;
cb53c626
TI		 1346 bus_temp.ops.pm_notify = azx_power_notify;
1347#endif
1da177e4 1348
d01ce99f
TI		 1349 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1350 if (err < 0)
1da177e4
LT		 1351 return err;
1352
dc9c8e21
WN		 1353 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1354 chip->bus->needs_damn_long_delay = 1;
1355
34c25350 1356 codecs = 0;
2f5983f2
TI		 1357 max_slots = azx_max_codecs[chip->driver_type];
1358 if (!max_slots)
1359 max_slots = AZX_MAX_CODECS;
6ce4a3bc
TI		 1360
1361 /* First try to probe all given codec slots */
1362 for (c = 0; c < max_slots; c++) {
f1eaaeec 1363 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1364 if (probe_codec(chip, c) < 0) {
1365 /* Some BIOSen give you wrong codec addresses
1366 * that don't exist
1367 */
4abc1cc2
TI		 1368 snd_printk(KERN_WARNING SFX
1369 "Codec #%d probe error; "
6ce4a3bc
TI		 1370 "disabling it...\n", c);
1371 chip->codec_mask &= ~(1 << c);
1372 /* More badly, accessing to a non-existing
1373 * codec often screws up the controller chip,
1374 * and distrubs the further communications.
1375 * Thus if an error occurs during probing,
1376 * better to reset the controller chip to
1377 * get back to the sanity state.
1378 */
1379 azx_stop_chip(chip);
1380 azx_init_chip(chip);
1381 }
1382 }
1383 }
1384
1385 /* Then create codec instances */
34c25350 1386 for (c = 0; c < max_slots; c++) {
f1eaaeec 1387 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1388 struct hda_codec *codec;
d4d9cd03 1389 err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1da177e4
LT		 1390 if (err < 0)
1391 continue;
1392 codecs++;
19a982b6
TI		 1393 }
1394 }
1395 if (!codecs) {
1da177e4
LT		 1396 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1397 return -ENXIO;
1398 }
1399
1400 return 0;
1401}
1402
1403
1404/*
1405 * PCM support
1406 */
1407
1408/* assign a stream for the PCM */
a98f90fd 1409static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 1410{
07e4ca50
TI		 1411 int dev, i, nums;
1412 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1413 dev = chip->playback_index_offset;
1414 nums = chip->playback_streams;
1415 } else {
1416 dev = chip->capture_index_offset;
1417 nums = chip->capture_streams;
1418 }
1419 for (i = 0; i < nums; i++, dev++)
d01ce99f 1420 if (!chip->azx_dev[dev].opened) {
1da177e4
LT		 1421 chip->azx_dev[dev].opened = 1;
1422 return &chip->azx_dev[dev];
1423 }
1424 return NULL;
1425}
1426
1427/* release the assigned stream */
a98f90fd 1428static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1429{
1430 azx_dev->opened = 0;
1431}
1432
a98f90fd 1433static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1434 .info = (SNDRV_PCM_INFO_MMAP |
1435 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1436 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1437 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1438 /* No full-resume yet implemented */
1439 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1440 SNDRV_PCM_INFO_PAUSE |
1441 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1442 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1443 .rates = SNDRV_PCM_RATE_48000,
1444 .rate_min = 48000,
1445 .rate_max = 48000,
1446 .channels_min = 2,
1447 .channels_max = 2,
1448 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1449 .period_bytes_min = 128,
1450 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1451 .periods_min = 2,
1452 .periods_max = AZX_MAX_FRAG,
1453 .fifo_size = 0,
1454};
1455
1456struct azx_pcm {
a98f90fd 1457 struct azx *chip;
1da177e4
LT		 1458 struct hda_codec *codec;
1459 struct hda_pcm_stream *hinfo[2];
1460};
1461
a98f90fd 1462static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1463{
1464 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1465 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1466 struct azx *chip = apcm->chip;
1467 struct azx_dev *azx_dev;
1468 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1469 unsigned long flags;
1470 int err;
1471
62932df8 1472 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1473 azx_dev = azx_assign_device(chip, substream->stream);
1474 if (azx_dev == NULL) {
62932df8 1475 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1476 return -EBUSY;
1477 }
1478 runtime->hw = azx_pcm_hw;
1479 runtime->hw.channels_min = hinfo->channels_min;
1480 runtime->hw.channels_max = hinfo->channels_max;
1481 runtime->hw.formats = hinfo->formats;
1482 runtime->hw.rates = hinfo->rates;
1483 snd_pcm_limit_hw_rates(runtime);
1484 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1485 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1486 128);
1487 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1488 128);
cb53c626 1489 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1490 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1491 if (err < 0) {
1da177e4 1492 azx_release_device(azx_dev);
cb53c626 1493 snd_hda_power_down(apcm->codec);
62932df8 1494 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1495 return err;
1496 }
70d321e6 1497 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1498 /* sanity check */
1499 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1500 snd_BUG_ON(!runtime->hw.channels_max) ||
1501 snd_BUG_ON(!runtime->hw.formats) ||
1502 snd_BUG_ON(!runtime->hw.rates)) {
1503 azx_release_device(azx_dev);
1504 hinfo->ops.close(hinfo, apcm->codec, substream);
1505 snd_hda_power_down(apcm->codec);
1506 mutex_unlock(&chip->open_mutex);
1507 return -EINVAL;
1508 }
1da177e4
LT		 1509 spin_lock_irqsave(&chip->reg_lock, flags);
1510 azx_dev->substream = substream;
1511 azx_dev->running = 0;
1512 spin_unlock_irqrestore(&chip->reg_lock, flags);
1513
1514 runtime->private_data = azx_dev;
850f0e52 1515 snd_pcm_set_sync(substream);
62932df8 1516 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1517 return 0;
1518}
1519
a98f90fd 1520static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1521{
1522 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1523 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1524 struct azx *chip = apcm->chip;
1525 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1526 unsigned long flags;
1527
62932df8 1528 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1529 spin_lock_irqsave(&chip->reg_lock, flags);
1530 azx_dev->substream = NULL;
1531 azx_dev->running = 0;
1532 spin_unlock_irqrestore(&chip->reg_lock, flags);
1533 azx_release_device(azx_dev);
1534 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1535 snd_hda_power_down(apcm->codec);
62932df8 1536 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1537 return 0;
1538}
1539
d01ce99f
TI		 1540static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1541 struct snd_pcm_hw_params *hw_params)
1da177e4 1542{
97b71c94
TI		 1543 struct azx_dev *azx_dev = get_azx_dev(substream);
1544
1545 azx_dev->bufsize = 0;
1546 azx_dev->period_bytes = 0;
1547 azx_dev->format_val = 0;
d01ce99f
TI		 1548 return snd_pcm_lib_malloc_pages(substream,
1549 params_buffer_bytes(hw_params));
1da177e4
LT		 1550}
1551
a98f90fd 1552static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1553{
1554 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1555 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1556 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1557
1558 /* reset BDL address */
1559 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1560 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1561 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1562 azx_dev->bufsize = 0;
1563 azx_dev->period_bytes = 0;
1564 azx_dev->format_val = 0;
1da177e4
LT		 1565
1566 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1567
1568 return snd_pcm_lib_free_pages(substream);
1569}
1570
a98f90fd 1571static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1572{
1573 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1574 struct azx *chip = apcm->chip;
1575 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1576 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1577 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94
TI		 1578 unsigned int bufsize, period_bytes, format_val;
1579 int err;
1da177e4 1580
fa00e046 1581 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1582 format_val = snd_hda_calc_stream_format(runtime->rate,
1583 runtime->channels,
1584 runtime->format,
1585 hinfo->maxbps);
1586 if (!format_val) {
d01ce99f
TI		 1587 snd_printk(KERN_ERR SFX
1588 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1589 runtime->rate, runtime->channels, runtime->format);
1590 return -EINVAL;
1591 }
1592
97b71c94
TI		 1593 bufsize = snd_pcm_lib_buffer_bytes(substream);
1594 period_bytes = snd_pcm_lib_period_bytes(substream);
1595
4abc1cc2 1596 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1597 bufsize, format_val);
1598
1599 if (bufsize != azx_dev->bufsize ||
1600 period_bytes != azx_dev->period_bytes ||
1601 format_val != azx_dev->format_val) {
1602 azx_dev->bufsize = bufsize;
1603 azx_dev->period_bytes = period_bytes;
1604 azx_dev->format_val = format_val;
1605 err = azx_setup_periods(chip, substream, azx_dev);
1606 if (err < 0)
1607 return err;
1608 }
1609
fa00e046
JK		 1610 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1611 (runtime->rate * 2);
1da177e4
LT		 1612 azx_setup_controller(chip, azx_dev);
1613 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1614 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1615 else
1616 azx_dev->fifo_size = 0;
1617
1618 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1619 azx_dev->format_val, substream);
1620}
1621
a98f90fd 1622static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1623{
1624 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1625 struct azx *chip = apcm->chip;
850f0e52
TI		 1626 struct azx_dev *azx_dev;
1627 struct snd_pcm_substream *s;
fa00e046 1628 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1629 int nwait, timeout;
1da177e4 1630
1da177e4 1631 switch (cmd) {
fa00e046
JK		 1632 case SNDRV_PCM_TRIGGER_START:
1633 rstart = 1;
1da177e4
LT		 1634 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1635 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1636 start = 1;
1da177e4
LT		 1637 break;
1638 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1639 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1640 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1641 start = 0;
1da177e4
LT		 1642 break;
1643 default:
850f0e52
TI		 1644 return -EINVAL;
1645 }
1646
1647 snd_pcm_group_for_each_entry(s, substream) {
1648 if (s->pcm->card != substream->pcm->card)
1649 continue;
1650 azx_dev = get_azx_dev(s);
1651 sbits |= 1 << azx_dev->index;
1652 nsync++;
1653 snd_pcm_trigger_done(s, substream);
1654 }
1655
1656 spin_lock(&chip->reg_lock);
1657 if (nsync > 1) {
1658 /* first, set SYNC bits of corresponding streams */
1659 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1660 }
1661 snd_pcm_group_for_each_entry(s, substream) {
1662 if (s->pcm->card != substream->pcm->card)
1663 continue;
1664 azx_dev = get_azx_dev(s);
fa00e046
JK		 1665 if (rstart) {
1666 azx_dev->start_flag = 1;
1667 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1668 }
850f0e52
TI		 1669 if (start)
1670 azx_stream_start(chip, azx_dev);
1671 else
1672 azx_stream_stop(chip, azx_dev);
1673 azx_dev->running = start;
1da177e4
LT		 1674 }
1675 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1676 if (start) {
1677 if (nsync == 1)
1678 return 0;
1679 /* wait until all FIFOs get ready */
1680 for (timeout = 5000; timeout; timeout--) {
1681 nwait = 0;
1682 snd_pcm_group_for_each_entry(s, substream) {
1683 if (s->pcm->card != substream->pcm->card)
1684 continue;
1685 azx_dev = get_azx_dev(s);
1686 if (!(azx_sd_readb(azx_dev, SD_STS) &
1687 SD_STS_FIFO_READY))
1688 nwait++;
1689 }
1690 if (!nwait)
1691 break;
1692 cpu_relax();
1693 }
1694 } else {
1695 /* wait until all RUN bits are cleared */
1696 for (timeout = 5000; timeout; timeout--) {
1697 nwait = 0;
1698 snd_pcm_group_for_each_entry(s, substream) {
1699 if (s->pcm->card != substream->pcm->card)
1700 continue;
1701 azx_dev = get_azx_dev(s);
1702 if (azx_sd_readb(azx_dev, SD_CTL) &
1703 SD_CTL_DMA_START)
1704 nwait++;
1705 }
1706 if (!nwait)
1707 break;
1708 cpu_relax();
1709 }
1da177e4 1710 }
850f0e52
TI		 1711 if (nsync > 1) {
1712 spin_lock(&chip->reg_lock);
1713 /* reset SYNC bits */
1714 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1715 spin_unlock(&chip->reg_lock);
1716 }
1717 return 0;
1da177e4
LT		 1718}
1719
0e153474
JC		 1720/* get the current DMA position with correction on VIA chips */
1721static unsigned int azx_via_get_position(struct azx *chip,
1722 struct azx_dev *azx_dev)
1723{
1724 unsigned int link_pos, mini_pos, bound_pos;
1725 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1726 unsigned int fifo_size;
1727
1728 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1729 if (azx_dev->index >= 4) {
1730 /* Playback, no problem using link position */
1731 return link_pos;
1732 }
1733
1734 /* Capture */
1735 /* For new chipset,
1736 * use mod to get the DMA position just like old chipset
1737 */
1738 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1739 mod_dma_pos %= azx_dev->period_bytes;
1740
1741 /* azx_dev->fifo_size can't get FIFO size of in stream.
1742 * Get from base address + offset.
1743 */
1744 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1745
1746 if (azx_dev->insufficient) {
1747 /* Link position never gather than FIFO size */
1748 if (link_pos <= fifo_size)
1749 return 0;
1750
1751 azx_dev->insufficient = 0;
1752 }
1753
1754 if (link_pos <= fifo_size)
1755 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1756 else
1757 mini_pos = link_pos - fifo_size;
1758
1759 /* Find nearest previous boudary */
1760 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1761 mod_link_pos = link_pos % azx_dev->period_bytes;
1762 if (mod_link_pos >= fifo_size)
1763 bound_pos = link_pos - mod_link_pos;
1764 else if (mod_dma_pos >= mod_mini_pos)
1765 bound_pos = mini_pos - mod_mini_pos;
1766 else {
1767 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1768 if (bound_pos >= azx_dev->bufsize)
1769 bound_pos = 0;
1770 }
1771
1772 /* Calculate real DMA position we want */
1773 return bound_pos + mod_dma_pos;
1774}
1775
9ad593f6
TI		 1776static unsigned int azx_get_position(struct azx *chip,
1777 struct azx_dev *azx_dev)
1da177e4 1778{
1da177e4
LT		 1779 unsigned int pos;
1780
0e153474
JC		 1781 if (chip->via_dmapos_patch)
1782 pos = azx_via_get_position(chip, azx_dev);
1783 else if (chip->position_fix == POS_FIX_POSBUF ||
1784 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1785 /* use the position buffer */
929861c6 1786 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1787 } else {
1788 /* read LPIB */
1789 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1790 }
1da177e4
LT		 1791 if (pos >= azx_dev->bufsize)
1792 pos = 0;
9ad593f6
TI		 1793 return pos;
1794}
1795
1796static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1797{
1798 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1799 struct azx *chip = apcm->chip;
1800 struct azx_dev *azx_dev = get_azx_dev(substream);
1801 return bytes_to_frames(substream->runtime,
1802 azx_get_position(chip, azx_dev));
1803}
1804
1805/*
1806 * Check whether the current DMA position is acceptable for updating
1807 * periods. Returns non-zero if it's OK.
1808 *
1809 * Many HD-audio controllers appear pretty inaccurate about
1810 * the update-IRQ timing. The IRQ is issued before actually the
1811 * data is processed. So, we need to process it afterwords in a
1812 * workqueue.
1813 */
1814static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1815{
1816 unsigned int pos;
1817
fa00e046
JK		 1818 if (azx_dev->start_flag &&
1819 time_before_eq(jiffies, azx_dev->start_jiffies))
1820 return -1; /* bogus (too early) interrupt */
1821 azx_dev->start_flag = 0;
1822
9ad593f6
TI		 1823 pos = azx_get_position(chip, azx_dev);
1824 if (chip->position_fix == POS_FIX_AUTO) {
1825 if (!pos) {
1826 printk(KERN_WARNING
1827 "hda-intel: Invalid position buffer, "
1828 "using LPIB read method instead.\n");
d2e1c973 1829 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1830 pos = azx_get_position(chip, azx_dev);
1831 } else
1832 chip->position_fix = POS_FIX_POSBUF;
1833 }
1834
a62741cf
TI		 1835 if (!bdl_pos_adj[chip->dev_index])
1836 return 1; /* no delayed ack */
9ad593f6
TI		 1837 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1838 return 0; /* NG - it's below the period boundary */
1839 return 1; /* OK, it's fine */
1840}
1841
1842/*
1843 * The work for pending PCM period updates.
1844 */
1845static void azx_irq_pending_work(struct work_struct *work)
1846{
1847 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1848 int i, pending;
1849
a6a950a8
TI		 1850 if (!chip->irq_pending_warned) {
1851 printk(KERN_WARNING
1852 "hda-intel: IRQ timing workaround is activated "
1853 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1854 chip->card->number);
1855 chip->irq_pending_warned = 1;
1856 }
1857
9ad593f6
TI		 1858 for (;;) {
1859 pending = 0;
1860 spin_lock_irq(&chip->reg_lock);
1861 for (i = 0; i < chip->num_streams; i++) {
1862 struct azx_dev *azx_dev = &chip->azx_dev[i];
1863 if (!azx_dev->irq_pending ||
1864 !azx_dev->substream ||
1865 !azx_dev->running)
1866 continue;
1867 if (azx_position_ok(chip, azx_dev)) {
1868 azx_dev->irq_pending = 0;
1869 spin_unlock(&chip->reg_lock);
1870 snd_pcm_period_elapsed(azx_dev->substream);
1871 spin_lock(&chip->reg_lock);
1872 } else
1873 pending++;
1874 }
1875 spin_unlock_irq(&chip->reg_lock);
1876 if (!pending)
1877 return;
1878 cond_resched();
1879 }
1880}
1881
1882/* clear irq_pending flags and assure no on-going workq */
1883static void azx_clear_irq_pending(struct azx *chip)
1884{
1885 int i;
1886
1887 spin_lock_irq(&chip->reg_lock);
1888 for (i = 0; i < chip->num_streams; i++)
1889 chip->azx_dev[i].irq_pending = 0;
1890 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1891}
1892
a98f90fd 1893static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1894 .open = azx_pcm_open,
1895 .close = azx_pcm_close,
1896 .ioctl = snd_pcm_lib_ioctl,
1897 .hw_params = azx_pcm_hw_params,
1898 .hw_free = azx_pcm_hw_free,
1899 .prepare = azx_pcm_prepare,
1900 .trigger = azx_pcm_trigger,
1901 .pointer = azx_pcm_pointer,
4ce107b9 1902 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1903};
1904
a98f90fd 1905static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 1906{
176d5335
TI		 1907 struct azx_pcm *apcm = pcm->private_data;
1908 if (apcm) {
1909 apcm->chip->pcm[pcm->device] = NULL;
1910 kfree(apcm);
1911 }
1da177e4
LT		 1912}
1913
176d5335 1914static int
33fa35ed
TI		 1915azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1916 struct hda_pcm *cpcm)
1da177e4 1917{
33fa35ed 1918 struct azx *chip = bus->private_data;
a98f90fd 1919 struct snd_pcm *pcm;
1da177e4 1920 struct azx_pcm *apcm;
176d5335
TI		 1921 int pcm_dev = cpcm->device;
1922 int s, err;
1da177e4 1923
176d5335
TI		 1924 if (pcm_dev >= AZX_MAX_PCMS) {
1925 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1926 pcm_dev);
da3cec35 1927 return -EINVAL;
176d5335
TI		 1928 }
1929 if (chip->pcm[pcm_dev]) {
1930 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1931 return -EBUSY;
1932 }
1933 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1934 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1935 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 1936 &pcm);
1937 if (err < 0)
1938 return err;
18cb7109 1939 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 1940 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 1941 if (apcm == NULL)
1942 return -ENOMEM;
1943 apcm->chip = chip;
1944 apcm->codec = codec;
1da177e4
LT		 1945 pcm->private_data = apcm;
1946 pcm->private_free = azx_pcm_free;
176d5335
TI		 1947 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1948 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1949 chip->pcm[pcm_dev] = pcm;
1950 cpcm->pcm = pcm;
1951 for (s = 0; s < 2; s++) {
1952 apcm->hinfo[s] = &cpcm->stream[s];
1953 if (cpcm->stream[s].substreams)
1954 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1955 }
1956 /* buffer pre-allocation */
4ce107b9 1957 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 1958 snd_dma_pci_data(chip->pci),
fc4abee8 1959 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 1960 return 0;
1961}
1962
1963/*
1964 * mixer creation - all stuff is implemented in hda module
1965 */
a98f90fd 1966static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 1967{
1968 return snd_hda_build_controls(chip->bus);
1969}
1970
1971
1972/*
1973 * initialize SD streams
1974 */
a98f90fd 1975static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 1976{
1977 int i;
1978
1979 /* initialize each stream (aka device)
d01ce99f
TI		 1980 * assign the starting bdl address to each stream (device)
1981 * and initialize
1da177e4 1982 */
07e4ca50 1983 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1984 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 1985 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 1986 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1987 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1988 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1989 azx_dev->sd_int_sta_mask = 1 << i;
1990 /* stream tag: must be non-zero and unique */
1991 azx_dev->index = i;
1992 azx_dev->stream_tag = i + 1;
1993 }
1994
1995 return 0;
1996}
1997
68e7fffc
TI		 1998static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1999{
437a5a46
TI		 2000 if (request_irq(chip->pci->irq, azx_interrupt,
2001 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI		 2002 "HDA Intel", chip)) {
2003 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2004 "disabling device\n", chip->pci->irq);
2005 if (do_disconnect)
2006 snd_card_disconnect(chip->card);
2007 return -1;
2008 }
2009 chip->irq = chip->pci->irq;
69e13418 2010 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2011 return 0;
2012}
2013
1da177e4 2014
cb53c626
TI		 2015static void azx_stop_chip(struct azx *chip)
2016{
95e99fda 2017 if (!chip->initialized)
cb53c626
TI		 2018 return;
2019
2020 /* disable interrupts */
2021 azx_int_disable(chip);
2022 azx_int_clear(chip);
2023
2024 /* disable CORB/RIRB */
2025 azx_free_cmd_io(chip);
2026
2027 /* disable position buffer */
2028 azx_writel(chip, DPLBASE, 0);
2029 azx_writel(chip, DPUBASE, 0);
2030
2031 chip->initialized = 0;
2032}
2033
2034#ifdef CONFIG_SND_HDA_POWER_SAVE
2035/* power-up/down the controller */
33fa35ed 2036static void azx_power_notify(struct hda_bus *bus)
cb53c626 2037{
33fa35ed 2038 struct azx *chip = bus->private_data;
cb53c626
TI		 2039 struct hda_codec *c;
2040 int power_on = 0;
2041
33fa35ed 2042 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2043 if (c->power_on) {
2044 power_on = 1;
2045 break;
2046 }
2047 }
2048 if (power_on)
2049 azx_init_chip(chip);
dee1b66c 2050 else if (chip->running && power_save_controller)
cb53c626 2051 azx_stop_chip(chip);
cb53c626 2052}
5c0b9bec
TI		 2053#endif /* CONFIG_SND_HDA_POWER_SAVE */
2054
2055#ifdef CONFIG_PM
2056/*
2057 * power management
2058 */
986862bd
TI		 2059
2060static int snd_hda_codecs_inuse(struct hda_bus *bus)
2061{
2062 struct hda_codec *codec;
2063
2064 list_for_each_entry(codec, &bus->codec_list, list) {
2065 if (snd_hda_codec_needs_resume(codec))
2066 return 1;
2067 }
2068 return 0;
2069}
cb53c626 2070
421a1252 2071static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2072{
421a1252
TI		 2073 struct snd_card *card = pci_get_drvdata(pci);
2074 struct azx *chip = card->private_data;
1da177e4
LT		 2075 int i;
2076
421a1252 2077 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2078 azx_clear_irq_pending(chip);
7ba72ba1 2079 for (i = 0; i < AZX_MAX_PCMS; i++)
421a1252 2080 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c 2081 if (chip->initialized)
8dd78330 2082 snd_hda_suspend(chip->bus);
cb53c626 2083 azx_stop_chip(chip);
30b35399 2084 if (chip->irq >= 0) {
43001c95 2085 free_irq(chip->irq, chip);
30b35399
TI		 2086 chip->irq = -1;
2087 }
68e7fffc 2088 if (chip->msi)
43001c95 2089 pci_disable_msi(chip->pci);
421a1252
TI		 2090 pci_disable_device(pci);
2091 pci_save_state(pci);
30b35399 2092 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2093 return 0;
2094}
2095
421a1252 2096static int azx_resume(struct pci_dev *pci)
1da177e4 2097{
421a1252
TI		 2098 struct snd_card *card = pci_get_drvdata(pci);
2099 struct azx *chip = card->private_data;
1da177e4 2100
d14a7e0b
TI		 2101 pci_set_power_state(pci, PCI_D0);
2102 pci_restore_state(pci);
30b35399
TI		 2103 if (pci_enable_device(pci) < 0) {
2104 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2105 "disabling device\n");
2106 snd_card_disconnect(card);
2107 return -EIO;
2108 }
2109 pci_set_master(pci);
68e7fffc
TI		 2110 if (chip->msi)
2111 if (pci_enable_msi(pci) < 0)
2112 chip->msi = 0;
2113 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2114 return -EIO;
cb53c626 2115 azx_init_pci(chip);
d804ad92
ML		 2116
2117 if (snd_hda_codecs_inuse(chip->bus))
2118 azx_init_chip(chip);
2119
1da177e4 2120 snd_hda_resume(chip->bus);
421a1252 2121 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2122 return 0;
2123}
2124#endif /* CONFIG_PM */
2125
2126
0cbf0098
TI		 2127/*
2128 * reboot notifier for hang-up problem at power-down
2129 */
2130static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2131{
2132 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2133 azx_stop_chip(chip);
2134 return NOTIFY_OK;
2135}
2136
2137static void azx_notifier_register(struct azx *chip)
2138{
2139 chip->reboot_notifier.notifier_call = azx_halt;
2140 register_reboot_notifier(&chip->reboot_notifier);
2141}
2142
2143static void azx_notifier_unregister(struct azx *chip)
2144{
2145 if (chip->reboot_notifier.notifier_call)
2146 unregister_reboot_notifier(&chip->reboot_notifier);
2147}
2148
1da177e4
LT		 2149/*
2150 * destructor
2151 */
a98f90fd 2152static int azx_free(struct azx *chip)
1da177e4 2153{
4ce107b9
TI		 2154 int i;
2155
0cbf0098
TI		 2156 azx_notifier_unregister(chip);
2157
ce43fbae 2158 if (chip->initialized) {
9ad593f6 2159 azx_clear_irq_pending(chip);
07e4ca50 2160 for (i = 0; i < chip->num_streams; i++)
1da177e4 2161 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2162 azx_stop_chip(chip);
1da177e4
LT		 2163 }
2164
f000fd80 2165 if (chip->irq >= 0)
1da177e4 2166 free_irq(chip->irq, (void*)chip);
68e7fffc 2167 if (chip->msi)
30b35399 2168 pci_disable_msi(chip->pci);
f079c25a
TI		 2169 if (chip->remap_addr)
2170 iounmap(chip->remap_addr);
1da177e4 2171
4ce107b9
TI		 2172 if (chip->azx_dev) {
2173 for (i = 0; i < chip->num_streams; i++)
2174 if (chip->azx_dev[i].bdl.area)
2175 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2176 }
1da177e4
LT		 2177 if (chip->rb.area)
2178 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2179 if (chip->posbuf.area)
2180 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2181 pci_release_regions(chip->pci);
2182 pci_disable_device(chip->pci);
07e4ca50 2183 kfree(chip->azx_dev);
1da177e4
LT		 2184 kfree(chip);
2185
2186 return 0;
2187}
2188
a98f90fd 2189static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2190{
2191 return azx_free(device->device_data);
2192}
2193
3372a153
TI		 2194/*
2195 * white/black-listing for position_fix
2196 */
623ec047 2197static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2198 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2199 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2200 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3372a153
TI		 2201 {}
2202};
2203
2204static int __devinit check_position_fix(struct azx *chip, int fix)
2205{
2206 const struct snd_pci_quirk *q;
2207
c673ba1c
TI		 2208 switch (fix) {
2209 case POS_FIX_LPIB:
2210 case POS_FIX_POSBUF:
2211 return fix;
2212 }
2213
2214 /* Check VIA/ATI HD Audio Controller exist */
2215 switch (chip->driver_type) {
2216 case AZX_DRIVER_VIA:
2217 case AZX_DRIVER_ATI:
0e153474
JC		 2218 chip->via_dmapos_patch = 1;
2219 /* Use link position directly, avoid any transfer problem. */
2220 return POS_FIX_LPIB;
2221 }
2222 chip->via_dmapos_patch = 0;
2223
c673ba1c
TI		 2224 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2225 if (q) {
2226 printk(KERN_INFO
2227 "hda_intel: position_fix set to %d "
2228 "for device %04x:%04x\n",
2229 q->value, q->subvendor, q->subdevice);
2230 return q->value;
3372a153 2231 }
c673ba1c 2232 return POS_FIX_AUTO;
3372a153
TI		 2233}
2234
669ba27a
TI		 2235/*
2236 * black-lists for probe_mask
2237 */
2238static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2239 /* Thinkpad often breaks the controller communication when accessing
2240 * to the non-working (or non-existing) modem codec slot.
2241 */
2242 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2243 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2244 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2245 /* broken BIOS */
2246 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2247 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2248 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2249 /* forced codec slots */
93574844 2250 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2251 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2252 {}
2253};
2254
f1eaaeec
TI		 2255#define AZX_FORCE_CODEC_MASK 0x100
2256
5aba4f8e 2257static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2258{
2259 const struct snd_pci_quirk *q;
2260
f1eaaeec
TI		 2261 chip->codec_probe_mask = probe_mask[dev];
2262 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2263 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2264 if (q) {
2265 printk(KERN_INFO
2266 "hda_intel: probe_mask set to 0x%x "
2267 "for device %04x:%04x\n",
2268 q->value, q->subvendor, q->subdevice);
f1eaaeec 2269 chip->codec_probe_mask = q->value;
669ba27a
TI		 2270 }
2271 }
f1eaaeec
TI		 2272
2273 /* check forced option */
2274 if (chip->codec_probe_mask != -1 &&
2275 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2276 chip->codec_mask = chip->codec_probe_mask & 0xff;
2277 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2278 chip->codec_mask);
2279 }
669ba27a
TI		 2280}
2281
2282
1da177e4
LT		 2283/*
2284 * constructor
2285 */
a98f90fd 2286static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2287 int dev, int driver_type,
a98f90fd 2288 struct azx **rchip)
1da177e4 2289{
a98f90fd 2290 struct azx *chip;
4ce107b9 2291 int i, err;
bcd72003 2292 unsigned short gcap;
a98f90fd 2293 static struct snd_device_ops ops = {
1da177e4
LT		 2294 .dev_free = azx_dev_free,
2295 };
2296
2297 *rchip = NULL;
bcd72003 2298
927fc866
PM		 2299 err = pci_enable_device(pci);
2300 if (err < 0)
1da177e4
LT		 2301 return err;
2302
e560d8d8 2303 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2304 if (!chip) {
1da177e4
LT		 2305 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2306 pci_disable_device(pci);
2307 return -ENOMEM;
2308 }
2309
2310 spin_lock_init(&chip->reg_lock);
62932df8 2311 mutex_init(&chip->open_mutex);
1da177e4
LT		 2312 chip->card = card;
2313 chip->pci = pci;
2314 chip->irq = -1;
07e4ca50 2315 chip->driver_type = driver_type;
134a11f0 2316 chip->msi = enable_msi;
555e219f 2317 chip->dev_index = dev;
9ad593f6 2318 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2319
5aba4f8e
TI		 2320 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2321 check_probe_mask(chip, dev);
3372a153 2322
27346166 2323 chip->single_cmd = single_cmd;
c74db86b 2324
5c0d7bc1
TI		 2325 if (bdl_pos_adj[dev] < 0) {
2326 switch (chip->driver_type) {
0c6341ac
TI		 2327 case AZX_DRIVER_ICH:
2328 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2329 break;
2330 default:
0c6341ac 2331 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2332 break;
2333 }
2334 }
2335
07e4ca50
TI		 2336#if BITS_PER_LONG != 64
2337 /* Fix up base address on ULI M5461 */
2338 if (chip->driver_type == AZX_DRIVER_ULI) {
2339 u16 tmp3;
2340 pci_read_config_word(pci, 0x40, &tmp3);
2341 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2342 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2343 }
2344#endif
2345
927fc866
PM		 2346 err = pci_request_regions(pci, "ICH HD audio");
2347 if (err < 0) {
1da177e4
LT		 2348 kfree(chip);
2349 pci_disable_device(pci);
2350 return err;
2351 }
2352
927fc866 2353 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2354 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2355 if (chip->remap_addr == NULL) {
2356 snd_printk(KERN_ERR SFX "ioremap error\n");
2357 err = -ENXIO;
2358 goto errout;
2359 }
2360
68e7fffc
TI		 2361 if (chip->msi)
2362 if (pci_enable_msi(pci) < 0)
2363 chip->msi = 0;
7376d013 2364
68e7fffc 2365 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2366 err = -EBUSY;
2367 goto errout;
2368 }
1da177e4
LT		 2369
2370 pci_set_master(pci);
2371 synchronize_irq(chip->irq);
2372
bcd72003 2373 gcap = azx_readw(chip, GCAP);
4abc1cc2 2374 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2375
dc4c2e6b
AB		 2376 /* disable SB600 64bit support for safety */
2377 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2378 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2379 struct pci_dev *p_smbus;
2380 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2381 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2382 NULL);
2383 if (p_smbus) {
2384 if (p_smbus->revision < 0x30)
2385 gcap &= ~ICH6_GCAP_64OK;
2386 pci_dev_put(p_smbus);
2387 }
2388 }
09240cf4 2389
cf7aaca8 2390 /* allow 64bit DMA address if supported by H/W */
b21fadb9 2391 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 2392 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 2393 else {
e930438c
YH		 2394 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2395 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 2396 }
cf7aaca8 2397
8b6ed8e7
TI		 2398 /* read number of streams from GCAP register instead of using
2399 * hardcoded value
2400 */
2401 chip->capture_streams = (gcap >> 8) & 0x0f;
2402 chip->playback_streams = (gcap >> 12) & 0x0f;
2403 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2404 /* gcap didn't give any info, switching to old method */
2405
2406 switch (chip->driver_type) {
2407 case AZX_DRIVER_ULI:
2408 chip->playback_streams = ULI_NUM_PLAYBACK;
2409 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2410 break;
2411 case AZX_DRIVER_ATIHDMI:
2412 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2413 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2414 break;
c4da29ca 2415 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2416 default:
2417 chip->playback_streams = ICH6_NUM_PLAYBACK;
2418 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2419 break;
2420 }
07e4ca50 2421 }
8b6ed8e7
TI		 2422 chip->capture_index_offset = 0;
2423 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2424 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2425 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2426 GFP_KERNEL);
927fc866 2427 if (!chip->azx_dev) {
4abc1cc2 2428 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
07e4ca50
TI		 2429 goto errout;
2430 }
2431
4ce107b9
TI		 2432 for (i = 0; i < chip->num_streams; i++) {
2433 /* allocate memory for the BDL for each stream */
2434 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2435 snd_dma_pci_data(chip->pci),
2436 BDL_SIZE, &chip->azx_dev[i].bdl);
2437 if (err < 0) {
2438 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2439 goto errout;
2440 }
1da177e4 2441 }
0be3b5d3 2442 /* allocate memory for the position buffer */
d01ce99f
TI		 2443 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2444 snd_dma_pci_data(chip->pci),
2445 chip->num_streams * 8, &chip->posbuf);
2446 if (err < 0) {
0be3b5d3
TI		 2447 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2448 goto errout;
1da177e4 2449 }
1da177e4 2450 /* allocate CORB/RIRB */
81740861
TI		 2451 err = azx_alloc_cmd_io(chip);
2452 if (err < 0)
2453 goto errout;
1da177e4
LT		 2454
2455 /* initialize streams */
2456 azx_init_stream(chip);
2457
2458 /* initialize chip */
cb53c626 2459 azx_init_pci(chip);
1da177e4
LT		 2460 azx_init_chip(chip);
2461
2462 /* codec detection */
927fc866 2463 if (!chip->codec_mask) {
1da177e4
LT		 2464 snd_printk(KERN_ERR SFX "no codecs found!\n");
2465 err = -ENODEV;
2466 goto errout;
2467 }
2468
d01ce99f
TI		 2469 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2470 if (err <0) {
1da177e4
LT		 2471 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2472 goto errout;
2473 }
2474
07e4ca50 2475 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2476 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2477 sizeof(card->shortname));
2478 snprintf(card->longname, sizeof(card->longname),
2479 "%s at 0x%lx irq %i",
2480 card->shortname, chip->addr, chip->irq);
07e4ca50 2481
1da177e4
LT		 2482 *rchip = chip;
2483 return 0;
2484
2485 errout:
2486 azx_free(chip);
2487 return err;
2488}
2489
cb53c626
TI		 2490static void power_down_all_codecs(struct azx *chip)
2491{
2492#ifdef CONFIG_SND_HDA_POWER_SAVE
2493 /* The codecs were powered up in snd_hda_codec_new().
2494 * Now all initialization done, so turn them down if possible
2495 */
2496 struct hda_codec *codec;
2497 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2498 snd_hda_power_down(codec);
2499 }
2500#endif
2501}
2502
d01ce99f
TI		 2503static int __devinit azx_probe(struct pci_dev *pci,
2504 const struct pci_device_id *pci_id)
1da177e4 2505{
5aba4f8e 2506 static int dev;
a98f90fd
TI		 2507 struct snd_card *card;
2508 struct azx *chip;
927fc866 2509 int err;
1da177e4 2510
5aba4f8e
TI		 2511 if (dev >= SNDRV_CARDS)
2512 return -ENODEV;
2513 if (!enable[dev]) {
2514 dev++;
2515 return -ENOENT;
2516 }
2517
e58de7ba
TI		 2518 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2519 if (err < 0) {
1da177e4 2520 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 2521 return err;
1da177e4
LT		 2522 }
2523
5aba4f8e 2524 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2525 if (err < 0)
2526 goto out_free;
421a1252 2527 card->private_data = chip;
1da177e4 2528
1da177e4 2529 /* create codec instances */
f1eaaeec 2530 err = azx_codec_create(chip, model[dev], probe_only[dev]);
41dda0fd
WF		 2531 if (err < 0)
2532 goto out_free;
1da177e4
LT		 2533
2534 /* create PCM streams */
176d5335 2535 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2536 if (err < 0)
2537 goto out_free;
1da177e4
LT		 2538
2539 /* create mixer controls */
d01ce99f 2540 err = azx_mixer_create(chip);
41dda0fd
WF		 2541 if (err < 0)
2542 goto out_free;
1da177e4 2543
1da177e4
LT		 2544 snd_card_set_dev(card, &pci->dev);
2545
d01ce99f 2546 err = snd_card_register(card);
41dda0fd
WF		 2547 if (err < 0)
2548 goto out_free;
1da177e4
LT		 2549
2550 pci_set_drvdata(pci, card);
cb53c626
TI		 2551 chip->running = 1;
2552 power_down_all_codecs(chip);
0cbf0098 2553 azx_notifier_register(chip);
1da177e4 2554
e25bcdba 2555 dev++;
1da177e4 2556 return err;
41dda0fd
WF		 2557out_free:
2558 snd_card_free(card);
2559 return err;
1da177e4
LT		 2560}
2561
2562static void __devexit azx_remove(struct pci_dev *pci)
2563{
2564 snd_card_free(pci_get_drvdata(pci));
2565 pci_set_drvdata(pci, NULL);
2566}
2567
2568/* PCI IDs */
f40b6890 2569static struct pci_device_id azx_ids[] = {
87218e9c
TI		 2570 /* ICH 6..10 */
2571 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2572 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2573 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2574 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2575 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2576 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2577 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2578 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2579 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
b29c2360
SH		 2580 /* PCH */
2581 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2582 /* SCH */
2583 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2584 /* ATI SB 450/600 */
2585 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2586 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2587 /* ATI HDMI */
2588 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2589 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2590 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2591 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2592 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2593 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2594 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2595 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2596 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2597 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2598 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2599 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2600 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2601 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2602 /* VIA VT8251/VT8237A */
2603 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2604 /* SIS966 */
2605 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2606 /* ULI M5461 */
2607 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2608 /* NVIDIA MCP */
2609 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2610 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2611 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2612 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2613 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2614 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2615 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2616 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2617 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2618 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2619 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2620 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2621 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2622 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2623 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2624 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2625 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2626 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
bedfcebb 2627 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2628 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2629 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2630 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2631 /* Teradici */
2632 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
4e01f54b 2633 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 2634#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2635 /* the following entry conflicts with snd-ctxfi driver,
2636 * as ctxfi driver mutates from HD-audio to native mode with
2637 * a special command sequence.
2638 */
4e01f54b
TI		 2639 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2640 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2641 .class_mask = 0xffffff,
2642 .driver_data = AZX_DRIVER_GENERIC },
313f6e2d
TI		 2643#else
2644 /* this entry seems still valid -- i.e. without emu20kx chip */
2645 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2646#endif
c4da29ca
YL		 2647 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2648 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2649 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2650 .class_mask = 0xffffff,
2651 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2652 { 0, }
2653};
2654MODULE_DEVICE_TABLE(pci, azx_ids);
2655
2656/* pci_driver definition */
2657static struct pci_driver driver = {
2658 .name = "HDA Intel",
2659 .id_table = azx_ids,
2660 .probe = azx_probe,
2661 .remove = __devexit_p(azx_remove),
421a1252
TI		 2662#ifdef CONFIG_PM
2663 .suspend = azx_suspend,
2664 .resume = azx_resume,
2665#endif
1da177e4
LT		 2666};
2667
2668static int __init alsa_card_azx_init(void)
2669{
01d25d46 2670 return pci_register_driver(&driver);
1da177e4
LT		 2671}
2672
2673static void __exit alsa_card_azx_exit(void)
2674{
2675 pci_unregister_driver(&driver);
2676}
2677
2678module_init(alsa_card_azx_init)
2679module_exit(alsa_card_azx_exit)
Linux 6.x block layer and io_uring tree(s)