Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
d01ce99f TI |
3 | * hda_intel.c - Implementation of primary alsa driver code base |
4 | * for Intel HD Audio. | |
1da177e4 LT |
5 | * |
6 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
7 | * | |
8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
9 | * PeiSen Hou <pshou@realtek.com.tw> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the Free | |
13 | * Software Foundation; either version 2 of the License, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along with | |
22 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
23 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
24 | * | |
25 | * CONTACTS: | |
26 | * | |
27 | * Matt Jared matt.jared@intel.com | |
28 | * Andy Kopp andy.kopp@intel.com | |
29 | * Dan Kogan dan.d.kogan@intel.com | |
30 | * | |
31 | * CHANGES: | |
32 | * | |
33 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | |
34 | * | |
35 | */ | |
36 | ||
1da177e4 LT |
37 | #include <asm/io.h> |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
362775e2 | 40 | #include <linux/kernel.h> |
1da177e4 | 41 | #include <linux/module.h> |
24982c5f | 42 | #include <linux/dma-mapping.h> |
1da177e4 LT |
43 | #include <linux/moduleparam.h> |
44 | #include <linux/init.h> | |
45 | #include <linux/slab.h> | |
46 | #include <linux/pci.h> | |
62932df8 | 47 | #include <linux/mutex.h> |
0cbf0098 | 48 | #include <linux/reboot.h> |
1da177e4 LT |
49 | #include <sound/core.h> |
50 | #include <sound/initval.h> | |
51 | #include "hda_codec.h" | |
52 | ||
53 | ||
5aba4f8e TI |
54 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; |
55 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | |
56 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; | |
57 | static char *model[SNDRV_CARDS]; | |
58 | static int position_fix[SNDRV_CARDS]; | |
5c0d7bc1 | 59 | static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
5aba4f8e | 60 | static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
d4d9cd03 | 61 | static int probe_only[SNDRV_CARDS]; |
27346166 | 62 | static int single_cmd; |
71623855 | 63 | static int enable_msi = -1; |
4ea6fbc8 TI |
64 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
65 | static char *patch[SNDRV_CARDS]; | |
66 | #endif | |
2dca0bba JK |
67 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
68 | static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = | |
69 | CONFIG_SND_HDA_INPUT_BEEP_MODE}; | |
70 | #endif | |
1da177e4 | 71 | |
5aba4f8e | 72 | module_param_array(index, int, NULL, 0444); |
1da177e4 | 73 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
5aba4f8e | 74 | module_param_array(id, charp, NULL, 0444); |
1da177e4 | 75 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
5aba4f8e TI |
76 | module_param_array(enable, bool, NULL, 0444); |
77 | MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); | |
78 | module_param_array(model, charp, NULL, 0444); | |
1da177e4 | 79 | MODULE_PARM_DESC(model, "Use the given board model."); |
5aba4f8e | 80 | module_param_array(position_fix, int, NULL, 0444); |
d01ce99f | 81 | MODULE_PARM_DESC(position_fix, "Fix DMA pointer " |
d2e1c973 | 82 | "(0 = auto, 1 = none, 2 = POSBUF)."); |
555e219f TI |
83 | module_param_array(bdl_pos_adj, int, NULL, 0644); |
84 | MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); | |
5aba4f8e | 85 | module_param_array(probe_mask, int, NULL, 0444); |
606ad75f | 86 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); |
079e683e | 87 | module_param_array(probe_only, int, NULL, 0444); |
d4d9cd03 | 88 | MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); |
27346166 | 89 | module_param(single_cmd, bool, 0444); |
d01ce99f TI |
90 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " |
91 | "(for debugging only)."); | |
5aba4f8e | 92 | module_param(enable_msi, int, 0444); |
134a11f0 | 93 | MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); |
4ea6fbc8 TI |
94 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
95 | module_param_array(patch, charp, NULL, 0444); | |
96 | MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); | |
97 | #endif | |
2dca0bba JK |
98 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
99 | module_param_array(beep_mode, int, NULL, 0444); | |
100 | MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " | |
101 | "(0=off, 1=on, 2=mute switch on/off) (default=1)."); | |
102 | #endif | |
606ad75f | 103 | |
dee1b66c | 104 | #ifdef CONFIG_SND_HDA_POWER_SAVE |
fee2fba3 TI |
105 | static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; |
106 | module_param(power_save, int, 0644); | |
107 | MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " | |
108 | "(in second, 0 = disable)."); | |
1da177e4 | 109 | |
dee1b66c TI |
110 | /* reset the HD-audio controller in power save mode. |
111 | * this may give more power-saving, but will take longer time to | |
112 | * wake up. | |
113 | */ | |
114 | static int power_save_controller = 1; | |
115 | module_param(power_save_controller, bool, 0644); | |
116 | MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); | |
117 | #endif | |
118 | ||
1da177e4 LT |
119 | MODULE_LICENSE("GPL"); |
120 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | |
121 | "{Intel, ICH6M}," | |
2f1b3818 | 122 | "{Intel, ICH7}," |
f5d40b30 | 123 | "{Intel, ESB2}," |
d2981393 | 124 | "{Intel, ICH8}," |
f9cc8a8b | 125 | "{Intel, ICH9}," |
c34f5a04 | 126 | "{Intel, ICH10}," |
b29c2360 | 127 | "{Intel, PCH}," |
d2f2fcd2 | 128 | "{Intel, CPT}," |
cea310e8 | 129 | "{Intel, PBG}," |
4979bca9 | 130 | "{Intel, SCH}," |
fc20a562 | 131 | "{ATI, SB450}," |
89be83f8 | 132 | "{ATI, SB600}," |
778b6e1b | 133 | "{ATI, RS600}," |
5b15c95f | 134 | "{ATI, RS690}," |
e6db1119 WL |
135 | "{ATI, RS780}," |
136 | "{ATI, R600}," | |
2797f724 HRK |
137 | "{ATI, RV630}," |
138 | "{ATI, RV610}," | |
27da1834 WL |
139 | "{ATI, RV670}," |
140 | "{ATI, RV635}," | |
141 | "{ATI, RV620}," | |
142 | "{ATI, RV770}," | |
fc20a562 | 143 | "{VIA, VT8251}," |
47672310 | 144 | "{VIA, VT8237A}," |
07e4ca50 TI |
145 | "{SiS, SIS966}," |
146 | "{ULI, M5461}}"); | |
1da177e4 LT |
147 | MODULE_DESCRIPTION("Intel HDA driver"); |
148 | ||
4abc1cc2 TI |
149 | #ifdef CONFIG_SND_VERBOSE_PRINTK |
150 | #define SFX /* nop */ | |
151 | #else | |
1da177e4 | 152 | #define SFX "hda-intel: " |
4abc1cc2 | 153 | #endif |
cb53c626 | 154 | |
1da177e4 LT |
155 | /* |
156 | * registers | |
157 | */ | |
158 | #define ICH6_REG_GCAP 0x00 | |
b21fadb9 TI |
159 | #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ |
160 | #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ | |
161 | #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ | |
162 | #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ | |
163 | #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ | |
1da177e4 LT |
164 | #define ICH6_REG_VMIN 0x02 |
165 | #define ICH6_REG_VMAJ 0x03 | |
166 | #define ICH6_REG_OUTPAY 0x04 | |
167 | #define ICH6_REG_INPAY 0x06 | |
168 | #define ICH6_REG_GCTL 0x08 | |
8a933ece | 169 | #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ |
b21fadb9 TI |
170 | #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ |
171 | #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ | |
1da177e4 LT |
172 | #define ICH6_REG_WAKEEN 0x0c |
173 | #define ICH6_REG_STATESTS 0x0e | |
174 | #define ICH6_REG_GSTS 0x10 | |
b21fadb9 | 175 | #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ |
1da177e4 LT |
176 | #define ICH6_REG_INTCTL 0x20 |
177 | #define ICH6_REG_INTSTS 0x24 | |
e5463720 | 178 | #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ |
1da177e4 LT |
179 | #define ICH6_REG_SYNC 0x34 |
180 | #define ICH6_REG_CORBLBASE 0x40 | |
181 | #define ICH6_REG_CORBUBASE 0x44 | |
182 | #define ICH6_REG_CORBWP 0x48 | |
b21fadb9 TI |
183 | #define ICH6_REG_CORBRP 0x4a |
184 | #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ | |
1da177e4 | 185 | #define ICH6_REG_CORBCTL 0x4c |
b21fadb9 TI |
186 | #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ |
187 | #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ | |
1da177e4 | 188 | #define ICH6_REG_CORBSTS 0x4d |
b21fadb9 | 189 | #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ |
1da177e4 LT |
190 | #define ICH6_REG_CORBSIZE 0x4e |
191 | ||
192 | #define ICH6_REG_RIRBLBASE 0x50 | |
193 | #define ICH6_REG_RIRBUBASE 0x54 | |
194 | #define ICH6_REG_RIRBWP 0x58 | |
b21fadb9 | 195 | #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ |
1da177e4 LT |
196 | #define ICH6_REG_RINTCNT 0x5a |
197 | #define ICH6_REG_RIRBCTL 0x5c | |
b21fadb9 TI |
198 | #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ |
199 | #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ | |
200 | #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ | |
1da177e4 | 201 | #define ICH6_REG_RIRBSTS 0x5d |
b21fadb9 TI |
202 | #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ |
203 | #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ | |
1da177e4 LT |
204 | #define ICH6_REG_RIRBSIZE 0x5e |
205 | ||
206 | #define ICH6_REG_IC 0x60 | |
207 | #define ICH6_REG_IR 0x64 | |
208 | #define ICH6_REG_IRS 0x68 | |
209 | #define ICH6_IRS_VALID (1<<1) | |
210 | #define ICH6_IRS_BUSY (1<<0) | |
211 | ||
212 | #define ICH6_REG_DPLBASE 0x70 | |
213 | #define ICH6_REG_DPUBASE 0x74 | |
214 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
215 | ||
216 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
217 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
218 | ||
219 | /* stream register offsets from stream base */ | |
220 | #define ICH6_REG_SD_CTL 0x00 | |
221 | #define ICH6_REG_SD_STS 0x03 | |
222 | #define ICH6_REG_SD_LPIB 0x04 | |
223 | #define ICH6_REG_SD_CBL 0x08 | |
224 | #define ICH6_REG_SD_LVI 0x0c | |
225 | #define ICH6_REG_SD_FIFOW 0x0e | |
226 | #define ICH6_REG_SD_FIFOSIZE 0x10 | |
227 | #define ICH6_REG_SD_FORMAT 0x12 | |
228 | #define ICH6_REG_SD_BDLPL 0x18 | |
229 | #define ICH6_REG_SD_BDLPU 0x1c | |
230 | ||
231 | /* PCI space */ | |
232 | #define ICH6_PCIREG_TCSEL 0x44 | |
233 | ||
234 | /* | |
235 | * other constants | |
236 | */ | |
237 | ||
238 | /* max number of SDs */ | |
07e4ca50 | 239 | /* ICH, ATI and VIA have 4 playback and 4 capture */ |
07e4ca50 | 240 | #define ICH6_NUM_CAPTURE 4 |
07e4ca50 TI |
241 | #define ICH6_NUM_PLAYBACK 4 |
242 | ||
243 | /* ULI has 6 playback and 5 capture */ | |
07e4ca50 | 244 | #define ULI_NUM_CAPTURE 5 |
07e4ca50 TI |
245 | #define ULI_NUM_PLAYBACK 6 |
246 | ||
778b6e1b | 247 | /* ATI HDMI has 1 playback and 0 capture */ |
778b6e1b | 248 | #define ATIHDMI_NUM_CAPTURE 0 |
778b6e1b FK |
249 | #define ATIHDMI_NUM_PLAYBACK 1 |
250 | ||
f269002e KY |
251 | /* TERA has 4 playback and 3 capture */ |
252 | #define TERA_NUM_CAPTURE 3 | |
253 | #define TERA_NUM_PLAYBACK 4 | |
254 | ||
07e4ca50 TI |
255 | /* this number is statically defined for simplicity */ |
256 | #define MAX_AZX_DEV 16 | |
257 | ||
1da177e4 | 258 | /* max number of fragments - we may use more if allocating more pages for BDL */ |
4ce107b9 TI |
259 | #define BDL_SIZE 4096 |
260 | #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) | |
261 | #define AZX_MAX_FRAG 32 | |
1da177e4 LT |
262 | /* max buffer size - no h/w limit, you can increase as you like */ |
263 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
1da177e4 LT |
264 | |
265 | /* RIRB int mask: overrun[2], response[0] */ | |
266 | #define RIRB_INT_RESPONSE 0x01 | |
267 | #define RIRB_INT_OVERRUN 0x04 | |
268 | #define RIRB_INT_MASK 0x05 | |
269 | ||
2f5983f2 | 270 | /* STATESTS int mask: S3,SD2,SD1,SD0 */ |
7445dfc1 WN |
271 | #define AZX_MAX_CODECS 8 |
272 | #define AZX_DEFAULT_CODECS 4 | |
deadff16 | 273 | #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) |
1da177e4 LT |
274 | |
275 | /* SD_CTL bits */ | |
276 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
277 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
850f0e52 TI |
278 | #define SD_CTL_STRIPE (3 << 16) /* stripe control */ |
279 | #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ | |
280 | #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ | |
1da177e4 LT |
281 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) |
282 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
283 | ||
284 | /* SD_CTL and SD_STS */ | |
285 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
286 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
287 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
d01ce99f TI |
288 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ |
289 | SD_INT_COMPLETE) | |
1da177e4 LT |
290 | |
291 | /* SD_STS */ | |
292 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
293 | ||
294 | /* INTCTL and INTSTS */ | |
d01ce99f TI |
295 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ |
296 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
297 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
1da177e4 | 298 | |
1da177e4 LT |
299 | /* below are so far hardcoded - should read registers in future */ |
300 | #define ICH6_MAX_CORB_ENTRIES 256 | |
301 | #define ICH6_MAX_RIRB_ENTRIES 256 | |
302 | ||
c74db86b TI |
303 | /* position fix mode */ |
304 | enum { | |
0be3b5d3 | 305 | POS_FIX_AUTO, |
d2e1c973 | 306 | POS_FIX_LPIB, |
0be3b5d3 | 307 | POS_FIX_POSBUF, |
c74db86b | 308 | }; |
1da177e4 | 309 | |
f5d40b30 | 310 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
f5d40b30 FL |
311 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
312 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | |
313 | ||
da3fca21 V |
314 | /* Defines for Nvidia HDA support */ |
315 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e | |
316 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f | |
320dcc30 PC |
317 | #define NVIDIA_HDA_ISTRM_COH 0x4d |
318 | #define NVIDIA_HDA_OSTRM_COH 0x4c | |
319 | #define NVIDIA_HDA_ENABLE_COHBIT 0x01 | |
f5d40b30 | 320 | |
90a5ad52 TI |
321 | /* Defines for Intel SCH HDA snoop control */ |
322 | #define INTEL_SCH_HDA_DEVC 0x78 | |
323 | #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) | |
324 | ||
0e153474 JC |
325 | /* Define IN stream 0 FIFO size offset in VIA controller */ |
326 | #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 | |
327 | /* Define VIA HD Audio Device ID*/ | |
328 | #define VIA_HDAC_DEVICE_ID 0x3288 | |
329 | ||
c4da29ca YL |
330 | /* HD Audio class code */ |
331 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 | |
90a5ad52 | 332 | |
1da177e4 LT |
333 | /* |
334 | */ | |
335 | ||
a98f90fd | 336 | struct azx_dev { |
4ce107b9 | 337 | struct snd_dma_buffer bdl; /* BDL buffer */ |
d01ce99f | 338 | u32 *posbuf; /* position buffer pointer */ |
1da177e4 | 339 | |
d01ce99f | 340 | unsigned int bufsize; /* size of the play buffer in bytes */ |
9ad593f6 | 341 | unsigned int period_bytes; /* size of the period in bytes */ |
d01ce99f TI |
342 | unsigned int frags; /* number for period in the play buffer */ |
343 | unsigned int fifo_size; /* FIFO size */ | |
e5463720 JK |
344 | unsigned long start_wallclk; /* start + minimum wallclk */ |
345 | unsigned long period_wallclk; /* wallclk for period */ | |
1da177e4 | 346 | |
d01ce99f | 347 | void __iomem *sd_addr; /* stream descriptor pointer */ |
1da177e4 | 348 | |
d01ce99f | 349 | u32 sd_int_sta_mask; /* stream int status mask */ |
1da177e4 LT |
350 | |
351 | /* pcm support */ | |
d01ce99f TI |
352 | struct snd_pcm_substream *substream; /* assigned substream, |
353 | * set in PCM open | |
354 | */ | |
355 | unsigned int format_val; /* format value to be set in the | |
356 | * controller and the codec | |
357 | */ | |
1da177e4 LT |
358 | unsigned char stream_tag; /* assigned stream */ |
359 | unsigned char index; /* stream index */ | |
ef18bede | 360 | int device; /* last device number assigned to */ |
1da177e4 | 361 | |
927fc866 PM |
362 | unsigned int opened :1; |
363 | unsigned int running :1; | |
675f25d4 | 364 | unsigned int irq_pending :1; |
0e153474 JC |
365 | /* |
366 | * For VIA: | |
367 | * A flag to ensure DMA position is 0 | |
368 | * when link position is not greater than FIFO size | |
369 | */ | |
370 | unsigned int insufficient :1; | |
1da177e4 LT |
371 | }; |
372 | ||
373 | /* CORB/RIRB */ | |
a98f90fd | 374 | struct azx_rb { |
1da177e4 LT |
375 | u32 *buf; /* CORB/RIRB buffer |
376 | * Each CORB entry is 4byte, RIRB is 8byte | |
377 | */ | |
378 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
379 | /* for RIRB */ | |
380 | unsigned short rp, wp; /* read/write pointers */ | |
deadff16 WF |
381 | int cmds[AZX_MAX_CODECS]; /* number of pending requests */ |
382 | u32 res[AZX_MAX_CODECS]; /* last read value */ | |
1da177e4 LT |
383 | }; |
384 | ||
a98f90fd TI |
385 | struct azx { |
386 | struct snd_card *card; | |
1da177e4 | 387 | struct pci_dev *pci; |
555e219f | 388 | int dev_index; |
1da177e4 | 389 | |
07e4ca50 TI |
390 | /* chip type specific */ |
391 | int driver_type; | |
392 | int playback_streams; | |
393 | int playback_index_offset; | |
394 | int capture_streams; | |
395 | int capture_index_offset; | |
396 | int num_streams; | |
397 | ||
1da177e4 LT |
398 | /* pci resources */ |
399 | unsigned long addr; | |
400 | void __iomem *remap_addr; | |
401 | int irq; | |
402 | ||
403 | /* locks */ | |
404 | spinlock_t reg_lock; | |
62932df8 | 405 | struct mutex open_mutex; |
1da177e4 | 406 | |
07e4ca50 | 407 | /* streams (x num_streams) */ |
a98f90fd | 408 | struct azx_dev *azx_dev; |
1da177e4 LT |
409 | |
410 | /* PCM */ | |
c8936222 | 411 | struct snd_pcm *pcm[HDA_MAX_PCMS]; |
1da177e4 LT |
412 | |
413 | /* HD codec */ | |
414 | unsigned short codec_mask; | |
f1eaaeec | 415 | int codec_probe_mask; /* copied from probe_mask option */ |
1da177e4 | 416 | struct hda_bus *bus; |
2dca0bba | 417 | unsigned int beep_mode; |
1da177e4 LT |
418 | |
419 | /* CORB/RIRB */ | |
a98f90fd TI |
420 | struct azx_rb corb; |
421 | struct azx_rb rirb; | |
1da177e4 | 422 | |
4ce107b9 | 423 | /* CORB/RIRB and position buffers */ |
1da177e4 LT |
424 | struct snd_dma_buffer rb; |
425 | struct snd_dma_buffer posbuf; | |
c74db86b TI |
426 | |
427 | /* flags */ | |
beaffc39 | 428 | int position_fix[2]; /* for both playback/capture streams */ |
1eb6dc7d | 429 | int poll_count; |
cb53c626 | 430 | unsigned int running :1; |
927fc866 PM |
431 | unsigned int initialized :1; |
432 | unsigned int single_cmd :1; | |
433 | unsigned int polling_mode :1; | |
68e7fffc | 434 | unsigned int msi :1; |
a6a950a8 | 435 | unsigned int irq_pending_warned :1; |
0e153474 | 436 | unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */ |
6ce4a3bc | 437 | unsigned int probing :1; /* codec probing phase */ |
43bbb6cc TI |
438 | |
439 | /* for debugging */ | |
feb27340 | 440 | unsigned int last_cmd[AZX_MAX_CODECS]; |
9ad593f6 TI |
441 | |
442 | /* for pending irqs */ | |
443 | struct work_struct irq_pending_work; | |
0cbf0098 TI |
444 | |
445 | /* reboot notifier (for mysterious hangup problem at power-down) */ | |
446 | struct notifier_block reboot_notifier; | |
1da177e4 LT |
447 | }; |
448 | ||
07e4ca50 TI |
449 | /* driver types */ |
450 | enum { | |
451 | AZX_DRIVER_ICH, | |
32679f95 | 452 | AZX_DRIVER_PCH, |
4979bca9 | 453 | AZX_DRIVER_SCH, |
07e4ca50 | 454 | AZX_DRIVER_ATI, |
778b6e1b | 455 | AZX_DRIVER_ATIHDMI, |
07e4ca50 TI |
456 | AZX_DRIVER_VIA, |
457 | AZX_DRIVER_SIS, | |
458 | AZX_DRIVER_ULI, | |
da3fca21 | 459 | AZX_DRIVER_NVIDIA, |
f269002e | 460 | AZX_DRIVER_TERA, |
c4da29ca | 461 | AZX_DRIVER_GENERIC, |
2f5983f2 | 462 | AZX_NUM_DRIVERS, /* keep this as last entry */ |
07e4ca50 TI |
463 | }; |
464 | ||
465 | static char *driver_short_names[] __devinitdata = { | |
466 | [AZX_DRIVER_ICH] = "HDA Intel", | |
32679f95 | 467 | [AZX_DRIVER_PCH] = "HDA Intel PCH", |
4979bca9 | 468 | [AZX_DRIVER_SCH] = "HDA Intel MID", |
07e4ca50 | 469 | [AZX_DRIVER_ATI] = "HDA ATI SB", |
778b6e1b | 470 | [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", |
07e4ca50 TI |
471 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", |
472 | [AZX_DRIVER_SIS] = "HDA SIS966", | |
da3fca21 V |
473 | [AZX_DRIVER_ULI] = "HDA ULI M5461", |
474 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", | |
f269002e | 475 | [AZX_DRIVER_TERA] = "HDA Teradici", |
c4da29ca | 476 | [AZX_DRIVER_GENERIC] = "HD-Audio Generic", |
07e4ca50 TI |
477 | }; |
478 | ||
1da177e4 LT |
479 | /* |
480 | * macros for easy use | |
481 | */ | |
482 | #define azx_writel(chip,reg,value) \ | |
483 | writel(value, (chip)->remap_addr + ICH6_REG_##reg) | |
484 | #define azx_readl(chip,reg) \ | |
485 | readl((chip)->remap_addr + ICH6_REG_##reg) | |
486 | #define azx_writew(chip,reg,value) \ | |
487 | writew(value, (chip)->remap_addr + ICH6_REG_##reg) | |
488 | #define azx_readw(chip,reg) \ | |
489 | readw((chip)->remap_addr + ICH6_REG_##reg) | |
490 | #define azx_writeb(chip,reg,value) \ | |
491 | writeb(value, (chip)->remap_addr + ICH6_REG_##reg) | |
492 | #define azx_readb(chip,reg) \ | |
493 | readb((chip)->remap_addr + ICH6_REG_##reg) | |
494 | ||
495 | #define azx_sd_writel(dev,reg,value) \ | |
496 | writel(value, (dev)->sd_addr + ICH6_REG_##reg) | |
497 | #define azx_sd_readl(dev,reg) \ | |
498 | readl((dev)->sd_addr + ICH6_REG_##reg) | |
499 | #define azx_sd_writew(dev,reg,value) \ | |
500 | writew(value, (dev)->sd_addr + ICH6_REG_##reg) | |
501 | #define azx_sd_readw(dev,reg) \ | |
502 | readw((dev)->sd_addr + ICH6_REG_##reg) | |
503 | #define azx_sd_writeb(dev,reg,value) \ | |
504 | writeb(value, (dev)->sd_addr + ICH6_REG_##reg) | |
505 | #define azx_sd_readb(dev,reg) \ | |
506 | readb((dev)->sd_addr + ICH6_REG_##reg) | |
507 | ||
508 | /* for pcm support */ | |
a98f90fd | 509 | #define get_azx_dev(substream) (substream->runtime->private_data) |
1da177e4 | 510 | |
68e7fffc | 511 | static int azx_acquire_irq(struct azx *chip, int do_disconnect); |
1eb6dc7d | 512 | static int azx_send_cmd(struct hda_bus *bus, unsigned int val); |
1da177e4 LT |
513 | /* |
514 | * Interface for HD codec | |
515 | */ | |
516 | ||
1da177e4 LT |
517 | /* |
518 | * CORB / RIRB interface | |
519 | */ | |
a98f90fd | 520 | static int azx_alloc_cmd_io(struct azx *chip) |
1da177e4 LT |
521 | { |
522 | int err; | |
523 | ||
524 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
d01ce99f TI |
525 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, |
526 | snd_dma_pci_data(chip->pci), | |
1da177e4 LT |
527 | PAGE_SIZE, &chip->rb); |
528 | if (err < 0) { | |
529 | snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); | |
530 | return err; | |
531 | } | |
532 | return 0; | |
533 | } | |
534 | ||
a98f90fd | 535 | static void azx_init_cmd_io(struct azx *chip) |
1da177e4 | 536 | { |
cdb1fbf2 | 537 | spin_lock_irq(&chip->reg_lock); |
1da177e4 LT |
538 | /* CORB set up */ |
539 | chip->corb.addr = chip->rb.addr; | |
540 | chip->corb.buf = (u32 *)chip->rb.area; | |
541 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | |
766979e0 | 542 | azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); |
1da177e4 | 543 | |
07e4ca50 TI |
544 | /* set the corb size to 256 entries (ULI requires explicitly) */ |
545 | azx_writeb(chip, CORBSIZE, 0x02); | |
1da177e4 LT |
546 | /* set the corb write pointer to 0 */ |
547 | azx_writew(chip, CORBWP, 0); | |
548 | /* reset the corb hw read pointer */ | |
b21fadb9 | 549 | azx_writew(chip, CORBRP, ICH6_CORBRP_RST); |
1da177e4 | 550 | /* enable corb dma */ |
b21fadb9 | 551 | azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); |
1da177e4 LT |
552 | |
553 | /* RIRB set up */ | |
554 | chip->rirb.addr = chip->rb.addr + 2048; | |
555 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | |
deadff16 WF |
556 | chip->rirb.wp = chip->rirb.rp = 0; |
557 | memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); | |
1da177e4 | 558 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); |
766979e0 | 559 | azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); |
1da177e4 | 560 | |
07e4ca50 TI |
561 | /* set the rirb size to 256 entries (ULI requires explicitly) */ |
562 | azx_writeb(chip, RIRBSIZE, 0x02); | |
1da177e4 | 563 | /* reset the rirb hw write pointer */ |
b21fadb9 | 564 | azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); |
1da177e4 LT |
565 | /* set N=1, get RIRB response interrupt for new entry */ |
566 | azx_writew(chip, RINTCNT, 1); | |
567 | /* enable rirb dma and response irq */ | |
1da177e4 | 568 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); |
cdb1fbf2 | 569 | spin_unlock_irq(&chip->reg_lock); |
1da177e4 LT |
570 | } |
571 | ||
a98f90fd | 572 | static void azx_free_cmd_io(struct azx *chip) |
1da177e4 | 573 | { |
cdb1fbf2 | 574 | spin_lock_irq(&chip->reg_lock); |
1da177e4 LT |
575 | /* disable ringbuffer DMAs */ |
576 | azx_writeb(chip, RIRBCTL, 0); | |
577 | azx_writeb(chip, CORBCTL, 0); | |
cdb1fbf2 | 578 | spin_unlock_irq(&chip->reg_lock); |
1da177e4 LT |
579 | } |
580 | ||
deadff16 WF |
581 | static unsigned int azx_command_addr(u32 cmd) |
582 | { | |
583 | unsigned int addr = cmd >> 28; | |
584 | ||
585 | if (addr >= AZX_MAX_CODECS) { | |
586 | snd_BUG(); | |
587 | addr = 0; | |
588 | } | |
589 | ||
590 | return addr; | |
591 | } | |
592 | ||
593 | static unsigned int azx_response_addr(u32 res) | |
594 | { | |
595 | unsigned int addr = res & 0xf; | |
596 | ||
597 | if (addr >= AZX_MAX_CODECS) { | |
598 | snd_BUG(); | |
599 | addr = 0; | |
600 | } | |
601 | ||
602 | return addr; | |
1da177e4 LT |
603 | } |
604 | ||
605 | /* send a command */ | |
33fa35ed | 606 | static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) |
1da177e4 | 607 | { |
33fa35ed | 608 | struct azx *chip = bus->private_data; |
deadff16 | 609 | unsigned int addr = azx_command_addr(val); |
1da177e4 | 610 | unsigned int wp; |
1da177e4 | 611 | |
c32649fe WF |
612 | spin_lock_irq(&chip->reg_lock); |
613 | ||
1da177e4 LT |
614 | /* add command to corb */ |
615 | wp = azx_readb(chip, CORBWP); | |
616 | wp++; | |
617 | wp %= ICH6_MAX_CORB_ENTRIES; | |
618 | ||
deadff16 | 619 | chip->rirb.cmds[addr]++; |
1da177e4 LT |
620 | chip->corb.buf[wp] = cpu_to_le32(val); |
621 | azx_writel(chip, CORBWP, wp); | |
c32649fe | 622 | |
1da177e4 LT |
623 | spin_unlock_irq(&chip->reg_lock); |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
628 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | |
629 | ||
630 | /* retrieve RIRB entry - called from interrupt handler */ | |
a98f90fd | 631 | static void azx_update_rirb(struct azx *chip) |
1da177e4 LT |
632 | { |
633 | unsigned int rp, wp; | |
deadff16 | 634 | unsigned int addr; |
1da177e4 LT |
635 | u32 res, res_ex; |
636 | ||
637 | wp = azx_readb(chip, RIRBWP); | |
638 | if (wp == chip->rirb.wp) | |
639 | return; | |
640 | chip->rirb.wp = wp; | |
deadff16 | 641 | |
1da177e4 LT |
642 | while (chip->rirb.rp != wp) { |
643 | chip->rirb.rp++; | |
644 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | |
645 | ||
646 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
647 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | |
648 | res = le32_to_cpu(chip->rirb.buf[rp]); | |
deadff16 | 649 | addr = azx_response_addr(res_ex); |
1da177e4 LT |
650 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) |
651 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | |
deadff16 WF |
652 | else if (chip->rirb.cmds[addr]) { |
653 | chip->rirb.res[addr] = res; | |
2add9b92 | 654 | smp_wmb(); |
deadff16 | 655 | chip->rirb.cmds[addr]--; |
e310bb06 WF |
656 | } else |
657 | snd_printk(KERN_ERR SFX "spurious response %#x:%#x, " | |
658 | "last cmd=%#08x\n", | |
659 | res, res_ex, | |
660 | chip->last_cmd[addr]); | |
1da177e4 LT |
661 | } |
662 | } | |
663 | ||
664 | /* receive a response */ | |
deadff16 WF |
665 | static unsigned int azx_rirb_get_response(struct hda_bus *bus, |
666 | unsigned int addr) | |
1da177e4 | 667 | { |
33fa35ed | 668 | struct azx *chip = bus->private_data; |
5c79b1f8 | 669 | unsigned long timeout; |
1eb6dc7d | 670 | int do_poll = 0; |
1da177e4 | 671 | |
5c79b1f8 TI |
672 | again: |
673 | timeout = jiffies + msecs_to_jiffies(1000); | |
28a0d9df | 674 | for (;;) { |
1eb6dc7d | 675 | if (chip->polling_mode || do_poll) { |
e96224ae TI |
676 | spin_lock_irq(&chip->reg_lock); |
677 | azx_update_rirb(chip); | |
678 | spin_unlock_irq(&chip->reg_lock); | |
679 | } | |
deadff16 | 680 | if (!chip->rirb.cmds[addr]) { |
2add9b92 | 681 | smp_rmb(); |
b613291f | 682 | bus->rirb_error = 0; |
1eb6dc7d ML |
683 | |
684 | if (!do_poll) | |
685 | chip->poll_count = 0; | |
deadff16 | 686 | return chip->rirb.res[addr]; /* the last value */ |
2add9b92 | 687 | } |
28a0d9df TI |
688 | if (time_after(jiffies, timeout)) |
689 | break; | |
33fa35ed | 690 | if (bus->needs_damn_long_delay) |
52987656 TI |
691 | msleep(2); /* temporary workaround */ |
692 | else { | |
693 | udelay(10); | |
694 | cond_resched(); | |
695 | } | |
28a0d9df | 696 | } |
5c79b1f8 | 697 | |
1eb6dc7d ML |
698 | if (!chip->polling_mode && chip->poll_count < 2) { |
699 | snd_printdd(SFX "azx_get_response timeout, " | |
700 | "polling the codec once: last cmd=0x%08x\n", | |
701 | chip->last_cmd[addr]); | |
702 | do_poll = 1; | |
703 | chip->poll_count++; | |
704 | goto again; | |
705 | } | |
706 | ||
707 | ||
23c4a881 TI |
708 | if (!chip->polling_mode) { |
709 | snd_printk(KERN_WARNING SFX "azx_get_response timeout, " | |
710 | "switching to polling mode: last cmd=0x%08x\n", | |
711 | chip->last_cmd[addr]); | |
712 | chip->polling_mode = 1; | |
713 | goto again; | |
714 | } | |
715 | ||
68e7fffc | 716 | if (chip->msi) { |
4abc1cc2 | 717 | snd_printk(KERN_WARNING SFX "No response from codec, " |
feb27340 WF |
718 | "disabling MSI: last cmd=0x%08x\n", |
719 | chip->last_cmd[addr]); | |
68e7fffc TI |
720 | free_irq(chip->irq, chip); |
721 | chip->irq = -1; | |
722 | pci_disable_msi(chip->pci); | |
723 | chip->msi = 0; | |
b613291f TI |
724 | if (azx_acquire_irq(chip, 1) < 0) { |
725 | bus->rirb_error = 1; | |
68e7fffc | 726 | return -1; |
b613291f | 727 | } |
68e7fffc TI |
728 | goto again; |
729 | } | |
730 | ||
6ce4a3bc TI |
731 | if (chip->probing) { |
732 | /* If this critical timeout happens during the codec probing | |
733 | * phase, this is likely an access to a non-existing codec | |
734 | * slot. Better to return an error and reset the system. | |
735 | */ | |
736 | return -1; | |
737 | } | |
738 | ||
8dd78330 TI |
739 | /* a fatal communication error; need either to reset or to fallback |
740 | * to the single_cmd mode | |
741 | */ | |
b613291f | 742 | bus->rirb_error = 1; |
b20f3b83 | 743 | if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { |
8dd78330 TI |
744 | bus->response_reset = 1; |
745 | return -1; /* give a chance to retry */ | |
746 | } | |
747 | ||
748 | snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " | |
749 | "switching to single_cmd mode: last cmd=0x%08x\n", | |
feb27340 | 750 | chip->last_cmd[addr]); |
8dd78330 TI |
751 | chip->single_cmd = 1; |
752 | bus->response_reset = 0; | |
1a696978 | 753 | /* release CORB/RIRB */ |
4fcd3920 | 754 | azx_free_cmd_io(chip); |
1a696978 TI |
755 | /* disable unsolicited responses */ |
756 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); | |
5c79b1f8 | 757 | return -1; |
1da177e4 LT |
758 | } |
759 | ||
1da177e4 LT |
760 | /* |
761 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
762 | * | |
763 | * Note: according to Intel, this is not preferred use. The command was | |
764 | * intended for the BIOS only, and may get confused with unsolicited | |
765 | * responses. So, we shouldn't use it for normal operation from the | |
766 | * driver. | |
767 | * I left the codes, however, for debugging/testing purposes. | |
768 | */ | |
769 | ||
b05a7d4f | 770 | /* receive a response */ |
deadff16 | 771 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) |
b05a7d4f TI |
772 | { |
773 | int timeout = 50; | |
774 | ||
775 | while (timeout--) { | |
776 | /* check IRV busy bit */ | |
777 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { | |
778 | /* reuse rirb.res as the response return value */ | |
deadff16 | 779 | chip->rirb.res[addr] = azx_readl(chip, IR); |
b05a7d4f TI |
780 | return 0; |
781 | } | |
782 | udelay(1); | |
783 | } | |
784 | if (printk_ratelimit()) | |
785 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", | |
786 | azx_readw(chip, IRS)); | |
deadff16 | 787 | chip->rirb.res[addr] = -1; |
b05a7d4f TI |
788 | return -EIO; |
789 | } | |
790 | ||
1da177e4 | 791 | /* send a command */ |
33fa35ed | 792 | static int azx_single_send_cmd(struct hda_bus *bus, u32 val) |
1da177e4 | 793 | { |
33fa35ed | 794 | struct azx *chip = bus->private_data; |
deadff16 | 795 | unsigned int addr = azx_command_addr(val); |
1da177e4 LT |
796 | int timeout = 50; |
797 | ||
8dd78330 | 798 | bus->rirb_error = 0; |
1da177e4 LT |
799 | while (timeout--) { |
800 | /* check ICB busy bit */ | |
d01ce99f | 801 | if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { |
1da177e4 | 802 | /* Clear IRV valid bit */ |
d01ce99f TI |
803 | azx_writew(chip, IRS, azx_readw(chip, IRS) | |
804 | ICH6_IRS_VALID); | |
1da177e4 | 805 | azx_writel(chip, IC, val); |
d01ce99f TI |
806 | azx_writew(chip, IRS, azx_readw(chip, IRS) | |
807 | ICH6_IRS_BUSY); | |
deadff16 | 808 | return azx_single_wait_for_response(chip, addr); |
1da177e4 LT |
809 | } |
810 | udelay(1); | |
811 | } | |
1cfd52bc MB |
812 | if (printk_ratelimit()) |
813 | snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", | |
814 | azx_readw(chip, IRS), val); | |
1da177e4 LT |
815 | return -EIO; |
816 | } | |
817 | ||
818 | /* receive a response */ | |
deadff16 WF |
819 | static unsigned int azx_single_get_response(struct hda_bus *bus, |
820 | unsigned int addr) | |
1da177e4 | 821 | { |
33fa35ed | 822 | struct azx *chip = bus->private_data; |
deadff16 | 823 | return chip->rirb.res[addr]; |
1da177e4 LT |
824 | } |
825 | ||
111d3af5 TI |
826 | /* |
827 | * The below are the main callbacks from hda_codec. | |
828 | * | |
829 | * They are just the skeleton to call sub-callbacks according to the | |
830 | * current setting of chip->single_cmd. | |
831 | */ | |
832 | ||
833 | /* send a command */ | |
33fa35ed | 834 | static int azx_send_cmd(struct hda_bus *bus, unsigned int val) |
111d3af5 | 835 | { |
33fa35ed | 836 | struct azx *chip = bus->private_data; |
43bbb6cc | 837 | |
feb27340 | 838 | chip->last_cmd[azx_command_addr(val)] = val; |
111d3af5 | 839 | if (chip->single_cmd) |
33fa35ed | 840 | return azx_single_send_cmd(bus, val); |
111d3af5 | 841 | else |
33fa35ed | 842 | return azx_corb_send_cmd(bus, val); |
111d3af5 TI |
843 | } |
844 | ||
845 | /* get a response */ | |
deadff16 WF |
846 | static unsigned int azx_get_response(struct hda_bus *bus, |
847 | unsigned int addr) | |
111d3af5 | 848 | { |
33fa35ed | 849 | struct azx *chip = bus->private_data; |
111d3af5 | 850 | if (chip->single_cmd) |
deadff16 | 851 | return azx_single_get_response(bus, addr); |
111d3af5 | 852 | else |
deadff16 | 853 | return azx_rirb_get_response(bus, addr); |
111d3af5 TI |
854 | } |
855 | ||
cb53c626 | 856 | #ifdef CONFIG_SND_HDA_POWER_SAVE |
33fa35ed | 857 | static void azx_power_notify(struct hda_bus *bus); |
cb53c626 | 858 | #endif |
111d3af5 | 859 | |
1da177e4 | 860 | /* reset codec link */ |
cd508fe5 | 861 | static int azx_reset(struct azx *chip, int full_reset) |
1da177e4 LT |
862 | { |
863 | int count; | |
864 | ||
cd508fe5 JK |
865 | if (!full_reset) |
866 | goto __skip; | |
867 | ||
e8a7f136 DT |
868 | /* clear STATESTS */ |
869 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); | |
870 | ||
1da177e4 LT |
871 | /* reset controller */ |
872 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | |
873 | ||
874 | count = 50; | |
875 | while (azx_readb(chip, GCTL) && --count) | |
876 | msleep(1); | |
877 | ||
878 | /* delay for >= 100us for codec PLL to settle per spec | |
879 | * Rev 0.9 section 5.5.1 | |
880 | */ | |
881 | msleep(1); | |
882 | ||
883 | /* Bring controller out of reset */ | |
884 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | |
885 | ||
886 | count = 50; | |
927fc866 | 887 | while (!azx_readb(chip, GCTL) && --count) |
1da177e4 LT |
888 | msleep(1); |
889 | ||
927fc866 | 890 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ |
1da177e4 LT |
891 | msleep(1); |
892 | ||
cd508fe5 | 893 | __skip: |
1da177e4 | 894 | /* check to see if controller is ready */ |
927fc866 | 895 | if (!azx_readb(chip, GCTL)) { |
4abc1cc2 | 896 | snd_printd(SFX "azx_reset: controller not ready!\n"); |
1da177e4 LT |
897 | return -EBUSY; |
898 | } | |
899 | ||
41e2fce4 | 900 | /* Accept unsolicited responses */ |
1a696978 TI |
901 | if (!chip->single_cmd) |
902 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | | |
903 | ICH6_GCTL_UNSOL); | |
41e2fce4 | 904 | |
1da177e4 | 905 | /* detect codecs */ |
927fc866 | 906 | if (!chip->codec_mask) { |
1da177e4 | 907 | chip->codec_mask = azx_readw(chip, STATESTS); |
4abc1cc2 | 908 | snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask); |
1da177e4 LT |
909 | } |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
914 | ||
915 | /* | |
916 | * Lowlevel interface | |
917 | */ | |
918 | ||
919 | /* enable interrupts */ | |
a98f90fd | 920 | static void azx_int_enable(struct azx *chip) |
1da177e4 LT |
921 | { |
922 | /* enable controller CIE and GIE */ | |
923 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | |
924 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | |
925 | } | |
926 | ||
927 | /* disable interrupts */ | |
a98f90fd | 928 | static void azx_int_disable(struct azx *chip) |
1da177e4 LT |
929 | { |
930 | int i; | |
931 | ||
932 | /* disable interrupts in stream descriptor */ | |
07e4ca50 | 933 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 934 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
935 | azx_sd_writeb(azx_dev, SD_CTL, |
936 | azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); | |
937 | } | |
938 | ||
939 | /* disable SIE for all streams */ | |
940 | azx_writeb(chip, INTCTL, 0); | |
941 | ||
942 | /* disable controller CIE and GIE */ | |
943 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | |
944 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | |
945 | } | |
946 | ||
947 | /* clear interrupts */ | |
a98f90fd | 948 | static void azx_int_clear(struct azx *chip) |
1da177e4 LT |
949 | { |
950 | int i; | |
951 | ||
952 | /* clear stream status */ | |
07e4ca50 | 953 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 954 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
955 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
956 | } | |
957 | ||
958 | /* clear STATESTS */ | |
959 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); | |
960 | ||
961 | /* clear rirb status */ | |
962 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
963 | ||
964 | /* clear int status */ | |
965 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | |
966 | } | |
967 | ||
968 | /* start a stream */ | |
a98f90fd | 969 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 | 970 | { |
0e153474 JC |
971 | /* |
972 | * Before stream start, initialize parameter | |
973 | */ | |
974 | azx_dev->insufficient = 1; | |
975 | ||
1da177e4 | 976 | /* enable SIE */ |
ccc5df05 WN |
977 | azx_writel(chip, INTCTL, |
978 | azx_readl(chip, INTCTL) | (1 << azx_dev->index)); | |
1da177e4 LT |
979 | /* set DMA start and interrupt mask */ |
980 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | | |
981 | SD_CTL_DMA_START | SD_INT_MASK); | |
982 | } | |
983 | ||
1dddab40 TI |
984 | /* stop DMA */ |
985 | static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) | |
1da177e4 | 986 | { |
1da177e4 LT |
987 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & |
988 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
989 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
1dddab40 TI |
990 | } |
991 | ||
992 | /* stop a stream */ | |
993 | static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) | |
994 | { | |
995 | azx_stream_clear(chip, azx_dev); | |
1da177e4 | 996 | /* disable SIE */ |
ccc5df05 WN |
997 | azx_writel(chip, INTCTL, |
998 | azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); | |
1da177e4 LT |
999 | } |
1000 | ||
1001 | ||
1002 | /* | |
cb53c626 | 1003 | * reset and start the controller registers |
1da177e4 | 1004 | */ |
cd508fe5 | 1005 | static void azx_init_chip(struct azx *chip, int full_reset) |
1da177e4 | 1006 | { |
cb53c626 TI |
1007 | if (chip->initialized) |
1008 | return; | |
1da177e4 LT |
1009 | |
1010 | /* reset controller */ | |
cd508fe5 | 1011 | azx_reset(chip, full_reset); |
1da177e4 LT |
1012 | |
1013 | /* initialize interrupts */ | |
1014 | azx_int_clear(chip); | |
1015 | azx_int_enable(chip); | |
1016 | ||
1017 | /* initialize the codec command I/O */ | |
1a696978 TI |
1018 | if (!chip->single_cmd) |
1019 | azx_init_cmd_io(chip); | |
1da177e4 | 1020 | |
0be3b5d3 TI |
1021 | /* program the position buffer */ |
1022 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | |
766979e0 | 1023 | azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); |
f5d40b30 | 1024 | |
cb53c626 TI |
1025 | chip->initialized = 1; |
1026 | } | |
1027 | ||
1028 | /* | |
1029 | * initialize the PCI registers | |
1030 | */ | |
1031 | /* update bits in a PCI register byte */ | |
1032 | static void update_pci_byte(struct pci_dev *pci, unsigned int reg, | |
1033 | unsigned char mask, unsigned char val) | |
1034 | { | |
1035 | unsigned char data; | |
1036 | ||
1037 | pci_read_config_byte(pci, reg, &data); | |
1038 | data &= ~mask; | |
1039 | data |= (val & mask); | |
1040 | pci_write_config_byte(pci, reg, data); | |
1041 | } | |
1042 | ||
1043 | static void azx_init_pci(struct azx *chip) | |
1044 | { | |
90a5ad52 TI |
1045 | unsigned short snoop; |
1046 | ||
cb53c626 TI |
1047 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) |
1048 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
1049 | * Ensuring these bits are 0 clears playback static on some HD Audio | |
1050 | * codecs | |
1051 | */ | |
1052 | update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); | |
1053 | ||
da3fca21 V |
1054 | switch (chip->driver_type) { |
1055 | case AZX_DRIVER_ATI: | |
1056 | /* For ATI SB450 azalia HD audio, we need to enable snoop */ | |
cb53c626 TI |
1057 | update_pci_byte(chip->pci, |
1058 | ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, | |
1059 | 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP); | |
da3fca21 V |
1060 | break; |
1061 | case AZX_DRIVER_NVIDIA: | |
1062 | /* For NVIDIA HDA, enable snoop */ | |
cb53c626 TI |
1063 | update_pci_byte(chip->pci, |
1064 | NVIDIA_HDA_TRANSREG_ADDR, | |
1065 | 0x0f, NVIDIA_HDA_ENABLE_COHBITS); | |
320dcc30 PC |
1066 | update_pci_byte(chip->pci, |
1067 | NVIDIA_HDA_ISTRM_COH, | |
1068 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | |
1069 | update_pci_byte(chip->pci, | |
1070 | NVIDIA_HDA_OSTRM_COH, | |
1071 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | |
da3fca21 | 1072 | break; |
90a5ad52 | 1073 | case AZX_DRIVER_SCH: |
32679f95 | 1074 | case AZX_DRIVER_PCH: |
90a5ad52 TI |
1075 | pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); |
1076 | if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) { | |
4abc1cc2 | 1077 | pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, |
90a5ad52 TI |
1078 | snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP)); |
1079 | pci_read_config_word(chip->pci, | |
1080 | INTEL_SCH_HDA_DEVC, &snoop); | |
4abc1cc2 TI |
1081 | snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n", |
1082 | (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) | |
90a5ad52 TI |
1083 | ? "Failed" : "OK"); |
1084 | } | |
1085 | break; | |
1086 | ||
da3fca21 | 1087 | } |
1da177e4 LT |
1088 | } |
1089 | ||
1090 | ||
9ad593f6 TI |
1091 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); |
1092 | ||
1da177e4 LT |
1093 | /* |
1094 | * interrupt handler | |
1095 | */ | |
7d12e780 | 1096 | static irqreturn_t azx_interrupt(int irq, void *dev_id) |
1da177e4 | 1097 | { |
a98f90fd TI |
1098 | struct azx *chip = dev_id; |
1099 | struct azx_dev *azx_dev; | |
1da177e4 | 1100 | u32 status; |
9ef04066 | 1101 | u8 sd_status; |
fa00e046 | 1102 | int i, ok; |
1da177e4 LT |
1103 | |
1104 | spin_lock(&chip->reg_lock); | |
1105 | ||
1106 | status = azx_readl(chip, INTSTS); | |
1107 | if (status == 0) { | |
1108 | spin_unlock(&chip->reg_lock); | |
1109 | return IRQ_NONE; | |
1110 | } | |
1111 | ||
07e4ca50 | 1112 | for (i = 0; i < chip->num_streams; i++) { |
1da177e4 LT |
1113 | azx_dev = &chip->azx_dev[i]; |
1114 | if (status & azx_dev->sd_int_sta_mask) { | |
9ef04066 | 1115 | sd_status = azx_sd_readb(azx_dev, SD_STS); |
1da177e4 | 1116 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
9ef04066 CL |
1117 | if (!azx_dev->substream || !azx_dev->running || |
1118 | !(sd_status & SD_INT_COMPLETE)) | |
9ad593f6 TI |
1119 | continue; |
1120 | /* check whether this IRQ is really acceptable */ | |
fa00e046 JK |
1121 | ok = azx_position_ok(chip, azx_dev); |
1122 | if (ok == 1) { | |
9ad593f6 | 1123 | azx_dev->irq_pending = 0; |
1da177e4 LT |
1124 | spin_unlock(&chip->reg_lock); |
1125 | snd_pcm_period_elapsed(azx_dev->substream); | |
1126 | spin_lock(&chip->reg_lock); | |
fa00e046 | 1127 | } else if (ok == 0 && chip->bus && chip->bus->workq) { |
9ad593f6 TI |
1128 | /* bogus IRQ, process it later */ |
1129 | azx_dev->irq_pending = 1; | |
6acaed38 TI |
1130 | queue_work(chip->bus->workq, |
1131 | &chip->irq_pending_work); | |
1da177e4 LT |
1132 | } |
1133 | } | |
1134 | } | |
1135 | ||
1136 | /* clear rirb int */ | |
1137 | status = azx_readb(chip, RIRBSTS); | |
1138 | if (status & RIRB_INT_MASK) { | |
81740861 | 1139 | if (status & RIRB_INT_RESPONSE) |
1da177e4 LT |
1140 | azx_update_rirb(chip); |
1141 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
1142 | } | |
1143 | ||
1144 | #if 0 | |
1145 | /* clear state status int */ | |
1146 | if (azx_readb(chip, STATESTS) & 0x04) | |
1147 | azx_writeb(chip, STATESTS, 0x04); | |
1148 | #endif | |
1149 | spin_unlock(&chip->reg_lock); | |
1150 | ||
1151 | return IRQ_HANDLED; | |
1152 | } | |
1153 | ||
1154 | ||
675f25d4 TI |
1155 | /* |
1156 | * set up a BDL entry | |
1157 | */ | |
1158 | static int setup_bdle(struct snd_pcm_substream *substream, | |
1159 | struct azx_dev *azx_dev, u32 **bdlp, | |
1160 | int ofs, int size, int with_ioc) | |
1161 | { | |
675f25d4 TI |
1162 | u32 *bdl = *bdlp; |
1163 | ||
1164 | while (size > 0) { | |
1165 | dma_addr_t addr; | |
1166 | int chunk; | |
1167 | ||
1168 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | |
1169 | return -EINVAL; | |
1170 | ||
77a23f26 | 1171 | addr = snd_pcm_sgbuf_get_addr(substream, ofs); |
675f25d4 TI |
1172 | /* program the address field of the BDL entry */ |
1173 | bdl[0] = cpu_to_le32((u32)addr); | |
766979e0 | 1174 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); |
675f25d4 | 1175 | /* program the size field of the BDL entry */ |
fc4abee8 | 1176 | chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size); |
675f25d4 TI |
1177 | bdl[2] = cpu_to_le32(chunk); |
1178 | /* program the IOC to enable interrupt | |
1179 | * only when the whole fragment is processed | |
1180 | */ | |
1181 | size -= chunk; | |
1182 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | |
1183 | bdl += 4; | |
1184 | azx_dev->frags++; | |
1185 | ofs += chunk; | |
1186 | } | |
1187 | *bdlp = bdl; | |
1188 | return ofs; | |
1189 | } | |
1190 | ||
1da177e4 LT |
1191 | /* |
1192 | * set up BDL entries | |
1193 | */ | |
555e219f TI |
1194 | static int azx_setup_periods(struct azx *chip, |
1195 | struct snd_pcm_substream *substream, | |
4ce107b9 | 1196 | struct azx_dev *azx_dev) |
1da177e4 | 1197 | { |
4ce107b9 TI |
1198 | u32 *bdl; |
1199 | int i, ofs, periods, period_bytes; | |
555e219f | 1200 | int pos_adj; |
1da177e4 LT |
1201 | |
1202 | /* reset BDL address */ | |
1203 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
1204 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
1205 | ||
97b71c94 | 1206 | period_bytes = azx_dev->period_bytes; |
4ce107b9 TI |
1207 | periods = azx_dev->bufsize / period_bytes; |
1208 | ||
1da177e4 | 1209 | /* program the initial BDL entries */ |
4ce107b9 TI |
1210 | bdl = (u32 *)azx_dev->bdl.area; |
1211 | ofs = 0; | |
1212 | azx_dev->frags = 0; | |
555e219f TI |
1213 | pos_adj = bdl_pos_adj[chip->dev_index]; |
1214 | if (pos_adj > 0) { | |
675f25d4 | 1215 | struct snd_pcm_runtime *runtime = substream->runtime; |
e785d3d8 | 1216 | int pos_align = pos_adj; |
555e219f | 1217 | pos_adj = (pos_adj * runtime->rate + 47999) / 48000; |
675f25d4 | 1218 | if (!pos_adj) |
e785d3d8 TI |
1219 | pos_adj = pos_align; |
1220 | else | |
1221 | pos_adj = ((pos_adj + pos_align - 1) / pos_align) * | |
1222 | pos_align; | |
675f25d4 TI |
1223 | pos_adj = frames_to_bytes(runtime, pos_adj); |
1224 | if (pos_adj >= period_bytes) { | |
4abc1cc2 | 1225 | snd_printk(KERN_WARNING SFX "Too big adjustment %d\n", |
555e219f | 1226 | bdl_pos_adj[chip->dev_index]); |
675f25d4 TI |
1227 | pos_adj = 0; |
1228 | } else { | |
1229 | ofs = setup_bdle(substream, azx_dev, | |
1230 | &bdl, ofs, pos_adj, 1); | |
1231 | if (ofs < 0) | |
1232 | goto error; | |
4ce107b9 | 1233 | } |
555e219f TI |
1234 | } else |
1235 | pos_adj = 0; | |
675f25d4 TI |
1236 | for (i = 0; i < periods; i++) { |
1237 | if (i == periods - 1 && pos_adj) | |
1238 | ofs = setup_bdle(substream, azx_dev, &bdl, ofs, | |
1239 | period_bytes - pos_adj, 0); | |
1240 | else | |
1241 | ofs = setup_bdle(substream, azx_dev, &bdl, ofs, | |
1242 | period_bytes, 1); | |
1243 | if (ofs < 0) | |
1244 | goto error; | |
1da177e4 | 1245 | } |
4ce107b9 | 1246 | return 0; |
675f25d4 TI |
1247 | |
1248 | error: | |
4abc1cc2 | 1249 | snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n", |
675f25d4 | 1250 | azx_dev->bufsize, period_bytes); |
675f25d4 | 1251 | return -EINVAL; |
1da177e4 LT |
1252 | } |
1253 | ||
1dddab40 TI |
1254 | /* reset stream */ |
1255 | static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) | |
1da177e4 LT |
1256 | { |
1257 | unsigned char val; | |
1258 | int timeout; | |
1259 | ||
1dddab40 TI |
1260 | azx_stream_clear(chip, azx_dev); |
1261 | ||
d01ce99f TI |
1262 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | |
1263 | SD_CTL_STREAM_RESET); | |
1da177e4 LT |
1264 | udelay(3); |
1265 | timeout = 300; | |
1266 | while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
1267 | --timeout) | |
1268 | ; | |
1269 | val &= ~SD_CTL_STREAM_RESET; | |
1270 | azx_sd_writeb(azx_dev, SD_CTL, val); | |
1271 | udelay(3); | |
1272 | ||
1273 | timeout = 300; | |
1274 | /* waiting for hardware to report that the stream is out of reset */ | |
1275 | while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
1276 | --timeout) | |
1277 | ; | |
fa00e046 JK |
1278 | |
1279 | /* reset first position - may not be synced with hw at this time */ | |
1280 | *azx_dev->posbuf = 0; | |
1dddab40 | 1281 | } |
1da177e4 | 1282 | |
1dddab40 TI |
1283 | /* |
1284 | * set up the SD for streaming | |
1285 | */ | |
1286 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) | |
1287 | { | |
1288 | /* make sure the run bit is zero for SD */ | |
1289 | azx_stream_clear(chip, azx_dev); | |
1da177e4 LT |
1290 | /* program the stream_tag */ |
1291 | azx_sd_writel(azx_dev, SD_CTL, | |
d01ce99f | 1292 | (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)| |
1da177e4 LT |
1293 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); |
1294 | ||
1295 | /* program the length of samples in cyclic buffer */ | |
1296 | azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
1297 | ||
1298 | /* program the stream format */ | |
1299 | /* this value needs to be the same as the one programmed */ | |
1300 | azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
1301 | ||
1302 | /* program the stream LVI (last valid index) of the BDL */ | |
1303 | azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
1304 | ||
1305 | /* program the BDL address */ | |
1306 | /* lower BDL address */ | |
4ce107b9 | 1307 | azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); |
1da177e4 | 1308 | /* upper BDL address */ |
766979e0 | 1309 | azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); |
1da177e4 | 1310 | |
0be3b5d3 | 1311 | /* enable the position buffer */ |
beaffc39 SG |
1312 | if (chip->position_fix[0] == POS_FIX_POSBUF || |
1313 | chip->position_fix[0] == POS_FIX_AUTO || | |
1314 | chip->position_fix[1] == POS_FIX_POSBUF || | |
1315 | chip->position_fix[1] == POS_FIX_AUTO || | |
0e153474 | 1316 | chip->via_dmapos_patch) { |
ee9d6b9a TI |
1317 | if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) |
1318 | azx_writel(chip, DPLBASE, | |
1319 | (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
1320 | } | |
c74db86b | 1321 | |
1da177e4 | 1322 | /* set the interrupt enable bits in the descriptor control register */ |
d01ce99f TI |
1323 | azx_sd_writel(azx_dev, SD_CTL, |
1324 | azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); | |
1da177e4 LT |
1325 | |
1326 | return 0; | |
1327 | } | |
1328 | ||
6ce4a3bc TI |
1329 | /* |
1330 | * Probe the given codec address | |
1331 | */ | |
1332 | static int probe_codec(struct azx *chip, int addr) | |
1333 | { | |
1334 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | |
1335 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
1336 | unsigned int res; | |
1337 | ||
a678cdee | 1338 | mutex_lock(&chip->bus->cmd_mutex); |
6ce4a3bc TI |
1339 | chip->probing = 1; |
1340 | azx_send_cmd(chip->bus, cmd); | |
deadff16 | 1341 | res = azx_get_response(chip->bus, addr); |
6ce4a3bc | 1342 | chip->probing = 0; |
a678cdee | 1343 | mutex_unlock(&chip->bus->cmd_mutex); |
6ce4a3bc TI |
1344 | if (res == -1) |
1345 | return -EIO; | |
4abc1cc2 | 1346 | snd_printdd(SFX "codec #%d probed OK\n", addr); |
6ce4a3bc TI |
1347 | return 0; |
1348 | } | |
1349 | ||
33fa35ed TI |
1350 | static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, |
1351 | struct hda_pcm *cpcm); | |
6ce4a3bc | 1352 | static void azx_stop_chip(struct azx *chip); |
1da177e4 | 1353 | |
8dd78330 TI |
1354 | static void azx_bus_reset(struct hda_bus *bus) |
1355 | { | |
1356 | struct azx *chip = bus->private_data; | |
8dd78330 TI |
1357 | |
1358 | bus->in_reset = 1; | |
1359 | azx_stop_chip(chip); | |
cd508fe5 | 1360 | azx_init_chip(chip, 1); |
65f75983 | 1361 | #ifdef CONFIG_PM |
8dd78330 | 1362 | if (chip->initialized) { |
65f75983 AB |
1363 | int i; |
1364 | ||
c8936222 | 1365 | for (i = 0; i < HDA_MAX_PCMS; i++) |
8dd78330 TI |
1366 | snd_pcm_suspend_all(chip->pcm[i]); |
1367 | snd_hda_suspend(chip->bus); | |
1368 | snd_hda_resume(chip->bus); | |
1369 | } | |
65f75983 | 1370 | #endif |
8dd78330 TI |
1371 | bus->in_reset = 0; |
1372 | } | |
1373 | ||
1da177e4 LT |
1374 | /* |
1375 | * Codec initialization | |
1376 | */ | |
1377 | ||
2f5983f2 TI |
1378 | /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ |
1379 | static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = { | |
7445dfc1 | 1380 | [AZX_DRIVER_NVIDIA] = 8, |
f269002e | 1381 | [AZX_DRIVER_TERA] = 1, |
a9995a35 TI |
1382 | }; |
1383 | ||
a1e21c90 | 1384 | static int __devinit azx_codec_create(struct azx *chip, const char *model) |
1da177e4 LT |
1385 | { |
1386 | struct hda_bus_template bus_temp; | |
34c25350 TI |
1387 | int c, codecs, err; |
1388 | int max_slots; | |
1da177e4 LT |
1389 | |
1390 | memset(&bus_temp, 0, sizeof(bus_temp)); | |
1391 | bus_temp.private_data = chip; | |
1392 | bus_temp.modelname = model; | |
1393 | bus_temp.pci = chip->pci; | |
111d3af5 TI |
1394 | bus_temp.ops.command = azx_send_cmd; |
1395 | bus_temp.ops.get_response = azx_get_response; | |
176d5335 | 1396 | bus_temp.ops.attach_pcm = azx_attach_pcm_stream; |
8dd78330 | 1397 | bus_temp.ops.bus_reset = azx_bus_reset; |
cb53c626 | 1398 | #ifdef CONFIG_SND_HDA_POWER_SAVE |
11cd41b8 | 1399 | bus_temp.power_save = &power_save; |
cb53c626 TI |
1400 | bus_temp.ops.pm_notify = azx_power_notify; |
1401 | #endif | |
1da177e4 | 1402 | |
d01ce99f TI |
1403 | err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); |
1404 | if (err < 0) | |
1da177e4 LT |
1405 | return err; |
1406 | ||
dc9c8e21 WN |
1407 | if (chip->driver_type == AZX_DRIVER_NVIDIA) |
1408 | chip->bus->needs_damn_long_delay = 1; | |
1409 | ||
34c25350 | 1410 | codecs = 0; |
2f5983f2 TI |
1411 | max_slots = azx_max_codecs[chip->driver_type]; |
1412 | if (!max_slots) | |
7445dfc1 | 1413 | max_slots = AZX_DEFAULT_CODECS; |
6ce4a3bc TI |
1414 | |
1415 | /* First try to probe all given codec slots */ | |
1416 | for (c = 0; c < max_slots; c++) { | |
f1eaaeec | 1417 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
6ce4a3bc TI |
1418 | if (probe_codec(chip, c) < 0) { |
1419 | /* Some BIOSen give you wrong codec addresses | |
1420 | * that don't exist | |
1421 | */ | |
4abc1cc2 TI |
1422 | snd_printk(KERN_WARNING SFX |
1423 | "Codec #%d probe error; " | |
6ce4a3bc TI |
1424 | "disabling it...\n", c); |
1425 | chip->codec_mask &= ~(1 << c); | |
1426 | /* More badly, accessing to a non-existing | |
1427 | * codec often screws up the controller chip, | |
2448158e | 1428 | * and disturbs the further communications. |
6ce4a3bc TI |
1429 | * Thus if an error occurs during probing, |
1430 | * better to reset the controller chip to | |
1431 | * get back to the sanity state. | |
1432 | */ | |
1433 | azx_stop_chip(chip); | |
cd508fe5 | 1434 | azx_init_chip(chip, 1); |
6ce4a3bc TI |
1435 | } |
1436 | } | |
1437 | } | |
1438 | ||
1439 | /* Then create codec instances */ | |
34c25350 | 1440 | for (c = 0; c < max_slots; c++) { |
f1eaaeec | 1441 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
bccad14e | 1442 | struct hda_codec *codec; |
a1e21c90 | 1443 | err = snd_hda_codec_new(chip->bus, c, &codec); |
1da177e4 LT |
1444 | if (err < 0) |
1445 | continue; | |
2dca0bba | 1446 | codec->beep_mode = chip->beep_mode; |
1da177e4 | 1447 | codecs++; |
19a982b6 TI |
1448 | } |
1449 | } | |
1450 | if (!codecs) { | |
1da177e4 LT |
1451 | snd_printk(KERN_ERR SFX "no codecs initialized\n"); |
1452 | return -ENXIO; | |
1453 | } | |
a1e21c90 TI |
1454 | return 0; |
1455 | } | |
1da177e4 | 1456 | |
a1e21c90 TI |
1457 | /* configure each codec instance */ |
1458 | static int __devinit azx_codec_configure(struct azx *chip) | |
1459 | { | |
1460 | struct hda_codec *codec; | |
1461 | list_for_each_entry(codec, &chip->bus->codec_list, list) { | |
1462 | snd_hda_codec_configure(codec); | |
1463 | } | |
1da177e4 LT |
1464 | return 0; |
1465 | } | |
1466 | ||
1467 | ||
1468 | /* | |
1469 | * PCM support | |
1470 | */ | |
1471 | ||
1472 | /* assign a stream for the PCM */ | |
ef18bede WF |
1473 | static inline struct azx_dev * |
1474 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) | |
1da177e4 | 1475 | { |
07e4ca50 | 1476 | int dev, i, nums; |
ef18bede WF |
1477 | struct azx_dev *res = NULL; |
1478 | ||
1479 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
07e4ca50 TI |
1480 | dev = chip->playback_index_offset; |
1481 | nums = chip->playback_streams; | |
1482 | } else { | |
1483 | dev = chip->capture_index_offset; | |
1484 | nums = chip->capture_streams; | |
1485 | } | |
1486 | for (i = 0; i < nums; i++, dev++) | |
d01ce99f | 1487 | if (!chip->azx_dev[dev].opened) { |
ef18bede WF |
1488 | res = &chip->azx_dev[dev]; |
1489 | if (res->device == substream->pcm->device) | |
1490 | break; | |
1da177e4 | 1491 | } |
ef18bede WF |
1492 | if (res) { |
1493 | res->opened = 1; | |
1494 | res->device = substream->pcm->device; | |
1495 | } | |
1496 | return res; | |
1da177e4 LT |
1497 | } |
1498 | ||
1499 | /* release the assigned stream */ | |
a98f90fd | 1500 | static inline void azx_release_device(struct azx_dev *azx_dev) |
1da177e4 LT |
1501 | { |
1502 | azx_dev->opened = 0; | |
1503 | } | |
1504 | ||
a98f90fd | 1505 | static struct snd_pcm_hardware azx_pcm_hw = { |
d01ce99f TI |
1506 | .info = (SNDRV_PCM_INFO_MMAP | |
1507 | SNDRV_PCM_INFO_INTERLEAVED | | |
1da177e4 LT |
1508 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
1509 | SNDRV_PCM_INFO_MMAP_VALID | | |
927fc866 PM |
1510 | /* No full-resume yet implemented */ |
1511 | /* SNDRV_PCM_INFO_RESUME |*/ | |
850f0e52 TI |
1512 | SNDRV_PCM_INFO_PAUSE | |
1513 | SNDRV_PCM_INFO_SYNC_START), | |
1da177e4 LT |
1514 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1515 | .rates = SNDRV_PCM_RATE_48000, | |
1516 | .rate_min = 48000, | |
1517 | .rate_max = 48000, | |
1518 | .channels_min = 2, | |
1519 | .channels_max = 2, | |
1520 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
1521 | .period_bytes_min = 128, | |
1522 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
1523 | .periods_min = 2, | |
1524 | .periods_max = AZX_MAX_FRAG, | |
1525 | .fifo_size = 0, | |
1526 | }; | |
1527 | ||
1528 | struct azx_pcm { | |
a98f90fd | 1529 | struct azx *chip; |
1da177e4 LT |
1530 | struct hda_codec *codec; |
1531 | struct hda_pcm_stream *hinfo[2]; | |
1532 | }; | |
1533 | ||
a98f90fd | 1534 | static int azx_pcm_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1535 | { |
1536 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1537 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1538 | struct azx *chip = apcm->chip; |
1539 | struct azx_dev *azx_dev; | |
1540 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1541 | unsigned long flags; |
1542 | int err; | |
1543 | ||
62932df8 | 1544 | mutex_lock(&chip->open_mutex); |
ef18bede | 1545 | azx_dev = azx_assign_device(chip, substream); |
1da177e4 | 1546 | if (azx_dev == NULL) { |
62932df8 | 1547 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1548 | return -EBUSY; |
1549 | } | |
1550 | runtime->hw = azx_pcm_hw; | |
1551 | runtime->hw.channels_min = hinfo->channels_min; | |
1552 | runtime->hw.channels_max = hinfo->channels_max; | |
1553 | runtime->hw.formats = hinfo->formats; | |
1554 | runtime->hw.rates = hinfo->rates; | |
1555 | snd_pcm_limit_hw_rates(runtime); | |
1556 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
5f1545bc JD |
1557 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, |
1558 | 128); | |
1559 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
1560 | 128); | |
cb53c626 | 1561 | snd_hda_power_up(apcm->codec); |
d01ce99f TI |
1562 | err = hinfo->ops.open(hinfo, apcm->codec, substream); |
1563 | if (err < 0) { | |
1da177e4 | 1564 | azx_release_device(azx_dev); |
cb53c626 | 1565 | snd_hda_power_down(apcm->codec); |
62932df8 | 1566 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1567 | return err; |
1568 | } | |
70d321e6 | 1569 | snd_pcm_limit_hw_rates(runtime); |
aba66536 TI |
1570 | /* sanity check */ |
1571 | if (snd_BUG_ON(!runtime->hw.channels_min) || | |
1572 | snd_BUG_ON(!runtime->hw.channels_max) || | |
1573 | snd_BUG_ON(!runtime->hw.formats) || | |
1574 | snd_BUG_ON(!runtime->hw.rates)) { | |
1575 | azx_release_device(azx_dev); | |
1576 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
1577 | snd_hda_power_down(apcm->codec); | |
1578 | mutex_unlock(&chip->open_mutex); | |
1579 | return -EINVAL; | |
1580 | } | |
1da177e4 LT |
1581 | spin_lock_irqsave(&chip->reg_lock, flags); |
1582 | azx_dev->substream = substream; | |
1583 | azx_dev->running = 0; | |
1584 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1585 | ||
1586 | runtime->private_data = azx_dev; | |
850f0e52 | 1587 | snd_pcm_set_sync(substream); |
62932df8 | 1588 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1589 | return 0; |
1590 | } | |
1591 | ||
a98f90fd | 1592 | static int azx_pcm_close(struct snd_pcm_substream *substream) |
1da177e4 LT |
1593 | { |
1594 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1595 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1596 | struct azx *chip = apcm->chip; |
1597 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 LT |
1598 | unsigned long flags; |
1599 | ||
62932df8 | 1600 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
1601 | spin_lock_irqsave(&chip->reg_lock, flags); |
1602 | azx_dev->substream = NULL; | |
1603 | azx_dev->running = 0; | |
1604 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1605 | azx_release_device(azx_dev); | |
1606 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
cb53c626 | 1607 | snd_hda_power_down(apcm->codec); |
62932df8 | 1608 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1609 | return 0; |
1610 | } | |
1611 | ||
d01ce99f TI |
1612 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, |
1613 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 1614 | { |
97b71c94 TI |
1615 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1616 | ||
1617 | azx_dev->bufsize = 0; | |
1618 | azx_dev->period_bytes = 0; | |
1619 | azx_dev->format_val = 0; | |
d01ce99f TI |
1620 | return snd_pcm_lib_malloc_pages(substream, |
1621 | params_buffer_bytes(hw_params)); | |
1da177e4 LT |
1622 | } |
1623 | ||
a98f90fd | 1624 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
1625 | { |
1626 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd | 1627 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1da177e4 LT |
1628 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
1629 | ||
1630 | /* reset BDL address */ | |
1631 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
1632 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
1633 | azx_sd_writel(azx_dev, SD_CTL, 0); | |
97b71c94 TI |
1634 | azx_dev->bufsize = 0; |
1635 | azx_dev->period_bytes = 0; | |
1636 | azx_dev->format_val = 0; | |
1da177e4 | 1637 | |
eb541337 | 1638 | snd_hda_codec_cleanup(apcm->codec, hinfo, substream); |
1da177e4 LT |
1639 | |
1640 | return snd_pcm_lib_free_pages(substream); | |
1641 | } | |
1642 | ||
a98f90fd | 1643 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 LT |
1644 | { |
1645 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd TI |
1646 | struct azx *chip = apcm->chip; |
1647 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 | 1648 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
a98f90fd | 1649 | struct snd_pcm_runtime *runtime = substream->runtime; |
97b71c94 TI |
1650 | unsigned int bufsize, period_bytes, format_val; |
1651 | int err; | |
1da177e4 | 1652 | |
fa00e046 | 1653 | azx_stream_reset(chip, azx_dev); |
97b71c94 TI |
1654 | format_val = snd_hda_calc_stream_format(runtime->rate, |
1655 | runtime->channels, | |
1656 | runtime->format, | |
32c168c8 AH |
1657 | hinfo->maxbps, |
1658 | apcm->codec->spdif_ctls); | |
97b71c94 | 1659 | if (!format_val) { |
d01ce99f TI |
1660 | snd_printk(KERN_ERR SFX |
1661 | "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
1da177e4 LT |
1662 | runtime->rate, runtime->channels, runtime->format); |
1663 | return -EINVAL; | |
1664 | } | |
1665 | ||
97b71c94 TI |
1666 | bufsize = snd_pcm_lib_buffer_bytes(substream); |
1667 | period_bytes = snd_pcm_lib_period_bytes(substream); | |
1668 | ||
4abc1cc2 | 1669 | snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", |
97b71c94 TI |
1670 | bufsize, format_val); |
1671 | ||
1672 | if (bufsize != azx_dev->bufsize || | |
1673 | period_bytes != azx_dev->period_bytes || | |
1674 | format_val != azx_dev->format_val) { | |
1675 | azx_dev->bufsize = bufsize; | |
1676 | azx_dev->period_bytes = period_bytes; | |
1677 | azx_dev->format_val = format_val; | |
1678 | err = azx_setup_periods(chip, substream, azx_dev); | |
1679 | if (err < 0) | |
1680 | return err; | |
1681 | } | |
1682 | ||
e5463720 JK |
1683 | /* wallclk has 24Mhz clock source */ |
1684 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | |
1685 | runtime->rate) * 1000); | |
1da177e4 LT |
1686 | azx_setup_controller(chip, azx_dev); |
1687 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1688 | azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; | |
1689 | else | |
1690 | azx_dev->fifo_size = 0; | |
1691 | ||
eb541337 TI |
1692 | return snd_hda_codec_prepare(apcm->codec, hinfo, azx_dev->stream_tag, |
1693 | azx_dev->format_val, substream); | |
1da177e4 LT |
1694 | } |
1695 | ||
a98f90fd | 1696 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 LT |
1697 | { |
1698 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd | 1699 | struct azx *chip = apcm->chip; |
850f0e52 TI |
1700 | struct azx_dev *azx_dev; |
1701 | struct snd_pcm_substream *s; | |
fa00e046 | 1702 | int rstart = 0, start, nsync = 0, sbits = 0; |
850f0e52 | 1703 | int nwait, timeout; |
1da177e4 | 1704 | |
1da177e4 | 1705 | switch (cmd) { |
fa00e046 JK |
1706 | case SNDRV_PCM_TRIGGER_START: |
1707 | rstart = 1; | |
1da177e4 LT |
1708 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1709 | case SNDRV_PCM_TRIGGER_RESUME: | |
850f0e52 | 1710 | start = 1; |
1da177e4 LT |
1711 | break; |
1712 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
47123197 | 1713 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 | 1714 | case SNDRV_PCM_TRIGGER_STOP: |
850f0e52 | 1715 | start = 0; |
1da177e4 LT |
1716 | break; |
1717 | default: | |
850f0e52 TI |
1718 | return -EINVAL; |
1719 | } | |
1720 | ||
1721 | snd_pcm_group_for_each_entry(s, substream) { | |
1722 | if (s->pcm->card != substream->pcm->card) | |
1723 | continue; | |
1724 | azx_dev = get_azx_dev(s); | |
1725 | sbits |= 1 << azx_dev->index; | |
1726 | nsync++; | |
1727 | snd_pcm_trigger_done(s, substream); | |
1728 | } | |
1729 | ||
1730 | spin_lock(&chip->reg_lock); | |
1731 | if (nsync > 1) { | |
1732 | /* first, set SYNC bits of corresponding streams */ | |
1733 | azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits); | |
1734 | } | |
1735 | snd_pcm_group_for_each_entry(s, substream) { | |
1736 | if (s->pcm->card != substream->pcm->card) | |
1737 | continue; | |
1738 | azx_dev = get_azx_dev(s); | |
e5463720 JK |
1739 | if (start) { |
1740 | azx_dev->start_wallclk = azx_readl(chip, WALLCLK); | |
1741 | if (!rstart) | |
1742 | azx_dev->start_wallclk -= | |
1743 | azx_dev->period_wallclk; | |
850f0e52 | 1744 | azx_stream_start(chip, azx_dev); |
e5463720 | 1745 | } else { |
850f0e52 | 1746 | azx_stream_stop(chip, azx_dev); |
e5463720 | 1747 | } |
850f0e52 | 1748 | azx_dev->running = start; |
1da177e4 LT |
1749 | } |
1750 | spin_unlock(&chip->reg_lock); | |
850f0e52 TI |
1751 | if (start) { |
1752 | if (nsync == 1) | |
1753 | return 0; | |
1754 | /* wait until all FIFOs get ready */ | |
1755 | for (timeout = 5000; timeout; timeout--) { | |
1756 | nwait = 0; | |
1757 | snd_pcm_group_for_each_entry(s, substream) { | |
1758 | if (s->pcm->card != substream->pcm->card) | |
1759 | continue; | |
1760 | azx_dev = get_azx_dev(s); | |
1761 | if (!(azx_sd_readb(azx_dev, SD_STS) & | |
1762 | SD_STS_FIFO_READY)) | |
1763 | nwait++; | |
1764 | } | |
1765 | if (!nwait) | |
1766 | break; | |
1767 | cpu_relax(); | |
1768 | } | |
1769 | } else { | |
1770 | /* wait until all RUN bits are cleared */ | |
1771 | for (timeout = 5000; timeout; timeout--) { | |
1772 | nwait = 0; | |
1773 | snd_pcm_group_for_each_entry(s, substream) { | |
1774 | if (s->pcm->card != substream->pcm->card) | |
1775 | continue; | |
1776 | azx_dev = get_azx_dev(s); | |
1777 | if (azx_sd_readb(azx_dev, SD_CTL) & | |
1778 | SD_CTL_DMA_START) | |
1779 | nwait++; | |
1780 | } | |
1781 | if (!nwait) | |
1782 | break; | |
1783 | cpu_relax(); | |
1784 | } | |
1da177e4 | 1785 | } |
850f0e52 TI |
1786 | if (nsync > 1) { |
1787 | spin_lock(&chip->reg_lock); | |
1788 | /* reset SYNC bits */ | |
1789 | azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits); | |
1790 | spin_unlock(&chip->reg_lock); | |
1791 | } | |
1792 | return 0; | |
1da177e4 LT |
1793 | } |
1794 | ||
0e153474 JC |
1795 | /* get the current DMA position with correction on VIA chips */ |
1796 | static unsigned int azx_via_get_position(struct azx *chip, | |
1797 | struct azx_dev *azx_dev) | |
1798 | { | |
1799 | unsigned int link_pos, mini_pos, bound_pos; | |
1800 | unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; | |
1801 | unsigned int fifo_size; | |
1802 | ||
1803 | link_pos = azx_sd_readl(azx_dev, SD_LPIB); | |
1804 | if (azx_dev->index >= 4) { | |
1805 | /* Playback, no problem using link position */ | |
1806 | return link_pos; | |
1807 | } | |
1808 | ||
1809 | /* Capture */ | |
1810 | /* For new chipset, | |
1811 | * use mod to get the DMA position just like old chipset | |
1812 | */ | |
1813 | mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); | |
1814 | mod_dma_pos %= azx_dev->period_bytes; | |
1815 | ||
1816 | /* azx_dev->fifo_size can't get FIFO size of in stream. | |
1817 | * Get from base address + offset. | |
1818 | */ | |
1819 | fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); | |
1820 | ||
1821 | if (azx_dev->insufficient) { | |
1822 | /* Link position never gather than FIFO size */ | |
1823 | if (link_pos <= fifo_size) | |
1824 | return 0; | |
1825 | ||
1826 | azx_dev->insufficient = 0; | |
1827 | } | |
1828 | ||
1829 | if (link_pos <= fifo_size) | |
1830 | mini_pos = azx_dev->bufsize + link_pos - fifo_size; | |
1831 | else | |
1832 | mini_pos = link_pos - fifo_size; | |
1833 | ||
1834 | /* Find nearest previous boudary */ | |
1835 | mod_mini_pos = mini_pos % azx_dev->period_bytes; | |
1836 | mod_link_pos = link_pos % azx_dev->period_bytes; | |
1837 | if (mod_link_pos >= fifo_size) | |
1838 | bound_pos = link_pos - mod_link_pos; | |
1839 | else if (mod_dma_pos >= mod_mini_pos) | |
1840 | bound_pos = mini_pos - mod_mini_pos; | |
1841 | else { | |
1842 | bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; | |
1843 | if (bound_pos >= azx_dev->bufsize) | |
1844 | bound_pos = 0; | |
1845 | } | |
1846 | ||
1847 | /* Calculate real DMA position we want */ | |
1848 | return bound_pos + mod_dma_pos; | |
1849 | } | |
1850 | ||
9ad593f6 TI |
1851 | static unsigned int azx_get_position(struct azx *chip, |
1852 | struct azx_dev *azx_dev) | |
1da177e4 | 1853 | { |
1da177e4 LT |
1854 | unsigned int pos; |
1855 | ||
0e153474 JC |
1856 | if (chip->via_dmapos_patch) |
1857 | pos = azx_via_get_position(chip, azx_dev); | |
beaffc39 SG |
1858 | else { |
1859 | int stream = azx_dev->substream->stream; | |
1860 | if (chip->position_fix[stream] == POS_FIX_POSBUF || | |
1861 | chip->position_fix[stream] == POS_FIX_AUTO) { | |
1862 | /* use the position buffer */ | |
1863 | pos = le32_to_cpu(*azx_dev->posbuf); | |
1864 | } else { | |
1865 | /* read LPIB */ | |
1866 | pos = azx_sd_readl(azx_dev, SD_LPIB); | |
1867 | } | |
c74db86b | 1868 | } |
1da177e4 LT |
1869 | if (pos >= azx_dev->bufsize) |
1870 | pos = 0; | |
9ad593f6 TI |
1871 | return pos; |
1872 | } | |
1873 | ||
1874 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | |
1875 | { | |
1876 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1877 | struct azx *chip = apcm->chip; | |
1878 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1879 | return bytes_to_frames(substream->runtime, | |
1880 | azx_get_position(chip, azx_dev)); | |
1881 | } | |
1882 | ||
1883 | /* | |
1884 | * Check whether the current DMA position is acceptable for updating | |
1885 | * periods. Returns non-zero if it's OK. | |
1886 | * | |
1887 | * Many HD-audio controllers appear pretty inaccurate about | |
1888 | * the update-IRQ timing. The IRQ is issued before actually the | |
1889 | * data is processed. So, we need to process it afterwords in a | |
1890 | * workqueue. | |
1891 | */ | |
1892 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) | |
1893 | { | |
e5463720 | 1894 | u32 wallclk; |
9ad593f6 | 1895 | unsigned int pos; |
beaffc39 | 1896 | int stream; |
9ad593f6 | 1897 | |
f48f606d JK |
1898 | wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; |
1899 | if (wallclk < (azx_dev->period_wallclk * 2) / 3) | |
fa00e046 | 1900 | return -1; /* bogus (too early) interrupt */ |
fa00e046 | 1901 | |
beaffc39 | 1902 | stream = azx_dev->substream->stream; |
9ad593f6 | 1903 | pos = azx_get_position(chip, azx_dev); |
beaffc39 | 1904 | if (chip->position_fix[stream] == POS_FIX_AUTO) { |
9ad593f6 TI |
1905 | if (!pos) { |
1906 | printk(KERN_WARNING | |
1907 | "hda-intel: Invalid position buffer, " | |
1908 | "using LPIB read method instead.\n"); | |
beaffc39 | 1909 | chip->position_fix[stream] = POS_FIX_LPIB; |
9ad593f6 TI |
1910 | pos = azx_get_position(chip, azx_dev); |
1911 | } else | |
beaffc39 | 1912 | chip->position_fix[stream] = POS_FIX_POSBUF; |
9ad593f6 TI |
1913 | } |
1914 | ||
d6d8bf54 TI |
1915 | if (WARN_ONCE(!azx_dev->period_bytes, |
1916 | "hda-intel: zero azx_dev->period_bytes")) | |
f48f606d | 1917 | return -1; /* this shouldn't happen! */ |
edb39935 | 1918 | if (wallclk < (azx_dev->period_wallclk * 5) / 4 && |
f48f606d JK |
1919 | pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) |
1920 | /* NG - it's below the first next period boundary */ | |
1921 | return bdl_pos_adj[chip->dev_index] ? 0 : -1; | |
edb39935 | 1922 | azx_dev->start_wallclk += wallclk; |
9ad593f6 TI |
1923 | return 1; /* OK, it's fine */ |
1924 | } | |
1925 | ||
1926 | /* | |
1927 | * The work for pending PCM period updates. | |
1928 | */ | |
1929 | static void azx_irq_pending_work(struct work_struct *work) | |
1930 | { | |
1931 | struct azx *chip = container_of(work, struct azx, irq_pending_work); | |
e5463720 | 1932 | int i, pending, ok; |
9ad593f6 | 1933 | |
a6a950a8 TI |
1934 | if (!chip->irq_pending_warned) { |
1935 | printk(KERN_WARNING | |
1936 | "hda-intel: IRQ timing workaround is activated " | |
1937 | "for card #%d. Suggest a bigger bdl_pos_adj.\n", | |
1938 | chip->card->number); | |
1939 | chip->irq_pending_warned = 1; | |
1940 | } | |
1941 | ||
9ad593f6 TI |
1942 | for (;;) { |
1943 | pending = 0; | |
1944 | spin_lock_irq(&chip->reg_lock); | |
1945 | for (i = 0; i < chip->num_streams; i++) { | |
1946 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | |
1947 | if (!azx_dev->irq_pending || | |
1948 | !azx_dev->substream || | |
1949 | !azx_dev->running) | |
1950 | continue; | |
e5463720 JK |
1951 | ok = azx_position_ok(chip, azx_dev); |
1952 | if (ok > 0) { | |
9ad593f6 TI |
1953 | azx_dev->irq_pending = 0; |
1954 | spin_unlock(&chip->reg_lock); | |
1955 | snd_pcm_period_elapsed(azx_dev->substream); | |
1956 | spin_lock(&chip->reg_lock); | |
e5463720 JK |
1957 | } else if (ok < 0) { |
1958 | pending = 0; /* too early */ | |
9ad593f6 TI |
1959 | } else |
1960 | pending++; | |
1961 | } | |
1962 | spin_unlock_irq(&chip->reg_lock); | |
1963 | if (!pending) | |
1964 | return; | |
08af495f | 1965 | msleep(1); |
9ad593f6 TI |
1966 | } |
1967 | } | |
1968 | ||
1969 | /* clear irq_pending flags and assure no on-going workq */ | |
1970 | static void azx_clear_irq_pending(struct azx *chip) | |
1971 | { | |
1972 | int i; | |
1973 | ||
1974 | spin_lock_irq(&chip->reg_lock); | |
1975 | for (i = 0; i < chip->num_streams; i++) | |
1976 | chip->azx_dev[i].irq_pending = 0; | |
1977 | spin_unlock_irq(&chip->reg_lock); | |
1da177e4 LT |
1978 | } |
1979 | ||
a98f90fd | 1980 | static struct snd_pcm_ops azx_pcm_ops = { |
1da177e4 LT |
1981 | .open = azx_pcm_open, |
1982 | .close = azx_pcm_close, | |
1983 | .ioctl = snd_pcm_lib_ioctl, | |
1984 | .hw_params = azx_pcm_hw_params, | |
1985 | .hw_free = azx_pcm_hw_free, | |
1986 | .prepare = azx_pcm_prepare, | |
1987 | .trigger = azx_pcm_trigger, | |
1988 | .pointer = azx_pcm_pointer, | |
4ce107b9 | 1989 | .page = snd_pcm_sgbuf_ops_page, |
1da177e4 LT |
1990 | }; |
1991 | ||
a98f90fd | 1992 | static void azx_pcm_free(struct snd_pcm *pcm) |
1da177e4 | 1993 | { |
176d5335 TI |
1994 | struct azx_pcm *apcm = pcm->private_data; |
1995 | if (apcm) { | |
1996 | apcm->chip->pcm[pcm->device] = NULL; | |
1997 | kfree(apcm); | |
1998 | } | |
1da177e4 LT |
1999 | } |
2000 | ||
176d5335 | 2001 | static int |
33fa35ed TI |
2002 | azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, |
2003 | struct hda_pcm *cpcm) | |
1da177e4 | 2004 | { |
33fa35ed | 2005 | struct azx *chip = bus->private_data; |
a98f90fd | 2006 | struct snd_pcm *pcm; |
1da177e4 | 2007 | struct azx_pcm *apcm; |
176d5335 TI |
2008 | int pcm_dev = cpcm->device; |
2009 | int s, err; | |
1da177e4 | 2010 | |
c8936222 | 2011 | if (pcm_dev >= HDA_MAX_PCMS) { |
176d5335 TI |
2012 | snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n", |
2013 | pcm_dev); | |
da3cec35 | 2014 | return -EINVAL; |
176d5335 TI |
2015 | } |
2016 | if (chip->pcm[pcm_dev]) { | |
2017 | snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev); | |
2018 | return -EBUSY; | |
2019 | } | |
2020 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
2021 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, | |
2022 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, | |
1da177e4 LT |
2023 | &pcm); |
2024 | if (err < 0) | |
2025 | return err; | |
18cb7109 | 2026 | strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); |
176d5335 | 2027 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); |
1da177e4 LT |
2028 | if (apcm == NULL) |
2029 | return -ENOMEM; | |
2030 | apcm->chip = chip; | |
2031 | apcm->codec = codec; | |
1da177e4 LT |
2032 | pcm->private_data = apcm; |
2033 | pcm->private_free = azx_pcm_free; | |
176d5335 TI |
2034 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) |
2035 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; | |
2036 | chip->pcm[pcm_dev] = pcm; | |
2037 | cpcm->pcm = pcm; | |
2038 | for (s = 0; s < 2; s++) { | |
2039 | apcm->hinfo[s] = &cpcm->stream[s]; | |
2040 | if (cpcm->stream[s].substreams) | |
2041 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); | |
2042 | } | |
2043 | /* buffer pre-allocation */ | |
4ce107b9 | 2044 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, |
1da177e4 | 2045 | snd_dma_pci_data(chip->pci), |
fc4abee8 | 2046 | 1024 * 64, 32 * 1024 * 1024); |
1da177e4 LT |
2047 | return 0; |
2048 | } | |
2049 | ||
2050 | /* | |
2051 | * mixer creation - all stuff is implemented in hda module | |
2052 | */ | |
a98f90fd | 2053 | static int __devinit azx_mixer_create(struct azx *chip) |
1da177e4 LT |
2054 | { |
2055 | return snd_hda_build_controls(chip->bus); | |
2056 | } | |
2057 | ||
2058 | ||
2059 | /* | |
2060 | * initialize SD streams | |
2061 | */ | |
a98f90fd | 2062 | static int __devinit azx_init_stream(struct azx *chip) |
1da177e4 LT |
2063 | { |
2064 | int i; | |
2065 | ||
2066 | /* initialize each stream (aka device) | |
d01ce99f TI |
2067 | * assign the starting bdl address to each stream (device) |
2068 | * and initialize | |
1da177e4 | 2069 | */ |
07e4ca50 | 2070 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 2071 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
929861c6 | 2072 | azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); |
1da177e4 LT |
2073 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
2074 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | |
2075 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
2076 | azx_dev->sd_int_sta_mask = 1 << i; | |
2077 | /* stream tag: must be non-zero and unique */ | |
2078 | azx_dev->index = i; | |
2079 | azx_dev->stream_tag = i + 1; | |
2080 | } | |
2081 | ||
2082 | return 0; | |
2083 | } | |
2084 | ||
68e7fffc TI |
2085 | static int azx_acquire_irq(struct azx *chip, int do_disconnect) |
2086 | { | |
437a5a46 TI |
2087 | if (request_irq(chip->pci->irq, azx_interrupt, |
2088 | chip->msi ? 0 : IRQF_SHARED, | |
9492837a | 2089 | "hda_intel", chip)) { |
68e7fffc TI |
2090 | printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " |
2091 | "disabling device\n", chip->pci->irq); | |
2092 | if (do_disconnect) | |
2093 | snd_card_disconnect(chip->card); | |
2094 | return -1; | |
2095 | } | |
2096 | chip->irq = chip->pci->irq; | |
69e13418 | 2097 | pci_intx(chip->pci, !chip->msi); |
68e7fffc TI |
2098 | return 0; |
2099 | } | |
2100 | ||
1da177e4 | 2101 | |
cb53c626 TI |
2102 | static void azx_stop_chip(struct azx *chip) |
2103 | { | |
95e99fda | 2104 | if (!chip->initialized) |
cb53c626 TI |
2105 | return; |
2106 | ||
2107 | /* disable interrupts */ | |
2108 | azx_int_disable(chip); | |
2109 | azx_int_clear(chip); | |
2110 | ||
2111 | /* disable CORB/RIRB */ | |
2112 | azx_free_cmd_io(chip); | |
2113 | ||
2114 | /* disable position buffer */ | |
2115 | azx_writel(chip, DPLBASE, 0); | |
2116 | azx_writel(chip, DPUBASE, 0); | |
2117 | ||
2118 | chip->initialized = 0; | |
2119 | } | |
2120 | ||
2121 | #ifdef CONFIG_SND_HDA_POWER_SAVE | |
2122 | /* power-up/down the controller */ | |
33fa35ed | 2123 | static void azx_power_notify(struct hda_bus *bus) |
cb53c626 | 2124 | { |
33fa35ed | 2125 | struct azx *chip = bus->private_data; |
cb53c626 TI |
2126 | struct hda_codec *c; |
2127 | int power_on = 0; | |
2128 | ||
33fa35ed | 2129 | list_for_each_entry(c, &bus->codec_list, list) { |
cb53c626 TI |
2130 | if (c->power_on) { |
2131 | power_on = 1; | |
2132 | break; | |
2133 | } | |
2134 | } | |
2135 | if (power_on) | |
cd508fe5 | 2136 | azx_init_chip(chip, 1); |
0287d970 WF |
2137 | else if (chip->running && power_save_controller && |
2138 | !bus->power_keep_link_on) | |
cb53c626 | 2139 | azx_stop_chip(chip); |
cb53c626 | 2140 | } |
5c0b9bec TI |
2141 | #endif /* CONFIG_SND_HDA_POWER_SAVE */ |
2142 | ||
2143 | #ifdef CONFIG_PM | |
2144 | /* | |
2145 | * power management | |
2146 | */ | |
986862bd TI |
2147 | |
2148 | static int snd_hda_codecs_inuse(struct hda_bus *bus) | |
2149 | { | |
2150 | struct hda_codec *codec; | |
2151 | ||
2152 | list_for_each_entry(codec, &bus->codec_list, list) { | |
2153 | if (snd_hda_codec_needs_resume(codec)) | |
2154 | return 1; | |
2155 | } | |
2156 | return 0; | |
2157 | } | |
cb53c626 | 2158 | |
421a1252 | 2159 | static int azx_suspend(struct pci_dev *pci, pm_message_t state) |
1da177e4 | 2160 | { |
421a1252 TI |
2161 | struct snd_card *card = pci_get_drvdata(pci); |
2162 | struct azx *chip = card->private_data; | |
1da177e4 LT |
2163 | int i; |
2164 | ||
421a1252 | 2165 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
9ad593f6 | 2166 | azx_clear_irq_pending(chip); |
c8936222 | 2167 | for (i = 0; i < HDA_MAX_PCMS; i++) |
421a1252 | 2168 | snd_pcm_suspend_all(chip->pcm[i]); |
0b7a2e9c | 2169 | if (chip->initialized) |
8dd78330 | 2170 | snd_hda_suspend(chip->bus); |
cb53c626 | 2171 | azx_stop_chip(chip); |
30b35399 | 2172 | if (chip->irq >= 0) { |
43001c95 | 2173 | free_irq(chip->irq, chip); |
30b35399 TI |
2174 | chip->irq = -1; |
2175 | } | |
68e7fffc | 2176 | if (chip->msi) |
43001c95 | 2177 | pci_disable_msi(chip->pci); |
421a1252 TI |
2178 | pci_disable_device(pci); |
2179 | pci_save_state(pci); | |
30b35399 | 2180 | pci_set_power_state(pci, pci_choose_state(pci, state)); |
1da177e4 LT |
2181 | return 0; |
2182 | } | |
2183 | ||
421a1252 | 2184 | static int azx_resume(struct pci_dev *pci) |
1da177e4 | 2185 | { |
421a1252 TI |
2186 | struct snd_card *card = pci_get_drvdata(pci); |
2187 | struct azx *chip = card->private_data; | |
1da177e4 | 2188 | |
d14a7e0b TI |
2189 | pci_set_power_state(pci, PCI_D0); |
2190 | pci_restore_state(pci); | |
30b35399 TI |
2191 | if (pci_enable_device(pci) < 0) { |
2192 | printk(KERN_ERR "hda-intel: pci_enable_device failed, " | |
2193 | "disabling device\n"); | |
2194 | snd_card_disconnect(card); | |
2195 | return -EIO; | |
2196 | } | |
2197 | pci_set_master(pci); | |
68e7fffc TI |
2198 | if (chip->msi) |
2199 | if (pci_enable_msi(pci) < 0) | |
2200 | chip->msi = 0; | |
2201 | if (azx_acquire_irq(chip, 1) < 0) | |
30b35399 | 2202 | return -EIO; |
cb53c626 | 2203 | azx_init_pci(chip); |
d804ad92 ML |
2204 | |
2205 | if (snd_hda_codecs_inuse(chip->bus)) | |
cd508fe5 | 2206 | azx_init_chip(chip, 1); |
d804ad92 | 2207 | |
1da177e4 | 2208 | snd_hda_resume(chip->bus); |
421a1252 | 2209 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
2210 | return 0; |
2211 | } | |
2212 | #endif /* CONFIG_PM */ | |
2213 | ||
2214 | ||
0cbf0098 TI |
2215 | /* |
2216 | * reboot notifier for hang-up problem at power-down | |
2217 | */ | |
2218 | static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) | |
2219 | { | |
2220 | struct azx *chip = container_of(nb, struct azx, reboot_notifier); | |
fb8d1a34 | 2221 | snd_hda_bus_reboot_notify(chip->bus); |
0cbf0098 TI |
2222 | azx_stop_chip(chip); |
2223 | return NOTIFY_OK; | |
2224 | } | |
2225 | ||
2226 | static void azx_notifier_register(struct azx *chip) | |
2227 | { | |
2228 | chip->reboot_notifier.notifier_call = azx_halt; | |
2229 | register_reboot_notifier(&chip->reboot_notifier); | |
2230 | } | |
2231 | ||
2232 | static void azx_notifier_unregister(struct azx *chip) | |
2233 | { | |
2234 | if (chip->reboot_notifier.notifier_call) | |
2235 | unregister_reboot_notifier(&chip->reboot_notifier); | |
2236 | } | |
2237 | ||
1da177e4 LT |
2238 | /* |
2239 | * destructor | |
2240 | */ | |
a98f90fd | 2241 | static int azx_free(struct azx *chip) |
1da177e4 | 2242 | { |
4ce107b9 TI |
2243 | int i; |
2244 | ||
0cbf0098 TI |
2245 | azx_notifier_unregister(chip); |
2246 | ||
ce43fbae | 2247 | if (chip->initialized) { |
9ad593f6 | 2248 | azx_clear_irq_pending(chip); |
07e4ca50 | 2249 | for (i = 0; i < chip->num_streams; i++) |
1da177e4 | 2250 | azx_stream_stop(chip, &chip->azx_dev[i]); |
cb53c626 | 2251 | azx_stop_chip(chip); |
1da177e4 LT |
2252 | } |
2253 | ||
f000fd80 | 2254 | if (chip->irq >= 0) |
1da177e4 | 2255 | free_irq(chip->irq, (void*)chip); |
68e7fffc | 2256 | if (chip->msi) |
30b35399 | 2257 | pci_disable_msi(chip->pci); |
f079c25a TI |
2258 | if (chip->remap_addr) |
2259 | iounmap(chip->remap_addr); | |
1da177e4 | 2260 | |
4ce107b9 TI |
2261 | if (chip->azx_dev) { |
2262 | for (i = 0; i < chip->num_streams; i++) | |
2263 | if (chip->azx_dev[i].bdl.area) | |
2264 | snd_dma_free_pages(&chip->azx_dev[i].bdl); | |
2265 | } | |
1da177e4 LT |
2266 | if (chip->rb.area) |
2267 | snd_dma_free_pages(&chip->rb); | |
1da177e4 LT |
2268 | if (chip->posbuf.area) |
2269 | snd_dma_free_pages(&chip->posbuf); | |
1da177e4 LT |
2270 | pci_release_regions(chip->pci); |
2271 | pci_disable_device(chip->pci); | |
07e4ca50 | 2272 | kfree(chip->azx_dev); |
1da177e4 LT |
2273 | kfree(chip); |
2274 | ||
2275 | return 0; | |
2276 | } | |
2277 | ||
a98f90fd | 2278 | static int azx_dev_free(struct snd_device *device) |
1da177e4 LT |
2279 | { |
2280 | return azx_free(device->device_data); | |
2281 | } | |
2282 | ||
3372a153 TI |
2283 | /* |
2284 | * white/black-listing for position_fix | |
2285 | */ | |
623ec047 | 2286 | static struct snd_pci_quirk position_fix_list[] __devinitdata = { |
7a68be94 | 2287 | SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB), |
d2e1c973 TI |
2288 | SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), |
2289 | SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), | |
9919c761 | 2290 | SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB), |
2f703e7a | 2291 | SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), |
d2e1c973 | 2292 | SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), |
dd37f8e8 | 2293 | SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), |
9f75c1b1 | 2294 | SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), |
e96d3127 | 2295 | SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), |
4e0938db DC |
2296 | SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB), |
2297 | SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB), | |
61bb42c3 | 2298 | SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), |
9ec8ddad | 2299 | SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), |
45d4ebf1 | 2300 | SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), |
0321b695 | 2301 | SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB), |
8815cd03 | 2302 | SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), |
b90c0764 | 2303 | SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), |
0e0280dc | 2304 | SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), |
572c0e3c | 2305 | SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB), |
3372a153 TI |
2306 | {} |
2307 | }; | |
2308 | ||
2309 | static int __devinit check_position_fix(struct azx *chip, int fix) | |
2310 | { | |
2311 | const struct snd_pci_quirk *q; | |
2312 | ||
c673ba1c TI |
2313 | switch (fix) { |
2314 | case POS_FIX_LPIB: | |
2315 | case POS_FIX_POSBUF: | |
2316 | return fix; | |
2317 | } | |
2318 | ||
2319 | /* Check VIA/ATI HD Audio Controller exist */ | |
2320 | switch (chip->driver_type) { | |
2321 | case AZX_DRIVER_VIA: | |
2322 | case AZX_DRIVER_ATI: | |
0e153474 JC |
2323 | chip->via_dmapos_patch = 1; |
2324 | /* Use link position directly, avoid any transfer problem. */ | |
2325 | return POS_FIX_LPIB; | |
2326 | } | |
2327 | chip->via_dmapos_patch = 0; | |
2328 | ||
c673ba1c TI |
2329 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); |
2330 | if (q) { | |
2331 | printk(KERN_INFO | |
2332 | "hda_intel: position_fix set to %d " | |
2333 | "for device %04x:%04x\n", | |
2334 | q->value, q->subvendor, q->subdevice); | |
2335 | return q->value; | |
3372a153 | 2336 | } |
c673ba1c | 2337 | return POS_FIX_AUTO; |
3372a153 TI |
2338 | } |
2339 | ||
669ba27a TI |
2340 | /* |
2341 | * black-lists for probe_mask | |
2342 | */ | |
2343 | static struct snd_pci_quirk probe_mask_list[] __devinitdata = { | |
2344 | /* Thinkpad often breaks the controller communication when accessing | |
2345 | * to the non-working (or non-existing) modem codec slot. | |
2346 | */ | |
2347 | SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), | |
2348 | SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), | |
2349 | SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), | |
0edb9454 TI |
2350 | /* broken BIOS */ |
2351 | SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), | |
ef1681d8 TI |
2352 | /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ |
2353 | SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), | |
20db7cb0 | 2354 | /* forced codec slots */ |
93574844 | 2355 | SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), |
20db7cb0 | 2356 | SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), |
669ba27a TI |
2357 | {} |
2358 | }; | |
2359 | ||
f1eaaeec TI |
2360 | #define AZX_FORCE_CODEC_MASK 0x100 |
2361 | ||
5aba4f8e | 2362 | static void __devinit check_probe_mask(struct azx *chip, int dev) |
669ba27a TI |
2363 | { |
2364 | const struct snd_pci_quirk *q; | |
2365 | ||
f1eaaeec TI |
2366 | chip->codec_probe_mask = probe_mask[dev]; |
2367 | if (chip->codec_probe_mask == -1) { | |
669ba27a TI |
2368 | q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); |
2369 | if (q) { | |
2370 | printk(KERN_INFO | |
2371 | "hda_intel: probe_mask set to 0x%x " | |
2372 | "for device %04x:%04x\n", | |
2373 | q->value, q->subvendor, q->subdevice); | |
f1eaaeec | 2374 | chip->codec_probe_mask = q->value; |
669ba27a TI |
2375 | } |
2376 | } | |
f1eaaeec TI |
2377 | |
2378 | /* check forced option */ | |
2379 | if (chip->codec_probe_mask != -1 && | |
2380 | (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { | |
2381 | chip->codec_mask = chip->codec_probe_mask & 0xff; | |
2382 | printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", | |
2383 | chip->codec_mask); | |
2384 | } | |
669ba27a TI |
2385 | } |
2386 | ||
4d8e22e0 | 2387 | /* |
71623855 | 2388 | * white/black-list for enable_msi |
4d8e22e0 | 2389 | */ |
71623855 | 2390 | static struct snd_pci_quirk msi_black_list[] __devinitdata = { |
9dc8398b | 2391 | SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ |
0a27fcfa | 2392 | SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ |
ecd21626 | 2393 | SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ |
4193d13b | 2394 | SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ |
3815595e | 2395 | SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ |
4d8e22e0 TI |
2396 | {} |
2397 | }; | |
2398 | ||
2399 | static void __devinit check_msi(struct azx *chip) | |
2400 | { | |
2401 | const struct snd_pci_quirk *q; | |
2402 | ||
71623855 TI |
2403 | if (enable_msi >= 0) { |
2404 | chip->msi = !!enable_msi; | |
4d8e22e0 | 2405 | return; |
71623855 TI |
2406 | } |
2407 | chip->msi = 1; /* enable MSI as default */ | |
2408 | q = snd_pci_quirk_lookup(chip->pci, msi_black_list); | |
4d8e22e0 TI |
2409 | if (q) { |
2410 | printk(KERN_INFO | |
2411 | "hda_intel: msi for device %04x:%04x set to %d\n", | |
2412 | q->subvendor, q->subdevice, q->value); | |
2413 | chip->msi = q->value; | |
80c43ed7 TI |
2414 | return; |
2415 | } | |
2416 | ||
2417 | /* NVidia chipsets seem to cause troubles with MSI */ | |
2418 | if (chip->driver_type == AZX_DRIVER_NVIDIA) { | |
2419 | printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n"); | |
2420 | chip->msi = 0; | |
4d8e22e0 TI |
2421 | } |
2422 | } | |
2423 | ||
669ba27a | 2424 | |
1da177e4 LT |
2425 | /* |
2426 | * constructor | |
2427 | */ | |
a98f90fd | 2428 | static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, |
5aba4f8e | 2429 | int dev, int driver_type, |
a98f90fd | 2430 | struct azx **rchip) |
1da177e4 | 2431 | { |
a98f90fd | 2432 | struct azx *chip; |
4ce107b9 | 2433 | int i, err; |
bcd72003 | 2434 | unsigned short gcap; |
a98f90fd | 2435 | static struct snd_device_ops ops = { |
1da177e4 LT |
2436 | .dev_free = azx_dev_free, |
2437 | }; | |
2438 | ||
2439 | *rchip = NULL; | |
bcd72003 | 2440 | |
927fc866 PM |
2441 | err = pci_enable_device(pci); |
2442 | if (err < 0) | |
1da177e4 LT |
2443 | return err; |
2444 | ||
e560d8d8 | 2445 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
927fc866 | 2446 | if (!chip) { |
1da177e4 LT |
2447 | snd_printk(KERN_ERR SFX "cannot allocate chip\n"); |
2448 | pci_disable_device(pci); | |
2449 | return -ENOMEM; | |
2450 | } | |
2451 | ||
2452 | spin_lock_init(&chip->reg_lock); | |
62932df8 | 2453 | mutex_init(&chip->open_mutex); |
1da177e4 LT |
2454 | chip->card = card; |
2455 | chip->pci = pci; | |
2456 | chip->irq = -1; | |
07e4ca50 | 2457 | chip->driver_type = driver_type; |
4d8e22e0 | 2458 | check_msi(chip); |
555e219f | 2459 | chip->dev_index = dev; |
9ad593f6 | 2460 | INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); |
1da177e4 | 2461 | |
beaffc39 SG |
2462 | chip->position_fix[0] = chip->position_fix[1] = |
2463 | check_position_fix(chip, position_fix[dev]); | |
5aba4f8e | 2464 | check_probe_mask(chip, dev); |
3372a153 | 2465 | |
27346166 | 2466 | chip->single_cmd = single_cmd; |
c74db86b | 2467 | |
5c0d7bc1 TI |
2468 | if (bdl_pos_adj[dev] < 0) { |
2469 | switch (chip->driver_type) { | |
0c6341ac | 2470 | case AZX_DRIVER_ICH: |
32679f95 | 2471 | case AZX_DRIVER_PCH: |
0c6341ac | 2472 | bdl_pos_adj[dev] = 1; |
5c0d7bc1 TI |
2473 | break; |
2474 | default: | |
0c6341ac | 2475 | bdl_pos_adj[dev] = 32; |
5c0d7bc1 TI |
2476 | break; |
2477 | } | |
2478 | } | |
2479 | ||
07e4ca50 TI |
2480 | #if BITS_PER_LONG != 64 |
2481 | /* Fix up base address on ULI M5461 */ | |
2482 | if (chip->driver_type == AZX_DRIVER_ULI) { | |
2483 | u16 tmp3; | |
2484 | pci_read_config_word(pci, 0x40, &tmp3); | |
2485 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); | |
2486 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); | |
2487 | } | |
2488 | #endif | |
2489 | ||
927fc866 PM |
2490 | err = pci_request_regions(pci, "ICH HD audio"); |
2491 | if (err < 0) { | |
1da177e4 LT |
2492 | kfree(chip); |
2493 | pci_disable_device(pci); | |
2494 | return err; | |
2495 | } | |
2496 | ||
927fc866 | 2497 | chip->addr = pci_resource_start(pci, 0); |
2f5ad54e | 2498 | chip->remap_addr = pci_ioremap_bar(pci, 0); |
1da177e4 LT |
2499 | if (chip->remap_addr == NULL) { |
2500 | snd_printk(KERN_ERR SFX "ioremap error\n"); | |
2501 | err = -ENXIO; | |
2502 | goto errout; | |
2503 | } | |
2504 | ||
68e7fffc TI |
2505 | if (chip->msi) |
2506 | if (pci_enable_msi(pci) < 0) | |
2507 | chip->msi = 0; | |
7376d013 | 2508 | |
68e7fffc | 2509 | if (azx_acquire_irq(chip, 0) < 0) { |
1da177e4 LT |
2510 | err = -EBUSY; |
2511 | goto errout; | |
2512 | } | |
1da177e4 LT |
2513 | |
2514 | pci_set_master(pci); | |
2515 | synchronize_irq(chip->irq); | |
2516 | ||
bcd72003 | 2517 | gcap = azx_readw(chip, GCAP); |
4abc1cc2 | 2518 | snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap); |
bcd72003 | 2519 | |
dc4c2e6b AB |
2520 | /* disable SB600 64bit support for safety */ |
2521 | if ((chip->driver_type == AZX_DRIVER_ATI) || | |
2522 | (chip->driver_type == AZX_DRIVER_ATIHDMI)) { | |
2523 | struct pci_dev *p_smbus; | |
2524 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, | |
2525 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
2526 | NULL); | |
2527 | if (p_smbus) { | |
2528 | if (p_smbus->revision < 0x30) | |
2529 | gcap &= ~ICH6_GCAP_64OK; | |
2530 | pci_dev_put(p_smbus); | |
2531 | } | |
2532 | } | |
09240cf4 | 2533 | |
396087ea JK |
2534 | /* disable 64bit DMA address for Teradici */ |
2535 | /* it does not work with device 6549:1200 subsys e4a2:040b */ | |
2536 | if (chip->driver_type == AZX_DRIVER_TERA) | |
2537 | gcap &= ~ICH6_GCAP_64OK; | |
2538 | ||
cf7aaca8 | 2539 | /* allow 64bit DMA address if supported by H/W */ |
b21fadb9 | 2540 | if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) |
e930438c | 2541 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); |
09240cf4 | 2542 | else { |
e930438c YH |
2543 | pci_set_dma_mask(pci, DMA_BIT_MASK(32)); |
2544 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); | |
09240cf4 | 2545 | } |
cf7aaca8 | 2546 | |
8b6ed8e7 TI |
2547 | /* read number of streams from GCAP register instead of using |
2548 | * hardcoded value | |
2549 | */ | |
2550 | chip->capture_streams = (gcap >> 8) & 0x0f; | |
2551 | chip->playback_streams = (gcap >> 12) & 0x0f; | |
2552 | if (!chip->playback_streams && !chip->capture_streams) { | |
bcd72003 TD |
2553 | /* gcap didn't give any info, switching to old method */ |
2554 | ||
2555 | switch (chip->driver_type) { | |
2556 | case AZX_DRIVER_ULI: | |
2557 | chip->playback_streams = ULI_NUM_PLAYBACK; | |
2558 | chip->capture_streams = ULI_NUM_CAPTURE; | |
bcd72003 TD |
2559 | break; |
2560 | case AZX_DRIVER_ATIHDMI: | |
2561 | chip->playback_streams = ATIHDMI_NUM_PLAYBACK; | |
2562 | chip->capture_streams = ATIHDMI_NUM_CAPTURE; | |
bcd72003 | 2563 | break; |
c4da29ca | 2564 | case AZX_DRIVER_GENERIC: |
bcd72003 TD |
2565 | default: |
2566 | chip->playback_streams = ICH6_NUM_PLAYBACK; | |
2567 | chip->capture_streams = ICH6_NUM_CAPTURE; | |
bcd72003 TD |
2568 | break; |
2569 | } | |
07e4ca50 | 2570 | } |
8b6ed8e7 TI |
2571 | chip->capture_index_offset = 0; |
2572 | chip->playback_index_offset = chip->capture_streams; | |
07e4ca50 | 2573 | chip->num_streams = chip->playback_streams + chip->capture_streams; |
d01ce99f TI |
2574 | chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), |
2575 | GFP_KERNEL); | |
927fc866 | 2576 | if (!chip->azx_dev) { |
4abc1cc2 | 2577 | snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n"); |
07e4ca50 TI |
2578 | goto errout; |
2579 | } | |
2580 | ||
4ce107b9 TI |
2581 | for (i = 0; i < chip->num_streams; i++) { |
2582 | /* allocate memory for the BDL for each stream */ | |
2583 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, | |
2584 | snd_dma_pci_data(chip->pci), | |
2585 | BDL_SIZE, &chip->azx_dev[i].bdl); | |
2586 | if (err < 0) { | |
2587 | snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); | |
2588 | goto errout; | |
2589 | } | |
1da177e4 | 2590 | } |
0be3b5d3 | 2591 | /* allocate memory for the position buffer */ |
d01ce99f TI |
2592 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, |
2593 | snd_dma_pci_data(chip->pci), | |
2594 | chip->num_streams * 8, &chip->posbuf); | |
2595 | if (err < 0) { | |
0be3b5d3 TI |
2596 | snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); |
2597 | goto errout; | |
1da177e4 | 2598 | } |
1da177e4 | 2599 | /* allocate CORB/RIRB */ |
81740861 TI |
2600 | err = azx_alloc_cmd_io(chip); |
2601 | if (err < 0) | |
2602 | goto errout; | |
1da177e4 LT |
2603 | |
2604 | /* initialize streams */ | |
2605 | azx_init_stream(chip); | |
2606 | ||
2607 | /* initialize chip */ | |
cb53c626 | 2608 | azx_init_pci(chip); |
10e77dda | 2609 | azx_init_chip(chip, (probe_only[dev] & 2) == 0); |
1da177e4 LT |
2610 | |
2611 | /* codec detection */ | |
927fc866 | 2612 | if (!chip->codec_mask) { |
1da177e4 LT |
2613 | snd_printk(KERN_ERR SFX "no codecs found!\n"); |
2614 | err = -ENODEV; | |
2615 | goto errout; | |
2616 | } | |
2617 | ||
d01ce99f TI |
2618 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); |
2619 | if (err <0) { | |
1da177e4 LT |
2620 | snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); |
2621 | goto errout; | |
2622 | } | |
2623 | ||
07e4ca50 | 2624 | strcpy(card->driver, "HDA-Intel"); |
18cb7109 TI |
2625 | strlcpy(card->shortname, driver_short_names[chip->driver_type], |
2626 | sizeof(card->shortname)); | |
2627 | snprintf(card->longname, sizeof(card->longname), | |
2628 | "%s at 0x%lx irq %i", | |
2629 | card->shortname, chip->addr, chip->irq); | |
07e4ca50 | 2630 | |
1da177e4 LT |
2631 | *rchip = chip; |
2632 | return 0; | |
2633 | ||
2634 | errout: | |
2635 | azx_free(chip); | |
2636 | return err; | |
2637 | } | |
2638 | ||
cb53c626 TI |
2639 | static void power_down_all_codecs(struct azx *chip) |
2640 | { | |
2641 | #ifdef CONFIG_SND_HDA_POWER_SAVE | |
2642 | /* The codecs were powered up in snd_hda_codec_new(). | |
2643 | * Now all initialization done, so turn them down if possible | |
2644 | */ | |
2645 | struct hda_codec *codec; | |
2646 | list_for_each_entry(codec, &chip->bus->codec_list, list) { | |
2647 | snd_hda_power_down(codec); | |
2648 | } | |
2649 | #endif | |
2650 | } | |
2651 | ||
d01ce99f TI |
2652 | static int __devinit azx_probe(struct pci_dev *pci, |
2653 | const struct pci_device_id *pci_id) | |
1da177e4 | 2654 | { |
5aba4f8e | 2655 | static int dev; |
a98f90fd TI |
2656 | struct snd_card *card; |
2657 | struct azx *chip; | |
927fc866 | 2658 | int err; |
1da177e4 | 2659 | |
5aba4f8e TI |
2660 | if (dev >= SNDRV_CARDS) |
2661 | return -ENODEV; | |
2662 | if (!enable[dev]) { | |
2663 | dev++; | |
2664 | return -ENOENT; | |
2665 | } | |
2666 | ||
e58de7ba TI |
2667 | err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); |
2668 | if (err < 0) { | |
1da177e4 | 2669 | snd_printk(KERN_ERR SFX "Error creating card!\n"); |
e58de7ba | 2670 | return err; |
1da177e4 LT |
2671 | } |
2672 | ||
4ea6fbc8 TI |
2673 | /* set this here since it's referred in snd_hda_load_patch() */ |
2674 | snd_card_set_dev(card, &pci->dev); | |
2675 | ||
5aba4f8e | 2676 | err = azx_create(card, pci, dev, pci_id->driver_data, &chip); |
41dda0fd WF |
2677 | if (err < 0) |
2678 | goto out_free; | |
421a1252 | 2679 | card->private_data = chip; |
1da177e4 | 2680 | |
2dca0bba JK |
2681 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
2682 | chip->beep_mode = beep_mode[dev]; | |
2683 | #endif | |
2684 | ||
1da177e4 | 2685 | /* create codec instances */ |
a1e21c90 | 2686 | err = azx_codec_create(chip, model[dev]); |
41dda0fd WF |
2687 | if (err < 0) |
2688 | goto out_free; | |
4ea6fbc8 TI |
2689 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
2690 | if (patch[dev]) { | |
2691 | snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n", | |
2692 | patch[dev]); | |
2693 | err = snd_hda_load_patch(chip->bus, patch[dev]); | |
2694 | if (err < 0) | |
2695 | goto out_free; | |
2696 | } | |
2697 | #endif | |
10e77dda | 2698 | if ((probe_only[dev] & 1) == 0) { |
a1e21c90 TI |
2699 | err = azx_codec_configure(chip); |
2700 | if (err < 0) | |
2701 | goto out_free; | |
2702 | } | |
1da177e4 LT |
2703 | |
2704 | /* create PCM streams */ | |
176d5335 | 2705 | err = snd_hda_build_pcms(chip->bus); |
41dda0fd WF |
2706 | if (err < 0) |
2707 | goto out_free; | |
1da177e4 LT |
2708 | |
2709 | /* create mixer controls */ | |
d01ce99f | 2710 | err = azx_mixer_create(chip); |
41dda0fd WF |
2711 | if (err < 0) |
2712 | goto out_free; | |
1da177e4 | 2713 | |
d01ce99f | 2714 | err = snd_card_register(card); |
41dda0fd WF |
2715 | if (err < 0) |
2716 | goto out_free; | |
1da177e4 LT |
2717 | |
2718 | pci_set_drvdata(pci, card); | |
cb53c626 TI |
2719 | chip->running = 1; |
2720 | power_down_all_codecs(chip); | |
0cbf0098 | 2721 | azx_notifier_register(chip); |
1da177e4 | 2722 | |
e25bcdba | 2723 | dev++; |
1da177e4 | 2724 | return err; |
41dda0fd WF |
2725 | out_free: |
2726 | snd_card_free(card); | |
2727 | return err; | |
1da177e4 LT |
2728 | } |
2729 | ||
2730 | static void __devexit azx_remove(struct pci_dev *pci) | |
2731 | { | |
2732 | snd_card_free(pci_get_drvdata(pci)); | |
2733 | pci_set_drvdata(pci, NULL); | |
2734 | } | |
2735 | ||
2736 | /* PCI IDs */ | |
cebe41d4 | 2737 | static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { |
d2f2fcd2 | 2738 | /* CPT */ |
32679f95 | 2739 | { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH }, |
cea310e8 SH |
2740 | /* PBG */ |
2741 | { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH }, | |
87218e9c TI |
2742 | /* SCH */ |
2743 | { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH }, | |
b6864535 TI |
2744 | /* Generic Intel */ |
2745 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), | |
2746 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2747 | .class_mask = 0xffffff, | |
2748 | .driver_data = AZX_DRIVER_ICH }, | |
87218e9c TI |
2749 | /* ATI SB 450/600 */ |
2750 | { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI }, | |
2751 | { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI }, | |
2752 | /* ATI HDMI */ | |
2753 | { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2754 | { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2755 | { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI }, | |
9e6dd47b | 2756 | { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI }, |
87218e9c TI |
2757 | { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI }, |
2758 | { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2759 | { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2760 | { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2761 | { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2762 | { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2763 | { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2764 | { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2765 | { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2766 | { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2767 | /* VIA VT8251/VT8237A */ | |
2768 | { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, | |
2769 | /* SIS966 */ | |
2770 | { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, | |
2771 | /* ULI M5461 */ | |
2772 | { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, | |
2773 | /* NVIDIA MCP */ | |
0c2fd1bf TI |
2774 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), |
2775 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2776 | .class_mask = 0xffffff, | |
2777 | .driver_data = AZX_DRIVER_NVIDIA }, | |
f269002e KY |
2778 | /* Teradici */ |
2779 | { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA }, | |
4e01f54b | 2780 | /* Creative X-Fi (CA0110-IBG) */ |
313f6e2d TI |
2781 | #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE) |
2782 | /* the following entry conflicts with snd-ctxfi driver, | |
2783 | * as ctxfi driver mutates from HD-audio to native mode with | |
2784 | * a special command sequence. | |
2785 | */ | |
4e01f54b TI |
2786 | { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), |
2787 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2788 | .class_mask = 0xffffff, | |
2789 | .driver_data = AZX_DRIVER_GENERIC }, | |
313f6e2d TI |
2790 | #else |
2791 | /* this entry seems still valid -- i.e. without emu20kx chip */ | |
2792 | { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC }, | |
2793 | #endif | |
e35d4b11 OS |
2794 | /* Vortex86MX */ |
2795 | { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, | |
9176b672 | 2796 | /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ |
c4da29ca YL |
2797 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), |
2798 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2799 | .class_mask = 0xffffff, | |
2800 | .driver_data = AZX_DRIVER_GENERIC }, | |
9176b672 AB |
2801 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), |
2802 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2803 | .class_mask = 0xffffff, | |
2804 | .driver_data = AZX_DRIVER_GENERIC }, | |
1da177e4 LT |
2805 | { 0, } |
2806 | }; | |
2807 | MODULE_DEVICE_TABLE(pci, azx_ids); | |
2808 | ||
2809 | /* pci_driver definition */ | |
2810 | static struct pci_driver driver = { | |
2811 | .name = "HDA Intel", | |
2812 | .id_table = azx_ids, | |
2813 | .probe = azx_probe, | |
2814 | .remove = __devexit_p(azx_remove), | |
421a1252 TI |
2815 | #ifdef CONFIG_PM |
2816 | .suspend = azx_suspend, | |
2817 | .resume = azx_resume, | |
2818 | #endif | |
1da177e4 LT |
2819 | }; |
2820 | ||
2821 | static int __init alsa_card_azx_init(void) | |
2822 | { | |
01d25d46 | 2823 | return pci_register_driver(&driver); |
1da177e4 LT |
2824 | } |
2825 | ||
2826 | static void __exit alsa_card_azx_exit(void) | |
2827 | { | |
2828 | pci_unregister_driver(&driver); | |
2829 | } | |
2830 | ||
2831 | module_init(alsa_card_azx_init) | |
2832 | module_exit(alsa_card_azx_exit) |