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ALSA: hda - Raise AZX_DCAPS_RIRB_DELAY handling into top drivers
[linux-2.6-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
98d8fc6c
ML		 60#include <sound/hdaudio.h>
61#include <sound/hda_i915.h>
9121947d 62#include <linux/vgaarb.h>
a82d51ed 63#include <linux/vga_switcheroo.h>
4918cdab 64#include <linux/firmware.h>
1da177e4 65#include "hda_codec.h"
05e84878 66#include "hda_controller.h"
347de1f8 67#include "hda_intel.h"
1da177e4 68
785d8c4b
LY		 69#define CREATE_TRACE_POINTS
70#include "hda_intel_trace.h"
71
b6050ef6
TI		 72/* position fix mode */
73enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79};
80
9a34af4a
TI		 81/* Defines for ATI HD Audio support in SB450 south bridge */
82#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85/* Defines for Nvidia HDA support */
86#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88#define NVIDIA_HDA_ISTRM_COH 0x4d
89#define NVIDIA_HDA_OSTRM_COH 0x4c
90#define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92/* Defines for Intel SCH HDA snoop control */
93#define INTEL_SCH_HDA_DEVC 0x78
94#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
95
96/* Define IN stream 0 FIFO size offset in VIA controller */
97#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
98/* Define VIA HD Audio Device ID*/
99#define VIA_HDAC_DEVICE_ID 0x3288
100
33124929
TI		 101/* max number of SDs */
102/* ICH, ATI and VIA have 4 playback and 4 capture */
103#define ICH6_NUM_CAPTURE 4
104#define ICH6_NUM_PLAYBACK 4
105
106/* ULI has 6 playback and 5 capture */
107#define ULI_NUM_CAPTURE 5
108#define ULI_NUM_PLAYBACK 6
109
110/* ATI HDMI may have up to 8 playbacks and 0 capture */
111#define ATIHDMI_NUM_CAPTURE 0
112#define ATIHDMI_NUM_PLAYBACK 8
113
114/* TERA has 4 playback and 3 capture */
115#define TERA_NUM_CAPTURE 3
116#define TERA_NUM_PLAYBACK 4
117
1da177e4 118
5aba4f8e
TI		 119static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 121static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 122static char *model[SNDRV_CARDS];
1dac6695 123static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 124static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 125static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 126static int probe_only[SNDRV_CARDS];
26a6cb6c 127static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 128static bool single_cmd;
71623855 129static int enable_msi = -1;
4ea6fbc8
TI		 130#ifdef CONFIG_SND_HDA_PATCH_LOADER
131static char *patch[SNDRV_CARDS];
132#endif
2dca0bba 133#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 134static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 135 CONFIG_SND_HDA_INPUT_BEEP_MODE};
136#endif
1da177e4 137
5aba4f8e 138module_param_array(index, int, NULL, 0444);
1da177e4 139MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 140module_param_array(id, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 142module_param_array(enable, bool, NULL, 0444);
143MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144module_param_array(model, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 146module_param_array(position_fix, int, NULL, 0444);
4cb36310 147MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 149module_param_array(bdl_pos_adj, int, NULL, 0644);
150MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 151module_param_array(probe_mask, int, NULL, 0444);
606ad75f 152MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 153module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 154MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 155module_param_array(jackpoll_ms, int, NULL, 0444);
156MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 157module_param(single_cmd, bool, 0444);
d01ce99f
TI		 158MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159 "(for debugging only).");
ac9ef6cf 160module_param(enable_msi, bint, 0444);
134a11f0 161MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 162#ifdef CONFIG_SND_HDA_PATCH_LOADER
163module_param_array(patch, charp, NULL, 0444);
164MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165#endif
2dca0bba 166#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 167module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 168MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 169 "(0=off, 1=on) (default=1).");
2dca0bba 170#endif
606ad75f 171
83012a7c 172#ifdef CONFIG_PM
65fcd41d 173static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 174static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 175 .set = param_set_xint,
176 .get = param_get_int,
177};
178#define param_check_xint param_check_int
179
fee2fba3 180static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 181module_param(power_save, xint, 0644);
fee2fba3
TI		 182MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183 "(in second, 0 = disable).");
1da177e4 184
dee1b66c
TI		 185/* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
8fc24426
TI		 189static bool power_save_controller = 1;
190module_param(power_save_controller, bool, 0644);
dee1b66c 191MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 192#else
bb573928 193#define power_save 0
83012a7c 194#endif /* CONFIG_PM */
dee1b66c 195
7bfe059e
TI		 196static int align_buffer_size = -1;
197module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 198MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
27fe48d9 201#ifdef CONFIG_X86
7c732015
TI		 202static int hda_snoop = -1;
203module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 204MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 205#else
206#define hda_snoop true
27fe48d9
TI		 207#endif
208
209
1da177e4
LT		 210MODULE_LICENSE("GPL");
211MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
2f1b3818 213 "{Intel, ICH7},"
f5d40b30 214 "{Intel, ESB2},"
d2981393 215 "{Intel, ICH8},"
f9cc8a8b 216 "{Intel, ICH9},"
c34f5a04 217 "{Intel, ICH10},"
b29c2360 218 "{Intel, PCH},"
d2f2fcd2 219 "{Intel, CPT},"
d2edeb7c 220 "{Intel, PPT},"
8bc039a1 221 "{Intel, LPT},"
144dad99 222 "{Intel, LPT_LP},"
4eeca499 223 "{Intel, WPT_LP},"
c8b00fd2 224 "{Intel, SPT},"
b4565913 225 "{Intel, SPT_LP},"
e926f2c8 226 "{Intel, HPT},"
cea310e8 227 "{Intel, PBG},"
4979bca9 228 "{Intel, SCH},"
fc20a562 229 "{ATI, SB450},"
89be83f8 230 "{ATI, SB600},"
778b6e1b 231 "{ATI, RS600},"
5b15c95f 232 "{ATI, RS690},"
e6db1119
WL		 233 "{ATI, RS780},"
234 "{ATI, R600},"
2797f724
HRK		 235 "{ATI, RV630},"
236 "{ATI, RV610},"
27da1834
WL		 237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
fc20a562 241 "{VIA, VT8251},"
47672310 242 "{VIA, VT8237A},"
07e4ca50
TI		 243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
1da177e4
LT		 245MODULE_DESCRIPTION("Intel HDA driver");
246
a82d51ed 247#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 248#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 249#define SUPPORT_VGA_SWITCHEROO
250#endif
251#endif
252
253
1da177e4 254/*
1da177e4 255 */
1da177e4 256
07e4ca50
TI		 257/* driver types */
258enum {
259 AZX_DRIVER_ICH,
32679f95 260 AZX_DRIVER_PCH,
4979bca9 261 AZX_DRIVER_SCH,
fab1285a 262 AZX_DRIVER_HDMI,
07e4ca50 263 AZX_DRIVER_ATI,
778b6e1b 264 AZX_DRIVER_ATIHDMI,
1815b34a 265 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 266 AZX_DRIVER_VIA,
267 AZX_DRIVER_SIS,
268 AZX_DRIVER_ULI,
da3fca21 269 AZX_DRIVER_NVIDIA,
f269002e 270 AZX_DRIVER_TERA,
14d34f16 271 AZX_DRIVER_CTX,
5ae763b1 272 AZX_DRIVER_CTHDA,
c563f473 273 AZX_DRIVER_CMEDIA,
c4da29ca 274 AZX_DRIVER_GENERIC,
2f5983f2 275 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 276};
277
37e661ee
TI		 278#define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
b42b4afb
TI		 282/* quirks for old Intel chipsets */
283#define AZX_DCAPS_INTEL_ICH \
103884a3 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 285
2ea3c6a2 286/* quirks for Intel PCH */
6603249d 287#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee 289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 290
55913110 291/* PCH up to IVB; no runtime PM */
6603249d 292#define AZX_DCAPS_INTEL_PCH_NOPM \
55913110 293 (AZX_DCAPS_INTEL_PCH_BASE)
6603249d 294
55913110 295/* PCH for HSW/BDW; with runtime PM */
d7dab4db 296#define AZX_DCAPS_INTEL_PCH \
6603249d 297 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 298
6603249d 299/* HSW HDMI */
33499a15 300#define AZX_DCAPS_INTEL_HASWELL \
103884a3 301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 304
54a0405d
LY		 305/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
306#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 307 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 308 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
309 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 310
40cc2392
ML		 311#define AZX_DCAPS_INTEL_BAYTRAIL \
312 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
313
2d846c74
LY		 314#define AZX_DCAPS_INTEL_BRASWELL \
315 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
316
d6795827 317#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 318 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
319 AZX_DCAPS_I915_POWERWELL)
d6795827 320
c87693da
LH		 321#define AZX_DCAPS_INTEL_BROXTON \
322 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
323 AZX_DCAPS_I915_POWERWELL)
324
9477c58e
TI		 325/* quirks for ATI SB / AMD Hudson */
326#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 327 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
328 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 329
330/* quirks for ATI/AMD HDMI */
331#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 332 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
333 AZX_DCAPS_NO_MSI64)
9477c58e 334
37e661ee
TI		 335/* quirks for ATI HDMI with snoop off */
336#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
337 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
338
9477c58e
TI		 339/* quirks for Nvidia */
340#define AZX_DCAPS_PRESET_NVIDIA \
7d9a1808 341 (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 342 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
343 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 344
5ae763b1 345#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 346 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 347 AZX_DCAPS_NO_64BIT |\
37e661ee 348 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 349
a82d51ed 350/*
2b760d88 351 * vga_switcheroo support
a82d51ed
TI		 352 */
353#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 354#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
355#else
356#define use_vga_switcheroo(chip) 0
357#endif
358
03b135ce
LY		 359#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
360 ((pci)->device == 0x0c0c) || \
361 ((pci)->device == 0x0d0c) || \
362 ((pci)->device == 0x160c))
363
48c8b0eb 364static char *driver_short_names[] = {
07e4ca50 365 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 366 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 367 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 368 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 369 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 370 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 371 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 372 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
373 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 374 [AZX_DRIVER_ULI] = "HDA ULI M5461",
375 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 376 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 377 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 378 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 379 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 380 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 381};
382
27fe48d9 383#ifdef CONFIG_X86
9ddf1aeb 384static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 385{
9ddf1aeb
TI		 386 int pages;
387
27fe48d9
TI		 388 if (azx_snoop(chip))
389 return;
9ddf1aeb
TI		 390 if (!dmab || !dmab->area || !dmab->bytes)
391 return;
392
393#ifdef CONFIG_SND_DMA_SGBUF
394 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
395 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 396 if (chip->driver_type == AZX_DRIVER_CMEDIA)
397 return; /* deal with only CORB/RIRB buffers */
27fe48d9 398 if (on)
9ddf1aeb 399 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 400 else
9ddf1aeb
TI		 401 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
402 return;
27fe48d9 403 }
9ddf1aeb
TI		 404#endif
405
406 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
407 if (on)
408 set_memory_wc((unsigned long)dmab->area, pages);
409 else
410 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 411}
412
413static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
414 bool on)
415{
9ddf1aeb 416 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 417}
418static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 419 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 420{
421 if (azx_dev->wc_marked != on) {
9ddf1aeb 422 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 423 azx_dev->wc_marked = on;
424 }
425}
426#else
427/* NOP for other archs */
428static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
429 bool on)
430{
431}
432static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 433 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 434{
435}
436#endif
437
68e7fffc 438static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 439
cb53c626
TI		 440/*
441 * initialize the PCI registers
442 */
443/* update bits in a PCI register byte */
444static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
445 unsigned char mask, unsigned char val)
446{
447 unsigned char data;
448
449 pci_read_config_byte(pci, reg, &data);
450 data &= ~mask;
451 data |= (val & mask);
452 pci_write_config_byte(pci, reg, data);
453}
454
455static void azx_init_pci(struct azx *chip)
456{
37e661ee
TI		 457 int snoop_type = azx_get_snoop_type(chip);
458
cb53c626
TI		 459 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
460 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
461 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 462 * codecs.
463 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 464 */
46f2cc80 465 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 466 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 467 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 468 }
cb53c626 469
9477c58e
TI		 470 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
471 * we need to enable snoop.
472 */
37e661ee 473 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 474 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
475 azx_snoop(chip));
cb53c626 476 update_pci_byte(chip->pci,
27fe48d9
TI		 477 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
478 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 479 }
480
481 /* For NVIDIA HDA, enable snoop */
37e661ee 482 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 483 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
484 azx_snoop(chip));
cb53c626
TI		 485 update_pci_byte(chip->pci,
486 NVIDIA_HDA_TRANSREG_ADDR,
487 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 488 update_pci_byte(chip->pci,
489 NVIDIA_HDA_ISTRM_COH,
490 0x01, NVIDIA_HDA_ENABLE_COHBIT);
491 update_pci_byte(chip->pci,
492 NVIDIA_HDA_OSTRM_COH,
493 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 494 }
495
496 /* Enable SCH/PCH snoop if needed */
37e661ee 497 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 498 unsigned short snoop;
90a5ad52 499 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 500 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
501 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
502 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
503 if (!azx_snoop(chip))
504 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
505 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 506 pci_read_config_word(chip->pci,
507 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 508 }
4e76a883
TI		 509 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
510 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
511 "Disabled" : "Enabled");
da3fca21 512 }
1da177e4
LT		 513}
514
0a673521
LH		 515static void hda_intel_init_chip(struct azx *chip, bool full_reset)
516{
98d8fc6c 517 struct hdac_bus *bus = azx_bus(chip);
0a673521
LH		 518
519 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 520 snd_hdac_set_codec_wakeup(bus, true);
0a673521
LH		 521 azx_init_chip(chip, full_reset);
522 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 523 snd_hdac_set_codec_wakeup(bus, false);
0a673521
LH		 524}
525
b6050ef6
TI		 526/* calculate runtime delay from LPIB */
527static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
528 unsigned int pos)
529{
7833c3f8 530 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 531 int stream = substream->stream;
532 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
533 int delay;
534
535 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
536 delay = pos - lpib_pos;
537 else
538 delay = lpib_pos - pos;
539 if (delay < 0) {
7833c3f8 540 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 541 delay = 0;
542 else
7833c3f8 543 delay += azx_dev->core.bufsize;
b6050ef6
TI		 544 }
545
7833c3f8 546 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 547 dev_info(chip->card->dev,
548 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 549 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 550 delay = 0;
551 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
552 chip->get_delay[stream] = NULL;
553 }
554
555 return bytes_to_frames(substream->runtime, delay);
556}
557
9ad593f6
TI		 558static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
559
7ca954a8
DR		 560/* called from IRQ */
561static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
562{
9a34af4a 563 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 564 int ok;
565
566 ok = azx_position_ok(chip, azx_dev);
567 if (ok == 1) {
568 azx_dev->irq_pending = 0;
569 return ok;
2f35c630 570 } else if (ok == 0) {
7ca954a8
DR		 571 /* bogus IRQ, process it later */
572 azx_dev->irq_pending = 1;
2f35c630 573 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 574 }
575 return 0;
576}
577
17eccb27
ML		 578/* Enable/disable i915 display power for the link */
579static int azx_intel_link_power(struct azx *chip, bool enable)
580{
98d8fc6c 581 struct hdac_bus *bus = azx_bus(chip);
17eccb27 582
98d8fc6c 583 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 584}
585
9ad593f6
TI		 586/*
587 * Check whether the current DMA position is acceptable for updating
588 * periods. Returns non-zero if it's OK.
589 *
590 * Many HD-audio controllers appear pretty inaccurate about
591 * the update-IRQ timing. The IRQ is issued before actually the
592 * data is processed. So, we need to process it afterwords in a
593 * workqueue.
594 */
595static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
596{
7833c3f8 597 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 598 int stream = substream->stream;
e5463720 599 u32 wallclk;
9ad593f6
TI		 600 unsigned int pos;
601
7833c3f8
TI		 602 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
603 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 604 return -1; /* bogus (too early) interrupt */
fa00e046 605
b6050ef6
TI		 606 if (chip->get_position[stream])
607 pos = chip->get_position[stream](chip, azx_dev);
608 else { /* use the position buffer as default */
609 pos = azx_get_pos_posbuf(chip, azx_dev);
610 if (!pos || pos == (u32)-1) {
611 dev_info(chip->card->dev,
612 "Invalid position buffer, using LPIB read method instead.\n");
613 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 614 if (chip->get_position[0] == azx_get_pos_lpib &&
615 chip->get_position[1] == azx_get_pos_lpib)
616 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 617 pos = azx_get_pos_lpib(chip, azx_dev);
618 chip->get_delay[stream] = NULL;
619 } else {
620 chip->get_position[stream] = azx_get_pos_posbuf;
621 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
622 chip->get_delay[stream] = azx_get_delay_from_lpib;
623 }
624 }
625
7833c3f8 626 if (pos >= azx_dev->core.bufsize)
b6050ef6 627 pos = 0;
9ad593f6 628
7833c3f8 629 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 630 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 631 return -1; /* this shouldn't happen! */
7833c3f8
TI		 632 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
633 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 634 /* NG - it's below the first next period boundary */
4f0189be 635 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 636 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 637 return 1; /* OK, it's fine */
638}
639
640/*
641 * The work for pending PCM period updates.
642 */
643static void azx_irq_pending_work(struct work_struct *work)
644{
9a34af4a
TI		 645 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
646 struct azx *chip = &hda->chip;
7833c3f8
TI		 647 struct hdac_bus *bus = azx_bus(chip);
648 struct hdac_stream *s;
649 int pending, ok;
9ad593f6 650
9a34af4a 651 if (!hda->irq_pending_warned) {
4e76a883
TI		 652 dev_info(chip->card->dev,
653 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
654 chip->card->number);
9a34af4a 655 hda->irq_pending_warned = 1;
a6a950a8
TI		 656 }
657
9ad593f6
TI		 658 for (;;) {
659 pending = 0;
a41d1224 660 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 661 list_for_each_entry(s, &bus->stream_list, list) {
662 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 663 if (!azx_dev->irq_pending ||
7833c3f8
TI		 664 !s->substream ||
665 !s->running)
9ad593f6 666 continue;
e5463720
JK		 667 ok = azx_position_ok(chip, azx_dev);
668 if (ok > 0) {
9ad593f6 669 azx_dev->irq_pending = 0;
a41d1224 670 spin_unlock(&bus->reg_lock);
7833c3f8 671 snd_pcm_period_elapsed(s->substream);
a41d1224 672 spin_lock(&bus->reg_lock);
e5463720
JK		 673 } else if (ok < 0) {
674 pending = 0; /* too early */
9ad593f6
TI		 675 } else
676 pending++;
677 }
a41d1224 678 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 679 if (!pending)
680 return;
08af495f 681 msleep(1);
9ad593f6
TI		 682 }
683}
684
685/* clear irq_pending flags and assure no on-going workq */
686static void azx_clear_irq_pending(struct azx *chip)
687{
7833c3f8
TI		 688 struct hdac_bus *bus = azx_bus(chip);
689 struct hdac_stream *s;
9ad593f6 690
a41d1224 691 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 692 list_for_each_entry(s, &bus->stream_list, list) {
693 struct azx_dev *azx_dev = stream_to_azx_dev(s);
694 azx_dev->irq_pending = 0;
695 }
a41d1224 696 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 697}
698
68e7fffc
TI		 699static int azx_acquire_irq(struct azx *chip, int do_disconnect)
700{
a41d1224
TI		 701 struct hdac_bus *bus = azx_bus(chip);
702
437a5a46
TI		 703 if (request_irq(chip->pci->irq, azx_interrupt,
704 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 705 KBUILD_MODNAME, chip)) {
4e76a883
TI		 706 dev_err(chip->card->dev,
707 "unable to grab IRQ %d, disabling device\n",
708 chip->pci->irq);
68e7fffc
TI		 709 if (do_disconnect)
710 snd_card_disconnect(chip->card);
711 return -1;
712 }
a41d1224 713 bus->irq = chip->pci->irq;
69e13418 714 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 715 return 0;
716}
717
b6050ef6
TI		 718/* get the current DMA position with correction on VIA chips */
719static unsigned int azx_via_get_position(struct azx *chip,
720 struct azx_dev *azx_dev)
721{
722 unsigned int link_pos, mini_pos, bound_pos;
723 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
724 unsigned int fifo_size;
725
1604eeee 726 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 727 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 728 /* Playback, no problem using link position */
729 return link_pos;
730 }
731
732 /* Capture */
733 /* For new chipset,
734 * use mod to get the DMA position just like old chipset
735 */
7833c3f8
TI		 736 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
737 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 738
739 /* azx_dev->fifo_size can't get FIFO size of in stream.
740 * Get from base address + offset.
741 */
a41d1224
TI		 742 fifo_size = readw(azx_bus(chip)->remap_addr +
743 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 744
745 if (azx_dev->insufficient) {
746 /* Link position never gather than FIFO size */
747 if (link_pos <= fifo_size)
748 return 0;
749
750 azx_dev->insufficient = 0;
751 }
752
753 if (link_pos <= fifo_size)
7833c3f8 754 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 755 else
756 mini_pos = link_pos - fifo_size;
757
758 /* Find nearest previous boudary */
7833c3f8
TI		 759 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
760 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 761 if (mod_link_pos >= fifo_size)
762 bound_pos = link_pos - mod_link_pos;
763 else if (mod_dma_pos >= mod_mini_pos)
764 bound_pos = mini_pos - mod_mini_pos;
765 else {
7833c3f8
TI		 766 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
767 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 768 bound_pos = 0;
769 }
770
771 /* Calculate real DMA position we want */
772 return bound_pos + mod_dma_pos;
773}
774
83012a7c 775#ifdef CONFIG_PM
65fcd41d
TI		 776static DEFINE_MUTEX(card_list_lock);
777static LIST_HEAD(card_list);
778
779static void azx_add_card_list(struct azx *chip)
780{
9a34af4a 781 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 782 mutex_lock(&card_list_lock);
9a34af4a 783 list_add(&hda->list, &card_list);
65fcd41d
TI		 784 mutex_unlock(&card_list_lock);
785}
786
787static void azx_del_card_list(struct azx *chip)
788{
9a34af4a 789 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 790 mutex_lock(&card_list_lock);
9a34af4a 791 list_del_init(&hda->list);
65fcd41d
TI		 792 mutex_unlock(&card_list_lock);
793}
794
795/* trigger power-save check at writing parameter */
796static int param_set_xint(const char *val, const struct kernel_param *kp)
797{
9a34af4a 798 struct hda_intel *hda;
65fcd41d 799 struct azx *chip;
65fcd41d
TI		 800 int prev = power_save;
801 int ret = param_set_int(val, kp);
802
803 if (ret || prev == power_save)
804 return ret;
805
806 mutex_lock(&card_list_lock);
9a34af4a
TI		 807 list_for_each_entry(hda, &card_list, list) {
808 chip = &hda->chip;
a41d1224 809 if (!hda->probe_continued || chip->disabled)
65fcd41d 810 continue;
a41d1224 811 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 812 }
813 mutex_unlock(&card_list_lock);
814 return 0;
815}
816#else
817#define azx_add_card_list(chip) /* NOP */
818#define azx_del_card_list(chip) /* NOP */
83012a7c 819#endif /* CONFIG_PM */
5c0b9bec 820
98d8fc6c
ML		 821/* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
822 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
823 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
824 * BCLK = CDCLK * M / N
825 * The values will be lost when the display power well is disabled and need to
826 * be restored to avoid abnormal playback speed.
827 */
828static void haswell_set_bclk(struct hda_intel *hda)
829{
830 struct azx *chip = &hda->chip;
831 int cdclk_freq;
832 unsigned int bclk_m, bclk_n;
833
834 if (!hda->need_i915_power)
835 return;
836
837 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
838 switch (cdclk_freq) {
839 case 337500:
840 bclk_m = 16;
841 bclk_n = 225;
842 break;
843
844 case 450000:
845 default: /* default CDCLK 450MHz */
846 bclk_m = 4;
847 bclk_n = 75;
848 break;
849
850 case 540000:
851 bclk_m = 4;
852 bclk_n = 90;
853 break;
854
855 case 675000:
856 bclk_m = 8;
857 bclk_n = 225;
858 break;
859 }
860
861 azx_writew(chip, HSW_EM4, bclk_m);
862 azx_writew(chip, HSW_EM5, bclk_n);
863}
864
7ccbde57 865#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 866/*
867 * power management
868 */
68cb2b55 869static int azx_suspend(struct device *dev)
1da177e4 870{
68cb2b55 871 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 872 struct azx *chip;
873 struct hda_intel *hda;
a41d1224 874 struct hdac_bus *bus;
1da177e4 875
2d9772ef
TI		 876 if (!card)
877 return 0;
878
879 chip = card->private_data;
880 hda = container_of(chip, struct hda_intel, chip);
342e8449 881 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 882 return 0;
883
a41d1224 884 bus = azx_bus(chip);
421a1252 885 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 886 azx_clear_irq_pending(chip);
cb53c626 887 azx_stop_chip(chip);
7295b264 888 azx_enter_link_reset(chip);
a41d1224
TI		 889 if (bus->irq >= 0) {
890 free_irq(bus->irq, chip);
891 bus->irq = -1;
30b35399 892 }
a07187c9 893
68e7fffc 894 if (chip->msi)
43001c95 895 pci_disable_msi(chip->pci);
795614dd
ML		 896 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
897 && hda->need_i915_power)
98d8fc6c 898 snd_hdac_display_power(bus, false);
785d8c4b
LY		 899
900 trace_azx_suspend(chip);
1da177e4
LT		 901 return 0;
902}
903
68cb2b55 904static int azx_resume(struct device *dev)
1da177e4 905{
68cb2b55
TI		 906 struct pci_dev *pci = to_pci_dev(dev);
907 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 908 struct azx *chip;
909 struct hda_intel *hda;
910
911 if (!card)
912 return 0;
1da177e4 913
2d9772ef
TI		 914 chip = card->private_data;
915 hda = container_of(chip, struct hda_intel, chip);
342e8449 916 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 917 return 0;
918
795614dd
ML		 919 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
920 && hda->need_i915_power) {
98d8fc6c 921 snd_hdac_display_power(azx_bus(chip), true);
926981ae 922 haswell_set_bclk(hda);
a07187c9 923 }
68e7fffc
TI		 924 if (chip->msi)
925 if (pci_enable_msi(pci) < 0)
926 chip->msi = 0;
927 if (azx_acquire_irq(chip, 1) < 0)
30b35399 928 return -EIO;
cb53c626 929 azx_init_pci(chip);
d804ad92 930
0a673521 931 hda_intel_init_chip(chip, true);
d804ad92 932
421a1252 933 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 934
935 trace_azx_resume(chip);
1da177e4
LT		 936 return 0;
937}
b8dfc462
ML		 938#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
939
641d334b 940#ifdef CONFIG_PM
b8dfc462
ML		 941static int azx_runtime_suspend(struct device *dev)
942{
943 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 944 struct azx *chip;
945 struct hda_intel *hda;
b8dfc462 946
2d9772ef
TI		 947 if (!card)
948 return 0;
949
950 chip = card->private_data;
951 hda = container_of(chip, struct hda_intel, chip);
1618e84a 952 if (chip->disabled || hda->init_failed)
246efa4a
DA		 953 return 0;
954
364aa716 955 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 956 return 0;
957
7d4f606c
WX		 958 /* enable controller wake up event */
959 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
960 STATESTS_INT_MASK);
961
b8dfc462 962 azx_stop_chip(chip);
873ce8ad 963 azx_enter_link_reset(chip);
b8dfc462 964 azx_clear_irq_pending(chip);
795614dd
ML		 965 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
966 && hda->need_i915_power)
98d8fc6c 967 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 968
785d8c4b 969 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 970 return 0;
971}
972
973static int azx_runtime_resume(struct device *dev)
974{
975 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 976 struct azx *chip;
977 struct hda_intel *hda;
98d8fc6c 978 struct hdac_bus *bus;
7d4f606c
WX		 979 struct hda_codec *codec;
980 int status;
b8dfc462 981
2d9772ef
TI		 982 if (!card)
983 return 0;
984
985 chip = card->private_data;
986 hda = container_of(chip, struct hda_intel, chip);
1618e84a 987 if (chip->disabled || hda->init_failed)
246efa4a
DA		 988 return 0;
989
364aa716 990 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 991 return 0;
992
033ea349
DH		 993 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
994 bus = azx_bus(chip);
995 if (hda->need_i915_power) {
996 snd_hdac_display_power(bus, true);
997 haswell_set_bclk(hda);
998 } else {
999 /* toggle codec wakeup bit for STATESTS read */
1000 snd_hdac_set_codec_wakeup(bus, true);
1001 snd_hdac_set_codec_wakeup(bus, false);
1002 }
a07187c9 1003 }
7d4f606c
WX		 1004
1005 /* Read STATESTS before controller reset */
1006 status = azx_readw(chip, STATESTS);
1007
b8dfc462 1008 azx_init_pci(chip);
0a673521 1009 hda_intel_init_chip(chip, true);
7d4f606c 1010
a41d1224
TI		 1011 if (status) {
1012 list_for_each_codec(codec, &chip->bus)
7d4f606c 1013 if (status & (1 << codec->addr))
2f35c630
TI		 1014 schedule_delayed_work(&codec->jackpoll_work,
1015 codec->jackpoll_interval);
7d4f606c
WX		 1016 }
1017
1018 /* disable controller Wake Up event*/
1019 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1020 ~STATESTS_INT_MASK);
1021
785d8c4b 1022 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1023 return 0;
1024}
6eb827d2
TI		 1025
1026static int azx_runtime_idle(struct device *dev)
1027{
1028 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1029 struct azx *chip;
1030 struct hda_intel *hda;
1031
1032 if (!card)
1033 return 0;
6eb827d2 1034
2d9772ef
TI		 1035 chip = card->private_data;
1036 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1037 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1038 return 0;
1039
55ed9cd1 1040 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1041 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1042 return -EBUSY;
1043
1044 return 0;
1045}
1046
b8dfc462
ML		 1047static const struct dev_pm_ops azx_pm = {
1048 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 1049 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1050};
1051
68cb2b55
TI		 1052#define AZX_PM_OPS &azx_pm
1053#else
68cb2b55 1054#define AZX_PM_OPS NULL
b8dfc462 1055#endif /* CONFIG_PM */
1da177e4
LT		 1056
1057
48c8b0eb 1058static int azx_probe_continue(struct azx *chip);
a82d51ed 1059
8393ec4a 1060#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1061static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1062
a82d51ed
TI		 1063static void azx_vs_set_state(struct pci_dev *pci,
1064 enum vga_switcheroo_state state)
1065{
1066 struct snd_card *card = pci_get_drvdata(pci);
1067 struct azx *chip = card->private_data;
9a34af4a 1068 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1069 bool disabled;
1070
9a34af4a
TI		 1071 wait_for_completion(&hda->probe_wait);
1072 if (hda->init_failed)
a82d51ed
TI		 1073 return;
1074
1075 disabled = (state == VGA_SWITCHEROO_OFF);
1076 if (chip->disabled == disabled)
1077 return;
1078
a41d1224 1079 if (!hda->probe_continued) {
a82d51ed
TI		 1080 chip->disabled = disabled;
1081 if (!disabled) {
4e76a883
TI		 1082 dev_info(chip->card->dev,
1083 "Start delayed initialization\n");
5c90680e 1084 if (azx_probe_continue(chip) < 0) {
4e76a883 1085 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1086 hda->init_failed = true;
a82d51ed
TI		 1087 }
1088 }
1089 } else {
2b760d88 1090 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1091 disabled ? "Disabling" : "Enabling");
a82d51ed 1092 if (disabled) {
8928756d
DR		 1093 pm_runtime_put_sync_suspend(card->dev);
1094 azx_suspend(card->dev);
2b760d88 1095 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1096 * however we have no ACPI handle, so pci/acpi can't put us there,
1097 * put ourselves there */
1098 pci->current_state = PCI_D3cold;
a82d51ed 1099 chip->disabled = true;
a41d1224 1100 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1101 dev_warn(chip->card->dev,
1102 "Cannot lock devices!\n");
a82d51ed 1103 } else {
a41d1224 1104 snd_hda_unlock_devices(&chip->bus);
8928756d 1105 pm_runtime_get_noresume(card->dev);
a82d51ed 1106 chip->disabled = false;
8928756d 1107 azx_resume(card->dev);
a82d51ed
TI		 1108 }
1109 }
1110}
1111
1112static bool azx_vs_can_switch(struct pci_dev *pci)
1113{
1114 struct snd_card *card = pci_get_drvdata(pci);
1115 struct azx *chip = card->private_data;
9a34af4a 1116 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1117
9a34af4a
TI		 1118 wait_for_completion(&hda->probe_wait);
1119 if (hda->init_failed)
a82d51ed 1120 return false;
a41d1224 1121 if (chip->disabled || !hda->probe_continued)
a82d51ed 1122 return true;
a41d1224 1123 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1124 return false;
a41d1224 1125 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1126 return true;
1127}
1128
e23e7a14 1129static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1130{
9a34af4a 1131 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1132 struct pci_dev *p = get_bound_vga(chip->pci);
1133 if (p) {
4e76a883 1134 dev_info(chip->card->dev,
2b760d88 1135 "Handle vga_switcheroo audio client\n");
9a34af4a 1136 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1137 pci_dev_put(p);
1138 }
1139}
1140
1141static const struct vga_switcheroo_client_ops azx_vs_ops = {
1142 .set_gpu_state = azx_vs_set_state,
1143 .can_switch = azx_vs_can_switch,
1144};
1145
e23e7a14 1146static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1147{
9a34af4a 1148 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1149 int err;
1150
9a34af4a 1151 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1152 return 0;
1153 /* FIXME: currently only handling DIS controller
1154 * is there any machine with two switchable HDMI audio controllers?
1155 */
128960a9 1156 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
21b45676 1157 VGA_SWITCHEROO_DIS);
128960a9
TI		 1158 if (err < 0)
1159 return err;
9a34af4a 1160 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1161
1162 /* register as an optimus hdmi audio power domain */
8928756d 1163 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1164 &hda->hdmi_pm_domain);
128960a9 1165 return 0;
a82d51ed
TI		 1166}
1167#else
1168#define init_vga_switcheroo(chip) /* NOP */
1169#define register_vga_switcheroo(chip) 0
8393ec4a 1170#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1171#endif /* SUPPORT_VGA_SWITCHER */
1172
1da177e4
LT		 1173/*
1174 * destructor
1175 */
a98f90fd 1176static int azx_free(struct azx *chip)
1da177e4 1177{
c67e2228 1178 struct pci_dev *pci = chip->pci;
a07187c9 1179 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1180 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1181
364aa716 1182 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1183 pm_runtime_get_noresume(&pci->dev);
1184
65fcd41d
TI		 1185 azx_del_card_list(chip);
1186
9a34af4a
TI		 1187 hda->init_failed = 1; /* to be sure */
1188 complete_all(&hda->probe_wait);
f4c482a4 1189
9a34af4a 1190 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1191 if (chip->disabled && hda->probe_continued)
1192 snd_hda_unlock_devices(&chip->bus);
9a34af4a 1193 if (hda->vga_switcheroo_registered)
128960a9 1194 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1195 }
1196
a41d1224 1197 if (bus->chip_init) {
9ad593f6 1198 azx_clear_irq_pending(chip);
7833c3f8 1199 azx_stop_all_streams(chip);
cb53c626 1200 azx_stop_chip(chip);
1da177e4
LT		 1201 }
1202
a41d1224
TI		 1203 if (bus->irq >= 0)
1204 free_irq(bus->irq, (void*)chip);
68e7fffc 1205 if (chip->msi)
30b35399 1206 pci_disable_msi(chip->pci);
a41d1224 1207 iounmap(bus->remap_addr);
1da177e4 1208
67908994 1209 azx_free_stream_pages(chip);
a41d1224
TI		 1210 azx_free_streams(chip);
1211 snd_hdac_bus_exit(bus);
1212
a82d51ed
TI		 1213 if (chip->region_requested)
1214 pci_release_regions(chip->pci);
a41d1224 1215
1da177e4 1216 pci_disable_device(chip->pci);
4918cdab 1217#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1218 release_firmware(chip->fw);
4918cdab 1219#endif
98d8fc6c 1220
99a2008d 1221 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1222 if (hda->need_i915_power)
98d8fc6c
ML		 1223 snd_hdac_display_power(bus, false);
1224 snd_hdac_i915_exit(bus);
99a2008d 1225 }
a07187c9 1226 kfree(hda);
1da177e4
LT		 1227
1228 return 0;
1229}
1230
a41d1224
TI		 1231static int azx_dev_disconnect(struct snd_device *device)
1232{
1233 struct azx *chip = device->device_data;
1234
1235 chip->bus.shutdown = 1;
1236 return 0;
1237}
1238
a98f90fd 1239static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1240{
1241 return azx_free(device->device_data);
1242}
1243
8393ec4a 1244#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1245/*
2b760d88 1246 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1247 */
e23e7a14 1248static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1249{
1250 struct pci_dev *p;
1251
1252 /* check only discrete GPU */
1253 switch (pci->vendor) {
1254 case PCI_VENDOR_ID_ATI:
1255 case PCI_VENDOR_ID_AMD:
1256 case PCI_VENDOR_ID_NVIDIA:
1257 if (pci->devfn == 1) {
1258 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1259 pci->bus->number, 0);
1260 if (p) {
1261 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1262 return p;
1263 pci_dev_put(p);
1264 }
1265 }
1266 break;
1267 }
1268 return NULL;
1269}
1270
e23e7a14 1271static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1272{
1273 bool vga_inactive = false;
1274 struct pci_dev *p = get_bound_vga(pci);
1275
1276 if (p) {
12b78a7f 1277 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1278 vga_inactive = true;
1279 pci_dev_put(p);
1280 }
1281 return vga_inactive;
1282}
8393ec4a 1283#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1284
3372a153
TI		 1285/*
1286 * white/black-listing for position_fix
1287 */
e23e7a14 1288static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1289 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1290 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1291 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1292 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1293 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1294 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1295 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1296 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1297 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1298 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1299 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1300 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1301 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1302 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1303 {}
1304};
1305
e23e7a14 1306static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1307{
1308 const struct snd_pci_quirk *q;
1309
c673ba1c 1310 switch (fix) {
1dac6695 1311 case POS_FIX_AUTO:
c673ba1c
TI		 1312 case POS_FIX_LPIB:
1313 case POS_FIX_POSBUF:
4cb36310 1314 case POS_FIX_VIACOMBO:
a6f2fd55 1315 case POS_FIX_COMBO:
c673ba1c
TI		 1316 return fix;
1317 }
1318
c673ba1c
TI		 1319 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1320 if (q) {
4e76a883
TI		 1321 dev_info(chip->card->dev,
1322 "position_fix set to %d for device %04x:%04x\n",
1323 q->value, q->subvendor, q->subdevice);
c673ba1c 1324 return q->value;
3372a153 1325 }
bdd9ef24
DH		 1326
1327 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1328 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1329 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1330 return POS_FIX_VIACOMBO;
9477c58e
TI		 1331 }
1332 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1333 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1334 return POS_FIX_LPIB;
bdd9ef24 1335 }
c673ba1c 1336 return POS_FIX_AUTO;
3372a153
TI		 1337}
1338
b6050ef6
TI		 1339static void assign_position_fix(struct azx *chip, int fix)
1340{
1341 static azx_get_pos_callback_t callbacks[] = {
1342 [POS_FIX_AUTO] = NULL,
1343 [POS_FIX_LPIB] = azx_get_pos_lpib,
1344 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1345 [POS_FIX_VIACOMBO] = azx_via_get_position,
1346 [POS_FIX_COMBO] = azx_get_pos_lpib,
1347 };
1348
1349 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1350
1351 /* combo mode uses LPIB only for playback */
1352 if (fix == POS_FIX_COMBO)
1353 chip->get_position[1] = NULL;
1354
1355 if (fix == POS_FIX_POSBUF &&
1356 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1357 chip->get_delay[0] = chip->get_delay[1] =
1358 azx_get_delay_from_lpib;
1359 }
1360
1361}
1362
669ba27a
TI		 1363/*
1364 * black-lists for probe_mask
1365 */
e23e7a14 1366static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1367 /* Thinkpad often breaks the controller communication when accessing
1368 * to the non-working (or non-existing) modem codec slot.
1369 */
1370 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1371 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1372 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1373 /* broken BIOS */
1374 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1375 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1376 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1377 /* forced codec slots */
93574844 1378 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1379 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1380 /* WinFast VP200 H (Teradici) user reported broken communication */
1381 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1382 {}
1383};
1384
f1eaaeec
TI		 1385#define AZX_FORCE_CODEC_MASK 0x100
1386
e23e7a14 1387static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1388{
1389 const struct snd_pci_quirk *q;
1390
f1eaaeec
TI		 1391 chip->codec_probe_mask = probe_mask[dev];
1392 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1393 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1394 if (q) {
4e76a883
TI		 1395 dev_info(chip->card->dev,
1396 "probe_mask set to 0x%x for device %04x:%04x\n",
1397 q->value, q->subvendor, q->subdevice);
f1eaaeec 1398 chip->codec_probe_mask = q->value;
669ba27a
TI		 1399 }
1400 }
f1eaaeec
TI		 1401
1402 /* check forced option */
1403 if (chip->codec_probe_mask != -1 &&
1404 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1405 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1406 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1407 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1408 }
669ba27a
TI		 1409}
1410
4d8e22e0 1411/*
71623855 1412 * white/black-list for enable_msi
4d8e22e0 1413 */
e23e7a14 1414static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1415 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1416 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1417 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1418 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1419 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1420 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1421 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1422 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1423 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1424 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1425 {}
1426};
1427
e23e7a14 1428static void check_msi(struct azx *chip)
4d8e22e0
TI		 1429{
1430 const struct snd_pci_quirk *q;
1431
71623855
TI		 1432 if (enable_msi >= 0) {
1433 chip->msi = !!enable_msi;
4d8e22e0 1434 return;
71623855
TI		 1435 }
1436 chip->msi = 1; /* enable MSI as default */
1437 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1438 if (q) {
4e76a883
TI		 1439 dev_info(chip->card->dev,
1440 "msi for device %04x:%04x set to %d\n",
1441 q->subvendor, q->subdevice, q->value);
4d8e22e0 1442 chip->msi = q->value;
80c43ed7
TI		 1443 return;
1444 }
1445
1446 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1447 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1448 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1449 chip->msi = 0;
4d8e22e0
TI		 1450 }
1451}
1452
a1585d76 1453/* check the snoop mode availability */
e23e7a14 1454static void azx_check_snoop_available(struct azx *chip)
a1585d76 1455{
7c732015 1456 int snoop = hda_snoop;
a1585d76 1457
7c732015
TI		 1458 if (snoop >= 0) {
1459 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1460 snoop ? "snoop" : "non-snoop");
1461 chip->snoop = snoop;
1462 return;
1463 }
1464
1465 snoop = true;
37e661ee
TI		 1466 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1467 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1468 /* force to non-snoop mode for a new VIA controller
1469 * when BIOS is set
1470 */
7c732015
TI		 1471 u8 val;
1472 pci_read_config_byte(chip->pci, 0x42, &val);
1473 if (!(val & 0x80) && chip->pci->revision == 0x30)
1474 snoop = false;
a1585d76
TI		 1475 }
1476
37e661ee
TI		 1477 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1478 snoop = false;
1479
7c732015
TI		 1480 chip->snoop = snoop;
1481 if (!snoop)
1482 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1483}
669ba27a 1484
99a2008d
WX		 1485static void azx_probe_work(struct work_struct *work)
1486{
9a34af4a
TI		 1487 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1488 azx_probe_continue(&hda->chip);
99a2008d 1489}
99a2008d 1490
4f0189be
TI		 1491static int default_bdl_pos_adj(struct azx *chip)
1492{
2cf721db
TI		 1493 /* some exceptions: Atoms seem problematic with value 1 */
1494 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1495 switch (chip->pci->device) {
1496 case 0x0f04: /* Baytrail */
1497 case 0x2284: /* Braswell */
1498 return 32;
1499 }
1500 }
1501
4f0189be
TI		 1502 switch (chip->driver_type) {
1503 case AZX_DRIVER_ICH:
1504 case AZX_DRIVER_PCH:
1505 return 1;
1506 default:
1507 return 32;
1508 }
1509}
1510
1da177e4
LT		 1511/*
1512 * constructor
1513 */
a43ff5ba
TI		 1514static const struct hdac_io_ops pci_hda_io_ops;
1515static const struct hda_controller_ops pci_hda_ops;
1516
e23e7a14
BP		 1517static int azx_create(struct snd_card *card, struct pci_dev *pci,
1518 int dev, unsigned int driver_caps,
1519 struct azx **rchip)
1da177e4 1520{
a98f90fd 1521 static struct snd_device_ops ops = {
a41d1224 1522 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1523 .dev_free = azx_dev_free,
1524 };
a07187c9 1525 struct hda_intel *hda;
a82d51ed
TI		 1526 struct azx *chip;
1527 int err;
1da177e4
LT		 1528
1529 *rchip = NULL;
bcd72003 1530
927fc866
PM		 1531 err = pci_enable_device(pci);
1532 if (err < 0)
1da177e4
LT		 1533 return err;
1534
a07187c9
ML		 1535 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1536 if (!hda) {
1da177e4
LT		 1537 pci_disable_device(pci);
1538 return -ENOMEM;
1539 }
1540
a07187c9 1541 chip = &hda->chip;
62932df8 1542 mutex_init(&chip->open_mutex);
1da177e4
LT		 1543 chip->card = card;
1544 chip->pci = pci;
a43ff5ba 1545 chip->ops = &pci_hda_ops;
9477c58e
TI		 1546 chip->driver_caps = driver_caps;
1547 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1548 check_msi(chip);
555e219f 1549 chip->dev_index = dev;
749ee287 1550 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1551 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1552 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1553 INIT_LIST_HEAD(&hda->list);
a82d51ed 1554 init_vga_switcheroo(chip);
9a34af4a 1555 init_completion(&hda->probe_wait);
1da177e4 1556
b6050ef6 1557 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1558
5aba4f8e 1559 check_probe_mask(chip, dev);
3372a153 1560
27346166 1561 chip->single_cmd = single_cmd;
a1585d76 1562 azx_check_snoop_available(chip);
c74db86b 1563
4f0189be
TI		 1564 if (bdl_pos_adj[dev] < 0)
1565 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1566 else
1567 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1568
a41d1224
TI		 1569 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1570 if (err < 0) {
1571 kfree(hda);
1572 pci_disable_device(pci);
1573 return err;
1574 }
1575
7d9a1808
TI		 1576 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1577 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1578 chip->bus.needs_damn_long_delay = 1;
1579 }
1580
a82d51ed
TI		 1581 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1582 if (err < 0) {
4e76a883 1583 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1584 azx_free(chip);
1585 return err;
1586 }
1587
99a2008d 1588 /* continue probing in work context as may trigger request module */
9a34af4a 1589 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1590
a82d51ed 1591 *rchip = chip;
99a2008d 1592
a82d51ed
TI		 1593 return 0;
1594}
1595
48c8b0eb 1596static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1597{
1598 int dev = chip->dev_index;
1599 struct pci_dev *pci = chip->pci;
1600 struct snd_card *card = chip->card;
a41d1224 1601 struct hdac_bus *bus = azx_bus(chip);
67908994 1602 int err;
a82d51ed 1603 unsigned short gcap;
413cbf46 1604 unsigned int dma_bits = 64;
a82d51ed 1605
07e4ca50
TI		 1606#if BITS_PER_LONG != 64
1607 /* Fix up base address on ULI M5461 */
1608 if (chip->driver_type == AZX_DRIVER_ULI) {
1609 u16 tmp3;
1610 pci_read_config_word(pci, 0x40, &tmp3);
1611 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1612 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1613 }
1614#endif
1615
927fc866 1616 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1617 if (err < 0)
1da177e4 1618 return err;
a82d51ed 1619 chip->region_requested = 1;
1da177e4 1620
a41d1224
TI		 1621 bus->addr = pci_resource_start(pci, 0);
1622 bus->remap_addr = pci_ioremap_bar(pci, 0);
1623 if (bus->remap_addr == NULL) {
4e76a883 1624 dev_err(card->dev, "ioremap error\n");
a82d51ed 1625 return -ENXIO;
1da177e4
LT		 1626 }
1627
db79afa1
BH		 1628 if (chip->msi) {
1629 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1630 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1631 pci->no_64bit_msi = true;
1632 }
68e7fffc
TI		 1633 if (pci_enable_msi(pci) < 0)
1634 chip->msi = 0;
db79afa1 1635 }
7376d013 1636
a82d51ed
TI		 1637 if (azx_acquire_irq(chip, 0) < 0)
1638 return -EBUSY;
1da177e4
LT		 1639
1640 pci_set_master(pci);
a41d1224 1641 synchronize_irq(bus->irq);
1da177e4 1642
bcd72003 1643 gcap = azx_readw(chip, GCAP);
4e76a883 1644 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1645
413cbf46
TI		 1646 /* AMD devices support 40 or 48bit DMA, take the safe one */
1647 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1648 dma_bits = 40;
1649
dc4c2e6b 1650 /* disable SB600 64bit support for safety */
9477c58e 1651 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1652 struct pci_dev *p_smbus;
413cbf46 1653 dma_bits = 40;
dc4c2e6b
AB		 1654 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1655 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1656 NULL);
1657 if (p_smbus) {
1658 if (p_smbus->revision < 0x30)
fb1d8ac2 1659 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1660 pci_dev_put(p_smbus);
1661 }
1662 }
09240cf4 1663
9477c58e
TI		 1664 /* disable 64bit DMA address on some devices */
1665 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1666 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1667 gcap &= ~AZX_GCAP_64OK;
9477c58e 1668 }
396087ea 1669
2ae66c26 1670 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1671 if (align_buffer_size >= 0)
1672 chip->align_buffer_size = !!align_buffer_size;
1673 else {
103884a3 1674 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1675 chip->align_buffer_size = 0;
7bfe059e
TI		 1676 else
1677 chip->align_buffer_size = 1;
1678 }
2ae66c26 1679
cf7aaca8 1680 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1681 if (!(gcap & AZX_GCAP_64OK))
1682 dma_bits = 32;
412b979c
QL		 1683 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1684 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1685 } else {
412b979c
QL		 1686 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1687 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1688 }
cf7aaca8 1689
8b6ed8e7
TI		 1690 /* read number of streams from GCAP register instead of using
1691 * hardcoded value
1692 */
1693 chip->capture_streams = (gcap >> 8) & 0x0f;
1694 chip->playback_streams = (gcap >> 12) & 0x0f;
1695 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1696 /* gcap didn't give any info, switching to old method */
1697
1698 switch (chip->driver_type) {
1699 case AZX_DRIVER_ULI:
1700 chip->playback_streams = ULI_NUM_PLAYBACK;
1701 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1702 break;
1703 case AZX_DRIVER_ATIHDMI:
1815b34a 1704 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1705 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1706 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1707 break;
c4da29ca 1708 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1709 default:
1710 chip->playback_streams = ICH6_NUM_PLAYBACK;
1711 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1712 break;
1713 }
07e4ca50 1714 }
8b6ed8e7
TI		 1715 chip->capture_index_offset = 0;
1716 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1717 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1718
a41d1224
TI		 1719 /* initialize streams */
1720 err = azx_init_streams(chip);
81740861 1721 if (err < 0)
a82d51ed 1722 return err;
1da177e4 1723
a41d1224
TI		 1724 err = azx_alloc_stream_pages(chip);
1725 if (err < 0)
1726 return err;
1da177e4
LT		 1727
1728 /* initialize chip */
cb53c626 1729 azx_init_pci(chip);
e4d9e513 1730
926981ae
ID		 1731 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1732 struct hda_intel *hda;
1733
1734 hda = container_of(chip, struct hda_intel, chip);
1735 haswell_set_bclk(hda);
1736 }
e4d9e513 1737
0a673521 1738 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1739
1740 /* codec detection */
a41d1224 1741 if (!azx_bus(chip)->codec_mask) {
4e76a883 1742 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1743 return -ENODEV;
1da177e4
LT		 1744 }
1745
07e4ca50 1746 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1747 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1748 sizeof(card->shortname));
1749 snprintf(card->longname, sizeof(card->longname),
1750 "%s at 0x%lx irq %i",
a41d1224 1751 card->shortname, bus->addr, bus->irq);
07e4ca50 1752
1da177e4 1753 return 0;
1da177e4
LT		 1754}
1755
97c6a3d1 1756#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1757/* callback from request_firmware_nowait() */
1758static void azx_firmware_cb(const struct firmware *fw, void *context)
1759{
1760 struct snd_card *card = context;
1761 struct azx *chip = card->private_data;
1762 struct pci_dev *pci = chip->pci;
1763
1764 if (!fw) {
4e76a883 1765 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1766 goto error;
1767 }
1768
1769 chip->fw = fw;
1770 if (!chip->disabled) {
1771 /* continue probing */
1772 if (azx_probe_continue(chip))
1773 goto error;
1774 }
1775 return; /* OK */
1776
1777 error:
1778 snd_card_free(card);
1779 pci_set_drvdata(pci, NULL);
1780}
97c6a3d1 1781#endif
5cb543db 1782
40830813
DR		 1783/*
1784 * HDA controller ops.
1785 */
1786
1787/* PCI register access. */
db291e36 1788static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1789{
1790 writel(value, addr);
1791}
1792
db291e36 1793static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1794{
1795 return readl(addr);
1796}
1797
db291e36 1798static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1799{
1800 writew(value, addr);
1801}
1802
db291e36 1803static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1804{
1805 return readw(addr);
1806}
1807
db291e36 1808static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1809{
1810 writeb(value, addr);
1811}
1812
db291e36 1813static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1814{
1815 return readb(addr);
1816}
1817
f46ea609
DR		 1818static int disable_msi_reset_irq(struct azx *chip)
1819{
a41d1224 1820 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1821 int err;
1822
a41d1224
TI		 1823 free_irq(bus->irq, chip);
1824 bus->irq = -1;
f46ea609
DR		 1825 pci_disable_msi(chip->pci);
1826 chip->msi = 0;
1827 err = azx_acquire_irq(chip, 1);
1828 if (err < 0)
1829 return err;
1830
1831 return 0;
1832}
1833
b419b35b 1834/* DMA page allocation helpers. */
a43ff5ba 1835static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1836 int type,
1837 size_t size,
1838 struct snd_dma_buffer *buf)
1839{
a41d1224 1840 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 1841 int err;
1842
1843 err = snd_dma_alloc_pages(type,
a43ff5ba 1844 bus->dev,
b419b35b
DR		 1845 size, buf);
1846 if (err < 0)
1847 return err;
1848 mark_pages_wc(chip, buf, true);
1849 return 0;
1850}
1851
a43ff5ba 1852static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 1853{
a41d1224 1854 struct azx *chip = bus_to_azx(bus);
a43ff5ba 1855
b419b35b
DR		 1856 mark_pages_wc(chip, buf, false);
1857 snd_dma_free_pages(buf);
1858}
1859
1860static int substream_alloc_pages(struct azx *chip,
1861 struct snd_pcm_substream *substream,
1862 size_t size)
1863{
1864 struct azx_dev *azx_dev = get_azx_dev(substream);
1865 int ret;
1866
1867 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 1868 ret = snd_pcm_lib_malloc_pages(substream, size);
1869 if (ret < 0)
1870 return ret;
1871 mark_runtime_wc(chip, azx_dev, substream, true);
1872 return 0;
1873}
1874
1875static int substream_free_pages(struct azx *chip,
1876 struct snd_pcm_substream *substream)
1877{
1878 struct azx_dev *azx_dev = get_azx_dev(substream);
1879 mark_runtime_wc(chip, azx_dev, substream, false);
1880 return snd_pcm_lib_free_pages(substream);
1881}
1882
8769b278
DR		 1883static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1884 struct vm_area_struct *area)
1885{
1886#ifdef CONFIG_X86
1887 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1888 struct azx *chip = apcm->chip;
3b70bdba 1889 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1890 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1891#endif
1892}
1893
a43ff5ba 1894static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 1895 .reg_writel = pci_azx_writel,
1896 .reg_readl = pci_azx_readl,
1897 .reg_writew = pci_azx_writew,
1898 .reg_readw = pci_azx_readw,
1899 .reg_writeb = pci_azx_writeb,
1900 .reg_readb = pci_azx_readb,
b419b35b
DR		 1901 .dma_alloc_pages = dma_alloc_pages,
1902 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 1903};
1904
1905static const struct hda_controller_ops pci_hda_ops = {
1906 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1907 .substream_alloc_pages = substream_alloc_pages,
1908 .substream_free_pages = substream_free_pages,
8769b278 1909 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1910 .position_check = azx_position_check,
17eccb27 1911 .link_power = azx_intel_link_power,
40830813
DR		 1912};
1913
e23e7a14
BP		 1914static int azx_probe(struct pci_dev *pci,
1915 const struct pci_device_id *pci_id)
1da177e4 1916{
5aba4f8e 1917 static int dev;
a98f90fd 1918 struct snd_card *card;
9a34af4a 1919 struct hda_intel *hda;
a98f90fd 1920 struct azx *chip;
aad730d0 1921 bool schedule_probe;
927fc866 1922 int err;
1da177e4 1923
5aba4f8e
TI		 1924 if (dev >= SNDRV_CARDS)
1925 return -ENODEV;
1926 if (!enable[dev]) {
1927 dev++;
1928 return -ENOENT;
1929 }
1930
60c5772b
TI		 1931 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1932 0, &card);
e58de7ba 1933 if (err < 0) {
4e76a883 1934 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1935 return err;
1da177e4
LT		 1936 }
1937
a43ff5ba 1938 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 1939 if (err < 0)
1940 goto out_free;
421a1252 1941 card->private_data = chip;
9a34af4a 1942 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1943
1944 pci_set_drvdata(pci, card);
1945
1946 err = register_vga_switcheroo(chip);
1947 if (err < 0) {
2b760d88 1948 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 1949 goto out_free;
1950 }
1951
1952 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1953 dev_info(card->dev, "VGA controller is disabled\n");
1954 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1955 chip->disabled = true;
1956 }
1957
aad730d0 1958 schedule_probe = !chip->disabled;
1da177e4 1959
4918cdab
TI		 1960#ifdef CONFIG_SND_HDA_PATCH_LOADER
1961 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1962 dev_info(card->dev, "Applying patch firmware '%s'\n",
1963 patch[dev]);
5cb543db
TI		 1964 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1965 &pci->dev, GFP_KERNEL, card,
1966 azx_firmware_cb);
4918cdab
TI		 1967 if (err < 0)
1968 goto out_free;
aad730d0 1969 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1970 }
1971#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1972
aad730d0 1973#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 1974 if (CONTROLLER_IN_GPU(pci))
1975 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 1976#endif
99a2008d 1977
aad730d0 1978 if (schedule_probe)
9a34af4a 1979 schedule_work(&hda->probe_work);
a82d51ed 1980
a82d51ed 1981 dev++;
88d071fc 1982 if (chip->disabled)
9a34af4a 1983 complete_all(&hda->probe_wait);
a82d51ed
TI		 1984 return 0;
1985
1986out_free:
1987 snd_card_free(card);
1988 return err;
1989}
1990
e62a42ae
DR		 1991/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1992static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1993 [AZX_DRIVER_NVIDIA] = 8,
1994 [AZX_DRIVER_TERA] = 1,
1995};
1996
48c8b0eb 1997static int azx_probe_continue(struct azx *chip)
a82d51ed 1998{
9a34af4a 1999 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2000 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2001 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2002 int dev = chip->dev_index;
2003 int err;
2004
a41d1224 2005 hda->probe_continued = 1;
795614dd
ML		 2006
2007 /* Request display power well for the HDA controller or codec. For
2008 * Haswell/Broadwell, both the display HDA controller and codec need
2009 * this power. For other platforms, like Baytrail/Braswell, only the
2010 * display codec needs the power and it can be released after probe.
2011 */
99a2008d 2012 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 2013 /* HSW/BDW controllers need this power */
2014 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 2015 hda->need_i915_power = 1;
2016
98d8fc6c 2017 err = snd_hdac_i915_init(bus);
535115b5
TI		 2018 if (err < 0) {
2019 /* if the controller is bound only with HDMI/DP
2020 * (for HSW and BDW), we need to abort the probe;
2021 * for other chips, still continue probing as other
2022 * codecs can be on the same link.
2023 */
2024 if (CONTROLLER_IN_GPU(pci))
2025 goto out_free;
2026 else
2027 goto skip_i915;
2028 }
795614dd 2029
98d8fc6c 2030 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2031 if (err < 0) {
2032 dev_err(chip->card->dev,
2033 "Cannot turn on display power on i915\n");
795614dd 2034 goto i915_power_fail;
74b0c2d7 2035 }
99a2008d
WX		 2036 }
2037
bf06848b 2038 skip_i915:
5c90680e
TI		 2039 err = azx_first_init(chip);
2040 if (err < 0)
2041 goto out_free;
2042
2dca0bba
JK		 2043#ifdef CONFIG_SND_HDA_INPUT_BEEP
2044 chip->beep_mode = beep_mode[dev];
2045#endif
2046
1da177e4 2047 /* create codec instances */
96d2bd6e 2048 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2049 if (err < 0)
2050 goto out_free;
96d2bd6e 2051
4ea6fbc8 2052#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2053 if (chip->fw) {
a41d1224 2054 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2055 chip->fw->data);
4ea6fbc8
TI		 2056 if (err < 0)
2057 goto out_free;
e39ae856 2058#ifndef CONFIG_PM
4918cdab
TI		 2059 release_firmware(chip->fw); /* no longer needed */
2060 chip->fw = NULL;
e39ae856 2061#endif
4ea6fbc8
TI		 2062 }
2063#endif
10e77dda 2064 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2065 err = azx_codec_configure(chip);
2066 if (err < 0)
2067 goto out_free;
2068 }
1da177e4 2069
a82d51ed 2070 err = snd_card_register(chip->card);
41dda0fd
WF		 2071 if (err < 0)
2072 goto out_free;
1da177e4 2073
cb53c626 2074 chip->running = 1;
65fcd41d 2075 azx_add_card_list(chip);
a41d1224 2076 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2077 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
c67e2228 2078 pm_runtime_put_noidle(&pci->dev);
1da177e4 2079
41dda0fd 2080out_free:
795614dd
ML		 2081 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2082 && !hda->need_i915_power)
98d8fc6c 2083 snd_hdac_display_power(bus, false);
795614dd
ML		 2084
2085i915_power_fail:
88d071fc 2086 if (err < 0)
9a34af4a
TI		 2087 hda->init_failed = 1;
2088 complete_all(&hda->probe_wait);
41dda0fd 2089 return err;
1da177e4
LT		 2090}
2091
e23e7a14 2092static void azx_remove(struct pci_dev *pci)
1da177e4 2093{
9121947d 2094 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 2095
9121947d
TI		 2096 if (card)
2097 snd_card_free(card);
1da177e4
LT		 2098}
2099
b2a0bafa
TI		 2100static void azx_shutdown(struct pci_dev *pci)
2101{
2102 struct snd_card *card = pci_get_drvdata(pci);
2103 struct azx *chip;
2104
2105 if (!card)
2106 return;
2107 chip = card->private_data;
2108 if (chip && chip->running)
2109 azx_stop_chip(chip);
2110}
2111
1da177e4 2112/* PCI IDs */
6f51f6cf 2113static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2114 /* CPT */
9477c58e 2115 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2116 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2117 /* PBG */
9477c58e 2118 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2119 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2120 /* Panther Point */
9477c58e 2121 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2122 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2123 /* Lynx Point */
2124 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2125 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2126 /* 9 Series */
2127 { PCI_DEVICE(0x8086, 0x8ca0),
2128 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2129 /* Wellsburg */
2130 { PCI_DEVICE(0x8086, 0x8d20),
2131 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2132 { PCI_DEVICE(0x8086, 0x8d21),
2133 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2134 /* Lewisburg */
2135 { PCI_DEVICE(0x8086, 0xa1f0),
2136 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2137 { PCI_DEVICE(0x8086, 0xa270),
2138 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2139 /* Lynx Point-LP */
2140 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2141 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2142 /* Lynx Point-LP */
2143 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2144 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2145 /* Wildcat Point-LP */
2146 { PCI_DEVICE(0x8086, 0x9ca0),
2147 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2148 /* Sunrise Point */
2149 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2150 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2151 /* Sunrise Point-LP */
2152 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2153 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
c87693da
LH		 2154 /* Broxton-P(Apollolake) */
2155 { PCI_DEVICE(0x8086, 0x5a98),
2156 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2157 /* Haswell */
4a7c516b 2158 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2159 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2160 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2161 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2162 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2163 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2164 /* Broadwell */
2165 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2166 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2167 /* 5 Series/3400 */
2168 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2169 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2170 /* Poulsbo */
9477c58e 2171 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2172 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2173 /* Oaktrail */
09904b95 2174 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2175 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2176 /* BayTrail */
2177 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2178 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2179 /* Braswell */
2180 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2181 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2182 /* ICH6 */
8b0bd226 2183 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2184 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2185 /* ICH7 */
8b0bd226 2186 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2187 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2188 /* ESB2 */
8b0bd226 2189 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2190 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2191 /* ICH8 */
8b0bd226 2192 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2193 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2194 /* ICH9 */
8b0bd226 2195 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2196 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2197 /* ICH9 */
8b0bd226 2198 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2199 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2200 /* ICH10 */
8b0bd226 2201 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2202 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2203 /* ICH10 */
8b0bd226 2204 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2205 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2206 /* Generic Intel */
2207 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2208 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2209 .class_mask = 0xffffff,
103884a3 2210 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2211 /* ATI SB 450/600/700/800/900 */
2212 { PCI_DEVICE(0x1002, 0x437b),
2213 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2214 { PCI_DEVICE(0x1002, 0x4383),
2215 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2216 /* AMD Hudson */
2217 { PCI_DEVICE(0x1022, 0x780d),
2218 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2219 /* ATI HDMI */
650474fb
AD		 2220 { PCI_DEVICE(0x1002, 0x1308),
2221 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2222 { PCI_DEVICE(0x1002, 0x157a),
2223 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2224 { PCI_DEVICE(0x1002, 0x793b),
2225 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2226 { PCI_DEVICE(0x1002, 0x7919),
2227 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2228 { PCI_DEVICE(0x1002, 0x960f),
2229 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2230 { PCI_DEVICE(0x1002, 0x970f),
2231 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2232 { PCI_DEVICE(0x1002, 0x9840),
2233 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2234 { PCI_DEVICE(0x1002, 0xaa00),
2235 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2236 { PCI_DEVICE(0x1002, 0xaa08),
2237 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2238 { PCI_DEVICE(0x1002, 0xaa10),
2239 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2240 { PCI_DEVICE(0x1002, 0xaa18),
2241 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2242 { PCI_DEVICE(0x1002, 0xaa20),
2243 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2244 { PCI_DEVICE(0x1002, 0xaa28),
2245 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2246 { PCI_DEVICE(0x1002, 0xaa30),
2247 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2248 { PCI_DEVICE(0x1002, 0xaa38),
2249 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2250 { PCI_DEVICE(0x1002, 0xaa40),
2251 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2252 { PCI_DEVICE(0x1002, 0xaa48),
2253 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2254 { PCI_DEVICE(0x1002, 0xaa50),
2255 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2256 { PCI_DEVICE(0x1002, 0xaa58),
2257 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2258 { PCI_DEVICE(0x1002, 0xaa60),
2259 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2260 { PCI_DEVICE(0x1002, 0xaa68),
2261 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2262 { PCI_DEVICE(0x1002, 0xaa80),
2263 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2264 { PCI_DEVICE(0x1002, 0xaa88),
2265 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2266 { PCI_DEVICE(0x1002, 0xaa90),
2267 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2268 { PCI_DEVICE(0x1002, 0xaa98),
2269 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2270 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2271 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2272 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2273 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2274 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2275 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2276 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2277 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2278 { PCI_DEVICE(0x1002, 0xaac0),
2279 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2280 { PCI_DEVICE(0x1002, 0xaac8),
2281 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2282 { PCI_DEVICE(0x1002, 0xaad8),
2283 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2284 { PCI_DEVICE(0x1002, 0xaae8),
2285 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2286 /* VIA VT8251/VT8237A */
9477c58e
TI		 2287 { PCI_DEVICE(0x1106, 0x3288),
2288 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2289 /* VIA GFX VT7122/VX900 */
2290 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2291 /* VIA GFX VT6122/VX11 */
2292 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2293 /* SIS966 */
2294 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2295 /* ULI M5461 */
2296 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2297 /* NVIDIA MCP */
0c2fd1bf
TI		 2298 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2299 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2300 .class_mask = 0xffffff,
9477c58e 2301 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2302 /* Teradici */
9477c58e
TI		 2303 { PCI_DEVICE(0x6549, 0x1200),
2304 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2305 { PCI_DEVICE(0x6549, 0x2200),
2306 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2307 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2308 /* CTHDA chips */
2309 { PCI_DEVICE(0x1102, 0x0010),
2310 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2311 { PCI_DEVICE(0x1102, 0x0012),
2312 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2313#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2314 /* the following entry conflicts with snd-ctxfi driver,
2315 * as ctxfi driver mutates from HD-audio to native mode with
2316 * a special command sequence.
2317 */
4e01f54b
TI		 2318 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2319 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2320 .class_mask = 0xffffff,
9477c58e 2321 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2322 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2323#else
2324 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2325 { PCI_DEVICE(0x1102, 0x0009),
2326 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2327 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2328#endif
c563f473
TI		 2329 /* CM8888 */
2330 { PCI_DEVICE(0x13f6, 0x5011),
2331 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2332 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2333 /* Vortex86MX */
2334 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2335 /* VMware HDAudio */
2336 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2337 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2338 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2339 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2340 .class_mask = 0xffffff,
9477c58e 2341 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2342 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2343 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2344 .class_mask = 0xffffff,
9477c58e 2345 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2346 { 0, }
2347};
2348MODULE_DEVICE_TABLE(pci, azx_ids);
2349
2350/* pci_driver definition */
e9f66d9b 2351static struct pci_driver azx_driver = {
3733e424 2352 .name = KBUILD_MODNAME,
1da177e4
LT		 2353 .id_table = azx_ids,
2354 .probe = azx_probe,
e23e7a14 2355 .remove = azx_remove,
b2a0bafa 2356 .shutdown = azx_shutdown,
68cb2b55
TI		 2357 .driver = {
2358 .pm = AZX_PM_OPS,
2359 },
1da177e4
LT		 2360};
2361
e9f66d9b 2362module_pci_driver(azx_driver);
Linux 6.x block layer and io_uring tree(s)