Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
d01ce99f TI |
3 | * hda_intel.c - Implementation of primary alsa driver code base |
4 | * for Intel HD Audio. | |
1da177e4 LT |
5 | * |
6 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
7 | * | |
8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
9 | * PeiSen Hou <pshou@realtek.com.tw> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the Free | |
13 | * Software Foundation; either version 2 of the License, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along with | |
22 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
23 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
24 | * | |
25 | * CONTACTS: | |
26 | * | |
27 | * Matt Jared matt.jared@intel.com | |
28 | * Andy Kopp andy.kopp@intel.com | |
29 | * Dan Kogan dan.d.kogan@intel.com | |
30 | * | |
31 | * CHANGES: | |
32 | * | |
33 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | |
34 | * | |
35 | */ | |
36 | ||
1da177e4 LT |
37 | #include <asm/io.h> |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
362775e2 | 40 | #include <linux/kernel.h> |
1da177e4 | 41 | #include <linux/module.h> |
24982c5f | 42 | #include <linux/dma-mapping.h> |
1da177e4 LT |
43 | #include <linux/moduleparam.h> |
44 | #include <linux/init.h> | |
45 | #include <linux/slab.h> | |
46 | #include <linux/pci.h> | |
62932df8 | 47 | #include <linux/mutex.h> |
0cbf0098 | 48 | #include <linux/reboot.h> |
1da177e4 LT |
49 | #include <sound/core.h> |
50 | #include <sound/initval.h> | |
51 | #include "hda_codec.h" | |
52 | ||
53 | ||
5aba4f8e TI |
54 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; |
55 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | |
56 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; | |
57 | static char *model[SNDRV_CARDS]; | |
58 | static int position_fix[SNDRV_CARDS]; | |
5c0d7bc1 | 59 | static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
5aba4f8e | 60 | static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
d4d9cd03 | 61 | static int probe_only[SNDRV_CARDS]; |
27346166 | 62 | static int single_cmd; |
71623855 | 63 | static int enable_msi = -1; |
4ea6fbc8 TI |
64 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
65 | static char *patch[SNDRV_CARDS]; | |
66 | #endif | |
2dca0bba JK |
67 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
68 | static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = | |
69 | CONFIG_SND_HDA_INPUT_BEEP_MODE}; | |
70 | #endif | |
1da177e4 | 71 | |
5aba4f8e | 72 | module_param_array(index, int, NULL, 0444); |
1da177e4 | 73 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
5aba4f8e | 74 | module_param_array(id, charp, NULL, 0444); |
1da177e4 | 75 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
5aba4f8e TI |
76 | module_param_array(enable, bool, NULL, 0444); |
77 | MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); | |
78 | module_param_array(model, charp, NULL, 0444); | |
1da177e4 | 79 | MODULE_PARM_DESC(model, "Use the given board model."); |
5aba4f8e | 80 | module_param_array(position_fix, int, NULL, 0444); |
d01ce99f | 81 | MODULE_PARM_DESC(position_fix, "Fix DMA pointer " |
d2e1c973 | 82 | "(0 = auto, 1 = none, 2 = POSBUF)."); |
555e219f TI |
83 | module_param_array(bdl_pos_adj, int, NULL, 0644); |
84 | MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); | |
5aba4f8e | 85 | module_param_array(probe_mask, int, NULL, 0444); |
606ad75f | 86 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); |
079e683e | 87 | module_param_array(probe_only, int, NULL, 0444); |
d4d9cd03 | 88 | MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); |
27346166 | 89 | module_param(single_cmd, bool, 0444); |
d01ce99f TI |
90 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " |
91 | "(for debugging only)."); | |
5aba4f8e | 92 | module_param(enable_msi, int, 0444); |
134a11f0 | 93 | MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); |
4ea6fbc8 TI |
94 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
95 | module_param_array(patch, charp, NULL, 0444); | |
96 | MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); | |
97 | #endif | |
2dca0bba JK |
98 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
99 | module_param_array(beep_mode, int, NULL, 0444); | |
100 | MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " | |
101 | "(0=off, 1=on, 2=mute switch on/off) (default=1)."); | |
102 | #endif | |
606ad75f | 103 | |
dee1b66c | 104 | #ifdef CONFIG_SND_HDA_POWER_SAVE |
fee2fba3 TI |
105 | static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; |
106 | module_param(power_save, int, 0644); | |
107 | MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " | |
108 | "(in second, 0 = disable)."); | |
1da177e4 | 109 | |
dee1b66c TI |
110 | /* reset the HD-audio controller in power save mode. |
111 | * this may give more power-saving, but will take longer time to | |
112 | * wake up. | |
113 | */ | |
114 | static int power_save_controller = 1; | |
115 | module_param(power_save_controller, bool, 0644); | |
116 | MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); | |
117 | #endif | |
118 | ||
1da177e4 LT |
119 | MODULE_LICENSE("GPL"); |
120 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | |
121 | "{Intel, ICH6M}," | |
2f1b3818 | 122 | "{Intel, ICH7}," |
f5d40b30 | 123 | "{Intel, ESB2}," |
d2981393 | 124 | "{Intel, ICH8}," |
f9cc8a8b | 125 | "{Intel, ICH9}," |
c34f5a04 | 126 | "{Intel, ICH10}," |
b29c2360 | 127 | "{Intel, PCH}," |
d2f2fcd2 | 128 | "{Intel, CPT}," |
4979bca9 | 129 | "{Intel, SCH}," |
fc20a562 | 130 | "{ATI, SB450}," |
89be83f8 | 131 | "{ATI, SB600}," |
778b6e1b | 132 | "{ATI, RS600}," |
5b15c95f | 133 | "{ATI, RS690}," |
e6db1119 WL |
134 | "{ATI, RS780}," |
135 | "{ATI, R600}," | |
2797f724 HRK |
136 | "{ATI, RV630}," |
137 | "{ATI, RV610}," | |
27da1834 WL |
138 | "{ATI, RV670}," |
139 | "{ATI, RV635}," | |
140 | "{ATI, RV620}," | |
141 | "{ATI, RV770}," | |
fc20a562 | 142 | "{VIA, VT8251}," |
47672310 | 143 | "{VIA, VT8237A}," |
07e4ca50 TI |
144 | "{SiS, SIS966}," |
145 | "{ULI, M5461}}"); | |
1da177e4 LT |
146 | MODULE_DESCRIPTION("Intel HDA driver"); |
147 | ||
4abc1cc2 TI |
148 | #ifdef CONFIG_SND_VERBOSE_PRINTK |
149 | #define SFX /* nop */ | |
150 | #else | |
1da177e4 | 151 | #define SFX "hda-intel: " |
4abc1cc2 | 152 | #endif |
cb53c626 | 153 | |
1da177e4 LT |
154 | /* |
155 | * registers | |
156 | */ | |
157 | #define ICH6_REG_GCAP 0x00 | |
b21fadb9 TI |
158 | #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ |
159 | #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ | |
160 | #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ | |
161 | #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ | |
162 | #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ | |
1da177e4 LT |
163 | #define ICH6_REG_VMIN 0x02 |
164 | #define ICH6_REG_VMAJ 0x03 | |
165 | #define ICH6_REG_OUTPAY 0x04 | |
166 | #define ICH6_REG_INPAY 0x06 | |
167 | #define ICH6_REG_GCTL 0x08 | |
8a933ece | 168 | #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ |
b21fadb9 TI |
169 | #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ |
170 | #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ | |
1da177e4 LT |
171 | #define ICH6_REG_WAKEEN 0x0c |
172 | #define ICH6_REG_STATESTS 0x0e | |
173 | #define ICH6_REG_GSTS 0x10 | |
b21fadb9 | 174 | #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ |
1da177e4 LT |
175 | #define ICH6_REG_INTCTL 0x20 |
176 | #define ICH6_REG_INTSTS 0x24 | |
e5463720 | 177 | #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ |
1da177e4 LT |
178 | #define ICH6_REG_SYNC 0x34 |
179 | #define ICH6_REG_CORBLBASE 0x40 | |
180 | #define ICH6_REG_CORBUBASE 0x44 | |
181 | #define ICH6_REG_CORBWP 0x48 | |
b21fadb9 TI |
182 | #define ICH6_REG_CORBRP 0x4a |
183 | #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ | |
1da177e4 | 184 | #define ICH6_REG_CORBCTL 0x4c |
b21fadb9 TI |
185 | #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ |
186 | #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ | |
1da177e4 | 187 | #define ICH6_REG_CORBSTS 0x4d |
b21fadb9 | 188 | #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ |
1da177e4 LT |
189 | #define ICH6_REG_CORBSIZE 0x4e |
190 | ||
191 | #define ICH6_REG_RIRBLBASE 0x50 | |
192 | #define ICH6_REG_RIRBUBASE 0x54 | |
193 | #define ICH6_REG_RIRBWP 0x58 | |
b21fadb9 | 194 | #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ |
1da177e4 LT |
195 | #define ICH6_REG_RINTCNT 0x5a |
196 | #define ICH6_REG_RIRBCTL 0x5c | |
b21fadb9 TI |
197 | #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ |
198 | #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ | |
199 | #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ | |
1da177e4 | 200 | #define ICH6_REG_RIRBSTS 0x5d |
b21fadb9 TI |
201 | #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ |
202 | #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ | |
1da177e4 LT |
203 | #define ICH6_REG_RIRBSIZE 0x5e |
204 | ||
205 | #define ICH6_REG_IC 0x60 | |
206 | #define ICH6_REG_IR 0x64 | |
207 | #define ICH6_REG_IRS 0x68 | |
208 | #define ICH6_IRS_VALID (1<<1) | |
209 | #define ICH6_IRS_BUSY (1<<0) | |
210 | ||
211 | #define ICH6_REG_DPLBASE 0x70 | |
212 | #define ICH6_REG_DPUBASE 0x74 | |
213 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
214 | ||
215 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
216 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
217 | ||
218 | /* stream register offsets from stream base */ | |
219 | #define ICH6_REG_SD_CTL 0x00 | |
220 | #define ICH6_REG_SD_STS 0x03 | |
221 | #define ICH6_REG_SD_LPIB 0x04 | |
222 | #define ICH6_REG_SD_CBL 0x08 | |
223 | #define ICH6_REG_SD_LVI 0x0c | |
224 | #define ICH6_REG_SD_FIFOW 0x0e | |
225 | #define ICH6_REG_SD_FIFOSIZE 0x10 | |
226 | #define ICH6_REG_SD_FORMAT 0x12 | |
227 | #define ICH6_REG_SD_BDLPL 0x18 | |
228 | #define ICH6_REG_SD_BDLPU 0x1c | |
229 | ||
230 | /* PCI space */ | |
231 | #define ICH6_PCIREG_TCSEL 0x44 | |
232 | ||
233 | /* | |
234 | * other constants | |
235 | */ | |
236 | ||
237 | /* max number of SDs */ | |
07e4ca50 | 238 | /* ICH, ATI and VIA have 4 playback and 4 capture */ |
07e4ca50 | 239 | #define ICH6_NUM_CAPTURE 4 |
07e4ca50 TI |
240 | #define ICH6_NUM_PLAYBACK 4 |
241 | ||
242 | /* ULI has 6 playback and 5 capture */ | |
07e4ca50 | 243 | #define ULI_NUM_CAPTURE 5 |
07e4ca50 TI |
244 | #define ULI_NUM_PLAYBACK 6 |
245 | ||
778b6e1b | 246 | /* ATI HDMI has 1 playback and 0 capture */ |
778b6e1b | 247 | #define ATIHDMI_NUM_CAPTURE 0 |
778b6e1b FK |
248 | #define ATIHDMI_NUM_PLAYBACK 1 |
249 | ||
f269002e KY |
250 | /* TERA has 4 playback and 3 capture */ |
251 | #define TERA_NUM_CAPTURE 3 | |
252 | #define TERA_NUM_PLAYBACK 4 | |
253 | ||
07e4ca50 TI |
254 | /* this number is statically defined for simplicity */ |
255 | #define MAX_AZX_DEV 16 | |
256 | ||
1da177e4 | 257 | /* max number of fragments - we may use more if allocating more pages for BDL */ |
4ce107b9 TI |
258 | #define BDL_SIZE 4096 |
259 | #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) | |
260 | #define AZX_MAX_FRAG 32 | |
1da177e4 LT |
261 | /* max buffer size - no h/w limit, you can increase as you like */ |
262 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
1da177e4 LT |
263 | |
264 | /* RIRB int mask: overrun[2], response[0] */ | |
265 | #define RIRB_INT_RESPONSE 0x01 | |
266 | #define RIRB_INT_OVERRUN 0x04 | |
267 | #define RIRB_INT_MASK 0x05 | |
268 | ||
2f5983f2 | 269 | /* STATESTS int mask: S3,SD2,SD1,SD0 */ |
7445dfc1 WN |
270 | #define AZX_MAX_CODECS 8 |
271 | #define AZX_DEFAULT_CODECS 4 | |
deadff16 | 272 | #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) |
1da177e4 LT |
273 | |
274 | /* SD_CTL bits */ | |
275 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
276 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
850f0e52 TI |
277 | #define SD_CTL_STRIPE (3 << 16) /* stripe control */ |
278 | #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ | |
279 | #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ | |
1da177e4 LT |
280 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) |
281 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
282 | ||
283 | /* SD_CTL and SD_STS */ | |
284 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
285 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
286 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
d01ce99f TI |
287 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ |
288 | SD_INT_COMPLETE) | |
1da177e4 LT |
289 | |
290 | /* SD_STS */ | |
291 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
292 | ||
293 | /* INTCTL and INTSTS */ | |
d01ce99f TI |
294 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ |
295 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
296 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
1da177e4 | 297 | |
1da177e4 LT |
298 | /* below are so far hardcoded - should read registers in future */ |
299 | #define ICH6_MAX_CORB_ENTRIES 256 | |
300 | #define ICH6_MAX_RIRB_ENTRIES 256 | |
301 | ||
c74db86b TI |
302 | /* position fix mode */ |
303 | enum { | |
0be3b5d3 | 304 | POS_FIX_AUTO, |
d2e1c973 | 305 | POS_FIX_LPIB, |
0be3b5d3 | 306 | POS_FIX_POSBUF, |
c74db86b | 307 | }; |
1da177e4 | 308 | |
f5d40b30 | 309 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
f5d40b30 FL |
310 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
311 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | |
312 | ||
da3fca21 V |
313 | /* Defines for Nvidia HDA support */ |
314 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e | |
315 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f | |
320dcc30 PC |
316 | #define NVIDIA_HDA_ISTRM_COH 0x4d |
317 | #define NVIDIA_HDA_OSTRM_COH 0x4c | |
318 | #define NVIDIA_HDA_ENABLE_COHBIT 0x01 | |
f5d40b30 | 319 | |
90a5ad52 TI |
320 | /* Defines for Intel SCH HDA snoop control */ |
321 | #define INTEL_SCH_HDA_DEVC 0x78 | |
322 | #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) | |
323 | ||
0e153474 JC |
324 | /* Define IN stream 0 FIFO size offset in VIA controller */ |
325 | #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 | |
326 | /* Define VIA HD Audio Device ID*/ | |
327 | #define VIA_HDAC_DEVICE_ID 0x3288 | |
328 | ||
c4da29ca YL |
329 | /* HD Audio class code */ |
330 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 | |
90a5ad52 | 331 | |
1da177e4 LT |
332 | /* |
333 | */ | |
334 | ||
a98f90fd | 335 | struct azx_dev { |
4ce107b9 | 336 | struct snd_dma_buffer bdl; /* BDL buffer */ |
d01ce99f | 337 | u32 *posbuf; /* position buffer pointer */ |
1da177e4 | 338 | |
d01ce99f | 339 | unsigned int bufsize; /* size of the play buffer in bytes */ |
9ad593f6 | 340 | unsigned int period_bytes; /* size of the period in bytes */ |
d01ce99f TI |
341 | unsigned int frags; /* number for period in the play buffer */ |
342 | unsigned int fifo_size; /* FIFO size */ | |
e5463720 JK |
343 | unsigned long start_wallclk; /* start + minimum wallclk */ |
344 | unsigned long period_wallclk; /* wallclk for period */ | |
1da177e4 | 345 | |
d01ce99f | 346 | void __iomem *sd_addr; /* stream descriptor pointer */ |
1da177e4 | 347 | |
d01ce99f | 348 | u32 sd_int_sta_mask; /* stream int status mask */ |
1da177e4 LT |
349 | |
350 | /* pcm support */ | |
d01ce99f TI |
351 | struct snd_pcm_substream *substream; /* assigned substream, |
352 | * set in PCM open | |
353 | */ | |
354 | unsigned int format_val; /* format value to be set in the | |
355 | * controller and the codec | |
356 | */ | |
1da177e4 LT |
357 | unsigned char stream_tag; /* assigned stream */ |
358 | unsigned char index; /* stream index */ | |
ef18bede | 359 | int device; /* last device number assigned to */ |
1da177e4 | 360 | |
927fc866 PM |
361 | unsigned int opened :1; |
362 | unsigned int running :1; | |
675f25d4 | 363 | unsigned int irq_pending :1; |
0e153474 JC |
364 | /* |
365 | * For VIA: | |
366 | * A flag to ensure DMA position is 0 | |
367 | * when link position is not greater than FIFO size | |
368 | */ | |
369 | unsigned int insufficient :1; | |
1da177e4 LT |
370 | }; |
371 | ||
372 | /* CORB/RIRB */ | |
a98f90fd | 373 | struct azx_rb { |
1da177e4 LT |
374 | u32 *buf; /* CORB/RIRB buffer |
375 | * Each CORB entry is 4byte, RIRB is 8byte | |
376 | */ | |
377 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
378 | /* for RIRB */ | |
379 | unsigned short rp, wp; /* read/write pointers */ | |
deadff16 WF |
380 | int cmds[AZX_MAX_CODECS]; /* number of pending requests */ |
381 | u32 res[AZX_MAX_CODECS]; /* last read value */ | |
1da177e4 LT |
382 | }; |
383 | ||
a98f90fd TI |
384 | struct azx { |
385 | struct snd_card *card; | |
1da177e4 | 386 | struct pci_dev *pci; |
555e219f | 387 | int dev_index; |
1da177e4 | 388 | |
07e4ca50 TI |
389 | /* chip type specific */ |
390 | int driver_type; | |
391 | int playback_streams; | |
392 | int playback_index_offset; | |
393 | int capture_streams; | |
394 | int capture_index_offset; | |
395 | int num_streams; | |
396 | ||
1da177e4 LT |
397 | /* pci resources */ |
398 | unsigned long addr; | |
399 | void __iomem *remap_addr; | |
400 | int irq; | |
401 | ||
402 | /* locks */ | |
403 | spinlock_t reg_lock; | |
62932df8 | 404 | struct mutex open_mutex; |
1da177e4 | 405 | |
07e4ca50 | 406 | /* streams (x num_streams) */ |
a98f90fd | 407 | struct azx_dev *azx_dev; |
1da177e4 LT |
408 | |
409 | /* PCM */ | |
c8936222 | 410 | struct snd_pcm *pcm[HDA_MAX_PCMS]; |
1da177e4 LT |
411 | |
412 | /* HD codec */ | |
413 | unsigned short codec_mask; | |
f1eaaeec | 414 | int codec_probe_mask; /* copied from probe_mask option */ |
1da177e4 | 415 | struct hda_bus *bus; |
2dca0bba | 416 | unsigned int beep_mode; |
1da177e4 LT |
417 | |
418 | /* CORB/RIRB */ | |
a98f90fd TI |
419 | struct azx_rb corb; |
420 | struct azx_rb rirb; | |
1da177e4 | 421 | |
4ce107b9 | 422 | /* CORB/RIRB and position buffers */ |
1da177e4 LT |
423 | struct snd_dma_buffer rb; |
424 | struct snd_dma_buffer posbuf; | |
c74db86b TI |
425 | |
426 | /* flags */ | |
beaffc39 | 427 | int position_fix[2]; /* for both playback/capture streams */ |
1eb6dc7d | 428 | int poll_count; |
cb53c626 | 429 | unsigned int running :1; |
927fc866 PM |
430 | unsigned int initialized :1; |
431 | unsigned int single_cmd :1; | |
432 | unsigned int polling_mode :1; | |
68e7fffc | 433 | unsigned int msi :1; |
a6a950a8 | 434 | unsigned int irq_pending_warned :1; |
0e153474 | 435 | unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */ |
6ce4a3bc | 436 | unsigned int probing :1; /* codec probing phase */ |
43bbb6cc TI |
437 | |
438 | /* for debugging */ | |
feb27340 | 439 | unsigned int last_cmd[AZX_MAX_CODECS]; |
9ad593f6 TI |
440 | |
441 | /* for pending irqs */ | |
442 | struct work_struct irq_pending_work; | |
0cbf0098 TI |
443 | |
444 | /* reboot notifier (for mysterious hangup problem at power-down) */ | |
445 | struct notifier_block reboot_notifier; | |
1da177e4 LT |
446 | }; |
447 | ||
07e4ca50 TI |
448 | /* driver types */ |
449 | enum { | |
450 | AZX_DRIVER_ICH, | |
32679f95 | 451 | AZX_DRIVER_PCH, |
4979bca9 | 452 | AZX_DRIVER_SCH, |
07e4ca50 | 453 | AZX_DRIVER_ATI, |
778b6e1b | 454 | AZX_DRIVER_ATIHDMI, |
07e4ca50 TI |
455 | AZX_DRIVER_VIA, |
456 | AZX_DRIVER_SIS, | |
457 | AZX_DRIVER_ULI, | |
da3fca21 | 458 | AZX_DRIVER_NVIDIA, |
f269002e | 459 | AZX_DRIVER_TERA, |
c4da29ca | 460 | AZX_DRIVER_GENERIC, |
2f5983f2 | 461 | AZX_NUM_DRIVERS, /* keep this as last entry */ |
07e4ca50 TI |
462 | }; |
463 | ||
464 | static char *driver_short_names[] __devinitdata = { | |
465 | [AZX_DRIVER_ICH] = "HDA Intel", | |
32679f95 | 466 | [AZX_DRIVER_PCH] = "HDA Intel PCH", |
4979bca9 | 467 | [AZX_DRIVER_SCH] = "HDA Intel MID", |
07e4ca50 | 468 | [AZX_DRIVER_ATI] = "HDA ATI SB", |
778b6e1b | 469 | [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", |
07e4ca50 TI |
470 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", |
471 | [AZX_DRIVER_SIS] = "HDA SIS966", | |
da3fca21 V |
472 | [AZX_DRIVER_ULI] = "HDA ULI M5461", |
473 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", | |
f269002e | 474 | [AZX_DRIVER_TERA] = "HDA Teradici", |
c4da29ca | 475 | [AZX_DRIVER_GENERIC] = "HD-Audio Generic", |
07e4ca50 TI |
476 | }; |
477 | ||
1da177e4 LT |
478 | /* |
479 | * macros for easy use | |
480 | */ | |
481 | #define azx_writel(chip,reg,value) \ | |
482 | writel(value, (chip)->remap_addr + ICH6_REG_##reg) | |
483 | #define azx_readl(chip,reg) \ | |
484 | readl((chip)->remap_addr + ICH6_REG_##reg) | |
485 | #define azx_writew(chip,reg,value) \ | |
486 | writew(value, (chip)->remap_addr + ICH6_REG_##reg) | |
487 | #define azx_readw(chip,reg) \ | |
488 | readw((chip)->remap_addr + ICH6_REG_##reg) | |
489 | #define azx_writeb(chip,reg,value) \ | |
490 | writeb(value, (chip)->remap_addr + ICH6_REG_##reg) | |
491 | #define azx_readb(chip,reg) \ | |
492 | readb((chip)->remap_addr + ICH6_REG_##reg) | |
493 | ||
494 | #define azx_sd_writel(dev,reg,value) \ | |
495 | writel(value, (dev)->sd_addr + ICH6_REG_##reg) | |
496 | #define azx_sd_readl(dev,reg) \ | |
497 | readl((dev)->sd_addr + ICH6_REG_##reg) | |
498 | #define azx_sd_writew(dev,reg,value) \ | |
499 | writew(value, (dev)->sd_addr + ICH6_REG_##reg) | |
500 | #define azx_sd_readw(dev,reg) \ | |
501 | readw((dev)->sd_addr + ICH6_REG_##reg) | |
502 | #define azx_sd_writeb(dev,reg,value) \ | |
503 | writeb(value, (dev)->sd_addr + ICH6_REG_##reg) | |
504 | #define azx_sd_readb(dev,reg) \ | |
505 | readb((dev)->sd_addr + ICH6_REG_##reg) | |
506 | ||
507 | /* for pcm support */ | |
a98f90fd | 508 | #define get_azx_dev(substream) (substream->runtime->private_data) |
1da177e4 | 509 | |
68e7fffc | 510 | static int azx_acquire_irq(struct azx *chip, int do_disconnect); |
1eb6dc7d | 511 | static int azx_send_cmd(struct hda_bus *bus, unsigned int val); |
1da177e4 LT |
512 | /* |
513 | * Interface for HD codec | |
514 | */ | |
515 | ||
1da177e4 LT |
516 | /* |
517 | * CORB / RIRB interface | |
518 | */ | |
a98f90fd | 519 | static int azx_alloc_cmd_io(struct azx *chip) |
1da177e4 LT |
520 | { |
521 | int err; | |
522 | ||
523 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
d01ce99f TI |
524 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, |
525 | snd_dma_pci_data(chip->pci), | |
1da177e4 LT |
526 | PAGE_SIZE, &chip->rb); |
527 | if (err < 0) { | |
528 | snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); | |
529 | return err; | |
530 | } | |
531 | return 0; | |
532 | } | |
533 | ||
a98f90fd | 534 | static void azx_init_cmd_io(struct azx *chip) |
1da177e4 | 535 | { |
cdb1fbf2 | 536 | spin_lock_irq(&chip->reg_lock); |
1da177e4 LT |
537 | /* CORB set up */ |
538 | chip->corb.addr = chip->rb.addr; | |
539 | chip->corb.buf = (u32 *)chip->rb.area; | |
540 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | |
766979e0 | 541 | azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); |
1da177e4 | 542 | |
07e4ca50 TI |
543 | /* set the corb size to 256 entries (ULI requires explicitly) */ |
544 | azx_writeb(chip, CORBSIZE, 0x02); | |
1da177e4 LT |
545 | /* set the corb write pointer to 0 */ |
546 | azx_writew(chip, CORBWP, 0); | |
547 | /* reset the corb hw read pointer */ | |
b21fadb9 | 548 | azx_writew(chip, CORBRP, ICH6_CORBRP_RST); |
1da177e4 | 549 | /* enable corb dma */ |
b21fadb9 | 550 | azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); |
1da177e4 LT |
551 | |
552 | /* RIRB set up */ | |
553 | chip->rirb.addr = chip->rb.addr + 2048; | |
554 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | |
deadff16 WF |
555 | chip->rirb.wp = chip->rirb.rp = 0; |
556 | memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); | |
1da177e4 | 557 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); |
766979e0 | 558 | azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); |
1da177e4 | 559 | |
07e4ca50 TI |
560 | /* set the rirb size to 256 entries (ULI requires explicitly) */ |
561 | azx_writeb(chip, RIRBSIZE, 0x02); | |
1da177e4 | 562 | /* reset the rirb hw write pointer */ |
b21fadb9 | 563 | azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); |
1da177e4 LT |
564 | /* set N=1, get RIRB response interrupt for new entry */ |
565 | azx_writew(chip, RINTCNT, 1); | |
566 | /* enable rirb dma and response irq */ | |
1da177e4 | 567 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); |
cdb1fbf2 | 568 | spin_unlock_irq(&chip->reg_lock); |
1da177e4 LT |
569 | } |
570 | ||
a98f90fd | 571 | static void azx_free_cmd_io(struct azx *chip) |
1da177e4 | 572 | { |
cdb1fbf2 | 573 | spin_lock_irq(&chip->reg_lock); |
1da177e4 LT |
574 | /* disable ringbuffer DMAs */ |
575 | azx_writeb(chip, RIRBCTL, 0); | |
576 | azx_writeb(chip, CORBCTL, 0); | |
cdb1fbf2 | 577 | spin_unlock_irq(&chip->reg_lock); |
1da177e4 LT |
578 | } |
579 | ||
deadff16 WF |
580 | static unsigned int azx_command_addr(u32 cmd) |
581 | { | |
582 | unsigned int addr = cmd >> 28; | |
583 | ||
584 | if (addr >= AZX_MAX_CODECS) { | |
585 | snd_BUG(); | |
586 | addr = 0; | |
587 | } | |
588 | ||
589 | return addr; | |
590 | } | |
591 | ||
592 | static unsigned int azx_response_addr(u32 res) | |
593 | { | |
594 | unsigned int addr = res & 0xf; | |
595 | ||
596 | if (addr >= AZX_MAX_CODECS) { | |
597 | snd_BUG(); | |
598 | addr = 0; | |
599 | } | |
600 | ||
601 | return addr; | |
1da177e4 LT |
602 | } |
603 | ||
604 | /* send a command */ | |
33fa35ed | 605 | static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) |
1da177e4 | 606 | { |
33fa35ed | 607 | struct azx *chip = bus->private_data; |
deadff16 | 608 | unsigned int addr = azx_command_addr(val); |
1da177e4 | 609 | unsigned int wp; |
1da177e4 | 610 | |
c32649fe WF |
611 | spin_lock_irq(&chip->reg_lock); |
612 | ||
1da177e4 LT |
613 | /* add command to corb */ |
614 | wp = azx_readb(chip, CORBWP); | |
615 | wp++; | |
616 | wp %= ICH6_MAX_CORB_ENTRIES; | |
617 | ||
deadff16 | 618 | chip->rirb.cmds[addr]++; |
1da177e4 LT |
619 | chip->corb.buf[wp] = cpu_to_le32(val); |
620 | azx_writel(chip, CORBWP, wp); | |
c32649fe | 621 | |
1da177e4 LT |
622 | spin_unlock_irq(&chip->reg_lock); |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | |
628 | ||
629 | /* retrieve RIRB entry - called from interrupt handler */ | |
a98f90fd | 630 | static void azx_update_rirb(struct azx *chip) |
1da177e4 LT |
631 | { |
632 | unsigned int rp, wp; | |
deadff16 | 633 | unsigned int addr; |
1da177e4 LT |
634 | u32 res, res_ex; |
635 | ||
636 | wp = azx_readb(chip, RIRBWP); | |
637 | if (wp == chip->rirb.wp) | |
638 | return; | |
639 | chip->rirb.wp = wp; | |
deadff16 | 640 | |
1da177e4 LT |
641 | while (chip->rirb.rp != wp) { |
642 | chip->rirb.rp++; | |
643 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | |
644 | ||
645 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
646 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | |
647 | res = le32_to_cpu(chip->rirb.buf[rp]); | |
deadff16 | 648 | addr = azx_response_addr(res_ex); |
1da177e4 LT |
649 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) |
650 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | |
deadff16 WF |
651 | else if (chip->rirb.cmds[addr]) { |
652 | chip->rirb.res[addr] = res; | |
2add9b92 | 653 | smp_wmb(); |
deadff16 | 654 | chip->rirb.cmds[addr]--; |
e310bb06 WF |
655 | } else |
656 | snd_printk(KERN_ERR SFX "spurious response %#x:%#x, " | |
657 | "last cmd=%#08x\n", | |
658 | res, res_ex, | |
659 | chip->last_cmd[addr]); | |
1da177e4 LT |
660 | } |
661 | } | |
662 | ||
663 | /* receive a response */ | |
deadff16 WF |
664 | static unsigned int azx_rirb_get_response(struct hda_bus *bus, |
665 | unsigned int addr) | |
1da177e4 | 666 | { |
33fa35ed | 667 | struct azx *chip = bus->private_data; |
5c79b1f8 | 668 | unsigned long timeout; |
1eb6dc7d | 669 | int do_poll = 0; |
1da177e4 | 670 | |
5c79b1f8 TI |
671 | again: |
672 | timeout = jiffies + msecs_to_jiffies(1000); | |
28a0d9df | 673 | for (;;) { |
1eb6dc7d | 674 | if (chip->polling_mode || do_poll) { |
e96224ae TI |
675 | spin_lock_irq(&chip->reg_lock); |
676 | azx_update_rirb(chip); | |
677 | spin_unlock_irq(&chip->reg_lock); | |
678 | } | |
deadff16 | 679 | if (!chip->rirb.cmds[addr]) { |
2add9b92 | 680 | smp_rmb(); |
b613291f | 681 | bus->rirb_error = 0; |
1eb6dc7d ML |
682 | |
683 | if (!do_poll) | |
684 | chip->poll_count = 0; | |
deadff16 | 685 | return chip->rirb.res[addr]; /* the last value */ |
2add9b92 | 686 | } |
28a0d9df TI |
687 | if (time_after(jiffies, timeout)) |
688 | break; | |
33fa35ed | 689 | if (bus->needs_damn_long_delay) |
52987656 TI |
690 | msleep(2); /* temporary workaround */ |
691 | else { | |
692 | udelay(10); | |
693 | cond_resched(); | |
694 | } | |
28a0d9df | 695 | } |
5c79b1f8 | 696 | |
1eb6dc7d ML |
697 | if (!chip->polling_mode && chip->poll_count < 2) { |
698 | snd_printdd(SFX "azx_get_response timeout, " | |
699 | "polling the codec once: last cmd=0x%08x\n", | |
700 | chip->last_cmd[addr]); | |
701 | do_poll = 1; | |
702 | chip->poll_count++; | |
703 | goto again; | |
704 | } | |
705 | ||
706 | ||
23c4a881 TI |
707 | if (!chip->polling_mode) { |
708 | snd_printk(KERN_WARNING SFX "azx_get_response timeout, " | |
709 | "switching to polling mode: last cmd=0x%08x\n", | |
710 | chip->last_cmd[addr]); | |
711 | chip->polling_mode = 1; | |
712 | goto again; | |
713 | } | |
714 | ||
68e7fffc | 715 | if (chip->msi) { |
4abc1cc2 | 716 | snd_printk(KERN_WARNING SFX "No response from codec, " |
feb27340 WF |
717 | "disabling MSI: last cmd=0x%08x\n", |
718 | chip->last_cmd[addr]); | |
68e7fffc TI |
719 | free_irq(chip->irq, chip); |
720 | chip->irq = -1; | |
721 | pci_disable_msi(chip->pci); | |
722 | chip->msi = 0; | |
b613291f TI |
723 | if (azx_acquire_irq(chip, 1) < 0) { |
724 | bus->rirb_error = 1; | |
68e7fffc | 725 | return -1; |
b613291f | 726 | } |
68e7fffc TI |
727 | goto again; |
728 | } | |
729 | ||
6ce4a3bc TI |
730 | if (chip->probing) { |
731 | /* If this critical timeout happens during the codec probing | |
732 | * phase, this is likely an access to a non-existing codec | |
733 | * slot. Better to return an error and reset the system. | |
734 | */ | |
735 | return -1; | |
736 | } | |
737 | ||
8dd78330 TI |
738 | /* a fatal communication error; need either to reset or to fallback |
739 | * to the single_cmd mode | |
740 | */ | |
b613291f | 741 | bus->rirb_error = 1; |
b20f3b83 | 742 | if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { |
8dd78330 TI |
743 | bus->response_reset = 1; |
744 | return -1; /* give a chance to retry */ | |
745 | } | |
746 | ||
747 | snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " | |
748 | "switching to single_cmd mode: last cmd=0x%08x\n", | |
feb27340 | 749 | chip->last_cmd[addr]); |
8dd78330 TI |
750 | chip->single_cmd = 1; |
751 | bus->response_reset = 0; | |
1a696978 | 752 | /* release CORB/RIRB */ |
4fcd3920 | 753 | azx_free_cmd_io(chip); |
1a696978 TI |
754 | /* disable unsolicited responses */ |
755 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); | |
5c79b1f8 | 756 | return -1; |
1da177e4 LT |
757 | } |
758 | ||
1da177e4 LT |
759 | /* |
760 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
761 | * | |
762 | * Note: according to Intel, this is not preferred use. The command was | |
763 | * intended for the BIOS only, and may get confused with unsolicited | |
764 | * responses. So, we shouldn't use it for normal operation from the | |
765 | * driver. | |
766 | * I left the codes, however, for debugging/testing purposes. | |
767 | */ | |
768 | ||
b05a7d4f | 769 | /* receive a response */ |
deadff16 | 770 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) |
b05a7d4f TI |
771 | { |
772 | int timeout = 50; | |
773 | ||
774 | while (timeout--) { | |
775 | /* check IRV busy bit */ | |
776 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { | |
777 | /* reuse rirb.res as the response return value */ | |
deadff16 | 778 | chip->rirb.res[addr] = azx_readl(chip, IR); |
b05a7d4f TI |
779 | return 0; |
780 | } | |
781 | udelay(1); | |
782 | } | |
783 | if (printk_ratelimit()) | |
784 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", | |
785 | azx_readw(chip, IRS)); | |
deadff16 | 786 | chip->rirb.res[addr] = -1; |
b05a7d4f TI |
787 | return -EIO; |
788 | } | |
789 | ||
1da177e4 | 790 | /* send a command */ |
33fa35ed | 791 | static int azx_single_send_cmd(struct hda_bus *bus, u32 val) |
1da177e4 | 792 | { |
33fa35ed | 793 | struct azx *chip = bus->private_data; |
deadff16 | 794 | unsigned int addr = azx_command_addr(val); |
1da177e4 LT |
795 | int timeout = 50; |
796 | ||
8dd78330 | 797 | bus->rirb_error = 0; |
1da177e4 LT |
798 | while (timeout--) { |
799 | /* check ICB busy bit */ | |
d01ce99f | 800 | if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { |
1da177e4 | 801 | /* Clear IRV valid bit */ |
d01ce99f TI |
802 | azx_writew(chip, IRS, azx_readw(chip, IRS) | |
803 | ICH6_IRS_VALID); | |
1da177e4 | 804 | azx_writel(chip, IC, val); |
d01ce99f TI |
805 | azx_writew(chip, IRS, azx_readw(chip, IRS) | |
806 | ICH6_IRS_BUSY); | |
deadff16 | 807 | return azx_single_wait_for_response(chip, addr); |
1da177e4 LT |
808 | } |
809 | udelay(1); | |
810 | } | |
1cfd52bc MB |
811 | if (printk_ratelimit()) |
812 | snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", | |
813 | azx_readw(chip, IRS), val); | |
1da177e4 LT |
814 | return -EIO; |
815 | } | |
816 | ||
817 | /* receive a response */ | |
deadff16 WF |
818 | static unsigned int azx_single_get_response(struct hda_bus *bus, |
819 | unsigned int addr) | |
1da177e4 | 820 | { |
33fa35ed | 821 | struct azx *chip = bus->private_data; |
deadff16 | 822 | return chip->rirb.res[addr]; |
1da177e4 LT |
823 | } |
824 | ||
111d3af5 TI |
825 | /* |
826 | * The below are the main callbacks from hda_codec. | |
827 | * | |
828 | * They are just the skeleton to call sub-callbacks according to the | |
829 | * current setting of chip->single_cmd. | |
830 | */ | |
831 | ||
832 | /* send a command */ | |
33fa35ed | 833 | static int azx_send_cmd(struct hda_bus *bus, unsigned int val) |
111d3af5 | 834 | { |
33fa35ed | 835 | struct azx *chip = bus->private_data; |
43bbb6cc | 836 | |
feb27340 | 837 | chip->last_cmd[azx_command_addr(val)] = val; |
111d3af5 | 838 | if (chip->single_cmd) |
33fa35ed | 839 | return azx_single_send_cmd(bus, val); |
111d3af5 | 840 | else |
33fa35ed | 841 | return azx_corb_send_cmd(bus, val); |
111d3af5 TI |
842 | } |
843 | ||
844 | /* get a response */ | |
deadff16 WF |
845 | static unsigned int azx_get_response(struct hda_bus *bus, |
846 | unsigned int addr) | |
111d3af5 | 847 | { |
33fa35ed | 848 | struct azx *chip = bus->private_data; |
111d3af5 | 849 | if (chip->single_cmd) |
deadff16 | 850 | return azx_single_get_response(bus, addr); |
111d3af5 | 851 | else |
deadff16 | 852 | return azx_rirb_get_response(bus, addr); |
111d3af5 TI |
853 | } |
854 | ||
cb53c626 | 855 | #ifdef CONFIG_SND_HDA_POWER_SAVE |
33fa35ed | 856 | static void azx_power_notify(struct hda_bus *bus); |
cb53c626 | 857 | #endif |
111d3af5 | 858 | |
1da177e4 | 859 | /* reset codec link */ |
cd508fe5 | 860 | static int azx_reset(struct azx *chip, int full_reset) |
1da177e4 LT |
861 | { |
862 | int count; | |
863 | ||
cd508fe5 JK |
864 | if (!full_reset) |
865 | goto __skip; | |
866 | ||
e8a7f136 DT |
867 | /* clear STATESTS */ |
868 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); | |
869 | ||
1da177e4 LT |
870 | /* reset controller */ |
871 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | |
872 | ||
873 | count = 50; | |
874 | while (azx_readb(chip, GCTL) && --count) | |
875 | msleep(1); | |
876 | ||
877 | /* delay for >= 100us for codec PLL to settle per spec | |
878 | * Rev 0.9 section 5.5.1 | |
879 | */ | |
880 | msleep(1); | |
881 | ||
882 | /* Bring controller out of reset */ | |
883 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | |
884 | ||
885 | count = 50; | |
927fc866 | 886 | while (!azx_readb(chip, GCTL) && --count) |
1da177e4 LT |
887 | msleep(1); |
888 | ||
927fc866 | 889 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ |
1da177e4 LT |
890 | msleep(1); |
891 | ||
cd508fe5 | 892 | __skip: |
1da177e4 | 893 | /* check to see if controller is ready */ |
927fc866 | 894 | if (!azx_readb(chip, GCTL)) { |
4abc1cc2 | 895 | snd_printd(SFX "azx_reset: controller not ready!\n"); |
1da177e4 LT |
896 | return -EBUSY; |
897 | } | |
898 | ||
41e2fce4 | 899 | /* Accept unsolicited responses */ |
1a696978 TI |
900 | if (!chip->single_cmd) |
901 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | | |
902 | ICH6_GCTL_UNSOL); | |
41e2fce4 | 903 | |
1da177e4 | 904 | /* detect codecs */ |
927fc866 | 905 | if (!chip->codec_mask) { |
1da177e4 | 906 | chip->codec_mask = azx_readw(chip, STATESTS); |
4abc1cc2 | 907 | snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask); |
1da177e4 LT |
908 | } |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
913 | ||
914 | /* | |
915 | * Lowlevel interface | |
916 | */ | |
917 | ||
918 | /* enable interrupts */ | |
a98f90fd | 919 | static void azx_int_enable(struct azx *chip) |
1da177e4 LT |
920 | { |
921 | /* enable controller CIE and GIE */ | |
922 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | |
923 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | |
924 | } | |
925 | ||
926 | /* disable interrupts */ | |
a98f90fd | 927 | static void azx_int_disable(struct azx *chip) |
1da177e4 LT |
928 | { |
929 | int i; | |
930 | ||
931 | /* disable interrupts in stream descriptor */ | |
07e4ca50 | 932 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 933 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
934 | azx_sd_writeb(azx_dev, SD_CTL, |
935 | azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); | |
936 | } | |
937 | ||
938 | /* disable SIE for all streams */ | |
939 | azx_writeb(chip, INTCTL, 0); | |
940 | ||
941 | /* disable controller CIE and GIE */ | |
942 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | |
943 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | |
944 | } | |
945 | ||
946 | /* clear interrupts */ | |
a98f90fd | 947 | static void azx_int_clear(struct azx *chip) |
1da177e4 LT |
948 | { |
949 | int i; | |
950 | ||
951 | /* clear stream status */ | |
07e4ca50 | 952 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 953 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
954 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
955 | } | |
956 | ||
957 | /* clear STATESTS */ | |
958 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); | |
959 | ||
960 | /* clear rirb status */ | |
961 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
962 | ||
963 | /* clear int status */ | |
964 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | |
965 | } | |
966 | ||
967 | /* start a stream */ | |
a98f90fd | 968 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 | 969 | { |
0e153474 JC |
970 | /* |
971 | * Before stream start, initialize parameter | |
972 | */ | |
973 | azx_dev->insufficient = 1; | |
974 | ||
1da177e4 | 975 | /* enable SIE */ |
ccc5df05 WN |
976 | azx_writel(chip, INTCTL, |
977 | azx_readl(chip, INTCTL) | (1 << azx_dev->index)); | |
1da177e4 LT |
978 | /* set DMA start and interrupt mask */ |
979 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | | |
980 | SD_CTL_DMA_START | SD_INT_MASK); | |
981 | } | |
982 | ||
1dddab40 TI |
983 | /* stop DMA */ |
984 | static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) | |
1da177e4 | 985 | { |
1da177e4 LT |
986 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & |
987 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
988 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
1dddab40 TI |
989 | } |
990 | ||
991 | /* stop a stream */ | |
992 | static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) | |
993 | { | |
994 | azx_stream_clear(chip, azx_dev); | |
1da177e4 | 995 | /* disable SIE */ |
ccc5df05 WN |
996 | azx_writel(chip, INTCTL, |
997 | azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); | |
1da177e4 LT |
998 | } |
999 | ||
1000 | ||
1001 | /* | |
cb53c626 | 1002 | * reset and start the controller registers |
1da177e4 | 1003 | */ |
cd508fe5 | 1004 | static void azx_init_chip(struct azx *chip, int full_reset) |
1da177e4 | 1005 | { |
cb53c626 TI |
1006 | if (chip->initialized) |
1007 | return; | |
1da177e4 LT |
1008 | |
1009 | /* reset controller */ | |
cd508fe5 | 1010 | azx_reset(chip, full_reset); |
1da177e4 LT |
1011 | |
1012 | /* initialize interrupts */ | |
1013 | azx_int_clear(chip); | |
1014 | azx_int_enable(chip); | |
1015 | ||
1016 | /* initialize the codec command I/O */ | |
1a696978 TI |
1017 | if (!chip->single_cmd) |
1018 | azx_init_cmd_io(chip); | |
1da177e4 | 1019 | |
0be3b5d3 TI |
1020 | /* program the position buffer */ |
1021 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | |
766979e0 | 1022 | azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); |
f5d40b30 | 1023 | |
cb53c626 TI |
1024 | chip->initialized = 1; |
1025 | } | |
1026 | ||
1027 | /* | |
1028 | * initialize the PCI registers | |
1029 | */ | |
1030 | /* update bits in a PCI register byte */ | |
1031 | static void update_pci_byte(struct pci_dev *pci, unsigned int reg, | |
1032 | unsigned char mask, unsigned char val) | |
1033 | { | |
1034 | unsigned char data; | |
1035 | ||
1036 | pci_read_config_byte(pci, reg, &data); | |
1037 | data &= ~mask; | |
1038 | data |= (val & mask); | |
1039 | pci_write_config_byte(pci, reg, data); | |
1040 | } | |
1041 | ||
1042 | static void azx_init_pci(struct azx *chip) | |
1043 | { | |
90a5ad52 TI |
1044 | unsigned short snoop; |
1045 | ||
cb53c626 TI |
1046 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) |
1047 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
1048 | * Ensuring these bits are 0 clears playback static on some HD Audio | |
1049 | * codecs | |
1050 | */ | |
1051 | update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); | |
1052 | ||
da3fca21 V |
1053 | switch (chip->driver_type) { |
1054 | case AZX_DRIVER_ATI: | |
1055 | /* For ATI SB450 azalia HD audio, we need to enable snoop */ | |
cb53c626 TI |
1056 | update_pci_byte(chip->pci, |
1057 | ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, | |
1058 | 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP); | |
da3fca21 V |
1059 | break; |
1060 | case AZX_DRIVER_NVIDIA: | |
1061 | /* For NVIDIA HDA, enable snoop */ | |
cb53c626 TI |
1062 | update_pci_byte(chip->pci, |
1063 | NVIDIA_HDA_TRANSREG_ADDR, | |
1064 | 0x0f, NVIDIA_HDA_ENABLE_COHBITS); | |
320dcc30 PC |
1065 | update_pci_byte(chip->pci, |
1066 | NVIDIA_HDA_ISTRM_COH, | |
1067 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | |
1068 | update_pci_byte(chip->pci, | |
1069 | NVIDIA_HDA_OSTRM_COH, | |
1070 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | |
da3fca21 | 1071 | break; |
90a5ad52 | 1072 | case AZX_DRIVER_SCH: |
32679f95 | 1073 | case AZX_DRIVER_PCH: |
90a5ad52 TI |
1074 | pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); |
1075 | if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) { | |
4abc1cc2 | 1076 | pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, |
90a5ad52 TI |
1077 | snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP)); |
1078 | pci_read_config_word(chip->pci, | |
1079 | INTEL_SCH_HDA_DEVC, &snoop); | |
4abc1cc2 TI |
1080 | snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n", |
1081 | (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) | |
90a5ad52 TI |
1082 | ? "Failed" : "OK"); |
1083 | } | |
1084 | break; | |
1085 | ||
da3fca21 | 1086 | } |
1da177e4 LT |
1087 | } |
1088 | ||
1089 | ||
9ad593f6 TI |
1090 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); |
1091 | ||
1da177e4 LT |
1092 | /* |
1093 | * interrupt handler | |
1094 | */ | |
7d12e780 | 1095 | static irqreturn_t azx_interrupt(int irq, void *dev_id) |
1da177e4 | 1096 | { |
a98f90fd TI |
1097 | struct azx *chip = dev_id; |
1098 | struct azx_dev *azx_dev; | |
1da177e4 | 1099 | u32 status; |
fa00e046 | 1100 | int i, ok; |
1da177e4 LT |
1101 | |
1102 | spin_lock(&chip->reg_lock); | |
1103 | ||
1104 | status = azx_readl(chip, INTSTS); | |
1105 | if (status == 0) { | |
1106 | spin_unlock(&chip->reg_lock); | |
1107 | return IRQ_NONE; | |
1108 | } | |
1109 | ||
07e4ca50 | 1110 | for (i = 0; i < chip->num_streams; i++) { |
1da177e4 LT |
1111 | azx_dev = &chip->azx_dev[i]; |
1112 | if (status & azx_dev->sd_int_sta_mask) { | |
1113 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
9ad593f6 TI |
1114 | if (!azx_dev->substream || !azx_dev->running) |
1115 | continue; | |
1116 | /* check whether this IRQ is really acceptable */ | |
fa00e046 JK |
1117 | ok = azx_position_ok(chip, azx_dev); |
1118 | if (ok == 1) { | |
9ad593f6 | 1119 | azx_dev->irq_pending = 0; |
1da177e4 LT |
1120 | spin_unlock(&chip->reg_lock); |
1121 | snd_pcm_period_elapsed(azx_dev->substream); | |
1122 | spin_lock(&chip->reg_lock); | |
fa00e046 | 1123 | } else if (ok == 0 && chip->bus && chip->bus->workq) { |
9ad593f6 TI |
1124 | /* bogus IRQ, process it later */ |
1125 | azx_dev->irq_pending = 1; | |
6acaed38 TI |
1126 | queue_work(chip->bus->workq, |
1127 | &chip->irq_pending_work); | |
1da177e4 LT |
1128 | } |
1129 | } | |
1130 | } | |
1131 | ||
1132 | /* clear rirb int */ | |
1133 | status = azx_readb(chip, RIRBSTS); | |
1134 | if (status & RIRB_INT_MASK) { | |
81740861 | 1135 | if (status & RIRB_INT_RESPONSE) |
1da177e4 LT |
1136 | azx_update_rirb(chip); |
1137 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
1138 | } | |
1139 | ||
1140 | #if 0 | |
1141 | /* clear state status int */ | |
1142 | if (azx_readb(chip, STATESTS) & 0x04) | |
1143 | azx_writeb(chip, STATESTS, 0x04); | |
1144 | #endif | |
1145 | spin_unlock(&chip->reg_lock); | |
1146 | ||
1147 | return IRQ_HANDLED; | |
1148 | } | |
1149 | ||
1150 | ||
675f25d4 TI |
1151 | /* |
1152 | * set up a BDL entry | |
1153 | */ | |
1154 | static int setup_bdle(struct snd_pcm_substream *substream, | |
1155 | struct azx_dev *azx_dev, u32 **bdlp, | |
1156 | int ofs, int size, int with_ioc) | |
1157 | { | |
675f25d4 TI |
1158 | u32 *bdl = *bdlp; |
1159 | ||
1160 | while (size > 0) { | |
1161 | dma_addr_t addr; | |
1162 | int chunk; | |
1163 | ||
1164 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | |
1165 | return -EINVAL; | |
1166 | ||
77a23f26 | 1167 | addr = snd_pcm_sgbuf_get_addr(substream, ofs); |
675f25d4 TI |
1168 | /* program the address field of the BDL entry */ |
1169 | bdl[0] = cpu_to_le32((u32)addr); | |
766979e0 | 1170 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); |
675f25d4 | 1171 | /* program the size field of the BDL entry */ |
fc4abee8 | 1172 | chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size); |
675f25d4 TI |
1173 | bdl[2] = cpu_to_le32(chunk); |
1174 | /* program the IOC to enable interrupt | |
1175 | * only when the whole fragment is processed | |
1176 | */ | |
1177 | size -= chunk; | |
1178 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | |
1179 | bdl += 4; | |
1180 | azx_dev->frags++; | |
1181 | ofs += chunk; | |
1182 | } | |
1183 | *bdlp = bdl; | |
1184 | return ofs; | |
1185 | } | |
1186 | ||
1da177e4 LT |
1187 | /* |
1188 | * set up BDL entries | |
1189 | */ | |
555e219f TI |
1190 | static int azx_setup_periods(struct azx *chip, |
1191 | struct snd_pcm_substream *substream, | |
4ce107b9 | 1192 | struct azx_dev *azx_dev) |
1da177e4 | 1193 | { |
4ce107b9 TI |
1194 | u32 *bdl; |
1195 | int i, ofs, periods, period_bytes; | |
555e219f | 1196 | int pos_adj; |
1da177e4 LT |
1197 | |
1198 | /* reset BDL address */ | |
1199 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
1200 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
1201 | ||
97b71c94 | 1202 | period_bytes = azx_dev->period_bytes; |
4ce107b9 TI |
1203 | periods = azx_dev->bufsize / period_bytes; |
1204 | ||
1da177e4 | 1205 | /* program the initial BDL entries */ |
4ce107b9 TI |
1206 | bdl = (u32 *)azx_dev->bdl.area; |
1207 | ofs = 0; | |
1208 | azx_dev->frags = 0; | |
555e219f TI |
1209 | pos_adj = bdl_pos_adj[chip->dev_index]; |
1210 | if (pos_adj > 0) { | |
675f25d4 | 1211 | struct snd_pcm_runtime *runtime = substream->runtime; |
e785d3d8 | 1212 | int pos_align = pos_adj; |
555e219f | 1213 | pos_adj = (pos_adj * runtime->rate + 47999) / 48000; |
675f25d4 | 1214 | if (!pos_adj) |
e785d3d8 TI |
1215 | pos_adj = pos_align; |
1216 | else | |
1217 | pos_adj = ((pos_adj + pos_align - 1) / pos_align) * | |
1218 | pos_align; | |
675f25d4 TI |
1219 | pos_adj = frames_to_bytes(runtime, pos_adj); |
1220 | if (pos_adj >= period_bytes) { | |
4abc1cc2 | 1221 | snd_printk(KERN_WARNING SFX "Too big adjustment %d\n", |
555e219f | 1222 | bdl_pos_adj[chip->dev_index]); |
675f25d4 TI |
1223 | pos_adj = 0; |
1224 | } else { | |
1225 | ofs = setup_bdle(substream, azx_dev, | |
1226 | &bdl, ofs, pos_adj, 1); | |
1227 | if (ofs < 0) | |
1228 | goto error; | |
4ce107b9 | 1229 | } |
555e219f TI |
1230 | } else |
1231 | pos_adj = 0; | |
675f25d4 TI |
1232 | for (i = 0; i < periods; i++) { |
1233 | if (i == periods - 1 && pos_adj) | |
1234 | ofs = setup_bdle(substream, azx_dev, &bdl, ofs, | |
1235 | period_bytes - pos_adj, 0); | |
1236 | else | |
1237 | ofs = setup_bdle(substream, azx_dev, &bdl, ofs, | |
1238 | period_bytes, 1); | |
1239 | if (ofs < 0) | |
1240 | goto error; | |
1da177e4 | 1241 | } |
4ce107b9 | 1242 | return 0; |
675f25d4 TI |
1243 | |
1244 | error: | |
4abc1cc2 | 1245 | snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n", |
675f25d4 | 1246 | azx_dev->bufsize, period_bytes); |
675f25d4 | 1247 | return -EINVAL; |
1da177e4 LT |
1248 | } |
1249 | ||
1dddab40 TI |
1250 | /* reset stream */ |
1251 | static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) | |
1da177e4 LT |
1252 | { |
1253 | unsigned char val; | |
1254 | int timeout; | |
1255 | ||
1dddab40 TI |
1256 | azx_stream_clear(chip, azx_dev); |
1257 | ||
d01ce99f TI |
1258 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | |
1259 | SD_CTL_STREAM_RESET); | |
1da177e4 LT |
1260 | udelay(3); |
1261 | timeout = 300; | |
1262 | while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
1263 | --timeout) | |
1264 | ; | |
1265 | val &= ~SD_CTL_STREAM_RESET; | |
1266 | azx_sd_writeb(azx_dev, SD_CTL, val); | |
1267 | udelay(3); | |
1268 | ||
1269 | timeout = 300; | |
1270 | /* waiting for hardware to report that the stream is out of reset */ | |
1271 | while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
1272 | --timeout) | |
1273 | ; | |
fa00e046 JK |
1274 | |
1275 | /* reset first position - may not be synced with hw at this time */ | |
1276 | *azx_dev->posbuf = 0; | |
1dddab40 | 1277 | } |
1da177e4 | 1278 | |
1dddab40 TI |
1279 | /* |
1280 | * set up the SD for streaming | |
1281 | */ | |
1282 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) | |
1283 | { | |
1284 | /* make sure the run bit is zero for SD */ | |
1285 | azx_stream_clear(chip, azx_dev); | |
1da177e4 LT |
1286 | /* program the stream_tag */ |
1287 | azx_sd_writel(azx_dev, SD_CTL, | |
d01ce99f | 1288 | (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)| |
1da177e4 LT |
1289 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); |
1290 | ||
1291 | /* program the length of samples in cyclic buffer */ | |
1292 | azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
1293 | ||
1294 | /* program the stream format */ | |
1295 | /* this value needs to be the same as the one programmed */ | |
1296 | azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
1297 | ||
1298 | /* program the stream LVI (last valid index) of the BDL */ | |
1299 | azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
1300 | ||
1301 | /* program the BDL address */ | |
1302 | /* lower BDL address */ | |
4ce107b9 | 1303 | azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); |
1da177e4 | 1304 | /* upper BDL address */ |
766979e0 | 1305 | azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); |
1da177e4 | 1306 | |
0be3b5d3 | 1307 | /* enable the position buffer */ |
beaffc39 SG |
1308 | if (chip->position_fix[0] == POS_FIX_POSBUF || |
1309 | chip->position_fix[0] == POS_FIX_AUTO || | |
1310 | chip->position_fix[1] == POS_FIX_POSBUF || | |
1311 | chip->position_fix[1] == POS_FIX_AUTO || | |
0e153474 | 1312 | chip->via_dmapos_patch) { |
ee9d6b9a TI |
1313 | if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) |
1314 | azx_writel(chip, DPLBASE, | |
1315 | (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
1316 | } | |
c74db86b | 1317 | |
1da177e4 | 1318 | /* set the interrupt enable bits in the descriptor control register */ |
d01ce99f TI |
1319 | azx_sd_writel(azx_dev, SD_CTL, |
1320 | azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); | |
1da177e4 LT |
1321 | |
1322 | return 0; | |
1323 | } | |
1324 | ||
6ce4a3bc TI |
1325 | /* |
1326 | * Probe the given codec address | |
1327 | */ | |
1328 | static int probe_codec(struct azx *chip, int addr) | |
1329 | { | |
1330 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | |
1331 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
1332 | unsigned int res; | |
1333 | ||
a678cdee | 1334 | mutex_lock(&chip->bus->cmd_mutex); |
6ce4a3bc TI |
1335 | chip->probing = 1; |
1336 | azx_send_cmd(chip->bus, cmd); | |
deadff16 | 1337 | res = azx_get_response(chip->bus, addr); |
6ce4a3bc | 1338 | chip->probing = 0; |
a678cdee | 1339 | mutex_unlock(&chip->bus->cmd_mutex); |
6ce4a3bc TI |
1340 | if (res == -1) |
1341 | return -EIO; | |
4abc1cc2 | 1342 | snd_printdd(SFX "codec #%d probed OK\n", addr); |
6ce4a3bc TI |
1343 | return 0; |
1344 | } | |
1345 | ||
33fa35ed TI |
1346 | static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, |
1347 | struct hda_pcm *cpcm); | |
6ce4a3bc | 1348 | static void azx_stop_chip(struct azx *chip); |
1da177e4 | 1349 | |
8dd78330 TI |
1350 | static void azx_bus_reset(struct hda_bus *bus) |
1351 | { | |
1352 | struct azx *chip = bus->private_data; | |
8dd78330 TI |
1353 | |
1354 | bus->in_reset = 1; | |
1355 | azx_stop_chip(chip); | |
cd508fe5 | 1356 | azx_init_chip(chip, 1); |
65f75983 | 1357 | #ifdef CONFIG_PM |
8dd78330 | 1358 | if (chip->initialized) { |
65f75983 AB |
1359 | int i; |
1360 | ||
c8936222 | 1361 | for (i = 0; i < HDA_MAX_PCMS; i++) |
8dd78330 TI |
1362 | snd_pcm_suspend_all(chip->pcm[i]); |
1363 | snd_hda_suspend(chip->bus); | |
1364 | snd_hda_resume(chip->bus); | |
1365 | } | |
65f75983 | 1366 | #endif |
8dd78330 TI |
1367 | bus->in_reset = 0; |
1368 | } | |
1369 | ||
1da177e4 LT |
1370 | /* |
1371 | * Codec initialization | |
1372 | */ | |
1373 | ||
2f5983f2 TI |
1374 | /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ |
1375 | static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = { | |
7445dfc1 | 1376 | [AZX_DRIVER_NVIDIA] = 8, |
f269002e | 1377 | [AZX_DRIVER_TERA] = 1, |
a9995a35 TI |
1378 | }; |
1379 | ||
a1e21c90 | 1380 | static int __devinit azx_codec_create(struct azx *chip, const char *model) |
1da177e4 LT |
1381 | { |
1382 | struct hda_bus_template bus_temp; | |
34c25350 TI |
1383 | int c, codecs, err; |
1384 | int max_slots; | |
1da177e4 LT |
1385 | |
1386 | memset(&bus_temp, 0, sizeof(bus_temp)); | |
1387 | bus_temp.private_data = chip; | |
1388 | bus_temp.modelname = model; | |
1389 | bus_temp.pci = chip->pci; | |
111d3af5 TI |
1390 | bus_temp.ops.command = azx_send_cmd; |
1391 | bus_temp.ops.get_response = azx_get_response; | |
176d5335 | 1392 | bus_temp.ops.attach_pcm = azx_attach_pcm_stream; |
8dd78330 | 1393 | bus_temp.ops.bus_reset = azx_bus_reset; |
cb53c626 | 1394 | #ifdef CONFIG_SND_HDA_POWER_SAVE |
11cd41b8 | 1395 | bus_temp.power_save = &power_save; |
cb53c626 TI |
1396 | bus_temp.ops.pm_notify = azx_power_notify; |
1397 | #endif | |
1da177e4 | 1398 | |
d01ce99f TI |
1399 | err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); |
1400 | if (err < 0) | |
1da177e4 LT |
1401 | return err; |
1402 | ||
dc9c8e21 WN |
1403 | if (chip->driver_type == AZX_DRIVER_NVIDIA) |
1404 | chip->bus->needs_damn_long_delay = 1; | |
1405 | ||
34c25350 | 1406 | codecs = 0; |
2f5983f2 TI |
1407 | max_slots = azx_max_codecs[chip->driver_type]; |
1408 | if (!max_slots) | |
7445dfc1 | 1409 | max_slots = AZX_DEFAULT_CODECS; |
6ce4a3bc TI |
1410 | |
1411 | /* First try to probe all given codec slots */ | |
1412 | for (c = 0; c < max_slots; c++) { | |
f1eaaeec | 1413 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
6ce4a3bc TI |
1414 | if (probe_codec(chip, c) < 0) { |
1415 | /* Some BIOSen give you wrong codec addresses | |
1416 | * that don't exist | |
1417 | */ | |
4abc1cc2 TI |
1418 | snd_printk(KERN_WARNING SFX |
1419 | "Codec #%d probe error; " | |
6ce4a3bc TI |
1420 | "disabling it...\n", c); |
1421 | chip->codec_mask &= ~(1 << c); | |
1422 | /* More badly, accessing to a non-existing | |
1423 | * codec often screws up the controller chip, | |
2448158e | 1424 | * and disturbs the further communications. |
6ce4a3bc TI |
1425 | * Thus if an error occurs during probing, |
1426 | * better to reset the controller chip to | |
1427 | * get back to the sanity state. | |
1428 | */ | |
1429 | azx_stop_chip(chip); | |
cd508fe5 | 1430 | azx_init_chip(chip, 1); |
6ce4a3bc TI |
1431 | } |
1432 | } | |
1433 | } | |
1434 | ||
1435 | /* Then create codec instances */ | |
34c25350 | 1436 | for (c = 0; c < max_slots; c++) { |
f1eaaeec | 1437 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
bccad14e | 1438 | struct hda_codec *codec; |
a1e21c90 | 1439 | err = snd_hda_codec_new(chip->bus, c, &codec); |
1da177e4 LT |
1440 | if (err < 0) |
1441 | continue; | |
2dca0bba | 1442 | codec->beep_mode = chip->beep_mode; |
1da177e4 | 1443 | codecs++; |
19a982b6 TI |
1444 | } |
1445 | } | |
1446 | if (!codecs) { | |
1da177e4 LT |
1447 | snd_printk(KERN_ERR SFX "no codecs initialized\n"); |
1448 | return -ENXIO; | |
1449 | } | |
a1e21c90 TI |
1450 | return 0; |
1451 | } | |
1da177e4 | 1452 | |
a1e21c90 TI |
1453 | /* configure each codec instance */ |
1454 | static int __devinit azx_codec_configure(struct azx *chip) | |
1455 | { | |
1456 | struct hda_codec *codec; | |
1457 | list_for_each_entry(codec, &chip->bus->codec_list, list) { | |
1458 | snd_hda_codec_configure(codec); | |
1459 | } | |
1da177e4 LT |
1460 | return 0; |
1461 | } | |
1462 | ||
1463 | ||
1464 | /* | |
1465 | * PCM support | |
1466 | */ | |
1467 | ||
1468 | /* assign a stream for the PCM */ | |
ef18bede WF |
1469 | static inline struct azx_dev * |
1470 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) | |
1da177e4 | 1471 | { |
07e4ca50 | 1472 | int dev, i, nums; |
ef18bede WF |
1473 | struct azx_dev *res = NULL; |
1474 | ||
1475 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
07e4ca50 TI |
1476 | dev = chip->playback_index_offset; |
1477 | nums = chip->playback_streams; | |
1478 | } else { | |
1479 | dev = chip->capture_index_offset; | |
1480 | nums = chip->capture_streams; | |
1481 | } | |
1482 | for (i = 0; i < nums; i++, dev++) | |
d01ce99f | 1483 | if (!chip->azx_dev[dev].opened) { |
ef18bede WF |
1484 | res = &chip->azx_dev[dev]; |
1485 | if (res->device == substream->pcm->device) | |
1486 | break; | |
1da177e4 | 1487 | } |
ef18bede WF |
1488 | if (res) { |
1489 | res->opened = 1; | |
1490 | res->device = substream->pcm->device; | |
1491 | } | |
1492 | return res; | |
1da177e4 LT |
1493 | } |
1494 | ||
1495 | /* release the assigned stream */ | |
a98f90fd | 1496 | static inline void azx_release_device(struct azx_dev *azx_dev) |
1da177e4 LT |
1497 | { |
1498 | azx_dev->opened = 0; | |
1499 | } | |
1500 | ||
a98f90fd | 1501 | static struct snd_pcm_hardware azx_pcm_hw = { |
d01ce99f TI |
1502 | .info = (SNDRV_PCM_INFO_MMAP | |
1503 | SNDRV_PCM_INFO_INTERLEAVED | | |
1da177e4 LT |
1504 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
1505 | SNDRV_PCM_INFO_MMAP_VALID | | |
927fc866 PM |
1506 | /* No full-resume yet implemented */ |
1507 | /* SNDRV_PCM_INFO_RESUME |*/ | |
850f0e52 TI |
1508 | SNDRV_PCM_INFO_PAUSE | |
1509 | SNDRV_PCM_INFO_SYNC_START), | |
1da177e4 LT |
1510 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1511 | .rates = SNDRV_PCM_RATE_48000, | |
1512 | .rate_min = 48000, | |
1513 | .rate_max = 48000, | |
1514 | .channels_min = 2, | |
1515 | .channels_max = 2, | |
1516 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
1517 | .period_bytes_min = 128, | |
1518 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
1519 | .periods_min = 2, | |
1520 | .periods_max = AZX_MAX_FRAG, | |
1521 | .fifo_size = 0, | |
1522 | }; | |
1523 | ||
1524 | struct azx_pcm { | |
a98f90fd | 1525 | struct azx *chip; |
1da177e4 LT |
1526 | struct hda_codec *codec; |
1527 | struct hda_pcm_stream *hinfo[2]; | |
1528 | }; | |
1529 | ||
a98f90fd | 1530 | static int azx_pcm_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1531 | { |
1532 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1533 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1534 | struct azx *chip = apcm->chip; |
1535 | struct azx_dev *azx_dev; | |
1536 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1537 | unsigned long flags; |
1538 | int err; | |
1539 | ||
62932df8 | 1540 | mutex_lock(&chip->open_mutex); |
ef18bede | 1541 | azx_dev = azx_assign_device(chip, substream); |
1da177e4 | 1542 | if (azx_dev == NULL) { |
62932df8 | 1543 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1544 | return -EBUSY; |
1545 | } | |
1546 | runtime->hw = azx_pcm_hw; | |
1547 | runtime->hw.channels_min = hinfo->channels_min; | |
1548 | runtime->hw.channels_max = hinfo->channels_max; | |
1549 | runtime->hw.formats = hinfo->formats; | |
1550 | runtime->hw.rates = hinfo->rates; | |
1551 | snd_pcm_limit_hw_rates(runtime); | |
1552 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
5f1545bc JD |
1553 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, |
1554 | 128); | |
1555 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
1556 | 128); | |
cb53c626 | 1557 | snd_hda_power_up(apcm->codec); |
d01ce99f TI |
1558 | err = hinfo->ops.open(hinfo, apcm->codec, substream); |
1559 | if (err < 0) { | |
1da177e4 | 1560 | azx_release_device(azx_dev); |
cb53c626 | 1561 | snd_hda_power_down(apcm->codec); |
62932df8 | 1562 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1563 | return err; |
1564 | } | |
70d321e6 | 1565 | snd_pcm_limit_hw_rates(runtime); |
aba66536 TI |
1566 | /* sanity check */ |
1567 | if (snd_BUG_ON(!runtime->hw.channels_min) || | |
1568 | snd_BUG_ON(!runtime->hw.channels_max) || | |
1569 | snd_BUG_ON(!runtime->hw.formats) || | |
1570 | snd_BUG_ON(!runtime->hw.rates)) { | |
1571 | azx_release_device(azx_dev); | |
1572 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
1573 | snd_hda_power_down(apcm->codec); | |
1574 | mutex_unlock(&chip->open_mutex); | |
1575 | return -EINVAL; | |
1576 | } | |
1da177e4 LT |
1577 | spin_lock_irqsave(&chip->reg_lock, flags); |
1578 | azx_dev->substream = substream; | |
1579 | azx_dev->running = 0; | |
1580 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1581 | ||
1582 | runtime->private_data = azx_dev; | |
850f0e52 | 1583 | snd_pcm_set_sync(substream); |
62932df8 | 1584 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1585 | return 0; |
1586 | } | |
1587 | ||
a98f90fd | 1588 | static int azx_pcm_close(struct snd_pcm_substream *substream) |
1da177e4 LT |
1589 | { |
1590 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1591 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1592 | struct azx *chip = apcm->chip; |
1593 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 LT |
1594 | unsigned long flags; |
1595 | ||
62932df8 | 1596 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
1597 | spin_lock_irqsave(&chip->reg_lock, flags); |
1598 | azx_dev->substream = NULL; | |
1599 | azx_dev->running = 0; | |
1600 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1601 | azx_release_device(azx_dev); | |
1602 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
cb53c626 | 1603 | snd_hda_power_down(apcm->codec); |
62932df8 | 1604 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1605 | return 0; |
1606 | } | |
1607 | ||
d01ce99f TI |
1608 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, |
1609 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 1610 | { |
97b71c94 TI |
1611 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1612 | ||
1613 | azx_dev->bufsize = 0; | |
1614 | azx_dev->period_bytes = 0; | |
1615 | azx_dev->format_val = 0; | |
d01ce99f TI |
1616 | return snd_pcm_lib_malloc_pages(substream, |
1617 | params_buffer_bytes(hw_params)); | |
1da177e4 LT |
1618 | } |
1619 | ||
a98f90fd | 1620 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
1621 | { |
1622 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd | 1623 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1da177e4 LT |
1624 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
1625 | ||
1626 | /* reset BDL address */ | |
1627 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
1628 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
1629 | azx_sd_writel(azx_dev, SD_CTL, 0); | |
97b71c94 TI |
1630 | azx_dev->bufsize = 0; |
1631 | azx_dev->period_bytes = 0; | |
1632 | azx_dev->format_val = 0; | |
1da177e4 LT |
1633 | |
1634 | hinfo->ops.cleanup(hinfo, apcm->codec, substream); | |
1635 | ||
1636 | return snd_pcm_lib_free_pages(substream); | |
1637 | } | |
1638 | ||
a98f90fd | 1639 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 LT |
1640 | { |
1641 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd TI |
1642 | struct azx *chip = apcm->chip; |
1643 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 | 1644 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
a98f90fd | 1645 | struct snd_pcm_runtime *runtime = substream->runtime; |
97b71c94 TI |
1646 | unsigned int bufsize, period_bytes, format_val; |
1647 | int err; | |
1da177e4 | 1648 | |
fa00e046 | 1649 | azx_stream_reset(chip, azx_dev); |
97b71c94 TI |
1650 | format_val = snd_hda_calc_stream_format(runtime->rate, |
1651 | runtime->channels, | |
1652 | runtime->format, | |
1653 | hinfo->maxbps); | |
1654 | if (!format_val) { | |
d01ce99f TI |
1655 | snd_printk(KERN_ERR SFX |
1656 | "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
1da177e4 LT |
1657 | runtime->rate, runtime->channels, runtime->format); |
1658 | return -EINVAL; | |
1659 | } | |
1660 | ||
97b71c94 TI |
1661 | bufsize = snd_pcm_lib_buffer_bytes(substream); |
1662 | period_bytes = snd_pcm_lib_period_bytes(substream); | |
1663 | ||
4abc1cc2 | 1664 | snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", |
97b71c94 TI |
1665 | bufsize, format_val); |
1666 | ||
1667 | if (bufsize != azx_dev->bufsize || | |
1668 | period_bytes != azx_dev->period_bytes || | |
1669 | format_val != azx_dev->format_val) { | |
1670 | azx_dev->bufsize = bufsize; | |
1671 | azx_dev->period_bytes = period_bytes; | |
1672 | azx_dev->format_val = format_val; | |
1673 | err = azx_setup_periods(chip, substream, azx_dev); | |
1674 | if (err < 0) | |
1675 | return err; | |
1676 | } | |
1677 | ||
e5463720 JK |
1678 | /* wallclk has 24Mhz clock source */ |
1679 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | |
1680 | runtime->rate) * 1000); | |
1da177e4 LT |
1681 | azx_setup_controller(chip, azx_dev); |
1682 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1683 | azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; | |
1684 | else | |
1685 | azx_dev->fifo_size = 0; | |
1686 | ||
1687 | return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, | |
1688 | azx_dev->format_val, substream); | |
1689 | } | |
1690 | ||
a98f90fd | 1691 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 LT |
1692 | { |
1693 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd | 1694 | struct azx *chip = apcm->chip; |
850f0e52 TI |
1695 | struct azx_dev *azx_dev; |
1696 | struct snd_pcm_substream *s; | |
fa00e046 | 1697 | int rstart = 0, start, nsync = 0, sbits = 0; |
850f0e52 | 1698 | int nwait, timeout; |
1da177e4 | 1699 | |
1da177e4 | 1700 | switch (cmd) { |
fa00e046 JK |
1701 | case SNDRV_PCM_TRIGGER_START: |
1702 | rstart = 1; | |
1da177e4 LT |
1703 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1704 | case SNDRV_PCM_TRIGGER_RESUME: | |
850f0e52 | 1705 | start = 1; |
1da177e4 LT |
1706 | break; |
1707 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
47123197 | 1708 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 | 1709 | case SNDRV_PCM_TRIGGER_STOP: |
850f0e52 | 1710 | start = 0; |
1da177e4 LT |
1711 | break; |
1712 | default: | |
850f0e52 TI |
1713 | return -EINVAL; |
1714 | } | |
1715 | ||
1716 | snd_pcm_group_for_each_entry(s, substream) { | |
1717 | if (s->pcm->card != substream->pcm->card) | |
1718 | continue; | |
1719 | azx_dev = get_azx_dev(s); | |
1720 | sbits |= 1 << azx_dev->index; | |
1721 | nsync++; | |
1722 | snd_pcm_trigger_done(s, substream); | |
1723 | } | |
1724 | ||
1725 | spin_lock(&chip->reg_lock); | |
1726 | if (nsync > 1) { | |
1727 | /* first, set SYNC bits of corresponding streams */ | |
1728 | azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits); | |
1729 | } | |
1730 | snd_pcm_group_for_each_entry(s, substream) { | |
1731 | if (s->pcm->card != substream->pcm->card) | |
1732 | continue; | |
1733 | azx_dev = get_azx_dev(s); | |
e5463720 JK |
1734 | if (start) { |
1735 | azx_dev->start_wallclk = azx_readl(chip, WALLCLK); | |
1736 | if (!rstart) | |
1737 | azx_dev->start_wallclk -= | |
1738 | azx_dev->period_wallclk; | |
850f0e52 | 1739 | azx_stream_start(chip, azx_dev); |
e5463720 | 1740 | } else { |
850f0e52 | 1741 | azx_stream_stop(chip, azx_dev); |
e5463720 | 1742 | } |
850f0e52 | 1743 | azx_dev->running = start; |
1da177e4 LT |
1744 | } |
1745 | spin_unlock(&chip->reg_lock); | |
850f0e52 TI |
1746 | if (start) { |
1747 | if (nsync == 1) | |
1748 | return 0; | |
1749 | /* wait until all FIFOs get ready */ | |
1750 | for (timeout = 5000; timeout; timeout--) { | |
1751 | nwait = 0; | |
1752 | snd_pcm_group_for_each_entry(s, substream) { | |
1753 | if (s->pcm->card != substream->pcm->card) | |
1754 | continue; | |
1755 | azx_dev = get_azx_dev(s); | |
1756 | if (!(azx_sd_readb(azx_dev, SD_STS) & | |
1757 | SD_STS_FIFO_READY)) | |
1758 | nwait++; | |
1759 | } | |
1760 | if (!nwait) | |
1761 | break; | |
1762 | cpu_relax(); | |
1763 | } | |
1764 | } else { | |
1765 | /* wait until all RUN bits are cleared */ | |
1766 | for (timeout = 5000; timeout; timeout--) { | |
1767 | nwait = 0; | |
1768 | snd_pcm_group_for_each_entry(s, substream) { | |
1769 | if (s->pcm->card != substream->pcm->card) | |
1770 | continue; | |
1771 | azx_dev = get_azx_dev(s); | |
1772 | if (azx_sd_readb(azx_dev, SD_CTL) & | |
1773 | SD_CTL_DMA_START) | |
1774 | nwait++; | |
1775 | } | |
1776 | if (!nwait) | |
1777 | break; | |
1778 | cpu_relax(); | |
1779 | } | |
1da177e4 | 1780 | } |
850f0e52 TI |
1781 | if (nsync > 1) { |
1782 | spin_lock(&chip->reg_lock); | |
1783 | /* reset SYNC bits */ | |
1784 | azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits); | |
1785 | spin_unlock(&chip->reg_lock); | |
1786 | } | |
1787 | return 0; | |
1da177e4 LT |
1788 | } |
1789 | ||
0e153474 JC |
1790 | /* get the current DMA position with correction on VIA chips */ |
1791 | static unsigned int azx_via_get_position(struct azx *chip, | |
1792 | struct azx_dev *azx_dev) | |
1793 | { | |
1794 | unsigned int link_pos, mini_pos, bound_pos; | |
1795 | unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; | |
1796 | unsigned int fifo_size; | |
1797 | ||
1798 | link_pos = azx_sd_readl(azx_dev, SD_LPIB); | |
1799 | if (azx_dev->index >= 4) { | |
1800 | /* Playback, no problem using link position */ | |
1801 | return link_pos; | |
1802 | } | |
1803 | ||
1804 | /* Capture */ | |
1805 | /* For new chipset, | |
1806 | * use mod to get the DMA position just like old chipset | |
1807 | */ | |
1808 | mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); | |
1809 | mod_dma_pos %= azx_dev->period_bytes; | |
1810 | ||
1811 | /* azx_dev->fifo_size can't get FIFO size of in stream. | |
1812 | * Get from base address + offset. | |
1813 | */ | |
1814 | fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); | |
1815 | ||
1816 | if (azx_dev->insufficient) { | |
1817 | /* Link position never gather than FIFO size */ | |
1818 | if (link_pos <= fifo_size) | |
1819 | return 0; | |
1820 | ||
1821 | azx_dev->insufficient = 0; | |
1822 | } | |
1823 | ||
1824 | if (link_pos <= fifo_size) | |
1825 | mini_pos = azx_dev->bufsize + link_pos - fifo_size; | |
1826 | else | |
1827 | mini_pos = link_pos - fifo_size; | |
1828 | ||
1829 | /* Find nearest previous boudary */ | |
1830 | mod_mini_pos = mini_pos % azx_dev->period_bytes; | |
1831 | mod_link_pos = link_pos % azx_dev->period_bytes; | |
1832 | if (mod_link_pos >= fifo_size) | |
1833 | bound_pos = link_pos - mod_link_pos; | |
1834 | else if (mod_dma_pos >= mod_mini_pos) | |
1835 | bound_pos = mini_pos - mod_mini_pos; | |
1836 | else { | |
1837 | bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; | |
1838 | if (bound_pos >= azx_dev->bufsize) | |
1839 | bound_pos = 0; | |
1840 | } | |
1841 | ||
1842 | /* Calculate real DMA position we want */ | |
1843 | return bound_pos + mod_dma_pos; | |
1844 | } | |
1845 | ||
9ad593f6 TI |
1846 | static unsigned int azx_get_position(struct azx *chip, |
1847 | struct azx_dev *azx_dev) | |
1da177e4 | 1848 | { |
1da177e4 LT |
1849 | unsigned int pos; |
1850 | ||
0e153474 JC |
1851 | if (chip->via_dmapos_patch) |
1852 | pos = azx_via_get_position(chip, azx_dev); | |
beaffc39 SG |
1853 | else { |
1854 | int stream = azx_dev->substream->stream; | |
1855 | if (chip->position_fix[stream] == POS_FIX_POSBUF || | |
1856 | chip->position_fix[stream] == POS_FIX_AUTO) { | |
1857 | /* use the position buffer */ | |
1858 | pos = le32_to_cpu(*azx_dev->posbuf); | |
1859 | } else { | |
1860 | /* read LPIB */ | |
1861 | pos = azx_sd_readl(azx_dev, SD_LPIB); | |
1862 | } | |
c74db86b | 1863 | } |
1da177e4 LT |
1864 | if (pos >= azx_dev->bufsize) |
1865 | pos = 0; | |
9ad593f6 TI |
1866 | return pos; |
1867 | } | |
1868 | ||
1869 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | |
1870 | { | |
1871 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1872 | struct azx *chip = apcm->chip; | |
1873 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1874 | return bytes_to_frames(substream->runtime, | |
1875 | azx_get_position(chip, azx_dev)); | |
1876 | } | |
1877 | ||
1878 | /* | |
1879 | * Check whether the current DMA position is acceptable for updating | |
1880 | * periods. Returns non-zero if it's OK. | |
1881 | * | |
1882 | * Many HD-audio controllers appear pretty inaccurate about | |
1883 | * the update-IRQ timing. The IRQ is issued before actually the | |
1884 | * data is processed. So, we need to process it afterwords in a | |
1885 | * workqueue. | |
1886 | */ | |
1887 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) | |
1888 | { | |
e5463720 | 1889 | u32 wallclk; |
9ad593f6 | 1890 | unsigned int pos; |
beaffc39 | 1891 | int stream; |
9ad593f6 | 1892 | |
f48f606d JK |
1893 | wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; |
1894 | if (wallclk < (azx_dev->period_wallclk * 2) / 3) | |
fa00e046 | 1895 | return -1; /* bogus (too early) interrupt */ |
fa00e046 | 1896 | |
beaffc39 | 1897 | stream = azx_dev->substream->stream; |
9ad593f6 | 1898 | pos = azx_get_position(chip, azx_dev); |
beaffc39 | 1899 | if (chip->position_fix[stream] == POS_FIX_AUTO) { |
9ad593f6 TI |
1900 | if (!pos) { |
1901 | printk(KERN_WARNING | |
1902 | "hda-intel: Invalid position buffer, " | |
1903 | "using LPIB read method instead.\n"); | |
beaffc39 | 1904 | chip->position_fix[stream] = POS_FIX_LPIB; |
9ad593f6 TI |
1905 | pos = azx_get_position(chip, azx_dev); |
1906 | } else | |
beaffc39 | 1907 | chip->position_fix[stream] = POS_FIX_POSBUF; |
9ad593f6 TI |
1908 | } |
1909 | ||
d6d8bf54 TI |
1910 | if (WARN_ONCE(!azx_dev->period_bytes, |
1911 | "hda-intel: zero azx_dev->period_bytes")) | |
f48f606d JK |
1912 | return -1; /* this shouldn't happen! */ |
1913 | if (wallclk <= azx_dev->period_wallclk && | |
1914 | pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) | |
1915 | /* NG - it's below the first next period boundary */ | |
1916 | return bdl_pos_adj[chip->dev_index] ? 0 : -1; | |
e5463720 | 1917 | azx_dev->start_wallclk = wallclk; |
9ad593f6 TI |
1918 | return 1; /* OK, it's fine */ |
1919 | } | |
1920 | ||
1921 | /* | |
1922 | * The work for pending PCM period updates. | |
1923 | */ | |
1924 | static void azx_irq_pending_work(struct work_struct *work) | |
1925 | { | |
1926 | struct azx *chip = container_of(work, struct azx, irq_pending_work); | |
e5463720 | 1927 | int i, pending, ok; |
9ad593f6 | 1928 | |
a6a950a8 TI |
1929 | if (!chip->irq_pending_warned) { |
1930 | printk(KERN_WARNING | |
1931 | "hda-intel: IRQ timing workaround is activated " | |
1932 | "for card #%d. Suggest a bigger bdl_pos_adj.\n", | |
1933 | chip->card->number); | |
1934 | chip->irq_pending_warned = 1; | |
1935 | } | |
1936 | ||
9ad593f6 TI |
1937 | for (;;) { |
1938 | pending = 0; | |
1939 | spin_lock_irq(&chip->reg_lock); | |
1940 | for (i = 0; i < chip->num_streams; i++) { | |
1941 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | |
1942 | if (!azx_dev->irq_pending || | |
1943 | !azx_dev->substream || | |
1944 | !azx_dev->running) | |
1945 | continue; | |
e5463720 JK |
1946 | ok = azx_position_ok(chip, azx_dev); |
1947 | if (ok > 0) { | |
9ad593f6 TI |
1948 | azx_dev->irq_pending = 0; |
1949 | spin_unlock(&chip->reg_lock); | |
1950 | snd_pcm_period_elapsed(azx_dev->substream); | |
1951 | spin_lock(&chip->reg_lock); | |
e5463720 JK |
1952 | } else if (ok < 0) { |
1953 | pending = 0; /* too early */ | |
9ad593f6 TI |
1954 | } else |
1955 | pending++; | |
1956 | } | |
1957 | spin_unlock_irq(&chip->reg_lock); | |
1958 | if (!pending) | |
1959 | return; | |
1960 | cond_resched(); | |
1961 | } | |
1962 | } | |
1963 | ||
1964 | /* clear irq_pending flags and assure no on-going workq */ | |
1965 | static void azx_clear_irq_pending(struct azx *chip) | |
1966 | { | |
1967 | int i; | |
1968 | ||
1969 | spin_lock_irq(&chip->reg_lock); | |
1970 | for (i = 0; i < chip->num_streams; i++) | |
1971 | chip->azx_dev[i].irq_pending = 0; | |
1972 | spin_unlock_irq(&chip->reg_lock); | |
1da177e4 LT |
1973 | } |
1974 | ||
a98f90fd | 1975 | static struct snd_pcm_ops azx_pcm_ops = { |
1da177e4 LT |
1976 | .open = azx_pcm_open, |
1977 | .close = azx_pcm_close, | |
1978 | .ioctl = snd_pcm_lib_ioctl, | |
1979 | .hw_params = azx_pcm_hw_params, | |
1980 | .hw_free = azx_pcm_hw_free, | |
1981 | .prepare = azx_pcm_prepare, | |
1982 | .trigger = azx_pcm_trigger, | |
1983 | .pointer = azx_pcm_pointer, | |
4ce107b9 | 1984 | .page = snd_pcm_sgbuf_ops_page, |
1da177e4 LT |
1985 | }; |
1986 | ||
a98f90fd | 1987 | static void azx_pcm_free(struct snd_pcm *pcm) |
1da177e4 | 1988 | { |
176d5335 TI |
1989 | struct azx_pcm *apcm = pcm->private_data; |
1990 | if (apcm) { | |
1991 | apcm->chip->pcm[pcm->device] = NULL; | |
1992 | kfree(apcm); | |
1993 | } | |
1da177e4 LT |
1994 | } |
1995 | ||
176d5335 | 1996 | static int |
33fa35ed TI |
1997 | azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, |
1998 | struct hda_pcm *cpcm) | |
1da177e4 | 1999 | { |
33fa35ed | 2000 | struct azx *chip = bus->private_data; |
a98f90fd | 2001 | struct snd_pcm *pcm; |
1da177e4 | 2002 | struct azx_pcm *apcm; |
176d5335 TI |
2003 | int pcm_dev = cpcm->device; |
2004 | int s, err; | |
1da177e4 | 2005 | |
c8936222 | 2006 | if (pcm_dev >= HDA_MAX_PCMS) { |
176d5335 TI |
2007 | snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n", |
2008 | pcm_dev); | |
da3cec35 | 2009 | return -EINVAL; |
176d5335 TI |
2010 | } |
2011 | if (chip->pcm[pcm_dev]) { | |
2012 | snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev); | |
2013 | return -EBUSY; | |
2014 | } | |
2015 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
2016 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, | |
2017 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, | |
1da177e4 LT |
2018 | &pcm); |
2019 | if (err < 0) | |
2020 | return err; | |
18cb7109 | 2021 | strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); |
176d5335 | 2022 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); |
1da177e4 LT |
2023 | if (apcm == NULL) |
2024 | return -ENOMEM; | |
2025 | apcm->chip = chip; | |
2026 | apcm->codec = codec; | |
1da177e4 LT |
2027 | pcm->private_data = apcm; |
2028 | pcm->private_free = azx_pcm_free; | |
176d5335 TI |
2029 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) |
2030 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; | |
2031 | chip->pcm[pcm_dev] = pcm; | |
2032 | cpcm->pcm = pcm; | |
2033 | for (s = 0; s < 2; s++) { | |
2034 | apcm->hinfo[s] = &cpcm->stream[s]; | |
2035 | if (cpcm->stream[s].substreams) | |
2036 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); | |
2037 | } | |
2038 | /* buffer pre-allocation */ | |
4ce107b9 | 2039 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, |
1da177e4 | 2040 | snd_dma_pci_data(chip->pci), |
fc4abee8 | 2041 | 1024 * 64, 32 * 1024 * 1024); |
1da177e4 LT |
2042 | return 0; |
2043 | } | |
2044 | ||
2045 | /* | |
2046 | * mixer creation - all stuff is implemented in hda module | |
2047 | */ | |
a98f90fd | 2048 | static int __devinit azx_mixer_create(struct azx *chip) |
1da177e4 LT |
2049 | { |
2050 | return snd_hda_build_controls(chip->bus); | |
2051 | } | |
2052 | ||
2053 | ||
2054 | /* | |
2055 | * initialize SD streams | |
2056 | */ | |
a98f90fd | 2057 | static int __devinit azx_init_stream(struct azx *chip) |
1da177e4 LT |
2058 | { |
2059 | int i; | |
2060 | ||
2061 | /* initialize each stream (aka device) | |
d01ce99f TI |
2062 | * assign the starting bdl address to each stream (device) |
2063 | * and initialize | |
1da177e4 | 2064 | */ |
07e4ca50 | 2065 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 2066 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
929861c6 | 2067 | azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); |
1da177e4 LT |
2068 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
2069 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | |
2070 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
2071 | azx_dev->sd_int_sta_mask = 1 << i; | |
2072 | /* stream tag: must be non-zero and unique */ | |
2073 | azx_dev->index = i; | |
2074 | azx_dev->stream_tag = i + 1; | |
2075 | } | |
2076 | ||
2077 | return 0; | |
2078 | } | |
2079 | ||
68e7fffc TI |
2080 | static int azx_acquire_irq(struct azx *chip, int do_disconnect) |
2081 | { | |
437a5a46 TI |
2082 | if (request_irq(chip->pci->irq, azx_interrupt, |
2083 | chip->msi ? 0 : IRQF_SHARED, | |
9492837a | 2084 | "hda_intel", chip)) { |
68e7fffc TI |
2085 | printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " |
2086 | "disabling device\n", chip->pci->irq); | |
2087 | if (do_disconnect) | |
2088 | snd_card_disconnect(chip->card); | |
2089 | return -1; | |
2090 | } | |
2091 | chip->irq = chip->pci->irq; | |
69e13418 | 2092 | pci_intx(chip->pci, !chip->msi); |
68e7fffc TI |
2093 | return 0; |
2094 | } | |
2095 | ||
1da177e4 | 2096 | |
cb53c626 TI |
2097 | static void azx_stop_chip(struct azx *chip) |
2098 | { | |
95e99fda | 2099 | if (!chip->initialized) |
cb53c626 TI |
2100 | return; |
2101 | ||
2102 | /* disable interrupts */ | |
2103 | azx_int_disable(chip); | |
2104 | azx_int_clear(chip); | |
2105 | ||
2106 | /* disable CORB/RIRB */ | |
2107 | azx_free_cmd_io(chip); | |
2108 | ||
2109 | /* disable position buffer */ | |
2110 | azx_writel(chip, DPLBASE, 0); | |
2111 | azx_writel(chip, DPUBASE, 0); | |
2112 | ||
2113 | chip->initialized = 0; | |
2114 | } | |
2115 | ||
2116 | #ifdef CONFIG_SND_HDA_POWER_SAVE | |
2117 | /* power-up/down the controller */ | |
33fa35ed | 2118 | static void azx_power_notify(struct hda_bus *bus) |
cb53c626 | 2119 | { |
33fa35ed | 2120 | struct azx *chip = bus->private_data; |
cb53c626 TI |
2121 | struct hda_codec *c; |
2122 | int power_on = 0; | |
2123 | ||
33fa35ed | 2124 | list_for_each_entry(c, &bus->codec_list, list) { |
cb53c626 TI |
2125 | if (c->power_on) { |
2126 | power_on = 1; | |
2127 | break; | |
2128 | } | |
2129 | } | |
2130 | if (power_on) | |
cd508fe5 | 2131 | azx_init_chip(chip, 1); |
0287d970 WF |
2132 | else if (chip->running && power_save_controller && |
2133 | !bus->power_keep_link_on) | |
cb53c626 | 2134 | azx_stop_chip(chip); |
cb53c626 | 2135 | } |
5c0b9bec TI |
2136 | #endif /* CONFIG_SND_HDA_POWER_SAVE */ |
2137 | ||
2138 | #ifdef CONFIG_PM | |
2139 | /* | |
2140 | * power management | |
2141 | */ | |
986862bd TI |
2142 | |
2143 | static int snd_hda_codecs_inuse(struct hda_bus *bus) | |
2144 | { | |
2145 | struct hda_codec *codec; | |
2146 | ||
2147 | list_for_each_entry(codec, &bus->codec_list, list) { | |
2148 | if (snd_hda_codec_needs_resume(codec)) | |
2149 | return 1; | |
2150 | } | |
2151 | return 0; | |
2152 | } | |
cb53c626 | 2153 | |
421a1252 | 2154 | static int azx_suspend(struct pci_dev *pci, pm_message_t state) |
1da177e4 | 2155 | { |
421a1252 TI |
2156 | struct snd_card *card = pci_get_drvdata(pci); |
2157 | struct azx *chip = card->private_data; | |
1da177e4 LT |
2158 | int i; |
2159 | ||
421a1252 | 2160 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
9ad593f6 | 2161 | azx_clear_irq_pending(chip); |
c8936222 | 2162 | for (i = 0; i < HDA_MAX_PCMS; i++) |
421a1252 | 2163 | snd_pcm_suspend_all(chip->pcm[i]); |
0b7a2e9c | 2164 | if (chip->initialized) |
8dd78330 | 2165 | snd_hda_suspend(chip->bus); |
cb53c626 | 2166 | azx_stop_chip(chip); |
30b35399 | 2167 | if (chip->irq >= 0) { |
43001c95 | 2168 | free_irq(chip->irq, chip); |
30b35399 TI |
2169 | chip->irq = -1; |
2170 | } | |
68e7fffc | 2171 | if (chip->msi) |
43001c95 | 2172 | pci_disable_msi(chip->pci); |
421a1252 TI |
2173 | pci_disable_device(pci); |
2174 | pci_save_state(pci); | |
30b35399 | 2175 | pci_set_power_state(pci, pci_choose_state(pci, state)); |
1da177e4 LT |
2176 | return 0; |
2177 | } | |
2178 | ||
421a1252 | 2179 | static int azx_resume(struct pci_dev *pci) |
1da177e4 | 2180 | { |
421a1252 TI |
2181 | struct snd_card *card = pci_get_drvdata(pci); |
2182 | struct azx *chip = card->private_data; | |
1da177e4 | 2183 | |
d14a7e0b TI |
2184 | pci_set_power_state(pci, PCI_D0); |
2185 | pci_restore_state(pci); | |
30b35399 TI |
2186 | if (pci_enable_device(pci) < 0) { |
2187 | printk(KERN_ERR "hda-intel: pci_enable_device failed, " | |
2188 | "disabling device\n"); | |
2189 | snd_card_disconnect(card); | |
2190 | return -EIO; | |
2191 | } | |
2192 | pci_set_master(pci); | |
68e7fffc TI |
2193 | if (chip->msi) |
2194 | if (pci_enable_msi(pci) < 0) | |
2195 | chip->msi = 0; | |
2196 | if (azx_acquire_irq(chip, 1) < 0) | |
30b35399 | 2197 | return -EIO; |
cb53c626 | 2198 | azx_init_pci(chip); |
d804ad92 ML |
2199 | |
2200 | if (snd_hda_codecs_inuse(chip->bus)) | |
cd508fe5 | 2201 | azx_init_chip(chip, 1); |
d804ad92 | 2202 | |
1da177e4 | 2203 | snd_hda_resume(chip->bus); |
421a1252 | 2204 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
2205 | return 0; |
2206 | } | |
2207 | #endif /* CONFIG_PM */ | |
2208 | ||
2209 | ||
0cbf0098 TI |
2210 | /* |
2211 | * reboot notifier for hang-up problem at power-down | |
2212 | */ | |
2213 | static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) | |
2214 | { | |
2215 | struct azx *chip = container_of(nb, struct azx, reboot_notifier); | |
fb8d1a34 | 2216 | snd_hda_bus_reboot_notify(chip->bus); |
0cbf0098 TI |
2217 | azx_stop_chip(chip); |
2218 | return NOTIFY_OK; | |
2219 | } | |
2220 | ||
2221 | static void azx_notifier_register(struct azx *chip) | |
2222 | { | |
2223 | chip->reboot_notifier.notifier_call = azx_halt; | |
2224 | register_reboot_notifier(&chip->reboot_notifier); | |
2225 | } | |
2226 | ||
2227 | static void azx_notifier_unregister(struct azx *chip) | |
2228 | { | |
2229 | if (chip->reboot_notifier.notifier_call) | |
2230 | unregister_reboot_notifier(&chip->reboot_notifier); | |
2231 | } | |
2232 | ||
1da177e4 LT |
2233 | /* |
2234 | * destructor | |
2235 | */ | |
a98f90fd | 2236 | static int azx_free(struct azx *chip) |
1da177e4 | 2237 | { |
4ce107b9 TI |
2238 | int i; |
2239 | ||
0cbf0098 TI |
2240 | azx_notifier_unregister(chip); |
2241 | ||
ce43fbae | 2242 | if (chip->initialized) { |
9ad593f6 | 2243 | azx_clear_irq_pending(chip); |
07e4ca50 | 2244 | for (i = 0; i < chip->num_streams; i++) |
1da177e4 | 2245 | azx_stream_stop(chip, &chip->azx_dev[i]); |
cb53c626 | 2246 | azx_stop_chip(chip); |
1da177e4 LT |
2247 | } |
2248 | ||
f000fd80 | 2249 | if (chip->irq >= 0) |
1da177e4 | 2250 | free_irq(chip->irq, (void*)chip); |
68e7fffc | 2251 | if (chip->msi) |
30b35399 | 2252 | pci_disable_msi(chip->pci); |
f079c25a TI |
2253 | if (chip->remap_addr) |
2254 | iounmap(chip->remap_addr); | |
1da177e4 | 2255 | |
4ce107b9 TI |
2256 | if (chip->azx_dev) { |
2257 | for (i = 0; i < chip->num_streams; i++) | |
2258 | if (chip->azx_dev[i].bdl.area) | |
2259 | snd_dma_free_pages(&chip->azx_dev[i].bdl); | |
2260 | } | |
1da177e4 LT |
2261 | if (chip->rb.area) |
2262 | snd_dma_free_pages(&chip->rb); | |
1da177e4 LT |
2263 | if (chip->posbuf.area) |
2264 | snd_dma_free_pages(&chip->posbuf); | |
1da177e4 LT |
2265 | pci_release_regions(chip->pci); |
2266 | pci_disable_device(chip->pci); | |
07e4ca50 | 2267 | kfree(chip->azx_dev); |
1da177e4 LT |
2268 | kfree(chip); |
2269 | ||
2270 | return 0; | |
2271 | } | |
2272 | ||
a98f90fd | 2273 | static int azx_dev_free(struct snd_device *device) |
1da177e4 LT |
2274 | { |
2275 | return azx_free(device->device_data); | |
2276 | } | |
2277 | ||
3372a153 TI |
2278 | /* |
2279 | * white/black-listing for position_fix | |
2280 | */ | |
623ec047 | 2281 | static struct snd_pci_quirk position_fix_list[] __devinitdata = { |
7a68be94 | 2282 | SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB), |
d2e1c973 TI |
2283 | SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), |
2284 | SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), | |
9919c761 | 2285 | SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB), |
2f703e7a | 2286 | SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), |
0708cc58 | 2287 | SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB), |
d2e1c973 | 2288 | SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), |
9ec8ddad | 2289 | SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), |
45d4ebf1 | 2290 | SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), |
0321b695 | 2291 | SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB), |
8815cd03 | 2292 | SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), |
0e0280dc | 2293 | SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), |
572c0e3c | 2294 | SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB), |
3372a153 TI |
2295 | {} |
2296 | }; | |
2297 | ||
2298 | static int __devinit check_position_fix(struct azx *chip, int fix) | |
2299 | { | |
2300 | const struct snd_pci_quirk *q; | |
2301 | ||
c673ba1c TI |
2302 | switch (fix) { |
2303 | case POS_FIX_LPIB: | |
2304 | case POS_FIX_POSBUF: | |
2305 | return fix; | |
2306 | } | |
2307 | ||
2308 | /* Check VIA/ATI HD Audio Controller exist */ | |
2309 | switch (chip->driver_type) { | |
2310 | case AZX_DRIVER_VIA: | |
2311 | case AZX_DRIVER_ATI: | |
0e153474 JC |
2312 | chip->via_dmapos_patch = 1; |
2313 | /* Use link position directly, avoid any transfer problem. */ | |
2314 | return POS_FIX_LPIB; | |
2315 | } | |
2316 | chip->via_dmapos_patch = 0; | |
2317 | ||
c673ba1c TI |
2318 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); |
2319 | if (q) { | |
2320 | printk(KERN_INFO | |
2321 | "hda_intel: position_fix set to %d " | |
2322 | "for device %04x:%04x\n", | |
2323 | q->value, q->subvendor, q->subdevice); | |
2324 | return q->value; | |
3372a153 | 2325 | } |
c673ba1c | 2326 | return POS_FIX_AUTO; |
3372a153 TI |
2327 | } |
2328 | ||
669ba27a TI |
2329 | /* |
2330 | * black-lists for probe_mask | |
2331 | */ | |
2332 | static struct snd_pci_quirk probe_mask_list[] __devinitdata = { | |
2333 | /* Thinkpad often breaks the controller communication when accessing | |
2334 | * to the non-working (or non-existing) modem codec slot. | |
2335 | */ | |
2336 | SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), | |
2337 | SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), | |
2338 | SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), | |
0edb9454 TI |
2339 | /* broken BIOS */ |
2340 | SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), | |
ef1681d8 TI |
2341 | /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ |
2342 | SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), | |
20db7cb0 | 2343 | /* forced codec slots */ |
93574844 | 2344 | SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), |
20db7cb0 | 2345 | SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), |
669ba27a TI |
2346 | {} |
2347 | }; | |
2348 | ||
f1eaaeec TI |
2349 | #define AZX_FORCE_CODEC_MASK 0x100 |
2350 | ||
5aba4f8e | 2351 | static void __devinit check_probe_mask(struct azx *chip, int dev) |
669ba27a TI |
2352 | { |
2353 | const struct snd_pci_quirk *q; | |
2354 | ||
f1eaaeec TI |
2355 | chip->codec_probe_mask = probe_mask[dev]; |
2356 | if (chip->codec_probe_mask == -1) { | |
669ba27a TI |
2357 | q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); |
2358 | if (q) { | |
2359 | printk(KERN_INFO | |
2360 | "hda_intel: probe_mask set to 0x%x " | |
2361 | "for device %04x:%04x\n", | |
2362 | q->value, q->subvendor, q->subdevice); | |
f1eaaeec | 2363 | chip->codec_probe_mask = q->value; |
669ba27a TI |
2364 | } |
2365 | } | |
f1eaaeec TI |
2366 | |
2367 | /* check forced option */ | |
2368 | if (chip->codec_probe_mask != -1 && | |
2369 | (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { | |
2370 | chip->codec_mask = chip->codec_probe_mask & 0xff; | |
2371 | printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", | |
2372 | chip->codec_mask); | |
2373 | } | |
669ba27a TI |
2374 | } |
2375 | ||
4d8e22e0 | 2376 | /* |
71623855 | 2377 | * white/black-list for enable_msi |
4d8e22e0 | 2378 | */ |
71623855 | 2379 | static struct snd_pci_quirk msi_black_list[] __devinitdata = { |
9dc8398b | 2380 | SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ |
0a27fcfa | 2381 | SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ |
ecd21626 | 2382 | SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ |
4193d13b | 2383 | SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ |
3815595e | 2384 | SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ |
4d8e22e0 TI |
2385 | {} |
2386 | }; | |
2387 | ||
2388 | static void __devinit check_msi(struct azx *chip) | |
2389 | { | |
2390 | const struct snd_pci_quirk *q; | |
2391 | ||
71623855 TI |
2392 | if (enable_msi >= 0) { |
2393 | chip->msi = !!enable_msi; | |
4d8e22e0 | 2394 | return; |
71623855 TI |
2395 | } |
2396 | chip->msi = 1; /* enable MSI as default */ | |
2397 | q = snd_pci_quirk_lookup(chip->pci, msi_black_list); | |
4d8e22e0 TI |
2398 | if (q) { |
2399 | printk(KERN_INFO | |
2400 | "hda_intel: msi for device %04x:%04x set to %d\n", | |
2401 | q->subvendor, q->subdevice, q->value); | |
2402 | chip->msi = q->value; | |
80c43ed7 TI |
2403 | return; |
2404 | } | |
2405 | ||
2406 | /* NVidia chipsets seem to cause troubles with MSI */ | |
2407 | if (chip->driver_type == AZX_DRIVER_NVIDIA) { | |
2408 | printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n"); | |
2409 | chip->msi = 0; | |
4d8e22e0 TI |
2410 | } |
2411 | } | |
2412 | ||
669ba27a | 2413 | |
1da177e4 LT |
2414 | /* |
2415 | * constructor | |
2416 | */ | |
a98f90fd | 2417 | static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, |
5aba4f8e | 2418 | int dev, int driver_type, |
a98f90fd | 2419 | struct azx **rchip) |
1da177e4 | 2420 | { |
a98f90fd | 2421 | struct azx *chip; |
4ce107b9 | 2422 | int i, err; |
bcd72003 | 2423 | unsigned short gcap; |
a98f90fd | 2424 | static struct snd_device_ops ops = { |
1da177e4 LT |
2425 | .dev_free = azx_dev_free, |
2426 | }; | |
2427 | ||
2428 | *rchip = NULL; | |
bcd72003 | 2429 | |
927fc866 PM |
2430 | err = pci_enable_device(pci); |
2431 | if (err < 0) | |
1da177e4 LT |
2432 | return err; |
2433 | ||
e560d8d8 | 2434 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
927fc866 | 2435 | if (!chip) { |
1da177e4 LT |
2436 | snd_printk(KERN_ERR SFX "cannot allocate chip\n"); |
2437 | pci_disable_device(pci); | |
2438 | return -ENOMEM; | |
2439 | } | |
2440 | ||
2441 | spin_lock_init(&chip->reg_lock); | |
62932df8 | 2442 | mutex_init(&chip->open_mutex); |
1da177e4 LT |
2443 | chip->card = card; |
2444 | chip->pci = pci; | |
2445 | chip->irq = -1; | |
07e4ca50 | 2446 | chip->driver_type = driver_type; |
4d8e22e0 | 2447 | check_msi(chip); |
555e219f | 2448 | chip->dev_index = dev; |
9ad593f6 | 2449 | INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); |
1da177e4 | 2450 | |
beaffc39 SG |
2451 | chip->position_fix[0] = chip->position_fix[1] = |
2452 | check_position_fix(chip, position_fix[dev]); | |
5aba4f8e | 2453 | check_probe_mask(chip, dev); |
3372a153 | 2454 | |
27346166 | 2455 | chip->single_cmd = single_cmd; |
c74db86b | 2456 | |
5c0d7bc1 TI |
2457 | if (bdl_pos_adj[dev] < 0) { |
2458 | switch (chip->driver_type) { | |
0c6341ac | 2459 | case AZX_DRIVER_ICH: |
32679f95 | 2460 | case AZX_DRIVER_PCH: |
0c6341ac | 2461 | bdl_pos_adj[dev] = 1; |
5c0d7bc1 TI |
2462 | break; |
2463 | default: | |
0c6341ac | 2464 | bdl_pos_adj[dev] = 32; |
5c0d7bc1 TI |
2465 | break; |
2466 | } | |
2467 | } | |
2468 | ||
07e4ca50 TI |
2469 | #if BITS_PER_LONG != 64 |
2470 | /* Fix up base address on ULI M5461 */ | |
2471 | if (chip->driver_type == AZX_DRIVER_ULI) { | |
2472 | u16 tmp3; | |
2473 | pci_read_config_word(pci, 0x40, &tmp3); | |
2474 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); | |
2475 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); | |
2476 | } | |
2477 | #endif | |
2478 | ||
927fc866 PM |
2479 | err = pci_request_regions(pci, "ICH HD audio"); |
2480 | if (err < 0) { | |
1da177e4 LT |
2481 | kfree(chip); |
2482 | pci_disable_device(pci); | |
2483 | return err; | |
2484 | } | |
2485 | ||
927fc866 | 2486 | chip->addr = pci_resource_start(pci, 0); |
2f5ad54e | 2487 | chip->remap_addr = pci_ioremap_bar(pci, 0); |
1da177e4 LT |
2488 | if (chip->remap_addr == NULL) { |
2489 | snd_printk(KERN_ERR SFX "ioremap error\n"); | |
2490 | err = -ENXIO; | |
2491 | goto errout; | |
2492 | } | |
2493 | ||
68e7fffc TI |
2494 | if (chip->msi) |
2495 | if (pci_enable_msi(pci) < 0) | |
2496 | chip->msi = 0; | |
7376d013 | 2497 | |
68e7fffc | 2498 | if (azx_acquire_irq(chip, 0) < 0) { |
1da177e4 LT |
2499 | err = -EBUSY; |
2500 | goto errout; | |
2501 | } | |
1da177e4 LT |
2502 | |
2503 | pci_set_master(pci); | |
2504 | synchronize_irq(chip->irq); | |
2505 | ||
bcd72003 | 2506 | gcap = azx_readw(chip, GCAP); |
4abc1cc2 | 2507 | snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap); |
bcd72003 | 2508 | |
dc4c2e6b AB |
2509 | /* disable SB600 64bit support for safety */ |
2510 | if ((chip->driver_type == AZX_DRIVER_ATI) || | |
2511 | (chip->driver_type == AZX_DRIVER_ATIHDMI)) { | |
2512 | struct pci_dev *p_smbus; | |
2513 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, | |
2514 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
2515 | NULL); | |
2516 | if (p_smbus) { | |
2517 | if (p_smbus->revision < 0x30) | |
2518 | gcap &= ~ICH6_GCAP_64OK; | |
2519 | pci_dev_put(p_smbus); | |
2520 | } | |
2521 | } | |
09240cf4 | 2522 | |
396087ea JK |
2523 | /* disable 64bit DMA address for Teradici */ |
2524 | /* it does not work with device 6549:1200 subsys e4a2:040b */ | |
2525 | if (chip->driver_type == AZX_DRIVER_TERA) | |
2526 | gcap &= ~ICH6_GCAP_64OK; | |
2527 | ||
cf7aaca8 | 2528 | /* allow 64bit DMA address if supported by H/W */ |
b21fadb9 | 2529 | if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) |
e930438c | 2530 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); |
09240cf4 | 2531 | else { |
e930438c YH |
2532 | pci_set_dma_mask(pci, DMA_BIT_MASK(32)); |
2533 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); | |
09240cf4 | 2534 | } |
cf7aaca8 | 2535 | |
8b6ed8e7 TI |
2536 | /* read number of streams from GCAP register instead of using |
2537 | * hardcoded value | |
2538 | */ | |
2539 | chip->capture_streams = (gcap >> 8) & 0x0f; | |
2540 | chip->playback_streams = (gcap >> 12) & 0x0f; | |
2541 | if (!chip->playback_streams && !chip->capture_streams) { | |
bcd72003 TD |
2542 | /* gcap didn't give any info, switching to old method */ |
2543 | ||
2544 | switch (chip->driver_type) { | |
2545 | case AZX_DRIVER_ULI: | |
2546 | chip->playback_streams = ULI_NUM_PLAYBACK; | |
2547 | chip->capture_streams = ULI_NUM_CAPTURE; | |
bcd72003 TD |
2548 | break; |
2549 | case AZX_DRIVER_ATIHDMI: | |
2550 | chip->playback_streams = ATIHDMI_NUM_PLAYBACK; | |
2551 | chip->capture_streams = ATIHDMI_NUM_CAPTURE; | |
bcd72003 | 2552 | break; |
c4da29ca | 2553 | case AZX_DRIVER_GENERIC: |
bcd72003 TD |
2554 | default: |
2555 | chip->playback_streams = ICH6_NUM_PLAYBACK; | |
2556 | chip->capture_streams = ICH6_NUM_CAPTURE; | |
bcd72003 TD |
2557 | break; |
2558 | } | |
07e4ca50 | 2559 | } |
8b6ed8e7 TI |
2560 | chip->capture_index_offset = 0; |
2561 | chip->playback_index_offset = chip->capture_streams; | |
07e4ca50 | 2562 | chip->num_streams = chip->playback_streams + chip->capture_streams; |
d01ce99f TI |
2563 | chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), |
2564 | GFP_KERNEL); | |
927fc866 | 2565 | if (!chip->azx_dev) { |
4abc1cc2 | 2566 | snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n"); |
07e4ca50 TI |
2567 | goto errout; |
2568 | } | |
2569 | ||
4ce107b9 TI |
2570 | for (i = 0; i < chip->num_streams; i++) { |
2571 | /* allocate memory for the BDL for each stream */ | |
2572 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, | |
2573 | snd_dma_pci_data(chip->pci), | |
2574 | BDL_SIZE, &chip->azx_dev[i].bdl); | |
2575 | if (err < 0) { | |
2576 | snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); | |
2577 | goto errout; | |
2578 | } | |
1da177e4 | 2579 | } |
0be3b5d3 | 2580 | /* allocate memory for the position buffer */ |
d01ce99f TI |
2581 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, |
2582 | snd_dma_pci_data(chip->pci), | |
2583 | chip->num_streams * 8, &chip->posbuf); | |
2584 | if (err < 0) { | |
0be3b5d3 TI |
2585 | snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); |
2586 | goto errout; | |
1da177e4 | 2587 | } |
1da177e4 | 2588 | /* allocate CORB/RIRB */ |
81740861 TI |
2589 | err = azx_alloc_cmd_io(chip); |
2590 | if (err < 0) | |
2591 | goto errout; | |
1da177e4 LT |
2592 | |
2593 | /* initialize streams */ | |
2594 | azx_init_stream(chip); | |
2595 | ||
2596 | /* initialize chip */ | |
cb53c626 | 2597 | azx_init_pci(chip); |
10e77dda | 2598 | azx_init_chip(chip, (probe_only[dev] & 2) == 0); |
1da177e4 LT |
2599 | |
2600 | /* codec detection */ | |
927fc866 | 2601 | if (!chip->codec_mask) { |
1da177e4 LT |
2602 | snd_printk(KERN_ERR SFX "no codecs found!\n"); |
2603 | err = -ENODEV; | |
2604 | goto errout; | |
2605 | } | |
2606 | ||
d01ce99f TI |
2607 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); |
2608 | if (err <0) { | |
1da177e4 LT |
2609 | snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); |
2610 | goto errout; | |
2611 | } | |
2612 | ||
07e4ca50 | 2613 | strcpy(card->driver, "HDA-Intel"); |
18cb7109 TI |
2614 | strlcpy(card->shortname, driver_short_names[chip->driver_type], |
2615 | sizeof(card->shortname)); | |
2616 | snprintf(card->longname, sizeof(card->longname), | |
2617 | "%s at 0x%lx irq %i", | |
2618 | card->shortname, chip->addr, chip->irq); | |
07e4ca50 | 2619 | |
1da177e4 LT |
2620 | *rchip = chip; |
2621 | return 0; | |
2622 | ||
2623 | errout: | |
2624 | azx_free(chip); | |
2625 | return err; | |
2626 | } | |
2627 | ||
cb53c626 TI |
2628 | static void power_down_all_codecs(struct azx *chip) |
2629 | { | |
2630 | #ifdef CONFIG_SND_HDA_POWER_SAVE | |
2631 | /* The codecs were powered up in snd_hda_codec_new(). | |
2632 | * Now all initialization done, so turn them down if possible | |
2633 | */ | |
2634 | struct hda_codec *codec; | |
2635 | list_for_each_entry(codec, &chip->bus->codec_list, list) { | |
2636 | snd_hda_power_down(codec); | |
2637 | } | |
2638 | #endif | |
2639 | } | |
2640 | ||
d01ce99f TI |
2641 | static int __devinit azx_probe(struct pci_dev *pci, |
2642 | const struct pci_device_id *pci_id) | |
1da177e4 | 2643 | { |
5aba4f8e | 2644 | static int dev; |
a98f90fd TI |
2645 | struct snd_card *card; |
2646 | struct azx *chip; | |
927fc866 | 2647 | int err; |
1da177e4 | 2648 | |
5aba4f8e TI |
2649 | if (dev >= SNDRV_CARDS) |
2650 | return -ENODEV; | |
2651 | if (!enable[dev]) { | |
2652 | dev++; | |
2653 | return -ENOENT; | |
2654 | } | |
2655 | ||
e58de7ba TI |
2656 | err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); |
2657 | if (err < 0) { | |
1da177e4 | 2658 | snd_printk(KERN_ERR SFX "Error creating card!\n"); |
e58de7ba | 2659 | return err; |
1da177e4 LT |
2660 | } |
2661 | ||
4ea6fbc8 TI |
2662 | /* set this here since it's referred in snd_hda_load_patch() */ |
2663 | snd_card_set_dev(card, &pci->dev); | |
2664 | ||
5aba4f8e | 2665 | err = azx_create(card, pci, dev, pci_id->driver_data, &chip); |
41dda0fd WF |
2666 | if (err < 0) |
2667 | goto out_free; | |
421a1252 | 2668 | card->private_data = chip; |
1da177e4 | 2669 | |
2dca0bba JK |
2670 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
2671 | chip->beep_mode = beep_mode[dev]; | |
2672 | #endif | |
2673 | ||
1da177e4 | 2674 | /* create codec instances */ |
a1e21c90 | 2675 | err = azx_codec_create(chip, model[dev]); |
41dda0fd WF |
2676 | if (err < 0) |
2677 | goto out_free; | |
4ea6fbc8 TI |
2678 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
2679 | if (patch[dev]) { | |
2680 | snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n", | |
2681 | patch[dev]); | |
2682 | err = snd_hda_load_patch(chip->bus, patch[dev]); | |
2683 | if (err < 0) | |
2684 | goto out_free; | |
2685 | } | |
2686 | #endif | |
10e77dda | 2687 | if ((probe_only[dev] & 1) == 0) { |
a1e21c90 TI |
2688 | err = azx_codec_configure(chip); |
2689 | if (err < 0) | |
2690 | goto out_free; | |
2691 | } | |
1da177e4 LT |
2692 | |
2693 | /* create PCM streams */ | |
176d5335 | 2694 | err = snd_hda_build_pcms(chip->bus); |
41dda0fd WF |
2695 | if (err < 0) |
2696 | goto out_free; | |
1da177e4 LT |
2697 | |
2698 | /* create mixer controls */ | |
d01ce99f | 2699 | err = azx_mixer_create(chip); |
41dda0fd WF |
2700 | if (err < 0) |
2701 | goto out_free; | |
1da177e4 | 2702 | |
d01ce99f | 2703 | err = snd_card_register(card); |
41dda0fd WF |
2704 | if (err < 0) |
2705 | goto out_free; | |
1da177e4 LT |
2706 | |
2707 | pci_set_drvdata(pci, card); | |
cb53c626 TI |
2708 | chip->running = 1; |
2709 | power_down_all_codecs(chip); | |
0cbf0098 | 2710 | azx_notifier_register(chip); |
1da177e4 | 2711 | |
e25bcdba | 2712 | dev++; |
1da177e4 | 2713 | return err; |
41dda0fd WF |
2714 | out_free: |
2715 | snd_card_free(card); | |
2716 | return err; | |
1da177e4 LT |
2717 | } |
2718 | ||
2719 | static void __devexit azx_remove(struct pci_dev *pci) | |
2720 | { | |
2721 | snd_card_free(pci_get_drvdata(pci)); | |
2722 | pci_set_drvdata(pci, NULL); | |
2723 | } | |
2724 | ||
2725 | /* PCI IDs */ | |
cebe41d4 | 2726 | static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { |
87218e9c TI |
2727 | /* ICH 6..10 */ |
2728 | { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH }, | |
2729 | { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH }, | |
2730 | { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH }, | |
2731 | { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH }, | |
abbc9d1b | 2732 | { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH }, |
87218e9c TI |
2733 | { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH }, |
2734 | { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH }, | |
2735 | { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH }, | |
2736 | { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH }, | |
b29c2360 SH |
2737 | /* PCH */ |
2738 | { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH }, | |
c602c8ad | 2739 | { PCI_DEVICE(0x8086, 0x3b57), .driver_data = AZX_DRIVER_ICH }, |
d2f2fcd2 | 2740 | /* CPT */ |
32679f95 | 2741 | { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH }, |
87218e9c TI |
2742 | /* SCH */ |
2743 | { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH }, | |
2744 | /* ATI SB 450/600 */ | |
2745 | { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI }, | |
2746 | { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI }, | |
2747 | /* ATI HDMI */ | |
2748 | { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2749 | { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2750 | { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI }, | |
9e6dd47b | 2751 | { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI }, |
87218e9c TI |
2752 | { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI }, |
2753 | { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2754 | { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2755 | { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2756 | { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2757 | { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2758 | { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2759 | { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2760 | { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2761 | { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI }, | |
2762 | /* VIA VT8251/VT8237A */ | |
2763 | { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, | |
2764 | /* SIS966 */ | |
2765 | { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, | |
2766 | /* ULI M5461 */ | |
2767 | { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, | |
2768 | /* NVIDIA MCP */ | |
0c2fd1bf TI |
2769 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), |
2770 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2771 | .class_mask = 0xffffff, | |
2772 | .driver_data = AZX_DRIVER_NVIDIA }, | |
f269002e KY |
2773 | /* Teradici */ |
2774 | { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA }, | |
4e01f54b | 2775 | /* Creative X-Fi (CA0110-IBG) */ |
313f6e2d TI |
2776 | #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE) |
2777 | /* the following entry conflicts with snd-ctxfi driver, | |
2778 | * as ctxfi driver mutates from HD-audio to native mode with | |
2779 | * a special command sequence. | |
2780 | */ | |
4e01f54b TI |
2781 | { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), |
2782 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2783 | .class_mask = 0xffffff, | |
2784 | .driver_data = AZX_DRIVER_GENERIC }, | |
313f6e2d TI |
2785 | #else |
2786 | /* this entry seems still valid -- i.e. without emu20kx chip */ | |
2787 | { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC }, | |
2788 | #endif | |
9176b672 | 2789 | /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ |
c4da29ca YL |
2790 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), |
2791 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2792 | .class_mask = 0xffffff, | |
2793 | .driver_data = AZX_DRIVER_GENERIC }, | |
9176b672 AB |
2794 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), |
2795 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2796 | .class_mask = 0xffffff, | |
2797 | .driver_data = AZX_DRIVER_GENERIC }, | |
1da177e4 LT |
2798 | { 0, } |
2799 | }; | |
2800 | MODULE_DEVICE_TABLE(pci, azx_ids); | |
2801 | ||
2802 | /* pci_driver definition */ | |
2803 | static struct pci_driver driver = { | |
2804 | .name = "HDA Intel", | |
2805 | .id_table = azx_ids, | |
2806 | .probe = azx_probe, | |
2807 | .remove = __devexit_p(azx_remove), | |
421a1252 TI |
2808 | #ifdef CONFIG_PM |
2809 | .suspend = azx_suspend, | |
2810 | .resume = azx_resume, | |
2811 | #endif | |
1da177e4 LT |
2812 | }; |
2813 | ||
2814 | static int __init alsa_card_azx_init(void) | |
2815 | { | |
01d25d46 | 2816 | return pci_register_driver(&driver); |
1da177e4 LT |
2817 | } |
2818 | ||
2819 | static void __exit alsa_card_azx_exit(void) | |
2820 | { | |
2821 | pci_unregister_driver(&driver); | |
2822 | } | |
2823 | ||
2824 | module_init(alsa_card_azx_init) | |
2825 | module_exit(alsa_card_azx_exit) |