projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda: intel: Reduce CONFIG_PM dependencies
[linux-2.6-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
586bc4aa 38#include <linux/acpi.h>
65fddcfc 39#include <linux/pgtable.h>
5d890f59 40
27fe48d9
TI		 41#ifdef CONFIG_X86
42/* for snoop control */
7f80f513 43#include <asm/set_memory.h>
50279d9b 44#include <asm/cpufeature.h>
27fe48d9 45#endif
1da177e4
LT		 46#include <sound/core.h>
47#include <sound/initval.h>
98d8fc6c
ML		 48#include <sound/hdaudio.h>
49#include <sound/hda_i915.h>
82d9d54a 50#include <sound/intel-dsp-config.h>
9121947d 51#include <linux/vgaarb.h>
a82d51ed 52#include <linux/vga_switcheroo.h>
5beb5627 53#include <linux/apple-gmux.h>
4918cdab 54#include <linux/firmware.h>
be57bfff 55#include <sound/hda_codec.h>
05e84878 56#include "hda_controller.h"
347de1f8 57#include "hda_intel.h"
1da177e4 58
785d8c4b
LY		 59#define CREATE_TRACE_POINTS
60#include "hda_intel_trace.h"
61
b6050ef6
TI		 62/* position fix mode */
63enum {
64 POS_FIX_AUTO,
65 POS_FIX_LPIB,
66 POS_FIX_POSBUF,
67 POS_FIX_VIACOMBO,
68 POS_FIX_COMBO,
f87e7f25 69 POS_FIX_SKL,
c02f77d3 70 POS_FIX_FIFO,
b6050ef6
TI		 71};
72
9a34af4a
TI		 73/* Defines for ATI HD Audio support in SB450 south bridge */
74#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
75#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
76
77/* Defines for Nvidia HDA support */
78#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
79#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
80#define NVIDIA_HDA_ISTRM_COH 0x4d
81#define NVIDIA_HDA_OSTRM_COH 0x4c
82#define NVIDIA_HDA_ENABLE_COHBIT 0x01
83
84/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 85#define INTEL_HDA_CGCTL 0x48
86#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 87#define INTEL_SCH_HDA_DEVC 0x78
88#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
89
33124929
TI		 90/* max number of SDs */
91/* ICH, ATI and VIA have 4 playback and 4 capture */
92#define ICH6_NUM_CAPTURE 4
93#define ICH6_NUM_PLAYBACK 4
94
95/* ULI has 6 playback and 5 capture */
96#define ULI_NUM_CAPTURE 5
97#define ULI_NUM_PLAYBACK 6
98
99/* ATI HDMI may have up to 8 playbacks and 0 capture */
100#define ATIHDMI_NUM_CAPTURE 0
101#define ATIHDMI_NUM_PLAYBACK 8
102
1da177e4 103
5aba4f8e
TI		 104static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
105static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 106static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 107static char *model[SNDRV_CARDS];
1dac6695 108static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 109static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 110static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 111static int probe_only[SNDRV_CARDS];
26a6cb6c 112static int jackpoll_ms[SNDRV_CARDS];
41438f13 113static int single_cmd = -1;
71623855 114static int enable_msi = -1;
4ea6fbc8
TI		 115#ifdef CONFIG_SND_HDA_PATCH_LOADER
116static char *patch[SNDRV_CARDS];
117#endif
2dca0bba 118#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 119static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 120 CONFIG_SND_HDA_INPUT_BEEP_MODE};
121#endif
7fba6aea 122static bool dmic_detect = 1;
d045bcef 123static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
1da177e4 124
5aba4f8e 125module_param_array(index, int, NULL, 0444);
1da177e4 126MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 127module_param_array(id, charp, NULL, 0444);
1da177e4 128MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 129module_param_array(enable, bool, NULL, 0444);
130MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
131module_param_array(model, charp, NULL, 0444);
1da177e4 132MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 133module_param_array(position_fix, int, NULL, 0444);
4cb36310 134MODULE_PARM_DESC(position_fix, "DMA pointer read method."
c02f77d3 135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
555e219f
TI		 136module_param_array(bdl_pos_adj, int, NULL, 0644);
137MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 138module_param_array(probe_mask, int, NULL, 0444);
606ad75f 139MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 140module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 141MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 142module_param_array(jackpoll_ms, int, NULL, 0444);
143MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 144module_param(single_cmd, bint, 0444);
d01ce99f
TI		 145MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
146 "(for debugging only).");
ac9ef6cf 147module_param(enable_msi, bint, 0444);
134a11f0 148MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 149#ifdef CONFIG_SND_HDA_PATCH_LOADER
150module_param_array(patch, charp, NULL, 0444);
151MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
152#endif
2dca0bba 153#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 154module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 155MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 156 "(0=off, 1=on) (default=1).");
2dca0bba 157#endif
7fba6aea
TI		 158module_param(dmic_detect, bool, 0444);
159MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
160 "(0=off, 1=on) (default=1); "
161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
d045bcef
JK		 162module_param(ctl_dev_id, bool, 0444);
163MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
606ad75f 164
83012a7c 165#ifdef CONFIG_PM
65fcd41d 166static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 167static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 168 .set = param_set_xint,
169 .get = param_get_int,
170};
171#define param_check_xint param_check_int
172
fee2fba3 173static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 174module_param(power_save, xint, 0644);
fee2fba3
TI		 175MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
176 "(in second, 0 = disable).");
1da177e4 177
40088dc4
TI		 178static bool pm_blacklist = true;
179module_param(pm_blacklist, bool, 0644);
6317e5eb 180MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
40088dc4 181
dee1b66c
TI		 182/* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
8fc24426
TI		 186static bool power_save_controller = 1;
187module_param(power_save_controller, bool, 0644);
dee1b66c 188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
32d7c6cd 189#else /* CONFIG_PM */
bb573928 190#define power_save 0
32d7c6cd
TI		 191#define pm_blacklist false
192#define power_save_controller false
83012a7c 193#endif /* CONFIG_PM */
dee1b66c 194
7bfe059e
TI		 195static int align_buffer_size = -1;
196module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 197MODULE_PARM_DESC(align_buffer_size,
198 "Force buffer and period sizes to be multiple of 128 bytes.");
199
27fe48d9 200#ifdef CONFIG_X86
7c732015
TI		 201static int hda_snoop = -1;
202module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 203MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 204#else
205#define hda_snoop true
27fe48d9
TI		 206#endif
207
208
1da177e4 209MODULE_LICENSE("GPL");
1da177e4
LT		 210MODULE_DESCRIPTION("Intel HDA driver");
211
a82d51ed 212#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 213#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 214#define SUPPORT_VGA_SWITCHEROO
215#endif
216#endif
217
218
1da177e4 219/*
1da177e4 220 */
1da177e4 221
07e4ca50
TI		 222/* driver types */
223enum {
224 AZX_DRIVER_ICH,
32679f95 225 AZX_DRIVER_PCH,
4979bca9 226 AZX_DRIVER_SCH,
a4b4793f 227 AZX_DRIVER_SKL,
fab1285a 228 AZX_DRIVER_HDMI,
07e4ca50 229 AZX_DRIVER_ATI,
778b6e1b 230 AZX_DRIVER_ATIHDMI,
1815b34a 231 AZX_DRIVER_ATIHDMI_NS,
c51e4310 232 AZX_DRIVER_GFHDMI,
07e4ca50
TI		 233 AZX_DRIVER_VIA,
234 AZX_DRIVER_SIS,
235 AZX_DRIVER_ULI,
da3fca21 236 AZX_DRIVER_NVIDIA,
f269002e 237 AZX_DRIVER_TERA,
14d34f16 238 AZX_DRIVER_CTX,
5ae763b1 239 AZX_DRIVER_CTHDA,
c563f473 240 AZX_DRIVER_CMEDIA,
b6fcab14 241 AZX_DRIVER_ZHAOXIN,
28bd137a 242 AZX_DRIVER_LOONGSON,
c4da29ca 243 AZX_DRIVER_GENERIC,
2f5983f2 244 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 245};
246
37e661ee
TI		 247#define azx_get_snoop_type(chip) \
248 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
249#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
250
b42b4afb
TI		 251/* quirks for old Intel chipsets */
252#define AZX_DCAPS_INTEL_ICH \
f34a4c9d 253 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 254
2ea3c6a2 255/* quirks for Intel PCH */
6603249d 256#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 257 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
f34a4c9d 258 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 259
dba9b7b6 260/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 261#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 262 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 263
55913110 264/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 265/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 266#define AZX_DCAPS_INTEL_PCH \
f5dac54d 267 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 268
6603249d 269/* HSW HDMI */
33499a15 270#define AZX_DCAPS_INTEL_HASWELL \
103884a3 271 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 272 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
f34a4c9d 273 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 274
54a0405d
LY		 275/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
276#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 277 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 278 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
f34a4c9d 279 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 280
40cc2392 281#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 282 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 283
2d846c74 284#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 285 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 286 AZX_DCAPS_I915_COMPONENT)
2d846c74 287
d6795827 288#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 289 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 290 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 291
2756d914 292#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
c87693da 293
9477c58e
TI		 294/* quirks for ATI SB / AMD Hudson */
295#define AZX_DCAPS_PRESET_ATI_SB \
f34a4c9d 296 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
37e661ee 297 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 298
299/* quirks for ATI/AMD HDMI */
300#define AZX_DCAPS_PRESET_ATI_HDMI \
f34a4c9d 301 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
db79afa1 302 AZX_DCAPS_NO_MSI64)
9477c58e 303
37e661ee
TI		 304/* quirks for ATI HDMI with snoop off */
305#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
306 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
307
c02f77d3
TI		 308/* quirks for AMD SB */
309#define AZX_DCAPS_PRESET_AMD_SB \
f34a4c9d 310 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
c0f1886d
TI		 311 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
312 AZX_DCAPS_RETRY_PROBE)
c02f77d3 313
9477c58e
TI		 314/* quirks for Nvidia */
315#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 316 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 317 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 318
5ae763b1 319#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 320 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 321 AZX_DCAPS_NO_64BIT |\
37e661ee 322 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 323
a82d51ed 324/*
2b760d88 325 * vga_switcheroo support
a82d51ed
TI		 326 */
327#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 328#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
dd23e1d5 329#define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
5cb543db
TI		 330#else
331#define use_vga_switcheroo(chip) 0
37a3a98e 332#define needs_eld_notify_link(chip) false
5cb543db
TI		 333#endif
334
bf82326f 335static const char * const driver_short_names[] = {
07e4ca50 336 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 337 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 338 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 339 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 340 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 341 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 342 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 343 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
c51e4310 344 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
07e4ca50
TI		 345 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
346 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 347 [AZX_DRIVER_ULI] = "HDA ULI M5461",
348 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 349 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 350 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 351 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 352 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
b6fcab14 353 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
28bd137a 354 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
c4da29ca 355 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 356};
357
68e7fffc 358static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 359static void set_default_power_save(struct azx *chip);
111d3af5 360
cb53c626
TI		 361/*
362 * initialize the PCI registers
363 */
364/* update bits in a PCI register byte */
365static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
366 unsigned char mask, unsigned char val)
367{
368 unsigned char data;
369
370 pci_read_config_byte(pci, reg, &data);
371 data &= ~mask;
372 data |= (val & mask);
373 pci_write_config_byte(pci, reg, data);
374}
375
376static void azx_init_pci(struct azx *chip)
377{
37e661ee
TI		 378 int snoop_type = azx_get_snoop_type(chip);
379
cb53c626
TI		 380 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
381 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
382 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 383 * codecs.
384 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 385 */
46f2cc80 386 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 387 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 388 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 389 }
cb53c626 390
9477c58e
TI		 391 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
392 * we need to enable snoop.
393 */
37e661ee 394 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 395 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
396 azx_snoop(chip));
cb53c626 397 update_pci_byte(chip->pci,
27fe48d9
TI		 398 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
399 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 400 }
401
402 /* For NVIDIA HDA, enable snoop */
37e661ee 403 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 404 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
405 azx_snoop(chip));
cb53c626
TI		 406 update_pci_byte(chip->pci,
407 NVIDIA_HDA_TRANSREG_ADDR,
408 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 409 update_pci_byte(chip->pci,
410 NVIDIA_HDA_ISTRM_COH,
411 0x01, NVIDIA_HDA_ENABLE_COHBIT);
412 update_pci_byte(chip->pci,
413 NVIDIA_HDA_OSTRM_COH,
414 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 415 }
416
417 /* Enable SCH/PCH snoop if needed */
37e661ee 418 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 419 unsigned short snoop;
90a5ad52 420 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 421 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
422 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
423 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
424 if (!azx_snoop(chip))
425 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
426 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 427 pci_read_config_word(chip->pci,
428 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 429 }
4e76a883
TI		 430 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
431 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
432 "Disabled" : "Enabled");
da3fca21 433 }
1da177e4
LT		 434}
435
7c23b7c1
LH		 436/*
437 * In BXT-P A0, HD-Audio DMA requests is later than expected,
438 * and makes an audio stream sensitive to system latencies when
439 * 24/32 bits are playing.
440 * Adjusting threshold of DMA fifo to force the DMA request
441 * sooner to improve latency tolerance at the expense of power.
442 */
443static void bxt_reduce_dma_latency(struct azx *chip)
444{
445 u32 val;
446
70eafad8 447 val = azx_readl(chip, VS_EM4L);
7c23b7c1 448 val &= (0x3 << 20);
70eafad8 449 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 450}
451
1f9d3d98
LY		 452/*
453 * ML_LCAP bits:
454 * bit 0: 6 MHz Supported
455 * bit 1: 12 MHz Supported
456 * bit 2: 24 MHz Supported
457 * bit 3: 48 MHz Supported
458 * bit 4: 96 MHz Supported
459 * bit 5: 192 MHz Supported
460 */
461static int intel_get_lctl_scf(struct azx *chip)
462{
463 struct hdac_bus *bus = azx_bus(chip);
bf82326f 464 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
1f9d3d98
LY		 465 u32 val, t;
466 int i;
467
468 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
469
470 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
471 t = preferred_bits[i];
472 if (val & (1 << t))
473 return t;
474 }
475
476 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
477 return 0;
478}
479
480static int intel_ml_lctl_set_power(struct azx *chip, int state)
481{
482 struct hdac_bus *bus = azx_bus(chip);
483 u32 val;
484 int timeout;
485
486 /*
10e794bd
PLB		 487 * Changes to LCTL.SCF are only needed for the first multi-link dealing
488 * with external codecs
1f9d3d98
LY		 489 */
490 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
18afcf90
PLB		 491 val &= ~AZX_ML_LCTL_SPA;
492 val |= state << AZX_ML_LCTL_SPA_SHIFT;
1f9d3d98
LY		 493 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
494 /* wait for CPA */
495 timeout = 50;
496 while (timeout) {
497 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
18afcf90 498 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
1f9d3d98
LY		 499 return 0;
500 timeout--;
501 udelay(10);
502 }
503
504 return -1;
505}
506
507static void intel_init_lctl(struct azx *chip)
508{
509 struct hdac_bus *bus = azx_bus(chip);
510 u32 val;
511 int ret;
512
513 /* 0. check lctl register value is correct or not */
514 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
10e794bd 515 /* only perform additional configurations if the SCF is initially based on 6MHz */
18afcf90 516 if ((val & AZX_ML_LCTL_SCF) != 0)
1f9d3d98
LY		 517 return;
518
519 /*
520 * Before operating on SPA, CPA must match SPA.
521 * Any deviation may result in undefined behavior.
522 */
18afcf90
PLB		 523 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
524 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
1f9d3d98
LY		 525 return;
526
527 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
528 ret = intel_ml_lctl_set_power(chip, 0);
529 udelay(100);
530 if (ret)
531 goto set_spa;
532
10e794bd 533 /* 2. update SCF to select an audio clock different from 6MHz */
18afcf90 534 val &= ~AZX_ML_LCTL_SCF;
1f9d3d98
LY		 535 val |= intel_get_lctl_scf(chip);
536 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
537
538set_spa:
539 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
540 intel_ml_lctl_set_power(chip, 1);
541 udelay(100);
542}
543
0a673521
LH		 544static void hda_intel_init_chip(struct azx *chip, bool full_reset)
545{
98d8fc6c 546 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 547 struct pci_dev *pci = chip->pci;
6639484d 548 u32 val;
0a673521 549
e454ff8e 550 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 551 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 552 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
553 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
554 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
555 }
0a673521 556 azx_init_chip(chip, full_reset);
a4b4793f 557 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 558 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
559 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
560 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
561 }
e454ff8e
TI		 562
563 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 564
565 /* reduce dma latency to avoid noise */
1b21bd7a 566 if (HDA_CONTROLLER_IS_APL(pci))
7c23b7c1 567 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 568
569 if (bus->mlcap != NULL)
570 intel_init_lctl(chip);
0a673521
LH		 571}
572
b6050ef6
TI		 573/* calculate runtime delay from LPIB */
574static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
575 unsigned int pos)
576{
7833c3f8 577 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 578 int stream = substream->stream;
579 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
580 int delay;
581
582 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
583 delay = pos - lpib_pos;
584 else
585 delay = lpib_pos - pos;
586 if (delay < 0) {
7833c3f8 587 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 588 delay = 0;
589 else
7833c3f8 590 delay += azx_dev->core.bufsize;
b6050ef6
TI		 591 }
592
7833c3f8 593 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 594 dev_info(chip->card->dev,
595 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 596 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 597 delay = 0;
598 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
599 chip->get_delay[stream] = NULL;
600 }
601
602 return bytes_to_frames(substream->runtime, delay);
603}
604
9ad593f6
TI		 605static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
606
7ca954a8
DR		 607/* called from IRQ */
608static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
609{
9a34af4a 610 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 611 int ok;
612
613 ok = azx_position_ok(chip, azx_dev);
614 if (ok == 1) {
615 azx_dev->irq_pending = 0;
616 return ok;
2f35c630 617 } else if (ok == 0) {
7ca954a8
DR		 618 /* bogus IRQ, process it later */
619 azx_dev->irq_pending = 1;
2f35c630 620 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 621 }
622 return 0;
623}
624
029d92c2
TI		 625#define display_power(chip, enable) \
626 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 627
9ad593f6
TI		 628/*
629 * Check whether the current DMA position is acceptable for updating
630 * periods. Returns non-zero if it's OK.
631 *
632 * Many HD-audio controllers appear pretty inaccurate about
633 * the update-IRQ timing. The IRQ is issued before actually the
634 * data is processed. So, we need to process it afterwords in a
635 * workqueue.
46243b85
TI		 636 *
637 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
9ad593f6
TI		 638 */
639static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
640{
7833c3f8 641 struct snd_pcm_substream *substream = azx_dev->core.substream;
46243b85 642 struct snd_pcm_runtime *runtime = substream->runtime;
b6050ef6 643 int stream = substream->stream;
e5463720 644 u32 wallclk;
9ad593f6 645 unsigned int pos;
46243b85 646 snd_pcm_uframes_t hwptr, target;
9ad593f6 647
a4d2b853
YS		 648 /*
649 * The value of the WALLCLK register is always 0
650 * on the Loongson controller, so we return directly.
651 */
652 if (chip->driver_type == AZX_DRIVER_LOONGSON)
653 return 1;
654
7833c3f8
TI		 655 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
656 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 657 return -1; /* bogus (too early) interrupt */
fa00e046 658
b6050ef6
TI		 659 if (chip->get_position[stream])
660 pos = chip->get_position[stream](chip, azx_dev);
661 else { /* use the position buffer as default */
662 pos = azx_get_pos_posbuf(chip, azx_dev);
663 if (!pos || pos == (u32)-1) {
664 dev_info(chip->card->dev,
665 "Invalid position buffer, using LPIB read method instead.\n");
666 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 667 if (chip->get_position[0] == azx_get_pos_lpib &&
668 chip->get_position[1] == azx_get_pos_lpib)
669 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 670 pos = azx_get_pos_lpib(chip, azx_dev);
671 chip->get_delay[stream] = NULL;
672 } else {
673 chip->get_position[stream] = azx_get_pos_posbuf;
674 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
675 chip->get_delay[stream] = azx_get_delay_from_lpib;
676 }
677 }
678
7833c3f8 679 if (pos >= azx_dev->core.bufsize)
b6050ef6 680 pos = 0;
9ad593f6 681
7833c3f8 682 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 683 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 684 return -1; /* this shouldn't happen! */
7833c3f8
TI		 685 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
686 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 687 /* NG - it's below the first next period boundary */
4f0189be 688 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 689 azx_dev->core.start_wallclk += wallclk;
46243b85
TI		 690
691 if (azx_dev->core.no_period_wakeup)
692 return 1; /* OK, no need to check period boundary */
693
694 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
695 return 1; /* OK, already in hwptr updating process */
696
697 /* check whether the period gets really elapsed */
698 pos = bytes_to_frames(runtime, pos);
699 hwptr = runtime->hw_ptr_base + pos;
700 if (hwptr < runtime->status->hw_ptr)
701 hwptr += runtime->buffer_size;
702 target = runtime->hw_ptr_interrupt + runtime->period_size;
703 if (hwptr < target) {
704 /* too early wakeup, process it later */
705 return chip->bdl_pos_adj ? 0 : -1;
706 }
707
9ad593f6
TI		 708 return 1; /* OK, it's fine */
709}
710
711/*
712 * The work for pending PCM period updates.
713 */
714static void azx_irq_pending_work(struct work_struct *work)
715{
9a34af4a
TI		 716 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
717 struct azx *chip = &hda->chip;
7833c3f8
TI		 718 struct hdac_bus *bus = azx_bus(chip);
719 struct hdac_stream *s;
720 int pending, ok;
9ad593f6 721
9a34af4a 722 if (!hda->irq_pending_warned) {
4e76a883
TI		 723 dev_info(chip->card->dev,
724 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
725 chip->card->number);
9a34af4a 726 hda->irq_pending_warned = 1;
a6a950a8
TI		 727 }
728
9ad593f6
TI		 729 for (;;) {
730 pending = 0;
a41d1224 731 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 732 list_for_each_entry(s, &bus->stream_list, list) {
733 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 734 if (!azx_dev->irq_pending ||
7833c3f8
TI		 735 !s->substream ||
736 !s->running)
9ad593f6 737 continue;
e5463720
JK		 738 ok = azx_position_ok(chip, azx_dev);
739 if (ok > 0) {
9ad593f6 740 azx_dev->irq_pending = 0;
a41d1224 741 spin_unlock(&bus->reg_lock);
7833c3f8 742 snd_pcm_period_elapsed(s->substream);
a41d1224 743 spin_lock(&bus->reg_lock);
e5463720
JK		 744 } else if (ok < 0) {
745 pending = 0; /* too early */
9ad593f6
TI		 746 } else
747 pending++;
748 }
a41d1224 749 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 750 if (!pending)
751 return;
08af495f 752 msleep(1);
9ad593f6
TI		 753 }
754}
755
756/* clear irq_pending flags and assure no on-going workq */
757static void azx_clear_irq_pending(struct azx *chip)
758{
7833c3f8
TI		 759 struct hdac_bus *bus = azx_bus(chip);
760 struct hdac_stream *s;
9ad593f6 761
a41d1224 762 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 763 list_for_each_entry(s, &bus->stream_list, list) {
764 struct azx_dev *azx_dev = stream_to_azx_dev(s);
765 azx_dev->irq_pending = 0;
766 }
a41d1224 767 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 768}
769
68e7fffc
TI		 770static int azx_acquire_irq(struct azx *chip, int do_disconnect)
771{
a41d1224
TI		 772 struct hdac_bus *bus = azx_bus(chip);
773
437a5a46
TI		 774 if (request_irq(chip->pci->irq, azx_interrupt,
775 chip->msi ? 0 : IRQF_SHARED,
de65360b 776 chip->card->irq_descr, chip)) {
4e76a883
TI		 777 dev_err(chip->card->dev,
778 "unable to grab IRQ %d, disabling device\n",
779 chip->pci->irq);
68e7fffc
TI		 780 if (do_disconnect)
781 snd_card_disconnect(chip->card);
782 return -1;
783 }
a41d1224 784 bus->irq = chip->pci->irq;
f36da940 785 chip->card->sync_irq = bus->irq;
69e13418 786 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 787 return 0;
788}
789
b6050ef6
TI		 790/* get the current DMA position with correction on VIA chips */
791static unsigned int azx_via_get_position(struct azx *chip,
792 struct azx_dev *azx_dev)
793{
794 unsigned int link_pos, mini_pos, bound_pos;
795 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
796 unsigned int fifo_size;
797
1604eeee 798 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 799 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 800 /* Playback, no problem using link position */
801 return link_pos;
802 }
803
804 /* Capture */
805 /* For new chipset,
806 * use mod to get the DMA position just like old chipset
807 */
7833c3f8
TI		 808 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
809 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6 810
956b610c 811 fifo_size = azx_stream(azx_dev)->fifo_size;
b6050ef6
TI		 812
813 if (azx_dev->insufficient) {
814 /* Link position never gather than FIFO size */
815 if (link_pos <= fifo_size)
816 return 0;
817
818 azx_dev->insufficient = 0;
819 }
820
821 if (link_pos <= fifo_size)
7833c3f8 822 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 823 else
824 mini_pos = link_pos - fifo_size;
825
826 /* Find nearest previous boudary */
7833c3f8
TI		 827 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
828 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 829 if (mod_link_pos >= fifo_size)
830 bound_pos = link_pos - mod_link_pos;
831 else if (mod_dma_pos >= mod_mini_pos)
832 bound_pos = mini_pos - mod_mini_pos;
833 else {
7833c3f8
TI		 834 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
835 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 836 bound_pos = 0;
837 }
838
839 /* Calculate real DMA position we want */
840 return bound_pos + mod_dma_pos;
841}
842
c02f77d3
TI		 843#define AMD_FIFO_SIZE 32
844
845/* get the current DMA position with FIFO size correction */
846static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
847{
848 struct snd_pcm_substream *substream = azx_dev->core.substream;
849 struct snd_pcm_runtime *runtime = substream->runtime;
850 unsigned int pos, delay;
851
852 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
853 if (!runtime)
854 return pos;
855
856 runtime->delay = AMD_FIFO_SIZE;
857 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
858 if (azx_dev->insufficient) {
859 if (pos < delay) {
860 delay = pos;
861 runtime->delay = bytes_to_frames(runtime, pos);
862 } else {
863 azx_dev->insufficient = 0;
864 }
865 }
866
867 /* correct the DMA position for capture stream */
868 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
869 if (pos < delay)
870 pos += azx_dev->core.bufsize;
871 pos -= delay;
872 }
873
874 return pos;
875}
876
877static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
878 unsigned int pos)
879{
880 struct snd_pcm_substream *substream = azx_dev->core.substream;
881
882 /* just read back the calculated value in the above */
883 return substream->runtime->delay;
884}
885
6f445784 886static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
472e18f6
ID		 887{
888 azx_stop_chip(chip);
6f445784
TI		 889 if (!skip_link_reset)
890 azx_enter_link_reset(chip);
472e18f6
ID		 891 azx_clear_irq_pending(chip);
892 display_power(chip, false);
893}
894
65fcd41d
TI		 895static DEFINE_MUTEX(card_list_lock);
896static LIST_HEAD(card_list);
897
6f445784
TI		 898static void azx_shutdown_chip(struct azx *chip)
899{
900 __azx_shutdown_chip(chip, false);
901}
902
65fcd41d
TI		 903static void azx_add_card_list(struct azx *chip)
904{
9a34af4a 905 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 906 mutex_lock(&card_list_lock);
9a34af4a 907 list_add(&hda->list, &card_list);
65fcd41d
TI		 908 mutex_unlock(&card_list_lock);
909}
910
911static void azx_del_card_list(struct azx *chip)
912{
9a34af4a 913 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 914 mutex_lock(&card_list_lock);
9a34af4a 915 list_del_init(&hda->list);
65fcd41d
TI		 916 mutex_unlock(&card_list_lock);
917}
918
919/* trigger power-save check at writing parameter */
32d7c6cd 920static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp)
65fcd41d 921{
9a34af4a 922 struct hda_intel *hda;
65fcd41d 923 struct azx *chip;
65fcd41d
TI		 924 int prev = power_save;
925 int ret = param_set_int(val, kp);
926
927 if (ret || prev == power_save)
928 return ret;
929
930 mutex_lock(&card_list_lock);
9a34af4a
TI		 931 list_for_each_entry(hda, &card_list, list) {
932 chip = &hda->chip;
a41d1224 933 if (!hda->probe_continued || chip->disabled)
65fcd41d 934 continue;
a41d1224 935 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 936 }
937 mutex_unlock(&card_list_lock);
938 return 0;
939}
5c0b9bec 940
5c0b9bec
TI		 941/*
942 * power management
943 */
3baffc4a 944static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 945{
2d9772ef
TI		 946 struct azx *chip;
947 struct hda_intel *hda;
1da177e4 948
2d9772ef 949 if (!card)
3baffc4a 950 return false;
2d9772ef
TI		 951 chip = card->private_data;
952 hda = container_of(chip, struct hda_intel, chip);
342e8449 953 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 954 return false;
955 return true;
956}
957
f5dac54d 958static void __azx_runtime_resume(struct azx *chip)
3baffc4a
TI		 959{
960 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
961 struct hdac_bus *bus = azx_bus(chip);
962 struct hda_codec *codec;
963 int status;
964
e454ff8e
TI		 965 display_power(chip, true);
966 if (hda->need_i915_power)
967 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 968
969 /* Read STATESTS before controller reset */
970 status = azx_readw(chip, STATESTS);
971
972 azx_init_pci(chip);
973 hda_intel_init_chip(chip, true);
974
f5dac54d
KHF		 975 /* Avoid codec resume if runtime resume is for system suspend */
976 if (!chip->pm_prepared) {
a6e7d0a4
KV		 977 list_for_each_codec(codec, &chip->bus) {
978 if (codec->relaxed_resume)
979 continue;
980
981 if (codec->forced_resume || (status & (1 << codec->addr)))
982 pm_request_resume(hda_codec_dev(codec));
983 }
3baffc4a
TI		 984 }
985
986 /* power down again for link-controlled chips */
e454ff8e 987 if (!hda->need_i915_power)
029d92c2 988 display_power(chip, false);
3baffc4a
TI		 989}
990
f5dac54d
KHF		 991static int azx_prepare(struct device *dev)
992{
993 struct snd_card *card = dev_get_drvdata(dev);
994 struct azx *chip;
995
66affb7b
TI		 996 if (!azx_is_pm_ready(card))
997 return 0;
998
f5dac54d
KHF		 999 chip = card->private_data;
1000 chip->pm_prepared = 1;
c8f79808 1001 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
f5dac54d 1002
13661fc4
TI		 1003 flush_work(&azx_bus(chip)->unsol_work);
1004
f5dac54d
KHF		 1005 /* HDA controller always requires different WAKEEN for runtime suspend
1006 * and system suspend, so don't use direct-complete here.
1007 */
1008 return 0;
1009}
1010
1011static void azx_complete(struct device *dev)
1012{
1013 struct snd_card *card = dev_get_drvdata(dev);
1014 struct azx *chip;
1015
66affb7b
TI		 1016 if (!azx_is_pm_ready(card))
1017 return;
1018
f5dac54d 1019 chip = card->private_data;
c8f79808 1020 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
f5dac54d
KHF		 1021 chip->pm_prepared = 0;
1022}
1023
3baffc4a
TI		 1024static int azx_suspend(struct device *dev)
1025{
1026 struct snd_card *card = dev_get_drvdata(dev);
1027 struct azx *chip;
1028 struct hdac_bus *bus;
1029
1030 if (!azx_is_pm_ready(card))
c5c21523
TI		 1031 return 0;
1032
3baffc4a 1033 chip = card->private_data;
a41d1224 1034 bus = azx_bus(chip);
472e18f6 1035 azx_shutdown_chip(chip);
a41d1224
TI		 1036 if (bus->irq >= 0) {
1037 free_irq(bus->irq, chip);
1038 bus->irq = -1;
f36da940 1039 chip->card->sync_irq = -1;
30b35399 1040 }
a07187c9 1041
68e7fffc 1042 if (chip->msi)
43001c95 1043 pci_disable_msi(chip->pci);
785d8c4b
LY		 1044
1045 trace_azx_suspend(chip);
1da177e4
LT		 1046 return 0;
1047}
1048
32d7c6cd 1049static int __maybe_unused azx_resume(struct device *dev)
1da177e4 1050{
68cb2b55 1051 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1052 struct azx *chip;
2d9772ef 1053
3baffc4a 1054 if (!azx_is_pm_ready(card))
2d9772ef 1055 return 0;
1da177e4 1056
2d9772ef 1057 chip = card->private_data;
68e7fffc 1058 if (chip->msi)
3baffc4a 1059 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1060 chip->msi = 0;
1061 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1062 return -EIO;
c4c8dd6e 1063
f5dac54d 1064 __azx_runtime_resume(chip);
785d8c4b
LY		 1065
1066 trace_azx_resume(chip);
1da177e4
LT		 1067 return 0;
1068}
b8dfc462 1069
3e6db33a
XZ		 1070/* put codec down to D3 at hibernation for Intel SKL+;
1071 * otherwise BIOS may still access the codec and screw up the driver
1072 */
3e6db33a
XZ		 1073static int azx_freeze_noirq(struct device *dev)
1074{
a4b4793f
TI		 1075 struct snd_card *card = dev_get_drvdata(dev);
1076 struct azx *chip = card->private_data;
3e6db33a
XZ		 1077 struct pci_dev *pci = to_pci_dev(dev);
1078
10db5bcc
TI		 1079 if (!azx_is_pm_ready(card))
1080 return 0;
a4b4793f 1081 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1082 pci_set_power_state(pci, PCI_D3hot);
1083
1084 return 0;
1085}
1086
1087static int azx_thaw_noirq(struct device *dev)
1088{
a4b4793f
TI		 1089 struct snd_card *card = dev_get_drvdata(dev);
1090 struct azx *chip = card->private_data;
3e6db33a
XZ		 1091 struct pci_dev *pci = to_pci_dev(dev);
1092
10db5bcc
TI		 1093 if (!azx_is_pm_ready(card))
1094 return 0;
a4b4793f 1095 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1096 pci_set_power_state(pci, PCI_D0);
1097
1098 return 0;
1099}
3e6db33a 1100
32d7c6cd 1101static int __maybe_unused azx_runtime_suspend(struct device *dev)
b8dfc462
ML		 1102{
1103 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1104 struct azx *chip;
b8dfc462 1105
3baffc4a 1106 if (!azx_is_pm_ready(card))
2d9772ef 1107 return 0;
2d9772ef 1108 chip = card->private_data;
246efa4a 1109
7d4f606c 1110 /* enable controller wake up event */
f5dac54d 1111 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
7d4f606c 1112
472e18f6 1113 azx_shutdown_chip(chip);
785d8c4b 1114 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1115 return 0;
1116}
1117
32d7c6cd 1118static int __maybe_unused azx_runtime_resume(struct device *dev)
b8dfc462
ML		 1119{
1120 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1121 struct azx *chip;
b8dfc462 1122
3baffc4a 1123 if (!azx_is_pm_ready(card))
2d9772ef 1124 return 0;
2d9772ef 1125 chip = card->private_data;
f5dac54d 1126 __azx_runtime_resume(chip);
7d4f606c
WX		 1127
1128 /* disable controller Wake Up event*/
f5dac54d 1129 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
7d4f606c 1130
785d8c4b 1131 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1132 return 0;
1133}
6eb827d2 1134
32d7c6cd 1135static int __maybe_unused azx_runtime_idle(struct device *dev)
6eb827d2
TI		 1136{
1137 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1138 struct azx *chip;
1139 struct hda_intel *hda;
1140
1141 if (!card)
1142 return 0;
6eb827d2 1143
2d9772ef
TI		 1144 chip = card->private_data;
1145 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1146 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1147 return 0;
1148
55ed9cd1 1149 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1150 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1151 return -EBUSY;
1152
37a3a98e 1153 /* ELD notification gets broken when HD-audio bus is off */
dd23e1d5 1154 if (needs_eld_notify_link(chip))
37a3a98e
TI		 1155 return -EBUSY;
1156
6eb827d2
TI		 1157 return 0;
1158}
1159
b8dfc462 1160static const struct dev_pm_ops azx_pm = {
32d7c6cd
TI		 1161 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1162 .prepare = pm_sleep_ptr(azx_prepare),
1163 .complete = pm_sleep_ptr(azx_complete),
1164 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq),
1165 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq),
6eb827d2 1166 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1167};
1168
1da177e4 1169
48c8b0eb 1170static int azx_probe_continue(struct azx *chip);
a82d51ed 1171
8393ec4a 1172#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1173static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1174
a82d51ed
TI		 1175static void azx_vs_set_state(struct pci_dev *pci,
1176 enum vga_switcheroo_state state)
1177{
1178 struct snd_card *card = pci_get_drvdata(pci);
1179 struct azx *chip = card->private_data;
9a34af4a 1180 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1181 struct hda_codec *codec;
a82d51ed
TI		 1182 bool disabled;
1183
9a34af4a
TI		 1184 wait_for_completion(&hda->probe_wait);
1185 if (hda->init_failed)
a82d51ed
TI		 1186 return;
1187
1188 disabled = (state == VGA_SWITCHEROO_OFF);
1189 if (chip->disabled == disabled)
1190 return;
1191
a41d1224 1192 if (!hda->probe_continued) {
a82d51ed
TI		 1193 chip->disabled = disabled;
1194 if (!disabled) {
4e76a883
TI		 1195 dev_info(chip->card->dev,
1196 "Start delayed initialization\n");
2393e755 1197 if (azx_probe_continue(chip) < 0)
4e76a883 1198 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 1199 }
1200 } else {
2b760d88 1201 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1202 disabled ? "Disabling" : "Enabling");
a82d51ed 1203 if (disabled) {
07f4f97d
LW		 1204 list_for_each_codec(codec, &chip->bus) {
1205 pm_runtime_suspend(hda_codec_dev(codec));
1206 pm_runtime_disable(hda_codec_dev(codec));
1207 }
1208 pm_runtime_suspend(card->dev);
1209 pm_runtime_disable(card->dev);
2b760d88 1210 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1211 * however we have no ACPI handle, so pci/acpi can't put us there,
1212 * put ourselves there */
1213 pci->current_state = PCI_D3cold;
a82d51ed 1214 chip->disabled = true;
a41d1224 1215 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1216 dev_warn(chip->card->dev,
1217 "Cannot lock devices!\n");
a82d51ed 1218 } else {
a41d1224 1219 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1220 chip->disabled = false;
07f4f97d
LW		 1221 pm_runtime_enable(card->dev);
1222 list_for_each_codec(codec, &chip->bus) {
1223 pm_runtime_enable(hda_codec_dev(codec));
1224 pm_runtime_resume(hda_codec_dev(codec));
1225 }
a82d51ed
TI		 1226 }
1227 }
1228}
1229
1230static bool azx_vs_can_switch(struct pci_dev *pci)
1231{
1232 struct snd_card *card = pci_get_drvdata(pci);
1233 struct azx *chip = card->private_data;
9a34af4a 1234 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1235
9a34af4a
TI		 1236 wait_for_completion(&hda->probe_wait);
1237 if (hda->init_failed)
a82d51ed 1238 return false;
a41d1224 1239 if (chip->disabled || !hda->probe_continued)
a82d51ed 1240 return true;
a41d1224 1241 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1242 return false;
a41d1224 1243 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1244 return true;
1245}
1246
37a3a98e
TI		 1247/*
1248 * The discrete GPU cannot power down unless the HDA controller runtime
1249 * suspends, so activate runtime PM on codecs even if power_save == 0.
1250 */
1251static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1252{
1253 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1254 struct hda_codec *codec;
1255
dd23e1d5 1256 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
37a3a98e
TI		 1257 list_for_each_codec(codec, &chip->bus)
1258 codec->auto_runtime_pm = 1;
1259 /* reset the power save setup */
1260 if (chip->running)
1261 set_default_power_save(chip);
1262 }
1263}
1264
1265static void azx_vs_gpu_bound(struct pci_dev *pci,
1266 enum vga_switcheroo_client_id client_id)
1267{
1268 struct snd_card *card = pci_get_drvdata(pci);
1269 struct azx *chip = card->private_data;
37a3a98e
TI		 1270
1271 if (client_id == VGA_SWITCHEROO_DIS)
dd23e1d5 1272 chip->bus.keep_power = 0;
37a3a98e
TI		 1273 setup_vga_switcheroo_runtime_pm(chip);
1274}
1275
e23e7a14 1276static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1277{
9a34af4a 1278 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1279 struct pci_dev *p = get_bound_vga(chip->pci);
bacd8614 1280 struct pci_dev *parent;
a82d51ed 1281 if (p) {
4e76a883 1282 dev_info(chip->card->dev,
2b760d88 1283 "Handle vga_switcheroo audio client\n");
9a34af4a 1284 hda->use_vga_switcheroo = 1;
bacd8614
KHF		 1285
1286 /* cleared in either gpu_bound op or codec probe, or when its
1287 * upstream port has _PR3 (i.e. dGPU).
1288 */
1289 parent = pci_upstream_bridge(p);
1290 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
07f4f97d 1291 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1292 pci_dev_put(p);
1293 }
1294}
1295
1296static const struct vga_switcheroo_client_ops azx_vs_ops = {
1297 .set_gpu_state = azx_vs_set_state,
1298 .can_switch = azx_vs_can_switch,
37a3a98e 1299 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1300};
1301
e23e7a14 1302static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1303{
9a34af4a 1304 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1305 struct pci_dev *p;
128960a9
TI		 1306 int err;
1307
9a34af4a 1308 if (!hda->use_vga_switcheroo)
a82d51ed 1309 return 0;
4aaf448f
JQ		 1310
1311 p = get_bound_vga(chip->pci);
1312 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1313 pci_dev_put(p);
1314
128960a9
TI		 1315 if (err < 0)
1316 return err;
9a34af4a 1317 hda->vga_switcheroo_registered = 1;
246efa4a 1318
128960a9 1319 return 0;
a82d51ed
TI		 1320}
1321#else
1322#define init_vga_switcheroo(chip) /* NOP */
1323#define register_vga_switcheroo(chip) 0
8393ec4a 1324#define check_hdmi_disabled(pci) false
37a3a98e 1325#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1326#endif /* SUPPORT_VGA_SWITCHER */
1327
1da177e4
LT		 1328/*
1329 * destructor
1330 */
2393e755 1331static void azx_free(struct azx *chip)
1da177e4 1332{
c67e2228 1333 struct pci_dev *pci = chip->pci;
a07187c9 1334 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1335 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1336
2393e755
TI		 1337 if (hda->freed)
1338 return;
1339
4f66a9ef 1340 if (azx_has_pm_runtime(chip) && chip->running) {
c67e2228 1341 pm_runtime_get_noresume(&pci->dev);
4f66a9ef
TI		 1342 pm_runtime_forbid(&pci->dev);
1343 pm_runtime_dont_use_autosuspend(&pci->dev);
1344 }
1345
37a3a98e 1346 chip->running = 0;
c67e2228 1347
65fcd41d
TI		 1348 azx_del_card_list(chip);
1349
9a34af4a
TI		 1350 hda->init_failed = 1; /* to be sure */
1351 complete_all(&hda->probe_wait);
f4c482a4 1352
9a34af4a 1353 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1354 if (chip->disabled && hda->probe_continued)
1355 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1356 if (hda->vga_switcheroo_registered)
128960a9 1357 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1358 }
1359
a41d1224 1360 if (bus->chip_init) {
9ad593f6 1361 azx_clear_irq_pending(chip);
7833c3f8 1362 azx_stop_all_streams(chip);
1a7f60b9 1363 azx_stop_chip(chip);
1da177e4
LT		 1364 }
1365
a41d1224
TI		 1366 if (bus->irq >= 0)
1367 free_irq(bus->irq, (void*)chip);
1da177e4 1368
67908994 1369 azx_free_stream_pages(chip);
a41d1224
TI		 1370 azx_free_streams(chip);
1371 snd_hdac_bus_exit(bus);
1372
4918cdab 1373#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1374 release_firmware(chip->fw);
4918cdab 1375#endif
e454ff8e 1376 display_power(chip, false);
98d8fc6c 1377
fc18282c 1378 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1379 snd_hdac_i915_exit(bus);
1da177e4 1380
2393e755 1381 hda->freed = 1;
1da177e4
LT		 1382}
1383
a41d1224
TI		 1384static int azx_dev_disconnect(struct snd_device *device)
1385{
1386 struct azx *chip = device->device_data;
ca58f551 1387 struct hdac_bus *bus = azx_bus(chip);
a41d1224
TI		 1388
1389 chip->bus.shutdown = 1;
ca58f551
TI		 1390 cancel_work_sync(&bus->unsol_work);
1391
a41d1224
TI		 1392 return 0;
1393}
1394
a98f90fd 1395static int azx_dev_free(struct snd_device *device)
1da177e4 1396{
2393e755
TI		 1397 azx_free(device->device_data);
1398 return 0;
1da177e4
LT		 1399}
1400
8393ec4a 1401#ifdef SUPPORT_VGA_SWITCHEROO
586bc4aa
AD		 1402#ifdef CONFIG_ACPI
1403/* ATPX is in the integrated GPU's namespace */
1404static bool atpx_present(void)
1405{
1406 struct pci_dev *pdev = NULL;
1407 acpi_handle dhandle, atpx_handle;
1408 acpi_status status;
1409
9ed8fcfd
SJ		 1410 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
1411 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
1412 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
1413 continue;
1414
586bc4aa
AD		 1415 dhandle = ACPI_HANDLE(&pdev->dev);
1416 if (dhandle) {
1417 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
10e92724 1418 if (ACPI_SUCCESS(status)) {
586bc4aa
AD		 1419 pci_dev_put(pdev);
1420 return true;
1421 }
1422 }
586bc4aa
AD		 1423 }
1424 return false;
1425}
1426#else
1427static bool atpx_present(void)
1428{
1429 return false;
1430}
1431#endif
1432
9121947d 1433/*
2b760d88 1434 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1435 */
e23e7a14 1436static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1437{
1438 struct pci_dev *p;
1439
1440 /* check only discrete GPU */
1441 switch (pci->vendor) {
1442 case PCI_VENDOR_ID_ATI:
1443 case PCI_VENDOR_ID_AMD:
586bc4aa
AD		 1444 if (pci->devfn == 1) {
1445 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1446 pci->bus->number, 0);
1447 if (p) {
1448 /* ATPX is in the integrated GPU's ACPI namespace
1449 * rather than the dGPU's namespace. However,
1450 * the dGPU is the one who is involved in
1451 * vgaswitcheroo.
1452 */
1453 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
5beb5627 1454 (atpx_present() || apple_gmux_detect(NULL, NULL)))
586bc4aa
AD		 1455 return p;
1456 pci_dev_put(p);
1457 }
1458 }
1459 break;
9121947d
TI		 1460 case PCI_VENDOR_ID_NVIDIA:
1461 if (pci->devfn == 1) {
1462 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1463 pci->bus->number, 0);
1464 if (p) {
b6d7b362 1465 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1466 return p;
1467 pci_dev_put(p);
1468 }
1469 }
1470 break;
1471 }
1472 return NULL;
1473}
1474
e23e7a14 1475static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1476{
1477 bool vga_inactive = false;
1478 struct pci_dev *p = get_bound_vga(pci);
1479
1480 if (p) {
12b78a7f 1481 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1482 vga_inactive = true;
1483 pci_dev_put(p);
1484 }
1485 return vga_inactive;
1486}
8393ec4a 1487#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1488
3372a153 1489/*
6317e5eb 1490 * allow/deny-listing for position_fix
3372a153 1491 */
a5dc05e4 1492static const struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1493 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1494 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1495 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1496 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1497 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1498 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1499 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1500 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1501 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1502 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1503 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1504 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1505 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1506 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1507 {}
1508};
1509
e23e7a14 1510static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1511{
1512 const struct snd_pci_quirk *q;
1513
c673ba1c 1514 switch (fix) {
1dac6695 1515 case POS_FIX_AUTO:
c673ba1c
TI		 1516 case POS_FIX_LPIB:
1517 case POS_FIX_POSBUF:
4cb36310 1518 case POS_FIX_VIACOMBO:
a6f2fd55 1519 case POS_FIX_COMBO:
f87e7f25 1520 case POS_FIX_SKL:
c02f77d3 1521 case POS_FIX_FIFO:
c673ba1c
TI		 1522 return fix;
1523 }
1524
c673ba1c
TI		 1525 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1526 if (q) {
4e76a883
TI		 1527 dev_info(chip->card->dev,
1528 "position_fix set to %d for device %04x:%04x\n",
1529 q->value, q->subvendor, q->subdevice);
c673ba1c 1530 return q->value;
3372a153 1531 }
bdd9ef24
DH		 1532
1533 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1534 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1535 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1536 return POS_FIX_VIACOMBO;
9477c58e 1537 }
c02f77d3
TI		 1538 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1539 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1540 return POS_FIX_FIFO;
1541 }
9477c58e 1542 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1543 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1544 return POS_FIX_LPIB;
bdd9ef24 1545 }
a4b4793f 1546 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1547 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1548 return POS_FIX_SKL;
1549 }
c673ba1c 1550 return POS_FIX_AUTO;
3372a153
TI		 1551}
1552
b6050ef6
TI		 1553static void assign_position_fix(struct azx *chip, int fix)
1554{
bf82326f 1555 static const azx_get_pos_callback_t callbacks[] = {
b6050ef6
TI		 1556 [POS_FIX_AUTO] = NULL,
1557 [POS_FIX_LPIB] = azx_get_pos_lpib,
1558 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1559 [POS_FIX_VIACOMBO] = azx_via_get_position,
1560 [POS_FIX_COMBO] = azx_get_pos_lpib,
c4ca3871 1561 [POS_FIX_SKL] = azx_get_pos_posbuf,
c02f77d3 1562 [POS_FIX_FIFO] = azx_get_pos_fifo,
b6050ef6
TI		 1563 };
1564
1565 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1566
1567 /* combo mode uses LPIB only for playback */
1568 if (fix == POS_FIX_COMBO)
1569 chip->get_position[1] = NULL;
1570
f87e7f25 1571 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1572 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1573 chip->get_delay[0] = chip->get_delay[1] =
1574 azx_get_delay_from_lpib;
1575 }
1576
c02f77d3
TI		 1577 if (fix == POS_FIX_FIFO)
1578 chip->get_delay[0] = chip->get_delay[1] =
1579 azx_get_delay_from_fifo;
b6050ef6
TI		 1580}
1581
669ba27a 1582/*
6317e5eb 1583 * deny-lists for probe_mask
669ba27a 1584 */
a5dc05e4 1585static const struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1586 /* Thinkpad often breaks the controller communication when accessing
1587 * to the non-working (or non-existing) modem codec slot.
1588 */
1589 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1590 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1591 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1592 /* broken BIOS */
1593 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1594 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1595 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1596 /* forced codec slots */
93574844 1597 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1598 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
dd8e5b16 1599 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
f3af9051
JK		 1600 /* WinFast VP200 H (Teradici) user reported broken communication */
1601 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1602 {}
1603};
1604
f1eaaeec
TI		 1605#define AZX_FORCE_CODEC_MASK 0x100
1606
e23e7a14 1607static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1608{
1609 const struct snd_pci_quirk *q;
1610
f1eaaeec
TI		 1611 chip->codec_probe_mask = probe_mask[dev];
1612 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1613 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1614 if (q) {
4e76a883
TI		 1615 dev_info(chip->card->dev,
1616 "probe_mask set to 0x%x for device %04x:%04x\n",
1617 q->value, q->subvendor, q->subdevice);
f1eaaeec 1618 chip->codec_probe_mask = q->value;
669ba27a
TI		 1619 }
1620 }
f1eaaeec
TI		 1621
1622 /* check forced option */
1623 if (chip->codec_probe_mask != -1 &&
1624 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1625 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1626 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1627 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1628 }
669ba27a
TI		 1629}
1630
4d8e22e0 1631/*
6317e5eb 1632 * allow/deny-list for enable_msi
4d8e22e0 1633 */
6317e5eb 1634static const struct snd_pci_quirk msi_deny_list[] = {
693e0cb0
DH		 1635 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1636 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1637 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1638 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1639 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1640 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1641 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1642 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1643 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1644 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1645 {}
1646};
1647
e23e7a14 1648static void check_msi(struct azx *chip)
4d8e22e0
TI		 1649{
1650 const struct snd_pci_quirk *q;
1651
71623855
TI		 1652 if (enable_msi >= 0) {
1653 chip->msi = !!enable_msi;
4d8e22e0 1654 return;
71623855
TI		 1655 }
1656 chip->msi = 1; /* enable MSI as default */
6317e5eb 1657 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
4d8e22e0 1658 if (q) {
4e76a883
TI		 1659 dev_info(chip->card->dev,
1660 "msi for device %04x:%04x set to %d\n",
1661 q->subvendor, q->subdevice, q->value);
4d8e22e0 1662 chip->msi = q->value;
80c43ed7
TI		 1663 return;
1664 }
1665
1666 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1667 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1668 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1669 chip->msi = 0;
4d8e22e0
TI		 1670 }
1671}
1672
a1585d76 1673/* check the snoop mode availability */
e23e7a14 1674static void azx_check_snoop_available(struct azx *chip)
a1585d76 1675{
7c732015 1676 int snoop = hda_snoop;
a1585d76 1677
7c732015
TI		 1678 if (snoop >= 0) {
1679 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1680 snoop ? "snoop" : "non-snoop");
1681 chip->snoop = snoop;
78c9be61 1682 chip->uc_buffer = !snoop;
7c732015
TI		 1683 return;
1684 }
1685
1686 snoop = true;
37e661ee
TI		 1687 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1688 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1689 /* force to non-snoop mode for a new VIA controller
1690 * when BIOS is set
1691 */
7c732015
TI		 1692 u8 val;
1693 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1694 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1695 chip->pci->revision == 0x20))
7c732015 1696 snoop = false;
a1585d76
TI		 1697 }
1698
37e661ee
TI		 1699 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1700 snoop = false;
1701
7c732015 1702 chip->snoop = snoop;
78c9be61 1703 if (!snoop) {
7c732015 1704 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1705 /* C-Media requires non-cached pages only for CORB/RIRB */
1706 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1707 chip->uc_buffer = true;
1708 }
a1585d76 1709}
669ba27a 1710
99a2008d
WX		 1711static void azx_probe_work(struct work_struct *work)
1712{
c0f1886d 1713 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
9a34af4a 1714 azx_probe_continue(&hda->chip);
99a2008d 1715}
99a2008d 1716
4f0189be
TI		 1717static int default_bdl_pos_adj(struct azx *chip)
1718{
2cf721db
TI		 1719 /* some exceptions: Atoms seem problematic with value 1 */
1720 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1721 switch (chip->pci->device) {
3526860f
RS		 1722 case PCI_DEVICE_ID_INTEL_HDA_BYT:
1723 case PCI_DEVICE_ID_INTEL_HDA_BSW:
2cf721db 1724 return 32;
56beedc8
RS		 1725 case PCI_DEVICE_ID_INTEL_HDA_APL:
1726 return 64;
2cf721db
TI		 1727 }
1728 }
1729
4f0189be 1730 switch (chip->driver_type) {
c51e4310 1731 /*
1732 * increase the bdl size for Glenfly Gpus for hardware
1733 * limitation on hdac interrupt interval
1734 */
1735 case AZX_DRIVER_GFHDMI:
1736 return 128;
4f0189be
TI		 1737 case AZX_DRIVER_ICH:
1738 case AZX_DRIVER_PCH:
1739 return 1;
1740 default:
1741 return 32;
1742 }
1743}
1744
1da177e4
LT		 1745/*
1746 * constructor
1747 */
a43ff5ba
TI		 1748static const struct hda_controller_ops pci_hda_ops;
1749
e23e7a14
BP		 1750static int azx_create(struct snd_card *card, struct pci_dev *pci,
1751 int dev, unsigned int driver_caps,
1752 struct azx **rchip)
1da177e4 1753{
41f394a8 1754 static const struct snd_device_ops ops = {
a41d1224 1755 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1756 .dev_free = azx_dev_free,
1757 };
a07187c9 1758 struct hda_intel *hda;
a82d51ed
TI		 1759 struct azx *chip;
1760 int err;
1da177e4
LT		 1761
1762 *rchip = NULL;
bcd72003 1763
3fcaf24e 1764 err = pcim_enable_device(pci);
927fc866 1765 if (err < 0)
1da177e4
LT		 1766 return err;
1767
2393e755 1768 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
3fcaf24e 1769 if (!hda)
1da177e4 1770 return -ENOMEM;
1da177e4 1771
a07187c9 1772 chip = &hda->chip;
62932df8 1773 mutex_init(&chip->open_mutex);
1da177e4
LT		 1774 chip->card = card;
1775 chip->pci = pci;
a43ff5ba 1776 chip->ops = &pci_hda_ops;
9477c58e
TI		 1777 chip->driver_caps = driver_caps;
1778 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1779 check_msi(chip);
555e219f 1780 chip->dev_index = dev;
3a182c84
TI		 1781 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1782 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1783 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1784 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1785 INIT_LIST_HEAD(&hda->list);
a82d51ed 1786 init_vga_switcheroo(chip);
9a34af4a 1787 init_completion(&hda->probe_wait);
1da177e4 1788
b6050ef6 1789 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1790
41438f13
TI		 1791 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1792 chip->fallback_to_single_cmd = 1;
1793 else /* explicitly set to single_cmd or not */
1794 chip->single_cmd = single_cmd;
1795
a1585d76 1796 azx_check_snoop_available(chip);
c74db86b 1797
4f0189be
TI		 1798 if (bdl_pos_adj[dev] < 0)
1799 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1800 else
1801 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1802
19abfefd 1803 err = azx_bus_init(chip, model[dev]);
3fcaf24e 1804 if (err < 0)
a41d1224 1805 return err;
a41d1224 1806
619a1f19
TI		 1807 /* use the non-cached pages in non-snoop mode */
1808 if (!azx_snoop(chip))
37137ec2 1809 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
619a1f19 1810
7d9a1808
TI		 1811 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1812 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
5f2cb361 1813 chip->bus.core.needs_damn_long_delay = 1;
7d9a1808
TI		 1814 }
1815
6317f744
TI		 1816 check_probe_mask(chip, dev);
1817
a82d51ed
TI		 1818 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1819 if (err < 0) {
4e76a883 1820 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1821 azx_free(chip);
1822 return err;
1823 }
1824
99a2008d 1825 /* continue probing in work context as may trigger request module */
c0f1886d 1826 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1827
a82d51ed 1828 *rchip = chip;
99a2008d 1829
a82d51ed
TI		 1830 return 0;
1831}
1832
48c8b0eb 1833static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1834{
1835 int dev = chip->dev_index;
1836 struct pci_dev *pci = chip->pci;
1837 struct snd_card *card = chip->card;
a41d1224 1838 struct hdac_bus *bus = azx_bus(chip);
67908994 1839 int err;
a82d51ed 1840 unsigned short gcap;
413cbf46 1841 unsigned int dma_bits = 64;
a82d51ed 1842
07e4ca50
TI		 1843#if BITS_PER_LONG != 64
1844 /* Fix up base address on ULI M5461 */
1845 if (chip->driver_type == AZX_DRIVER_ULI) {
1846 u16 tmp3;
1847 pci_read_config_word(pci, 0x40, &tmp3);
1848 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1849 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1850 }
1851#endif
c51e4310 1852 /*
1853 * Fix response write request not synced to memory when handle
1854 * hdac interrupt on Glenfly Gpus
1855 */
1856 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1857 bus->polling_mode = 1;
07e4ca50 1858
cbc3e98a
YS		 1859 if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1860 bus->polling_mode = 1;
1861 bus->not_use_interrupts = 1;
942ccdd8 1862 bus->access_sdnctl_in_dword = 1;
cbc3e98a
YS		 1863 }
1864
3fcaf24e 1865 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
a82d51ed 1866 if (err < 0)
1da177e4 1867 return err;
1da177e4 1868
a41d1224 1869 bus->addr = pci_resource_start(pci, 0);
3fcaf24e 1870 bus->remap_addr = pcim_iomap_table(pci)[0];
1da177e4 1871
a4b4793f 1872 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1873 snd_hdac_bus_parse_capabilities(bus);
1874
1875 /*
1876 * Some Intel CPUs has always running timer (ART) feature and
1877 * controller may have Global time sync reporting capability, so
1878 * check both of these before declaring synchronized time reporting
1879 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1880 */
1881 chip->gts_present = false;
1882
1883#ifdef CONFIG_X86
1884 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1885 chip->gts_present = true;
1886#endif
1887
db79afa1
BH		 1888 if (chip->msi) {
1889 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1890 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1891 pci->no_64bit_msi = true;
1892 }
68e7fffc
TI		 1893 if (pci_enable_msi(pci) < 0)
1894 chip->msi = 0;
db79afa1 1895 }
7376d013 1896
1da177e4 1897 pci_set_master(pci);
1da177e4 1898
bcd72003 1899 gcap = azx_readw(chip, GCAP);
4e76a883 1900 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1901
413cbf46
TI		 1902 /* AMD devices support 40 or 48bit DMA, take the safe one */
1903 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1904 dma_bits = 40;
1905
dc4c2e6b 1906 /* disable SB600 64bit support for safety */
9477c58e 1907 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1908 struct pci_dev *p_smbus;
413cbf46 1909 dma_bits = 40;
dc4c2e6b
AB		 1910 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1911 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1912 NULL);
1913 if (p_smbus) {
1914 if (p_smbus->revision < 0x30)
fb1d8ac2 1915 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1916 pci_dev_put(p_smbus);
1917 }
1918 }
09240cf4 1919
3ab7511e
AB		 1920 /* NVidia hardware normally only supports up to 40 bits of DMA */
1921 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1922 dma_bits = 40;
1923
9477c58e
TI		 1924 /* disable 64bit DMA address on some devices */
1925 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1926 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1927 gcap &= ~AZX_GCAP_64OK;
9477c58e 1928 }
396087ea 1929
2ae66c26 1930 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1931 if (align_buffer_size >= 0)
1932 chip->align_buffer_size = !!align_buffer_size;
1933 else {
103884a3 1934 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1935 chip->align_buffer_size = 0;
7bfe059e
TI		 1936 else
1937 chip->align_buffer_size = 1;
1938 }
2ae66c26 1939
cf7aaca8 1940 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1941 if (!(gcap & AZX_GCAP_64OK))
1942 dma_bits = 32;
669f65ea
TI		 1943 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1944 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
acd289e0 1945 dma_set_max_seg_size(&pci->dev, UINT_MAX);
cf7aaca8 1946
8b6ed8e7
TI		 1947 /* read number of streams from GCAP register instead of using
1948 * hardcoded value
1949 */
1950 chip->capture_streams = (gcap >> 8) & 0x0f;
1951 chip->playback_streams = (gcap >> 12) & 0x0f;
1952 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1953 /* gcap didn't give any info, switching to old method */
1954
1955 switch (chip->driver_type) {
1956 case AZX_DRIVER_ULI:
1957 chip->playback_streams = ULI_NUM_PLAYBACK;
1958 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1959 break;
1960 case AZX_DRIVER_ATIHDMI:
1815b34a 1961 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1962 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1963 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1964 break;
c51e4310 1965 case AZX_DRIVER_GFHDMI:
c4da29ca 1966 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1967 default:
1968 chip->playback_streams = ICH6_NUM_PLAYBACK;
1969 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1970 break;
1971 }
07e4ca50 1972 }
8b6ed8e7
TI		 1973 chip->capture_index_offset = 0;
1974 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1975 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1976
df56c3db
JK		 1977 /* sanity check for the SDxCTL.STRM field overflow */
1978 if (chip->num_streams > 15 &&
1979 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1980 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1981 "forcing separate stream tags", chip->num_streams);
1982 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1983 }
1984
a41d1224
TI		 1985 /* initialize streams */
1986 err = azx_init_streams(chip);
81740861 1987 if (err < 0)
a82d51ed 1988 return err;
1da177e4 1989
a41d1224
TI		 1990 err = azx_alloc_stream_pages(chip);
1991 if (err < 0)
1992 return err;
1da177e4
LT		 1993
1994 /* initialize chip */
cb53c626 1995 azx_init_pci(chip);
e4d9e513 1996
e454ff8e 1997 snd_hdac_i915_set_bclk(bus);
e4d9e513 1998
0a673521 1999 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 2000
2001 /* codec detection */
a41d1224 2002 if (!azx_bus(chip)->codec_mask) {
4e76a883 2003 dev_err(card->dev, "no codecs found!\n");
9479e75f 2004 /* keep running the rest for the runtime PM */
1da177e4
LT		 2005 }
2006
f495222e
TI		 2007 if (azx_acquire_irq(chip, 0) < 0)
2008 return -EBUSY;
2009
07e4ca50 2010 strcpy(card->driver, "HDA-Intel");
75b1a8f9 2011 strscpy(card->shortname, driver_short_names[chip->driver_type],
18cb7109
TI		 2012 sizeof(card->shortname));
2013 snprintf(card->longname, sizeof(card->longname),
2014 "%s at 0x%lx irq %i",
a41d1224 2015 card->shortname, bus->addr, bus->irq);
07e4ca50 2016
1da177e4 2017 return 0;
1da177e4
LT		 2018}
2019
97c6a3d1 2020#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 2021/* callback from request_firmware_nowait() */
2022static void azx_firmware_cb(const struct firmware *fw, void *context)
2023{
2024 struct snd_card *card = context;
2025 struct azx *chip = card->private_data;
5cb543db 2026
25faa4bd
TI		 2027 if (fw)
2028 chip->fw = fw;
2029 else
2030 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
5cb543db
TI		 2031 if (!chip->disabled) {
2032 /* continue probing */
25faa4bd 2033 azx_probe_continue(chip);
5cb543db 2034 }
5cb543db 2035}
97c6a3d1 2036#endif
5cb543db 2037
f46ea609
DR		 2038static int disable_msi_reset_irq(struct azx *chip)
2039{
a41d1224 2040 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2041 int err;
2042
a41d1224
TI		 2043 free_irq(bus->irq, chip);
2044 bus->irq = -1;
f36da940 2045 chip->card->sync_irq = -1;
f46ea609
DR		 2046 pci_disable_msi(chip->pci);
2047 chip->msi = 0;
2048 err = azx_acquire_irq(chip, 1);
2049 if (err < 0)
2050 return err;
2051
2052 return 0;
2053}
2054
6317e5eb 2055/* Denylist for skipping the whole probe:
3c6fd1f0
TI		 2056 * some HD-audio PCI entries are exposed without any codecs, and such devices
2057 * should be ignored from the beginning.
2058 */
6317e5eb 2059static const struct pci_device_id driver_denylist[] = {
977dfef4
TI		 2060 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2061 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2062 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
df42ee7e 2063 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */
3c6fd1f0
TI		 2064 {}
2065};
2066
a43ff5ba
TI		 2067static const struct hda_controller_ops pci_hda_ops = {
2068 .disable_msi_reset_irq = disable_msi_reset_irq,
7ca954a8 2069 .position_check = azx_position_check,
40830813
DR		 2070};
2071
69458e2c
TI		 2072static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2073
e23e7a14
BP		 2074static int azx_probe(struct pci_dev *pci,
2075 const struct pci_device_id *pci_id)
1da177e4 2076{
a98f90fd 2077 struct snd_card *card;
9a34af4a 2078 struct hda_intel *hda;
a98f90fd 2079 struct azx *chip;
aad730d0 2080 bool schedule_probe;
69458e2c 2081 int dev;
927fc866 2082 int err;
1da177e4 2083
6317e5eb
TI		 2084 if (pci_match_id(driver_denylist, pci)) {
2085 dev_info(&pci->dev, "Skipping the device on the denylist\n");
3c6fd1f0
TI		 2086 return -ENODEV;
2087 }
2088
69458e2c 2089 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
5aba4f8e
TI		 2090 if (dev >= SNDRV_CARDS)
2091 return -ENODEV;
2092 if (!enable[dev]) {
69458e2c 2093 set_bit(dev, probed_devs);
5aba4f8e
TI		 2094 return -ENOENT;
2095 }
2096
82d9d54a
JK		 2097 /*
2098 * stop probe if another Intel's DSP driver should be activated
2099 */
7fba6aea 2100 if (dmic_detect) {
82d9d54a 2101 err = snd_intel_dsp_driver_probe(pci);
ae035947
PLB		 2102 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2103 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
82d9d54a 2104 return -ENODEV;
ae035947 2105 }
7fba6aea
TI		 2106 } else {
2107 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
82d9d54a
JK		 2108 }
2109
60c5772b
TI		 2110 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2111 0, &card);
e58de7ba 2112 if (err < 0) {
4e76a883 2113 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2114 return err;
1da177e4
LT		 2115 }
2116
a43ff5ba 2117 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2118 if (err < 0)
2119 goto out_free;
421a1252 2120 card->private_data = chip;
9a34af4a 2121 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2122
2123 pci_set_drvdata(pci, card);
2124
65cbbfa4
ML		 2125#ifdef CONFIG_SND_HDA_I915
2126 /* bind with i915 if needed */
2127 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
e6d0c13e 2128 err = snd_hdac_i915_init(azx_bus(chip));
65cbbfa4 2129 if (err < 0) {
9e88b493
ML		 2130 if (err == -EPROBE_DEFER)
2131 goto out_free;
2132
65cbbfa4
ML		 2133 /* if the controller is bound only with HDMI/DP
2134 * (for HSW and BDW), we need to abort the probe;
2135 * for other chips, still continue probing as other
2136 * codecs can be on the same link.
2137 */
2138 if (HDA_CONTROLLER_IN_GPU(pci)) {
2139 dev_err_probe(card->dev, err,
2140 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2141
2142 goto out_free;
2143 } else {
2144 /* don't bother any longer */
2145 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2146 }
2147 }
2148
2149 /* HSW/BDW controllers need this power */
2150 if (HDA_CONTROLLER_IN_GPU(pci))
2151 hda->need_i915_power = true;
2152 }
2153#else
2154 if (HDA_CONTROLLER_IN_GPU(pci))
2155 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2156#endif
2157
f4c482a4
TI		 2158 err = register_vga_switcheroo(chip);
2159 if (err < 0) {
2b760d88 2160 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2161 goto out_free;
2162 }
2163
2164 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2165 dev_info(card->dev, "VGA controller is disabled\n");
2166 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2167 chip->disabled = true;
2168 }
2169
aad730d0 2170 schedule_probe = !chip->disabled;
1da177e4 2171
4918cdab
TI		 2172#ifdef CONFIG_SND_HDA_PATCH_LOADER
2173 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2174 dev_info(card->dev, "Applying patch firmware '%s'\n",
2175 patch[dev]);
5cb543db
TI		 2176 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2177 &pci->dev, GFP_KERNEL, card,
2178 azx_firmware_cb);
4918cdab
TI		 2179 if (err < 0)
2180 goto out_free;
aad730d0 2181 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2182 }
2183#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2184
aad730d0 2185 if (schedule_probe)
c0f1886d 2186 schedule_delayed_work(&hda->probe_work, 0);
a82d51ed 2187
69458e2c 2188 set_bit(dev, probed_devs);
88d071fc 2189 if (chip->disabled)
9a34af4a 2190 complete_all(&hda->probe_wait);
a82d51ed
TI		 2191 return 0;
2192
2193out_free:
ad6413bc 2194 pci_set_drvdata(pci, NULL);
a82d51ed
TI		 2195 snd_card_free(card);
2196 return err;
2197}
2198
1ba8f9d3
HG		 2199/* On some boards setting power_save to a non 0 value leads to clicking /
2200 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2201 * figure out how to avoid these sounds, but that is not always feasible.
2202 * So we keep a list of devices where we disable powersaving as its known
2203 * to causes problems on these devices.
2204 */
6317e5eb 2205static const struct snd_pci_quirk power_save_denylist[] = {
1ba8f9d3 2206 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2207 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2208 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2209 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2210 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2211 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2212 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2213 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
38d9c12c 2214 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2215 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2216 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2217 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2218 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2219 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2220 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2221 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2222 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2223 /* https://bugs.launchpad.net/bugs/1821663 */
2224 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2225 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2226 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2227 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2228 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
057a28ef 2229 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
721f1e6c
JK		 2230 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2231 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2232 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2233 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2234 /* https://bugs.launchpad.net/bugs/1821663 */
2235 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
a337c355
TI		 2236 /* KONTRON SinglePC may cause a stall at runtime resume */
2237 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
1ba8f9d3
HG		 2238 {}
2239};
1ba8f9d3 2240
37a3a98e
TI		 2241static void set_default_power_save(struct azx *chip)
2242{
2243 int val = power_save;
2244
37a3a98e
TI		 2245 if (pm_blacklist) {
2246 const struct snd_pci_quirk *q;
2247
6317e5eb 2248 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
37a3a98e 2249 if (q && val) {
6317e5eb 2250 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
37a3a98e
TI		 2251 q->subvendor, q->subdevice);
2252 val = 0;
2253 }
2254 }
37a3a98e
TI		 2255 snd_hda_set_power_save(&chip->bus, val * 1000);
2256}
2257
e62a42ae 2258/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
bf82326f 2259static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
e62a42ae
DR		 2260 [AZX_DRIVER_NVIDIA] = 8,
2261 [AZX_DRIVER_TERA] = 1,
2262};
2263
48c8b0eb 2264static int azx_probe_continue(struct azx *chip)
a82d51ed 2265{
9a34af4a 2266 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2267 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2268 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2269 int dev = chip->dev_index;
2270 int err;
2271
c0f1886d
TI		 2272 if (chip->disabled || hda->init_failed)
2273 return -EIO;
2274 if (hda->probe_retry)
2275 goto probe_retry;
2276
305a0ade 2277 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2278 hda->probe_continued = 1;
795614dd 2279
fcc88d91
TI		 2280 /* Request display power well for the HDA controller or codec. For
2281 * Haswell/Broadwell, both the display HDA controller and codec need
2282 * this power. For other platforms, like Baytrail/Braswell, only the
2283 * display codec needs the power and it can be released after probe.
2284 */
4f799e73 2285 display_power(chip, true);
99a2008d 2286
5c90680e
TI		 2287 err = azx_first_init(chip);
2288 if (err < 0)
2289 goto out_free;
2290
2dca0bba
JK		 2291#ifdef CONFIG_SND_HDA_INPUT_BEEP
2292 chip->beep_mode = beep_mode[dev];
2293#endif
2294
d045bcef
JK		 2295 chip->ctl_dev_id = ctl_dev_id;
2296
1da177e4 2297 /* create codec instances */
9479e75f
TI		 2298 if (bus->codec_mask) {
2299 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2300 if (err < 0)
2301 goto out_free;
2302 }
96d2bd6e 2303
4ea6fbc8 2304#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2305 if (chip->fw) {
a41d1224 2306 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2307 chip->fw->data);
4ea6fbc8
TI		 2308 if (err < 0)
2309 goto out_free;
2310 }
2311#endif
c0f1886d
TI		 2312
2313 probe_retry:
9479e75f 2314 if (bus->codec_mask && !(probe_only[dev] & 1)) {
a1e21c90 2315 err = azx_codec_configure(chip);
c0f1886d
TI		 2316 if (err) {
2317 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2318 ++hda->probe_retry < 60) {
2319 schedule_delayed_work(&hda->probe_work,
2320 msecs_to_jiffies(1000));
2321 return 0; /* keep things up */
2322 }
2323 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
a1e21c90 2324 goto out_free;
c0f1886d 2325 }
a1e21c90 2326 }
1da177e4 2327
a82d51ed 2328 err = snd_card_register(chip->card);
41dda0fd
WF		 2329 if (err < 0)
2330 goto out_free;
1da177e4 2331
37a3a98e
TI		 2332 setup_vga_switcheroo_runtime_pm(chip);
2333
cb53c626 2334 chip->running = 1;
65fcd41d 2335 azx_add_card_list(chip);
07f4f97d 2336
37a3a98e 2337 set_default_power_save(chip);
07f4f97d 2338
3ba21113
RS		 2339 if (azx_has_pm_runtime(chip)) {
2340 pm_runtime_use_autosuspend(&pci->dev);
9fc149c3 2341 pm_runtime_allow(&pci->dev);
30ff5957 2342 pm_runtime_put_autosuspend(&pci->dev);
3ba21113 2343 }
1da177e4 2344
41dda0fd 2345out_free:
2393e755 2346 if (err < 0) {
39173303
TI		 2347 pci_set_drvdata(pci, NULL);
2348 snd_card_free(chip->card);
2393e755
TI		 2349 return err;
2350 }
2351
2352 if (!hda->need_i915_power)
029d92c2 2353 display_power(chip, false);
9a34af4a 2354 complete_all(&hda->probe_wait);
305a0ade 2355 to_hda_bus(bus)->bus_probing = 0;
c0f1886d 2356 hda->probe_retry = 0;
2393e755 2357 return 0;
1da177e4
LT		 2358}
2359
e23e7a14 2360static void azx_remove(struct pci_dev *pci)
1da177e4 2361{
9121947d 2362 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2363 struct azx *chip;
2364 struct hda_intel *hda;
2365
2366 if (card) {
0b8c8219 2367 /* cancel the pending probing work */
991f86d7
TI		 2368 chip = card->private_data;
2369 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2370 /* FIXME: below is an ugly workaround.
2371 * Both device_release_driver() and driver_probe_device()
2372 * take *both* the device's and its parent's lock before
2373 * calling the remove() and probe() callbacks. The codec
2374 * probe takes the locks of both the codec itself and its
2375 * parent, i.e. the PCI controller dev. Meanwhile, when
2376 * the PCI controller is unbound, it takes its lock, too
2377 * ==> ouch, a deadlock!
2378 * As a workaround, we unlock temporarily here the controller
2379 * device during cancel_work_sync() call.
2380 */
2381 device_unlock(&pci->dev);
c0f1886d 2382 cancel_delayed_work_sync(&hda->probe_work);
ab949d51 2383 device_lock(&pci->dev);
b8dfc462 2384
69458e2c 2385 clear_bit(chip->dev_index, probed_devs);
e81478bb 2386 pci_set_drvdata(pci, NULL);
9121947d 2387 snd_card_free(card);
991f86d7 2388 }
1da177e4
LT		 2389}
2390
b2a0bafa
TI		 2391static void azx_shutdown(struct pci_dev *pci)
2392{
2393 struct snd_card *card = pci_get_drvdata(pci);
2394 struct azx *chip;
2395
2396 if (!card)
2397 return;
2398 chip = card->private_data;
2399 if (chip && chip->running)
6f445784 2400 __azx_shutdown_chip(chip, true);
b2a0bafa
TI		 2401}
2402
1da177e4 2403/* PCI IDs */
6f51f6cf 2404static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2405 /* CPT */
e6232c80 2406 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
cea310e8 2407 /* PBG */
e6232c80 2408 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
d2edeb7c 2409 /* Panther Point */
e6232c80 2410 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
8bc039a1 2411 /* Lynx Point */
e6232c80 2412 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
77f07800 2413 /* 9 Series */
e6232c80 2414 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
884b088f 2415 /* Wellsburg */
e6232c80
AS		 2416 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2417 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
5cf92c8b 2418 /* Lewisburg */
e6232c80
AS		 2419 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2420 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
144dad99 2421 /* Lynx Point-LP */
e6232c80 2422 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
144dad99 2423 /* Lynx Point-LP */
e6232c80 2424 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
4eeca499 2425 /* Wildcat Point-LP */
e6232c80
AS		 2426 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2427 /* Skylake (Sunrise Point) */
2428 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2429 /* Skylake-LP (Sunrise Point-LP) */
2430 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
35639a0e 2431 /* Kabylake */
e6232c80 2432 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
35639a0e 2433 /* Kabylake-LP */
e6232c80 2434 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
6858107e 2435 /* Kabylake-H */
e6232c80 2436 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
e79b0006 2437 /* Coffelake */
e6232c80 2438 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2357f6f0 2439 /* Cannonlake */
e6232c80 2440 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d4c2ccdb 2441 /* CometLake-LP */
e6232c80 2442 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d4c2ccdb 2443 /* CometLake-H */
e6232c80
AS		 2444 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2445 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
b73a5854 2446 /* CometLake-S */
e6232c80 2447 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
f84d3a1e 2448 /* CometLake-R */
e6232c80 2449 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
491f8331 2450 /* Icelake */
e6232c80 2451 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d50313a5 2452 /* Icelake-H */
e6232c80 2453 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4750c212 2454 /* Jasperlake */
e6232c80
AS		 2455 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2456 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4750c212 2457 /* Tigerlake */
e6232c80 2458 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d50313a5 2459 /* Tigerlake-H */
e6232c80 2460 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
69b08bdf 2461 /* DG1 */
e6232c80 2462 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d85ffff5 2463 /* DG2 */
e6232c80
AS		 2464 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2465 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2466 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d78359b2 2467 /* Alderlake-S */
e6232c80 2468 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
5e941fc0 2469 /* Alderlake-P */
e6232c80
AS		 2470 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2471 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2472 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4ad7935d 2473 /* Alderlake-M */
e6232c80 2474 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4d5a628d 2475 /* Alderlake-N */
e6232c80 2476 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
f94287b6 2477 /* Elkhart Lake */
e6232c80
AS		 2478 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2479 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
a531caa5 2480 /* Raptor Lake */
e6232c80
AS		 2481 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2482 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2483 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2484 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2485 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2486 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
714b2f02 2487 /* Lunarlake-P */
e6232c80 2488 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
3bef0681
KV		 2489 /* Arrow Lake-S */
2490 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
a31014eb
PLB		 2491 /* Arrow Lake */
2492 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
e6232c80
AS		 2493 /* Apollolake (Broxton-P) */
2494 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
44b46d73 2495 /* Gemini-Lake */
e6232c80 2496 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
e926f2c8 2497 /* Haswell */
e6232c80
AS		 2498 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2499 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2500 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
862d7618 2501 /* Broadwell */
e6232c80 2502 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },
99df18b3 2503 /* 5 Series/3400 */
e6232c80
AS		 2504 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2505 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
f748abcc 2506 /* Poulsbo */
e6232c80
AS		 2507 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2508 AZX_DCAPS_POSFIX_LPIB) },
f748abcc 2509 /* Oaktrail */
e6232c80 2510 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },
e44007e0 2511 /* BayTrail */
e6232c80 2512 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },
f31b2ffc 2513 /* Braswell */
e6232c80 2514 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },
b42b4afb 2515 /* ICH6 */
e6232c80 2516 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2517 /* ICH7 */
e6232c80 2518 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2519 /* ESB2 */
e6232c80 2520 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2521 /* ICH8 */
e6232c80 2522 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2523 /* ICH9 */
e6232c80 2524 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2525 /* ICH9 */
e6232c80 2526 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2527 /* ICH10 */
e6232c80 2528 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2529 /* ICH10 */
e6232c80 2530 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b6864535
TI		 2531 /* Generic Intel */
2532 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2533 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2534 .class_mask = 0xffffff,
103884a3 2535 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e 2536 /* ATI SB 450/600/700/800/900 */
e6232c80 2537 { PCI_VDEVICE(ATI, 0x437b),
9477c58e 2538 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
e6232c80 2539 { PCI_VDEVICE(ATI, 0x4383),
9477c58e
TI		 2540 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2541 /* AMD Hudson */
e6232c80 2542 { PCI_VDEVICE(AMD, 0x780d),
9477c58e 2543 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
c02f77d3 2544 /* AMD, X370 & co */
e6232c80 2545 { PCI_VDEVICE(AMD, 0x1457),
c02f77d3 2546 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
de768ce4 2547 /* AMD, X570 & co */
e6232c80 2548 { PCI_VDEVICE(AMD, 0x1487),
de768ce4 2549 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
3deef52c 2550 /* AMD Stoney */
e6232c80 2551 { PCI_VDEVICE(AMD, 0x157a),
3deef52c
KHF		 2552 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2553 AZX_DCAPS_PM_RUNTIME },
9ceace3c 2554 /* AMD Raven */
e6232c80 2555 { PCI_VDEVICE(AMD, 0x15e3),
d2c63b7d 2556 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
87218e9c 2557 /* ATI HDMI */
e6232c80 2558 { PCI_VDEVICE(ATI, 0x0002),
20c7842e
AD		 2559 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2560 AZX_DCAPS_PM_RUNTIME },
e6232c80 2561 { PCI_VDEVICE(ATI, 0x1308),
650474fb 2562 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2563 { PCI_VDEVICE(ATI, 0x157a),
5022813d 2564 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2565 { PCI_VDEVICE(ATI, 0x15b3),
d716fb03 2566 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2567 { PCI_VDEVICE(ATI, 0x793b),
9477c58e 2568 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2569 { PCI_VDEVICE(ATI, 0x7919),
9477c58e 2570 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2571 { PCI_VDEVICE(ATI, 0x960f),
9477c58e 2572 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2573 { PCI_VDEVICE(ATI, 0x970f),
9477c58e 2574 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2575 { PCI_VDEVICE(ATI, 0x9840),
650474fb 2576 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2577 { PCI_VDEVICE(ATI, 0xaa00),
9477c58e 2578 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2579 { PCI_VDEVICE(ATI, 0xaa08),
9477c58e 2580 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2581 { PCI_VDEVICE(ATI, 0xaa10),
9477c58e 2582 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2583 { PCI_VDEVICE(ATI, 0xaa18),
9477c58e 2584 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2585 { PCI_VDEVICE(ATI, 0xaa20),
9477c58e 2586 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2587 { PCI_VDEVICE(ATI, 0xaa28),
9477c58e 2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2589 { PCI_VDEVICE(ATI, 0xaa30),
9477c58e 2590 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2591 { PCI_VDEVICE(ATI, 0xaa38),
9477c58e 2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2593 { PCI_VDEVICE(ATI, 0xaa40),
9477c58e 2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2595 { PCI_VDEVICE(ATI, 0xaa48),
9477c58e 2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2597 { PCI_VDEVICE(ATI, 0xaa50),
bbaa0d66 2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2599 { PCI_VDEVICE(ATI, 0xaa58),
bbaa0d66 2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2601 { PCI_VDEVICE(ATI, 0xaa60),
bbaa0d66 2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2603 { PCI_VDEVICE(ATI, 0xaa68),
bbaa0d66 2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2605 { PCI_VDEVICE(ATI, 0xaa80),
bbaa0d66 2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2607 { PCI_VDEVICE(ATI, 0xaa88),
bbaa0d66 2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2609 { PCI_VDEVICE(ATI, 0xaa90),
bbaa0d66 2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2611 { PCI_VDEVICE(ATI, 0xaa98),
bbaa0d66 2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2613 { PCI_VDEVICE(ATI, 0x9902),
37e661ee 2614 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2615 { PCI_VDEVICE(ATI, 0xaaa0),
37e661ee 2616 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2617 { PCI_VDEVICE(ATI, 0xaaa8),
37e661ee 2618 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2619 { PCI_VDEVICE(ATI, 0xaab0),
37e661ee 2620 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2621 { PCI_VDEVICE(ATI, 0xaac0),
20c7842e
AD		 2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2623 AZX_DCAPS_PM_RUNTIME },
e6232c80 2624 { PCI_VDEVICE(ATI, 0xaac8),
20c7842e
AD		 2625 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2626 AZX_DCAPS_PM_RUNTIME },
e6232c80 2627 { PCI_VDEVICE(ATI, 0xaad8),
73b1422b
AD		 2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2629 AZX_DCAPS_PM_RUNTIME },
e6232c80 2630 { PCI_VDEVICE(ATI, 0xaae0),
73b1422b
AD		 2631 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2632 AZX_DCAPS_PM_RUNTIME },
e6232c80 2633 { PCI_VDEVICE(ATI, 0xaae8),
73b1422b
AD		 2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2635 AZX_DCAPS_PM_RUNTIME },
e6232c80 2636 { PCI_VDEVICE(ATI, 0xaaf0),
73b1422b
AD		 2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2638 AZX_DCAPS_PM_RUNTIME },
e6232c80 2639 { PCI_VDEVICE(ATI, 0xaaf8),
73b1422b
AD		 2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2641 AZX_DCAPS_PM_RUNTIME },
e6232c80 2642 { PCI_VDEVICE(ATI, 0xab00),
73b1422b
AD		 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2644 AZX_DCAPS_PM_RUNTIME },
e6232c80 2645 { PCI_VDEVICE(ATI, 0xab08),
73b1422b
AD		 2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2647 AZX_DCAPS_PM_RUNTIME },
e6232c80 2648 { PCI_VDEVICE(ATI, 0xab10),
73b1422b
AD		 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2650 AZX_DCAPS_PM_RUNTIME },
e6232c80 2651 { PCI_VDEVICE(ATI, 0xab18),
73b1422b
AD		 2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2653 AZX_DCAPS_PM_RUNTIME },
e6232c80 2654 { PCI_VDEVICE(ATI, 0xab20),
73b1422b 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
27a7c670 2656 AZX_DCAPS_PM_RUNTIME },
e6232c80 2657 { PCI_VDEVICE(ATI, 0xab28),
27a7c670 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
fdcc4c22 2659 AZX_DCAPS_PM_RUNTIME },
e6232c80 2660 { PCI_VDEVICE(ATI, 0xab30),
fdcc4c22 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
73b1422b 2662 AZX_DCAPS_PM_RUNTIME },
e6232c80 2663 { PCI_VDEVICE(ATI, 0xab38),
73b1422b
AD		 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2665 AZX_DCAPS_PM_RUNTIME },
c51e4310 2666 /* GLENFLY */
2667 { PCI_DEVICE(0x6766, PCI_ANY_ID),
2668 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2669 .class_mask = 0xffffff,
2670 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2671 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
87218e9c 2672 /* VIA VT8251/VT8237A */
e6232c80 2673 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8 2674 /* VIA GFX VT7122/VX900 */
e6232c80 2675 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
754fdff8 2676 /* VIA GFX VT6122/VX11 */
e6232c80 2677 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c 2678 /* SIS966 */
e6232c80 2679 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
87218e9c 2680 /* ULI M5461 */
e6232c80 2681 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },
87218e9c 2682 /* NVIDIA MCP */
0c2fd1bf
TI		 2683 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2684 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2685 .class_mask = 0xffffff,
9477c58e 2686 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2687 /* Teradici */
9477c58e
TI		 2688 { PCI_DEVICE(0x6549, 0x1200),
2689 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2690 { PCI_DEVICE(0x6549, 0x2200),
2691 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2692 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf 2693 /* CTHDA chips */
e6232c80 2694 { PCI_VDEVICE(CREATIVE, 0x0010),
f2a8ecaf 2695 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
e6232c80 2696 { PCI_VDEVICE(CREATIVE, 0x0012),
f2a8ecaf 2697 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2698#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2699 /* the following entry conflicts with snd-ctxfi driver,
2700 * as ctxfi driver mutates from HD-audio to native mode with
2701 * a special command sequence.
2702 */
4e01f54b
TI		 2703 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2704 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2705 .class_mask = 0xffffff,
9477c58e 2706 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2707 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2708#else
2709 /* this entry seems still valid -- i.e. without emu20kx chip */
e6232c80 2710 { PCI_VDEVICE(CREATIVE, 0x0009),
9477c58e 2711 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2712 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2713#endif
c563f473 2714 /* CM8888 */
e6232c80 2715 { PCI_VDEVICE(CMEDIA, 0x5011),
c563f473 2716 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2717 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11 2718 /* Vortex86MX */
e6232c80 2719 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5 2720 /* VMware HDAudio */
e6232c80 2721 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2722 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2723 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2724 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2725 .class_mask = 0xffffff,
9477c58e 2726 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2727 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2728 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2729 .class_mask = 0xffffff,
9477c58e 2730 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
b6fcab14 2731 /* Zhaoxin */
e6232c80 2732 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
28bd137a 2733 /* Loongson HDAudio*/
e6232c80 2734 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
28bd137a 2735 .driver_data = AZX_DRIVER_LOONGSON },
e6232c80 2736 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
28bd137a 2737 .driver_data = AZX_DRIVER_LOONGSON },
1da177e4
LT		 2738 { 0, }
2739};
2740MODULE_DEVICE_TABLE(pci, azx_ids);
2741
2742/* pci_driver definition */
e9f66d9b 2743static struct pci_driver azx_driver = {
3733e424 2744 .name = KBUILD_MODNAME,
1da177e4
LT		 2745 .id_table = azx_ids,
2746 .probe = azx_probe,
e23e7a14 2747 .remove = azx_remove,
b2a0bafa 2748 .shutdown = azx_shutdown,
68cb2b55 2749 .driver = {
32d7c6cd 2750 .pm = &azx_pm,
68cb2b55 2751 },
1da177e4
LT		 2752};
2753
e9f66d9b 2754module_pci_driver(azx_driver);
Linux 6.x block layer and io_uring tree(s)