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Merge tag 'v3.18-rc7' into for-next
[linux-2.6-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
9121947d 60#include <linux/vgaarb.h>
a82d51ed 61#include <linux/vga_switcheroo.h>
4918cdab 62#include <linux/firmware.h>
1da177e4 63#include "hda_codec.h"
05e84878 64#include "hda_controller.h"
2538a4f5 65#include "hda_priv.h"
e4d9e513 66#include "hda_i915.h"
1da177e4 67
b6050ef6
TI		 68/* position fix mode */
69enum {
70 POS_FIX_AUTO,
71 POS_FIX_LPIB,
72 POS_FIX_POSBUF,
73 POS_FIX_VIACOMBO,
74 POS_FIX_COMBO,
75};
76
9a34af4a
TI		 77/* Defines for ATI HD Audio support in SB450 south bridge */
78#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
79#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
80
81/* Defines for Nvidia HDA support */
82#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
83#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
84#define NVIDIA_HDA_ISTRM_COH 0x4d
85#define NVIDIA_HDA_OSTRM_COH 0x4c
86#define NVIDIA_HDA_ENABLE_COHBIT 0x01
87
88/* Defines for Intel SCH HDA snoop control */
89#define INTEL_SCH_HDA_DEVC 0x78
90#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
91
92/* Define IN stream 0 FIFO size offset in VIA controller */
93#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
94/* Define VIA HD Audio Device ID*/
95#define VIA_HDAC_DEVICE_ID 0x3288
96
33124929
TI		 97/* max number of SDs */
98/* ICH, ATI and VIA have 4 playback and 4 capture */
99#define ICH6_NUM_CAPTURE 4
100#define ICH6_NUM_PLAYBACK 4
101
102/* ULI has 6 playback and 5 capture */
103#define ULI_NUM_CAPTURE 5
104#define ULI_NUM_PLAYBACK 6
105
106/* ATI HDMI may have up to 8 playbacks and 0 capture */
107#define ATIHDMI_NUM_CAPTURE 0
108#define ATIHDMI_NUM_PLAYBACK 8
109
110/* TERA has 4 playback and 3 capture */
111#define TERA_NUM_CAPTURE 3
112#define TERA_NUM_PLAYBACK 4
113
1da177e4 114
5aba4f8e
TI		 115static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
116static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 117static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 118static char *model[SNDRV_CARDS];
1dac6695 119static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 120static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 121static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 122static int probe_only[SNDRV_CARDS];
26a6cb6c 123static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 124static bool single_cmd;
71623855 125static int enable_msi = -1;
4ea6fbc8
TI		 126#ifdef CONFIG_SND_HDA_PATCH_LOADER
127static char *patch[SNDRV_CARDS];
128#endif
2dca0bba 129#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 130static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 131 CONFIG_SND_HDA_INPUT_BEEP_MODE};
132#endif
1da177e4 133
5aba4f8e 134module_param_array(index, int, NULL, 0444);
1da177e4 135MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 136module_param_array(id, charp, NULL, 0444);
1da177e4 137MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 138module_param_array(enable, bool, NULL, 0444);
139MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
140module_param_array(model, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 142module_param_array(position_fix, int, NULL, 0444);
4cb36310 143MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 145module_param_array(bdl_pos_adj, int, NULL, 0644);
146MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 147module_param_array(probe_mask, int, NULL, 0444);
606ad75f 148MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 149module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 150MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 151module_param_array(jackpoll_ms, int, NULL, 0444);
152MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 153module_param(single_cmd, bool, 0444);
d01ce99f
TI		 154MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
155 "(for debugging only).");
ac9ef6cf 156module_param(enable_msi, bint, 0444);
134a11f0 157MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 158#ifdef CONFIG_SND_HDA_PATCH_LOADER
159module_param_array(patch, charp, NULL, 0444);
160MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
161#endif
2dca0bba 162#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 163module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 164MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 165 "(0=off, 1=on) (default=1).");
2dca0bba 166#endif
606ad75f 167
83012a7c 168#ifdef CONFIG_PM
65fcd41d
TI		 169static int param_set_xint(const char *val, const struct kernel_param *kp);
170static struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173};
174#define param_check_xint param_check_int
175
fee2fba3 176static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 177static int *power_save_addr = &power_save;
65fcd41d 178module_param(power_save, xint, 0644);
fee2fba3
TI		 179MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
180 "(in second, 0 = disable).");
1da177e4 181
dee1b66c
TI		 182/* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
8fc24426
TI		 186static bool power_save_controller = 1;
187module_param(power_save_controller, bool, 0644);
dee1b66c 188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 189#else
190static int *power_save_addr;
83012a7c 191#endif /* CONFIG_PM */
dee1b66c 192
7bfe059e
TI		 193static int align_buffer_size = -1;
194module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 195MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
27fe48d9 198#ifdef CONFIG_X86
7c732015
TI		 199static int hda_snoop = -1;
200module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 201MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 202#else
203#define hda_snoop true
27fe48d9
TI		 204#endif
205
206
1da177e4
LT		 207MODULE_LICENSE("GPL");
208MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
209 "{Intel, ICH6M},"
2f1b3818 210 "{Intel, ICH7},"
f5d40b30 211 "{Intel, ESB2},"
d2981393 212 "{Intel, ICH8},"
f9cc8a8b 213 "{Intel, ICH9},"
c34f5a04 214 "{Intel, ICH10},"
b29c2360 215 "{Intel, PCH},"
d2f2fcd2 216 "{Intel, CPT},"
d2edeb7c 217 "{Intel, PPT},"
8bc039a1 218 "{Intel, LPT},"
144dad99 219 "{Intel, LPT_LP},"
4eeca499 220 "{Intel, WPT_LP},"
c8b00fd2 221 "{Intel, SPT},"
b4565913 222 "{Intel, SPT_LP},"
e926f2c8 223 "{Intel, HPT},"
cea310e8 224 "{Intel, PBG},"
4979bca9 225 "{Intel, SCH},"
fc20a562 226 "{ATI, SB450},"
89be83f8 227 "{ATI, SB600},"
778b6e1b 228 "{ATI, RS600},"
5b15c95f 229 "{ATI, RS690},"
e6db1119
WL		 230 "{ATI, RS780},"
231 "{ATI, R600},"
2797f724
HRK		 232 "{ATI, RV630},"
233 "{ATI, RV610},"
27da1834
WL		 234 "{ATI, RV670},"
235 "{ATI, RV635},"
236 "{ATI, RV620},"
237 "{ATI, RV770},"
fc20a562 238 "{VIA, VT8251},"
47672310 239 "{VIA, VT8237A},"
07e4ca50
TI		 240 "{SiS, SIS966},"
241 "{ULI, M5461}}");
1da177e4
LT		 242MODULE_DESCRIPTION("Intel HDA driver");
243
a82d51ed 244#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 245#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 246#define SUPPORT_VGA_SWITCHEROO
247#endif
248#endif
249
250
1da177e4 251/*
1da177e4 252 */
1da177e4 253
07e4ca50
TI		 254/* driver types */
255enum {
256 AZX_DRIVER_ICH,
32679f95 257 AZX_DRIVER_PCH,
4979bca9 258 AZX_DRIVER_SCH,
fab1285a 259 AZX_DRIVER_HDMI,
07e4ca50 260 AZX_DRIVER_ATI,
778b6e1b 261 AZX_DRIVER_ATIHDMI,
1815b34a 262 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 263 AZX_DRIVER_VIA,
264 AZX_DRIVER_SIS,
265 AZX_DRIVER_ULI,
da3fca21 266 AZX_DRIVER_NVIDIA,
f269002e 267 AZX_DRIVER_TERA,
14d34f16 268 AZX_DRIVER_CTX,
5ae763b1 269 AZX_DRIVER_CTHDA,
c563f473 270 AZX_DRIVER_CMEDIA,
c4da29ca 271 AZX_DRIVER_GENERIC,
2f5983f2 272 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 273};
274
37e661ee
TI		 275#define azx_get_snoop_type(chip) \
276 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
277#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
278
2ea3c6a2 279/* quirks for Intel PCH */
d7dab4db 280#define AZX_DCAPS_INTEL_PCH_NOPM \
37e661ee
TI		 281 (AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
282 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db
TI		 283
284#define AZX_DCAPS_INTEL_PCH \
285 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 286
33499a15 287#define AZX_DCAPS_INTEL_HASWELL \
37e661ee
TI		 288 (AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
289 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
290 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 291
54a0405d
LY		 292/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
293#define AZX_DCAPS_INTEL_BROADWELL \
37e661ee
TI		 294 (AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_POSFIX_LPIB |\
295 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
296 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 297
9477c58e
TI		 298/* quirks for ATI SB / AMD Hudson */
299#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
301 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 302
303/* quirks for ATI/AMD HDMI */
304#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 305 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
306 AZX_DCAPS_NO_MSI64)
9477c58e 307
37e661ee
TI		 308/* quirks for ATI HDMI with snoop off */
309#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
310 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
311
9477c58e
TI		 312/* quirks for Nvidia */
313#define AZX_DCAPS_PRESET_NVIDIA \
37e661ee
TI		 314 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | AZX_DCAPS_ALIGN_BUFSIZE |\
315 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
316 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 317
5ae763b1 318#define AZX_DCAPS_PRESET_CTHDA \
37e661ee
TI		 319 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
320 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 321
a82d51ed
TI		 322/*
323 * VGA-switcher support
324 */
325#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 326#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
327#else
328#define use_vga_switcheroo(chip) 0
329#endif
330
48c8b0eb 331static char *driver_short_names[] = {
07e4ca50 332 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 333 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 334 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 335 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 336 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 337 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 338 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 339 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
340 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 341 [AZX_DRIVER_ULI] = "HDA ULI M5461",
342 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 343 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 344 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 345 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 346 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 347 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 348};
349
a07187c9
ML		 350struct hda_intel {
351 struct azx chip;
352
9a34af4a
TI		 353 /* for pending irqs */
354 struct work_struct irq_pending_work;
355
356 /* sync probing */
357 struct completion probe_wait;
358 struct work_struct probe_work;
359
360 /* card list (for power_save trigger) */
361 struct list_head list;
362
363 /* extra flags */
364 unsigned int irq_pending_warned:1;
365
366 /* VGA-switcheroo setup */
367 unsigned int use_vga_switcheroo:1;
368 unsigned int vga_switcheroo_registered:1;
369 unsigned int init_failed:1; /* delayed init failed */
370
371 /* secondary power domain for hdmi audio under vga device */
372 struct dev_pm_domain hdmi_pm_domain;
373};
a07187c9 374
27fe48d9 375#ifdef CONFIG_X86
9ddf1aeb 376static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 377{
9ddf1aeb
TI		 378 int pages;
379
27fe48d9
TI		 380 if (azx_snoop(chip))
381 return;
9ddf1aeb
TI		 382 if (!dmab || !dmab->area || !dmab->bytes)
383 return;
384
385#ifdef CONFIG_SND_DMA_SGBUF
386 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
387 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 388 if (chip->driver_type == AZX_DRIVER_CMEDIA)
389 return; /* deal with only CORB/RIRB buffers */
27fe48d9 390 if (on)
9ddf1aeb 391 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 392 else
9ddf1aeb
TI		 393 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
394 return;
27fe48d9 395 }
9ddf1aeb
TI		 396#endif
397
398 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
399 if (on)
400 set_memory_wc((unsigned long)dmab->area, pages);
401 else
402 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 403}
404
405static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
406 bool on)
407{
9ddf1aeb 408 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 409}
410static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 411 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 412{
413 if (azx_dev->wc_marked != on) {
9ddf1aeb 414 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 415 azx_dev->wc_marked = on;
416 }
417}
418#else
419/* NOP for other archs */
420static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
421 bool on)
422{
423}
424static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 425 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 426{
427}
428#endif
429
68e7fffc 430static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 431
cb53c626
TI		 432/*
433 * initialize the PCI registers
434 */
435/* update bits in a PCI register byte */
436static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
437 unsigned char mask, unsigned char val)
438{
439 unsigned char data;
440
441 pci_read_config_byte(pci, reg, &data);
442 data &= ~mask;
443 data |= (val & mask);
444 pci_write_config_byte(pci, reg, data);
445}
446
447static void azx_init_pci(struct azx *chip)
448{
37e661ee
TI		 449 int snoop_type = azx_get_snoop_type(chip);
450
cb53c626
TI		 451 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
452 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
453 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 454 * codecs.
455 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 456 */
46f2cc80 457 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 458 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 459 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 460 }
cb53c626 461
9477c58e
TI		 462 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
463 * we need to enable snoop.
464 */
37e661ee 465 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 466 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
467 azx_snoop(chip));
cb53c626 468 update_pci_byte(chip->pci,
27fe48d9
TI		 469 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
470 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 471 }
472
473 /* For NVIDIA HDA, enable snoop */
37e661ee 474 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 475 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
476 azx_snoop(chip));
cb53c626
TI		 477 update_pci_byte(chip->pci,
478 NVIDIA_HDA_TRANSREG_ADDR,
479 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 480 update_pci_byte(chip->pci,
481 NVIDIA_HDA_ISTRM_COH,
482 0x01, NVIDIA_HDA_ENABLE_COHBIT);
483 update_pci_byte(chip->pci,
484 NVIDIA_HDA_OSTRM_COH,
485 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 486 }
487
488 /* Enable SCH/PCH snoop if needed */
37e661ee 489 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 490 unsigned short snoop;
90a5ad52 491 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 492 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
493 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
494 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
495 if (!azx_snoop(chip))
496 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
497 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 498 pci_read_config_word(chip->pci,
499 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 500 }
4e76a883
TI		 501 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
502 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
503 "Disabled" : "Enabled");
da3fca21 504 }
1da177e4
LT		 505}
506
b6050ef6
TI		 507/* calculate runtime delay from LPIB */
508static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
509 unsigned int pos)
510{
511 struct snd_pcm_substream *substream = azx_dev->substream;
512 int stream = substream->stream;
513 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
514 int delay;
515
516 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
517 delay = pos - lpib_pos;
518 else
519 delay = lpib_pos - pos;
520 if (delay < 0) {
521 if (delay >= azx_dev->delay_negative_threshold)
522 delay = 0;
523 else
524 delay += azx_dev->bufsize;
525 }
526
527 if (delay >= azx_dev->period_bytes) {
528 dev_info(chip->card->dev,
529 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
530 delay, azx_dev->period_bytes);
531 delay = 0;
532 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
533 chip->get_delay[stream] = NULL;
534 }
535
536 return bytes_to_frames(substream->runtime, delay);
537}
538
9ad593f6
TI		 539static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
540
7ca954a8
DR		 541/* called from IRQ */
542static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
543{
9a34af4a 544 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 545 int ok;
546
547 ok = azx_position_ok(chip, azx_dev);
548 if (ok == 1) {
549 azx_dev->irq_pending = 0;
550 return ok;
551 } else if (ok == 0 && chip->bus && chip->bus->workq) {
552 /* bogus IRQ, process it later */
553 azx_dev->irq_pending = 1;
9a34af4a 554 queue_work(chip->bus->workq, &hda->irq_pending_work);
7ca954a8
DR		 555 }
556 return 0;
557}
558
9ad593f6
TI		 559/*
560 * Check whether the current DMA position is acceptable for updating
561 * periods. Returns non-zero if it's OK.
562 *
563 * Many HD-audio controllers appear pretty inaccurate about
564 * the update-IRQ timing. The IRQ is issued before actually the
565 * data is processed. So, we need to process it afterwords in a
566 * workqueue.
567 */
568static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
569{
b6050ef6
TI		 570 struct snd_pcm_substream *substream = azx_dev->substream;
571 int stream = substream->stream;
e5463720 572 u32 wallclk;
9ad593f6
TI		 573 unsigned int pos;
574
f48f606d
JK		 575 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
576 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 577 return -1; /* bogus (too early) interrupt */
fa00e046 578
b6050ef6
TI		 579 if (chip->get_position[stream])
580 pos = chip->get_position[stream](chip, azx_dev);
581 else { /* use the position buffer as default */
582 pos = azx_get_pos_posbuf(chip, azx_dev);
583 if (!pos || pos == (u32)-1) {
584 dev_info(chip->card->dev,
585 "Invalid position buffer, using LPIB read method instead.\n");
586 chip->get_position[stream] = azx_get_pos_lpib;
587 pos = azx_get_pos_lpib(chip, azx_dev);
588 chip->get_delay[stream] = NULL;
589 } else {
590 chip->get_position[stream] = azx_get_pos_posbuf;
591 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
592 chip->get_delay[stream] = azx_get_delay_from_lpib;
593 }
594 }
595
596 if (pos >= azx_dev->bufsize)
597 pos = 0;
9ad593f6 598
d6d8bf54
TI		 599 if (WARN_ONCE(!azx_dev->period_bytes,
600 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 601 return -1; /* this shouldn't happen! */
edb39935 602 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 603 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
604 /* NG - it's below the first next period boundary */
9cdc0115 605 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 606 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 607 return 1; /* OK, it's fine */
608}
609
610/*
611 * The work for pending PCM period updates.
612 */
613static void azx_irq_pending_work(struct work_struct *work)
614{
9a34af4a
TI		 615 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
616 struct azx *chip = &hda->chip;
e5463720 617 int i, pending, ok;
9ad593f6 618
9a34af4a 619 if (!hda->irq_pending_warned) {
4e76a883
TI		 620 dev_info(chip->card->dev,
621 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
622 chip->card->number);
9a34af4a 623 hda->irq_pending_warned = 1;
a6a950a8
TI		 624 }
625
9ad593f6
TI		 626 for (;;) {
627 pending = 0;
628 spin_lock_irq(&chip->reg_lock);
629 for (i = 0; i < chip->num_streams; i++) {
630 struct azx_dev *azx_dev = &chip->azx_dev[i];
631 if (!azx_dev->irq_pending ||
632 !azx_dev->substream ||
633 !azx_dev->running)
634 continue;
e5463720
JK		 635 ok = azx_position_ok(chip, azx_dev);
636 if (ok > 0) {
9ad593f6
TI		 637 azx_dev->irq_pending = 0;
638 spin_unlock(&chip->reg_lock);
639 snd_pcm_period_elapsed(azx_dev->substream);
640 spin_lock(&chip->reg_lock);
e5463720
JK		 641 } else if (ok < 0) {
642 pending = 0; /* too early */
9ad593f6
TI		 643 } else
644 pending++;
645 }
646 spin_unlock_irq(&chip->reg_lock);
647 if (!pending)
648 return;
08af495f 649 msleep(1);
9ad593f6
TI		 650 }
651}
652
653/* clear irq_pending flags and assure no on-going workq */
654static void azx_clear_irq_pending(struct azx *chip)
655{
656 int i;
657
658 spin_lock_irq(&chip->reg_lock);
659 for (i = 0; i < chip->num_streams; i++)
660 chip->azx_dev[i].irq_pending = 0;
661 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 662}
663
68e7fffc
TI		 664static int azx_acquire_irq(struct azx *chip, int do_disconnect)
665{
437a5a46
TI		 666 if (request_irq(chip->pci->irq, azx_interrupt,
667 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 668 KBUILD_MODNAME, chip)) {
4e76a883
TI		 669 dev_err(chip->card->dev,
670 "unable to grab IRQ %d, disabling device\n",
671 chip->pci->irq);
68e7fffc
TI		 672 if (do_disconnect)
673 snd_card_disconnect(chip->card);
674 return -1;
675 }
676 chip->irq = chip->pci->irq;
69e13418 677 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 678 return 0;
679}
680
b6050ef6
TI		 681/* get the current DMA position with correction on VIA chips */
682static unsigned int azx_via_get_position(struct azx *chip,
683 struct azx_dev *azx_dev)
684{
685 unsigned int link_pos, mini_pos, bound_pos;
686 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
687 unsigned int fifo_size;
688
689 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
690 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
691 /* Playback, no problem using link position */
692 return link_pos;
693 }
694
695 /* Capture */
696 /* For new chipset,
697 * use mod to get the DMA position just like old chipset
698 */
699 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
700 mod_dma_pos %= azx_dev->period_bytes;
701
702 /* azx_dev->fifo_size can't get FIFO size of in stream.
703 * Get from base address + offset.
704 */
705 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
706
707 if (azx_dev->insufficient) {
708 /* Link position never gather than FIFO size */
709 if (link_pos <= fifo_size)
710 return 0;
711
712 azx_dev->insufficient = 0;
713 }
714
715 if (link_pos <= fifo_size)
716 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
717 else
718 mini_pos = link_pos - fifo_size;
719
720 /* Find nearest previous boudary */
721 mod_mini_pos = mini_pos % azx_dev->period_bytes;
722 mod_link_pos = link_pos % azx_dev->period_bytes;
723 if (mod_link_pos >= fifo_size)
724 bound_pos = link_pos - mod_link_pos;
725 else if (mod_dma_pos >= mod_mini_pos)
726 bound_pos = mini_pos - mod_mini_pos;
727 else {
728 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
729 if (bound_pos >= azx_dev->bufsize)
730 bound_pos = 0;
731 }
732
733 /* Calculate real DMA position we want */
734 return bound_pos + mod_dma_pos;
735}
736
83012a7c 737#ifdef CONFIG_PM
65fcd41d
TI		 738static DEFINE_MUTEX(card_list_lock);
739static LIST_HEAD(card_list);
740
741static void azx_add_card_list(struct azx *chip)
742{
9a34af4a 743 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 744 mutex_lock(&card_list_lock);
9a34af4a 745 list_add(&hda->list, &card_list);
65fcd41d
TI		 746 mutex_unlock(&card_list_lock);
747}
748
749static void azx_del_card_list(struct azx *chip)
750{
9a34af4a 751 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 752 mutex_lock(&card_list_lock);
9a34af4a 753 list_del_init(&hda->list);
65fcd41d
TI		 754 mutex_unlock(&card_list_lock);
755}
756
757/* trigger power-save check at writing parameter */
758static int param_set_xint(const char *val, const struct kernel_param *kp)
759{
9a34af4a 760 struct hda_intel *hda;
65fcd41d
TI		 761 struct azx *chip;
762 struct hda_codec *c;
763 int prev = power_save;
764 int ret = param_set_int(val, kp);
765
766 if (ret || prev == power_save)
767 return ret;
768
769 mutex_lock(&card_list_lock);
9a34af4a
TI		 770 list_for_each_entry(hda, &card_list, list) {
771 chip = &hda->chip;
65fcd41d
TI		 772 if (!chip->bus || chip->disabled)
773 continue;
774 list_for_each_entry(c, &chip->bus->codec_list, list)
775 snd_hda_power_sync(c);
776 }
777 mutex_unlock(&card_list_lock);
778 return 0;
779}
780#else
781#define azx_add_card_list(chip) /* NOP */
782#define azx_del_card_list(chip) /* NOP */
83012a7c 783#endif /* CONFIG_PM */
5c0b9bec 784
7ccbde57 785#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 786/*
787 * power management
788 */
68cb2b55 789static int azx_suspend(struct device *dev)
1da177e4 790{
68cb2b55
TI		 791 struct pci_dev *pci = to_pci_dev(dev);
792 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 793 struct azx *chip;
794 struct hda_intel *hda;
01b65bfb 795 struct azx_pcm *p;
1da177e4 796
2d9772ef
TI		 797 if (!card)
798 return 0;
799
800 chip = card->private_data;
801 hda = container_of(chip, struct hda_intel, chip);
1618e84a 802 if (chip->disabled || hda->init_failed)
c5c21523
TI		 803 return 0;
804
421a1252 805 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 806 azx_clear_irq_pending(chip);
01b65bfb
TI		 807 list_for_each_entry(p, &chip->pcm_list, list)
808 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 809 if (chip->initialized)
8dd78330 810 snd_hda_suspend(chip->bus);
cb53c626 811 azx_stop_chip(chip);
7295b264 812 azx_enter_link_reset(chip);
30b35399 813 if (chip->irq >= 0) {
43001c95 814 free_irq(chip->irq, chip);
30b35399
TI		 815 chip->irq = -1;
816 }
a07187c9 817
68e7fffc 818 if (chip->msi)
43001c95 819 pci_disable_msi(chip->pci);
421a1252
TI		 820 pci_disable_device(pci);
821 pci_save_state(pci);
68cb2b55 822 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 823 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
824 hda_display_power(false);
1da177e4
LT		 825 return 0;
826}
827
68cb2b55 828static int azx_resume(struct device *dev)
1da177e4 829{
68cb2b55
TI		 830 struct pci_dev *pci = to_pci_dev(dev);
831 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 832 struct azx *chip;
833 struct hda_intel *hda;
834
835 if (!card)
836 return 0;
1da177e4 837
2d9772ef
TI		 838 chip = card->private_data;
839 hda = container_of(chip, struct hda_intel, chip);
1618e84a 840 if (chip->disabled || hda->init_failed)
c5c21523
TI		 841 return 0;
842
a07187c9 843 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 844 hda_display_power(true);
e4d9e513 845 haswell_set_bclk(chip);
a07187c9 846 }
d14a7e0b
TI		 847 pci_set_power_state(pci, PCI_D0);
848 pci_restore_state(pci);
30b35399 849 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 850 dev_err(chip->card->dev,
851 "pci_enable_device failed, disabling device\n");
30b35399
TI		 852 snd_card_disconnect(card);
853 return -EIO;
854 }
855 pci_set_master(pci);
68e7fffc
TI		 856 if (chip->msi)
857 if (pci_enable_msi(pci) < 0)
858 chip->msi = 0;
859 if (azx_acquire_irq(chip, 1) < 0)
30b35399 860 return -EIO;
cb53c626 861 azx_init_pci(chip);
d804ad92 862
17c3ad03 863 azx_init_chip(chip, true);
d804ad92 864
1da177e4 865 snd_hda_resume(chip->bus);
421a1252 866 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 867 return 0;
868}
b8dfc462
ML		 869#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
870
871#ifdef CONFIG_PM_RUNTIME
872static int azx_runtime_suspend(struct device *dev)
873{
874 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 875 struct azx *chip;
876 struct hda_intel *hda;
b8dfc462 877
2d9772ef
TI		 878 if (!card)
879 return 0;
880
881 chip = card->private_data;
882 hda = container_of(chip, struct hda_intel, chip);
1618e84a 883 if (chip->disabled || hda->init_failed)
246efa4a
DA		 884 return 0;
885
886 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
887 return 0;
888
7d4f606c
WX		 889 /* enable controller wake up event */
890 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
891 STATESTS_INT_MASK);
892
b8dfc462 893 azx_stop_chip(chip);
873ce8ad 894 azx_enter_link_reset(chip);
b8dfc462 895 azx_clear_irq_pending(chip);
e4d9e513 896 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
99a2008d 897 hda_display_power(false);
e4d9e513 898
b8dfc462
ML		 899 return 0;
900}
901
902static int azx_runtime_resume(struct device *dev)
903{
904 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 905 struct azx *chip;
906 struct hda_intel *hda;
7d4f606c
WX		 907 struct hda_bus *bus;
908 struct hda_codec *codec;
909 int status;
b8dfc462 910
2d9772ef
TI		 911 if (!card)
912 return 0;
913
914 chip = card->private_data;
915 hda = container_of(chip, struct hda_intel, chip);
1618e84a 916 if (chip->disabled || hda->init_failed)
246efa4a
DA		 917 return 0;
918
919 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
920 return 0;
921
a07187c9 922 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 923 hda_display_power(true);
e4d9e513 924 haswell_set_bclk(chip);
a07187c9 925 }
7d4f606c
WX		 926
927 /* Read STATESTS before controller reset */
928 status = azx_readw(chip, STATESTS);
929
b8dfc462 930 azx_init_pci(chip);
17c3ad03 931 azx_init_chip(chip, true);
7d4f606c
WX		 932
933 bus = chip->bus;
934 if (status && bus) {
935 list_for_each_entry(codec, &bus->codec_list, list)
936 if (status & (1 << codec->addr))
937 queue_delayed_work(codec->bus->workq,
938 &codec->jackpoll_work, codec->jackpoll_interval);
939 }
940
941 /* disable controller Wake Up event*/
942 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
943 ~STATESTS_INT_MASK);
944
b8dfc462
ML		 945 return 0;
946}
6eb827d2
TI		 947
948static int azx_runtime_idle(struct device *dev)
949{
950 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 951 struct azx *chip;
952 struct hda_intel *hda;
953
954 if (!card)
955 return 0;
6eb827d2 956
2d9772ef
TI		 957 chip = card->private_data;
958 hda = container_of(chip, struct hda_intel, chip);
1618e84a 959 if (chip->disabled || hda->init_failed)
246efa4a
DA		 960 return 0;
961
6eb827d2
TI		 962 if (!power_save_controller ||
963 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
964 return -EBUSY;
965
966 return 0;
967}
968
b8dfc462
ML		 969#endif /* CONFIG_PM_RUNTIME */
970
971#ifdef CONFIG_PM
972static const struct dev_pm_ops azx_pm = {
973 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 974 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 975};
976
68cb2b55
TI		 977#define AZX_PM_OPS &azx_pm
978#else
68cb2b55 979#define AZX_PM_OPS NULL
b8dfc462 980#endif /* CONFIG_PM */
1da177e4
LT		 981
982
48c8b0eb 983static int azx_probe_continue(struct azx *chip);
a82d51ed 984
8393ec4a 985#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 986static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 987
a82d51ed
TI		 988static void azx_vs_set_state(struct pci_dev *pci,
989 enum vga_switcheroo_state state)
990{
991 struct snd_card *card = pci_get_drvdata(pci);
992 struct azx *chip = card->private_data;
9a34af4a 993 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 994 bool disabled;
995
9a34af4a
TI		 996 wait_for_completion(&hda->probe_wait);
997 if (hda->init_failed)
a82d51ed
TI		 998 return;
999
1000 disabled = (state == VGA_SWITCHEROO_OFF);
1001 if (chip->disabled == disabled)
1002 return;
1003
1004 if (!chip->bus) {
1005 chip->disabled = disabled;
1006 if (!disabled) {
4e76a883
TI		 1007 dev_info(chip->card->dev,
1008 "Start delayed initialization\n");
5c90680e 1009 if (azx_probe_continue(chip) < 0) {
4e76a883 1010 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1011 hda->init_failed = true;
a82d51ed
TI		 1012 }
1013 }
1014 } else {
4e76a883
TI		 1015 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1016 disabled ? "Disabling" : "Enabling");
a82d51ed 1017 if (disabled) {
8928756d
DR		 1018 pm_runtime_put_sync_suspend(card->dev);
1019 azx_suspend(card->dev);
246efa4a
DA		 1020 /* when we get suspended by vga switcheroo we end up in D3cold,
1021 * however we have no ACPI handle, so pci/acpi can't put us there,
1022 * put ourselves there */
1023 pci->current_state = PCI_D3cold;
a82d51ed 1024 chip->disabled = true;
128960a9 1025 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 1026 dev_warn(chip->card->dev,
1027 "Cannot lock devices!\n");
a82d51ed
TI		 1028 } else {
1029 snd_hda_unlock_devices(chip->bus);
8928756d 1030 pm_runtime_get_noresume(card->dev);
a82d51ed 1031 chip->disabled = false;
8928756d 1032 azx_resume(card->dev);
a82d51ed
TI		 1033 }
1034 }
1035}
1036
1037static bool azx_vs_can_switch(struct pci_dev *pci)
1038{
1039 struct snd_card *card = pci_get_drvdata(pci);
1040 struct azx *chip = card->private_data;
9a34af4a 1041 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1042
9a34af4a
TI		 1043 wait_for_completion(&hda->probe_wait);
1044 if (hda->init_failed)
a82d51ed
TI		 1045 return false;
1046 if (chip->disabled || !chip->bus)
1047 return true;
1048 if (snd_hda_lock_devices(chip->bus))
1049 return false;
1050 snd_hda_unlock_devices(chip->bus);
1051 return true;
1052}
1053
e23e7a14 1054static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1055{
9a34af4a 1056 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1057 struct pci_dev *p = get_bound_vga(chip->pci);
1058 if (p) {
4e76a883
TI		 1059 dev_info(chip->card->dev,
1060 "Handle VGA-switcheroo audio client\n");
9a34af4a 1061 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1062 pci_dev_put(p);
1063 }
1064}
1065
1066static const struct vga_switcheroo_client_ops azx_vs_ops = {
1067 .set_gpu_state = azx_vs_set_state,
1068 .can_switch = azx_vs_can_switch,
1069};
1070
e23e7a14 1071static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1072{
9a34af4a 1073 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1074 int err;
1075
9a34af4a 1076 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1077 return 0;
1078 /* FIXME: currently only handling DIS controller
1079 * is there any machine with two switchable HDMI audio controllers?
1080 */
128960a9 1081 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 1082 VGA_SWITCHEROO_DIS,
1083 chip->bus != NULL);
128960a9
TI		 1084 if (err < 0)
1085 return err;
9a34af4a 1086 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1087
1088 /* register as an optimus hdmi audio power domain */
8928756d 1089 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1090 &hda->hdmi_pm_domain);
128960a9 1091 return 0;
a82d51ed
TI		 1092}
1093#else
1094#define init_vga_switcheroo(chip) /* NOP */
1095#define register_vga_switcheroo(chip) 0
8393ec4a 1096#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1097#endif /* SUPPORT_VGA_SWITCHER */
1098
1da177e4
LT		 1099/*
1100 * destructor
1101 */
a98f90fd 1102static int azx_free(struct azx *chip)
1da177e4 1103{
c67e2228 1104 struct pci_dev *pci = chip->pci;
a07187c9 1105 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4ce107b9
TI		 1106 int i;
1107
c67e2228
WX		 1108 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1109 && chip->running)
1110 pm_runtime_get_noresume(&pci->dev);
1111
65fcd41d
TI		 1112 azx_del_card_list(chip);
1113
0cbf0098
TI		 1114 azx_notifier_unregister(chip);
1115
9a34af4a
TI		 1116 hda->init_failed = 1; /* to be sure */
1117 complete_all(&hda->probe_wait);
f4c482a4 1118
9a34af4a 1119 if (use_vga_switcheroo(hda)) {
a82d51ed
TI		 1120 if (chip->disabled && chip->bus)
1121 snd_hda_unlock_devices(chip->bus);
9a34af4a 1122 if (hda->vga_switcheroo_registered)
128960a9 1123 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1124 }
1125
ce43fbae 1126 if (chip->initialized) {
9ad593f6 1127 azx_clear_irq_pending(chip);
07e4ca50 1128 for (i = 0; i < chip->num_streams; i++)
1da177e4 1129 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1130 azx_stop_chip(chip);
1da177e4
LT		 1131 }
1132
f000fd80 1133 if (chip->irq >= 0)
1da177e4 1134 free_irq(chip->irq, (void*)chip);
68e7fffc 1135 if (chip->msi)
30b35399 1136 pci_disable_msi(chip->pci);
f079c25a
TI		 1137 if (chip->remap_addr)
1138 iounmap(chip->remap_addr);
1da177e4 1139
67908994 1140 azx_free_stream_pages(chip);
a82d51ed
TI		 1141 if (chip->region_requested)
1142 pci_release_regions(chip->pci);
1da177e4 1143 pci_disable_device(chip->pci);
07e4ca50 1144 kfree(chip->azx_dev);
4918cdab 1145#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1146 release_firmware(chip->fw);
4918cdab 1147#endif
99a2008d
WX		 1148 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1149 hda_display_power(false);
1150 hda_i915_exit();
1151 }
a07187c9 1152 kfree(hda);
1da177e4
LT		 1153
1154 return 0;
1155}
1156
a98f90fd 1157static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1158{
1159 return azx_free(device->device_data);
1160}
1161
8393ec4a 1162#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1163/*
1164 * Check of disabled HDMI controller by vga-switcheroo
1165 */
e23e7a14 1166static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1167{
1168 struct pci_dev *p;
1169
1170 /* check only discrete GPU */
1171 switch (pci->vendor) {
1172 case PCI_VENDOR_ID_ATI:
1173 case PCI_VENDOR_ID_AMD:
1174 case PCI_VENDOR_ID_NVIDIA:
1175 if (pci->devfn == 1) {
1176 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1177 pci->bus->number, 0);
1178 if (p) {
1179 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1180 return p;
1181 pci_dev_put(p);
1182 }
1183 }
1184 break;
1185 }
1186 return NULL;
1187}
1188
e23e7a14 1189static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1190{
1191 bool vga_inactive = false;
1192 struct pci_dev *p = get_bound_vga(pci);
1193
1194 if (p) {
12b78a7f 1195 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1196 vga_inactive = true;
1197 pci_dev_put(p);
1198 }
1199 return vga_inactive;
1200}
8393ec4a 1201#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1202
3372a153
TI		 1203/*
1204 * white/black-listing for position_fix
1205 */
e23e7a14 1206static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1207 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1208 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1209 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1210 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1211 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1212 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1213 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1214 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1215 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1216 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1217 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1218 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1219 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1220 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1221 {}
1222};
1223
e23e7a14 1224static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1225{
1226 const struct snd_pci_quirk *q;
1227
c673ba1c 1228 switch (fix) {
1dac6695 1229 case POS_FIX_AUTO:
c673ba1c
TI		 1230 case POS_FIX_LPIB:
1231 case POS_FIX_POSBUF:
4cb36310 1232 case POS_FIX_VIACOMBO:
a6f2fd55 1233 case POS_FIX_COMBO:
c673ba1c
TI		 1234 return fix;
1235 }
1236
c673ba1c
TI		 1237 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1238 if (q) {
4e76a883
TI		 1239 dev_info(chip->card->dev,
1240 "position_fix set to %d for device %04x:%04x\n",
1241 q->value, q->subvendor, q->subdevice);
c673ba1c 1242 return q->value;
3372a153 1243 }
bdd9ef24
DH		 1244
1245 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1246 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1247 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1248 return POS_FIX_VIACOMBO;
9477c58e
TI		 1249 }
1250 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1251 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1252 return POS_FIX_LPIB;
bdd9ef24 1253 }
c673ba1c 1254 return POS_FIX_AUTO;
3372a153
TI		 1255}
1256
b6050ef6
TI		 1257static void assign_position_fix(struct azx *chip, int fix)
1258{
1259 static azx_get_pos_callback_t callbacks[] = {
1260 [POS_FIX_AUTO] = NULL,
1261 [POS_FIX_LPIB] = azx_get_pos_lpib,
1262 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1263 [POS_FIX_VIACOMBO] = azx_via_get_position,
1264 [POS_FIX_COMBO] = azx_get_pos_lpib,
1265 };
1266
1267 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1268
1269 /* combo mode uses LPIB only for playback */
1270 if (fix == POS_FIX_COMBO)
1271 chip->get_position[1] = NULL;
1272
1273 if (fix == POS_FIX_POSBUF &&
1274 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1275 chip->get_delay[0] = chip->get_delay[1] =
1276 azx_get_delay_from_lpib;
1277 }
1278
1279}
1280
669ba27a
TI		 1281/*
1282 * black-lists for probe_mask
1283 */
e23e7a14 1284static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1285 /* Thinkpad often breaks the controller communication when accessing
1286 * to the non-working (or non-existing) modem codec slot.
1287 */
1288 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1289 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1290 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1291 /* broken BIOS */
1292 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1293 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1294 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1295 /* forced codec slots */
93574844 1296 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1297 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1298 /* WinFast VP200 H (Teradici) user reported broken communication */
1299 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1300 {}
1301};
1302
f1eaaeec
TI		 1303#define AZX_FORCE_CODEC_MASK 0x100
1304
e23e7a14 1305static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1306{
1307 const struct snd_pci_quirk *q;
1308
f1eaaeec
TI		 1309 chip->codec_probe_mask = probe_mask[dev];
1310 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1311 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1312 if (q) {
4e76a883
TI		 1313 dev_info(chip->card->dev,
1314 "probe_mask set to 0x%x for device %04x:%04x\n",
1315 q->value, q->subvendor, q->subdevice);
f1eaaeec 1316 chip->codec_probe_mask = q->value;
669ba27a
TI		 1317 }
1318 }
f1eaaeec
TI		 1319
1320 /* check forced option */
1321 if (chip->codec_probe_mask != -1 &&
1322 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1323 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1324 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1325 chip->codec_mask);
f1eaaeec 1326 }
669ba27a
TI		 1327}
1328
4d8e22e0 1329/*
71623855 1330 * white/black-list for enable_msi
4d8e22e0 1331 */
e23e7a14 1332static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1333 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1334 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1335 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1336 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1337 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1338 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1339 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1340 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1341 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1342 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1343 {}
1344};
1345
e23e7a14 1346static void check_msi(struct azx *chip)
4d8e22e0
TI		 1347{
1348 const struct snd_pci_quirk *q;
1349
71623855
TI		 1350 if (enable_msi >= 0) {
1351 chip->msi = !!enable_msi;
4d8e22e0 1352 return;
71623855
TI		 1353 }
1354 chip->msi = 1; /* enable MSI as default */
1355 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1356 if (q) {
4e76a883
TI		 1357 dev_info(chip->card->dev,
1358 "msi for device %04x:%04x set to %d\n",
1359 q->subvendor, q->subdevice, q->value);
4d8e22e0 1360 chip->msi = q->value;
80c43ed7
TI		 1361 return;
1362 }
1363
1364 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1365 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1366 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1367 chip->msi = 0;
4d8e22e0
TI		 1368 }
1369}
1370
a1585d76 1371/* check the snoop mode availability */
e23e7a14 1372static void azx_check_snoop_available(struct azx *chip)
a1585d76 1373{
7c732015 1374 int snoop = hda_snoop;
a1585d76 1375
7c732015
TI		 1376 if (snoop >= 0) {
1377 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1378 snoop ? "snoop" : "non-snoop");
1379 chip->snoop = snoop;
1380 return;
1381 }
1382
1383 snoop = true;
37e661ee
TI		 1384 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1385 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1386 /* force to non-snoop mode for a new VIA controller
1387 * when BIOS is set
1388 */
7c732015
TI		 1389 u8 val;
1390 pci_read_config_byte(chip->pci, 0x42, &val);
1391 if (!(val & 0x80) && chip->pci->revision == 0x30)
1392 snoop = false;
a1585d76
TI		 1393 }
1394
37e661ee
TI		 1395 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1396 snoop = false;
1397
7c732015
TI		 1398 chip->snoop = snoop;
1399 if (!snoop)
1400 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1401}
669ba27a 1402
99a2008d
WX		 1403static void azx_probe_work(struct work_struct *work)
1404{
9a34af4a
TI		 1405 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1406 azx_probe_continue(&hda->chip);
99a2008d 1407}
99a2008d 1408
1da177e4
LT		 1409/*
1410 * constructor
1411 */
e23e7a14
BP		 1412static int azx_create(struct snd_card *card, struct pci_dev *pci,
1413 int dev, unsigned int driver_caps,
40830813 1414 const struct hda_controller_ops *hda_ops,
e23e7a14 1415 struct azx **rchip)
1da177e4 1416{
a98f90fd 1417 static struct snd_device_ops ops = {
1da177e4
LT		 1418 .dev_free = azx_dev_free,
1419 };
a07187c9 1420 struct hda_intel *hda;
a82d51ed
TI		 1421 struct azx *chip;
1422 int err;
1da177e4
LT		 1423
1424 *rchip = NULL;
bcd72003 1425
927fc866
PM		 1426 err = pci_enable_device(pci);
1427 if (err < 0)
1da177e4
LT		 1428 return err;
1429
a07187c9
ML		 1430 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1431 if (!hda) {
1432 dev_err(card->dev, "Cannot allocate hda\n");
1da177e4
LT		 1433 pci_disable_device(pci);
1434 return -ENOMEM;
1435 }
1436
a07187c9 1437 chip = &hda->chip;
1da177e4 1438 spin_lock_init(&chip->reg_lock);
62932df8 1439 mutex_init(&chip->open_mutex);
1da177e4
LT		 1440 chip->card = card;
1441 chip->pci = pci;
40830813 1442 chip->ops = hda_ops;
1da177e4 1443 chip->irq = -1;
9477c58e
TI		 1444 chip->driver_caps = driver_caps;
1445 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1446 check_msi(chip);
555e219f 1447 chip->dev_index = dev;
749ee287 1448 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1449 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1450 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1451 INIT_LIST_HEAD(&hda->list);
a82d51ed 1452 init_vga_switcheroo(chip);
9a34af4a 1453 init_completion(&hda->probe_wait);
1da177e4 1454
b6050ef6 1455 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1456
5aba4f8e 1457 check_probe_mask(chip, dev);
3372a153 1458
27346166 1459 chip->single_cmd = single_cmd;
a1585d76 1460 azx_check_snoop_available(chip);
c74db86b 1461
5c0d7bc1
TI		 1462 if (bdl_pos_adj[dev] < 0) {
1463 switch (chip->driver_type) {
0c6341ac 1464 case AZX_DRIVER_ICH:
32679f95 1465 case AZX_DRIVER_PCH:
0c6341ac 1466 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1467 break;
1468 default:
0c6341ac 1469 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1470 break;
1471 }
1472 }
9cdc0115 1473 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1474
a82d51ed
TI		 1475 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1476 if (err < 0) {
4e76a883 1477 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1478 azx_free(chip);
1479 return err;
1480 }
1481
99a2008d 1482 /* continue probing in work context as may trigger request module */
9a34af4a 1483 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1484
a82d51ed 1485 *rchip = chip;
99a2008d 1486
a82d51ed
TI		 1487 return 0;
1488}
1489
48c8b0eb 1490static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1491{
1492 int dev = chip->dev_index;
1493 struct pci_dev *pci = chip->pci;
1494 struct snd_card *card = chip->card;
67908994 1495 int err;
a82d51ed 1496 unsigned short gcap;
413cbf46 1497 unsigned int dma_bits = 64;
a82d51ed 1498
07e4ca50
TI		 1499#if BITS_PER_LONG != 64
1500 /* Fix up base address on ULI M5461 */
1501 if (chip->driver_type == AZX_DRIVER_ULI) {
1502 u16 tmp3;
1503 pci_read_config_word(pci, 0x40, &tmp3);
1504 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1505 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1506 }
1507#endif
1508
927fc866 1509 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1510 if (err < 0)
1da177e4 1511 return err;
a82d51ed 1512 chip->region_requested = 1;
1da177e4 1513
927fc866 1514 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1515 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1516 if (chip->remap_addr == NULL) {
4e76a883 1517 dev_err(card->dev, "ioremap error\n");
a82d51ed 1518 return -ENXIO;
1da177e4
LT		 1519 }
1520
db79afa1
BH		 1521 if (chip->msi) {
1522 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1523 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1524 pci->no_64bit_msi = true;
1525 }
68e7fffc
TI		 1526 if (pci_enable_msi(pci) < 0)
1527 chip->msi = 0;
db79afa1 1528 }
7376d013 1529
a82d51ed
TI		 1530 if (azx_acquire_irq(chip, 0) < 0)
1531 return -EBUSY;
1da177e4
LT		 1532
1533 pci_set_master(pci);
1534 synchronize_irq(chip->irq);
1535
bcd72003 1536 gcap = azx_readw(chip, GCAP);
4e76a883 1537 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1538
413cbf46
TI		 1539 /* AMD devices support 40 or 48bit DMA, take the safe one */
1540 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1541 dma_bits = 40;
1542
dc4c2e6b 1543 /* disable SB600 64bit support for safety */
9477c58e 1544 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1545 struct pci_dev *p_smbus;
413cbf46 1546 dma_bits = 40;
dc4c2e6b
AB		 1547 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1548 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1549 NULL);
1550 if (p_smbus) {
1551 if (p_smbus->revision < 0x30)
fb1d8ac2 1552 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1553 pci_dev_put(p_smbus);
1554 }
1555 }
09240cf4 1556
9477c58e
TI		 1557 /* disable 64bit DMA address on some devices */
1558 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1559 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1560 gcap &= ~AZX_GCAP_64OK;
9477c58e 1561 }
396087ea 1562
2ae66c26 1563 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1564 if (align_buffer_size >= 0)
1565 chip->align_buffer_size = !!align_buffer_size;
1566 else {
1567 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1568 chip->align_buffer_size = 0;
1569 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1570 chip->align_buffer_size = 1;
1571 else
1572 chip->align_buffer_size = 1;
1573 }
2ae66c26 1574
cf7aaca8 1575 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1576 if (!(gcap & AZX_GCAP_64OK))
1577 dma_bits = 32;
1578 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1579 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1580 } else {
e930438c
YH		 1581 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1582 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1583 }
cf7aaca8 1584
8b6ed8e7
TI		 1585 /* read number of streams from GCAP register instead of using
1586 * hardcoded value
1587 */
1588 chip->capture_streams = (gcap >> 8) & 0x0f;
1589 chip->playback_streams = (gcap >> 12) & 0x0f;
1590 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1591 /* gcap didn't give any info, switching to old method */
1592
1593 switch (chip->driver_type) {
1594 case AZX_DRIVER_ULI:
1595 chip->playback_streams = ULI_NUM_PLAYBACK;
1596 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1597 break;
1598 case AZX_DRIVER_ATIHDMI:
1815b34a 1599 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1600 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1601 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1602 break;
c4da29ca 1603 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1604 default:
1605 chip->playback_streams = ICH6_NUM_PLAYBACK;
1606 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1607 break;
1608 }
07e4ca50 1609 }
8b6ed8e7
TI		 1610 chip->capture_index_offset = 0;
1611 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1612 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1613 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1614 GFP_KERNEL);
927fc866 1615 if (!chip->azx_dev) {
4e76a883 1616 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1617 return -ENOMEM;
07e4ca50
TI		 1618 }
1619
67908994 1620 err = azx_alloc_stream_pages(chip);
81740861 1621 if (err < 0)
a82d51ed 1622 return err;
1da177e4
LT		 1623
1624 /* initialize streams */
1625 azx_init_stream(chip);
1626
1627 /* initialize chip */
cb53c626 1628 azx_init_pci(chip);
e4d9e513
ML		 1629
1630 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1631 haswell_set_bclk(chip);
1632
10e77dda 1633 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1634
1635 /* codec detection */
927fc866 1636 if (!chip->codec_mask) {
4e76a883 1637 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1638 return -ENODEV;
1da177e4
LT		 1639 }
1640
07e4ca50 1641 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1642 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1643 sizeof(card->shortname));
1644 snprintf(card->longname, sizeof(card->longname),
1645 "%s at 0x%lx irq %i",
1646 card->shortname, chip->addr, chip->irq);
07e4ca50 1647
1da177e4 1648 return 0;
1da177e4
LT		 1649}
1650
cb53c626
TI		 1651static void power_down_all_codecs(struct azx *chip)
1652{
83012a7c 1653#ifdef CONFIG_PM
cb53c626
TI		 1654 /* The codecs were powered up in snd_hda_codec_new().
1655 * Now all initialization done, so turn them down if possible
1656 */
1657 struct hda_codec *codec;
1658 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1659 snd_hda_power_down(codec);
1660 }
1661#endif
1662}
1663
97c6a3d1 1664#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1665/* callback from request_firmware_nowait() */
1666static void azx_firmware_cb(const struct firmware *fw, void *context)
1667{
1668 struct snd_card *card = context;
1669 struct azx *chip = card->private_data;
1670 struct pci_dev *pci = chip->pci;
1671
1672 if (!fw) {
4e76a883 1673 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1674 goto error;
1675 }
1676
1677 chip->fw = fw;
1678 if (!chip->disabled) {
1679 /* continue probing */
1680 if (azx_probe_continue(chip))
1681 goto error;
1682 }
1683 return; /* OK */
1684
1685 error:
1686 snd_card_free(card);
1687 pci_set_drvdata(pci, NULL);
1688}
97c6a3d1 1689#endif
5cb543db 1690
40830813
DR		 1691/*
1692 * HDA controller ops.
1693 */
1694
1695/* PCI register access. */
db291e36 1696static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1697{
1698 writel(value, addr);
1699}
1700
db291e36 1701static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1702{
1703 return readl(addr);
1704}
1705
db291e36 1706static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1707{
1708 writew(value, addr);
1709}
1710
db291e36 1711static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1712{
1713 return readw(addr);
1714}
1715
db291e36 1716static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1717{
1718 writeb(value, addr);
1719}
1720
db291e36 1721static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1722{
1723 return readb(addr);
1724}
1725
f46ea609
DR		 1726static int disable_msi_reset_irq(struct azx *chip)
1727{
1728 int err;
1729
1730 free_irq(chip->irq, chip);
1731 chip->irq = -1;
1732 pci_disable_msi(chip->pci);
1733 chip->msi = 0;
1734 err = azx_acquire_irq(chip, 1);
1735 if (err < 0)
1736 return err;
1737
1738 return 0;
1739}
1740
b419b35b
DR		 1741/* DMA page allocation helpers. */
1742static int dma_alloc_pages(struct azx *chip,
1743 int type,
1744 size_t size,
1745 struct snd_dma_buffer *buf)
1746{
1747 int err;
1748
1749 err = snd_dma_alloc_pages(type,
1750 chip->card->dev,
1751 size, buf);
1752 if (err < 0)
1753 return err;
1754 mark_pages_wc(chip, buf, true);
1755 return 0;
1756}
1757
1758static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1759{
1760 mark_pages_wc(chip, buf, false);
1761 snd_dma_free_pages(buf);
1762}
1763
1764static int substream_alloc_pages(struct azx *chip,
1765 struct snd_pcm_substream *substream,
1766 size_t size)
1767{
1768 struct azx_dev *azx_dev = get_azx_dev(substream);
1769 int ret;
1770
1771 mark_runtime_wc(chip, azx_dev, substream, false);
1772 azx_dev->bufsize = 0;
1773 azx_dev->period_bytes = 0;
1774 azx_dev->format_val = 0;
1775 ret = snd_pcm_lib_malloc_pages(substream, size);
1776 if (ret < 0)
1777 return ret;
1778 mark_runtime_wc(chip, azx_dev, substream, true);
1779 return 0;
1780}
1781
1782static int substream_free_pages(struct azx *chip,
1783 struct snd_pcm_substream *substream)
1784{
1785 struct azx_dev *azx_dev = get_azx_dev(substream);
1786 mark_runtime_wc(chip, azx_dev, substream, false);
1787 return snd_pcm_lib_free_pages(substream);
1788}
1789
8769b278
DR		 1790static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1791 struct vm_area_struct *area)
1792{
1793#ifdef CONFIG_X86
1794 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1795 struct azx *chip = apcm->chip;
3b70bdba 1796 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1797 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1798#endif
1799}
1800
40830813 1801static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1802 .reg_writel = pci_azx_writel,
1803 .reg_readl = pci_azx_readl,
1804 .reg_writew = pci_azx_writew,
1805 .reg_readw = pci_azx_readw,
1806 .reg_writeb = pci_azx_writeb,
1807 .reg_readb = pci_azx_readb,
f46ea609 1808 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1809 .dma_alloc_pages = dma_alloc_pages,
1810 .dma_free_pages = dma_free_pages,
1811 .substream_alloc_pages = substream_alloc_pages,
1812 .substream_free_pages = substream_free_pages,
8769b278 1813 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1814 .position_check = azx_position_check,
40830813
DR		 1815};
1816
e23e7a14
BP		 1817static int azx_probe(struct pci_dev *pci,
1818 const struct pci_device_id *pci_id)
1da177e4 1819{
5aba4f8e 1820 static int dev;
a98f90fd 1821 struct snd_card *card;
9a34af4a 1822 struct hda_intel *hda;
a98f90fd 1823 struct azx *chip;
aad730d0 1824 bool schedule_probe;
927fc866 1825 int err;
1da177e4 1826
5aba4f8e
TI		 1827 if (dev >= SNDRV_CARDS)
1828 return -ENODEV;
1829 if (!enable[dev]) {
1830 dev++;
1831 return -ENOENT;
1832 }
1833
60c5772b
TI		 1834 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1835 0, &card);
e58de7ba 1836 if (err < 0) {
4e76a883 1837 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1838 return err;
1da177e4
LT		 1839 }
1840
40830813
DR		 1841 err = azx_create(card, pci, dev, pci_id->driver_data,
1842 &pci_hda_ops, &chip);
41dda0fd
WF		 1843 if (err < 0)
1844 goto out_free;
421a1252 1845 card->private_data = chip;
9a34af4a 1846 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1847
1848 pci_set_drvdata(pci, card);
1849
1850 err = register_vga_switcheroo(chip);
1851 if (err < 0) {
4e76a883 1852 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1853 goto out_free;
1854 }
1855
1856 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1857 dev_info(card->dev, "VGA controller is disabled\n");
1858 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1859 chip->disabled = true;
1860 }
1861
aad730d0 1862 schedule_probe = !chip->disabled;
1da177e4 1863
4918cdab
TI		 1864#ifdef CONFIG_SND_HDA_PATCH_LOADER
1865 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1866 dev_info(card->dev, "Applying patch firmware '%s'\n",
1867 patch[dev]);
5cb543db
TI		 1868 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1869 &pci->dev, GFP_KERNEL, card,
1870 azx_firmware_cb);
4918cdab
TI		 1871 if (err < 0)
1872 goto out_free;
aad730d0 1873 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1874 }
1875#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1876
aad730d0
TI		 1877#ifndef CONFIG_SND_HDA_I915
1878 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1879 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1880#endif
99a2008d 1881
aad730d0 1882 if (schedule_probe)
9a34af4a 1883 schedule_work(&hda->probe_work);
a82d51ed 1884
a82d51ed 1885 dev++;
88d071fc 1886 if (chip->disabled)
9a34af4a 1887 complete_all(&hda->probe_wait);
a82d51ed
TI		 1888 return 0;
1889
1890out_free:
1891 snd_card_free(card);
1892 return err;
1893}
1894
e62a42ae
DR		 1895/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1896static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1897 [AZX_DRIVER_NVIDIA] = 8,
1898 [AZX_DRIVER_TERA] = 1,
1899};
1900
48c8b0eb 1901static int azx_probe_continue(struct azx *chip)
a82d51ed 1902{
9a34af4a 1903 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
c67e2228 1904 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1905 int dev = chip->dev_index;
1906 int err;
1907
99a2008d
WX		 1908 /* Request power well for Haswell HDA controller and codec */
1909 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1910#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1911 err = hda_i915_init();
1912 if (err < 0) {
4e76a883
TI		 1913 dev_err(chip->card->dev,
1914 "Error request power-well from i915\n");
99a2008d
WX		 1915 goto out_free;
1916 }
74b0c2d7
TI		 1917 err = hda_display_power(true);
1918 if (err < 0) {
1919 dev_err(chip->card->dev,
1920 "Cannot turn on display power on i915\n");
1921 goto out_free;
1922 }
c841ad2a 1923#endif
99a2008d
WX		 1924 }
1925
5c90680e
TI		 1926 err = azx_first_init(chip);
1927 if (err < 0)
1928 goto out_free;
1929
2dca0bba
JK		 1930#ifdef CONFIG_SND_HDA_INPUT_BEEP
1931 chip->beep_mode = beep_mode[dev];
1932#endif
1933
1da177e4 1934 /* create codec instances */
e62a42ae
DR		 1935 err = azx_codec_create(chip, model[dev],
1936 azx_max_codecs[chip->driver_type],
1937 power_save_addr);
1938
41dda0fd
WF		 1939 if (err < 0)
1940 goto out_free;
4ea6fbc8 1941#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1942 if (chip->fw) {
1943 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1944 chip->fw->data);
4ea6fbc8
TI		 1945 if (err < 0)
1946 goto out_free;
e39ae856 1947#ifndef CONFIG_PM
4918cdab
TI		 1948 release_firmware(chip->fw); /* no longer needed */
1949 chip->fw = NULL;
e39ae856 1950#endif
4ea6fbc8
TI		 1951 }
1952#endif
10e77dda 1953 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1954 err = azx_codec_configure(chip);
1955 if (err < 0)
1956 goto out_free;
1957 }
1da177e4
LT		 1958
1959 /* create PCM streams */
176d5335 1960 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1961 if (err < 0)
1962 goto out_free;
1da177e4
LT		 1963
1964 /* create mixer controls */
d01ce99f 1965 err = azx_mixer_create(chip);
41dda0fd
WF		 1966 if (err < 0)
1967 goto out_free;
1da177e4 1968
a82d51ed 1969 err = snd_card_register(chip->card);
41dda0fd
WF		 1970 if (err < 0)
1971 goto out_free;
1da177e4 1972
cb53c626
TI		 1973 chip->running = 1;
1974 power_down_all_codecs(chip);
0cbf0098 1975 azx_notifier_register(chip);
65fcd41d 1976 azx_add_card_list(chip);
9a34af4a 1977 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo)
c67e2228 1978 pm_runtime_put_noidle(&pci->dev);
1da177e4 1979
41dda0fd 1980out_free:
88d071fc 1981 if (err < 0)
9a34af4a
TI		 1982 hda->init_failed = 1;
1983 complete_all(&hda->probe_wait);
41dda0fd 1984 return err;
1da177e4
LT		 1985}
1986
e23e7a14 1987static void azx_remove(struct pci_dev *pci)
1da177e4 1988{
9121947d 1989 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1990
9121947d
TI		 1991 if (card)
1992 snd_card_free(card);
1da177e4
LT		 1993}
1994
1995/* PCI IDs */
6f51f6cf 1996static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1997 /* CPT */
9477c58e 1998 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1999 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2000 /* PBG */
9477c58e 2001 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2002 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2003 /* Panther Point */
9477c58e 2004 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 2005 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 2006 /* Lynx Point */
2007 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2008 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2009 /* 9 Series */
2010 { PCI_DEVICE(0x8086, 0x8ca0),
2011 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2012 /* Wellsburg */
2013 { PCI_DEVICE(0x8086, 0x8d20),
2014 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2015 { PCI_DEVICE(0x8086, 0x8d21),
2016 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2017 /* Lynx Point-LP */
2018 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2019 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2020 /* Lynx Point-LP */
2021 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2022 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2023 /* Wildcat Point-LP */
2024 { PCI_DEVICE(0x8086, 0x9ca0),
2025 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2026 /* Sunrise Point */
2027 { PCI_DEVICE(0x8086, 0xa170),
2028 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
b4565913
DR		 2029 /* Sunrise Point-LP */
2030 { PCI_DEVICE(0x8086, 0x9d70),
2031 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 2032 /* Haswell */
4a7c516b 2033 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2034 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2035 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2036 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2037 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2038 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2039 /* Broadwell */
2040 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2041 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2042 /* 5 Series/3400 */
2043 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2044 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2045 /* Poulsbo */
9477c58e 2046 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2047 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2048 /* Oaktrail */
09904b95 2049 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2050 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2051 /* BayTrail */
2052 { PCI_DEVICE(0x8086, 0x0f04),
2053 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
f31b2ffc
LY		 2054 /* Braswell */
2055 { PCI_DEVICE(0x8086, 0x2284),
2056 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
645e9035 2057 /* ICH */
8b0bd226 2058 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 2059 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2060 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 2061 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 2062 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2063 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 2064 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 2065 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2066 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 2067 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 2068 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2069 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 2070 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 2071 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2072 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 2073 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 2074 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2075 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 2076 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 2077 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2078 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 2079 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 2080 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2081 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 2082 /* Generic Intel */
2083 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2084 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2085 .class_mask = 0xffffff,
2ae66c26 2086 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 2087 /* ATI SB 450/600/700/800/900 */
2088 { PCI_DEVICE(0x1002, 0x437b),
2089 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2090 { PCI_DEVICE(0x1002, 0x4383),
2091 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2092 /* AMD Hudson */
2093 { PCI_DEVICE(0x1022, 0x780d),
2094 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2095 /* ATI HDMI */
9477c58e
TI		 2096 { PCI_DEVICE(0x1002, 0x793b),
2097 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2098 { PCI_DEVICE(0x1002, 0x7919),
2099 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2100 { PCI_DEVICE(0x1002, 0x960f),
2101 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2102 { PCI_DEVICE(0x1002, 0x970f),
2103 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2104 { PCI_DEVICE(0x1002, 0xaa00),
2105 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2106 { PCI_DEVICE(0x1002, 0xaa08),
2107 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2108 { PCI_DEVICE(0x1002, 0xaa10),
2109 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2110 { PCI_DEVICE(0x1002, 0xaa18),
2111 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2112 { PCI_DEVICE(0x1002, 0xaa20),
2113 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2114 { PCI_DEVICE(0x1002, 0xaa28),
2115 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2116 { PCI_DEVICE(0x1002, 0xaa30),
2117 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2118 { PCI_DEVICE(0x1002, 0xaa38),
2119 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2120 { PCI_DEVICE(0x1002, 0xaa40),
2121 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2122 { PCI_DEVICE(0x1002, 0xaa48),
2123 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2124 { PCI_DEVICE(0x1002, 0xaa50),
2125 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2126 { PCI_DEVICE(0x1002, 0xaa58),
2127 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2128 { PCI_DEVICE(0x1002, 0xaa60),
2129 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2130 { PCI_DEVICE(0x1002, 0xaa68),
2131 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2132 { PCI_DEVICE(0x1002, 0xaa80),
2133 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2134 { PCI_DEVICE(0x1002, 0xaa88),
2135 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2136 { PCI_DEVICE(0x1002, 0xaa90),
2137 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2138 { PCI_DEVICE(0x1002, 0xaa98),
2139 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2140 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2141 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2142 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2143 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2144 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2145 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2146 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2147 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2148 /* VIA VT8251/VT8237A */
9477c58e
TI		 2149 { PCI_DEVICE(0x1106, 0x3288),
2150 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2151 /* VIA GFX VT7122/VX900 */
2152 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2153 /* VIA GFX VT6122/VX11 */
2154 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2155 /* SIS966 */
2156 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2157 /* ULI M5461 */
2158 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2159 /* NVIDIA MCP */
0c2fd1bf
TI		 2160 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2161 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2162 .class_mask = 0xffffff,
9477c58e 2163 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2164 /* Teradici */
9477c58e
TI		 2165 { PCI_DEVICE(0x6549, 0x1200),
2166 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2167 { PCI_DEVICE(0x6549, 0x2200),
2168 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2169 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2170 /* CTHDA chips */
2171 { PCI_DEVICE(0x1102, 0x0010),
2172 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2173 { PCI_DEVICE(0x1102, 0x0012),
2174 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2175#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2176 /* the following entry conflicts with snd-ctxfi driver,
2177 * as ctxfi driver mutates from HD-audio to native mode with
2178 * a special command sequence.
2179 */
4e01f54b
TI		 2180 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2181 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2182 .class_mask = 0xffffff,
9477c58e 2183 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2184 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2185#else
2186 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2187 { PCI_DEVICE(0x1102, 0x0009),
2188 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2189 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2190#endif
c563f473
TI		 2191 /* CM8888 */
2192 { PCI_DEVICE(0x13f6, 0x5011),
2193 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2194 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2195 /* Vortex86MX */
2196 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2197 /* VMware HDAudio */
2198 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2199 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2200 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2201 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2202 .class_mask = 0xffffff,
9477c58e 2203 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2204 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2205 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2206 .class_mask = 0xffffff,
9477c58e 2207 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2208 { 0, }
2209};
2210MODULE_DEVICE_TABLE(pci, azx_ids);
2211
2212/* pci_driver definition */
e9f66d9b 2213static struct pci_driver azx_driver = {
3733e424 2214 .name = KBUILD_MODNAME,
1da177e4
LT		 2215 .id_table = azx_ids,
2216 .probe = azx_probe,
e23e7a14 2217 .remove = azx_remove,
68cb2b55
TI		 2218 .driver = {
2219 .pm = AZX_PM_OPS,
2220 },
1da177e4
LT		 2221};
2222
e9f66d9b 2223module_pci_driver(azx_driver);
Linux 6.x block layer and io_uring tree(s)