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ALSA: sound/pci/hda/hda_codec.c: various coding style fixes
[linux-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
71623855 63static int enable_msi = -1;
4ea6fbc8
TI		 64#ifdef CONFIG_SND_HDA_PATCH_LOADER
65static char *patch[SNDRV_CARDS];
66#endif
2dca0bba
JK		 67#ifdef CONFIG_SND_HDA_INPUT_BEEP
68static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70#endif
1da177e4 71
5aba4f8e 72module_param_array(index, int, NULL, 0444);
1da177e4 73MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 74module_param_array(id, charp, NULL, 0444);
1da177e4 75MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 76module_param_array(enable, bool, NULL, 0444);
77MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78module_param_array(model, charp, NULL, 0444);
1da177e4 79MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 80module_param_array(position_fix, int, NULL, 0444);
d01ce99f 81MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 82 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 83module_param_array(bdl_pos_adj, int, NULL, 0644);
84MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 85module_param_array(probe_mask, int, NULL, 0444);
606ad75f 86MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
d4d9cd03
TI		 87module_param_array(probe_only, bool, NULL, 0444);
88MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 89module_param(single_cmd, bool, 0444);
d01ce99f
TI		 90MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
5aba4f8e 92module_param(enable_msi, int, 0444);
134a11f0 93MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 94#ifdef CONFIG_SND_HDA_PATCH_LOADER
95module_param_array(patch, charp, NULL, 0444);
96MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97#endif
2dca0bba
JK		 98#ifdef CONFIG_SND_HDA_INPUT_BEEP
99module_param_array(beep_mode, int, NULL, 0444);
100MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102#endif
606ad75f 103
dee1b66c 104#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 105static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106module_param(power_save, int, 0644);
107MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
1da177e4 109
dee1b66c
TI		 110/* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114static int power_save_controller = 1;
115module_param(power_save_controller, bool, 0644);
116MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117#endif
118
1da177e4
LT		 119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
2f1b3818 122 "{Intel, ICH7},"
f5d40b30 123 "{Intel, ESB2},"
d2981393 124 "{Intel, ICH8},"
f9cc8a8b 125 "{Intel, ICH9},"
c34f5a04 126 "{Intel, ICH10},"
b29c2360 127 "{Intel, PCH},"
d2f2fcd2 128 "{Intel, CPT},"
4979bca9 129 "{Intel, SCH},"
fc20a562 130 "{ATI, SB450},"
89be83f8 131 "{ATI, SB600},"
778b6e1b 132 "{ATI, RS600},"
5b15c95f 133 "{ATI, RS690},"
e6db1119
WL		 134 "{ATI, RS780},"
135 "{ATI, R600},"
2797f724
HRK		 136 "{ATI, RV630},"
137 "{ATI, RV610},"
27da1834
WL		 138 "{ATI, RV670},"
139 "{ATI, RV635},"
140 "{ATI, RV620},"
141 "{ATI, RV770},"
fc20a562 142 "{VIA, VT8251},"
47672310 143 "{VIA, VT8237A},"
07e4ca50
TI		 144 "{SiS, SIS966},"
145 "{ULI, M5461}}");
1da177e4
LT		 146MODULE_DESCRIPTION("Intel HDA driver");
147
4abc1cc2
TI		 148#ifdef CONFIG_SND_VERBOSE_PRINTK
149#define SFX /* nop */
150#else
1da177e4 151#define SFX "hda-intel: "
4abc1cc2 152#endif
cb53c626 153
1da177e4
LT		 154/*
155 * registers
156 */
157#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 158#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
159#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
160#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
161#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
162#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 163#define ICH6_REG_VMIN 0x02
164#define ICH6_REG_VMAJ 0x03
165#define ICH6_REG_OUTPAY 0x04
166#define ICH6_REG_INPAY 0x06
167#define ICH6_REG_GCTL 0x08
8a933ece 168#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 169#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
170#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 171#define ICH6_REG_WAKEEN 0x0c
172#define ICH6_REG_STATESTS 0x0e
173#define ICH6_REG_GSTS 0x10
b21fadb9 174#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 175#define ICH6_REG_INTCTL 0x20
176#define ICH6_REG_INTSTS 0x24
177#define ICH6_REG_WALCLK 0x30
178#define ICH6_REG_SYNC 0x34
179#define ICH6_REG_CORBLBASE 0x40
180#define ICH6_REG_CORBUBASE 0x44
181#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 182#define ICH6_REG_CORBRP 0x4a
183#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 184#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 185#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
186#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 187#define ICH6_REG_CORBSTS 0x4d
b21fadb9 188#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 189#define ICH6_REG_CORBSIZE 0x4e
190
191#define ICH6_REG_RIRBLBASE 0x50
192#define ICH6_REG_RIRBUBASE 0x54
193#define ICH6_REG_RIRBWP 0x58
b21fadb9 194#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 195#define ICH6_REG_RINTCNT 0x5a
196#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 197#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
198#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
199#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 200#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 201#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
202#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 203#define ICH6_REG_RIRBSIZE 0x5e
204
205#define ICH6_REG_IC 0x60
206#define ICH6_REG_IR 0x64
207#define ICH6_REG_IRS 0x68
208#define ICH6_IRS_VALID (1<<1)
209#define ICH6_IRS_BUSY (1<<0)
210
211#define ICH6_REG_DPLBASE 0x70
212#define ICH6_REG_DPUBASE 0x74
213#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
214
215/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
216enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
217
218/* stream register offsets from stream base */
219#define ICH6_REG_SD_CTL 0x00
220#define ICH6_REG_SD_STS 0x03
221#define ICH6_REG_SD_LPIB 0x04
222#define ICH6_REG_SD_CBL 0x08
223#define ICH6_REG_SD_LVI 0x0c
224#define ICH6_REG_SD_FIFOW 0x0e
225#define ICH6_REG_SD_FIFOSIZE 0x10
226#define ICH6_REG_SD_FORMAT 0x12
227#define ICH6_REG_SD_BDLPL 0x18
228#define ICH6_REG_SD_BDLPU 0x1c
229
230/* PCI space */
231#define ICH6_PCIREG_TCSEL 0x44
232
233/*
234 * other constants
235 */
236
237/* max number of SDs */
07e4ca50 238/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 239#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 240#define ICH6_NUM_PLAYBACK 4
241
242/* ULI has 6 playback and 5 capture */
07e4ca50 243#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 244#define ULI_NUM_PLAYBACK 6
245
778b6e1b 246/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 247#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 248#define ATIHDMI_NUM_PLAYBACK 1
249
f269002e
KY		 250/* TERA has 4 playback and 3 capture */
251#define TERA_NUM_CAPTURE 3
252#define TERA_NUM_PLAYBACK 4
253
07e4ca50
TI		 254/* this number is statically defined for simplicity */
255#define MAX_AZX_DEV 16
256
1da177e4 257/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 258#define BDL_SIZE 4096
259#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
260#define AZX_MAX_FRAG 32
1da177e4
LT		 261/* max buffer size - no h/w limit, you can increase as you like */
262#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 263
264/* RIRB int mask: overrun[2], response[0] */
265#define RIRB_INT_RESPONSE 0x01
266#define RIRB_INT_OVERRUN 0x04
267#define RIRB_INT_MASK 0x05
268
2f5983f2
TI		 269/* STATESTS int mask: S3,SD2,SD1,SD0 */
270#define AZX_MAX_CODECS 4
deadff16 271#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 272
273/* SD_CTL bits */
274#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
275#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 276#define SD_CTL_STRIPE (3 << 16) /* stripe control */
277#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
278#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 279#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
280#define SD_CTL_STREAM_TAG_SHIFT 20
281
282/* SD_CTL and SD_STS */
283#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
284#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
285#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 286#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
287 SD_INT_COMPLETE)
1da177e4
LT		 288
289/* SD_STS */
290#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
291
292/* INTCTL and INTSTS */
d01ce99f
TI		 293#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
294#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
295#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 296
1da177e4
LT		 297/* below are so far hardcoded - should read registers in future */
298#define ICH6_MAX_CORB_ENTRIES 256
299#define ICH6_MAX_RIRB_ENTRIES 256
300
c74db86b
TI		 301/* position fix mode */
302enum {
0be3b5d3 303 POS_FIX_AUTO,
d2e1c973 304 POS_FIX_LPIB,
0be3b5d3 305 POS_FIX_POSBUF,
c74db86b 306};
1da177e4 307
f5d40b30 308/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 309#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
310#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
311
da3fca21
V		 312/* Defines for Nvidia HDA support */
313#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
314#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 315#define NVIDIA_HDA_ISTRM_COH 0x4d
316#define NVIDIA_HDA_OSTRM_COH 0x4c
317#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 318
90a5ad52
TI		 319/* Defines for Intel SCH HDA snoop control */
320#define INTEL_SCH_HDA_DEVC 0x78
321#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
322
0e153474
JC		 323/* Define IN stream 0 FIFO size offset in VIA controller */
324#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
325/* Define VIA HD Audio Device ID*/
326#define VIA_HDAC_DEVICE_ID 0x3288
327
c4da29ca
YL		 328/* HD Audio class code */
329#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 330
1da177e4
LT		 331/*
332 */
333
a98f90fd 334struct azx_dev {
4ce107b9 335 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 336 u32 *posbuf; /* position buffer pointer */
1da177e4 337
d01ce99f 338 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 339 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 340 unsigned int frags; /* number for period in the play buffer */
341 unsigned int fifo_size; /* FIFO size */
fa00e046
JK		 342 unsigned long start_jiffies; /* start + minimum jiffies */
343 unsigned long min_jiffies; /* minimum jiffies before position is valid */
1da177e4 344
d01ce99f 345 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 346
d01ce99f 347 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 348
349 /* pcm support */
d01ce99f
TI		 350 struct snd_pcm_substream *substream; /* assigned substream,
351 * set in PCM open
352 */
353 unsigned int format_val; /* format value to be set in the
354 * controller and the codec
355 */
1da177e4
LT		 356 unsigned char stream_tag; /* assigned stream */
357 unsigned char index; /* stream index */
ef18bede 358 int device; /* last device number assigned to */
1da177e4 359
927fc866
PM		 360 unsigned int opened :1;
361 unsigned int running :1;
675f25d4 362 unsigned int irq_pending :1;
d523b0c8 363 unsigned int start_flag: 1; /* stream full start flag */
0e153474
JC		 364 /*
365 * For VIA:
366 * A flag to ensure DMA position is 0
367 * when link position is not greater than FIFO size
368 */
369 unsigned int insufficient :1;
1da177e4
LT		 370};
371
372/* CORB/RIRB */
a98f90fd 373struct azx_rb {
1da177e4
LT		 374 u32 *buf; /* CORB/RIRB buffer
375 * Each CORB entry is 4byte, RIRB is 8byte
376 */
377 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
378 /* for RIRB */
379 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 380 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
381 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 382};
383
a98f90fd
TI		 384struct azx {
385 struct snd_card *card;
1da177e4 386 struct pci_dev *pci;
555e219f 387 int dev_index;
1da177e4 388
07e4ca50
TI		 389 /* chip type specific */
390 int driver_type;
391 int playback_streams;
392 int playback_index_offset;
393 int capture_streams;
394 int capture_index_offset;
395 int num_streams;
396
1da177e4
LT		 397 /* pci resources */
398 unsigned long addr;
399 void __iomem *remap_addr;
400 int irq;
401
402 /* locks */
403 spinlock_t reg_lock;
62932df8 404 struct mutex open_mutex;
1da177e4 405
07e4ca50 406 /* streams (x num_streams) */
a98f90fd 407 struct azx_dev *azx_dev;
1da177e4
LT		 408
409 /* PCM */
c8936222 410 struct snd_pcm *pcm[HDA_MAX_PCMS];
1da177e4
LT		 411
412 /* HD codec */
413 unsigned short codec_mask;
f1eaaeec 414 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 415 struct hda_bus *bus;
2dca0bba 416 unsigned int beep_mode;
1da177e4
LT		 417
418 /* CORB/RIRB */
a98f90fd
TI		 419 struct azx_rb corb;
420 struct azx_rb rirb;
1da177e4 421
4ce107b9 422 /* CORB/RIRB and position buffers */
1da177e4
LT		 423 struct snd_dma_buffer rb;
424 struct snd_dma_buffer posbuf;
c74db86b
TI		 425
426 /* flags */
427 int position_fix;
1eb6dc7d 428 int poll_count;
cb53c626 429 unsigned int running :1;
927fc866
PM		 430 unsigned int initialized :1;
431 unsigned int single_cmd :1;
432 unsigned int polling_mode :1;
68e7fffc 433 unsigned int msi :1;
a6a950a8 434 unsigned int irq_pending_warned :1;
0e153474 435 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
6ce4a3bc 436 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 437
438 /* for debugging */
feb27340 439 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 440
441 /* for pending irqs */
442 struct work_struct irq_pending_work;
0cbf0098
TI		 443
444 /* reboot notifier (for mysterious hangup problem at power-down) */
445 struct notifier_block reboot_notifier;
1da177e4
LT		 446};
447
07e4ca50
TI		 448/* driver types */
449enum {
450 AZX_DRIVER_ICH,
32679f95 451 AZX_DRIVER_PCH,
4979bca9 452 AZX_DRIVER_SCH,
07e4ca50 453 AZX_DRIVER_ATI,
778b6e1b 454 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 455 AZX_DRIVER_VIA,
456 AZX_DRIVER_SIS,
457 AZX_DRIVER_ULI,
da3fca21 458 AZX_DRIVER_NVIDIA,
f269002e 459 AZX_DRIVER_TERA,
c4da29ca 460 AZX_DRIVER_GENERIC,
2f5983f2 461 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 462};
463
464static char *driver_short_names[] __devinitdata = {
465 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 466 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 467 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 468 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 469 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 470 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
471 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 472 [AZX_DRIVER_ULI] = "HDA ULI M5461",
473 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 474 [AZX_DRIVER_TERA] = "HDA Teradici",
c4da29ca 475 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 476};
477
1da177e4
LT		 478/*
479 * macros for easy use
480 */
481#define azx_writel(chip,reg,value) \
482 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
483#define azx_readl(chip,reg) \
484 readl((chip)->remap_addr + ICH6_REG_##reg)
485#define azx_writew(chip,reg,value) \
486 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
487#define azx_readw(chip,reg) \
488 readw((chip)->remap_addr + ICH6_REG_##reg)
489#define azx_writeb(chip,reg,value) \
490 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
491#define azx_readb(chip,reg) \
492 readb((chip)->remap_addr + ICH6_REG_##reg)
493
494#define azx_sd_writel(dev,reg,value) \
495 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
496#define azx_sd_readl(dev,reg) \
497 readl((dev)->sd_addr + ICH6_REG_##reg)
498#define azx_sd_writew(dev,reg,value) \
499 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
500#define azx_sd_readw(dev,reg) \
501 readw((dev)->sd_addr + ICH6_REG_##reg)
502#define azx_sd_writeb(dev,reg,value) \
503 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
504#define azx_sd_readb(dev,reg) \
505 readb((dev)->sd_addr + ICH6_REG_##reg)
506
507/* for pcm support */
a98f90fd 508#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 509
68e7fffc 510static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 511static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 512/*
513 * Interface for HD codec
514 */
515
1da177e4
LT		 516/*
517 * CORB / RIRB interface
518 */
a98f90fd 519static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 520{
521 int err;
522
523 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 524 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
525 snd_dma_pci_data(chip->pci),
1da177e4
LT		 526 PAGE_SIZE, &chip->rb);
527 if (err < 0) {
528 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
529 return err;
530 }
531 return 0;
532}
533
a98f90fd 534static void azx_init_cmd_io(struct azx *chip)
1da177e4 535{
cdb1fbf2 536 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 537 /* CORB set up */
538 chip->corb.addr = chip->rb.addr;
539 chip->corb.buf = (u32 *)chip->rb.area;
540 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 541 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 542
07e4ca50
TI		 543 /* set the corb size to 256 entries (ULI requires explicitly) */
544 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 545 /* set the corb write pointer to 0 */
546 azx_writew(chip, CORBWP, 0);
547 /* reset the corb hw read pointer */
b21fadb9 548 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 549 /* enable corb dma */
b21fadb9 550 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 551
552 /* RIRB set up */
553 chip->rirb.addr = chip->rb.addr + 2048;
554 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 555 chip->rirb.wp = chip->rirb.rp = 0;
556 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 557 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 558 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 559
07e4ca50
TI		 560 /* set the rirb size to 256 entries (ULI requires explicitly) */
561 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 562 /* reset the rirb hw write pointer */
b21fadb9 563 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4
LT		 564 /* set N=1, get RIRB response interrupt for new entry */
565 azx_writew(chip, RINTCNT, 1);
566 /* enable rirb dma and response irq */
1da177e4 567 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 568 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 569}
570
a98f90fd 571static void azx_free_cmd_io(struct azx *chip)
1da177e4 572{
cdb1fbf2 573 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 574 /* disable ringbuffer DMAs */
575 azx_writeb(chip, RIRBCTL, 0);
576 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 577 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 578}
579
deadff16
WF		 580static unsigned int azx_command_addr(u32 cmd)
581{
582 unsigned int addr = cmd >> 28;
583
584 if (addr >= AZX_MAX_CODECS) {
585 snd_BUG();
586 addr = 0;
587 }
588
589 return addr;
590}
591
592static unsigned int azx_response_addr(u32 res)
593{
594 unsigned int addr = res & 0xf;
595
596 if (addr >= AZX_MAX_CODECS) {
597 snd_BUG();
598 addr = 0;
599 }
600
601 return addr;
1da177e4
LT		 602}
603
604/* send a command */
33fa35ed 605static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 606{
33fa35ed 607 struct azx *chip = bus->private_data;
deadff16 608 unsigned int addr = azx_command_addr(val);
1da177e4 609 unsigned int wp;
1da177e4 610
c32649fe
WF		 611 spin_lock_irq(&chip->reg_lock);
612
1da177e4
LT		 613 /* add command to corb */
614 wp = azx_readb(chip, CORBWP);
615 wp++;
616 wp %= ICH6_MAX_CORB_ENTRIES;
617
deadff16 618 chip->rirb.cmds[addr]++;
1da177e4
LT		 619 chip->corb.buf[wp] = cpu_to_le32(val);
620 azx_writel(chip, CORBWP, wp);
c32649fe 621
1da177e4
LT		 622 spin_unlock_irq(&chip->reg_lock);
623
624 return 0;
625}
626
627#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
628
629/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 630static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 631{
632 unsigned int rp, wp;
deadff16 633 unsigned int addr;
1da177e4
LT		 634 u32 res, res_ex;
635
636 wp = azx_readb(chip, RIRBWP);
637 if (wp == chip->rirb.wp)
638 return;
639 chip->rirb.wp = wp;
deadff16 640
1da177e4
LT		 641 while (chip->rirb.rp != wp) {
642 chip->rirb.rp++;
643 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
644
645 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
646 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
647 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 648 addr = azx_response_addr(res_ex);
1da177e4
LT		 649 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
650 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 651 else if (chip->rirb.cmds[addr]) {
652 chip->rirb.res[addr] = res;
2add9b92 653 smp_wmb();
deadff16 654 chip->rirb.cmds[addr]--;
e310bb06
WF		 655 } else
656 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
657 "last cmd=%#08x\n",
658 res, res_ex,
659 chip->last_cmd[addr]);
1da177e4
LT		 660 }
661}
662
663/* receive a response */
deadff16
WF		 664static unsigned int azx_rirb_get_response(struct hda_bus *bus,
665 unsigned int addr)
1da177e4 666{
33fa35ed 667 struct azx *chip = bus->private_data;
5c79b1f8 668 unsigned long timeout;
1eb6dc7d 669 int do_poll = 0;
1da177e4 670
5c79b1f8
TI		 671 again:
672 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 673 for (;;) {
1eb6dc7d 674 if (chip->polling_mode || do_poll) {
e96224ae
TI		 675 spin_lock_irq(&chip->reg_lock);
676 azx_update_rirb(chip);
677 spin_unlock_irq(&chip->reg_lock);
678 }
deadff16 679 if (!chip->rirb.cmds[addr]) {
2add9b92 680 smp_rmb();
b613291f 681 bus->rirb_error = 0;
1eb6dc7d
ML		 682
683 if (!do_poll)
684 chip->poll_count = 0;
deadff16 685 return chip->rirb.res[addr]; /* the last value */
2add9b92 686 }
28a0d9df
TI		 687 if (time_after(jiffies, timeout))
688 break;
33fa35ed 689 if (bus->needs_damn_long_delay)
52987656
TI		 690 msleep(2); /* temporary workaround */
691 else {
692 udelay(10);
693 cond_resched();
694 }
28a0d9df 695 }
5c79b1f8 696
1eb6dc7d
ML		 697 if (!chip->polling_mode && chip->poll_count < 2) {
698 snd_printdd(SFX "azx_get_response timeout, "
699 "polling the codec once: last cmd=0x%08x\n",
700 chip->last_cmd[addr]);
701 do_poll = 1;
702 chip->poll_count++;
703 goto again;
704 }
705
706
23c4a881
TI		 707 if (!chip->polling_mode) {
708 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
709 "switching to polling mode: last cmd=0x%08x\n",
710 chip->last_cmd[addr]);
711 chip->polling_mode = 1;
712 goto again;
713 }
714
68e7fffc 715 if (chip->msi) {
4abc1cc2 716 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 717 "disabling MSI: last cmd=0x%08x\n",
718 chip->last_cmd[addr]);
68e7fffc
TI		 719 free_irq(chip->irq, chip);
720 chip->irq = -1;
721 pci_disable_msi(chip->pci);
722 chip->msi = 0;
b613291f
TI		 723 if (azx_acquire_irq(chip, 1) < 0) {
724 bus->rirb_error = 1;
68e7fffc 725 return -1;
b613291f 726 }
68e7fffc
TI		 727 goto again;
728 }
729
6ce4a3bc
TI		 730 if (chip->probing) {
731 /* If this critical timeout happens during the codec probing
732 * phase, this is likely an access to a non-existing codec
733 * slot. Better to return an error and reset the system.
734 */
735 return -1;
736 }
737
8dd78330
TI		 738 /* a fatal communication error; need either to reset or to fallback
739 * to the single_cmd mode
740 */
b613291f 741 bus->rirb_error = 1;
b20f3b83 742 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 743 bus->response_reset = 1;
744 return -1; /* give a chance to retry */
745 }
746
747 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
748 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 749 chip->last_cmd[addr]);
8dd78330
TI		 750 chip->single_cmd = 1;
751 bus->response_reset = 0;
1a696978 752 /* release CORB/RIRB */
4fcd3920 753 azx_free_cmd_io(chip);
1a696978
TI		 754 /* disable unsolicited responses */
755 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 756 return -1;
1da177e4
LT		 757}
758
1da177e4
LT		 759/*
760 * Use the single immediate command instead of CORB/RIRB for simplicity
761 *
762 * Note: according to Intel, this is not preferred use. The command was
763 * intended for the BIOS only, and may get confused with unsolicited
764 * responses. So, we shouldn't use it for normal operation from the
765 * driver.
766 * I left the codes, however, for debugging/testing purposes.
767 */
768
b05a7d4f 769/* receive a response */
deadff16 770static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 771{
772 int timeout = 50;
773
774 while (timeout--) {
775 /* check IRV busy bit */
776 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
777 /* reuse rirb.res as the response return value */
deadff16 778 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 779 return 0;
780 }
781 udelay(1);
782 }
783 if (printk_ratelimit())
784 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
785 azx_readw(chip, IRS));
deadff16 786 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 787 return -EIO;
788}
789
1da177e4 790/* send a command */
33fa35ed 791static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 792{
33fa35ed 793 struct azx *chip = bus->private_data;
deadff16 794 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 795 int timeout = 50;
796
8dd78330 797 bus->rirb_error = 0;
1da177e4
LT		 798 while (timeout--) {
799 /* check ICB busy bit */
d01ce99f 800 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 801 /* Clear IRV valid bit */
d01ce99f
TI		 802 azx_writew(chip, IRS, azx_readw(chip, IRS) |
803 ICH6_IRS_VALID);
1da177e4 804 azx_writel(chip, IC, val);
d01ce99f
TI		 805 azx_writew(chip, IRS, azx_readw(chip, IRS) |
806 ICH6_IRS_BUSY);
deadff16 807 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 808 }
809 udelay(1);
810 }
1cfd52bc
MB		 811 if (printk_ratelimit())
812 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
813 azx_readw(chip, IRS), val);
1da177e4
LT		 814 return -EIO;
815}
816
817/* receive a response */
deadff16
WF		 818static unsigned int azx_single_get_response(struct hda_bus *bus,
819 unsigned int addr)
1da177e4 820{
33fa35ed 821 struct azx *chip = bus->private_data;
deadff16 822 return chip->rirb.res[addr];
1da177e4
LT		 823}
824
111d3af5
TI		 825/*
826 * The below are the main callbacks from hda_codec.
827 *
828 * They are just the skeleton to call sub-callbacks according to the
829 * current setting of chip->single_cmd.
830 */
831
832/* send a command */
33fa35ed 833static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 834{
33fa35ed 835 struct azx *chip = bus->private_data;
43bbb6cc 836
feb27340 837 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 838 if (chip->single_cmd)
33fa35ed 839 return azx_single_send_cmd(bus, val);
111d3af5 840 else
33fa35ed 841 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 842}
843
844/* get a response */
deadff16
WF		 845static unsigned int azx_get_response(struct hda_bus *bus,
846 unsigned int addr)
111d3af5 847{
33fa35ed 848 struct azx *chip = bus->private_data;
111d3af5 849 if (chip->single_cmd)
deadff16 850 return azx_single_get_response(bus, addr);
111d3af5 851 else
deadff16 852 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 853}
854
cb53c626 855#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 856static void azx_power_notify(struct hda_bus *bus);
cb53c626 857#endif
111d3af5 858
1da177e4 859/* reset codec link */
a98f90fd 860static int azx_reset(struct azx *chip)
1da177e4
LT		 861{
862 int count;
863
e8a7f136
DT		 864 /* clear STATESTS */
865 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
866
1da177e4
LT		 867 /* reset controller */
868 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
869
870 count = 50;
871 while (azx_readb(chip, GCTL) && --count)
872 msleep(1);
873
874 /* delay for >= 100us for codec PLL to settle per spec
875 * Rev 0.9 section 5.5.1
876 */
877 msleep(1);
878
879 /* Bring controller out of reset */
880 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
881
882 count = 50;
927fc866 883 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 884 msleep(1);
885
927fc866 886 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 887 msleep(1);
888
889 /* check to see if controller is ready */
927fc866 890 if (!azx_readb(chip, GCTL)) {
4abc1cc2 891 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 892 return -EBUSY;
893 }
894
41e2fce4 895 /* Accept unsolicited responses */
1a696978
TI		 896 if (!chip->single_cmd)
897 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
898 ICH6_GCTL_UNSOL);
41e2fce4 899
1da177e4 900 /* detect codecs */
927fc866 901 if (!chip->codec_mask) {
1da177e4 902 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 903 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 904 }
905
906 return 0;
907}
908
909
910/*
911 * Lowlevel interface
912 */
913
914/* enable interrupts */
a98f90fd 915static void azx_int_enable(struct azx *chip)
1da177e4
LT		 916{
917 /* enable controller CIE and GIE */
918 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
919 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
920}
921
922/* disable interrupts */
a98f90fd 923static void azx_int_disable(struct azx *chip)
1da177e4
LT		 924{
925 int i;
926
927 /* disable interrupts in stream descriptor */
07e4ca50 928 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 929 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 930 azx_sd_writeb(azx_dev, SD_CTL,
931 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
932 }
933
934 /* disable SIE for all streams */
935 azx_writeb(chip, INTCTL, 0);
936
937 /* disable controller CIE and GIE */
938 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
939 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
940}
941
942/* clear interrupts */
a98f90fd 943static void azx_int_clear(struct azx *chip)
1da177e4
LT		 944{
945 int i;
946
947 /* clear stream status */
07e4ca50 948 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 949 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 950 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
951 }
952
953 /* clear STATESTS */
954 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
955
956 /* clear rirb status */
957 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
958
959 /* clear int status */
960 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
961}
962
963/* start a stream */
a98f90fd 964static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 965{
0e153474
JC		 966 /*
967 * Before stream start, initialize parameter
968 */
969 azx_dev->insufficient = 1;
970
1da177e4 971 /* enable SIE */
ccc5df05
WN		 972 azx_writel(chip, INTCTL,
973 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 974 /* set DMA start and interrupt mask */
975 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
976 SD_CTL_DMA_START | SD_INT_MASK);
977}
978
1dddab40
TI		 979/* stop DMA */
980static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 981{
1da177e4
LT		 982 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
983 ~(SD_CTL_DMA_START | SD_INT_MASK));
984 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 985}
986
987/* stop a stream */
988static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
989{
990 azx_stream_clear(chip, azx_dev);
1da177e4 991 /* disable SIE */
ccc5df05
WN		 992 azx_writel(chip, INTCTL,
993 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 994}
995
996
997/*
cb53c626 998 * reset and start the controller registers
1da177e4 999 */
a98f90fd 1000static void azx_init_chip(struct azx *chip)
1da177e4 1001{
cb53c626
TI		 1002 if (chip->initialized)
1003 return;
1da177e4
LT		 1004
1005 /* reset controller */
1006 azx_reset(chip);
1007
1008 /* initialize interrupts */
1009 azx_int_clear(chip);
1010 azx_int_enable(chip);
1011
1012 /* initialize the codec command I/O */
1a696978
TI		 1013 if (!chip->single_cmd)
1014 azx_init_cmd_io(chip);
1da177e4 1015
0be3b5d3
TI		 1016 /* program the position buffer */
1017 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1018 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1019
cb53c626
TI		 1020 chip->initialized = 1;
1021}
1022
1023/*
1024 * initialize the PCI registers
1025 */
1026/* update bits in a PCI register byte */
1027static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1028 unsigned char mask, unsigned char val)
1029{
1030 unsigned char data;
1031
1032 pci_read_config_byte(pci, reg, &data);
1033 data &= ~mask;
1034 data |= (val & mask);
1035 pci_write_config_byte(pci, reg, data);
1036}
1037
1038static void azx_init_pci(struct azx *chip)
1039{
90a5ad52
TI		 1040 unsigned short snoop;
1041
cb53c626
TI		 1042 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1043 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1044 * Ensuring these bits are 0 clears playback static on some HD Audio
1045 * codecs
1046 */
1047 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1048
da3fca21
V		 1049 switch (chip->driver_type) {
1050 case AZX_DRIVER_ATI:
1051 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 1052 update_pci_byte(chip->pci,
1053 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1054 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 1055 break;
1056 case AZX_DRIVER_NVIDIA:
1057 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 1058 update_pci_byte(chip->pci,
1059 NVIDIA_HDA_TRANSREG_ADDR,
1060 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1061 update_pci_byte(chip->pci,
1062 NVIDIA_HDA_ISTRM_COH,
1063 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1064 update_pci_byte(chip->pci,
1065 NVIDIA_HDA_OSTRM_COH,
1066 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 1067 break;
90a5ad52 1068 case AZX_DRIVER_SCH:
32679f95 1069 case AZX_DRIVER_PCH:
90a5ad52
TI		 1070 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1071 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
4abc1cc2 1072 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
90a5ad52
TI		 1073 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1074 pci_read_config_word(chip->pci,
1075 INTEL_SCH_HDA_DEVC, &snoop);
4abc1cc2
TI		 1076 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1077 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
90a5ad52
TI		 1078 ? "Failed" : "OK");
1079 }
1080 break;
1081
da3fca21 1082 }
1da177e4
LT		 1083}
1084
1085
9ad593f6
TI		 1086static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1087
1da177e4
LT		 1088/*
1089 * interrupt handler
1090 */
7d12e780 1091static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1092{
a98f90fd
TI		 1093 struct azx *chip = dev_id;
1094 struct azx_dev *azx_dev;
1da177e4 1095 u32 status;
fa00e046 1096 int i, ok;
1da177e4
LT		 1097
1098 spin_lock(&chip->reg_lock);
1099
1100 status = azx_readl(chip, INTSTS);
1101 if (status == 0) {
1102 spin_unlock(&chip->reg_lock);
1103 return IRQ_NONE;
1104 }
1105
07e4ca50 1106 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1107 azx_dev = &chip->azx_dev[i];
1108 if (status & azx_dev->sd_int_sta_mask) {
1109 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 1110 if (!azx_dev->substream || !azx_dev->running)
1111 continue;
1112 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1113 ok = azx_position_ok(chip, azx_dev);
1114 if (ok == 1) {
9ad593f6 1115 azx_dev->irq_pending = 0;
1da177e4
LT		 1116 spin_unlock(&chip->reg_lock);
1117 snd_pcm_period_elapsed(azx_dev->substream);
1118 spin_lock(&chip->reg_lock);
fa00e046 1119 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1120 /* bogus IRQ, process it later */
1121 azx_dev->irq_pending = 1;
6acaed38
TI		 1122 queue_work(chip->bus->workq,
1123 &chip->irq_pending_work);
1da177e4
LT		 1124 }
1125 }
1126 }
1127
1128 /* clear rirb int */
1129 status = azx_readb(chip, RIRBSTS);
1130 if (status & RIRB_INT_MASK) {
81740861 1131 if (status & RIRB_INT_RESPONSE)
1da177e4
LT		 1132 azx_update_rirb(chip);
1133 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1134 }
1135
1136#if 0
1137 /* clear state status int */
1138 if (azx_readb(chip, STATESTS) & 0x04)
1139 azx_writeb(chip, STATESTS, 0x04);
1140#endif
1141 spin_unlock(&chip->reg_lock);
1142
1143 return IRQ_HANDLED;
1144}
1145
1146
675f25d4
TI		 1147/*
1148 * set up a BDL entry
1149 */
1150static int setup_bdle(struct snd_pcm_substream *substream,
1151 struct azx_dev *azx_dev, u32 **bdlp,
1152 int ofs, int size, int with_ioc)
1153{
675f25d4
TI		 1154 u32 *bdl = *bdlp;
1155
1156 while (size > 0) {
1157 dma_addr_t addr;
1158 int chunk;
1159
1160 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1161 return -EINVAL;
1162
77a23f26 1163 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1164 /* program the address field of the BDL entry */
1165 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1166 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1167 /* program the size field of the BDL entry */
fc4abee8 1168 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1169 bdl[2] = cpu_to_le32(chunk);
1170 /* program the IOC to enable interrupt
1171 * only when the whole fragment is processed
1172 */
1173 size -= chunk;
1174 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1175 bdl += 4;
1176 azx_dev->frags++;
1177 ofs += chunk;
1178 }
1179 *bdlp = bdl;
1180 return ofs;
1181}
1182
1da177e4
LT		 1183/*
1184 * set up BDL entries
1185 */
555e219f
TI		 1186static int azx_setup_periods(struct azx *chip,
1187 struct snd_pcm_substream *substream,
4ce107b9 1188 struct azx_dev *azx_dev)
1da177e4 1189{
4ce107b9
TI		 1190 u32 *bdl;
1191 int i, ofs, periods, period_bytes;
555e219f 1192 int pos_adj;
1da177e4
LT		 1193
1194 /* reset BDL address */
1195 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1196 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1197
97b71c94 1198 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1199 periods = azx_dev->bufsize / period_bytes;
1200
1da177e4 1201 /* program the initial BDL entries */
4ce107b9
TI		 1202 bdl = (u32 *)azx_dev->bdl.area;
1203 ofs = 0;
1204 azx_dev->frags = 0;
555e219f
TI		 1205 pos_adj = bdl_pos_adj[chip->dev_index];
1206 if (pos_adj > 0) {
675f25d4 1207 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1208 int pos_align = pos_adj;
555e219f 1209 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1210 if (!pos_adj)
e785d3d8
TI		 1211 pos_adj = pos_align;
1212 else
1213 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1214 pos_align;
675f25d4
TI		 1215 pos_adj = frames_to_bytes(runtime, pos_adj);
1216 if (pos_adj >= period_bytes) {
4abc1cc2 1217 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1218 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1219 pos_adj = 0;
1220 } else {
1221 ofs = setup_bdle(substream, azx_dev,
1222 &bdl, ofs, pos_adj, 1);
1223 if (ofs < 0)
1224 goto error;
4ce107b9 1225 }
555e219f
TI		 1226 } else
1227 pos_adj = 0;
675f25d4
TI		 1228 for (i = 0; i < periods; i++) {
1229 if (i == periods - 1 && pos_adj)
1230 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1231 period_bytes - pos_adj, 0);
1232 else
1233 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1234 period_bytes, 1);
1235 if (ofs < 0)
1236 goto error;
1da177e4 1237 }
4ce107b9 1238 return 0;
675f25d4
TI		 1239
1240 error:
4abc1cc2 1241 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1242 azx_dev->bufsize, period_bytes);
675f25d4 1243 return -EINVAL;
1da177e4
LT		 1244}
1245
1dddab40
TI		 1246/* reset stream */
1247static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1248{
1249 unsigned char val;
1250 int timeout;
1251
1dddab40
TI		 1252 azx_stream_clear(chip, azx_dev);
1253
d01ce99f
TI		 1254 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1255 SD_CTL_STREAM_RESET);
1da177e4
LT		 1256 udelay(3);
1257 timeout = 300;
1258 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1259 --timeout)
1260 ;
1261 val &= ~SD_CTL_STREAM_RESET;
1262 azx_sd_writeb(azx_dev, SD_CTL, val);
1263 udelay(3);
1264
1265 timeout = 300;
1266 /* waiting for hardware to report that the stream is out of reset */
1267 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1268 --timeout)
1269 ;
fa00e046
JK		 1270
1271 /* reset first position - may not be synced with hw at this time */
1272 *azx_dev->posbuf = 0;
1dddab40 1273}
1da177e4 1274
1dddab40
TI		 1275/*
1276 * set up the SD for streaming
1277 */
1278static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1279{
1280 /* make sure the run bit is zero for SD */
1281 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 1282 /* program the stream_tag */
1283 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1284 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1285 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1286
1287 /* program the length of samples in cyclic buffer */
1288 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1289
1290 /* program the stream format */
1291 /* this value needs to be the same as the one programmed */
1292 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1293
1294 /* program the stream LVI (last valid index) of the BDL */
1295 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1296
1297 /* program the BDL address */
1298 /* lower BDL address */
4ce107b9 1299 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1300 /* upper BDL address */
766979e0 1301 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1302
0be3b5d3 1303 /* enable the position buffer */
ee9d6b9a 1304 if (chip->position_fix == POS_FIX_POSBUF ||
0e153474
JC		 1305 chip->position_fix == POS_FIX_AUTO ||
1306 chip->via_dmapos_patch) {
ee9d6b9a
TI		 1307 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1308 azx_writel(chip, DPLBASE,
1309 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1310 }
c74db86b 1311
1da177e4 1312 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1313 azx_sd_writel(azx_dev, SD_CTL,
1314 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1315
1316 return 0;
1317}
1318
6ce4a3bc
TI		 1319/*
1320 * Probe the given codec address
1321 */
1322static int probe_codec(struct azx *chip, int addr)
1323{
1324 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1325 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1326 unsigned int res;
1327
a678cdee 1328 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1329 chip->probing = 1;
1330 azx_send_cmd(chip->bus, cmd);
deadff16 1331 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1332 chip->probing = 0;
a678cdee 1333 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1334 if (res == -1)
1335 return -EIO;
4abc1cc2 1336 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1337 return 0;
1338}
1339
33fa35ed
TI		 1340static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1341 struct hda_pcm *cpcm);
6ce4a3bc 1342static void azx_stop_chip(struct azx *chip);
1da177e4 1343
8dd78330
TI		 1344static void azx_bus_reset(struct hda_bus *bus)
1345{
1346 struct azx *chip = bus->private_data;
8dd78330
TI		 1347
1348 bus->in_reset = 1;
1349 azx_stop_chip(chip);
1350 azx_init_chip(chip);
65f75983 1351#ifdef CONFIG_PM
8dd78330 1352 if (chip->initialized) {
65f75983
AB		 1353 int i;
1354
c8936222 1355 for (i = 0; i < HDA_MAX_PCMS; i++)
8dd78330
TI		 1356 snd_pcm_suspend_all(chip->pcm[i]);
1357 snd_hda_suspend(chip->bus);
1358 snd_hda_resume(chip->bus);
1359 }
65f75983 1360#endif
8dd78330
TI		 1361 bus->in_reset = 0;
1362}
1363
1da177e4
LT		 1364/*
1365 * Codec initialization
1366 */
1367
2f5983f2
TI		 1368/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1369static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
f269002e 1370 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1371};
1372
a1e21c90 1373static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1374{
1375 struct hda_bus_template bus_temp;
34c25350
TI		 1376 int c, codecs, err;
1377 int max_slots;
1da177e4
LT		 1378
1379 memset(&bus_temp, 0, sizeof(bus_temp));
1380 bus_temp.private_data = chip;
1381 bus_temp.modelname = model;
1382 bus_temp.pci = chip->pci;
111d3af5
TI		 1383 bus_temp.ops.command = azx_send_cmd;
1384 bus_temp.ops.get_response = azx_get_response;
176d5335 1385 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1386 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1387#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1388 bus_temp.power_save = &power_save;
cb53c626
TI		 1389 bus_temp.ops.pm_notify = azx_power_notify;
1390#endif
1da177e4 1391
d01ce99f
TI		 1392 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1393 if (err < 0)
1da177e4
LT		 1394 return err;
1395
dc9c8e21
WN		 1396 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1397 chip->bus->needs_damn_long_delay = 1;
1398
34c25350 1399 codecs = 0;
2f5983f2
TI		 1400 max_slots = azx_max_codecs[chip->driver_type];
1401 if (!max_slots)
1402 max_slots = AZX_MAX_CODECS;
6ce4a3bc
TI		 1403
1404 /* First try to probe all given codec slots */
1405 for (c = 0; c < max_slots; c++) {
f1eaaeec 1406 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1407 if (probe_codec(chip, c) < 0) {
1408 /* Some BIOSen give you wrong codec addresses
1409 * that don't exist
1410 */
4abc1cc2
TI		 1411 snd_printk(KERN_WARNING SFX
1412 "Codec #%d probe error; "
6ce4a3bc
TI		 1413 "disabling it...\n", c);
1414 chip->codec_mask &= ~(1 << c);
1415 /* More badly, accessing to a non-existing
1416 * codec often screws up the controller chip,
2448158e 1417 * and disturbs the further communications.
6ce4a3bc
TI		 1418 * Thus if an error occurs during probing,
1419 * better to reset the controller chip to
1420 * get back to the sanity state.
1421 */
1422 azx_stop_chip(chip);
1423 azx_init_chip(chip);
1424 }
1425 }
1426 }
1427
1428 /* Then create codec instances */
34c25350 1429 for (c = 0; c < max_slots; c++) {
f1eaaeec 1430 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1431 struct hda_codec *codec;
a1e21c90 1432 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1433 if (err < 0)
1434 continue;
2dca0bba 1435 codec->beep_mode = chip->beep_mode;
1da177e4 1436 codecs++;
19a982b6
TI		 1437 }
1438 }
1439 if (!codecs) {
1da177e4
LT		 1440 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1441 return -ENXIO;
1442 }
a1e21c90
TI		 1443 return 0;
1444}
1da177e4 1445
a1e21c90
TI		 1446/* configure each codec instance */
1447static int __devinit azx_codec_configure(struct azx *chip)
1448{
1449 struct hda_codec *codec;
1450 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1451 snd_hda_codec_configure(codec);
1452 }
1da177e4
LT		 1453 return 0;
1454}
1455
1456
1457/*
1458 * PCM support
1459 */
1460
1461/* assign a stream for the PCM */
ef18bede
WF		 1462static inline struct azx_dev *
1463azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1464{
07e4ca50 1465 int dev, i, nums;
ef18bede
WF		 1466 struct azx_dev *res = NULL;
1467
1468 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1469 dev = chip->playback_index_offset;
1470 nums = chip->playback_streams;
1471 } else {
1472 dev = chip->capture_index_offset;
1473 nums = chip->capture_streams;
1474 }
1475 for (i = 0; i < nums; i++, dev++)
d01ce99f 1476 if (!chip->azx_dev[dev].opened) {
ef18bede
WF		 1477 res = &chip->azx_dev[dev];
1478 if (res->device == substream->pcm->device)
1479 break;
1da177e4 1480 }
ef18bede
WF		 1481 if (res) {
1482 res->opened = 1;
1483 res->device = substream->pcm->device;
1484 }
1485 return res;
1da177e4
LT		 1486}
1487
1488/* release the assigned stream */
a98f90fd 1489static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1490{
1491 azx_dev->opened = 0;
1492}
1493
a98f90fd 1494static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1495 .info = (SNDRV_PCM_INFO_MMAP |
1496 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1497 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1498 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1499 /* No full-resume yet implemented */
1500 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1501 SNDRV_PCM_INFO_PAUSE |
1502 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1503 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1504 .rates = SNDRV_PCM_RATE_48000,
1505 .rate_min = 48000,
1506 .rate_max = 48000,
1507 .channels_min = 2,
1508 .channels_max = 2,
1509 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1510 .period_bytes_min = 128,
1511 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1512 .periods_min = 2,
1513 .periods_max = AZX_MAX_FRAG,
1514 .fifo_size = 0,
1515};
1516
1517struct azx_pcm {
a98f90fd 1518 struct azx *chip;
1da177e4
LT		 1519 struct hda_codec *codec;
1520 struct hda_pcm_stream *hinfo[2];
1521};
1522
a98f90fd 1523static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1524{
1525 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1526 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1527 struct azx *chip = apcm->chip;
1528 struct azx_dev *azx_dev;
1529 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1530 unsigned long flags;
1531 int err;
1532
62932df8 1533 mutex_lock(&chip->open_mutex);
ef18bede 1534 azx_dev = azx_assign_device(chip, substream);
1da177e4 1535 if (azx_dev == NULL) {
62932df8 1536 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1537 return -EBUSY;
1538 }
1539 runtime->hw = azx_pcm_hw;
1540 runtime->hw.channels_min = hinfo->channels_min;
1541 runtime->hw.channels_max = hinfo->channels_max;
1542 runtime->hw.formats = hinfo->formats;
1543 runtime->hw.rates = hinfo->rates;
1544 snd_pcm_limit_hw_rates(runtime);
1545 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1546 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1547 128);
1548 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1549 128);
cb53c626 1550 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1551 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1552 if (err < 0) {
1da177e4 1553 azx_release_device(azx_dev);
cb53c626 1554 snd_hda_power_down(apcm->codec);
62932df8 1555 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1556 return err;
1557 }
70d321e6 1558 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1559 /* sanity check */
1560 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1561 snd_BUG_ON(!runtime->hw.channels_max) ||
1562 snd_BUG_ON(!runtime->hw.formats) ||
1563 snd_BUG_ON(!runtime->hw.rates)) {
1564 azx_release_device(azx_dev);
1565 hinfo->ops.close(hinfo, apcm->codec, substream);
1566 snd_hda_power_down(apcm->codec);
1567 mutex_unlock(&chip->open_mutex);
1568 return -EINVAL;
1569 }
1da177e4
LT		 1570 spin_lock_irqsave(&chip->reg_lock, flags);
1571 azx_dev->substream = substream;
1572 azx_dev->running = 0;
1573 spin_unlock_irqrestore(&chip->reg_lock, flags);
1574
1575 runtime->private_data = azx_dev;
850f0e52 1576 snd_pcm_set_sync(substream);
62932df8 1577 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1578 return 0;
1579}
1580
a98f90fd 1581static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1582{
1583 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1584 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1585 struct azx *chip = apcm->chip;
1586 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1587 unsigned long flags;
1588
62932df8 1589 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1590 spin_lock_irqsave(&chip->reg_lock, flags);
1591 azx_dev->substream = NULL;
1592 azx_dev->running = 0;
1593 spin_unlock_irqrestore(&chip->reg_lock, flags);
1594 azx_release_device(azx_dev);
1595 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1596 snd_hda_power_down(apcm->codec);
62932df8 1597 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1598 return 0;
1599}
1600
d01ce99f
TI		 1601static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1602 struct snd_pcm_hw_params *hw_params)
1da177e4 1603{
97b71c94
TI		 1604 struct azx_dev *azx_dev = get_azx_dev(substream);
1605
1606 azx_dev->bufsize = 0;
1607 azx_dev->period_bytes = 0;
1608 azx_dev->format_val = 0;
d01ce99f
TI		 1609 return snd_pcm_lib_malloc_pages(substream,
1610 params_buffer_bytes(hw_params));
1da177e4
LT		 1611}
1612
a98f90fd 1613static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1614{
1615 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1616 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1617 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1618
1619 /* reset BDL address */
1620 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1621 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1622 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1623 azx_dev->bufsize = 0;
1624 azx_dev->period_bytes = 0;
1625 azx_dev->format_val = 0;
1da177e4
LT		 1626
1627 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1628
1629 return snd_pcm_lib_free_pages(substream);
1630}
1631
a98f90fd 1632static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1633{
1634 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1635 struct azx *chip = apcm->chip;
1636 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1637 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1638 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94
TI		 1639 unsigned int bufsize, period_bytes, format_val;
1640 int err;
1da177e4 1641
fa00e046 1642 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1643 format_val = snd_hda_calc_stream_format(runtime->rate,
1644 runtime->channels,
1645 runtime->format,
1646 hinfo->maxbps);
1647 if (!format_val) {
d01ce99f
TI		 1648 snd_printk(KERN_ERR SFX
1649 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1650 runtime->rate, runtime->channels, runtime->format);
1651 return -EINVAL;
1652 }
1653
97b71c94
TI		 1654 bufsize = snd_pcm_lib_buffer_bytes(substream);
1655 period_bytes = snd_pcm_lib_period_bytes(substream);
1656
4abc1cc2 1657 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1658 bufsize, format_val);
1659
1660 if (bufsize != azx_dev->bufsize ||
1661 period_bytes != azx_dev->period_bytes ||
1662 format_val != azx_dev->format_val) {
1663 azx_dev->bufsize = bufsize;
1664 azx_dev->period_bytes = period_bytes;
1665 azx_dev->format_val = format_val;
1666 err = azx_setup_periods(chip, substream, azx_dev);
1667 if (err < 0)
1668 return err;
1669 }
1670
fa00e046
JK		 1671 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1672 (runtime->rate * 2);
1da177e4
LT		 1673 azx_setup_controller(chip, azx_dev);
1674 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1675 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1676 else
1677 azx_dev->fifo_size = 0;
1678
1679 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1680 azx_dev->format_val, substream);
1681}
1682
a98f90fd 1683static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1684{
1685 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1686 struct azx *chip = apcm->chip;
850f0e52
TI		 1687 struct azx_dev *azx_dev;
1688 struct snd_pcm_substream *s;
fa00e046 1689 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1690 int nwait, timeout;
1da177e4 1691
1da177e4 1692 switch (cmd) {
fa00e046
JK		 1693 case SNDRV_PCM_TRIGGER_START:
1694 rstart = 1;
1da177e4
LT		 1695 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1696 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1697 start = 1;
1da177e4
LT		 1698 break;
1699 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1700 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1701 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1702 start = 0;
1da177e4
LT		 1703 break;
1704 default:
850f0e52
TI		 1705 return -EINVAL;
1706 }
1707
1708 snd_pcm_group_for_each_entry(s, substream) {
1709 if (s->pcm->card != substream->pcm->card)
1710 continue;
1711 azx_dev = get_azx_dev(s);
1712 sbits |= 1 << azx_dev->index;
1713 nsync++;
1714 snd_pcm_trigger_done(s, substream);
1715 }
1716
1717 spin_lock(&chip->reg_lock);
1718 if (nsync > 1) {
1719 /* first, set SYNC bits of corresponding streams */
1720 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1721 }
1722 snd_pcm_group_for_each_entry(s, substream) {
1723 if (s->pcm->card != substream->pcm->card)
1724 continue;
1725 azx_dev = get_azx_dev(s);
fa00e046
JK		 1726 if (rstart) {
1727 azx_dev->start_flag = 1;
1728 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1729 }
850f0e52
TI		 1730 if (start)
1731 azx_stream_start(chip, azx_dev);
1732 else
1733 azx_stream_stop(chip, azx_dev);
1734 azx_dev->running = start;
1da177e4
LT		 1735 }
1736 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1737 if (start) {
1738 if (nsync == 1)
1739 return 0;
1740 /* wait until all FIFOs get ready */
1741 for (timeout = 5000; timeout; timeout--) {
1742 nwait = 0;
1743 snd_pcm_group_for_each_entry(s, substream) {
1744 if (s->pcm->card != substream->pcm->card)
1745 continue;
1746 azx_dev = get_azx_dev(s);
1747 if (!(azx_sd_readb(azx_dev, SD_STS) &
1748 SD_STS_FIFO_READY))
1749 nwait++;
1750 }
1751 if (!nwait)
1752 break;
1753 cpu_relax();
1754 }
1755 } else {
1756 /* wait until all RUN bits are cleared */
1757 for (timeout = 5000; timeout; timeout--) {
1758 nwait = 0;
1759 snd_pcm_group_for_each_entry(s, substream) {
1760 if (s->pcm->card != substream->pcm->card)
1761 continue;
1762 azx_dev = get_azx_dev(s);
1763 if (azx_sd_readb(azx_dev, SD_CTL) &
1764 SD_CTL_DMA_START)
1765 nwait++;
1766 }
1767 if (!nwait)
1768 break;
1769 cpu_relax();
1770 }
1da177e4 1771 }
850f0e52
TI		 1772 if (nsync > 1) {
1773 spin_lock(&chip->reg_lock);
1774 /* reset SYNC bits */
1775 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1776 spin_unlock(&chip->reg_lock);
1777 }
1778 return 0;
1da177e4
LT		 1779}
1780
0e153474
JC		 1781/* get the current DMA position with correction on VIA chips */
1782static unsigned int azx_via_get_position(struct azx *chip,
1783 struct azx_dev *azx_dev)
1784{
1785 unsigned int link_pos, mini_pos, bound_pos;
1786 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1787 unsigned int fifo_size;
1788
1789 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1790 if (azx_dev->index >= 4) {
1791 /* Playback, no problem using link position */
1792 return link_pos;
1793 }
1794
1795 /* Capture */
1796 /* For new chipset,
1797 * use mod to get the DMA position just like old chipset
1798 */
1799 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1800 mod_dma_pos %= azx_dev->period_bytes;
1801
1802 /* azx_dev->fifo_size can't get FIFO size of in stream.
1803 * Get from base address + offset.
1804 */
1805 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1806
1807 if (azx_dev->insufficient) {
1808 /* Link position never gather than FIFO size */
1809 if (link_pos <= fifo_size)
1810 return 0;
1811
1812 azx_dev->insufficient = 0;
1813 }
1814
1815 if (link_pos <= fifo_size)
1816 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1817 else
1818 mini_pos = link_pos - fifo_size;
1819
1820 /* Find nearest previous boudary */
1821 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1822 mod_link_pos = link_pos % azx_dev->period_bytes;
1823 if (mod_link_pos >= fifo_size)
1824 bound_pos = link_pos - mod_link_pos;
1825 else if (mod_dma_pos >= mod_mini_pos)
1826 bound_pos = mini_pos - mod_mini_pos;
1827 else {
1828 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1829 if (bound_pos >= azx_dev->bufsize)
1830 bound_pos = 0;
1831 }
1832
1833 /* Calculate real DMA position we want */
1834 return bound_pos + mod_dma_pos;
1835}
1836
9ad593f6
TI		 1837static unsigned int azx_get_position(struct azx *chip,
1838 struct azx_dev *azx_dev)
1da177e4 1839{
1da177e4
LT		 1840 unsigned int pos;
1841
0e153474
JC		 1842 if (chip->via_dmapos_patch)
1843 pos = azx_via_get_position(chip, azx_dev);
1844 else if (chip->position_fix == POS_FIX_POSBUF ||
1845 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1846 /* use the position buffer */
929861c6 1847 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1848 } else {
1849 /* read LPIB */
1850 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1851 }
1da177e4
LT		 1852 if (pos >= azx_dev->bufsize)
1853 pos = 0;
9ad593f6
TI		 1854 return pos;
1855}
1856
1857static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1858{
1859 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1860 struct azx *chip = apcm->chip;
1861 struct azx_dev *azx_dev = get_azx_dev(substream);
1862 return bytes_to_frames(substream->runtime,
1863 azx_get_position(chip, azx_dev));
1864}
1865
1866/*
1867 * Check whether the current DMA position is acceptable for updating
1868 * periods. Returns non-zero if it's OK.
1869 *
1870 * Many HD-audio controllers appear pretty inaccurate about
1871 * the update-IRQ timing. The IRQ is issued before actually the
1872 * data is processed. So, we need to process it afterwords in a
1873 * workqueue.
1874 */
1875static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1876{
1877 unsigned int pos;
1878
fa00e046
JK		 1879 if (azx_dev->start_flag &&
1880 time_before_eq(jiffies, azx_dev->start_jiffies))
1881 return -1; /* bogus (too early) interrupt */
1882 azx_dev->start_flag = 0;
1883
9ad593f6
TI		 1884 pos = azx_get_position(chip, azx_dev);
1885 if (chip->position_fix == POS_FIX_AUTO) {
1886 if (!pos) {
1887 printk(KERN_WARNING
1888 "hda-intel: Invalid position buffer, "
1889 "using LPIB read method instead.\n");
d2e1c973 1890 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1891 pos = azx_get_position(chip, azx_dev);
1892 } else
1893 chip->position_fix = POS_FIX_POSBUF;
1894 }
1895
a62741cf
TI		 1896 if (!bdl_pos_adj[chip->dev_index])
1897 return 1; /* no delayed ack */
fed08d03
JB		 1898 if (azx_dev->period_bytes == 0) {
1899 printk(KERN_WARNING
1900 "hda-intel: Divide by zero was avoided "
1901 "in azx_dev->period_bytes.\n");
1902 return 0;
1903 }
9ad593f6
TI		 1904 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1905 return 0; /* NG - it's below the period boundary */
1906 return 1; /* OK, it's fine */
1907}
1908
1909/*
1910 * The work for pending PCM period updates.
1911 */
1912static void azx_irq_pending_work(struct work_struct *work)
1913{
1914 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1915 int i, pending;
1916
a6a950a8
TI		 1917 if (!chip->irq_pending_warned) {
1918 printk(KERN_WARNING
1919 "hda-intel: IRQ timing workaround is activated "
1920 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1921 chip->card->number);
1922 chip->irq_pending_warned = 1;
1923 }
1924
9ad593f6
TI		 1925 for (;;) {
1926 pending = 0;
1927 spin_lock_irq(&chip->reg_lock);
1928 for (i = 0; i < chip->num_streams; i++) {
1929 struct azx_dev *azx_dev = &chip->azx_dev[i];
1930 if (!azx_dev->irq_pending ||
1931 !azx_dev->substream ||
1932 !azx_dev->running)
1933 continue;
1934 if (azx_position_ok(chip, azx_dev)) {
1935 azx_dev->irq_pending = 0;
1936 spin_unlock(&chip->reg_lock);
1937 snd_pcm_period_elapsed(azx_dev->substream);
1938 spin_lock(&chip->reg_lock);
1939 } else
1940 pending++;
1941 }
1942 spin_unlock_irq(&chip->reg_lock);
1943 if (!pending)
1944 return;
1945 cond_resched();
1946 }
1947}
1948
1949/* clear irq_pending flags and assure no on-going workq */
1950static void azx_clear_irq_pending(struct azx *chip)
1951{
1952 int i;
1953
1954 spin_lock_irq(&chip->reg_lock);
1955 for (i = 0; i < chip->num_streams; i++)
1956 chip->azx_dev[i].irq_pending = 0;
1957 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1958}
1959
a98f90fd 1960static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1961 .open = azx_pcm_open,
1962 .close = azx_pcm_close,
1963 .ioctl = snd_pcm_lib_ioctl,
1964 .hw_params = azx_pcm_hw_params,
1965 .hw_free = azx_pcm_hw_free,
1966 .prepare = azx_pcm_prepare,
1967 .trigger = azx_pcm_trigger,
1968 .pointer = azx_pcm_pointer,
4ce107b9 1969 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1970};
1971
a98f90fd 1972static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 1973{
176d5335
TI		 1974 struct azx_pcm *apcm = pcm->private_data;
1975 if (apcm) {
1976 apcm->chip->pcm[pcm->device] = NULL;
1977 kfree(apcm);
1978 }
1da177e4
LT		 1979}
1980
176d5335 1981static int
33fa35ed
TI		 1982azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1983 struct hda_pcm *cpcm)
1da177e4 1984{
33fa35ed 1985 struct azx *chip = bus->private_data;
a98f90fd 1986 struct snd_pcm *pcm;
1da177e4 1987 struct azx_pcm *apcm;
176d5335
TI		 1988 int pcm_dev = cpcm->device;
1989 int s, err;
1da177e4 1990
c8936222 1991 if (pcm_dev >= HDA_MAX_PCMS) {
176d5335
TI		 1992 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1993 pcm_dev);
da3cec35 1994 return -EINVAL;
176d5335
TI		 1995 }
1996 if (chip->pcm[pcm_dev]) {
1997 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1998 return -EBUSY;
1999 }
2000 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2001 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2002 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2003 &pcm);
2004 if (err < 0)
2005 return err;
18cb7109 2006 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2007 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2008 if (apcm == NULL)
2009 return -ENOMEM;
2010 apcm->chip = chip;
2011 apcm->codec = codec;
1da177e4
LT		 2012 pcm->private_data = apcm;
2013 pcm->private_free = azx_pcm_free;
176d5335
TI		 2014 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2015 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2016 chip->pcm[pcm_dev] = pcm;
2017 cpcm->pcm = pcm;
2018 for (s = 0; s < 2; s++) {
2019 apcm->hinfo[s] = &cpcm->stream[s];
2020 if (cpcm->stream[s].substreams)
2021 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2022 }
2023 /* buffer pre-allocation */
4ce107b9 2024 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2025 snd_dma_pci_data(chip->pci),
fc4abee8 2026 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 2027 return 0;
2028}
2029
2030/*
2031 * mixer creation - all stuff is implemented in hda module
2032 */
a98f90fd 2033static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2034{
2035 return snd_hda_build_controls(chip->bus);
2036}
2037
2038
2039/*
2040 * initialize SD streams
2041 */
a98f90fd 2042static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2043{
2044 int i;
2045
2046 /* initialize each stream (aka device)
d01ce99f
TI		 2047 * assign the starting bdl address to each stream (device)
2048 * and initialize
1da177e4 2049 */
07e4ca50 2050 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2051 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2052 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2053 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2054 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2055 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2056 azx_dev->sd_int_sta_mask = 1 << i;
2057 /* stream tag: must be non-zero and unique */
2058 azx_dev->index = i;
2059 azx_dev->stream_tag = i + 1;
2060 }
2061
2062 return 0;
2063}
2064
68e7fffc
TI		 2065static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2066{
437a5a46
TI		 2067 if (request_irq(chip->pci->irq, azx_interrupt,
2068 chip->msi ? 0 : IRQF_SHARED,
9492837a 2069 "hda_intel", chip)) {
68e7fffc
TI		 2070 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2071 "disabling device\n", chip->pci->irq);
2072 if (do_disconnect)
2073 snd_card_disconnect(chip->card);
2074 return -1;
2075 }
2076 chip->irq = chip->pci->irq;
69e13418 2077 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2078 return 0;
2079}
2080
1da177e4 2081
cb53c626
TI		 2082static void azx_stop_chip(struct azx *chip)
2083{
95e99fda 2084 if (!chip->initialized)
cb53c626
TI		 2085 return;
2086
2087 /* disable interrupts */
2088 azx_int_disable(chip);
2089 azx_int_clear(chip);
2090
2091 /* disable CORB/RIRB */
2092 azx_free_cmd_io(chip);
2093
2094 /* disable position buffer */
2095 azx_writel(chip, DPLBASE, 0);
2096 azx_writel(chip, DPUBASE, 0);
2097
2098 chip->initialized = 0;
2099}
2100
2101#ifdef CONFIG_SND_HDA_POWER_SAVE
2102/* power-up/down the controller */
33fa35ed 2103static void azx_power_notify(struct hda_bus *bus)
cb53c626 2104{
33fa35ed 2105 struct azx *chip = bus->private_data;
cb53c626
TI		 2106 struct hda_codec *c;
2107 int power_on = 0;
2108
33fa35ed 2109 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2110 if (c->power_on) {
2111 power_on = 1;
2112 break;
2113 }
2114 }
2115 if (power_on)
2116 azx_init_chip(chip);
0287d970
WF		 2117 else if (chip->running && power_save_controller &&
2118 !bus->power_keep_link_on)
cb53c626 2119 azx_stop_chip(chip);
cb53c626 2120}
5c0b9bec
TI		 2121#endif /* CONFIG_SND_HDA_POWER_SAVE */
2122
2123#ifdef CONFIG_PM
2124/*
2125 * power management
2126 */
986862bd
TI		 2127
2128static int snd_hda_codecs_inuse(struct hda_bus *bus)
2129{
2130 struct hda_codec *codec;
2131
2132 list_for_each_entry(codec, &bus->codec_list, list) {
2133 if (snd_hda_codec_needs_resume(codec))
2134 return 1;
2135 }
2136 return 0;
2137}
cb53c626 2138
421a1252 2139static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2140{
421a1252
TI		 2141 struct snd_card *card = pci_get_drvdata(pci);
2142 struct azx *chip = card->private_data;
1da177e4
LT		 2143 int i;
2144
421a1252 2145 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2146 azx_clear_irq_pending(chip);
c8936222 2147 for (i = 0; i < HDA_MAX_PCMS; i++)
421a1252 2148 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c 2149 if (chip->initialized)
8dd78330 2150 snd_hda_suspend(chip->bus);
cb53c626 2151 azx_stop_chip(chip);
30b35399 2152 if (chip->irq >= 0) {
43001c95 2153 free_irq(chip->irq, chip);
30b35399
TI		 2154 chip->irq = -1;
2155 }
68e7fffc 2156 if (chip->msi)
43001c95 2157 pci_disable_msi(chip->pci);
421a1252
TI		 2158 pci_disable_device(pci);
2159 pci_save_state(pci);
30b35399 2160 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2161 return 0;
2162}
2163
421a1252 2164static int azx_resume(struct pci_dev *pci)
1da177e4 2165{
421a1252
TI		 2166 struct snd_card *card = pci_get_drvdata(pci);
2167 struct azx *chip = card->private_data;
1da177e4 2168
d14a7e0b
TI		 2169 pci_set_power_state(pci, PCI_D0);
2170 pci_restore_state(pci);
30b35399
TI		 2171 if (pci_enable_device(pci) < 0) {
2172 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2173 "disabling device\n");
2174 snd_card_disconnect(card);
2175 return -EIO;
2176 }
2177 pci_set_master(pci);
68e7fffc
TI		 2178 if (chip->msi)
2179 if (pci_enable_msi(pci) < 0)
2180 chip->msi = 0;
2181 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2182 return -EIO;
cb53c626 2183 azx_init_pci(chip);
d804ad92
ML		 2184
2185 if (snd_hda_codecs_inuse(chip->bus))
2186 azx_init_chip(chip);
2187
1da177e4 2188 snd_hda_resume(chip->bus);
421a1252 2189 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2190 return 0;
2191}
2192#endif /* CONFIG_PM */
2193
2194
0cbf0098
TI		 2195/*
2196 * reboot notifier for hang-up problem at power-down
2197 */
2198static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2199{
2200 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2201 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2202 azx_stop_chip(chip);
2203 return NOTIFY_OK;
2204}
2205
2206static void azx_notifier_register(struct azx *chip)
2207{
2208 chip->reboot_notifier.notifier_call = azx_halt;
2209 register_reboot_notifier(&chip->reboot_notifier);
2210}
2211
2212static void azx_notifier_unregister(struct azx *chip)
2213{
2214 if (chip->reboot_notifier.notifier_call)
2215 unregister_reboot_notifier(&chip->reboot_notifier);
2216}
2217
1da177e4
LT		 2218/*
2219 * destructor
2220 */
a98f90fd 2221static int azx_free(struct azx *chip)
1da177e4 2222{
4ce107b9
TI		 2223 int i;
2224
0cbf0098
TI		 2225 azx_notifier_unregister(chip);
2226
ce43fbae 2227 if (chip->initialized) {
9ad593f6 2228 azx_clear_irq_pending(chip);
07e4ca50 2229 for (i = 0; i < chip->num_streams; i++)
1da177e4 2230 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2231 azx_stop_chip(chip);
1da177e4
LT		 2232 }
2233
f000fd80 2234 if (chip->irq >= 0)
1da177e4 2235 free_irq(chip->irq, (void*)chip);
68e7fffc 2236 if (chip->msi)
30b35399 2237 pci_disable_msi(chip->pci);
f079c25a
TI		 2238 if (chip->remap_addr)
2239 iounmap(chip->remap_addr);
1da177e4 2240
4ce107b9
TI		 2241 if (chip->azx_dev) {
2242 for (i = 0; i < chip->num_streams; i++)
2243 if (chip->azx_dev[i].bdl.area)
2244 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2245 }
1da177e4
LT		 2246 if (chip->rb.area)
2247 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2248 if (chip->posbuf.area)
2249 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2250 pci_release_regions(chip->pci);
2251 pci_disable_device(chip->pci);
07e4ca50 2252 kfree(chip->azx_dev);
1da177e4
LT		 2253 kfree(chip);
2254
2255 return 0;
2256}
2257
a98f90fd 2258static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2259{
2260 return azx_free(device->device_data);
2261}
2262
3372a153
TI		 2263/*
2264 * white/black-listing for position_fix
2265 */
623ec047 2266static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2267 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2268 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2269 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
0708cc58 2270 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
d2e1c973 2271 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
45d4ebf1 2272 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3372a153
TI		 2273 {}
2274};
2275
2276static int __devinit check_position_fix(struct azx *chip, int fix)
2277{
2278 const struct snd_pci_quirk *q;
2279
c673ba1c
TI		 2280 switch (fix) {
2281 case POS_FIX_LPIB:
2282 case POS_FIX_POSBUF:
2283 return fix;
2284 }
2285
2286 /* Check VIA/ATI HD Audio Controller exist */
2287 switch (chip->driver_type) {
2288 case AZX_DRIVER_VIA:
2289 case AZX_DRIVER_ATI:
0e153474
JC		 2290 chip->via_dmapos_patch = 1;
2291 /* Use link position directly, avoid any transfer problem. */
2292 return POS_FIX_LPIB;
2293 }
2294 chip->via_dmapos_patch = 0;
2295
c673ba1c
TI		 2296 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2297 if (q) {
2298 printk(KERN_INFO
2299 "hda_intel: position_fix set to %d "
2300 "for device %04x:%04x\n",
2301 q->value, q->subvendor, q->subdevice);
2302 return q->value;
3372a153 2303 }
c673ba1c 2304 return POS_FIX_AUTO;
3372a153
TI		 2305}
2306
669ba27a
TI		 2307/*
2308 * black-lists for probe_mask
2309 */
2310static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2311 /* Thinkpad often breaks the controller communication when accessing
2312 * to the non-working (or non-existing) modem codec slot.
2313 */
2314 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2315 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2316 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2317 /* broken BIOS */
2318 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2319 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2320 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2321 /* forced codec slots */
93574844 2322 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2323 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2324 {}
2325};
2326
f1eaaeec
TI		 2327#define AZX_FORCE_CODEC_MASK 0x100
2328
5aba4f8e 2329static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2330{
2331 const struct snd_pci_quirk *q;
2332
f1eaaeec
TI		 2333 chip->codec_probe_mask = probe_mask[dev];
2334 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2335 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2336 if (q) {
2337 printk(KERN_INFO
2338 "hda_intel: probe_mask set to 0x%x "
2339 "for device %04x:%04x\n",
2340 q->value, q->subvendor, q->subdevice);
f1eaaeec 2341 chip->codec_probe_mask = q->value;
669ba27a
TI		 2342 }
2343 }
f1eaaeec
TI		 2344
2345 /* check forced option */
2346 if (chip->codec_probe_mask != -1 &&
2347 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2348 chip->codec_mask = chip->codec_probe_mask & 0xff;
2349 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2350 chip->codec_mask);
2351 }
669ba27a
TI		 2352}
2353
4d8e22e0 2354/*
71623855 2355 * white/black-list for enable_msi
4d8e22e0 2356 */
71623855 2357static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2358 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
8ce28d6a 2359 SND_PCI_QUIRK(0x1043, 0x829c, "ASUS", 0), /* nvidia */
4d8e22e0
TI		 2360 {}
2361};
2362
2363static void __devinit check_msi(struct azx *chip)
2364{
2365 const struct snd_pci_quirk *q;
2366
71623855
TI		 2367 if (enable_msi >= 0) {
2368 chip->msi = !!enable_msi;
4d8e22e0 2369 return;
71623855
TI		 2370 }
2371 chip->msi = 1; /* enable MSI as default */
2372 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2373 if (q) {
2374 printk(KERN_INFO
2375 "hda_intel: msi for device %04x:%04x set to %d\n",
2376 q->subvendor, q->subdevice, q->value);
2377 chip->msi = q->value;
2378 }
2379}
2380
669ba27a 2381
1da177e4
LT		 2382/*
2383 * constructor
2384 */
a98f90fd 2385static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2386 int dev, int driver_type,
a98f90fd 2387 struct azx **rchip)
1da177e4 2388{
a98f90fd 2389 struct azx *chip;
4ce107b9 2390 int i, err;
bcd72003 2391 unsigned short gcap;
a98f90fd 2392 static struct snd_device_ops ops = {
1da177e4
LT		 2393 .dev_free = azx_dev_free,
2394 };
2395
2396 *rchip = NULL;
bcd72003 2397
927fc866
PM		 2398 err = pci_enable_device(pci);
2399 if (err < 0)
1da177e4
LT		 2400 return err;
2401
e560d8d8 2402 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2403 if (!chip) {
1da177e4
LT		 2404 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2405 pci_disable_device(pci);
2406 return -ENOMEM;
2407 }
2408
2409 spin_lock_init(&chip->reg_lock);
62932df8 2410 mutex_init(&chip->open_mutex);
1da177e4
LT		 2411 chip->card = card;
2412 chip->pci = pci;
2413 chip->irq = -1;
07e4ca50 2414 chip->driver_type = driver_type;
4d8e22e0 2415 check_msi(chip);
555e219f 2416 chip->dev_index = dev;
9ad593f6 2417 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2418
5aba4f8e
TI		 2419 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2420 check_probe_mask(chip, dev);
3372a153 2421
27346166 2422 chip->single_cmd = single_cmd;
c74db86b 2423
5c0d7bc1
TI		 2424 if (bdl_pos_adj[dev] < 0) {
2425 switch (chip->driver_type) {
0c6341ac 2426 case AZX_DRIVER_ICH:
32679f95 2427 case AZX_DRIVER_PCH:
0c6341ac 2428 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2429 break;
2430 default:
0c6341ac 2431 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2432 break;
2433 }
2434 }
2435
07e4ca50
TI		 2436#if BITS_PER_LONG != 64
2437 /* Fix up base address on ULI M5461 */
2438 if (chip->driver_type == AZX_DRIVER_ULI) {
2439 u16 tmp3;
2440 pci_read_config_word(pci, 0x40, &tmp3);
2441 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2442 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2443 }
2444#endif
2445
927fc866
PM		 2446 err = pci_request_regions(pci, "ICH HD audio");
2447 if (err < 0) {
1da177e4
LT		 2448 kfree(chip);
2449 pci_disable_device(pci);
2450 return err;
2451 }
2452
927fc866 2453 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2454 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2455 if (chip->remap_addr == NULL) {
2456 snd_printk(KERN_ERR SFX "ioremap error\n");
2457 err = -ENXIO;
2458 goto errout;
2459 }
2460
68e7fffc
TI		 2461 if (chip->msi)
2462 if (pci_enable_msi(pci) < 0)
2463 chip->msi = 0;
7376d013 2464
68e7fffc 2465 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2466 err = -EBUSY;
2467 goto errout;
2468 }
1da177e4
LT		 2469
2470 pci_set_master(pci);
2471 synchronize_irq(chip->irq);
2472
bcd72003 2473 gcap = azx_readw(chip, GCAP);
4abc1cc2 2474 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2475
dc4c2e6b
AB		 2476 /* disable SB600 64bit support for safety */
2477 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2478 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2479 struct pci_dev *p_smbus;
2480 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2481 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2482 NULL);
2483 if (p_smbus) {
2484 if (p_smbus->revision < 0x30)
2485 gcap &= ~ICH6_GCAP_64OK;
2486 pci_dev_put(p_smbus);
2487 }
2488 }
09240cf4 2489
396087ea
JK		 2490 /* disable 64bit DMA address for Teradici */
2491 /* it does not work with device 6549:1200 subsys e4a2:040b */
2492 if (chip->driver_type == AZX_DRIVER_TERA)
2493 gcap &= ~ICH6_GCAP_64OK;
2494
cf7aaca8 2495 /* allow 64bit DMA address if supported by H/W */
b21fadb9 2496 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 2497 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 2498 else {
e930438c
YH		 2499 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2500 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 2501 }
cf7aaca8 2502
8b6ed8e7
TI		 2503 /* read number of streams from GCAP register instead of using
2504 * hardcoded value
2505 */
2506 chip->capture_streams = (gcap >> 8) & 0x0f;
2507 chip->playback_streams = (gcap >> 12) & 0x0f;
2508 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2509 /* gcap didn't give any info, switching to old method */
2510
2511 switch (chip->driver_type) {
2512 case AZX_DRIVER_ULI:
2513 chip->playback_streams = ULI_NUM_PLAYBACK;
2514 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2515 break;
2516 case AZX_DRIVER_ATIHDMI:
2517 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2518 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2519 break;
c4da29ca 2520 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2521 default:
2522 chip->playback_streams = ICH6_NUM_PLAYBACK;
2523 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2524 break;
2525 }
07e4ca50 2526 }
8b6ed8e7
TI		 2527 chip->capture_index_offset = 0;
2528 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2529 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2530 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2531 GFP_KERNEL);
927fc866 2532 if (!chip->azx_dev) {
4abc1cc2 2533 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
07e4ca50
TI		 2534 goto errout;
2535 }
2536
4ce107b9
TI		 2537 for (i = 0; i < chip->num_streams; i++) {
2538 /* allocate memory for the BDL for each stream */
2539 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2540 snd_dma_pci_data(chip->pci),
2541 BDL_SIZE, &chip->azx_dev[i].bdl);
2542 if (err < 0) {
2543 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2544 goto errout;
2545 }
1da177e4 2546 }
0be3b5d3 2547 /* allocate memory for the position buffer */
d01ce99f
TI		 2548 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2549 snd_dma_pci_data(chip->pci),
2550 chip->num_streams * 8, &chip->posbuf);
2551 if (err < 0) {
0be3b5d3
TI		 2552 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2553 goto errout;
1da177e4 2554 }
1da177e4 2555 /* allocate CORB/RIRB */
81740861
TI		 2556 err = azx_alloc_cmd_io(chip);
2557 if (err < 0)
2558 goto errout;
1da177e4
LT		 2559
2560 /* initialize streams */
2561 azx_init_stream(chip);
2562
2563 /* initialize chip */
cb53c626 2564 azx_init_pci(chip);
1da177e4
LT		 2565 azx_init_chip(chip);
2566
2567 /* codec detection */
927fc866 2568 if (!chip->codec_mask) {
1da177e4
LT		 2569 snd_printk(KERN_ERR SFX "no codecs found!\n");
2570 err = -ENODEV;
2571 goto errout;
2572 }
2573
d01ce99f
TI		 2574 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2575 if (err <0) {
1da177e4
LT		 2576 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2577 goto errout;
2578 }
2579
07e4ca50 2580 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2581 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2582 sizeof(card->shortname));
2583 snprintf(card->longname, sizeof(card->longname),
2584 "%s at 0x%lx irq %i",
2585 card->shortname, chip->addr, chip->irq);
07e4ca50 2586
1da177e4
LT		 2587 *rchip = chip;
2588 return 0;
2589
2590 errout:
2591 azx_free(chip);
2592 return err;
2593}
2594
cb53c626
TI		 2595static void power_down_all_codecs(struct azx *chip)
2596{
2597#ifdef CONFIG_SND_HDA_POWER_SAVE
2598 /* The codecs were powered up in snd_hda_codec_new().
2599 * Now all initialization done, so turn them down if possible
2600 */
2601 struct hda_codec *codec;
2602 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2603 snd_hda_power_down(codec);
2604 }
2605#endif
2606}
2607
d01ce99f
TI		 2608static int __devinit azx_probe(struct pci_dev *pci,
2609 const struct pci_device_id *pci_id)
1da177e4 2610{
5aba4f8e 2611 static int dev;
a98f90fd
TI		 2612 struct snd_card *card;
2613 struct azx *chip;
927fc866 2614 int err;
1da177e4 2615
5aba4f8e
TI		 2616 if (dev >= SNDRV_CARDS)
2617 return -ENODEV;
2618 if (!enable[dev]) {
2619 dev++;
2620 return -ENOENT;
2621 }
2622
e58de7ba
TI		 2623 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2624 if (err < 0) {
1da177e4 2625 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 2626 return err;
1da177e4
LT		 2627 }
2628
4ea6fbc8
TI		 2629 /* set this here since it's referred in snd_hda_load_patch() */
2630 snd_card_set_dev(card, &pci->dev);
2631
5aba4f8e 2632 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2633 if (err < 0)
2634 goto out_free;
421a1252 2635 card->private_data = chip;
1da177e4 2636
2dca0bba
JK		 2637#ifdef CONFIG_SND_HDA_INPUT_BEEP
2638 chip->beep_mode = beep_mode[dev];
2639#endif
2640
1da177e4 2641 /* create codec instances */
a1e21c90 2642 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 2643 if (err < 0)
2644 goto out_free;
4ea6fbc8
TI		 2645#ifdef CONFIG_SND_HDA_PATCH_LOADER
2646 if (patch[dev]) {
2647 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2648 patch[dev]);
2649 err = snd_hda_load_patch(chip->bus, patch[dev]);
2650 if (err < 0)
2651 goto out_free;
2652 }
2653#endif
a1e21c90
TI		 2654 if (!probe_only[dev]) {
2655 err = azx_codec_configure(chip);
2656 if (err < 0)
2657 goto out_free;
2658 }
1da177e4
LT		 2659
2660 /* create PCM streams */
176d5335 2661 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2662 if (err < 0)
2663 goto out_free;
1da177e4
LT		 2664
2665 /* create mixer controls */
d01ce99f 2666 err = azx_mixer_create(chip);
41dda0fd
WF		 2667 if (err < 0)
2668 goto out_free;
1da177e4 2669
d01ce99f 2670 err = snd_card_register(card);
41dda0fd
WF		 2671 if (err < 0)
2672 goto out_free;
1da177e4
LT		 2673
2674 pci_set_drvdata(pci, card);
cb53c626
TI		 2675 chip->running = 1;
2676 power_down_all_codecs(chip);
0cbf0098 2677 azx_notifier_register(chip);
1da177e4 2678
e25bcdba 2679 dev++;
1da177e4 2680 return err;
41dda0fd
WF		 2681out_free:
2682 snd_card_free(card);
2683 return err;
1da177e4
LT		 2684}
2685
2686static void __devexit azx_remove(struct pci_dev *pci)
2687{
2688 snd_card_free(pci_get_drvdata(pci));
2689 pci_set_drvdata(pci, NULL);
2690}
2691
2692/* PCI IDs */
f40b6890 2693static struct pci_device_id azx_ids[] = {
87218e9c
TI		 2694 /* ICH 6..10 */
2695 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2696 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2697 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2698 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2699 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2700 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2701 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2702 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2703 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
b29c2360
SH		 2704 /* PCH */
2705 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
d2f2fcd2 2706 /* CPT */
32679f95 2707 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
87218e9c
TI		 2708 /* SCH */
2709 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2710 /* ATI SB 450/600 */
2711 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2712 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2713 /* ATI HDMI */
2714 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2715 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2716 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2717 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2718 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2719 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2720 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2721 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2722 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2723 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2724 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2725 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2726 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2727 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2728 /* VIA VT8251/VT8237A */
2729 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2730 /* SIS966 */
2731 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2732 /* ULI M5461 */
2733 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2734 /* NVIDIA MCP */
0c2fd1bf
TI		 2735 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2736 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2737 .class_mask = 0xffffff,
2738 .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2739 /* Teradici */
2740 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
4e01f54b 2741 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 2742#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2743 /* the following entry conflicts with snd-ctxfi driver,
2744 * as ctxfi driver mutates from HD-audio to native mode with
2745 * a special command sequence.
2746 */
4e01f54b
TI		 2747 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2748 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2749 .class_mask = 0xffffff,
2750 .driver_data = AZX_DRIVER_GENERIC },
313f6e2d
TI		 2751#else
2752 /* this entry seems still valid -- i.e. without emu20kx chip */
2753 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2754#endif
9176b672 2755 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2756 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2757 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2758 .class_mask = 0xffffff,
2759 .driver_data = AZX_DRIVER_GENERIC },
9176b672
AB		 2760 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2761 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2762 .class_mask = 0xffffff,
2763 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2764 { 0, }
2765};
2766MODULE_DEVICE_TABLE(pci, azx_ids);
2767
2768/* pci_driver definition */
2769static struct pci_driver driver = {
2770 .name = "HDA Intel",
2771 .id_table = azx_ids,
2772 .probe = azx_probe,
2773 .remove = __devexit_p(azx_remove),
421a1252
TI		 2774#ifdef CONFIG_PM
2775 .suspend = azx_suspend,
2776 .resume = azx_resume,
2777#endif
1da177e4
LT		 2778};
2779
2780static int __init alsa_card_azx_init(void)
2781{
01d25d46 2782 return pci_register_driver(&driver);
1da177e4
LT		 2783}
2784
2785static void __exit alsa_card_azx_exit(void)
2786{
2787 pci_unregister_driver(&driver);
2788}
2789
2790module_init(alsa_card_azx_init)
2791module_exit(alsa_card_azx_exit)
Linux 6.x block layer and io_uring tree(s)