projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda: Direct MMIO accesses
[linux-2.6-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
5d890f59 38
27fe48d9
TI		 39#ifdef CONFIG_X86
40/* for snoop control */
41#include <asm/pgtable.h>
7f80f513 42#include <asm/set_memory.h>
50279d9b 43#include <asm/cpufeature.h>
27fe48d9 44#endif
1da177e4
LT		 45#include <sound/core.h>
46#include <sound/initval.h>
98d8fc6c
ML		 47#include <sound/hdaudio.h>
48#include <sound/hda_i915.h>
9121947d 49#include <linux/vgaarb.h>
a82d51ed 50#include <linux/vga_switcheroo.h>
4918cdab 51#include <linux/firmware.h>
be57bfff 52#include <sound/hda_codec.h>
05e84878 53#include "hda_controller.h"
347de1f8 54#include "hda_intel.h"
1da177e4 55
785d8c4b
LY		 56#define CREATE_TRACE_POINTS
57#include "hda_intel_trace.h"
58
b6050ef6
TI		 59/* position fix mode */
60enum {
61 POS_FIX_AUTO,
62 POS_FIX_LPIB,
63 POS_FIX_POSBUF,
64 POS_FIX_VIACOMBO,
65 POS_FIX_COMBO,
f87e7f25 66 POS_FIX_SKL,
b6050ef6
TI		 67};
68
9a34af4a
TI		 69/* Defines for ATI HD Audio support in SB450 south bridge */
70#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
71#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
72
73/* Defines for Nvidia HDA support */
74#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
75#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
76#define NVIDIA_HDA_ISTRM_COH 0x4d
77#define NVIDIA_HDA_OSTRM_COH 0x4c
78#define NVIDIA_HDA_ENABLE_COHBIT 0x01
79
80/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 81#define INTEL_HDA_CGCTL 0x48
82#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 83#define INTEL_SCH_HDA_DEVC 0x78
84#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
85
86/* Define IN stream 0 FIFO size offset in VIA controller */
87#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
88/* Define VIA HD Audio Device ID*/
89#define VIA_HDAC_DEVICE_ID 0x3288
90
33124929
TI		 91/* max number of SDs */
92/* ICH, ATI and VIA have 4 playback and 4 capture */
93#define ICH6_NUM_CAPTURE 4
94#define ICH6_NUM_PLAYBACK 4
95
96/* ULI has 6 playback and 5 capture */
97#define ULI_NUM_CAPTURE 5
98#define ULI_NUM_PLAYBACK 6
99
100/* ATI HDMI may have up to 8 playbacks and 0 capture */
101#define ATIHDMI_NUM_CAPTURE 0
102#define ATIHDMI_NUM_PLAYBACK 8
103
104/* TERA has 4 playback and 3 capture */
105#define TERA_NUM_CAPTURE 3
106#define TERA_NUM_PLAYBACK 4
107
1da177e4 108
5aba4f8e
TI		 109static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
110static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 111static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 112static char *model[SNDRV_CARDS];
1dac6695 113static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 114static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 115static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 116static int probe_only[SNDRV_CARDS];
26a6cb6c 117static int jackpoll_ms[SNDRV_CARDS];
41438f13 118static int single_cmd = -1;
71623855 119static int enable_msi = -1;
4ea6fbc8
TI		 120#ifdef CONFIG_SND_HDA_PATCH_LOADER
121static char *patch[SNDRV_CARDS];
122#endif
2dca0bba 123#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 124static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 125 CONFIG_SND_HDA_INPUT_BEEP_MODE};
126#endif
1da177e4 127
5aba4f8e 128module_param_array(index, int, NULL, 0444);
1da177e4 129MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 130module_param_array(id, charp, NULL, 0444);
1da177e4 131MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 132module_param_array(enable, bool, NULL, 0444);
133MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
134module_param_array(model, charp, NULL, 0444);
1da177e4 135MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 136module_param_array(position_fix, int, NULL, 0444);
4cb36310 137MODULE_PARM_DESC(position_fix, "DMA pointer read method."
f87e7f25 138 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
555e219f
TI		 139module_param_array(bdl_pos_adj, int, NULL, 0644);
140MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 141module_param_array(probe_mask, int, NULL, 0444);
606ad75f 142MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 143module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 144MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 145module_param_array(jackpoll_ms, int, NULL, 0444);
146MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 147module_param(single_cmd, bint, 0444);
d01ce99f
TI		 148MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
149 "(for debugging only).");
ac9ef6cf 150module_param(enable_msi, bint, 0444);
134a11f0 151MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 152#ifdef CONFIG_SND_HDA_PATCH_LOADER
153module_param_array(patch, charp, NULL, 0444);
154MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
155#endif
2dca0bba 156#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 157module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 158MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 159 "(0=off, 1=on) (default=1).");
2dca0bba 160#endif
606ad75f 161
83012a7c 162#ifdef CONFIG_PM
65fcd41d 163static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 164static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 165 .set = param_set_xint,
166 .get = param_get_int,
167};
168#define param_check_xint param_check_int
169
fee2fba3 170static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 171module_param(power_save, xint, 0644);
fee2fba3
TI		 172MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
173 "(in second, 0 = disable).");
1da177e4 174
40088dc4
TI		 175static bool pm_blacklist = true;
176module_param(pm_blacklist, bool, 0644);
177MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
178
dee1b66c
TI		 179/* reset the HD-audio controller in power save mode.
180 * this may give more power-saving, but will take longer time to
181 * wake up.
182 */
8fc24426
TI		 183static bool power_save_controller = 1;
184module_param(power_save_controller, bool, 0644);
dee1b66c 185MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 186#else
bb573928 187#define power_save 0
83012a7c 188#endif /* CONFIG_PM */
dee1b66c 189
7bfe059e
TI		 190static int align_buffer_size = -1;
191module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 192MODULE_PARM_DESC(align_buffer_size,
193 "Force buffer and period sizes to be multiple of 128 bytes.");
194
27fe48d9 195#ifdef CONFIG_X86
7c732015
TI		 196static int hda_snoop = -1;
197module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 198MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 199#else
200#define hda_snoop true
27fe48d9
TI		 201#endif
202
203
1da177e4
LT		 204MODULE_LICENSE("GPL");
205MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
206 "{Intel, ICH6M},"
2f1b3818 207 "{Intel, ICH7},"
f5d40b30 208 "{Intel, ESB2},"
d2981393 209 "{Intel, ICH8},"
f9cc8a8b 210 "{Intel, ICH9},"
c34f5a04 211 "{Intel, ICH10},"
b29c2360 212 "{Intel, PCH},"
d2f2fcd2 213 "{Intel, CPT},"
d2edeb7c 214 "{Intel, PPT},"
8bc039a1 215 "{Intel, LPT},"
144dad99 216 "{Intel, LPT_LP},"
4eeca499 217 "{Intel, WPT_LP},"
c8b00fd2 218 "{Intel, SPT},"
b4565913 219 "{Intel, SPT_LP},"
e926f2c8 220 "{Intel, HPT},"
cea310e8 221 "{Intel, PBG},"
4979bca9 222 "{Intel, SCH},"
fc20a562 223 "{ATI, SB450},"
89be83f8 224 "{ATI, SB600},"
778b6e1b 225 "{ATI, RS600},"
5b15c95f 226 "{ATI, RS690},"
e6db1119
WL		 227 "{ATI, RS780},"
228 "{ATI, R600},"
2797f724
HRK		 229 "{ATI, RV630},"
230 "{ATI, RV610},"
27da1834
WL		 231 "{ATI, RV670},"
232 "{ATI, RV635},"
233 "{ATI, RV620},"
234 "{ATI, RV770},"
fc20a562 235 "{VIA, VT8251},"
47672310 236 "{VIA, VT8237A},"
07e4ca50
TI		 237 "{SiS, SIS966},"
238 "{ULI, M5461}}");
1da177e4
LT		 239MODULE_DESCRIPTION("Intel HDA driver");
240
a82d51ed 241#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 242#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 243#define SUPPORT_VGA_SWITCHEROO
244#endif
245#endif
246
247
1da177e4 248/*
1da177e4 249 */
1da177e4 250
07e4ca50
TI		 251/* driver types */
252enum {
253 AZX_DRIVER_ICH,
32679f95 254 AZX_DRIVER_PCH,
4979bca9 255 AZX_DRIVER_SCH,
a4b4793f 256 AZX_DRIVER_SKL,
fab1285a 257 AZX_DRIVER_HDMI,
07e4ca50 258 AZX_DRIVER_ATI,
778b6e1b 259 AZX_DRIVER_ATIHDMI,
1815b34a 260 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 261 AZX_DRIVER_VIA,
262 AZX_DRIVER_SIS,
263 AZX_DRIVER_ULI,
da3fca21 264 AZX_DRIVER_NVIDIA,
f269002e 265 AZX_DRIVER_TERA,
14d34f16 266 AZX_DRIVER_CTX,
5ae763b1 267 AZX_DRIVER_CTHDA,
c563f473 268 AZX_DRIVER_CMEDIA,
c4da29ca 269 AZX_DRIVER_GENERIC,
2f5983f2 270 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 271};
272
37e661ee
TI		 273#define azx_get_snoop_type(chip) \
274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
275#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
276
b42b4afb
TI		 277/* quirks for old Intel chipsets */
278#define AZX_DCAPS_INTEL_ICH \
103884a3 279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 280
2ea3c6a2 281/* quirks for Intel PCH */
6603249d 282#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 284 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 285
dba9b7b6 286/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 287#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 288 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 289
55913110 290/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 291/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 292#define AZX_DCAPS_INTEL_PCH \
6603249d 293 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 294
6603249d 295/* HSW HDMI */
33499a15 296#define AZX_DCAPS_INTEL_HASWELL \
103884a3 297 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 298 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 299 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 300
54a0405d
LY		 301/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
302#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 305 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 306
40cc2392 307#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 308 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 309
2d846c74 310#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 311 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 312 AZX_DCAPS_I915_COMPONENT)
2d846c74 313
d6795827 314#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 316 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 317
c87693da 318#define AZX_DCAPS_INTEL_BROXTON \
dba9b7b6 319 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 320 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
c87693da 321
9477c58e
TI		 322/* quirks for ATI SB / AMD Hudson */
323#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 324 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
325 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 326
327/* quirks for ATI/AMD HDMI */
328#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
330 AZX_DCAPS_NO_MSI64)
9477c58e 331
37e661ee
TI		 332/* quirks for ATI HDMI with snoop off */
333#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
334 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
335
9477c58e
TI		 336/* quirks for Nvidia */
337#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 338 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 339 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 340
5ae763b1 341#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 342 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 343 AZX_DCAPS_NO_64BIT |\
37e661ee 344 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 345
a82d51ed 346/*
2b760d88 347 * vga_switcheroo support
a82d51ed
TI		 348 */
349#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 350#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
37a3a98e 351#define needs_eld_notify_link(chip) ((chip)->need_eld_notify_link)
5cb543db
TI		 352#else
353#define use_vga_switcheroo(chip) 0
37a3a98e 354#define needs_eld_notify_link(chip) false
5cb543db
TI		 355#endif
356
03b135ce
LY		 357#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
358 ((pci)->device == 0x0c0c) || \
359 ((pci)->device == 0x0d0c) || \
360 ((pci)->device == 0x160c))
361
7e31a015 362#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
a8d7bde2 363#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
fa763f1b 364#define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
7c23b7c1 365
48c8b0eb 366static char *driver_short_names[] = {
07e4ca50 367 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 368 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 369 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 370 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 371 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 372 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 373 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 374 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 375 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
376 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 377 [AZX_DRIVER_ULI] = "HDA ULI M5461",
378 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 379 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 380 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 381 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 382 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 383 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 384};
385
68e7fffc 386static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 387static void set_default_power_save(struct azx *chip);
111d3af5 388
cb53c626
TI		 389/*
390 * initialize the PCI registers
391 */
392/* update bits in a PCI register byte */
393static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
394 unsigned char mask, unsigned char val)
395{
396 unsigned char data;
397
398 pci_read_config_byte(pci, reg, &data);
399 data &= ~mask;
400 data |= (val & mask);
401 pci_write_config_byte(pci, reg, data);
402}
403
404static void azx_init_pci(struct azx *chip)
405{
37e661ee
TI		 406 int snoop_type = azx_get_snoop_type(chip);
407
cb53c626
TI		 408 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
409 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
410 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 411 * codecs.
412 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 413 */
46f2cc80 414 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 415 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 416 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 417 }
cb53c626 418
9477c58e
TI		 419 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
420 * we need to enable snoop.
421 */
37e661ee 422 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 423 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
424 azx_snoop(chip));
cb53c626 425 update_pci_byte(chip->pci,
27fe48d9
TI		 426 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
427 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 428 }
429
430 /* For NVIDIA HDA, enable snoop */
37e661ee 431 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 432 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
433 azx_snoop(chip));
cb53c626
TI		 434 update_pci_byte(chip->pci,
435 NVIDIA_HDA_TRANSREG_ADDR,
436 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 437 update_pci_byte(chip->pci,
438 NVIDIA_HDA_ISTRM_COH,
439 0x01, NVIDIA_HDA_ENABLE_COHBIT);
440 update_pci_byte(chip->pci,
441 NVIDIA_HDA_OSTRM_COH,
442 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 443 }
444
445 /* Enable SCH/PCH snoop if needed */
37e661ee 446 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 447 unsigned short snoop;
90a5ad52 448 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 449 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
450 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
451 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
452 if (!azx_snoop(chip))
453 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
454 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 455 pci_read_config_word(chip->pci,
456 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 457 }
4e76a883
TI		 458 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
459 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
460 "Disabled" : "Enabled");
da3fca21 461 }
1da177e4
LT		 462}
463
7c23b7c1
LH		 464/*
465 * In BXT-P A0, HD-Audio DMA requests is later than expected,
466 * and makes an audio stream sensitive to system latencies when
467 * 24/32 bits are playing.
468 * Adjusting threshold of DMA fifo to force the DMA request
469 * sooner to improve latency tolerance at the expense of power.
470 */
471static void bxt_reduce_dma_latency(struct azx *chip)
472{
473 u32 val;
474
70eafad8 475 val = azx_readl(chip, VS_EM4L);
7c23b7c1 476 val &= (0x3 << 20);
70eafad8 477 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 478}
479
1f9d3d98
LY		 480/*
481 * ML_LCAP bits:
482 * bit 0: 6 MHz Supported
483 * bit 1: 12 MHz Supported
484 * bit 2: 24 MHz Supported
485 * bit 3: 48 MHz Supported
486 * bit 4: 96 MHz Supported
487 * bit 5: 192 MHz Supported
488 */
489static int intel_get_lctl_scf(struct azx *chip)
490{
491 struct hdac_bus *bus = azx_bus(chip);
492 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
493 u32 val, t;
494 int i;
495
496 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
497
498 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
499 t = preferred_bits[i];
500 if (val & (1 << t))
501 return t;
502 }
503
504 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
505 return 0;
506}
507
508static int intel_ml_lctl_set_power(struct azx *chip, int state)
509{
510 struct hdac_bus *bus = azx_bus(chip);
511 u32 val;
512 int timeout;
513
514 /*
515 * the codecs are sharing the first link setting by default
516 * If other links are enabled for stream, they need similar fix
517 */
518 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
519 val &= ~AZX_MLCTL_SPA;
520 val |= state << AZX_MLCTL_SPA_SHIFT;
521 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
522 /* wait for CPA */
523 timeout = 50;
524 while (timeout) {
525 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
526 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
527 return 0;
528 timeout--;
529 udelay(10);
530 }
531
532 return -1;
533}
534
535static void intel_init_lctl(struct azx *chip)
536{
537 struct hdac_bus *bus = azx_bus(chip);
538 u32 val;
539 int ret;
540
541 /* 0. check lctl register value is correct or not */
542 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
543 /* if SCF is already set, let's use it */
544 if ((val & ML_LCTL_SCF_MASK) != 0)
545 return;
546
547 /*
548 * Before operating on SPA, CPA must match SPA.
549 * Any deviation may result in undefined behavior.
550 */
551 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
552 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
553 return;
554
555 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
556 ret = intel_ml_lctl_set_power(chip, 0);
557 udelay(100);
558 if (ret)
559 goto set_spa;
560
561 /* 2. update SCF to select a properly audio clock*/
562 val &= ~ML_LCTL_SCF_MASK;
563 val |= intel_get_lctl_scf(chip);
564 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
565
566set_spa:
567 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
568 intel_ml_lctl_set_power(chip, 1);
569 udelay(100);
570}
571
0a673521
LH		 572static void hda_intel_init_chip(struct azx *chip, bool full_reset)
573{
98d8fc6c 574 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 575 struct pci_dev *pci = chip->pci;
6639484d 576 u32 val;
0a673521 577
e454ff8e 578 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 579 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 580 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
581 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
582 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
583 }
0a673521 584 azx_init_chip(chip, full_reset);
a4b4793f 585 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 586 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
587 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
588 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
589 }
e454ff8e
TI		 590
591 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 592
593 /* reduce dma latency to avoid noise */
7e31a015 594 if (IS_BXT(pci))
7c23b7c1 595 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 596
597 if (bus->mlcap != NULL)
598 intel_init_lctl(chip);
0a673521
LH		 599}
600
b6050ef6
TI		 601/* calculate runtime delay from LPIB */
602static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
603 unsigned int pos)
604{
7833c3f8 605 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 606 int stream = substream->stream;
607 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
608 int delay;
609
610 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
611 delay = pos - lpib_pos;
612 else
613 delay = lpib_pos - pos;
614 if (delay < 0) {
7833c3f8 615 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 616 delay = 0;
617 else
7833c3f8 618 delay += azx_dev->core.bufsize;
b6050ef6
TI		 619 }
620
7833c3f8 621 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 622 dev_info(chip->card->dev,
623 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 624 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 625 delay = 0;
626 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
627 chip->get_delay[stream] = NULL;
628 }
629
630 return bytes_to_frames(substream->runtime, delay);
631}
632
9ad593f6
TI		 633static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
634
7ca954a8
DR		 635/* called from IRQ */
636static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
637{
9a34af4a 638 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 639 int ok;
640
641 ok = azx_position_ok(chip, azx_dev);
642 if (ok == 1) {
643 azx_dev->irq_pending = 0;
644 return ok;
2f35c630 645 } else if (ok == 0) {
7ca954a8
DR		 646 /* bogus IRQ, process it later */
647 azx_dev->irq_pending = 1;
2f35c630 648 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 649 }
650 return 0;
651}
652
029d92c2
TI		 653#define display_power(chip, enable) \
654 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 655
9ad593f6
TI		 656/*
657 * Check whether the current DMA position is acceptable for updating
658 * periods. Returns non-zero if it's OK.
659 *
660 * Many HD-audio controllers appear pretty inaccurate about
661 * the update-IRQ timing. The IRQ is issued before actually the
662 * data is processed. So, we need to process it afterwords in a
663 * workqueue.
664 */
665static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
666{
7833c3f8 667 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 668 int stream = substream->stream;
e5463720 669 u32 wallclk;
9ad593f6
TI		 670 unsigned int pos;
671
7833c3f8
TI		 672 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
673 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 674 return -1; /* bogus (too early) interrupt */
fa00e046 675
b6050ef6
TI		 676 if (chip->get_position[stream])
677 pos = chip->get_position[stream](chip, azx_dev);
678 else { /* use the position buffer as default */
679 pos = azx_get_pos_posbuf(chip, azx_dev);
680 if (!pos || pos == (u32)-1) {
681 dev_info(chip->card->dev,
682 "Invalid position buffer, using LPIB read method instead.\n");
683 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 684 if (chip->get_position[0] == azx_get_pos_lpib &&
685 chip->get_position[1] == azx_get_pos_lpib)
686 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 687 pos = azx_get_pos_lpib(chip, azx_dev);
688 chip->get_delay[stream] = NULL;
689 } else {
690 chip->get_position[stream] = azx_get_pos_posbuf;
691 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
692 chip->get_delay[stream] = azx_get_delay_from_lpib;
693 }
694 }
695
7833c3f8 696 if (pos >= azx_dev->core.bufsize)
b6050ef6 697 pos = 0;
9ad593f6 698
7833c3f8 699 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 700 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 701 return -1; /* this shouldn't happen! */
7833c3f8
TI		 702 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
703 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 704 /* NG - it's below the first next period boundary */
4f0189be 705 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 706 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 707 return 1; /* OK, it's fine */
708}
709
710/*
711 * The work for pending PCM period updates.
712 */
713static void azx_irq_pending_work(struct work_struct *work)
714{
9a34af4a
TI		 715 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
716 struct azx *chip = &hda->chip;
7833c3f8
TI		 717 struct hdac_bus *bus = azx_bus(chip);
718 struct hdac_stream *s;
719 int pending, ok;
9ad593f6 720
9a34af4a 721 if (!hda->irq_pending_warned) {
4e76a883
TI		 722 dev_info(chip->card->dev,
723 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
724 chip->card->number);
9a34af4a 725 hda->irq_pending_warned = 1;
a6a950a8
TI		 726 }
727
9ad593f6
TI		 728 for (;;) {
729 pending = 0;
a41d1224 730 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 731 list_for_each_entry(s, &bus->stream_list, list) {
732 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 733 if (!azx_dev->irq_pending ||
7833c3f8
TI		 734 !s->substream ||
735 !s->running)
9ad593f6 736 continue;
e5463720
JK		 737 ok = azx_position_ok(chip, azx_dev);
738 if (ok > 0) {
9ad593f6 739 azx_dev->irq_pending = 0;
a41d1224 740 spin_unlock(&bus->reg_lock);
7833c3f8 741 snd_pcm_period_elapsed(s->substream);
a41d1224 742 spin_lock(&bus->reg_lock);
e5463720
JK		 743 } else if (ok < 0) {
744 pending = 0; /* too early */
9ad593f6
TI		 745 } else
746 pending++;
747 }
a41d1224 748 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 749 if (!pending)
750 return;
08af495f 751 msleep(1);
9ad593f6
TI		 752 }
753}
754
755/* clear irq_pending flags and assure no on-going workq */
756static void azx_clear_irq_pending(struct azx *chip)
757{
7833c3f8
TI		 758 struct hdac_bus *bus = azx_bus(chip);
759 struct hdac_stream *s;
9ad593f6 760
a41d1224 761 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 762 list_for_each_entry(s, &bus->stream_list, list) {
763 struct azx_dev *azx_dev = stream_to_azx_dev(s);
764 azx_dev->irq_pending = 0;
765 }
a41d1224 766 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 767}
768
68e7fffc
TI		 769static int azx_acquire_irq(struct azx *chip, int do_disconnect)
770{
a41d1224
TI		 771 struct hdac_bus *bus = azx_bus(chip);
772
437a5a46
TI		 773 if (request_irq(chip->pci->irq, azx_interrupt,
774 chip->msi ? 0 : IRQF_SHARED,
de65360b 775 chip->card->irq_descr, chip)) {
4e76a883
TI		 776 dev_err(chip->card->dev,
777 "unable to grab IRQ %d, disabling device\n",
778 chip->pci->irq);
68e7fffc
TI		 779 if (do_disconnect)
780 snd_card_disconnect(chip->card);
781 return -1;
782 }
a41d1224 783 bus->irq = chip->pci->irq;
69e13418 784 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 785 return 0;
786}
787
b6050ef6
TI		 788/* get the current DMA position with correction on VIA chips */
789static unsigned int azx_via_get_position(struct azx *chip,
790 struct azx_dev *azx_dev)
791{
792 unsigned int link_pos, mini_pos, bound_pos;
793 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
794 unsigned int fifo_size;
795
1604eeee 796 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 797 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 798 /* Playback, no problem using link position */
799 return link_pos;
800 }
801
802 /* Capture */
803 /* For new chipset,
804 * use mod to get the DMA position just like old chipset
805 */
7833c3f8
TI		 806 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
807 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 808
809 /* azx_dev->fifo_size can't get FIFO size of in stream.
810 * Get from base address + offset.
811 */
a41d1224
TI		 812 fifo_size = readw(azx_bus(chip)->remap_addr +
813 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 814
815 if (azx_dev->insufficient) {
816 /* Link position never gather than FIFO size */
817 if (link_pos <= fifo_size)
818 return 0;
819
820 azx_dev->insufficient = 0;
821 }
822
823 if (link_pos <= fifo_size)
7833c3f8 824 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 825 else
826 mini_pos = link_pos - fifo_size;
827
828 /* Find nearest previous boudary */
7833c3f8
TI		 829 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
830 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 831 if (mod_link_pos >= fifo_size)
832 bound_pos = link_pos - mod_link_pos;
833 else if (mod_dma_pos >= mod_mini_pos)
834 bound_pos = mini_pos - mod_mini_pos;
835 else {
7833c3f8
TI		 836 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
837 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 838 bound_pos = 0;
839 }
840
841 /* Calculate real DMA position we want */
842 return bound_pos + mod_dma_pos;
843}
844
f87e7f25
TI		 845static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
846 struct azx_dev *azx_dev)
847{
848 return _snd_hdac_chip_readl(azx_bus(chip),
849 AZX_REG_VS_SDXDPIB_XBASE +
850 (AZX_REG_VS_SDXDPIB_XINTERVAL *
851 azx_dev->core.index));
852}
853
854/* get the current DMA position with correction on SKL+ chips */
855static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
856{
857 /* DPIB register gives a more accurate position for playback */
858 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
859 return azx_skl_get_dpib_pos(chip, azx_dev);
860
861 /* For capture, we need to read posbuf, but it requires a delay
862 * for the possible boundary overlap; the read of DPIB fetches the
863 * actual posbuf
864 */
865 udelay(20);
866 azx_skl_get_dpib_pos(chip, azx_dev);
867 return azx_get_pos_posbuf(chip, azx_dev);
868}
869
83012a7c 870#ifdef CONFIG_PM
65fcd41d
TI		 871static DEFINE_MUTEX(card_list_lock);
872static LIST_HEAD(card_list);
873
874static void azx_add_card_list(struct azx *chip)
875{
9a34af4a 876 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 877 mutex_lock(&card_list_lock);
9a34af4a 878 list_add(&hda->list, &card_list);
65fcd41d
TI		 879 mutex_unlock(&card_list_lock);
880}
881
882static void azx_del_card_list(struct azx *chip)
883{
9a34af4a 884 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 885 mutex_lock(&card_list_lock);
9a34af4a 886 list_del_init(&hda->list);
65fcd41d
TI		 887 mutex_unlock(&card_list_lock);
888}
889
890/* trigger power-save check at writing parameter */
891static int param_set_xint(const char *val, const struct kernel_param *kp)
892{
9a34af4a 893 struct hda_intel *hda;
65fcd41d 894 struct azx *chip;
65fcd41d
TI		 895 int prev = power_save;
896 int ret = param_set_int(val, kp);
897
898 if (ret || prev == power_save)
899 return ret;
900
901 mutex_lock(&card_list_lock);
9a34af4a
TI		 902 list_for_each_entry(hda, &card_list, list) {
903 chip = &hda->chip;
a41d1224 904 if (!hda->probe_continued || chip->disabled)
65fcd41d 905 continue;
a41d1224 906 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 907 }
908 mutex_unlock(&card_list_lock);
909 return 0;
910}
5c0b9bec 911
5c0b9bec
TI		 912/*
913 * power management
914 */
3baffc4a 915static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 916{
2d9772ef
TI		 917 struct azx *chip;
918 struct hda_intel *hda;
1da177e4 919
2d9772ef 920 if (!card)
3baffc4a 921 return false;
2d9772ef
TI		 922 chip = card->private_data;
923 hda = container_of(chip, struct hda_intel, chip);
342e8449 924 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 925 return false;
926 return true;
927}
928
929static void __azx_runtime_suspend(struct azx *chip)
930{
3baffc4a
TI		 931 azx_stop_chip(chip);
932 azx_enter_link_reset(chip);
933 azx_clear_irq_pending(chip);
e454ff8e 934 display_power(chip, false);
3baffc4a
TI		 935}
936
744c67ff 937static void __azx_runtime_resume(struct azx *chip, bool from_rt)
3baffc4a
TI		 938{
939 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
940 struct hdac_bus *bus = azx_bus(chip);
941 struct hda_codec *codec;
942 int status;
943
e454ff8e
TI		 944 display_power(chip, true);
945 if (hda->need_i915_power)
946 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 947
948 /* Read STATESTS before controller reset */
949 status = azx_readw(chip, STATESTS);
950
951 azx_init_pci(chip);
952 hda_intel_init_chip(chip, true);
953
744c67ff 954 if (status && from_rt) {
3baffc4a
TI		 955 list_for_each_codec(codec, &chip->bus)
956 if (status & (1 << codec->addr))
957 schedule_delayed_work(&codec->jackpoll_work,
958 codec->jackpoll_interval);
959 }
960
961 /* power down again for link-controlled chips */
e454ff8e 962 if (!hda->need_i915_power)
029d92c2 963 display_power(chip, false);
3baffc4a
TI		 964}
965
966#ifdef CONFIG_PM_SLEEP
967static int azx_suspend(struct device *dev)
968{
969 struct snd_card *card = dev_get_drvdata(dev);
970 struct azx *chip;
971 struct hdac_bus *bus;
972
973 if (!azx_is_pm_ready(card))
c5c21523
TI		 974 return 0;
975
3baffc4a 976 chip = card->private_data;
a41d1224 977 bus = azx_bus(chip);
421a1252 978 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3baffc4a 979 __azx_runtime_suspend(chip);
a41d1224
TI		 980 if (bus->irq >= 0) {
981 free_irq(bus->irq, chip);
982 bus->irq = -1;
30b35399 983 }
a07187c9 984
68e7fffc 985 if (chip->msi)
43001c95 986 pci_disable_msi(chip->pci);
785d8c4b
LY		 987
988 trace_azx_suspend(chip);
1da177e4
LT		 989 return 0;
990}
991
68cb2b55 992static int azx_resume(struct device *dev)
1da177e4 993{
68cb2b55 994 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 995 struct azx *chip;
2d9772ef 996
3baffc4a 997 if (!azx_is_pm_ready(card))
2d9772ef 998 return 0;
1da177e4 999
2d9772ef 1000 chip = card->private_data;
68e7fffc 1001 if (chip->msi)
3baffc4a 1002 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1003 chip->msi = 0;
1004 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1005 return -EIO;
744c67ff 1006 __azx_runtime_resume(chip, false);
421a1252 1007 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1008
1009 trace_azx_resume(chip);
1da177e4
LT		 1010 return 0;
1011}
b8dfc462 1012
3e6db33a
XZ		 1013/* put codec down to D3 at hibernation for Intel SKL+;
1014 * otherwise BIOS may still access the codec and screw up the driver
1015 */
3e6db33a
XZ		 1016static int azx_freeze_noirq(struct device *dev)
1017{
a4b4793f
TI		 1018 struct snd_card *card = dev_get_drvdata(dev);
1019 struct azx *chip = card->private_data;
3e6db33a
XZ		 1020 struct pci_dev *pci = to_pci_dev(dev);
1021
a4b4793f 1022 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1023 pci_set_power_state(pci, PCI_D3hot);
1024
1025 return 0;
1026}
1027
1028static int azx_thaw_noirq(struct device *dev)
1029{
a4b4793f
TI		 1030 struct snd_card *card = dev_get_drvdata(dev);
1031 struct azx *chip = card->private_data;
3e6db33a
XZ		 1032 struct pci_dev *pci = to_pci_dev(dev);
1033
a4b4793f 1034 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1035 pci_set_power_state(pci, PCI_D0);
1036
1037 return 0;
1038}
1039#endif /* CONFIG_PM_SLEEP */
1040
b8dfc462
ML		 1041static int azx_runtime_suspend(struct device *dev)
1042{
1043 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1044 struct azx *chip;
b8dfc462 1045
3baffc4a 1046 if (!azx_is_pm_ready(card))
2d9772ef 1047 return 0;
2d9772ef 1048 chip = card->private_data;
364aa716 1049 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1050 return 0;
1051
7d4f606c
WX		 1052 /* enable controller wake up event */
1053 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1054 STATESTS_INT_MASK);
1055
3baffc4a 1056 __azx_runtime_suspend(chip);
785d8c4b 1057 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1058 return 0;
1059}
1060
1061static int azx_runtime_resume(struct device *dev)
1062{
1063 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1064 struct azx *chip;
b8dfc462 1065
3baffc4a 1066 if (!azx_is_pm_ready(card))
2d9772ef 1067 return 0;
2d9772ef 1068 chip = card->private_data;
364aa716 1069 if (!azx_has_pm_runtime(chip))
246efa4a 1070 return 0;
744c67ff 1071 __azx_runtime_resume(chip, true);
7d4f606c
WX		 1072
1073 /* disable controller Wake Up event*/
1074 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1075 ~STATESTS_INT_MASK);
1076
785d8c4b 1077 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1078 return 0;
1079}
6eb827d2
TI		 1080
1081static int azx_runtime_idle(struct device *dev)
1082{
1083 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1084 struct azx *chip;
1085 struct hda_intel *hda;
1086
1087 if (!card)
1088 return 0;
6eb827d2 1089
2d9772ef
TI		 1090 chip = card->private_data;
1091 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1092 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1093 return 0;
1094
55ed9cd1 1095 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1096 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1097 return -EBUSY;
1098
37a3a98e
TI		 1099 /* ELD notification gets broken when HD-audio bus is off */
1100 if (needs_eld_notify_link(hda))
1101 return -EBUSY;
1102
6eb827d2
TI		 1103 return 0;
1104}
1105
b8dfc462
ML		 1106static const struct dev_pm_ops azx_pm = {
1107 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1108#ifdef CONFIG_PM_SLEEP
1109 .freeze_noirq = azx_freeze_noirq,
1110 .thaw_noirq = azx_thaw_noirq,
1111#endif
6eb827d2 1112 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1113};
1114
68cb2b55
TI		 1115#define AZX_PM_OPS &azx_pm
1116#else
3baffc4a
TI		 1117#define azx_add_card_list(chip) /* NOP */
1118#define azx_del_card_list(chip) /* NOP */
68cb2b55 1119#define AZX_PM_OPS NULL
b8dfc462 1120#endif /* CONFIG_PM */
1da177e4
LT		 1121
1122
48c8b0eb 1123static int azx_probe_continue(struct azx *chip);
a82d51ed 1124
8393ec4a 1125#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1126static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1127
a82d51ed
TI		 1128static void azx_vs_set_state(struct pci_dev *pci,
1129 enum vga_switcheroo_state state)
1130{
1131 struct snd_card *card = pci_get_drvdata(pci);
1132 struct azx *chip = card->private_data;
9a34af4a 1133 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1134 struct hda_codec *codec;
a82d51ed
TI		 1135 bool disabled;
1136
9a34af4a
TI		 1137 wait_for_completion(&hda->probe_wait);
1138 if (hda->init_failed)
a82d51ed
TI		 1139 return;
1140
1141 disabled = (state == VGA_SWITCHEROO_OFF);
1142 if (chip->disabled == disabled)
1143 return;
1144
a41d1224 1145 if (!hda->probe_continued) {
a82d51ed
TI		 1146 chip->disabled = disabled;
1147 if (!disabled) {
4e76a883
TI		 1148 dev_info(chip->card->dev,
1149 "Start delayed initialization\n");
5c90680e 1150 if (azx_probe_continue(chip) < 0) {
4e76a883 1151 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1152 hda->init_failed = true;
a82d51ed
TI		 1153 }
1154 }
1155 } else {
2b760d88 1156 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1157 disabled ? "Disabling" : "Enabling");
a82d51ed 1158 if (disabled) {
07f4f97d
LW		 1159 list_for_each_codec(codec, &chip->bus) {
1160 pm_runtime_suspend(hda_codec_dev(codec));
1161 pm_runtime_disable(hda_codec_dev(codec));
1162 }
1163 pm_runtime_suspend(card->dev);
1164 pm_runtime_disable(card->dev);
2b760d88 1165 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1166 * however we have no ACPI handle, so pci/acpi can't put us there,
1167 * put ourselves there */
1168 pci->current_state = PCI_D3cold;
a82d51ed 1169 chip->disabled = true;
a41d1224 1170 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1171 dev_warn(chip->card->dev,
1172 "Cannot lock devices!\n");
a82d51ed 1173 } else {
a41d1224 1174 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1175 chip->disabled = false;
07f4f97d
LW		 1176 pm_runtime_enable(card->dev);
1177 list_for_each_codec(codec, &chip->bus) {
1178 pm_runtime_enable(hda_codec_dev(codec));
1179 pm_runtime_resume(hda_codec_dev(codec));
1180 }
a82d51ed
TI		 1181 }
1182 }
1183}
1184
1185static bool azx_vs_can_switch(struct pci_dev *pci)
1186{
1187 struct snd_card *card = pci_get_drvdata(pci);
1188 struct azx *chip = card->private_data;
9a34af4a 1189 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1190
9a34af4a
TI		 1191 wait_for_completion(&hda->probe_wait);
1192 if (hda->init_failed)
a82d51ed 1193 return false;
a41d1224 1194 if (chip->disabled || !hda->probe_continued)
a82d51ed 1195 return true;
a41d1224 1196 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1197 return false;
a41d1224 1198 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1199 return true;
1200}
1201
37a3a98e
TI		 1202/*
1203 * The discrete GPU cannot power down unless the HDA controller runtime
1204 * suspends, so activate runtime PM on codecs even if power_save == 0.
1205 */
1206static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1207{
1208 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1209 struct hda_codec *codec;
1210
1211 if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1212 list_for_each_codec(codec, &chip->bus)
1213 codec->auto_runtime_pm = 1;
1214 /* reset the power save setup */
1215 if (chip->running)
1216 set_default_power_save(chip);
1217 }
1218}
1219
1220static void azx_vs_gpu_bound(struct pci_dev *pci,
1221 enum vga_switcheroo_client_id client_id)
1222{
1223 struct snd_card *card = pci_get_drvdata(pci);
1224 struct azx *chip = card->private_data;
1225 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1226
1227 if (client_id == VGA_SWITCHEROO_DIS)
1228 hda->need_eld_notify_link = 0;
1229 setup_vga_switcheroo_runtime_pm(chip);
1230}
1231
e23e7a14 1232static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1233{
9a34af4a 1234 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1235 struct pci_dev *p = get_bound_vga(chip->pci);
1236 if (p) {
4e76a883 1237 dev_info(chip->card->dev,
2b760d88 1238 "Handle vga_switcheroo audio client\n");
9a34af4a 1239 hda->use_vga_switcheroo = 1;
37a3a98e 1240 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
07f4f97d 1241 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1242 pci_dev_put(p);
1243 }
1244}
1245
1246static const struct vga_switcheroo_client_ops azx_vs_ops = {
1247 .set_gpu_state = azx_vs_set_state,
1248 .can_switch = azx_vs_can_switch,
37a3a98e 1249 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1250};
1251
e23e7a14 1252static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1253{
9a34af4a 1254 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1255 struct pci_dev *p;
128960a9
TI		 1256 int err;
1257
9a34af4a 1258 if (!hda->use_vga_switcheroo)
a82d51ed 1259 return 0;
4aaf448f
JQ		 1260
1261 p = get_bound_vga(chip->pci);
1262 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1263 pci_dev_put(p);
1264
128960a9
TI		 1265 if (err < 0)
1266 return err;
9a34af4a 1267 hda->vga_switcheroo_registered = 1;
246efa4a 1268
128960a9 1269 return 0;
a82d51ed
TI		 1270}
1271#else
1272#define init_vga_switcheroo(chip) /* NOP */
1273#define register_vga_switcheroo(chip) 0
8393ec4a 1274#define check_hdmi_disabled(pci) false
37a3a98e 1275#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1276#endif /* SUPPORT_VGA_SWITCHER */
1277
1da177e4
LT		 1278/*
1279 * destructor
1280 */
a98f90fd 1281static int azx_free(struct azx *chip)
1da177e4 1282{
c67e2228 1283 struct pci_dev *pci = chip->pci;
a07187c9 1284 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1285 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1286
364aa716 1287 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228 1288 pm_runtime_get_noresume(&pci->dev);
37a3a98e 1289 chip->running = 0;
c67e2228 1290
65fcd41d
TI		 1291 azx_del_card_list(chip);
1292
9a34af4a
TI		 1293 hda->init_failed = 1; /* to be sure */
1294 complete_all(&hda->probe_wait);
f4c482a4 1295
9a34af4a 1296 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1297 if (chip->disabled && hda->probe_continued)
1298 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1299 if (hda->vga_switcheroo_registered)
128960a9 1300 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1301 }
1302
a41d1224 1303 if (bus->chip_init) {
9ad593f6 1304 azx_clear_irq_pending(chip);
7833c3f8 1305 azx_stop_all_streams(chip);
cb53c626 1306 azx_stop_chip(chip);
1da177e4
LT		 1307 }
1308
a41d1224
TI		 1309 if (bus->irq >= 0)
1310 free_irq(bus->irq, (void*)chip);
68e7fffc 1311 if (chip->msi)
30b35399 1312 pci_disable_msi(chip->pci);
a41d1224 1313 iounmap(bus->remap_addr);
1da177e4 1314
67908994 1315 azx_free_stream_pages(chip);
a41d1224
TI		 1316 azx_free_streams(chip);
1317 snd_hdac_bus_exit(bus);
1318
a82d51ed
TI		 1319 if (chip->region_requested)
1320 pci_release_regions(chip->pci);
a41d1224 1321
1da177e4 1322 pci_disable_device(chip->pci);
4918cdab 1323#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1324 release_firmware(chip->fw);
4918cdab 1325#endif
e454ff8e 1326 display_power(chip, false);
98d8fc6c 1327
fc18282c 1328 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1329 snd_hdac_i915_exit(bus);
a07187c9 1330 kfree(hda);
1da177e4
LT		 1331
1332 return 0;
1333}
1334
a41d1224
TI		 1335static int azx_dev_disconnect(struct snd_device *device)
1336{
1337 struct azx *chip = device->device_data;
1338
1339 chip->bus.shutdown = 1;
1340 return 0;
1341}
1342
a98f90fd 1343static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1344{
1345 return azx_free(device->device_data);
1346}
1347
8393ec4a 1348#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1349/*
2b760d88 1350 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1351 */
e23e7a14 1352static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1353{
1354 struct pci_dev *p;
1355
1356 /* check only discrete GPU */
1357 switch (pci->vendor) {
1358 case PCI_VENDOR_ID_ATI:
1359 case PCI_VENDOR_ID_AMD:
1360 case PCI_VENDOR_ID_NVIDIA:
1361 if (pci->devfn == 1) {
1362 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1363 pci->bus->number, 0);
1364 if (p) {
b6d7b362 1365 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1366 return p;
1367 pci_dev_put(p);
1368 }
1369 }
1370 break;
1371 }
1372 return NULL;
1373}
1374
e23e7a14 1375static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1376{
1377 bool vga_inactive = false;
1378 struct pci_dev *p = get_bound_vga(pci);
1379
1380 if (p) {
12b78a7f 1381 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1382 vga_inactive = true;
1383 pci_dev_put(p);
1384 }
1385 return vga_inactive;
1386}
8393ec4a 1387#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1388
3372a153
TI		 1389/*
1390 * white/black-listing for position_fix
1391 */
e23e7a14 1392static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1393 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1394 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1395 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1396 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1397 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1398 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1399 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1400 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1401 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1402 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1403 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1404 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1405 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1406 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1407 {}
1408};
1409
e23e7a14 1410static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1411{
1412 const struct snd_pci_quirk *q;
1413
c673ba1c 1414 switch (fix) {
1dac6695 1415 case POS_FIX_AUTO:
c673ba1c
TI		 1416 case POS_FIX_LPIB:
1417 case POS_FIX_POSBUF:
4cb36310 1418 case POS_FIX_VIACOMBO:
a6f2fd55 1419 case POS_FIX_COMBO:
f87e7f25 1420 case POS_FIX_SKL:
c673ba1c
TI		 1421 return fix;
1422 }
1423
c673ba1c
TI		 1424 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1425 if (q) {
4e76a883
TI		 1426 dev_info(chip->card->dev,
1427 "position_fix set to %d for device %04x:%04x\n",
1428 q->value, q->subvendor, q->subdevice);
c673ba1c 1429 return q->value;
3372a153 1430 }
bdd9ef24
DH		 1431
1432 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1433 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1434 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1435 return POS_FIX_VIACOMBO;
9477c58e
TI		 1436 }
1437 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1438 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1439 return POS_FIX_LPIB;
bdd9ef24 1440 }
a4b4793f 1441 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1442 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1443 return POS_FIX_SKL;
1444 }
c673ba1c 1445 return POS_FIX_AUTO;
3372a153
TI		 1446}
1447
b6050ef6
TI		 1448static void assign_position_fix(struct azx *chip, int fix)
1449{
1450 static azx_get_pos_callback_t callbacks[] = {
1451 [POS_FIX_AUTO] = NULL,
1452 [POS_FIX_LPIB] = azx_get_pos_lpib,
1453 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1454 [POS_FIX_VIACOMBO] = azx_via_get_position,
1455 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1456 [POS_FIX_SKL] = azx_get_pos_skl,
b6050ef6
TI		 1457 };
1458
1459 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1460
1461 /* combo mode uses LPIB only for playback */
1462 if (fix == POS_FIX_COMBO)
1463 chip->get_position[1] = NULL;
1464
f87e7f25 1465 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1466 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1467 chip->get_delay[0] = chip->get_delay[1] =
1468 azx_get_delay_from_lpib;
1469 }
1470
1471}
1472
669ba27a
TI		 1473/*
1474 * black-lists for probe_mask
1475 */
e23e7a14 1476static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1477 /* Thinkpad often breaks the controller communication when accessing
1478 * to the non-working (or non-existing) modem codec slot.
1479 */
1480 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1481 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1482 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1483 /* broken BIOS */
1484 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1485 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1486 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1487 /* forced codec slots */
93574844 1488 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1489 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1490 /* WinFast VP200 H (Teradici) user reported broken communication */
1491 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1492 {}
1493};
1494
f1eaaeec
TI		 1495#define AZX_FORCE_CODEC_MASK 0x100
1496
e23e7a14 1497static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1498{
1499 const struct snd_pci_quirk *q;
1500
f1eaaeec
TI		 1501 chip->codec_probe_mask = probe_mask[dev];
1502 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1503 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1504 if (q) {
4e76a883
TI		 1505 dev_info(chip->card->dev,
1506 "probe_mask set to 0x%x for device %04x:%04x\n",
1507 q->value, q->subvendor, q->subdevice);
f1eaaeec 1508 chip->codec_probe_mask = q->value;
669ba27a
TI		 1509 }
1510 }
f1eaaeec
TI		 1511
1512 /* check forced option */
1513 if (chip->codec_probe_mask != -1 &&
1514 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1515 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1516 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1517 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1518 }
669ba27a
TI		 1519}
1520
4d8e22e0 1521/*
71623855 1522 * white/black-list for enable_msi
4d8e22e0 1523 */
e23e7a14 1524static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1525 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1526 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1527 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1528 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1529 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1530 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1531 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1532 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1533 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1534 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1535 {}
1536};
1537
e23e7a14 1538static void check_msi(struct azx *chip)
4d8e22e0
TI		 1539{
1540 const struct snd_pci_quirk *q;
1541
71623855
TI		 1542 if (enable_msi >= 0) {
1543 chip->msi = !!enable_msi;
4d8e22e0 1544 return;
71623855
TI		 1545 }
1546 chip->msi = 1; /* enable MSI as default */
1547 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1548 if (q) {
4e76a883
TI		 1549 dev_info(chip->card->dev,
1550 "msi for device %04x:%04x set to %d\n",
1551 q->subvendor, q->subdevice, q->value);
4d8e22e0 1552 chip->msi = q->value;
80c43ed7
TI		 1553 return;
1554 }
1555
1556 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1557 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1558 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1559 chip->msi = 0;
4d8e22e0
TI		 1560 }
1561}
1562
a1585d76 1563/* check the snoop mode availability */
e23e7a14 1564static void azx_check_snoop_available(struct azx *chip)
a1585d76 1565{
7c732015 1566 int snoop = hda_snoop;
a1585d76 1567
7c732015
TI		 1568 if (snoop >= 0) {
1569 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1570 snoop ? "snoop" : "non-snoop");
1571 chip->snoop = snoop;
78c9be61 1572 chip->uc_buffer = !snoop;
7c732015
TI		 1573 return;
1574 }
1575
1576 snoop = true;
37e661ee
TI		 1577 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1578 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1579 /* force to non-snoop mode for a new VIA controller
1580 * when BIOS is set
1581 */
7c732015
TI		 1582 u8 val;
1583 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1584 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1585 chip->pci->revision == 0x20))
7c732015 1586 snoop = false;
a1585d76
TI		 1587 }
1588
37e661ee
TI		 1589 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1590 snoop = false;
1591
7c732015 1592 chip->snoop = snoop;
78c9be61 1593 if (!snoop) {
7c732015 1594 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1595 /* C-Media requires non-cached pages only for CORB/RIRB */
1596 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1597 chip->uc_buffer = true;
1598 }
a1585d76 1599}
669ba27a 1600
99a2008d
WX		 1601static void azx_probe_work(struct work_struct *work)
1602{
9a34af4a
TI		 1603 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1604 azx_probe_continue(&hda->chip);
99a2008d 1605}
99a2008d 1606
4f0189be
TI		 1607static int default_bdl_pos_adj(struct azx *chip)
1608{
2cf721db
TI		 1609 /* some exceptions: Atoms seem problematic with value 1 */
1610 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1611 switch (chip->pci->device) {
1612 case 0x0f04: /* Baytrail */
1613 case 0x2284: /* Braswell */
1614 return 32;
1615 }
1616 }
1617
4f0189be
TI		 1618 switch (chip->driver_type) {
1619 case AZX_DRIVER_ICH:
1620 case AZX_DRIVER_PCH:
1621 return 1;
1622 default:
1623 return 32;
1624 }
1625}
1626
1da177e4
LT		 1627/*
1628 * constructor
1629 */
a43ff5ba
TI		 1630static const struct hda_controller_ops pci_hda_ops;
1631
e23e7a14
BP		 1632static int azx_create(struct snd_card *card, struct pci_dev *pci,
1633 int dev, unsigned int driver_caps,
1634 struct azx **rchip)
1da177e4 1635{
a98f90fd 1636 static struct snd_device_ops ops = {
a41d1224 1637 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1638 .dev_free = azx_dev_free,
1639 };
a07187c9 1640 struct hda_intel *hda;
a82d51ed
TI		 1641 struct azx *chip;
1642 int err;
1da177e4
LT		 1643
1644 *rchip = NULL;
bcd72003 1645
927fc866
PM		 1646 err = pci_enable_device(pci);
1647 if (err < 0)
1da177e4
LT		 1648 return err;
1649
a07187c9
ML		 1650 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1651 if (!hda) {
1da177e4
LT		 1652 pci_disable_device(pci);
1653 return -ENOMEM;
1654 }
1655
a07187c9 1656 chip = &hda->chip;
62932df8 1657 mutex_init(&chip->open_mutex);
1da177e4
LT		 1658 chip->card = card;
1659 chip->pci = pci;
a43ff5ba 1660 chip->ops = &pci_hda_ops;
9477c58e
TI		 1661 chip->driver_caps = driver_caps;
1662 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1663 check_msi(chip);
555e219f 1664 chip->dev_index = dev;
3a182c84
TI		 1665 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1666 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1667 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1668 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1669 INIT_LIST_HEAD(&hda->list);
a82d51ed 1670 init_vga_switcheroo(chip);
9a34af4a 1671 init_completion(&hda->probe_wait);
1da177e4 1672
b6050ef6 1673 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1674
5aba4f8e 1675 check_probe_mask(chip, dev);
3372a153 1676
41438f13
TI		 1677 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1678 chip->fallback_to_single_cmd = 1;
1679 else /* explicitly set to single_cmd or not */
1680 chip->single_cmd = single_cmd;
1681
a1585d76 1682 azx_check_snoop_available(chip);
c74db86b 1683
4f0189be
TI		 1684 if (bdl_pos_adj[dev] < 0)
1685 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1686 else
1687 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1688
19abfefd 1689 err = azx_bus_init(chip, model[dev]);
a41d1224
TI		 1690 if (err < 0) {
1691 kfree(hda);
1692 pci_disable_device(pci);
1693 return err;
1694 }
1695
619a1f19
TI		 1696 /* use the non-cached pages in non-snoop mode */
1697 if (!azx_snoop(chip))
1698 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1699
bd2956e4
BL		 1700 /* Workaround for a communication error on CFL (bko#199007) and CNL */
1701 if (IS_CFL(pci) || IS_CNL(pci))
8af42130 1702 azx_bus(chip)->polling_mode = 1;
bd2956e4 1703
7d9a1808
TI		 1704 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1705 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1706 chip->bus.needs_damn_long_delay = 1;
1707 }
1708
a82d51ed
TI		 1709 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1710 if (err < 0) {
4e76a883 1711 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1712 azx_free(chip);
1713 return err;
1714 }
1715
99a2008d 1716 /* continue probing in work context as may trigger request module */
9a34af4a 1717 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1718
a82d51ed 1719 *rchip = chip;
99a2008d 1720
a82d51ed
TI		 1721 return 0;
1722}
1723
48c8b0eb 1724static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1725{
1726 int dev = chip->dev_index;
1727 struct pci_dev *pci = chip->pci;
1728 struct snd_card *card = chip->card;
a41d1224 1729 struct hdac_bus *bus = azx_bus(chip);
67908994 1730 int err;
a82d51ed 1731 unsigned short gcap;
413cbf46 1732 unsigned int dma_bits = 64;
a82d51ed 1733
07e4ca50
TI		 1734#if BITS_PER_LONG != 64
1735 /* Fix up base address on ULI M5461 */
1736 if (chip->driver_type == AZX_DRIVER_ULI) {
1737 u16 tmp3;
1738 pci_read_config_word(pci, 0x40, &tmp3);
1739 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1740 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1741 }
1742#endif
1743
927fc866 1744 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1745 if (err < 0)
1da177e4 1746 return err;
a82d51ed 1747 chip->region_requested = 1;
1da177e4 1748
a41d1224
TI		 1749 bus->addr = pci_resource_start(pci, 0);
1750 bus->remap_addr = pci_ioremap_bar(pci, 0);
1751 if (bus->remap_addr == NULL) {
4e76a883 1752 dev_err(card->dev, "ioremap error\n");
a82d51ed 1753 return -ENXIO;
1da177e4
LT		 1754 }
1755
a4b4793f 1756 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1757 snd_hdac_bus_parse_capabilities(bus);
1758
1759 /*
1760 * Some Intel CPUs has always running timer (ART) feature and
1761 * controller may have Global time sync reporting capability, so
1762 * check both of these before declaring synchronized time reporting
1763 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1764 */
1765 chip->gts_present = false;
1766
1767#ifdef CONFIG_X86
1768 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1769 chip->gts_present = true;
1770#endif
1771
db79afa1
BH		 1772 if (chip->msi) {
1773 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1774 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1775 pci->no_64bit_msi = true;
1776 }
68e7fffc
TI		 1777 if (pci_enable_msi(pci) < 0)
1778 chip->msi = 0;
db79afa1 1779 }
7376d013 1780
1da177e4 1781 pci_set_master(pci);
a41d1224 1782 synchronize_irq(bus->irq);
1da177e4 1783
bcd72003 1784 gcap = azx_readw(chip, GCAP);
4e76a883 1785 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1786
413cbf46
TI		 1787 /* AMD devices support 40 or 48bit DMA, take the safe one */
1788 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1789 dma_bits = 40;
1790
dc4c2e6b 1791 /* disable SB600 64bit support for safety */
9477c58e 1792 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1793 struct pci_dev *p_smbus;
413cbf46 1794 dma_bits = 40;
dc4c2e6b
AB		 1795 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1796 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1797 NULL);
1798 if (p_smbus) {
1799 if (p_smbus->revision < 0x30)
fb1d8ac2 1800 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1801 pci_dev_put(p_smbus);
1802 }
1803 }
09240cf4 1804
3ab7511e
AB		 1805 /* NVidia hardware normally only supports up to 40 bits of DMA */
1806 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1807 dma_bits = 40;
1808
9477c58e
TI		 1809 /* disable 64bit DMA address on some devices */
1810 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1811 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1812 gcap &= ~AZX_GCAP_64OK;
9477c58e 1813 }
396087ea 1814
2ae66c26 1815 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1816 if (align_buffer_size >= 0)
1817 chip->align_buffer_size = !!align_buffer_size;
1818 else {
103884a3 1819 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1820 chip->align_buffer_size = 0;
7bfe059e
TI		 1821 else
1822 chip->align_buffer_size = 1;
1823 }
2ae66c26 1824
cf7aaca8 1825 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1826 if (!(gcap & AZX_GCAP_64OK))
1827 dma_bits = 32;
412b979c
QL		 1828 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1829 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1830 } else {
412b979c
QL		 1831 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1832 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1833 }
cf7aaca8 1834
8b6ed8e7
TI		 1835 /* read number of streams from GCAP register instead of using
1836 * hardcoded value
1837 */
1838 chip->capture_streams = (gcap >> 8) & 0x0f;
1839 chip->playback_streams = (gcap >> 12) & 0x0f;
1840 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1841 /* gcap didn't give any info, switching to old method */
1842
1843 switch (chip->driver_type) {
1844 case AZX_DRIVER_ULI:
1845 chip->playback_streams = ULI_NUM_PLAYBACK;
1846 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1847 break;
1848 case AZX_DRIVER_ATIHDMI:
1815b34a 1849 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1850 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1851 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1852 break;
c4da29ca 1853 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1854 default:
1855 chip->playback_streams = ICH6_NUM_PLAYBACK;
1856 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1857 break;
1858 }
07e4ca50 1859 }
8b6ed8e7
TI		 1860 chip->capture_index_offset = 0;
1861 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1862 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1863
df56c3db
JK		 1864 /* sanity check for the SDxCTL.STRM field overflow */
1865 if (chip->num_streams > 15 &&
1866 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1867 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1868 "forcing separate stream tags", chip->num_streams);
1869 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1870 }
1871
a41d1224
TI		 1872 /* initialize streams */
1873 err = azx_init_streams(chip);
81740861 1874 if (err < 0)
a82d51ed 1875 return err;
1da177e4 1876
a41d1224
TI		 1877 err = azx_alloc_stream_pages(chip);
1878 if (err < 0)
1879 return err;
1da177e4
LT		 1880
1881 /* initialize chip */
cb53c626 1882 azx_init_pci(chip);
e4d9e513 1883
e454ff8e 1884 snd_hdac_i915_set_bclk(bus);
e4d9e513 1885
0a673521 1886 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1887
1888 /* codec detection */
a41d1224 1889 if (!azx_bus(chip)->codec_mask) {
4e76a883 1890 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1891 return -ENODEV;
1da177e4
LT		 1892 }
1893
f495222e
TI		 1894 if (azx_acquire_irq(chip, 0) < 0)
1895 return -EBUSY;
1896
07e4ca50 1897 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1898 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1899 sizeof(card->shortname));
1900 snprintf(card->longname, sizeof(card->longname),
1901 "%s at 0x%lx irq %i",
a41d1224 1902 card->shortname, bus->addr, bus->irq);
07e4ca50 1903
1da177e4 1904 return 0;
1da177e4
LT		 1905}
1906
97c6a3d1 1907#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1908/* callback from request_firmware_nowait() */
1909static void azx_firmware_cb(const struct firmware *fw, void *context)
1910{
1911 struct snd_card *card = context;
1912 struct azx *chip = card->private_data;
1913 struct pci_dev *pci = chip->pci;
1914
1915 if (!fw) {
4e76a883 1916 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1917 goto error;
1918 }
1919
1920 chip->fw = fw;
1921 if (!chip->disabled) {
1922 /* continue probing */
1923 if (azx_probe_continue(chip))
1924 goto error;
1925 }
1926 return; /* OK */
1927
1928 error:
1929 snd_card_free(card);
1930 pci_set_drvdata(pci, NULL);
1931}
97c6a3d1 1932#endif
5cb543db 1933
f46ea609
DR		 1934static int disable_msi_reset_irq(struct azx *chip)
1935{
a41d1224 1936 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1937 int err;
1938
a41d1224
TI		 1939 free_irq(bus->irq, chip);
1940 bus->irq = -1;
f46ea609
DR		 1941 pci_disable_msi(chip->pci);
1942 chip->msi = 0;
1943 err = azx_acquire_irq(chip, 1);
1944 if (err < 0)
1945 return err;
1946
1947 return 0;
1948}
1949
8769b278
DR		 1950static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1951 struct vm_area_struct *area)
1952{
1953#ifdef CONFIG_X86
1954 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1955 struct azx *chip = apcm->chip;
78c9be61 1956 if (chip->uc_buffer)
8769b278
DR		 1957 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1958#endif
1959}
1960
a43ff5ba
TI		 1961static const struct hda_controller_ops pci_hda_ops = {
1962 .disable_msi_reset_irq = disable_msi_reset_irq,
8769b278 1963 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1964 .position_check = azx_position_check,
40830813
DR		 1965};
1966
e23e7a14
BP		 1967static int azx_probe(struct pci_dev *pci,
1968 const struct pci_device_id *pci_id)
1da177e4 1969{
5aba4f8e 1970 static int dev;
a98f90fd 1971 struct snd_card *card;
9a34af4a 1972 struct hda_intel *hda;
a98f90fd 1973 struct azx *chip;
aad730d0 1974 bool schedule_probe;
927fc866 1975 int err;
1da177e4 1976
5aba4f8e
TI		 1977 if (dev >= SNDRV_CARDS)
1978 return -ENODEV;
1979 if (!enable[dev]) {
1980 dev++;
1981 return -ENOENT;
1982 }
1983
60c5772b
TI		 1984 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1985 0, &card);
e58de7ba 1986 if (err < 0) {
4e76a883 1987 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1988 return err;
1da177e4
LT		 1989 }
1990
a43ff5ba 1991 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 1992 if (err < 0)
1993 goto out_free;
421a1252 1994 card->private_data = chip;
9a34af4a 1995 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1996
1997 pci_set_drvdata(pci, card);
1998
1999 err = register_vga_switcheroo(chip);
2000 if (err < 0) {
2b760d88 2001 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2002 goto out_free;
2003 }
2004
2005 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2006 dev_info(card->dev, "VGA controller is disabled\n");
2007 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2008 chip->disabled = true;
2009 }
2010
aad730d0 2011 schedule_probe = !chip->disabled;
1da177e4 2012
4918cdab
TI		 2013#ifdef CONFIG_SND_HDA_PATCH_LOADER
2014 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2015 dev_info(card->dev, "Applying patch firmware '%s'\n",
2016 patch[dev]);
5cb543db
TI		 2017 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2018 &pci->dev, GFP_KERNEL, card,
2019 azx_firmware_cb);
4918cdab
TI		 2020 if (err < 0)
2021 goto out_free;
aad730d0 2022 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2023 }
2024#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2025
aad730d0 2026#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2027 if (CONTROLLER_IN_GPU(pci))
2028 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2029#endif
99a2008d 2030
aad730d0 2031 if (schedule_probe)
9a34af4a 2032 schedule_work(&hda->probe_work);
a82d51ed 2033
a82d51ed 2034 dev++;
88d071fc 2035 if (chip->disabled)
9a34af4a 2036 complete_all(&hda->probe_wait);
a82d51ed
TI		 2037 return 0;
2038
2039out_free:
2040 snd_card_free(card);
2041 return err;
2042}
2043
1ba8f9d3
HG		 2044#ifdef CONFIG_PM
2045/* On some boards setting power_save to a non 0 value leads to clicking /
2046 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2047 * figure out how to avoid these sounds, but that is not always feasible.
2048 * So we keep a list of devices where we disable powersaving as its known
2049 * to causes problems on these devices.
2050 */
2051static struct snd_pci_quirk power_save_blacklist[] = {
2052 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2053 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2054 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2055 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2056 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2057 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2058 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2059 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
b529ef24
HG		 2060 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2061 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
38d9c12c 2062 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2063 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2064 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2065 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2066 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2067 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2068 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2069 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2070 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2071 /* https://bugs.launchpad.net/bugs/1821663 */
2072 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2073 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2074 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2075 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2076 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
721f1e6c
JK		 2077 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2078 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2079 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2080 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2081 /* https://bugs.launchpad.net/bugs/1821663 */
2082 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
1ba8f9d3
HG		 2083 {}
2084};
2085#endif /* CONFIG_PM */
2086
37a3a98e
TI		 2087static void set_default_power_save(struct azx *chip)
2088{
2089 int val = power_save;
2090
2091#ifdef CONFIG_PM
2092 if (pm_blacklist) {
2093 const struct snd_pci_quirk *q;
2094
2095 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2096 if (q && val) {
2097 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2098 q->subvendor, q->subdevice);
2099 val = 0;
2100 }
2101 }
2102#endif /* CONFIG_PM */
2103 snd_hda_set_power_save(&chip->bus, val * 1000);
2104}
2105
e62a42ae
DR		 2106/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2107static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2108 [AZX_DRIVER_NVIDIA] = 8,
2109 [AZX_DRIVER_TERA] = 1,
2110};
2111
48c8b0eb 2112static int azx_probe_continue(struct azx *chip)
a82d51ed 2113{
9a34af4a 2114 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2115 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2116 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2117 int dev = chip->dev_index;
2118 int err;
2119
305a0ade 2120 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2121 hda->probe_continued = 1;
795614dd 2122
fcc88d91 2123 /* bind with i915 if needed */
dba9b7b6 2124 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2125 err = snd_hdac_i915_init(bus);
535115b5
TI		 2126 if (err < 0) {
2127 /* if the controller is bound only with HDMI/DP
2128 * (for HSW and BDW), we need to abort the probe;
2129 * for other chips, still continue probing as other
2130 * codecs can be on the same link.
2131 */
bed2e98e
TI		 2132 if (CONTROLLER_IN_GPU(pci)) {
2133 dev_err(chip->card->dev,
2134 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2135 goto out_free;
fcc88d91
TI		 2136 } else {
2137 /* don't bother any longer */
e454ff8e 2138 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
fcc88d91 2139 }
535115b5 2140 }
e454ff8e
TI		 2141
2142 /* HSW/BDW controllers need this power */
2143 if (CONTROLLER_IN_GPU(pci))
2144 hda->need_i915_power = 1;
fcc88d91
TI		 2145 }
2146
2147 /* Request display power well for the HDA controller or codec. For
2148 * Haswell/Broadwell, both the display HDA controller and codec need
2149 * this power. For other platforms, like Baytrail/Braswell, only the
2150 * display codec needs the power and it can be released after probe.
2151 */
4f799e73 2152 display_power(chip, true);
99a2008d 2153
5c90680e
TI		 2154 err = azx_first_init(chip);
2155 if (err < 0)
2156 goto out_free;
2157
2dca0bba
JK		 2158#ifdef CONFIG_SND_HDA_INPUT_BEEP
2159 chip->beep_mode = beep_mode[dev];
2160#endif
2161
1da177e4 2162 /* create codec instances */
96d2bd6e 2163 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2164 if (err < 0)
2165 goto out_free;
96d2bd6e 2166
4ea6fbc8 2167#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2168 if (chip->fw) {
a41d1224 2169 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2170 chip->fw->data);
4ea6fbc8
TI		 2171 if (err < 0)
2172 goto out_free;
e39ae856 2173#ifndef CONFIG_PM
4918cdab
TI		 2174 release_firmware(chip->fw); /* no longer needed */
2175 chip->fw = NULL;
e39ae856 2176#endif
4ea6fbc8
TI		 2177 }
2178#endif
10e77dda 2179 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2180 err = azx_codec_configure(chip);
2181 if (err < 0)
2182 goto out_free;
2183 }
1da177e4 2184
a82d51ed 2185 err = snd_card_register(chip->card);
41dda0fd
WF		 2186 if (err < 0)
2187 goto out_free;
1da177e4 2188
37a3a98e
TI		 2189 setup_vga_switcheroo_runtime_pm(chip);
2190
cb53c626 2191 chip->running = 1;
65fcd41d 2192 azx_add_card_list(chip);
07f4f97d 2193
37a3a98e 2194 set_default_power_save(chip);
07f4f97d 2195
07f4f97d 2196 if (azx_has_pm_runtime(chip))
30ff5957 2197 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2198
41dda0fd 2199out_free:
457f3c86 2200 if (err < 0 || !hda->need_i915_power)
029d92c2 2201 display_power(chip, false);
88d071fc 2202 if (err < 0)
9a34af4a
TI		 2203 hda->init_failed = 1;
2204 complete_all(&hda->probe_wait);
305a0ade 2205 to_hda_bus(bus)->bus_probing = 0;
41dda0fd 2206 return err;
1da177e4
LT		 2207}
2208
e23e7a14 2209static void azx_remove(struct pci_dev *pci)
1da177e4 2210{
9121947d 2211 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2212 struct azx *chip;
2213 struct hda_intel *hda;
2214
2215 if (card) {
0b8c8219 2216 /* cancel the pending probing work */
991f86d7
TI		 2217 chip = card->private_data;
2218 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2219 /* FIXME: below is an ugly workaround.
2220 * Both device_release_driver() and driver_probe_device()
2221 * take *both* the device's and its parent's lock before
2222 * calling the remove() and probe() callbacks. The codec
2223 * probe takes the locks of both the codec itself and its
2224 * parent, i.e. the PCI controller dev. Meanwhile, when
2225 * the PCI controller is unbound, it takes its lock, too
2226 * ==> ouch, a deadlock!
2227 * As a workaround, we unlock temporarily here the controller
2228 * device during cancel_work_sync() call.
2229 */
2230 device_unlock(&pci->dev);
0b8c8219 2231 cancel_work_sync(&hda->probe_work);
ab949d51 2232 device_lock(&pci->dev);
b8dfc462 2233
9121947d 2234 snd_card_free(card);
991f86d7 2235 }
1da177e4
LT		 2236}
2237
b2a0bafa
TI		 2238static void azx_shutdown(struct pci_dev *pci)
2239{
2240 struct snd_card *card = pci_get_drvdata(pci);
2241 struct azx *chip;
2242
2243 if (!card)
2244 return;
2245 chip = card->private_data;
2246 if (chip && chip->running)
2247 azx_stop_chip(chip);
2248}
2249
1da177e4 2250/* PCI IDs */
6f51f6cf 2251static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2252 /* CPT */
9477c58e 2253 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2254 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2255 /* PBG */
9477c58e 2256 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2257 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2258 /* Panther Point */
9477c58e 2259 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2260 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2261 /* Lynx Point */
2262 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2263 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2264 /* 9 Series */
2265 { PCI_DEVICE(0x8086, 0x8ca0),
2266 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2267 /* Wellsburg */
2268 { PCI_DEVICE(0x8086, 0x8d20),
2269 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2270 { PCI_DEVICE(0x8086, 0x8d21),
2271 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2272 /* Lewisburg */
2273 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2274 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2275 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2276 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2277 /* Lynx Point-LP */
2278 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2279 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2280 /* Lynx Point-LP */
2281 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2282 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2283 /* Wildcat Point-LP */
2284 { PCI_DEVICE(0x8086, 0x9ca0),
2285 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2286 /* Sunrise Point */
2287 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2288 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2289 /* Sunrise Point-LP */
2290 { PCI_DEVICE(0x8086, 0x9d70),
3e9ad24b 2291 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2292 /* Kabylake */
2293 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2294 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2295 /* Kabylake-LP */
2296 { PCI_DEVICE(0x8086, 0x9d71),
3e9ad24b 2297 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2298 /* Kabylake-H */
2299 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2300 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2301 /* Coffelake */
2302 { PCI_DEVICE(0x8086, 0xa348),
3e9ad24b 2303 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2304 /* Cannonlake */
2305 { PCI_DEVICE(0x8086, 0x9dc8),
3e9ad24b 2306 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d4c2ccdb
PLB		 2307 /* CometLake-LP */
2308 { PCI_DEVICE(0x8086, 0x02C8),
2309 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2310 /* CometLake-H */
2311 { PCI_DEVICE(0x8086, 0x06C8),
2312 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
491f8331
GS		 2313 /* Icelake */
2314 { PCI_DEVICE(0x8086, 0x34c8),
3e9ad24b 2315 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
f94287b6
LPS		 2316 /* Elkhart Lake */
2317 { PCI_DEVICE(0x8086, 0x4b55),
2318 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2319 /* Broxton-P(Apollolake) */
2320 { PCI_DEVICE(0x8086, 0x5a98),
3e9ad24b 2321 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2322 /* Broxton-T */
2323 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2324 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2325 /* Gemini-Lake */
2326 { PCI_DEVICE(0x8086, 0x3198),
3e9ad24b 2327 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2328 /* Haswell */
4a7c516b 2329 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2330 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2331 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2332 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2333 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2334 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2335 /* Broadwell */
2336 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2337 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2338 /* 5 Series/3400 */
2339 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2340 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2341 /* Poulsbo */
9477c58e 2342 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2343 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2344 /* Oaktrail */
09904b95 2345 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2346 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2347 /* BayTrail */
2348 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2349 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2350 /* Braswell */
2351 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2352 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2353 /* ICH6 */
8b0bd226 2354 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2355 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2356 /* ICH7 */
8b0bd226 2357 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2358 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2359 /* ESB2 */
8b0bd226 2360 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2361 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2362 /* ICH8 */
8b0bd226 2363 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2364 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2365 /* ICH9 */
8b0bd226 2366 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2367 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2368 /* ICH9 */
8b0bd226 2369 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2370 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2371 /* ICH10 */
8b0bd226 2372 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2373 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2374 /* ICH10 */
8b0bd226 2375 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2376 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2377 /* Generic Intel */
2378 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2379 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2380 .class_mask = 0xffffff,
103884a3 2381 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2382 /* ATI SB 450/600/700/800/900 */
2383 { PCI_DEVICE(0x1002, 0x437b),
2384 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2385 { PCI_DEVICE(0x1002, 0x4383),
2386 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2387 /* AMD Hudson */
2388 { PCI_DEVICE(0x1022, 0x780d),
2389 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3deef52c
KHF		 2390 /* AMD Stoney */
2391 { PCI_DEVICE(0x1022, 0x157a),
2392 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2393 AZX_DCAPS_PM_RUNTIME },
9ceace3c
VM		 2394 /* AMD Raven */
2395 { PCI_DEVICE(0x1022, 0x15e3),
1adca4b0
KHF		 2396 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2397 AZX_DCAPS_PM_RUNTIME },
87218e9c 2398 /* ATI HDMI */
fd48331f
MSB		 2399 { PCI_DEVICE(0x1002, 0x0002),
2400 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2401 { PCI_DEVICE(0x1002, 0x1308),
2402 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2403 { PCI_DEVICE(0x1002, 0x157a),
2404 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2405 { PCI_DEVICE(0x1002, 0x15b3),
2406 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2407 { PCI_DEVICE(0x1002, 0x793b),
2408 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2409 { PCI_DEVICE(0x1002, 0x7919),
2410 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2411 { PCI_DEVICE(0x1002, 0x960f),
2412 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2413 { PCI_DEVICE(0x1002, 0x970f),
2414 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2415 { PCI_DEVICE(0x1002, 0x9840),
2416 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2417 { PCI_DEVICE(0x1002, 0xaa00),
2418 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2419 { PCI_DEVICE(0x1002, 0xaa08),
2420 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2421 { PCI_DEVICE(0x1002, 0xaa10),
2422 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2423 { PCI_DEVICE(0x1002, 0xaa18),
2424 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2425 { PCI_DEVICE(0x1002, 0xaa20),
2426 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2427 { PCI_DEVICE(0x1002, 0xaa28),
2428 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2429 { PCI_DEVICE(0x1002, 0xaa30),
2430 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2431 { PCI_DEVICE(0x1002, 0xaa38),
2432 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2433 { PCI_DEVICE(0x1002, 0xaa40),
2434 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2435 { PCI_DEVICE(0x1002, 0xaa48),
2436 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2437 { PCI_DEVICE(0x1002, 0xaa50),
2438 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2439 { PCI_DEVICE(0x1002, 0xaa58),
2440 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2441 { PCI_DEVICE(0x1002, 0xaa60),
2442 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2443 { PCI_DEVICE(0x1002, 0xaa68),
2444 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2445 { PCI_DEVICE(0x1002, 0xaa80),
2446 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2447 { PCI_DEVICE(0x1002, 0xaa88),
2448 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2449 { PCI_DEVICE(0x1002, 0xaa90),
2450 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2451 { PCI_DEVICE(0x1002, 0xaa98),
2452 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2453 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2454 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2455 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2456 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2457 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2458 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2459 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2460 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2461 { PCI_DEVICE(0x1002, 0xaac0),
2462 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2463 { PCI_DEVICE(0x1002, 0xaac8),
2464 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2465 { PCI_DEVICE(0x1002, 0xaad8),
2466 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2467 { PCI_DEVICE(0x1002, 0xaae8),
2468 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2469 { PCI_DEVICE(0x1002, 0xaae0),
2470 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2471 { PCI_DEVICE(0x1002, 0xaaf0),
2472 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2473 /* VIA VT8251/VT8237A */
26f05717 2474 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2475 /* VIA GFX VT7122/VX900 */
2476 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2477 /* VIA GFX VT6122/VX11 */
2478 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2479 /* SIS966 */
2480 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2481 /* ULI M5461 */
2482 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2483 /* NVIDIA MCP */
0c2fd1bf
TI		 2484 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2485 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2486 .class_mask = 0xffffff,
9477c58e 2487 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2488 /* Teradici */
9477c58e
TI		 2489 { PCI_DEVICE(0x6549, 0x1200),
2490 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2491 { PCI_DEVICE(0x6549, 0x2200),
2492 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2493 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2494 /* CTHDA chips */
2495 { PCI_DEVICE(0x1102, 0x0010),
2496 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2497 { PCI_DEVICE(0x1102, 0x0012),
2498 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2499#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2500 /* the following entry conflicts with snd-ctxfi driver,
2501 * as ctxfi driver mutates from HD-audio to native mode with
2502 * a special command sequence.
2503 */
4e01f54b
TI		 2504 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2505 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2506 .class_mask = 0xffffff,
9477c58e 2507 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2508 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2509#else
2510 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2511 { PCI_DEVICE(0x1102, 0x0009),
2512 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2513 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2514#endif
c563f473
TI		 2515 /* CM8888 */
2516 { PCI_DEVICE(0x13f6, 0x5011),
2517 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2518 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2519 /* Vortex86MX */
2520 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2521 /* VMware HDAudio */
2522 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2523 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2524 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2525 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2526 .class_mask = 0xffffff,
9477c58e 2527 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2528 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2529 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2530 .class_mask = 0xffffff,
9477c58e 2531 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2532 { 0, }
2533};
2534MODULE_DEVICE_TABLE(pci, azx_ids);
2535
2536/* pci_driver definition */
e9f66d9b 2537static struct pci_driver azx_driver = {
3733e424 2538 .name = KBUILD_MODNAME,
1da177e4
LT		 2539 .id_table = azx_ids,
2540 .probe = azx_probe,
e23e7a14 2541 .remove = azx_remove,
b2a0bafa 2542 .shutdown = azx_shutdown,
68cb2b55
TI		 2543 .driver = {
2544 .pm = AZX_PM_OPS,
2545 },
1da177e4
LT		 2546};
2547
e9f66d9b 2548module_pci_driver(azx_driver);
Linux 6.x block layer and io_uring tree(s)