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spi: sh-msiof: Constify platform_device_id
[linux-2.6-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
9121947d 60#include <linux/vgaarb.h>
a82d51ed 61#include <linux/vga_switcheroo.h>
4918cdab 62#include <linux/firmware.h>
1da177e4 63#include "hda_codec.h"
05e84878 64#include "hda_controller.h"
347de1f8 65#include "hda_intel.h"
1da177e4 66
b6050ef6
TI		 67/* position fix mode */
68enum {
69 POS_FIX_AUTO,
70 POS_FIX_LPIB,
71 POS_FIX_POSBUF,
72 POS_FIX_VIACOMBO,
73 POS_FIX_COMBO,
74};
75
9a34af4a
TI		 76/* Defines for ATI HD Audio support in SB450 south bridge */
77#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
78#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
79
80/* Defines for Nvidia HDA support */
81#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
82#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
83#define NVIDIA_HDA_ISTRM_COH 0x4d
84#define NVIDIA_HDA_OSTRM_COH 0x4c
85#define NVIDIA_HDA_ENABLE_COHBIT 0x01
86
87/* Defines for Intel SCH HDA snoop control */
88#define INTEL_SCH_HDA_DEVC 0x78
89#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90
91/* Define IN stream 0 FIFO size offset in VIA controller */
92#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
93/* Define VIA HD Audio Device ID*/
94#define VIA_HDAC_DEVICE_ID 0x3288
95
33124929
TI		 96/* max number of SDs */
97/* ICH, ATI and VIA have 4 playback and 4 capture */
98#define ICH6_NUM_CAPTURE 4
99#define ICH6_NUM_PLAYBACK 4
100
101/* ULI has 6 playback and 5 capture */
102#define ULI_NUM_CAPTURE 5
103#define ULI_NUM_PLAYBACK 6
104
105/* ATI HDMI may have up to 8 playbacks and 0 capture */
106#define ATIHDMI_NUM_CAPTURE 0
107#define ATIHDMI_NUM_PLAYBACK 8
108
109/* TERA has 4 playback and 3 capture */
110#define TERA_NUM_CAPTURE 3
111#define TERA_NUM_PLAYBACK 4
112
1da177e4 113
5aba4f8e
TI		 114static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
115static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 116static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 117static char *model[SNDRV_CARDS];
1dac6695 118static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 119static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 120static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 121static int probe_only[SNDRV_CARDS];
26a6cb6c 122static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 123static bool single_cmd;
71623855 124static int enable_msi = -1;
4ea6fbc8
TI		 125#ifdef CONFIG_SND_HDA_PATCH_LOADER
126static char *patch[SNDRV_CARDS];
127#endif
2dca0bba 128#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 129static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 130 CONFIG_SND_HDA_INPUT_BEEP_MODE};
131#endif
1da177e4 132
5aba4f8e 133module_param_array(index, int, NULL, 0444);
1da177e4 134MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 135module_param_array(id, charp, NULL, 0444);
1da177e4 136MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 137module_param_array(enable, bool, NULL, 0444);
138MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
139module_param_array(model, charp, NULL, 0444);
1da177e4 140MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 141module_param_array(position_fix, int, NULL, 0444);
4cb36310 142MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 143 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 144module_param_array(bdl_pos_adj, int, NULL, 0644);
145MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 146module_param_array(probe_mask, int, NULL, 0444);
606ad75f 147MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 148module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 149MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 150module_param_array(jackpoll_ms, int, NULL, 0444);
151MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 152module_param(single_cmd, bool, 0444);
d01ce99f
TI		 153MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
154 "(for debugging only).");
ac9ef6cf 155module_param(enable_msi, bint, 0444);
134a11f0 156MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 157#ifdef CONFIG_SND_HDA_PATCH_LOADER
158module_param_array(patch, charp, NULL, 0444);
159MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
160#endif
2dca0bba 161#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 162module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 163MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 164 "(0=off, 1=on) (default=1).");
2dca0bba 165#endif
606ad75f 166
83012a7c 167#ifdef CONFIG_PM
65fcd41d
TI		 168static int param_set_xint(const char *val, const struct kernel_param *kp);
169static struct kernel_param_ops param_ops_xint = {
170 .set = param_set_xint,
171 .get = param_get_int,
172};
173#define param_check_xint param_check_int
174
fee2fba3 175static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 176module_param(power_save, xint, 0644);
fee2fba3
TI		 177MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
178 "(in second, 0 = disable).");
1da177e4 179
dee1b66c
TI		 180/* reset the HD-audio controller in power save mode.
181 * this may give more power-saving, but will take longer time to
182 * wake up.
183 */
8fc24426
TI		 184static bool power_save_controller = 1;
185module_param(power_save_controller, bool, 0644);
dee1b66c 186MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 187#else
bb573928 188#define power_save 0
83012a7c 189#endif /* CONFIG_PM */
dee1b66c 190
7bfe059e
TI		 191static int align_buffer_size = -1;
192module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 193MODULE_PARM_DESC(align_buffer_size,
194 "Force buffer and period sizes to be multiple of 128 bytes.");
195
27fe48d9 196#ifdef CONFIG_X86
7c732015
TI		 197static int hda_snoop = -1;
198module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 199MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 200#else
201#define hda_snoop true
27fe48d9
TI		 202#endif
203
204
1da177e4
LT		 205MODULE_LICENSE("GPL");
206MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
207 "{Intel, ICH6M},"
2f1b3818 208 "{Intel, ICH7},"
f5d40b30 209 "{Intel, ESB2},"
d2981393 210 "{Intel, ICH8},"
f9cc8a8b 211 "{Intel, ICH9},"
c34f5a04 212 "{Intel, ICH10},"
b29c2360 213 "{Intel, PCH},"
d2f2fcd2 214 "{Intel, CPT},"
d2edeb7c 215 "{Intel, PPT},"
8bc039a1 216 "{Intel, LPT},"
144dad99 217 "{Intel, LPT_LP},"
4eeca499 218 "{Intel, WPT_LP},"
c8b00fd2 219 "{Intel, SPT},"
b4565913 220 "{Intel, SPT_LP},"
e926f2c8 221 "{Intel, HPT},"
cea310e8 222 "{Intel, PBG},"
4979bca9 223 "{Intel, SCH},"
fc20a562 224 "{ATI, SB450},"
89be83f8 225 "{ATI, SB600},"
778b6e1b 226 "{ATI, RS600},"
5b15c95f 227 "{ATI, RS690},"
e6db1119
WL		 228 "{ATI, RS780},"
229 "{ATI, R600},"
2797f724
HRK		 230 "{ATI, RV630},"
231 "{ATI, RV610},"
27da1834
WL		 232 "{ATI, RV670},"
233 "{ATI, RV635},"
234 "{ATI, RV620},"
235 "{ATI, RV770},"
fc20a562 236 "{VIA, VT8251},"
47672310 237 "{VIA, VT8237A},"
07e4ca50
TI		 238 "{SiS, SIS966},"
239 "{ULI, M5461}}");
1da177e4
LT		 240MODULE_DESCRIPTION("Intel HDA driver");
241
a82d51ed 242#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 243#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 244#define SUPPORT_VGA_SWITCHEROO
245#endif
246#endif
247
248
1da177e4 249/*
1da177e4 250 */
1da177e4 251
07e4ca50
TI		 252/* driver types */
253enum {
254 AZX_DRIVER_ICH,
32679f95 255 AZX_DRIVER_PCH,
4979bca9 256 AZX_DRIVER_SCH,
fab1285a 257 AZX_DRIVER_HDMI,
07e4ca50 258 AZX_DRIVER_ATI,
778b6e1b 259 AZX_DRIVER_ATIHDMI,
1815b34a 260 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 261 AZX_DRIVER_VIA,
262 AZX_DRIVER_SIS,
263 AZX_DRIVER_ULI,
da3fca21 264 AZX_DRIVER_NVIDIA,
f269002e 265 AZX_DRIVER_TERA,
14d34f16 266 AZX_DRIVER_CTX,
5ae763b1 267 AZX_DRIVER_CTHDA,
c563f473 268 AZX_DRIVER_CMEDIA,
c4da29ca 269 AZX_DRIVER_GENERIC,
2f5983f2 270 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 271};
272
37e661ee
TI		 273#define azx_get_snoop_type(chip) \
274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
275#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
276
b42b4afb
TI		 277/* quirks for old Intel chipsets */
278#define AZX_DCAPS_INTEL_ICH \
103884a3 279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 280
2ea3c6a2 281/* quirks for Intel PCH */
d7dab4db 282#define AZX_DCAPS_INTEL_PCH_NOPM \
103884a3 283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee 284 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db
TI		 285
286#define AZX_DCAPS_INTEL_PCH \
287 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 288
33499a15 289#define AZX_DCAPS_INTEL_HASWELL \
103884a3 290 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 291 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
292 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 293
54a0405d
LY		 294/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
295#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 296 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 297 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
298 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 299
40cc2392
ML		 300#define AZX_DCAPS_INTEL_BAYTRAIL \
301 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
302
2d846c74
LY		 303#define AZX_DCAPS_INTEL_BRASWELL \
304 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
305
d6795827 306#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 307 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
308 AZX_DCAPS_I915_POWERWELL)
d6795827 309
9477c58e
TI		 310/* quirks for ATI SB / AMD Hudson */
311#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 312 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
313 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 314
315/* quirks for ATI/AMD HDMI */
316#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
318 AZX_DCAPS_NO_MSI64)
9477c58e 319
37e661ee
TI		 320/* quirks for ATI HDMI with snoop off */
321#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
322 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
323
9477c58e
TI		 324/* quirks for Nvidia */
325#define AZX_DCAPS_PRESET_NVIDIA \
103884a3 326 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 327 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
328 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 329
5ae763b1 330#define AZX_DCAPS_PRESET_CTHDA \
37e661ee
TI		 331 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 333
a82d51ed
TI		 334/*
335 * VGA-switcher support
336 */
337#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 338#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
339#else
340#define use_vga_switcheroo(chip) 0
341#endif
342
48c8b0eb 343static char *driver_short_names[] = {
07e4ca50 344 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 345 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 346 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 347 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 348 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 349 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 350 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 351 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
352 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 353 [AZX_DRIVER_ULI] = "HDA ULI M5461",
354 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 355 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 356 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 357 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 358 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 359 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 360};
361
27fe48d9 362#ifdef CONFIG_X86
9ddf1aeb 363static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 364{
9ddf1aeb
TI		 365 int pages;
366
27fe48d9
TI		 367 if (azx_snoop(chip))
368 return;
9ddf1aeb
TI		 369 if (!dmab || !dmab->area || !dmab->bytes)
370 return;
371
372#ifdef CONFIG_SND_DMA_SGBUF
373 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
374 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 375 if (chip->driver_type == AZX_DRIVER_CMEDIA)
376 return; /* deal with only CORB/RIRB buffers */
27fe48d9 377 if (on)
9ddf1aeb 378 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 379 else
9ddf1aeb
TI		 380 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
381 return;
27fe48d9 382 }
9ddf1aeb
TI		 383#endif
384
385 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
386 if (on)
387 set_memory_wc((unsigned long)dmab->area, pages);
388 else
389 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 390}
391
392static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
393 bool on)
394{
9ddf1aeb 395 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 396}
397static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 398 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 399{
400 if (azx_dev->wc_marked != on) {
9ddf1aeb 401 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 402 azx_dev->wc_marked = on;
403 }
404}
405#else
406/* NOP for other archs */
407static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
408 bool on)
409{
410}
411static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 412 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 413{
414}
415#endif
416
68e7fffc 417static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 418
cb53c626
TI		 419/*
420 * initialize the PCI registers
421 */
422/* update bits in a PCI register byte */
423static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
424 unsigned char mask, unsigned char val)
425{
426 unsigned char data;
427
428 pci_read_config_byte(pci, reg, &data);
429 data &= ~mask;
430 data |= (val & mask);
431 pci_write_config_byte(pci, reg, data);
432}
433
434static void azx_init_pci(struct azx *chip)
435{
37e661ee
TI		 436 int snoop_type = azx_get_snoop_type(chip);
437
cb53c626
TI		 438 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
439 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
440 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 441 * codecs.
442 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 443 */
46f2cc80 444 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 445 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 446 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 447 }
cb53c626 448
9477c58e
TI		 449 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
450 * we need to enable snoop.
451 */
37e661ee 452 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 453 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
454 azx_snoop(chip));
cb53c626 455 update_pci_byte(chip->pci,
27fe48d9
TI		 456 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
457 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 458 }
459
460 /* For NVIDIA HDA, enable snoop */
37e661ee 461 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 462 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
463 azx_snoop(chip));
cb53c626
TI		 464 update_pci_byte(chip->pci,
465 NVIDIA_HDA_TRANSREG_ADDR,
466 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 467 update_pci_byte(chip->pci,
468 NVIDIA_HDA_ISTRM_COH,
469 0x01, NVIDIA_HDA_ENABLE_COHBIT);
470 update_pci_byte(chip->pci,
471 NVIDIA_HDA_OSTRM_COH,
472 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 473 }
474
475 /* Enable SCH/PCH snoop if needed */
37e661ee 476 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 477 unsigned short snoop;
90a5ad52 478 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 479 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
480 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
481 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
482 if (!azx_snoop(chip))
483 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
484 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 485 pci_read_config_word(chip->pci,
486 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 487 }
4e76a883
TI		 488 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
489 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
490 "Disabled" : "Enabled");
da3fca21 491 }
1da177e4
LT		 492}
493
b6050ef6
TI		 494/* calculate runtime delay from LPIB */
495static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
496 unsigned int pos)
497{
498 struct snd_pcm_substream *substream = azx_dev->substream;
499 int stream = substream->stream;
500 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
501 int delay;
502
503 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
504 delay = pos - lpib_pos;
505 else
506 delay = lpib_pos - pos;
507 if (delay < 0) {
508 if (delay >= azx_dev->delay_negative_threshold)
509 delay = 0;
510 else
511 delay += azx_dev->bufsize;
512 }
513
514 if (delay >= azx_dev->period_bytes) {
515 dev_info(chip->card->dev,
516 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
517 delay, azx_dev->period_bytes);
518 delay = 0;
519 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
520 chip->get_delay[stream] = NULL;
521 }
522
523 return bytes_to_frames(substream->runtime, delay);
524}
525
9ad593f6
TI		 526static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
527
7ca954a8
DR		 528/* called from IRQ */
529static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
530{
9a34af4a 531 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 532 int ok;
533
534 ok = azx_position_ok(chip, azx_dev);
535 if (ok == 1) {
536 azx_dev->irq_pending = 0;
537 return ok;
2f35c630 538 } else if (ok == 0) {
7ca954a8
DR		 539 /* bogus IRQ, process it later */
540 azx_dev->irq_pending = 1;
2f35c630 541 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 542 }
543 return 0;
544}
545
9ad593f6
TI		 546/*
547 * Check whether the current DMA position is acceptable for updating
548 * periods. Returns non-zero if it's OK.
549 *
550 * Many HD-audio controllers appear pretty inaccurate about
551 * the update-IRQ timing. The IRQ is issued before actually the
552 * data is processed. So, we need to process it afterwords in a
553 * workqueue.
554 */
555static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
556{
b6050ef6
TI		 557 struct snd_pcm_substream *substream = azx_dev->substream;
558 int stream = substream->stream;
e5463720 559 u32 wallclk;
9ad593f6
TI		 560 unsigned int pos;
561
f48f606d
JK		 562 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
563 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 564 return -1; /* bogus (too early) interrupt */
fa00e046 565
b6050ef6
TI		 566 if (chip->get_position[stream])
567 pos = chip->get_position[stream](chip, azx_dev);
568 else { /* use the position buffer as default */
569 pos = azx_get_pos_posbuf(chip, azx_dev);
570 if (!pos || pos == (u32)-1) {
571 dev_info(chip->card->dev,
572 "Invalid position buffer, using LPIB read method instead.\n");
573 chip->get_position[stream] = azx_get_pos_lpib;
574 pos = azx_get_pos_lpib(chip, azx_dev);
575 chip->get_delay[stream] = NULL;
576 } else {
577 chip->get_position[stream] = azx_get_pos_posbuf;
578 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
579 chip->get_delay[stream] = azx_get_delay_from_lpib;
580 }
581 }
582
583 if (pos >= azx_dev->bufsize)
584 pos = 0;
9ad593f6 585
d6d8bf54
TI		 586 if (WARN_ONCE(!azx_dev->period_bytes,
587 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 588 return -1; /* this shouldn't happen! */
edb39935 589 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 590 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
591 /* NG - it's below the first next period boundary */
9cdc0115 592 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 593 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 594 return 1; /* OK, it's fine */
595}
596
597/*
598 * The work for pending PCM period updates.
599 */
600static void azx_irq_pending_work(struct work_struct *work)
601{
9a34af4a
TI		 602 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
603 struct azx *chip = &hda->chip;
e5463720 604 int i, pending, ok;
9ad593f6 605
9a34af4a 606 if (!hda->irq_pending_warned) {
4e76a883
TI		 607 dev_info(chip->card->dev,
608 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
609 chip->card->number);
9a34af4a 610 hda->irq_pending_warned = 1;
a6a950a8
TI		 611 }
612
9ad593f6
TI		 613 for (;;) {
614 pending = 0;
615 spin_lock_irq(&chip->reg_lock);
616 for (i = 0; i < chip->num_streams; i++) {
617 struct azx_dev *azx_dev = &chip->azx_dev[i];
618 if (!azx_dev->irq_pending ||
619 !azx_dev->substream ||
620 !azx_dev->running)
621 continue;
e5463720
JK		 622 ok = azx_position_ok(chip, azx_dev);
623 if (ok > 0) {
9ad593f6
TI		 624 azx_dev->irq_pending = 0;
625 spin_unlock(&chip->reg_lock);
626 snd_pcm_period_elapsed(azx_dev->substream);
627 spin_lock(&chip->reg_lock);
e5463720
JK		 628 } else if (ok < 0) {
629 pending = 0; /* too early */
9ad593f6
TI		 630 } else
631 pending++;
632 }
633 spin_unlock_irq(&chip->reg_lock);
634 if (!pending)
635 return;
08af495f 636 msleep(1);
9ad593f6
TI		 637 }
638}
639
640/* clear irq_pending flags and assure no on-going workq */
641static void azx_clear_irq_pending(struct azx *chip)
642{
643 int i;
644
645 spin_lock_irq(&chip->reg_lock);
646 for (i = 0; i < chip->num_streams; i++)
647 chip->azx_dev[i].irq_pending = 0;
648 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 649}
650
68e7fffc
TI		 651static int azx_acquire_irq(struct azx *chip, int do_disconnect)
652{
437a5a46
TI		 653 if (request_irq(chip->pci->irq, azx_interrupt,
654 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 655 KBUILD_MODNAME, chip)) {
4e76a883
TI		 656 dev_err(chip->card->dev,
657 "unable to grab IRQ %d, disabling device\n",
658 chip->pci->irq);
68e7fffc
TI		 659 if (do_disconnect)
660 snd_card_disconnect(chip->card);
661 return -1;
662 }
663 chip->irq = chip->pci->irq;
69e13418 664 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 665 return 0;
666}
667
b6050ef6
TI		 668/* get the current DMA position with correction on VIA chips */
669static unsigned int azx_via_get_position(struct azx *chip,
670 struct azx_dev *azx_dev)
671{
672 unsigned int link_pos, mini_pos, bound_pos;
673 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
674 unsigned int fifo_size;
675
676 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
677 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
678 /* Playback, no problem using link position */
679 return link_pos;
680 }
681
682 /* Capture */
683 /* For new chipset,
684 * use mod to get the DMA position just like old chipset
685 */
686 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
687 mod_dma_pos %= azx_dev->period_bytes;
688
689 /* azx_dev->fifo_size can't get FIFO size of in stream.
690 * Get from base address + offset.
691 */
692 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
693
694 if (azx_dev->insufficient) {
695 /* Link position never gather than FIFO size */
696 if (link_pos <= fifo_size)
697 return 0;
698
699 azx_dev->insufficient = 0;
700 }
701
702 if (link_pos <= fifo_size)
703 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
704 else
705 mini_pos = link_pos - fifo_size;
706
707 /* Find nearest previous boudary */
708 mod_mini_pos = mini_pos % azx_dev->period_bytes;
709 mod_link_pos = link_pos % azx_dev->period_bytes;
710 if (mod_link_pos >= fifo_size)
711 bound_pos = link_pos - mod_link_pos;
712 else if (mod_dma_pos >= mod_mini_pos)
713 bound_pos = mini_pos - mod_mini_pos;
714 else {
715 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
716 if (bound_pos >= azx_dev->bufsize)
717 bound_pos = 0;
718 }
719
720 /* Calculate real DMA position we want */
721 return bound_pos + mod_dma_pos;
722}
723
83012a7c 724#ifdef CONFIG_PM
65fcd41d
TI		 725static DEFINE_MUTEX(card_list_lock);
726static LIST_HEAD(card_list);
727
728static void azx_add_card_list(struct azx *chip)
729{
9a34af4a 730 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 731 mutex_lock(&card_list_lock);
9a34af4a 732 list_add(&hda->list, &card_list);
65fcd41d
TI		 733 mutex_unlock(&card_list_lock);
734}
735
736static void azx_del_card_list(struct azx *chip)
737{
9a34af4a 738 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 739 mutex_lock(&card_list_lock);
9a34af4a 740 list_del_init(&hda->list);
65fcd41d
TI		 741 mutex_unlock(&card_list_lock);
742}
743
744/* trigger power-save check at writing parameter */
745static int param_set_xint(const char *val, const struct kernel_param *kp)
746{
9a34af4a 747 struct hda_intel *hda;
65fcd41d 748 struct azx *chip;
65fcd41d
TI		 749 int prev = power_save;
750 int ret = param_set_int(val, kp);
751
752 if (ret || prev == power_save)
753 return ret;
754
755 mutex_lock(&card_list_lock);
9a34af4a
TI		 756 list_for_each_entry(hda, &card_list, list) {
757 chip = &hda->chip;
65fcd41d
TI		 758 if (!chip->bus || chip->disabled)
759 continue;
bb573928 760 snd_hda_set_power_save(chip->bus, power_save * 1000);
65fcd41d
TI		 761 }
762 mutex_unlock(&card_list_lock);
763 return 0;
764}
765#else
766#define azx_add_card_list(chip) /* NOP */
767#define azx_del_card_list(chip) /* NOP */
83012a7c 768#endif /* CONFIG_PM */
5c0b9bec 769
7ccbde57 770#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 771/*
772 * power management
773 */
68cb2b55 774static int azx_suspend(struct device *dev)
1da177e4 775{
68cb2b55 776 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 777 struct azx *chip;
778 struct hda_intel *hda;
1da177e4 779
2d9772ef
TI		 780 if (!card)
781 return 0;
782
783 chip = card->private_data;
784 hda = container_of(chip, struct hda_intel, chip);
1618e84a 785 if (chip->disabled || hda->init_failed)
c5c21523
TI		 786 return 0;
787
421a1252 788 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 789 azx_clear_irq_pending(chip);
cb53c626 790 azx_stop_chip(chip);
7295b264 791 azx_enter_link_reset(chip);
30b35399 792 if (chip->irq >= 0) {
43001c95 793 free_irq(chip->irq, chip);
30b35399
TI		 794 chip->irq = -1;
795 }
a07187c9 796
68e7fffc 797 if (chip->msi)
43001c95 798 pci_disable_msi(chip->pci);
99a2008d 799 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
926981ae 800 hda_display_power(hda, false);
1da177e4
LT		 801 return 0;
802}
803
68cb2b55 804static int azx_resume(struct device *dev)
1da177e4 805{
68cb2b55
TI		 806 struct pci_dev *pci = to_pci_dev(dev);
807 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 808 struct azx *chip;
809 struct hda_intel *hda;
810
811 if (!card)
812 return 0;
1da177e4 813
2d9772ef
TI		 814 chip = card->private_data;
815 hda = container_of(chip, struct hda_intel, chip);
1618e84a 816 if (chip->disabled || hda->init_failed)
c5c21523
TI		 817 return 0;
818
a07187c9 819 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
926981ae
ID		 820 hda_display_power(hda, true);
821 haswell_set_bclk(hda);
a07187c9 822 }
68e7fffc
TI		 823 if (chip->msi)
824 if (pci_enable_msi(pci) < 0)
825 chip->msi = 0;
826 if (azx_acquire_irq(chip, 1) < 0)
30b35399 827 return -EIO;
cb53c626 828 azx_init_pci(chip);
d804ad92 829
17c3ad03 830 azx_init_chip(chip, true);
d804ad92 831
421a1252 832 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 833 return 0;
834}
b8dfc462
ML		 835#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
836
641d334b 837#ifdef CONFIG_PM
b8dfc462
ML		 838static int azx_runtime_suspend(struct device *dev)
839{
840 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 841 struct azx *chip;
842 struct hda_intel *hda;
b8dfc462 843
2d9772ef
TI		 844 if (!card)
845 return 0;
846
847 chip = card->private_data;
848 hda = container_of(chip, struct hda_intel, chip);
1618e84a 849 if (chip->disabled || hda->init_failed)
246efa4a
DA		 850 return 0;
851
364aa716 852 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 853 return 0;
854
7d4f606c
WX		 855 /* enable controller wake up event */
856 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
857 STATESTS_INT_MASK);
858
b8dfc462 859 azx_stop_chip(chip);
873ce8ad 860 azx_enter_link_reset(chip);
b8dfc462 861 azx_clear_irq_pending(chip);
e4d9e513 862 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
926981ae 863 hda_display_power(hda, false);
e4d9e513 864
b8dfc462
ML		 865 return 0;
866}
867
868static int azx_runtime_resume(struct device *dev)
869{
870 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 871 struct azx *chip;
872 struct hda_intel *hda;
7d4f606c
WX		 873 struct hda_bus *bus;
874 struct hda_codec *codec;
875 int status;
b8dfc462 876
2d9772ef
TI		 877 if (!card)
878 return 0;
879
880 chip = card->private_data;
881 hda = container_of(chip, struct hda_intel, chip);
1618e84a 882 if (chip->disabled || hda->init_failed)
246efa4a
DA		 883 return 0;
884
364aa716 885 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 886 return 0;
887
a07187c9 888 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
926981ae
ID		 889 hda_display_power(hda, true);
890 haswell_set_bclk(hda);
a07187c9 891 }
7d4f606c
WX		 892
893 /* Read STATESTS before controller reset */
894 status = azx_readw(chip, STATESTS);
895
b8dfc462 896 azx_init_pci(chip);
17c3ad03 897 azx_init_chip(chip, true);
7d4f606c
WX		 898
899 bus = chip->bus;
900 if (status && bus) {
d068ebc2 901 list_for_each_codec(codec, bus)
7d4f606c 902 if (status & (1 << codec->addr))
2f35c630
TI		 903 schedule_delayed_work(&codec->jackpoll_work,
904 codec->jackpoll_interval);
7d4f606c
WX		 905 }
906
907 /* disable controller Wake Up event*/
908 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
909 ~STATESTS_INT_MASK);
910
b8dfc462
ML		 911 return 0;
912}
6eb827d2
TI		 913
914static int azx_runtime_idle(struct device *dev)
915{
916 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 917 struct azx *chip;
918 struct hda_intel *hda;
919
920 if (!card)
921 return 0;
6eb827d2 922
2d9772ef
TI		 923 chip = card->private_data;
924 hda = container_of(chip, struct hda_intel, chip);
1618e84a 925 if (chip->disabled || hda->init_failed)
246efa4a
DA		 926 return 0;
927
55ed9cd1 928 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
d068ebc2 929 chip->bus->core.codec_powered)
6eb827d2
TI		 930 return -EBUSY;
931
932 return 0;
933}
934
b8dfc462
ML		 935static const struct dev_pm_ops azx_pm = {
936 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 937 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 938};
939
68cb2b55
TI		 940#define AZX_PM_OPS &azx_pm
941#else
68cb2b55 942#define AZX_PM_OPS NULL
b8dfc462 943#endif /* CONFIG_PM */
1da177e4
LT		 944
945
48c8b0eb 946static int azx_probe_continue(struct azx *chip);
a82d51ed 947
8393ec4a 948#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 949static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 950
a82d51ed
TI		 951static void azx_vs_set_state(struct pci_dev *pci,
952 enum vga_switcheroo_state state)
953{
954 struct snd_card *card = pci_get_drvdata(pci);
955 struct azx *chip = card->private_data;
9a34af4a 956 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 957 bool disabled;
958
9a34af4a
TI		 959 wait_for_completion(&hda->probe_wait);
960 if (hda->init_failed)
a82d51ed
TI		 961 return;
962
963 disabled = (state == VGA_SWITCHEROO_OFF);
964 if (chip->disabled == disabled)
965 return;
966
967 if (!chip->bus) {
968 chip->disabled = disabled;
969 if (!disabled) {
4e76a883
TI		 970 dev_info(chip->card->dev,
971 "Start delayed initialization\n");
5c90680e 972 if (azx_probe_continue(chip) < 0) {
4e76a883 973 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 974 hda->init_failed = true;
a82d51ed
TI		 975 }
976 }
977 } else {
4e76a883
TI		 978 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
979 disabled ? "Disabling" : "Enabling");
a82d51ed 980 if (disabled) {
8928756d
DR		 981 pm_runtime_put_sync_suspend(card->dev);
982 azx_suspend(card->dev);
246efa4a
DA		 983 /* when we get suspended by vga switcheroo we end up in D3cold,
984 * however we have no ACPI handle, so pci/acpi can't put us there,
985 * put ourselves there */
986 pci->current_state = PCI_D3cold;
a82d51ed 987 chip->disabled = true;
128960a9 988 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 989 dev_warn(chip->card->dev,
990 "Cannot lock devices!\n");
a82d51ed
TI		 991 } else {
992 snd_hda_unlock_devices(chip->bus);
8928756d 993 pm_runtime_get_noresume(card->dev);
a82d51ed 994 chip->disabled = false;
8928756d 995 azx_resume(card->dev);
a82d51ed
TI		 996 }
997 }
998}
999
1000static bool azx_vs_can_switch(struct pci_dev *pci)
1001{
1002 struct snd_card *card = pci_get_drvdata(pci);
1003 struct azx *chip = card->private_data;
9a34af4a 1004 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1005
9a34af4a
TI		 1006 wait_for_completion(&hda->probe_wait);
1007 if (hda->init_failed)
a82d51ed
TI		 1008 return false;
1009 if (chip->disabled || !chip->bus)
1010 return true;
1011 if (snd_hda_lock_devices(chip->bus))
1012 return false;
1013 snd_hda_unlock_devices(chip->bus);
1014 return true;
1015}
1016
e23e7a14 1017static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1018{
9a34af4a 1019 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1020 struct pci_dev *p = get_bound_vga(chip->pci);
1021 if (p) {
4e76a883
TI		 1022 dev_info(chip->card->dev,
1023 "Handle VGA-switcheroo audio client\n");
9a34af4a 1024 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1025 pci_dev_put(p);
1026 }
1027}
1028
1029static const struct vga_switcheroo_client_ops azx_vs_ops = {
1030 .set_gpu_state = azx_vs_set_state,
1031 .can_switch = azx_vs_can_switch,
1032};
1033
e23e7a14 1034static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1035{
9a34af4a 1036 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1037 int err;
1038
9a34af4a 1039 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1040 return 0;
1041 /* FIXME: currently only handling DIS controller
1042 * is there any machine with two switchable HDMI audio controllers?
1043 */
128960a9 1044 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 1045 VGA_SWITCHEROO_DIS,
1046 chip->bus != NULL);
128960a9
TI		 1047 if (err < 0)
1048 return err;
9a34af4a 1049 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1050
1051 /* register as an optimus hdmi audio power domain */
8928756d 1052 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1053 &hda->hdmi_pm_domain);
128960a9 1054 return 0;
a82d51ed
TI		 1055}
1056#else
1057#define init_vga_switcheroo(chip) /* NOP */
1058#define register_vga_switcheroo(chip) 0
8393ec4a 1059#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1060#endif /* SUPPORT_VGA_SWITCHER */
1061
1da177e4
LT		 1062/*
1063 * destructor
1064 */
a98f90fd 1065static int azx_free(struct azx *chip)
1da177e4 1066{
c67e2228 1067 struct pci_dev *pci = chip->pci;
a07187c9 1068 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4ce107b9
TI		 1069 int i;
1070
364aa716 1071 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1072 pm_runtime_get_noresume(&pci->dev);
1073
65fcd41d
TI		 1074 azx_del_card_list(chip);
1075
9a34af4a
TI		 1076 hda->init_failed = 1; /* to be sure */
1077 complete_all(&hda->probe_wait);
f4c482a4 1078
9a34af4a 1079 if (use_vga_switcheroo(hda)) {
a82d51ed
TI		 1080 if (chip->disabled && chip->bus)
1081 snd_hda_unlock_devices(chip->bus);
9a34af4a 1082 if (hda->vga_switcheroo_registered)
128960a9 1083 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1084 }
1085
ce43fbae 1086 if (chip->initialized) {
9ad593f6 1087 azx_clear_irq_pending(chip);
07e4ca50 1088 for (i = 0; i < chip->num_streams; i++)
1da177e4 1089 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1090 azx_stop_chip(chip);
1da177e4
LT		 1091 }
1092
f000fd80 1093 if (chip->irq >= 0)
1da177e4 1094 free_irq(chip->irq, (void*)chip);
68e7fffc 1095 if (chip->msi)
30b35399 1096 pci_disable_msi(chip->pci);
ff6defa6 1097 iounmap(chip->remap_addr);
1da177e4 1098
67908994 1099 azx_free_stream_pages(chip);
a82d51ed
TI		 1100 if (chip->region_requested)
1101 pci_release_regions(chip->pci);
1da177e4 1102 pci_disable_device(chip->pci);
07e4ca50 1103 kfree(chip->azx_dev);
4918cdab 1104#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1105 release_firmware(chip->fw);
4918cdab 1106#endif
99a2008d 1107 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
926981ae
ID		 1108 hda_display_power(hda, false);
1109 hda_i915_exit(hda);
99a2008d 1110 }
a07187c9 1111 kfree(hda);
1da177e4
LT		 1112
1113 return 0;
1114}
1115
a98f90fd 1116static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1117{
1118 return azx_free(device->device_data);
1119}
1120
8393ec4a 1121#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1122/*
1123 * Check of disabled HDMI controller by vga-switcheroo
1124 */
e23e7a14 1125static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1126{
1127 struct pci_dev *p;
1128
1129 /* check only discrete GPU */
1130 switch (pci->vendor) {
1131 case PCI_VENDOR_ID_ATI:
1132 case PCI_VENDOR_ID_AMD:
1133 case PCI_VENDOR_ID_NVIDIA:
1134 if (pci->devfn == 1) {
1135 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1136 pci->bus->number, 0);
1137 if (p) {
1138 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1139 return p;
1140 pci_dev_put(p);
1141 }
1142 }
1143 break;
1144 }
1145 return NULL;
1146}
1147
e23e7a14 1148static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1149{
1150 bool vga_inactive = false;
1151 struct pci_dev *p = get_bound_vga(pci);
1152
1153 if (p) {
12b78a7f 1154 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1155 vga_inactive = true;
1156 pci_dev_put(p);
1157 }
1158 return vga_inactive;
1159}
8393ec4a 1160#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1161
3372a153
TI		 1162/*
1163 * white/black-listing for position_fix
1164 */
e23e7a14 1165static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1166 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1167 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1168 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1169 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1170 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1171 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1172 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1173 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1174 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1175 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1176 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1177 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1178 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1179 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1180 {}
1181};
1182
e23e7a14 1183static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1184{
1185 const struct snd_pci_quirk *q;
1186
c673ba1c 1187 switch (fix) {
1dac6695 1188 case POS_FIX_AUTO:
c673ba1c
TI		 1189 case POS_FIX_LPIB:
1190 case POS_FIX_POSBUF:
4cb36310 1191 case POS_FIX_VIACOMBO:
a6f2fd55 1192 case POS_FIX_COMBO:
c673ba1c
TI		 1193 return fix;
1194 }
1195
c673ba1c
TI		 1196 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1197 if (q) {
4e76a883
TI		 1198 dev_info(chip->card->dev,
1199 "position_fix set to %d for device %04x:%04x\n",
1200 q->value, q->subvendor, q->subdevice);
c673ba1c 1201 return q->value;
3372a153 1202 }
bdd9ef24
DH		 1203
1204 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1205 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1206 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1207 return POS_FIX_VIACOMBO;
9477c58e
TI		 1208 }
1209 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1210 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1211 return POS_FIX_LPIB;
bdd9ef24 1212 }
c673ba1c 1213 return POS_FIX_AUTO;
3372a153
TI		 1214}
1215
b6050ef6
TI		 1216static void assign_position_fix(struct azx *chip, int fix)
1217{
1218 static azx_get_pos_callback_t callbacks[] = {
1219 [POS_FIX_AUTO] = NULL,
1220 [POS_FIX_LPIB] = azx_get_pos_lpib,
1221 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1222 [POS_FIX_VIACOMBO] = azx_via_get_position,
1223 [POS_FIX_COMBO] = azx_get_pos_lpib,
1224 };
1225
1226 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1227
1228 /* combo mode uses LPIB only for playback */
1229 if (fix == POS_FIX_COMBO)
1230 chip->get_position[1] = NULL;
1231
1232 if (fix == POS_FIX_POSBUF &&
1233 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1234 chip->get_delay[0] = chip->get_delay[1] =
1235 azx_get_delay_from_lpib;
1236 }
1237
1238}
1239
669ba27a
TI		 1240/*
1241 * black-lists for probe_mask
1242 */
e23e7a14 1243static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1244 /* Thinkpad often breaks the controller communication when accessing
1245 * to the non-working (or non-existing) modem codec slot.
1246 */
1247 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1248 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1249 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1250 /* broken BIOS */
1251 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1252 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1253 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1254 /* forced codec slots */
93574844 1255 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1256 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1257 /* WinFast VP200 H (Teradici) user reported broken communication */
1258 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1259 {}
1260};
1261
f1eaaeec
TI		 1262#define AZX_FORCE_CODEC_MASK 0x100
1263
e23e7a14 1264static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1265{
1266 const struct snd_pci_quirk *q;
1267
f1eaaeec
TI		 1268 chip->codec_probe_mask = probe_mask[dev];
1269 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1270 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1271 if (q) {
4e76a883
TI		 1272 dev_info(chip->card->dev,
1273 "probe_mask set to 0x%x for device %04x:%04x\n",
1274 q->value, q->subvendor, q->subdevice);
f1eaaeec 1275 chip->codec_probe_mask = q->value;
669ba27a
TI		 1276 }
1277 }
f1eaaeec
TI		 1278
1279 /* check forced option */
1280 if (chip->codec_probe_mask != -1 &&
1281 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1282 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1283 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1284 chip->codec_mask);
f1eaaeec 1285 }
669ba27a
TI		 1286}
1287
4d8e22e0 1288/*
71623855 1289 * white/black-list for enable_msi
4d8e22e0 1290 */
e23e7a14 1291static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1292 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1293 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1294 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1295 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1296 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1297 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1298 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1299 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1300 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1301 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1302 {}
1303};
1304
e23e7a14 1305static void check_msi(struct azx *chip)
4d8e22e0
TI		 1306{
1307 const struct snd_pci_quirk *q;
1308
71623855
TI		 1309 if (enable_msi >= 0) {
1310 chip->msi = !!enable_msi;
4d8e22e0 1311 return;
71623855
TI		 1312 }
1313 chip->msi = 1; /* enable MSI as default */
1314 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1315 if (q) {
4e76a883
TI		 1316 dev_info(chip->card->dev,
1317 "msi for device %04x:%04x set to %d\n",
1318 q->subvendor, q->subdevice, q->value);
4d8e22e0 1319 chip->msi = q->value;
80c43ed7
TI		 1320 return;
1321 }
1322
1323 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1324 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1325 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1326 chip->msi = 0;
4d8e22e0
TI		 1327 }
1328}
1329
a1585d76 1330/* check the snoop mode availability */
e23e7a14 1331static void azx_check_snoop_available(struct azx *chip)
a1585d76 1332{
7c732015 1333 int snoop = hda_snoop;
a1585d76 1334
7c732015
TI		 1335 if (snoop >= 0) {
1336 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1337 snoop ? "snoop" : "non-snoop");
1338 chip->snoop = snoop;
1339 return;
1340 }
1341
1342 snoop = true;
37e661ee
TI		 1343 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1344 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1345 /* force to non-snoop mode for a new VIA controller
1346 * when BIOS is set
1347 */
7c732015
TI		 1348 u8 val;
1349 pci_read_config_byte(chip->pci, 0x42, &val);
1350 if (!(val & 0x80) && chip->pci->revision == 0x30)
1351 snoop = false;
a1585d76
TI		 1352 }
1353
37e661ee
TI		 1354 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1355 snoop = false;
1356
7c732015
TI		 1357 chip->snoop = snoop;
1358 if (!snoop)
1359 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1360}
669ba27a 1361
99a2008d
WX		 1362static void azx_probe_work(struct work_struct *work)
1363{
9a34af4a
TI		 1364 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1365 azx_probe_continue(&hda->chip);
99a2008d 1366}
99a2008d 1367
1da177e4
LT		 1368/*
1369 * constructor
1370 */
e23e7a14
BP		 1371static int azx_create(struct snd_card *card, struct pci_dev *pci,
1372 int dev, unsigned int driver_caps,
40830813 1373 const struct hda_controller_ops *hda_ops,
e23e7a14 1374 struct azx **rchip)
1da177e4 1375{
a98f90fd 1376 static struct snd_device_ops ops = {
1da177e4
LT		 1377 .dev_free = azx_dev_free,
1378 };
a07187c9 1379 struct hda_intel *hda;
a82d51ed
TI		 1380 struct azx *chip;
1381 int err;
1da177e4
LT		 1382
1383 *rchip = NULL;
bcd72003 1384
927fc866
PM		 1385 err = pci_enable_device(pci);
1386 if (err < 0)
1da177e4
LT		 1387 return err;
1388
a07187c9
ML		 1389 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1390 if (!hda) {
1da177e4
LT		 1391 pci_disable_device(pci);
1392 return -ENOMEM;
1393 }
1394
a07187c9 1395 chip = &hda->chip;
1da177e4 1396 spin_lock_init(&chip->reg_lock);
62932df8 1397 mutex_init(&chip->open_mutex);
1da177e4
LT		 1398 chip->card = card;
1399 chip->pci = pci;
40830813 1400 chip->ops = hda_ops;
1da177e4 1401 chip->irq = -1;
9477c58e
TI		 1402 chip->driver_caps = driver_caps;
1403 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1404 check_msi(chip);
555e219f 1405 chip->dev_index = dev;
749ee287 1406 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1407 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1408 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1409 INIT_LIST_HEAD(&hda->list);
a82d51ed 1410 init_vga_switcheroo(chip);
9a34af4a 1411 init_completion(&hda->probe_wait);
1da177e4 1412
b6050ef6 1413 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1414
5aba4f8e 1415 check_probe_mask(chip, dev);
3372a153 1416
27346166 1417 chip->single_cmd = single_cmd;
a1585d76 1418 azx_check_snoop_available(chip);
c74db86b 1419
5c0d7bc1
TI		 1420 if (bdl_pos_adj[dev] < 0) {
1421 switch (chip->driver_type) {
0c6341ac 1422 case AZX_DRIVER_ICH:
32679f95 1423 case AZX_DRIVER_PCH:
0c6341ac 1424 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1425 break;
1426 default:
0c6341ac 1427 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1428 break;
1429 }
1430 }
9cdc0115 1431 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1432
a82d51ed
TI		 1433 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1434 if (err < 0) {
4e76a883 1435 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1436 azx_free(chip);
1437 return err;
1438 }
1439
99a2008d 1440 /* continue probing in work context as may trigger request module */
9a34af4a 1441 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1442
a82d51ed 1443 *rchip = chip;
99a2008d 1444
a82d51ed
TI		 1445 return 0;
1446}
1447
48c8b0eb 1448static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1449{
1450 int dev = chip->dev_index;
1451 struct pci_dev *pci = chip->pci;
1452 struct snd_card *card = chip->card;
67908994 1453 int err;
a82d51ed 1454 unsigned short gcap;
413cbf46 1455 unsigned int dma_bits = 64;
a82d51ed 1456
07e4ca50
TI		 1457#if BITS_PER_LONG != 64
1458 /* Fix up base address on ULI M5461 */
1459 if (chip->driver_type == AZX_DRIVER_ULI) {
1460 u16 tmp3;
1461 pci_read_config_word(pci, 0x40, &tmp3);
1462 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1463 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1464 }
1465#endif
1466
927fc866 1467 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1468 if (err < 0)
1da177e4 1469 return err;
a82d51ed 1470 chip->region_requested = 1;
1da177e4 1471
927fc866 1472 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1473 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1474 if (chip->remap_addr == NULL) {
4e76a883 1475 dev_err(card->dev, "ioremap error\n");
a82d51ed 1476 return -ENXIO;
1da177e4
LT		 1477 }
1478
db79afa1
BH		 1479 if (chip->msi) {
1480 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1481 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1482 pci->no_64bit_msi = true;
1483 }
68e7fffc
TI		 1484 if (pci_enable_msi(pci) < 0)
1485 chip->msi = 0;
db79afa1 1486 }
7376d013 1487
a82d51ed
TI		 1488 if (azx_acquire_irq(chip, 0) < 0)
1489 return -EBUSY;
1da177e4
LT		 1490
1491 pci_set_master(pci);
1492 synchronize_irq(chip->irq);
1493
bcd72003 1494 gcap = azx_readw(chip, GCAP);
4e76a883 1495 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1496
413cbf46
TI		 1497 /* AMD devices support 40 or 48bit DMA, take the safe one */
1498 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1499 dma_bits = 40;
1500
dc4c2e6b 1501 /* disable SB600 64bit support for safety */
9477c58e 1502 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1503 struct pci_dev *p_smbus;
413cbf46 1504 dma_bits = 40;
dc4c2e6b
AB		 1505 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1506 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1507 NULL);
1508 if (p_smbus) {
1509 if (p_smbus->revision < 0x30)
fb1d8ac2 1510 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1511 pci_dev_put(p_smbus);
1512 }
1513 }
09240cf4 1514
9477c58e
TI		 1515 /* disable 64bit DMA address on some devices */
1516 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1517 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1518 gcap &= ~AZX_GCAP_64OK;
9477c58e 1519 }
396087ea 1520
2ae66c26 1521 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1522 if (align_buffer_size >= 0)
1523 chip->align_buffer_size = !!align_buffer_size;
1524 else {
103884a3 1525 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1526 chip->align_buffer_size = 0;
7bfe059e
TI		 1527 else
1528 chip->align_buffer_size = 1;
1529 }
2ae66c26 1530
cf7aaca8 1531 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1532 if (!(gcap & AZX_GCAP_64OK))
1533 dma_bits = 32;
1534 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1535 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1536 } else {
e930438c
YH		 1537 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1538 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1539 }
cf7aaca8 1540
8b6ed8e7
TI		 1541 /* read number of streams from GCAP register instead of using
1542 * hardcoded value
1543 */
1544 chip->capture_streams = (gcap >> 8) & 0x0f;
1545 chip->playback_streams = (gcap >> 12) & 0x0f;
1546 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1547 /* gcap didn't give any info, switching to old method */
1548
1549 switch (chip->driver_type) {
1550 case AZX_DRIVER_ULI:
1551 chip->playback_streams = ULI_NUM_PLAYBACK;
1552 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1553 break;
1554 case AZX_DRIVER_ATIHDMI:
1815b34a 1555 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1556 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1557 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1558 break;
c4da29ca 1559 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1560 default:
1561 chip->playback_streams = ICH6_NUM_PLAYBACK;
1562 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1563 break;
1564 }
07e4ca50 1565 }
8b6ed8e7
TI		 1566 chip->capture_index_offset = 0;
1567 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1568 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1569 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1570 GFP_KERNEL);
f4de8fe6 1571 if (!chip->azx_dev)
a82d51ed 1572 return -ENOMEM;
07e4ca50 1573
67908994 1574 err = azx_alloc_stream_pages(chip);
81740861 1575 if (err < 0)
a82d51ed 1576 return err;
1da177e4
LT		 1577
1578 /* initialize streams */
1579 azx_init_stream(chip);
1580
1581 /* initialize chip */
cb53c626 1582 azx_init_pci(chip);
e4d9e513 1583
926981ae
ID		 1584 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1585 struct hda_intel *hda;
1586
1587 hda = container_of(chip, struct hda_intel, chip);
1588 haswell_set_bclk(hda);
1589 }
e4d9e513 1590
10e77dda 1591 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1592
1593 /* codec detection */
927fc866 1594 if (!chip->codec_mask) {
4e76a883 1595 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1596 return -ENODEV;
1da177e4
LT		 1597 }
1598
07e4ca50 1599 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1600 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1601 sizeof(card->shortname));
1602 snprintf(card->longname, sizeof(card->longname),
1603 "%s at 0x%lx irq %i",
1604 card->shortname, chip->addr, chip->irq);
07e4ca50 1605
1da177e4 1606 return 0;
1da177e4
LT		 1607}
1608
97c6a3d1 1609#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1610/* callback from request_firmware_nowait() */
1611static void azx_firmware_cb(const struct firmware *fw, void *context)
1612{
1613 struct snd_card *card = context;
1614 struct azx *chip = card->private_data;
1615 struct pci_dev *pci = chip->pci;
1616
1617 if (!fw) {
4e76a883 1618 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1619 goto error;
1620 }
1621
1622 chip->fw = fw;
1623 if (!chip->disabled) {
1624 /* continue probing */
1625 if (azx_probe_continue(chip))
1626 goto error;
1627 }
1628 return; /* OK */
1629
1630 error:
1631 snd_card_free(card);
1632 pci_set_drvdata(pci, NULL);
1633}
97c6a3d1 1634#endif
5cb543db 1635
40830813
DR		 1636/*
1637 * HDA controller ops.
1638 */
1639
1640/* PCI register access. */
db291e36 1641static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1642{
1643 writel(value, addr);
1644}
1645
db291e36 1646static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1647{
1648 return readl(addr);
1649}
1650
db291e36 1651static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1652{
1653 writew(value, addr);
1654}
1655
db291e36 1656static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1657{
1658 return readw(addr);
1659}
1660
db291e36 1661static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1662{
1663 writeb(value, addr);
1664}
1665
db291e36 1666static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1667{
1668 return readb(addr);
1669}
1670
f46ea609
DR		 1671static int disable_msi_reset_irq(struct azx *chip)
1672{
1673 int err;
1674
1675 free_irq(chip->irq, chip);
1676 chip->irq = -1;
1677 pci_disable_msi(chip->pci);
1678 chip->msi = 0;
1679 err = azx_acquire_irq(chip, 1);
1680 if (err < 0)
1681 return err;
1682
1683 return 0;
1684}
1685
b419b35b
DR		 1686/* DMA page allocation helpers. */
1687static int dma_alloc_pages(struct azx *chip,
1688 int type,
1689 size_t size,
1690 struct snd_dma_buffer *buf)
1691{
1692 int err;
1693
1694 err = snd_dma_alloc_pages(type,
1695 chip->card->dev,
1696 size, buf);
1697 if (err < 0)
1698 return err;
1699 mark_pages_wc(chip, buf, true);
1700 return 0;
1701}
1702
1703static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1704{
1705 mark_pages_wc(chip, buf, false);
1706 snd_dma_free_pages(buf);
1707}
1708
1709static int substream_alloc_pages(struct azx *chip,
1710 struct snd_pcm_substream *substream,
1711 size_t size)
1712{
1713 struct azx_dev *azx_dev = get_azx_dev(substream);
1714 int ret;
1715
1716 mark_runtime_wc(chip, azx_dev, substream, false);
1717 azx_dev->bufsize = 0;
1718 azx_dev->period_bytes = 0;
1719 azx_dev->format_val = 0;
1720 ret = snd_pcm_lib_malloc_pages(substream, size);
1721 if (ret < 0)
1722 return ret;
1723 mark_runtime_wc(chip, azx_dev, substream, true);
1724 return 0;
1725}
1726
1727static int substream_free_pages(struct azx *chip,
1728 struct snd_pcm_substream *substream)
1729{
1730 struct azx_dev *azx_dev = get_azx_dev(substream);
1731 mark_runtime_wc(chip, azx_dev, substream, false);
1732 return snd_pcm_lib_free_pages(substream);
1733}
1734
8769b278
DR		 1735static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1736 struct vm_area_struct *area)
1737{
1738#ifdef CONFIG_X86
1739 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1740 struct azx *chip = apcm->chip;
3b70bdba 1741 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1742 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1743#endif
1744}
1745
40830813 1746static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1747 .reg_writel = pci_azx_writel,
1748 .reg_readl = pci_azx_readl,
1749 .reg_writew = pci_azx_writew,
1750 .reg_readw = pci_azx_readw,
1751 .reg_writeb = pci_azx_writeb,
1752 .reg_readb = pci_azx_readb,
f46ea609 1753 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1754 .dma_alloc_pages = dma_alloc_pages,
1755 .dma_free_pages = dma_free_pages,
1756 .substream_alloc_pages = substream_alloc_pages,
1757 .substream_free_pages = substream_free_pages,
8769b278 1758 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1759 .position_check = azx_position_check,
40830813
DR		 1760};
1761
e23e7a14
BP		 1762static int azx_probe(struct pci_dev *pci,
1763 const struct pci_device_id *pci_id)
1da177e4 1764{
5aba4f8e 1765 static int dev;
a98f90fd 1766 struct snd_card *card;
9a34af4a 1767 struct hda_intel *hda;
a98f90fd 1768 struct azx *chip;
aad730d0 1769 bool schedule_probe;
927fc866 1770 int err;
1da177e4 1771
5aba4f8e
TI		 1772 if (dev >= SNDRV_CARDS)
1773 return -ENODEV;
1774 if (!enable[dev]) {
1775 dev++;
1776 return -ENOENT;
1777 }
1778
60c5772b
TI		 1779 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1780 0, &card);
e58de7ba 1781 if (err < 0) {
4e76a883 1782 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1783 return err;
1da177e4
LT		 1784 }
1785
40830813
DR		 1786 err = azx_create(card, pci, dev, pci_id->driver_data,
1787 &pci_hda_ops, &chip);
41dda0fd
WF		 1788 if (err < 0)
1789 goto out_free;
421a1252 1790 card->private_data = chip;
9a34af4a 1791 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1792
1793 pci_set_drvdata(pci, card);
1794
1795 err = register_vga_switcheroo(chip);
1796 if (err < 0) {
4e76a883 1797 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1798 goto out_free;
1799 }
1800
1801 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1802 dev_info(card->dev, "VGA controller is disabled\n");
1803 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1804 chip->disabled = true;
1805 }
1806
aad730d0 1807 schedule_probe = !chip->disabled;
1da177e4 1808
4918cdab
TI		 1809#ifdef CONFIG_SND_HDA_PATCH_LOADER
1810 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1811 dev_info(card->dev, "Applying patch firmware '%s'\n",
1812 patch[dev]);
5cb543db
TI		 1813 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1814 &pci->dev, GFP_KERNEL, card,
1815 azx_firmware_cb);
4918cdab
TI		 1816 if (err < 0)
1817 goto out_free;
aad730d0 1818 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1819 }
1820#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1821
aad730d0
TI		 1822#ifndef CONFIG_SND_HDA_I915
1823 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1824 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1825#endif
99a2008d 1826
aad730d0 1827 if (schedule_probe)
9a34af4a 1828 schedule_work(&hda->probe_work);
a82d51ed 1829
a82d51ed 1830 dev++;
88d071fc 1831 if (chip->disabled)
9a34af4a 1832 complete_all(&hda->probe_wait);
a82d51ed
TI		 1833 return 0;
1834
1835out_free:
1836 snd_card_free(card);
1837 return err;
1838}
1839
e62a42ae
DR		 1840/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1841static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1842 [AZX_DRIVER_NVIDIA] = 8,
1843 [AZX_DRIVER_TERA] = 1,
1844};
1845
48c8b0eb 1846static int azx_probe_continue(struct azx *chip)
a82d51ed 1847{
9a34af4a 1848 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
c67e2228 1849 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1850 int dev = chip->dev_index;
1851 int err;
1852
99a2008d
WX		 1853 /* Request power well for Haswell HDA controller and codec */
1854 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1855#ifdef CONFIG_SND_HDA_I915
926981ae 1856 err = hda_i915_init(hda);
d7055bd6 1857 if (err < 0)
99a2008d 1858 goto out_free;
926981ae 1859 err = hda_display_power(hda, true);
74b0c2d7
TI		 1860 if (err < 0) {
1861 dev_err(chip->card->dev,
1862 "Cannot turn on display power on i915\n");
1863 goto out_free;
1864 }
c841ad2a 1865#endif
99a2008d
WX		 1866 }
1867
5c90680e
TI		 1868 err = azx_first_init(chip);
1869 if (err < 0)
1870 goto out_free;
1871
2dca0bba
JK		 1872#ifdef CONFIG_SND_HDA_INPUT_BEEP
1873 chip->beep_mode = beep_mode[dev];
1874#endif
1875
1da177e4 1876 /* create codec instances */
bb573928 1877 err = azx_bus_create(chip, model[dev]);
96d2bd6e
TI		 1878 if (err < 0)
1879 goto out_free;
e62a42ae 1880
96d2bd6e 1881 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 1882 if (err < 0)
1883 goto out_free;
96d2bd6e 1884
4ea6fbc8 1885#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1886 if (chip->fw) {
1887 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1888 chip->fw->data);
4ea6fbc8
TI		 1889 if (err < 0)
1890 goto out_free;
e39ae856 1891#ifndef CONFIG_PM
4918cdab
TI		 1892 release_firmware(chip->fw); /* no longer needed */
1893 chip->fw = NULL;
e39ae856 1894#endif
4ea6fbc8
TI		 1895 }
1896#endif
10e77dda 1897 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1898 err = azx_codec_configure(chip);
1899 if (err < 0)
1900 goto out_free;
1901 }
1da177e4 1902
a82d51ed 1903 err = snd_card_register(chip->card);
41dda0fd
WF		 1904 if (err < 0)
1905 goto out_free;
1da177e4 1906
cb53c626 1907 chip->running = 1;
65fcd41d 1908 azx_add_card_list(chip);
bb573928 1909 snd_hda_set_power_save(chip->bus, power_save * 1000);
364aa716 1910 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
c67e2228 1911 pm_runtime_put_noidle(&pci->dev);
1da177e4 1912
41dda0fd 1913out_free:
88d071fc 1914 if (err < 0)
9a34af4a
TI		 1915 hda->init_failed = 1;
1916 complete_all(&hda->probe_wait);
41dda0fd 1917 return err;
1da177e4
LT		 1918}
1919
e23e7a14 1920static void azx_remove(struct pci_dev *pci)
1da177e4 1921{
9121947d 1922 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1923
9121947d
TI		 1924 if (card)
1925 snd_card_free(card);
1da177e4
LT		 1926}
1927
b2a0bafa
TI		 1928static void azx_shutdown(struct pci_dev *pci)
1929{
1930 struct snd_card *card = pci_get_drvdata(pci);
1931 struct azx *chip;
1932
1933 if (!card)
1934 return;
1935 chip = card->private_data;
1936 if (chip && chip->running)
1937 azx_stop_chip(chip);
1938}
1939
1da177e4 1940/* PCI IDs */
6f51f6cf 1941static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1942 /* CPT */
9477c58e 1943 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1944 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1945 /* PBG */
9477c58e 1946 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1947 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1948 /* Panther Point */
9477c58e 1949 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 1950 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 1951 /* Lynx Point */
1952 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1953 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 1954 /* 9 Series */
1955 { PCI_DEVICE(0x8086, 0x8ca0),
1956 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1957 /* Wellsburg */
1958 { PCI_DEVICE(0x8086, 0x8d20),
1959 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1960 { PCI_DEVICE(0x8086, 0x8d21),
1961 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1962 /* Lynx Point-LP */
1963 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1964 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1965 /* Lynx Point-LP */
1966 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 1967 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 1968 /* Wildcat Point-LP */
1969 { PCI_DEVICE(0x8086, 0x9ca0),
1970 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 1971 /* Sunrise Point */
1972 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 1973 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 1974 /* Sunrise Point-LP */
1975 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 1976 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
e926f2c8 1977 /* Haswell */
4a7c516b 1978 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 1979 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 1980 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 1981 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 1982 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 1983 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 1984 /* Broadwell */
1985 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 1986 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 1987 /* 5 Series/3400 */
1988 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 1989 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 1990 /* Poulsbo */
9477c58e 1991 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 1992 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1993 /* Oaktrail */
09904b95 1994 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 1995 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 1996 /* BayTrail */
1997 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 1998 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 1999 /* Braswell */
2000 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2001 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2002 /* ICH6 */
8b0bd226 2003 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2004 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2005 /* ICH7 */
8b0bd226 2006 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2007 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2008 /* ESB2 */
8b0bd226 2009 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2010 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2011 /* ICH8 */
8b0bd226 2012 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2013 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2014 /* ICH9 */
8b0bd226 2015 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2016 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2017 /* ICH9 */
8b0bd226 2018 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2019 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2020 /* ICH10 */
8b0bd226 2021 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2022 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2023 /* ICH10 */
8b0bd226 2024 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2025 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2026 /* Generic Intel */
2027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2028 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2029 .class_mask = 0xffffff,
103884a3 2030 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2031 /* ATI SB 450/600/700/800/900 */
2032 { PCI_DEVICE(0x1002, 0x437b),
2033 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2034 { PCI_DEVICE(0x1002, 0x4383),
2035 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2036 /* AMD Hudson */
2037 { PCI_DEVICE(0x1022, 0x780d),
2038 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2039 /* ATI HDMI */
9477c58e
TI		 2040 { PCI_DEVICE(0x1002, 0x793b),
2041 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2042 { PCI_DEVICE(0x1002, 0x7919),
2043 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2044 { PCI_DEVICE(0x1002, 0x960f),
2045 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2046 { PCI_DEVICE(0x1002, 0x970f),
2047 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2048 { PCI_DEVICE(0x1002, 0xaa00),
2049 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2050 { PCI_DEVICE(0x1002, 0xaa08),
2051 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2052 { PCI_DEVICE(0x1002, 0xaa10),
2053 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2054 { PCI_DEVICE(0x1002, 0xaa18),
2055 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2056 { PCI_DEVICE(0x1002, 0xaa20),
2057 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2058 { PCI_DEVICE(0x1002, 0xaa28),
2059 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2060 { PCI_DEVICE(0x1002, 0xaa30),
2061 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2062 { PCI_DEVICE(0x1002, 0xaa38),
2063 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2064 { PCI_DEVICE(0x1002, 0xaa40),
2065 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2066 { PCI_DEVICE(0x1002, 0xaa48),
2067 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2068 { PCI_DEVICE(0x1002, 0xaa50),
2069 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2070 { PCI_DEVICE(0x1002, 0xaa58),
2071 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2072 { PCI_DEVICE(0x1002, 0xaa60),
2073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2074 { PCI_DEVICE(0x1002, 0xaa68),
2075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2076 { PCI_DEVICE(0x1002, 0xaa80),
2077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2078 { PCI_DEVICE(0x1002, 0xaa88),
2079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2080 { PCI_DEVICE(0x1002, 0xaa90),
2081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2082 { PCI_DEVICE(0x1002, 0xaa98),
2083 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2084 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2085 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2086 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2087 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2088 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2089 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2090 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2091 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2092 /* VIA VT8251/VT8237A */
9477c58e
TI		 2093 { PCI_DEVICE(0x1106, 0x3288),
2094 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2095 /* VIA GFX VT7122/VX900 */
2096 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2097 /* VIA GFX VT6122/VX11 */
2098 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2099 /* SIS966 */
2100 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2101 /* ULI M5461 */
2102 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2103 /* NVIDIA MCP */
0c2fd1bf
TI		 2104 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2105 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2106 .class_mask = 0xffffff,
9477c58e 2107 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2108 /* Teradici */
9477c58e
TI		 2109 { PCI_DEVICE(0x6549, 0x1200),
2110 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2111 { PCI_DEVICE(0x6549, 0x2200),
2112 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2113 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2114 /* CTHDA chips */
2115 { PCI_DEVICE(0x1102, 0x0010),
2116 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2117 { PCI_DEVICE(0x1102, 0x0012),
2118 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2119#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2120 /* the following entry conflicts with snd-ctxfi driver,
2121 * as ctxfi driver mutates from HD-audio to native mode with
2122 * a special command sequence.
2123 */
4e01f54b
TI		 2124 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2125 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2126 .class_mask = 0xffffff,
9477c58e 2127 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2128 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2129#else
2130 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2131 { PCI_DEVICE(0x1102, 0x0009),
2132 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2133 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2134#endif
c563f473
TI		 2135 /* CM8888 */
2136 { PCI_DEVICE(0x13f6, 0x5011),
2137 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2138 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2139 /* Vortex86MX */
2140 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2141 /* VMware HDAudio */
2142 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2143 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2144 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2145 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2146 .class_mask = 0xffffff,
9477c58e 2147 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2148 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2149 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2150 .class_mask = 0xffffff,
9477c58e 2151 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2152 { 0, }
2153};
2154MODULE_DEVICE_TABLE(pci, azx_ids);
2155
2156/* pci_driver definition */
e9f66d9b 2157static struct pci_driver azx_driver = {
3733e424 2158 .name = KBUILD_MODNAME,
1da177e4
LT		 2159 .id_table = azx_ids,
2160 .probe = azx_probe,
e23e7a14 2161 .remove = azx_remove,
b2a0bafa 2162 .shutdown = azx_shutdown,
68cb2b55
TI		 2163 .driver = {
2164 .pm = AZX_PM_OPS,
2165 },
1da177e4
LT		 2166};
2167
e9f66d9b 2168module_pci_driver(azx_driver);
Linux 6.x block layer and io_uring tree(s)