Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
05e84878 DR |
2 | /* |
3 | * | |
4 | * Implementation of primary alsa driver code base for Intel HD Audio. | |
5 | * | |
6 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
7 | * | |
8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
9 | * PeiSen Hou <pshou@realtek.com.tw> | |
05e84878 DR |
10 | */ |
11 | ||
12 | #include <linux/clocksource.h> | |
13 | #include <linux/delay.h> | |
f0b1df88 | 14 | #include <linux/interrupt.h> |
05e84878 DR |
15 | #include <linux/kernel.h> |
16 | #include <linux/module.h> | |
154867cf | 17 | #include <linux/pm_runtime.h> |
05e84878 | 18 | #include <linux/slab.h> |
bfcba288 GS |
19 | |
20 | #ifdef CONFIG_X86 | |
21 | /* for art-tsc conversion */ | |
22 | #include <asm/tsc.h> | |
23 | #endif | |
24 | ||
05e84878 DR |
25 | #include <sound/core.h> |
26 | #include <sound/initval.h> | |
05e84878 DR |
27 | #include "hda_controller.h" |
28 | ||
43db4a59 | 29 | #define CREATE_TRACE_POINTS |
18486508 | 30 | #include "hda_controller_trace.h" |
43db4a59 | 31 | |
2b5fd6c2 | 32 | /* DSP lock helpers */ |
7833c3f8 TI |
33 | #define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev)) |
34 | #define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev)) | |
35 | #define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev)) | |
2b5fd6c2 | 36 | |
05e84878 DR |
37 | /* assign a stream for the PCM */ |
38 | static inline struct azx_dev * | |
39 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) | |
40 | { | |
7833c3f8 TI |
41 | struct hdac_stream *s; |
42 | ||
43 | s = snd_hdac_stream_assign(azx_bus(chip), substream); | |
44 | if (!s) | |
45 | return NULL; | |
46 | return stream_to_azx_dev(s); | |
05e84878 DR |
47 | } |
48 | ||
49 | /* release the assigned stream */ | |
50 | static inline void azx_release_device(struct azx_dev *azx_dev) | |
51 | { | |
7833c3f8 | 52 | snd_hdac_stream_release(azx_stream(azx_dev)); |
05e84878 DR |
53 | } |
54 | ||
820cc6cf TI |
55 | static inline struct hda_pcm_stream * |
56 | to_hda_pcm_stream(struct snd_pcm_substream *substream) | |
57 | { | |
58 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
59 | return &apcm->info->stream[substream->stream]; | |
60 | } | |
61 | ||
05e84878 DR |
62 | static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, |
63 | u64 nsec) | |
64 | { | |
65 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
820cc6cf | 66 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
67 | u64 codec_frames, codec_nsecs; |
68 | ||
69 | if (!hinfo->ops.get_delay) | |
70 | return nsec; | |
71 | ||
72 | codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); | |
73 | codec_nsecs = div_u64(codec_frames * 1000000000LL, | |
74 | substream->runtime->rate); | |
75 | ||
76 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
77 | return nsec + codec_nsecs; | |
78 | ||
79 | return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; | |
80 | } | |
81 | ||
05e84878 DR |
82 | /* |
83 | * PCM ops | |
84 | */ | |
85 | ||
86 | static int azx_pcm_close(struct snd_pcm_substream *substream) | |
87 | { | |
88 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
820cc6cf | 89 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
90 | struct azx *chip = apcm->chip; |
91 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
05e84878 | 92 | |
18486508 | 93 | trace_azx_pcm_close(chip, azx_dev); |
05e84878 | 94 | mutex_lock(&chip->open_mutex); |
05e84878 | 95 | azx_release_device(azx_dev); |
61ca4107 TI |
96 | if (hinfo->ops.close) |
97 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
05e84878 DR |
98 | snd_hda_power_down(apcm->codec); |
99 | mutex_unlock(&chip->open_mutex); | |
9a6246ff | 100 | snd_hda_codec_pcm_put(apcm->info); |
05e84878 DR |
101 | return 0; |
102 | } | |
103 | ||
104 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, | |
105 | struct snd_pcm_hw_params *hw_params) | |
106 | { | |
107 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
108 | struct azx *chip = apcm->chip; | |
602518a2 | 109 | struct azx_dev *azx_dev = get_azx_dev(substream); |
7a6d4a5a | 110 | int ret = 0; |
05e84878 | 111 | |
18486508 | 112 | trace_azx_pcm_hw_params(chip, azx_dev); |
602518a2 TI |
113 | dsp_lock(azx_dev); |
114 | if (dsp_is_locked(azx_dev)) { | |
05e84878 DR |
115 | ret = -EBUSY; |
116 | goto unlock; | |
117 | } | |
118 | ||
602518a2 TI |
119 | azx_dev->core.bufsize = 0; |
120 | azx_dev->core.period_bytes = 0; | |
121 | azx_dev->core.format_val = 0; | |
193c7e14 | 122 | |
05e84878 | 123 | unlock: |
602518a2 | 124 | dsp_unlock(azx_dev); |
05e84878 DR |
125 | return ret; |
126 | } | |
127 | ||
128 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) | |
129 | { | |
130 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
131 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
820cc6cf | 132 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
133 | |
134 | /* reset BDL address */ | |
135 | dsp_lock(azx_dev); | |
ccc98865 TI |
136 | if (!dsp_is_locked(azx_dev)) |
137 | snd_hdac_stream_cleanup(azx_stream(azx_dev)); | |
05e84878 DR |
138 | |
139 | snd_hda_codec_cleanup(apcm->codec, hinfo, substream); | |
140 | ||
6d23c8f5 | 141 | azx_stream(azx_dev)->prepared = 0; |
05e84878 | 142 | dsp_unlock(azx_dev); |
7a6d4a5a | 143 | return 0; |
05e84878 DR |
144 | } |
145 | ||
146 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) | |
147 | { | |
148 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
149 | struct azx *chip = apcm->chip; | |
150 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
820cc6cf | 151 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 | 152 | struct snd_pcm_runtime *runtime = substream->runtime; |
0dd76f36 | 153 | unsigned int format_val, stream_tag; |
05e84878 DR |
154 | int err; |
155 | struct hda_spdif_out *spdif = | |
156 | snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); | |
157 | unsigned short ctls = spdif ? spdif->ctls : 0; | |
158 | ||
18486508 | 159 | trace_azx_pcm_prepare(chip, azx_dev); |
05e84878 DR |
160 | dsp_lock(azx_dev); |
161 | if (dsp_is_locked(azx_dev)) { | |
162 | err = -EBUSY; | |
163 | goto unlock; | |
164 | } | |
165 | ||
7833c3f8 | 166 | snd_hdac_stream_reset(azx_stream(azx_dev)); |
b7d023e1 | 167 | format_val = snd_hdac_calc_stream_format(runtime->rate, |
05e84878 DR |
168 | runtime->channels, |
169 | runtime->format, | |
170 | hinfo->maxbps, | |
171 | ctls); | |
172 | if (!format_val) { | |
173 | dev_err(chip->card->dev, | |
174 | "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
175 | runtime->rate, runtime->channels, runtime->format); | |
176 | err = -EINVAL; | |
177 | goto unlock; | |
178 | } | |
179 | ||
0dd76f36 TI |
180 | err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val); |
181 | if (err < 0) | |
182 | goto unlock; | |
05e84878 | 183 | |
ccc98865 | 184 | snd_hdac_stream_setup(azx_stream(azx_dev)); |
05e84878 | 185 | |
7833c3f8 | 186 | stream_tag = azx_dev->core.stream_tag; |
05e84878 DR |
187 | /* CA-IBG chips need the playback stream starting from 1 */ |
188 | if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && | |
189 | stream_tag > chip->capture_streams) | |
190 | stream_tag -= chip->capture_streams; | |
191 | err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, | |
7833c3f8 | 192 | azx_dev->core.format_val, substream); |
05e84878 DR |
193 | |
194 | unlock: | |
195 | if (!err) | |
6d23c8f5 | 196 | azx_stream(azx_dev)->prepared = 1; |
05e84878 DR |
197 | dsp_unlock(azx_dev); |
198 | return err; | |
199 | } | |
200 | ||
201 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) | |
202 | { | |
203 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
204 | struct azx *chip = apcm->chip; | |
a41d1224 | 205 | struct hdac_bus *bus = azx_bus(chip); |
05e84878 DR |
206 | struct azx_dev *azx_dev; |
207 | struct snd_pcm_substream *s; | |
ccc98865 TI |
208 | struct hdac_stream *hstr; |
209 | bool start; | |
210 | int sbits = 0; | |
211 | int sync_reg; | |
05e84878 DR |
212 | |
213 | azx_dev = get_azx_dev(substream); | |
43db4a59 TI |
214 | trace_azx_pcm_trigger(chip, azx_dev, cmd); |
215 | ||
ccc98865 TI |
216 | hstr = azx_stream(azx_dev); |
217 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | |
218 | sync_reg = AZX_REG_OLD_SSYNC; | |
219 | else | |
220 | sync_reg = AZX_REG_SSYNC; | |
05e84878 | 221 | |
6d23c8f5 | 222 | if (dsp_is_locked(azx_dev) || !hstr->prepared) |
05e84878 DR |
223 | return -EPIPE; |
224 | ||
225 | switch (cmd) { | |
226 | case SNDRV_PCM_TRIGGER_START: | |
05e84878 DR |
227 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
228 | case SNDRV_PCM_TRIGGER_RESUME: | |
ccc98865 | 229 | start = true; |
05e84878 DR |
230 | break; |
231 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
232 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
233 | case SNDRV_PCM_TRIGGER_STOP: | |
ccc98865 | 234 | start = false; |
05e84878 DR |
235 | break; |
236 | default: | |
237 | return -EINVAL; | |
238 | } | |
239 | ||
240 | snd_pcm_group_for_each_entry(s, substream) { | |
241 | if (s->pcm->card != substream->pcm->card) | |
242 | continue; | |
243 | azx_dev = get_azx_dev(s); | |
7833c3f8 | 244 | sbits |= 1 << azx_dev->core.index; |
05e84878 DR |
245 | snd_pcm_trigger_done(s, substream); |
246 | } | |
247 | ||
a41d1224 | 248 | spin_lock(&bus->reg_lock); |
05e84878 DR |
249 | |
250 | /* first, set SYNC bits of corresponding streams */ | |
ccc98865 | 251 | snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg); |
05e84878 DR |
252 | |
253 | snd_pcm_group_for_each_entry(s, substream) { | |
254 | if (s->pcm->card != substream->pcm->card) | |
255 | continue; | |
256 | azx_dev = get_azx_dev(s); | |
257 | if (start) { | |
7833c3f8 TI |
258 | azx_dev->insufficient = 1; |
259 | snd_hdac_stream_start(azx_stream(azx_dev), true); | |
05e84878 | 260 | } else { |
7833c3f8 | 261 | snd_hdac_stream_stop(azx_stream(azx_dev)); |
05e84878 | 262 | } |
05e84878 | 263 | } |
a41d1224 | 264 | spin_unlock(&bus->reg_lock); |
ccc98865 TI |
265 | |
266 | snd_hdac_stream_sync(hstr, start, sbits); | |
267 | ||
a41d1224 | 268 | spin_lock(&bus->reg_lock); |
05e84878 | 269 | /* reset SYNC bits */ |
ccc98865 TI |
270 | snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg); |
271 | if (start) | |
272 | snd_hdac_stream_timecounter_init(hstr, sbits); | |
a41d1224 | 273 | spin_unlock(&bus->reg_lock); |
05e84878 DR |
274 | return 0; |
275 | } | |
276 | ||
b6050ef6 | 277 | unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev) |
05e84878 | 278 | { |
7833c3f8 | 279 | return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); |
b6050ef6 TI |
280 | } |
281 | EXPORT_SYMBOL_GPL(azx_get_pos_lpib); | |
05e84878 | 282 | |
b6050ef6 TI |
283 | unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev) |
284 | { | |
7833c3f8 | 285 | return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev)); |
05e84878 | 286 | } |
b6050ef6 | 287 | EXPORT_SYMBOL_GPL(azx_get_pos_posbuf); |
05e84878 DR |
288 | |
289 | unsigned int azx_get_position(struct azx *chip, | |
b6050ef6 | 290 | struct azx_dev *azx_dev) |
05e84878 | 291 | { |
7833c3f8 | 292 | struct snd_pcm_substream *substream = azx_dev->core.substream; |
05e84878 DR |
293 | unsigned int pos; |
294 | int stream = substream->stream; | |
05e84878 DR |
295 | int delay = 0; |
296 | ||
b6050ef6 TI |
297 | if (chip->get_position[stream]) |
298 | pos = chip->get_position[stream](chip, azx_dev); | |
299 | else /* use the position buffer as default */ | |
300 | pos = azx_get_pos_posbuf(chip, azx_dev); | |
05e84878 | 301 | |
7833c3f8 | 302 | if (pos >= azx_dev->core.bufsize) |
05e84878 DR |
303 | pos = 0; |
304 | ||
05e84878 | 305 | if (substream->runtime) { |
b6050ef6 | 306 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
820cc6cf | 307 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
b6050ef6 TI |
308 | |
309 | if (chip->get_delay[stream]) | |
310 | delay += chip->get_delay[stream](chip, azx_dev, pos); | |
05e84878 DR |
311 | if (hinfo->ops.get_delay) |
312 | delay += hinfo->ops.get_delay(hinfo, apcm->codec, | |
313 | substream); | |
314 | substream->runtime->delay = delay; | |
315 | } | |
316 | ||
43db4a59 | 317 | trace_azx_get_position(chip, azx_dev, pos, delay); |
05e84878 DR |
318 | return pos; |
319 | } | |
320 | EXPORT_SYMBOL_GPL(azx_get_position); | |
321 | ||
322 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | |
323 | { | |
324 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
325 | struct azx *chip = apcm->chip; | |
326 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
327 | return bytes_to_frames(substream->runtime, | |
b6050ef6 | 328 | azx_get_position(chip, azx_dev)); |
05e84878 DR |
329 | } |
330 | ||
bfcba288 GS |
331 | /* |
332 | * azx_scale64: Scale base by mult/div while not overflowing sanely | |
333 | * | |
334 | * Derived from scale64_check_overflow in kernel/time/timekeeping.c | |
335 | * | |
336 | * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which | |
337 | * is about 384307 ie ~4.5 days. | |
338 | * | |
339 | * This scales the calculation so that overflow will happen but after 2^64 / | |
340 | * 48000 secs, which is pretty large! | |
341 | * | |
342 | * In caln below: | |
343 | * base may overflow, but since there isn’t any additional division | |
344 | * performed on base it’s OK | |
345 | * rem can’t overflow because both are 32-bit values | |
346 | */ | |
347 | ||
348 | #ifdef CONFIG_X86 | |
349 | static u64 azx_scale64(u64 base, u32 num, u32 den) | |
350 | { | |
351 | u64 rem; | |
352 | ||
353 | rem = do_div(base, den); | |
354 | ||
355 | base *= num; | |
356 | rem *= num; | |
357 | ||
358 | do_div(rem, den); | |
359 | ||
360 | return base + rem; | |
361 | } | |
362 | ||
363 | static int azx_get_sync_time(ktime_t *device, | |
364 | struct system_counterval_t *system, void *ctx) | |
365 | { | |
366 | struct snd_pcm_substream *substream = ctx; | |
367 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
368 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
369 | struct azx *chip = apcm->chip; | |
370 | struct snd_pcm_runtime *runtime; | |
371 | u64 ll_counter, ll_counter_l, ll_counter_h; | |
372 | u64 tsc_counter, tsc_counter_l, tsc_counter_h; | |
373 | u32 wallclk_ctr, wallclk_cycles; | |
374 | bool direction; | |
375 | u32 dma_select; | |
4dca80b4 | 376 | u32 timeout; |
bfcba288 GS |
377 | u32 retry_count = 0; |
378 | ||
379 | runtime = substream->runtime; | |
380 | ||
381 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
382 | direction = 1; | |
383 | else | |
384 | direction = 0; | |
385 | ||
386 | /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */ | |
387 | do { | |
388 | timeout = 100; | |
389 | dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) | | |
390 | (azx_dev->core.stream_tag - 1); | |
391 | snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select); | |
392 | ||
393 | /* Enable the capture */ | |
394 | snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK); | |
395 | ||
396 | while (timeout) { | |
397 | if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) & | |
398 | GTSCC_TSCCD_MASK) | |
399 | break; | |
400 | ||
401 | timeout--; | |
402 | } | |
403 | ||
404 | if (!timeout) { | |
405 | dev_err(chip->card->dev, "GTSCC capture Timedout!\n"); | |
406 | return -EIO; | |
407 | } | |
408 | ||
409 | /* Read wall clock counter */ | |
410 | wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC); | |
411 | ||
412 | /* Read TSC counter */ | |
413 | tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL); | |
414 | tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU); | |
415 | ||
416 | /* Read Link counter */ | |
417 | ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL); | |
418 | ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU); | |
419 | ||
420 | /* Ack: registers read done */ | |
421 | snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT); | |
422 | ||
423 | tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) | | |
424 | tsc_counter_l; | |
425 | ||
426 | ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l; | |
427 | wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK; | |
428 | ||
429 | /* | |
430 | * An error occurs near frame "rollover". The clocks in | |
431 | * frame value indicates whether this error may have | |
432 | * occurred. Here we use the value of 10 i.e., | |
433 | * HDA_MAX_CYCLE_OFFSET | |
434 | */ | |
435 | if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET | |
436 | && wallclk_cycles > HDA_MAX_CYCLE_OFFSET) | |
437 | break; | |
438 | ||
439 | /* | |
440 | * Sleep before we read again, else we may again get | |
441 | * value near to MAX_CYCLE. Try to sleep for different | |
442 | * amount of time so we dont hit the same number again | |
443 | */ | |
444 | udelay(retry_count++); | |
445 | ||
446 | } while (retry_count != HDA_MAX_CYCLE_READ_RETRY); | |
447 | ||
448 | if (retry_count == HDA_MAX_CYCLE_READ_RETRY) { | |
449 | dev_err_ratelimited(chip->card->dev, | |
450 | "Error in WALFCC cycle count\n"); | |
451 | return -EIO; | |
452 | } | |
453 | ||
454 | *device = ns_to_ktime(azx_scale64(ll_counter, | |
455 | NSEC_PER_SEC, runtime->rate)); | |
456 | *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) / | |
457 | ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate)); | |
458 | ||
459 | *system = convert_art_to_tsc(tsc_counter); | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | #else | |
465 | static int azx_get_sync_time(ktime_t *device, | |
466 | struct system_counterval_t *system, void *ctx) | |
467 | { | |
468 | return -ENXIO; | |
469 | } | |
470 | #endif | |
471 | ||
472 | static int azx_get_crosststamp(struct snd_pcm_substream *substream, | |
473 | struct system_device_crosststamp *xtstamp) | |
474 | { | |
475 | return get_device_system_crosststamp(azx_get_sync_time, | |
476 | substream, NULL, xtstamp); | |
477 | } | |
478 | ||
479 | static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime, | |
480 | struct snd_pcm_audio_tstamp_config *ts) | |
481 | { | |
482 | if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME) | |
483 | if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED) | |
484 | return true; | |
485 | ||
486 | return false; | |
487 | } | |
488 | ||
9e94df3a | 489 | static int azx_get_time_info(struct snd_pcm_substream *substream, |
fcae40c9 | 490 | struct timespec64 *system_ts, struct timespec64 *audio_ts, |
9e94df3a PLB |
491 | struct snd_pcm_audio_tstamp_config *audio_tstamp_config, |
492 | struct snd_pcm_audio_tstamp_report *audio_tstamp_report) | |
05e84878 DR |
493 | { |
494 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
bfcba288 GS |
495 | struct snd_pcm_runtime *runtime = substream->runtime; |
496 | struct system_device_crosststamp xtstamp; | |
497 | int ret; | |
05e84878 DR |
498 | u64 nsec; |
499 | ||
9e94df3a PLB |
500 | if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && |
501 | (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { | |
05e84878 | 502 | |
9e94df3a PLB |
503 | snd_pcm_gettime(substream->runtime, system_ts); |
504 | ||
7833c3f8 | 505 | nsec = timecounter_read(&azx_dev->core.tc); |
9e94df3a PLB |
506 | nsec = div_u64(nsec, 3); /* can be optimized */ |
507 | if (audio_tstamp_config->report_delay) | |
508 | nsec = azx_adjust_codec_delay(substream, nsec); | |
509 | ||
fcae40c9 | 510 | *audio_ts = ns_to_timespec64(nsec); |
9e94df3a PLB |
511 | |
512 | audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; | |
513 | audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */ | |
514 | audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */ | |
515 | ||
bfcba288 GS |
516 | } else if (is_link_time_supported(runtime, audio_tstamp_config)) { |
517 | ||
518 | ret = azx_get_crosststamp(substream, &xtstamp); | |
519 | if (ret) | |
520 | return ret; | |
521 | ||
522 | switch (runtime->tstamp_type) { | |
523 | case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC: | |
524 | return -EINVAL; | |
525 | ||
526 | case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW: | |
fcae40c9 | 527 | *system_ts = ktime_to_timespec64(xtstamp.sys_monoraw); |
bfcba288 GS |
528 | break; |
529 | ||
530 | default: | |
fcae40c9 | 531 | *system_ts = ktime_to_timespec64(xtstamp.sys_realtime); |
bfcba288 GS |
532 | break; |
533 | ||
534 | } | |
535 | ||
fcae40c9 | 536 | *audio_ts = ktime_to_timespec64(xtstamp.device); |
bfcba288 GS |
537 | |
538 | audio_tstamp_report->actual_type = | |
539 | SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED; | |
540 | audio_tstamp_report->accuracy_report = 1; | |
541 | /* 24 MHz WallClock == 42ns resolution */ | |
542 | audio_tstamp_report->accuracy = 42; | |
543 | ||
544 | } else { | |
9e94df3a | 545 | audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; |
bfcba288 | 546 | } |
05e84878 DR |
547 | |
548 | return 0; | |
549 | } | |
550 | ||
c56fc8c9 | 551 | static const struct snd_pcm_hardware azx_pcm_hw = { |
05e84878 DR |
552 | .info = (SNDRV_PCM_INFO_MMAP | |
553 | SNDRV_PCM_INFO_INTERLEAVED | | |
554 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
555 | SNDRV_PCM_INFO_MMAP_VALID | | |
556 | /* No full-resume yet implemented */ | |
557 | /* SNDRV_PCM_INFO_RESUME |*/ | |
558 | SNDRV_PCM_INFO_PAUSE | | |
559 | SNDRV_PCM_INFO_SYNC_START | | |
9e94df3a PLB |
560 | SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ |
561 | SNDRV_PCM_INFO_HAS_LINK_ATIME | | |
05e84878 DR |
562 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), |
563 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
564 | .rates = SNDRV_PCM_RATE_48000, | |
565 | .rate_min = 48000, | |
566 | .rate_max = 48000, | |
567 | .channels_min = 2, | |
568 | .channels_max = 2, | |
569 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
570 | .period_bytes_min = 128, | |
571 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
572 | .periods_min = 2, | |
573 | .periods_max = AZX_MAX_FRAG, | |
574 | .fifo_size = 0, | |
575 | }; | |
576 | ||
577 | static int azx_pcm_open(struct snd_pcm_substream *substream) | |
578 | { | |
579 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
820cc6cf | 580 | struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream); |
05e84878 DR |
581 | struct azx *chip = apcm->chip; |
582 | struct azx_dev *azx_dev; | |
583 | struct snd_pcm_runtime *runtime = substream->runtime; | |
05e84878 DR |
584 | int err; |
585 | int buff_step; | |
586 | ||
9a6246ff | 587 | snd_hda_codec_pcm_get(apcm->info); |
05e84878 DR |
588 | mutex_lock(&chip->open_mutex); |
589 | azx_dev = azx_assign_device(chip, substream); | |
18486508 | 590 | trace_azx_pcm_open(chip, azx_dev); |
05e84878 | 591 | if (azx_dev == NULL) { |
61ca4107 TI |
592 | err = -EBUSY; |
593 | goto unlock; | |
05e84878 | 594 | } |
ccc98865 | 595 | runtime->private_data = azx_dev; |
50279d9b | 596 | |
05e84878 | 597 | runtime->hw = azx_pcm_hw; |
c1c6c877 TI |
598 | if (chip->gts_present) |
599 | runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME; | |
05e84878 DR |
600 | runtime->hw.channels_min = hinfo->channels_min; |
601 | runtime->hw.channels_max = hinfo->channels_max; | |
602 | runtime->hw.formats = hinfo->formats; | |
603 | runtime->hw.rates = hinfo->rates; | |
604 | snd_pcm_limit_hw_rates(runtime); | |
605 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
606 | ||
607 | /* avoid wrap-around with wall-clock */ | |
608 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, | |
609 | 20, | |
610 | 178000000); | |
611 | ||
612 | if (chip->align_buffer_size) | |
613 | /* constrain buffer sizes to be multiple of 128 | |
614 | bytes. This is more efficient in terms of memory | |
615 | access but isn't required by the HDA spec and | |
616 | prevents users from specifying exact period/buffer | |
617 | sizes. For example for 44.1kHz, a period size set | |
618 | to 20ms will be rounded to 19.59ms. */ | |
619 | buff_step = 128; | |
620 | else | |
621 | /* Don't enforce steps on buffer sizes, still need to | |
622 | be multiple of 4 bytes (HDA spec). Tested on Intel | |
623 | HDA controllers, may not work on all devices where | |
624 | option needs to be disabled */ | |
625 | buff_step = 4; | |
626 | ||
627 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, | |
628 | buff_step); | |
629 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
630 | buff_step); | |
cc72da7d | 631 | snd_hda_power_up(apcm->codec); |
61ca4107 TI |
632 | if (hinfo->ops.open) |
633 | err = hinfo->ops.open(hinfo, apcm->codec, substream); | |
634 | else | |
635 | err = -ENODEV; | |
05e84878 DR |
636 | if (err < 0) { |
637 | azx_release_device(azx_dev); | |
61ca4107 | 638 | goto powerdown; |
05e84878 DR |
639 | } |
640 | snd_pcm_limit_hw_rates(runtime); | |
641 | /* sanity check */ | |
642 | if (snd_BUG_ON(!runtime->hw.channels_min) || | |
643 | snd_BUG_ON(!runtime->hw.channels_max) || | |
644 | snd_BUG_ON(!runtime->hw.formats) || | |
645 | snd_BUG_ON(!runtime->hw.rates)) { | |
646 | azx_release_device(azx_dev); | |
61ca4107 TI |
647 | if (hinfo->ops.close) |
648 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
649 | err = -EINVAL; | |
650 | goto powerdown; | |
05e84878 DR |
651 | } |
652 | ||
9e94df3a | 653 | /* disable LINK_ATIME timestamps for capture streams |
05e84878 | 654 | until we figure out how to handle digital inputs */ |
9e94df3a PLB |
655 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
656 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ | |
657 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; | |
658 | } | |
05e84878 | 659 | |
05e84878 DR |
660 | snd_pcm_set_sync(substream); |
661 | mutex_unlock(&chip->open_mutex); | |
662 | return 0; | |
61ca4107 TI |
663 | |
664 | powerdown: | |
665 | snd_hda_power_down(apcm->codec); | |
666 | unlock: | |
667 | mutex_unlock(&chip->open_mutex); | |
9a6246ff | 668 | snd_hda_codec_pcm_put(apcm->info); |
61ca4107 | 669 | return err; |
05e84878 DR |
670 | } |
671 | ||
672 | static int azx_pcm_mmap(struct snd_pcm_substream *substream, | |
673 | struct vm_area_struct *area) | |
674 | { | |
675 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
676 | struct azx *chip = apcm->chip; | |
677 | if (chip->ops->pcm_mmap_prepare) | |
678 | chip->ops->pcm_mmap_prepare(substream, area); | |
679 | return snd_pcm_lib_default_mmap(substream, area); | |
680 | } | |
681 | ||
6769e988 | 682 | static const struct snd_pcm_ops azx_pcm_ops = { |
05e84878 DR |
683 | .open = azx_pcm_open, |
684 | .close = azx_pcm_close, | |
05e84878 DR |
685 | .hw_params = azx_pcm_hw_params, |
686 | .hw_free = azx_pcm_hw_free, | |
687 | .prepare = azx_pcm_prepare, | |
688 | .trigger = azx_pcm_trigger, | |
689 | .pointer = azx_pcm_pointer, | |
9e94df3a | 690 | .get_time_info = azx_get_time_info, |
05e84878 | 691 | .mmap = azx_pcm_mmap, |
05e84878 DR |
692 | }; |
693 | ||
694 | static void azx_pcm_free(struct snd_pcm *pcm) | |
695 | { | |
696 | struct azx_pcm *apcm = pcm->private_data; | |
697 | if (apcm) { | |
698 | list_del(&apcm->list); | |
820cc6cf | 699 | apcm->info->pcm = NULL; |
05e84878 DR |
700 | kfree(apcm); |
701 | } | |
702 | } | |
703 | ||
704 | #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) | |
705 | ||
0a50575b TI |
706 | int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec, |
707 | struct hda_pcm *cpcm) | |
05e84878 | 708 | { |
a41d1224 TI |
709 | struct hdac_bus *bus = &_bus->core; |
710 | struct azx *chip = bus_to_azx(bus); | |
05e84878 DR |
711 | struct snd_pcm *pcm; |
712 | struct azx_pcm *apcm; | |
713 | int pcm_dev = cpcm->device; | |
714 | unsigned int size; | |
715 | int s, err; | |
fc478143 | 716 | int type = SNDRV_DMA_TYPE_DEV_SG; |
05e84878 DR |
717 | |
718 | list_for_each_entry(apcm, &chip->pcm_list, list) { | |
719 | if (apcm->pcm->device == pcm_dev) { | |
720 | dev_err(chip->card->dev, "PCM %d already exists\n", | |
721 | pcm_dev); | |
722 | return -EBUSY; | |
723 | } | |
724 | } | |
725 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
726 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, | |
727 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, | |
728 | &pcm); | |
729 | if (err < 0) | |
730 | return err; | |
75b1a8f9 | 731 | strscpy(pcm->name, cpcm->name, sizeof(pcm->name)); |
05e84878 | 732 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); |
a3aa60d5 BC |
733 | if (apcm == NULL) { |
734 | snd_device_free(chip->card, pcm); | |
05e84878 | 735 | return -ENOMEM; |
a3aa60d5 | 736 | } |
05e84878 DR |
737 | apcm->chip = chip; |
738 | apcm->pcm = pcm; | |
739 | apcm->codec = codec; | |
820cc6cf | 740 | apcm->info = cpcm; |
05e84878 DR |
741 | pcm->private_data = apcm; |
742 | pcm->private_free = azx_pcm_free; | |
743 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) | |
744 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; | |
745 | list_add_tail(&apcm->list, &chip->pcm_list); | |
746 | cpcm->pcm = pcm; | |
747 | for (s = 0; s < 2; s++) { | |
05e84878 DR |
748 | if (cpcm->stream[s].substreams) |
749 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); | |
750 | } | |
751 | /* buffer pre-allocation */ | |
752 | size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; | |
753 | if (size > MAX_PREALLOC_SIZE) | |
754 | size = MAX_PREALLOC_SIZE; | |
fc478143 TI |
755 | if (chip->uc_buffer) |
756 | type = SNDRV_DMA_TYPE_DEV_UC_SG; | |
7a6d4a5a TI |
757 | snd_pcm_set_managed_buffer_all(pcm, type, chip->card->dev, |
758 | size, MAX_PREALLOC_SIZE); | |
05e84878 DR |
759 | return 0; |
760 | } | |
05e84878 | 761 | |
6e85dddc DR |
762 | static unsigned int azx_command_addr(u32 cmd) |
763 | { | |
764 | unsigned int addr = cmd >> 28; | |
765 | ||
766 | if (addr >= AZX_MAX_CODECS) { | |
767 | snd_BUG(); | |
768 | addr = 0; | |
769 | } | |
770 | ||
771 | return addr; | |
772 | } | |
773 | ||
6e85dddc | 774 | /* receive a response */ |
a41d1224 | 775 | static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr, |
cad372f1 | 776 | unsigned int *res) |
6e85dddc | 777 | { |
a41d1224 TI |
778 | struct azx *chip = bus_to_azx(bus); |
779 | struct hda_bus *hbus = &chip->bus; | |
5f2cb361 | 780 | int err; |
6e85dddc DR |
781 | |
782 | again: | |
5f2cb361 TI |
783 | err = snd_hdac_bus_get_response(bus, addr, res); |
784 | if (!err) | |
785 | return 0; | |
88452da9 | 786 | |
a41d1224 | 787 | if (hbus->no_response_fallback) |
cad372f1 | 788 | return -EIO; |
6e85dddc | 789 | |
8af42130 | 790 | if (!bus->polling_mode) { |
6e85dddc DR |
791 | dev_warn(chip->card->dev, |
792 | "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n", | |
a41d1224 | 793 | bus->last_cmd[addr]); |
8af42130 | 794 | bus->polling_mode = 1; |
6e85dddc DR |
795 | goto again; |
796 | } | |
797 | ||
798 | if (chip->msi) { | |
799 | dev_warn(chip->card->dev, | |
800 | "No response from codec, disabling MSI: last cmd=0x%08x\n", | |
a41d1224 TI |
801 | bus->last_cmd[addr]); |
802 | if (chip->ops->disable_msi_reset_irq && | |
cad372f1 TI |
803 | chip->ops->disable_msi_reset_irq(chip) < 0) |
804 | return -EIO; | |
6e85dddc DR |
805 | goto again; |
806 | } | |
807 | ||
808 | if (chip->probing) { | |
809 | /* If this critical timeout happens during the codec probing | |
810 | * phase, this is likely an access to a non-existing codec | |
811 | * slot. Better to return an error and reset the system. | |
812 | */ | |
cad372f1 | 813 | return -EIO; |
6e85dddc DR |
814 | } |
815 | ||
41438f13 TI |
816 | /* no fallback mechanism? */ |
817 | if (!chip->fallback_to_single_cmd) | |
818 | return -EIO; | |
819 | ||
6e85dddc DR |
820 | /* a fatal communication error; need either to reset or to fallback |
821 | * to the single_cmd mode | |
822 | */ | |
a41d1224 TI |
823 | if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) { |
824 | hbus->response_reset = 1; | |
dd65f7e1 TI |
825 | dev_err(chip->card->dev, |
826 | "No response from codec, resetting bus: last cmd=0x%08x\n", | |
827 | bus->last_cmd[addr]); | |
cad372f1 | 828 | return -EAGAIN; /* give a chance to retry */ |
6e85dddc DR |
829 | } |
830 | ||
475feec0 | 831 | dev_err(chip->card->dev, |
6e85dddc | 832 | "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n", |
a41d1224 | 833 | bus->last_cmd[addr]); |
6e85dddc | 834 | chip->single_cmd = 1; |
a41d1224 TI |
835 | hbus->response_reset = 0; |
836 | snd_hdac_bus_stop_cmd_io(bus); | |
cad372f1 | 837 | return -EIO; |
6e85dddc DR |
838 | } |
839 | ||
840 | /* | |
841 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
842 | * | |
843 | * Note: according to Intel, this is not preferred use. The command was | |
844 | * intended for the BIOS only, and may get confused with unsolicited | |
845 | * responses. So, we shouldn't use it for normal operation from the | |
846 | * driver. | |
847 | * I left the codes, however, for debugging/testing purposes. | |
848 | */ | |
849 | ||
850 | /* receive a response */ | |
851 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) | |
852 | { | |
853 | int timeout = 50; | |
854 | ||
855 | while (timeout--) { | |
856 | /* check IRV busy bit */ | |
fb1d8ac2 | 857 | if (azx_readw(chip, IRS) & AZX_IRS_VALID) { |
6e85dddc | 858 | /* reuse rirb.res as the response return value */ |
a41d1224 | 859 | azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR); |
6e85dddc DR |
860 | return 0; |
861 | } | |
862 | udelay(1); | |
863 | } | |
864 | if (printk_ratelimit()) | |
865 | dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", | |
866 | azx_readw(chip, IRS)); | |
a41d1224 | 867 | azx_bus(chip)->rirb.res[addr] = -1; |
6e85dddc DR |
868 | return -EIO; |
869 | } | |
870 | ||
871 | /* send a command */ | |
a41d1224 | 872 | static int azx_single_send_cmd(struct hdac_bus *bus, u32 val) |
6e85dddc | 873 | { |
a41d1224 | 874 | struct azx *chip = bus_to_azx(bus); |
6e85dddc DR |
875 | unsigned int addr = azx_command_addr(val); |
876 | int timeout = 50; | |
877 | ||
a41d1224 | 878 | bus->last_cmd[azx_command_addr(val)] = val; |
6e85dddc DR |
879 | while (timeout--) { |
880 | /* check ICB busy bit */ | |
fb1d8ac2 | 881 | if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) { |
6e85dddc DR |
882 | /* Clear IRV valid bit */ |
883 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | |
fb1d8ac2 | 884 | AZX_IRS_VALID); |
6e85dddc DR |
885 | azx_writel(chip, IC, val); |
886 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | |
fb1d8ac2 | 887 | AZX_IRS_BUSY); |
6e85dddc DR |
888 | return azx_single_wait_for_response(chip, addr); |
889 | } | |
890 | udelay(1); | |
891 | } | |
892 | if (printk_ratelimit()) | |
893 | dev_dbg(chip->card->dev, | |
894 | "send_cmd timeout: IRS=0x%x, val=0x%x\n", | |
895 | azx_readw(chip, IRS), val); | |
896 | return -EIO; | |
897 | } | |
898 | ||
899 | /* receive a response */ | |
a41d1224 | 900 | static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr, |
cad372f1 | 901 | unsigned int *res) |
6e85dddc | 902 | { |
cad372f1 | 903 | if (res) |
a41d1224 | 904 | *res = bus->rirb.res[addr]; |
cad372f1 | 905 | return 0; |
6e85dddc DR |
906 | } |
907 | ||
908 | /* | |
909 | * The below are the main callbacks from hda_codec. | |
910 | * | |
911 | * They are just the skeleton to call sub-callbacks according to the | |
912 | * current setting of chip->single_cmd. | |
913 | */ | |
914 | ||
915 | /* send a command */ | |
a41d1224 | 916 | static int azx_send_cmd(struct hdac_bus *bus, unsigned int val) |
6e85dddc | 917 | { |
a41d1224 | 918 | struct azx *chip = bus_to_azx(bus); |
6e85dddc DR |
919 | |
920 | if (chip->disabled) | |
921 | return 0; | |
6e85dddc DR |
922 | if (chip->single_cmd) |
923 | return azx_single_send_cmd(bus, val); | |
924 | else | |
a41d1224 | 925 | return snd_hdac_bus_send_cmd(bus, val); |
6e85dddc | 926 | } |
6e85dddc DR |
927 | |
928 | /* get a response */ | |
a41d1224 | 929 | static int azx_get_response(struct hdac_bus *bus, unsigned int addr, |
cad372f1 | 930 | unsigned int *res) |
6e85dddc | 931 | { |
a41d1224 TI |
932 | struct azx *chip = bus_to_azx(bus); |
933 | ||
6e85dddc DR |
934 | if (chip->disabled) |
935 | return 0; | |
936 | if (chip->single_cmd) | |
cad372f1 | 937 | return azx_single_get_response(bus, addr, res); |
6e85dddc | 938 | else |
cad372f1 | 939 | return azx_rirb_get_response(bus, addr, res); |
6e85dddc | 940 | } |
6e85dddc | 941 | |
7e8be1b3 TI |
942 | static const struct hdac_bus_ops bus_core_ops = { |
943 | .command = azx_send_cmd, | |
944 | .get_response = azx_get_response, | |
945 | }; | |
946 | ||
2b5fd6c2 DR |
947 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
948 | /* | |
949 | * DSP loading code (e.g. for CA0132) | |
950 | */ | |
951 | ||
952 | /* use the first stream for loading DSP */ | |
953 | static struct azx_dev * | |
954 | azx_get_dsp_loader_dev(struct azx *chip) | |
955 | { | |
7833c3f8 TI |
956 | struct hdac_bus *bus = azx_bus(chip); |
957 | struct hdac_stream *s; | |
958 | ||
959 | list_for_each_entry(s, &bus->stream_list, list) | |
960 | if (s->index == chip->playback_index_offset) | |
961 | return stream_to_azx_dev(s); | |
962 | ||
963 | return NULL; | |
2b5fd6c2 DR |
964 | } |
965 | ||
0a50575b TI |
966 | int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format, |
967 | unsigned int byte_size, | |
968 | struct snd_dma_buffer *bufp) | |
2b5fd6c2 | 969 | { |
0a50575b | 970 | struct hdac_bus *bus = &codec->bus->core; |
a41d1224 | 971 | struct azx *chip = bus_to_azx(bus); |
2b5fd6c2 | 972 | struct azx_dev *azx_dev; |
ccc98865 TI |
973 | struct hdac_stream *hstr; |
974 | bool saved = false; | |
2b5fd6c2 DR |
975 | int err; |
976 | ||
977 | azx_dev = azx_get_dsp_loader_dev(chip); | |
ccc98865 | 978 | hstr = azx_stream(azx_dev); |
a41d1224 | 979 | spin_lock_irq(&bus->reg_lock); |
ccc98865 TI |
980 | if (hstr->opened) { |
981 | chip->saved_azx_dev = *azx_dev; | |
982 | saved = true; | |
2b5fd6c2 | 983 | } |
a41d1224 | 984 | spin_unlock_irq(&bus->reg_lock); |
2b5fd6c2 | 985 | |
ccc98865 TI |
986 | err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp); |
987 | if (err < 0) { | |
a41d1224 | 988 | spin_lock_irq(&bus->reg_lock); |
ccc98865 TI |
989 | if (saved) |
990 | *azx_dev = chip->saved_azx_dev; | |
a41d1224 | 991 | spin_unlock_irq(&bus->reg_lock); |
ccc98865 TI |
992 | return err; |
993 | } | |
2b5fd6c2 | 994 | |
6d23c8f5 | 995 | hstr->prepared = 0; |
2b5fd6c2 DR |
996 | return err; |
997 | } | |
0a50575b | 998 | EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare); |
2b5fd6c2 | 999 | |
0a50575b | 1000 | void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start) |
2b5fd6c2 | 1001 | { |
0a50575b | 1002 | struct hdac_bus *bus = &codec->bus->core; |
a41d1224 | 1003 | struct azx *chip = bus_to_azx(bus); |
2b5fd6c2 DR |
1004 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
1005 | ||
ccc98865 | 1006 | snd_hdac_dsp_trigger(azx_stream(azx_dev), start); |
2b5fd6c2 | 1007 | } |
0a50575b | 1008 | EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger); |
2b5fd6c2 | 1009 | |
0a50575b TI |
1010 | void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec, |
1011 | struct snd_dma_buffer *dmab) | |
2b5fd6c2 | 1012 | { |
0a50575b | 1013 | struct hdac_bus *bus = &codec->bus->core; |
a41d1224 | 1014 | struct azx *chip = bus_to_azx(bus); |
2b5fd6c2 | 1015 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
ccc98865 | 1016 | struct hdac_stream *hstr = azx_stream(azx_dev); |
2b5fd6c2 | 1017 | |
0a50575b | 1018 | if (!dmab->area || !hstr->locked) |
2b5fd6c2 DR |
1019 | return; |
1020 | ||
ccc98865 | 1021 | snd_hdac_dsp_cleanup(hstr, dmab); |
a41d1224 | 1022 | spin_lock_irq(&bus->reg_lock); |
ccc98865 | 1023 | if (hstr->opened) |
2b5fd6c2 | 1024 | *azx_dev = chip->saved_azx_dev; |
ccc98865 | 1025 | hstr->locked = false; |
a41d1224 | 1026 | spin_unlock_irq(&bus->reg_lock); |
2b5fd6c2 | 1027 | } |
0a50575b | 1028 | EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup); |
2b5fd6c2 DR |
1029 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ |
1030 | ||
f43923ff DR |
1031 | /* |
1032 | * reset and start the controller registers | |
1033 | */ | |
17c3ad03 | 1034 | void azx_init_chip(struct azx *chip, bool full_reset) |
f43923ff | 1035 | { |
a41d1224 TI |
1036 | if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) { |
1037 | /* correct RINTCNT for CXT */ | |
1038 | if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) | |
1039 | azx_writew(chip, RINTCNT, 0xc0); | |
1040 | } | |
f43923ff DR |
1041 | } |
1042 | EXPORT_SYMBOL_GPL(azx_init_chip); | |
1043 | ||
7833c3f8 TI |
1044 | void azx_stop_all_streams(struct azx *chip) |
1045 | { | |
1046 | struct hdac_bus *bus = azx_bus(chip); | |
1047 | struct hdac_stream *s; | |
1048 | ||
1049 | list_for_each_entry(s, &bus->stream_list, list) | |
1050 | snd_hdac_stream_stop(s); | |
1051 | } | |
1052 | EXPORT_SYMBOL_GPL(azx_stop_all_streams); | |
1053 | ||
f43923ff DR |
1054 | void azx_stop_chip(struct azx *chip) |
1055 | { | |
a41d1224 | 1056 | snd_hdac_bus_stop_chip(azx_bus(chip)); |
f43923ff | 1057 | } |
154867cf | 1058 | EXPORT_SYMBOL_GPL(azx_stop_chip); |
f43923ff | 1059 | |
f0b1df88 DR |
1060 | /* |
1061 | * interrupt handler | |
1062 | */ | |
7833c3f8 TI |
1063 | static void stream_update(struct hdac_bus *bus, struct hdac_stream *s) |
1064 | { | |
a41d1224 | 1065 | struct azx *chip = bus_to_azx(bus); |
7833c3f8 TI |
1066 | struct azx_dev *azx_dev = stream_to_azx_dev(s); |
1067 | ||
1068 | /* check whether this IRQ is really acceptable */ | |
1069 | if (!chip->ops->position_check || | |
1070 | chip->ops->position_check(chip, azx_dev)) { | |
a41d1224 TI |
1071 | spin_unlock(&bus->reg_lock); |
1072 | snd_pcm_period_elapsed(azx_stream(azx_dev)->substream); | |
1073 | spin_lock(&bus->reg_lock); | |
7833c3f8 TI |
1074 | } |
1075 | } | |
1076 | ||
f0b1df88 DR |
1077 | irqreturn_t azx_interrupt(int irq, void *dev_id) |
1078 | { | |
1079 | struct azx *chip = dev_id; | |
7833c3f8 | 1080 | struct hdac_bus *bus = azx_bus(chip); |
f0b1df88 | 1081 | u32 status; |
473f4145 TI |
1082 | bool active, handled = false; |
1083 | int repeat = 0; /* count for avoiding endless loop */ | |
f0b1df88 | 1084 | |
641d334b | 1085 | #ifdef CONFIG_PM |
364aa716 | 1086 | if (azx_has_pm_runtime(chip)) |
7b0a48f3 | 1087 | if (!pm_runtime_active(chip->card->dev)) |
f0b1df88 DR |
1088 | return IRQ_NONE; |
1089 | #endif | |
1090 | ||
a41d1224 | 1091 | spin_lock(&bus->reg_lock); |
f0b1df88 | 1092 | |
473f4145 TI |
1093 | if (chip->disabled) |
1094 | goto unlock; | |
f0b1df88 | 1095 | |
473f4145 TI |
1096 | do { |
1097 | status = azx_readl(chip, INTSTS); | |
1098 | if (status == 0 || status == 0xffffffff) | |
1099 | break; | |
f0b1df88 | 1100 | |
473f4145 TI |
1101 | handled = true; |
1102 | active = false; | |
1103 | if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update)) | |
1104 | active = true; | |
1105 | ||
473f4145 TI |
1106 | status = azx_readb(chip, RIRBSTS); |
1107 | if (status & RIRB_INT_MASK) { | |
6d011d50 MK |
1108 | /* |
1109 | * Clearing the interrupt status here ensures that no | |
1110 | * interrupt gets masked after the RIRB wp is read in | |
1111 | * snd_hdac_bus_update_rirb. This avoids a possible | |
1112 | * race condition where codec response in RIRB may | |
1113 | * remain unserviced by IRQ, eventually falling back | |
1114 | * to polling mode in azx_rirb_get_response. | |
1115 | */ | |
1116 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
473f4145 TI |
1117 | active = true; |
1118 | if (status & RIRB_INT_RESPONSE) { | |
1119 | if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) | |
1120 | udelay(80); | |
1121 | snd_hdac_bus_update_rirb(bus); | |
1122 | } | |
f0b1df88 | 1123 | } |
473f4145 | 1124 | } while (active && ++repeat < 10); |
f0b1df88 | 1125 | |
473f4145 | 1126 | unlock: |
a41d1224 | 1127 | spin_unlock(&bus->reg_lock); |
f0b1df88 | 1128 | |
473f4145 | 1129 | return IRQ_RETVAL(handled); |
f0b1df88 DR |
1130 | } |
1131 | EXPORT_SYMBOL_GPL(azx_interrupt); | |
1132 | ||
154867cf DR |
1133 | /* |
1134 | * Codec initerface | |
1135 | */ | |
1136 | ||
1137 | /* | |
1138 | * Probe the given codec address | |
1139 | */ | |
1140 | static int probe_codec(struct azx *chip, int addr) | |
1141 | { | |
1142 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | |
1143 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
7833c3f8 | 1144 | struct hdac_bus *bus = azx_bus(chip); |
cad372f1 | 1145 | int err; |
a41d1224 | 1146 | unsigned int res = -1; |
154867cf | 1147 | |
7e8be1b3 | 1148 | mutex_lock(&bus->cmd_mutex); |
154867cf | 1149 | chip->probing = 1; |
7e8be1b3 TI |
1150 | azx_send_cmd(bus, cmd); |
1151 | err = azx_get_response(bus, addr, &res); | |
154867cf | 1152 | chip->probing = 0; |
7e8be1b3 | 1153 | mutex_unlock(&bus->cmd_mutex); |
cad372f1 | 1154 | if (err < 0 || res == -1) |
154867cf DR |
1155 | return -EIO; |
1156 | dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr); | |
1157 | return 0; | |
1158 | } | |
1159 | ||
0a50575b | 1160 | void snd_hda_bus_reset(struct hda_bus *bus) |
154867cf | 1161 | { |
a41d1224 | 1162 | struct azx *chip = bus_to_azx(&bus->core); |
154867cf DR |
1163 | |
1164 | bus->in_reset = 1; | |
1165 | azx_stop_chip(chip); | |
17c3ad03 | 1166 | azx_init_chip(chip, true); |
a41d1224 | 1167 | if (bus->core.chip_init) |
0a50575b | 1168 | snd_hda_bus_reset_codecs(bus); |
154867cf DR |
1169 | bus->in_reset = 0; |
1170 | } | |
1171 | ||
96d2bd6e | 1172 | /* HD-audio bus initialization */ |
19abfefd | 1173 | int azx_bus_init(struct azx *chip, const char *model) |
154867cf | 1174 | { |
a41d1224 | 1175 | struct hda_bus *bus = &chip->bus; |
96d2bd6e | 1176 | int err; |
154867cf | 1177 | |
19abfefd | 1178 | err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops); |
154867cf DR |
1179 | if (err < 0) |
1180 | return err; | |
1181 | ||
a41d1224 TI |
1182 | bus->card = chip->card; |
1183 | mutex_init(&bus->prepare_mutex); | |
ef744978 TI |
1184 | bus->pci = chip->pci; |
1185 | bus->modelname = model; | |
2f0eaad9 | 1186 | bus->mixer_assigned = -1; |
ccc98865 TI |
1187 | bus->core.snoop = azx_snoop(chip); |
1188 | if (chip->get_position[0] != azx_get_pos_lpib || | |
1189 | chip->get_position[1] != azx_get_pos_lpib) | |
1190 | bus->core.use_posbuf = true; | |
4f0189be | 1191 | bus->core.bdl_pos_adj = chip->bdl_pos_adj; |
a41d1224 TI |
1192 | if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR) |
1193 | bus->core.corbrp_self_clear = true; | |
ef744978 | 1194 | |
de1ab6af TI |
1195 | if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) |
1196 | bus->core.align_bdle_4k = true; | |
1197 | ||
f34a4c9d TI |
1198 | /* enable sync_write flag for stable communication as default */ |
1199 | bus->core.sync_write = 1; | |
96d2bd6e TI |
1200 | |
1201 | return 0; | |
1202 | } | |
a41d1224 | 1203 | EXPORT_SYMBOL_GPL(azx_bus_init); |
96d2bd6e TI |
1204 | |
1205 | /* Probe codecs */ | |
1206 | int azx_probe_codecs(struct azx *chip, unsigned int max_slots) | |
1207 | { | |
a41d1224 | 1208 | struct hdac_bus *bus = azx_bus(chip); |
96d2bd6e TI |
1209 | int c, codecs, err; |
1210 | ||
154867cf DR |
1211 | codecs = 0; |
1212 | if (!max_slots) | |
1213 | max_slots = AZX_DEFAULT_CODECS; | |
1214 | ||
1215 | /* First try to probe all given codec slots */ | |
1216 | for (c = 0; c < max_slots; c++) { | |
a41d1224 | 1217 | if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
154867cf DR |
1218 | if (probe_codec(chip, c) < 0) { |
1219 | /* Some BIOSen give you wrong codec addresses | |
1220 | * that don't exist | |
1221 | */ | |
1222 | dev_warn(chip->card->dev, | |
1223 | "Codec #%d probe error; disabling it...\n", c); | |
a41d1224 | 1224 | bus->codec_mask &= ~(1 << c); |
154867cf DR |
1225 | /* More badly, accessing to a non-existing |
1226 | * codec often screws up the controller chip, | |
1227 | * and disturbs the further communications. | |
1228 | * Thus if an error occurs during probing, | |
1229 | * better to reset the controller chip to | |
1230 | * get back to the sanity state. | |
1231 | */ | |
1232 | azx_stop_chip(chip); | |
17c3ad03 | 1233 | azx_init_chip(chip, true); |
154867cf DR |
1234 | } |
1235 | } | |
1236 | } | |
1237 | ||
154867cf DR |
1238 | /* Then create codec instances */ |
1239 | for (c = 0; c < max_slots; c++) { | |
a41d1224 | 1240 | if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
154867cf | 1241 | struct hda_codec *codec; |
a41d1224 | 1242 | err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec); |
154867cf DR |
1243 | if (err < 0) |
1244 | continue; | |
3a182c84 | 1245 | codec->jackpoll_interval = chip->jackpoll_interval; |
154867cf DR |
1246 | codec->beep_mode = chip->beep_mode; |
1247 | codecs++; | |
1248 | } | |
1249 | } | |
1250 | if (!codecs) { | |
1251 | dev_err(chip->card->dev, "no codecs initialized\n"); | |
1252 | return -ENXIO; | |
1253 | } | |
1254 | return 0; | |
1255 | } | |
96d2bd6e | 1256 | EXPORT_SYMBOL_GPL(azx_probe_codecs); |
154867cf DR |
1257 | |
1258 | /* configure each codec instance */ | |
1259 | int azx_codec_configure(struct azx *chip) | |
1260 | { | |
d94815f9 TI |
1261 | struct hda_codec *codec, *next; |
1262 | ||
1263 | /* use _safe version here since snd_hda_codec_configure() deregisters | |
1264 | * the device upon error and deletes itself from the bus list. | |
1265 | */ | |
1266 | list_for_each_codec_safe(codec, next, &chip->bus) { | |
154867cf DR |
1267 | snd_hda_codec_configure(codec); |
1268 | } | |
17890880 TI |
1269 | |
1270 | if (!azx_bus(chip)->num_codecs) | |
1271 | return -ENODEV; | |
154867cf DR |
1272 | return 0; |
1273 | } | |
1274 | EXPORT_SYMBOL_GPL(azx_codec_configure); | |
1275 | ||
7833c3f8 | 1276 | static int stream_direction(struct azx *chip, unsigned char index) |
93e3423e | 1277 | { |
7833c3f8 TI |
1278 | if (index >= chip->capture_index_offset && |
1279 | index < chip->capture_index_offset + chip->capture_streams) | |
1280 | return SNDRV_PCM_STREAM_CAPTURE; | |
1281 | return SNDRV_PCM_STREAM_PLAYBACK; | |
93e3423e RR |
1282 | } |
1283 | ||
154867cf | 1284 | /* initialize SD streams */ |
a41d1224 | 1285 | int azx_init_streams(struct azx *chip) |
154867cf DR |
1286 | { |
1287 | int i; | |
7833c3f8 | 1288 | int stream_tags[2] = { 0, 0 }; |
154867cf DR |
1289 | |
1290 | /* initialize each stream (aka device) | |
1291 | * assign the starting bdl address to each stream (device) | |
1292 | * and initialize | |
1293 | */ | |
1294 | for (i = 0; i < chip->num_streams; i++) { | |
7833c3f8 TI |
1295 | struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL); |
1296 | int dir, tag; | |
1297 | ||
1298 | if (!azx_dev) | |
1299 | return -ENOMEM; | |
93e3423e | 1300 | |
7833c3f8 | 1301 | dir = stream_direction(chip, i); |
93e3423e RR |
1302 | /* stream tag must be unique throughout |
1303 | * the stream direction group, | |
1304 | * valid values 1...15 | |
1305 | * use separate stream tag if the flag | |
1306 | * AZX_DCAPS_SEPARATE_STREAM_TAG is used | |
1307 | */ | |
1308 | if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) | |
7833c3f8 | 1309 | tag = ++stream_tags[dir]; |
93e3423e | 1310 | else |
7833c3f8 TI |
1311 | tag = i + 1; |
1312 | snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev), | |
1313 | i, dir, tag); | |
154867cf DR |
1314 | } |
1315 | ||
1316 | return 0; | |
1317 | } | |
a41d1224 TI |
1318 | EXPORT_SYMBOL_GPL(azx_init_streams); |
1319 | ||
1320 | void azx_free_streams(struct azx *chip) | |
1321 | { | |
1322 | struct hdac_bus *bus = azx_bus(chip); | |
1323 | struct hdac_stream *s; | |
1324 | ||
1325 | while (!list_empty(&bus->stream_list)) { | |
1326 | s = list_first_entry(&bus->stream_list, struct hdac_stream, list); | |
1327 | list_del(&s->list); | |
1328 | kfree(stream_to_azx_dev(s)); | |
1329 | } | |
1330 | } | |
1331 | EXPORT_SYMBOL_GPL(azx_free_streams); |