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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard | |
c1017a4c | 4 | * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, |
1da177e4 | 5 | * Thomas Sailer <sailer@ife.ee.ethz.ch> |
1da177e4 LT |
6 | */ |
7 | ||
f31a31b9 KB |
8 | /* Power-Management-Code ( CONFIG_PM ) |
9 | * for ens1371 only ( FIXME ) | |
10 | * derived from cs4281.c, atiixp.c and via82xx.c | |
d15534a6 | 11 | * using https://www.kernel.org/doc/html/latest/sound/kernel-api/writing-an-alsa-driver.html |
f31a31b9 KB |
12 | * by Kurt J. Bosch |
13 | */ | |
14 | ||
6cbbfe1c | 15 | #include <linux/io.h> |
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16 | #include <linux/delay.h> |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/gameport.h> | |
65a77217 | 22 | #include <linux/module.h> |
62932df8 IM |
23 | #include <linux/mutex.h> |
24 | ||
1da177e4 LT |
25 | #include <sound/core.h> |
26 | #include <sound/control.h> | |
27 | #include <sound/pcm.h> | |
28 | #include <sound/rawmidi.h> | |
29 | #ifdef CHIP1371 | |
30 | #include <sound/ac97_codec.h> | |
31 | #else | |
32 | #include <sound/ak4531_codec.h> | |
33 | #endif | |
34 | #include <sound/initval.h> | |
35 | #include <sound/asoundef.h> | |
36 | ||
37 | #ifndef CHIP1371 | |
38 | #undef CHIP1370 | |
39 | #define CHIP1370 | |
40 | #endif | |
41 | ||
42 | #ifdef CHIP1370 | |
43 | #define DRIVER_NAME "ENS1370" | |
1fe4d42e | 44 | #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */ |
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45 | #else |
46 | #define DRIVER_NAME "ENS1371" | |
1fe4d42e | 47 | #define CHIP_NAME "ES1371" |
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48 | #endif |
49 | ||
50 | ||
c1017a4c | 51 | MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>"); |
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52 | MODULE_LICENSE("GPL"); |
53 | #ifdef CHIP1370 | |
54 | MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370"); | |
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55 | #endif |
56 | #ifdef CHIP1371 | |
57 | MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+"); | |
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58 | #endif |
59 | ||
b2fac073 | 60 | #if IS_REACHABLE(CONFIG_GAMEPORT) |
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61 | #define SUPPORT_JOYSTICK |
62 | #endif | |
63 | ||
64 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
65 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
a67ff6a5 | 66 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ |
1da177e4 LT |
67 | #ifdef SUPPORT_JOYSTICK |
68 | #ifdef CHIP1371 | |
69 | static int joystick_port[SNDRV_CARDS]; | |
70 | #else | |
a67ff6a5 | 71 | static bool joystick[SNDRV_CARDS]; |
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72 | #endif |
73 | #endif | |
156b2aa3 CL |
74 | #ifdef CHIP1371 |
75 | static int spdif[SNDRV_CARDS]; | |
76 | static int lineio[SNDRV_CARDS]; | |
77 | #endif | |
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78 | |
79 | module_param_array(index, int, NULL, 0444); | |
80 | MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard."); | |
81 | module_param_array(id, charp, NULL, 0444); | |
82 | MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard."); | |
83 | module_param_array(enable, bool, NULL, 0444); | |
84 | MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard."); | |
85 | #ifdef SUPPORT_JOYSTICK | |
86 | #ifdef CHIP1371 | |
6192c41f | 87 | module_param_hw_array(joystick_port, int, ioport, NULL, 0444); |
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88 | MODULE_PARM_DESC(joystick_port, "Joystick port address."); |
89 | #else | |
90 | module_param_array(joystick, bool, NULL, 0444); | |
91 | MODULE_PARM_DESC(joystick, "Enable joystick."); | |
92 | #endif | |
93 | #endif /* SUPPORT_JOYSTICK */ | |
156b2aa3 CL |
94 | #ifdef CHIP1371 |
95 | module_param_array(spdif, int, NULL, 0444); | |
96 | MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force)."); | |
97 | module_param_array(lineio, int, NULL, 0444); | |
98 | MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force)."); | |
99 | #endif | |
1da177e4 | 100 | |
1da177e4 LT |
101 | /* ES1371 chip ID */ |
102 | /* This is a little confusing because all ES1371 compatible chips have the | |
103 | same DEVICE_ID, the only thing differentiating them is the REV_ID field. | |
104 | This is only significant if you want to enable features on the later parts. | |
105 | Yes, I know it's stupid and why didn't we use the sub IDs? | |
106 | */ | |
107 | #define ES1371REV_ES1373_A 0x04 | |
108 | #define ES1371REV_ES1373_B 0x06 | |
109 | #define ES1371REV_CT5880_A 0x07 | |
110 | #define CT5880REV_CT5880_C 0x02 | |
111 | #define CT5880REV_CT5880_D 0x03 /* ??? -jk */ | |
112 | #define CT5880REV_CT5880_E 0x04 /* mw */ | |
113 | #define ES1371REV_ES1371_B 0x09 | |
114 | #define EV1938REV_EV1938_A 0x00 | |
115 | #define ES1371REV_ES1373_8 0x08 | |
116 | ||
117 | /* | |
118 | * Direct registers | |
119 | */ | |
120 | ||
121 | #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x) | |
122 | ||
123 | #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */ | |
124 | #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */ | |
125 | #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */ | |
126 | #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */ | |
127 | #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */ | |
128 | #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */ | |
129 | #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */ | |
130 | #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */ | |
131 | #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */ | |
132 | #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */ | |
133 | #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */ | |
134 | #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03) | |
135 | #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */ | |
136 | #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */ | |
137 | #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */ | |
138 | #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */ | |
139 | #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */ | |
140 | #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */ | |
141 | #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */ | |
142 | #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */ | |
143 | #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */ | |
144 | #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */ | |
145 | #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */ | |
146 | #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */ | |
147 | #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */ | |
148 | #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */ | |
149 | #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */ | |
150 | #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */ | |
151 | #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */ | |
152 | #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */ | |
153 | #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */ | |
154 | #define ES_1371_PDLEVM (0x03<<8) /* mask for above */ | |
155 | #define ES_BREQ (1<<7) /* memory bus request enable */ | |
156 | #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */ | |
157 | #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */ | |
158 | #define ES_ADC_EN (1<<4) /* ADC capture channel enable */ | |
159 | #define ES_UART_EN (1<<3) /* UART enable */ | |
160 | #define ES_JYSTK_EN (1<<2) /* Joystick module enable */ | |
161 | #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */ | |
162 | #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */ | |
163 | #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */ | |
164 | #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */ | |
165 | #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */ | |
166 | #define ES_INTR (1<<31) /* Interrupt is pending */ | |
167 | #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */ | |
168 | #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */ | |
169 | #define ES_1373_REAR_BIT26 (1<<26) | |
170 | #define ES_1373_REAR_BIT24 (1<<24) | |
171 | #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */ | |
172 | #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */ | |
173 | #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */ | |
174 | #define ES_1371_TEST (1<<16) /* test ASIC */ | |
175 | #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */ | |
176 | #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */ | |
177 | #define ES_1370_CBUSY (1<<9) /* CODEC is busy */ | |
178 | #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */ | |
179 | #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */ | |
180 | #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */ | |
181 | #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */ | |
182 | #define ES_1371_MPWR (1<<5) /* power level interrupt pending */ | |
183 | #define ES_MCCB (1<<4) /* CCB interrupt pending */ | |
184 | #define ES_UART (1<<3) /* UART interrupt pending */ | |
185 | #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */ | |
186 | #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */ | |
187 | #define ES_ADC (1<<0) /* ADC channel interrupt pending */ | |
188 | #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */ | |
189 | #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */ | |
190 | #define ES_RXINT (1<<7) /* RX interrupt occurred */ | |
191 | #define ES_TXINT (1<<2) /* TX interrupt occurred */ | |
192 | #define ES_TXRDY (1<<1) /* transmitter ready */ | |
193 | #define ES_RXRDY (1<<0) /* receiver ready */ | |
194 | #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */ | |
195 | #define ES_RXINTEN (1<<7) /* RX interrupt enable */ | |
196 | #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */ | |
197 | #define ES_TXINTENM (0x03<<5) /* mask for above */ | |
198 | #define ES_TXINTENI(i) (((i)>>5)&0x03) | |
199 | #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */ | |
200 | #define ES_CNTRLM (0x03<<0) /* mask for above */ | |
201 | #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */ | |
202 | #define ES_TEST_MODE (1<<0) /* test mode enabled */ | |
203 | #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */ | |
204 | #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */ | |
205 | #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */ | |
206 | #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */ | |
207 | #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */ | |
208 | #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0)) | |
209 | #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */ | |
210 | #define ES_1371_CODEC_RDY (1<<31) /* codec ready */ | |
211 | #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */ | |
6ebb8a4a | 212 | #define EV_1938_CODEC_MAGIC (1<<26) |
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213 | #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */ |
214 | #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0)) | |
215 | #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD) | |
216 | #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff) | |
217 | ||
218 | #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */ | |
219 | #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */ | |
220 | #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */ | |
221 | #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */ | |
222 | #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */ | |
223 | #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */ | |
224 | #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */ | |
225 | #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */ | |
226 | #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */ | |
227 | #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */ | |
228 | #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */ | |
229 | #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */ | |
230 | #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */ | |
231 | ||
232 | #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */ | |
233 | #define ES_1371_JFAST (1<<31) /* fast joystick timing */ | |
234 | #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */ | |
235 | #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */ | |
236 | #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */ | |
237 | #define ES_1371_VMPUM (0x03<<27) /* mask for above */ | |
238 | #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */ | |
239 | #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */ | |
240 | #define ES_1371_VCDCM (0x03<<25) /* mask for above */ | |
241 | #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */ | |
242 | #define ES_1371_FIRQ (1<<24) /* force an interrupt */ | |
243 | #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */ | |
244 | #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */ | |
245 | #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */ | |
246 | #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */ | |
247 | #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */ | |
248 | #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */ | |
249 | #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */ | |
250 | #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */ | |
251 | #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */ | |
252 | #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */ | |
253 | #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */ | |
254 | #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */ | |
255 | ||
256 | #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */ | |
257 | ||
258 | #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */ | |
259 | #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */ | |
260 | #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */ | |
261 | #define ES_P2_END_INCM (0x07<<19) /* mask for above */ | |
262 | #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */ | |
263 | #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */ | |
264 | #define ES_P2_ST_INCM (0x07<<16) /* mask for above */ | |
265 | #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */ | |
266 | #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */ | |
267 | #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */ | |
268 | #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */ | |
269 | #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */ | |
270 | #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */ | |
271 | #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */ | |
272 | #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */ | |
273 | #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */ | |
274 | #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */ | |
275 | #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */ | |
276 | #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */ | |
277 | #define ES_R1_MODEM (0x03<<4) /* mask for above */ | |
278 | #define ES_R1_MODEI(i) (((i)>>4)&0x03) | |
279 | #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */ | |
280 | #define ES_P2_MODEM (0x03<<2) /* mask for above */ | |
281 | #define ES_P2_MODEI(i) (((i)>>2)&0x03) | |
282 | #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */ | |
283 | #define ES_P1_MODEM (0x03<<0) /* mask for above */ | |
284 | #define ES_P1_MODEI(i) (((i)>>0)&0x03) | |
285 | ||
286 | #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */ | |
287 | #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */ | |
288 | #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */ | |
289 | #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff) | |
290 | #define ES_REG_COUNTO(o) (((o)&0xffff)<<0) | |
291 | #define ES_REG_COUNTM (0xffff<<0) | |
292 | #define ES_REG_COUNTI(i) (((i)>>0)&0xffff) | |
293 | ||
294 | #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */ | |
295 | #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */ | |
296 | #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */ | |
297 | #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */ | |
298 | #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */ | |
299 | #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */ | |
300 | #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16) | |
301 | #define ES_REG_FCURR_COUNTM (0xffff<<16) | |
302 | #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc) | |
303 | #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0) | |
304 | #define ES_REG_FSIZEM (0xffff<<0) | |
305 | #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff) | |
306 | #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */ | |
307 | #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */ | |
308 | ||
309 | #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */ | |
310 | #define ES_REG_UF_VALID (1<<8) | |
311 | #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0) | |
312 | #define ES_REG_UF_BYTEM (0xff<<0) | |
313 | #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff) | |
314 | ||
315 | ||
316 | /* | |
317 | * Pages | |
318 | */ | |
319 | ||
320 | #define ES_PAGE_DAC 0x0c | |
321 | #define ES_PAGE_ADC 0x0d | |
322 | #define ES_PAGE_UART 0x0e | |
323 | #define ES_PAGE_UART1 0x0f | |
324 | ||
325 | /* | |
326 | * Sample rate converter addresses | |
327 | */ | |
328 | ||
329 | #define ES_SMPREG_DAC1 0x70 | |
330 | #define ES_SMPREG_DAC2 0x74 | |
331 | #define ES_SMPREG_ADC 0x78 | |
332 | #define ES_SMPREG_VOL_ADC 0x6c | |
333 | #define ES_SMPREG_VOL_DAC1 0x7c | |
334 | #define ES_SMPREG_VOL_DAC2 0x7e | |
335 | #define ES_SMPREG_TRUNC_N 0x00 | |
336 | #define ES_SMPREG_INT_REGS 0x01 | |
337 | #define ES_SMPREG_ACCUM_FRAC 0x02 | |
338 | #define ES_SMPREG_VFREQ_FRAC 0x03 | |
339 | ||
340 | /* | |
341 | * Some contants | |
342 | */ | |
343 | ||
344 | #define ES_1370_SRCLOCK 1411200 | |
345 | #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2) | |
346 | ||
347 | /* | |
348 | * Open modes | |
349 | */ | |
350 | ||
351 | #define ES_MODE_PLAY1 0x0001 | |
352 | #define ES_MODE_PLAY2 0x0002 | |
353 | #define ES_MODE_CAPTURE 0x0004 | |
354 | ||
355 | #define ES_MODE_OUTPUT 0x0001 /* for MIDI */ | |
356 | #define ES_MODE_INPUT 0x0002 /* for MIDI */ | |
357 | ||
358 | /* | |
359 | ||
360 | */ | |
361 | ||
eb3414b4 | 362 | struct ensoniq { |
1da177e4 | 363 | spinlock_t reg_lock; |
62932df8 | 364 | struct mutex src_mutex; |
1da177e4 LT |
365 | |
366 | int irq; | |
367 | ||
368 | unsigned long playback1size; | |
369 | unsigned long playback2size; | |
370 | unsigned long capture3size; | |
371 | ||
372 | unsigned long port; | |
373 | unsigned int mode; | |
374 | unsigned int uartm; /* UART mode */ | |
375 | ||
376 | unsigned int ctrl; /* control register */ | |
377 | unsigned int sctrl; /* serial control register */ | |
378 | unsigned int cssr; /* control status register */ | |
379 | unsigned int uartc; /* uart control register */ | |
380 | unsigned int rev; /* chip revision */ | |
381 | ||
382 | union { | |
383 | #ifdef CHIP1371 | |
384 | struct { | |
eb3414b4 | 385 | struct snd_ac97 *ac97; |
1da177e4 LT |
386 | } es1371; |
387 | #else | |
388 | struct { | |
389 | int pclkdiv_lock; | |
eb3414b4 | 390 | struct snd_ak4531 *ak4531; |
1da177e4 LT |
391 | } es1370; |
392 | #endif | |
393 | } u; | |
394 | ||
395 | struct pci_dev *pci; | |
eb3414b4 TI |
396 | struct snd_card *card; |
397 | struct snd_pcm *pcm1; /* DAC1/ADC PCM */ | |
398 | struct snd_pcm *pcm2; /* DAC2 PCM */ | |
399 | struct snd_pcm_substream *playback1_substream; | |
400 | struct snd_pcm_substream *playback2_substream; | |
401 | struct snd_pcm_substream *capture_substream; | |
1da177e4 LT |
402 | unsigned int p1_dma_size; |
403 | unsigned int p2_dma_size; | |
404 | unsigned int c_dma_size; | |
405 | unsigned int p1_period_size; | |
406 | unsigned int p2_period_size; | |
407 | unsigned int c_period_size; | |
eb3414b4 TI |
408 | struct snd_rawmidi *rmidi; |
409 | struct snd_rawmidi_substream *midi_input; | |
410 | struct snd_rawmidi_substream *midi_output; | |
1da177e4 LT |
411 | |
412 | unsigned int spdif; | |
413 | unsigned int spdif_default; | |
414 | unsigned int spdif_stream; | |
415 | ||
416 | #ifdef CHIP1370 | |
10ed6eaf | 417 | struct snd_dma_buffer *dma_bug; |
1da177e4 LT |
418 | #endif |
419 | ||
420 | #ifdef SUPPORT_JOYSTICK | |
421 | struct gameport *gameport; | |
422 | #endif | |
423 | }; | |
424 | ||
7d12e780 | 425 | static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id); |
1da177e4 | 426 | |
9baa3c34 | 427 | static const struct pci_device_id snd_audiopci_ids[] = { |
1da177e4 | 428 | #ifdef CHIP1370 |
28d27aae | 429 | { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */ |
1da177e4 LT |
430 | #endif |
431 | #ifdef CHIP1371 | |
28d27aae JP |
432 | { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */ |
433 | { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */ | |
0d7392e5 | 434 | { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */ |
1da177e4 LT |
435 | #endif |
436 | { 0, } | |
437 | }; | |
438 | ||
439 | MODULE_DEVICE_TABLE(pci, snd_audiopci_ids); | |
440 | ||
441 | /* | |
442 | * constants | |
443 | */ | |
444 | ||
445 | #define POLL_COUNT 0xa000 | |
446 | ||
447 | #ifdef CHIP1370 | |
8130829a | 448 | static const unsigned int snd_es1370_fixed_rates[] = |
1da177e4 | 449 | {5512, 11025, 22050, 44100}; |
8130829a | 450 | static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = { |
1da177e4 LT |
451 | .count = 4, |
452 | .list = snd_es1370_fixed_rates, | |
453 | .mask = 0, | |
454 | }; | |
8130829a | 455 | static const struct snd_ratnum es1370_clock = { |
1da177e4 LT |
456 | .num = ES_1370_SRCLOCK, |
457 | .den_min = 29, | |
458 | .den_max = 353, | |
459 | .den_step = 1, | |
460 | }; | |
8130829a | 461 | static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = { |
1da177e4 LT |
462 | .nrats = 1, |
463 | .rats = &es1370_clock, | |
464 | }; | |
465 | #else | |
8130829a | 466 | static const struct snd_ratden es1371_dac_clock = { |
1da177e4 LT |
467 | .num_min = 3000 * (1 << 15), |
468 | .num_max = 48000 * (1 << 15), | |
469 | .num_step = 3000, | |
470 | .den = 1 << 15, | |
471 | }; | |
8130829a | 472 | static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = { |
1da177e4 LT |
473 | .nrats = 1, |
474 | .rats = &es1371_dac_clock, | |
475 | }; | |
8130829a | 476 | static const struct snd_ratnum es1371_adc_clock = { |
1da177e4 LT |
477 | .num = 48000 << 15, |
478 | .den_min = 32768, | |
479 | .den_max = 393216, | |
480 | .den_step = 1, | |
481 | }; | |
8130829a | 482 | static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = { |
1da177e4 LT |
483 | .nrats = 1, |
484 | .rats = &es1371_adc_clock, | |
485 | }; | |
486 | #endif | |
487 | static const unsigned int snd_ensoniq_sample_shift[] = | |
488 | {0, 1, 1, 2}; | |
489 | ||
490 | /* | |
491 | * common I/O routines | |
492 | */ | |
493 | ||
494 | #ifdef CHIP1371 | |
495 | ||
eb3414b4 | 496 | static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq) |
1da177e4 LT |
497 | { |
498 | unsigned int t, r = 0; | |
499 | ||
500 | for (t = 0; t < POLL_COUNT; t++) { | |
501 | r = inl(ES_REG(ensoniq, 1371_SMPRATE)); | |
502 | if ((r & ES_1371_SRC_RAM_BUSY) == 0) | |
503 | return r; | |
504 | cond_resched(); | |
505 | } | |
7ddbd181 | 506 | dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n", |
eb3414b4 | 507 | ES_REG(ensoniq, 1371_SMPRATE), r); |
1da177e4 LT |
508 | return 0; |
509 | } | |
510 | ||
eb3414b4 | 511 | static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg) |
1da177e4 LT |
512 | { |
513 | unsigned int temp, i, orig, r; | |
514 | ||
515 | /* wait for ready */ | |
516 | temp = orig = snd_es1371_wait_src_ready(ensoniq); | |
517 | ||
518 | /* expose the SRC state bits */ | |
519 | r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | | |
520 | ES_1371_DIS_P2 | ES_1371_DIS_R1); | |
521 | r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000; | |
522 | outl(r, ES_REG(ensoniq, 1371_SMPRATE)); | |
523 | ||
524 | /* now, wait for busy and the correct time to read */ | |
525 | temp = snd_es1371_wait_src_ready(ensoniq); | |
526 | ||
527 | if ((temp & 0x00870000) != 0x00010000) { | |
528 | /* wait for the right state */ | |
529 | for (i = 0; i < POLL_COUNT; i++) { | |
530 | temp = inl(ES_REG(ensoniq, 1371_SMPRATE)); | |
531 | if ((temp & 0x00870000) == 0x00010000) | |
532 | break; | |
533 | } | |
534 | } | |
535 | ||
536 | /* hide the state bits */ | |
537 | r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | | |
538 | ES_1371_DIS_P2 | ES_1371_DIS_R1); | |
539 | r |= ES_1371_SRC_RAM_ADDRO(reg); | |
540 | outl(r, ES_REG(ensoniq, 1371_SMPRATE)); | |
541 | ||
542 | return temp; | |
543 | } | |
544 | ||
eb3414b4 | 545 | static void snd_es1371_src_write(struct ensoniq * ensoniq, |
1da177e4 LT |
546 | unsigned short reg, unsigned short data) |
547 | { | |
548 | unsigned int r; | |
549 | ||
550 | r = snd_es1371_wait_src_ready(ensoniq) & | |
551 | (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | | |
552 | ES_1371_DIS_P2 | ES_1371_DIS_R1); | |
553 | r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data); | |
554 | outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE)); | |
555 | } | |
556 | ||
557 | #endif /* CHIP1371 */ | |
558 | ||
559 | #ifdef CHIP1370 | |
560 | ||
eb3414b4 | 561 | static void snd_es1370_codec_write(struct snd_ak4531 *ak4531, |
1da177e4 LT |
562 | unsigned short reg, unsigned short val) |
563 | { | |
eb3414b4 | 564 | struct ensoniq *ensoniq = ak4531->private_data; |
1da177e4 LT |
565 | unsigned long end_time = jiffies + HZ / 10; |
566 | ||
567 | #if 0 | |
7ddbd181 | 568 | dev_dbg(ensoniq->card->dev, |
ee419653 | 569 | "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", |
eb3414b4 | 570 | reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); |
1da177e4 LT |
571 | #endif |
572 | do { | |
573 | if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) { | |
574 | outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); | |
575 | return; | |
576 | } | |
8433a509 | 577 | schedule_timeout_uninterruptible(1); |
1da177e4 | 578 | } while (time_after(end_time, jiffies)); |
7ddbd181 | 579 | dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n", |
eb3414b4 | 580 | inl(ES_REG(ensoniq, STATUS))); |
1da177e4 LT |
581 | } |
582 | ||
583 | #endif /* CHIP1370 */ | |
584 | ||
585 | #ifdef CHIP1371 | |
586 | ||
6ebb8a4a CL |
587 | static inline bool is_ev1938(struct ensoniq *ensoniq) |
588 | { | |
589 | return ensoniq->pci->device == 0x8938; | |
590 | } | |
591 | ||
eb3414b4 | 592 | static void snd_es1371_codec_write(struct snd_ac97 *ac97, |
1da177e4 LT |
593 | unsigned short reg, unsigned short val) |
594 | { | |
eb3414b4 | 595 | struct ensoniq *ensoniq = ac97->private_data; |
6ebb8a4a | 596 | unsigned int t, x, flag; |
1da177e4 | 597 | |
6ebb8a4a | 598 | flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0; |
62932df8 | 599 | mutex_lock(&ensoniq->src_mutex); |
1da177e4 LT |
600 | for (t = 0; t < POLL_COUNT; t++) { |
601 | if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { | |
602 | /* save the current state for latter */ | |
603 | x = snd_es1371_wait_src_ready(ensoniq); | |
604 | outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | | |
605 | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, | |
606 | ES_REG(ensoniq, 1371_SMPRATE)); | |
607 | /* wait for not busy (state 0) first to avoid | |
608 | transition states */ | |
609 | for (t = 0; t < POLL_COUNT; t++) { | |
eb3414b4 TI |
610 | if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == |
611 | 0x00000000) | |
1da177e4 LT |
612 | break; |
613 | } | |
614 | /* wait for a SAFE time to write addr/data and then do it, dammit */ | |
615 | for (t = 0; t < POLL_COUNT; t++) { | |
eb3414b4 TI |
616 | if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == |
617 | 0x00010000) | |
1da177e4 LT |
618 | break; |
619 | } | |
6ebb8a4a CL |
620 | outl(ES_1371_CODEC_WRITE(reg, val) | flag, |
621 | ES_REG(ensoniq, 1371_CODEC)); | |
1da177e4 LT |
622 | /* restore SRC reg */ |
623 | snd_es1371_wait_src_ready(ensoniq); | |
624 | outl(x, ES_REG(ensoniq, 1371_SMPRATE)); | |
62932df8 | 625 | mutex_unlock(&ensoniq->src_mutex); |
1da177e4 LT |
626 | return; |
627 | } | |
628 | } | |
62932df8 | 629 | mutex_unlock(&ensoniq->src_mutex); |
7ddbd181 | 630 | dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n", |
eb3414b4 | 631 | ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); |
1da177e4 LT |
632 | } |
633 | ||
eb3414b4 | 634 | static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97, |
1da177e4 LT |
635 | unsigned short reg) |
636 | { | |
eb3414b4 | 637 | struct ensoniq *ensoniq = ac97->private_data; |
6ebb8a4a | 638 | unsigned int t, x, flag, fail = 0; |
1da177e4 | 639 | |
6ebb8a4a | 640 | flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0; |
1da177e4 | 641 | __again: |
62932df8 | 642 | mutex_lock(&ensoniq->src_mutex); |
1da177e4 LT |
643 | for (t = 0; t < POLL_COUNT; t++) { |
644 | if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { | |
645 | /* save the current state for latter */ | |
646 | x = snd_es1371_wait_src_ready(ensoniq); | |
647 | outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | | |
648 | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, | |
649 | ES_REG(ensoniq, 1371_SMPRATE)); | |
650 | /* wait for not busy (state 0) first to avoid | |
651 | transition states */ | |
652 | for (t = 0; t < POLL_COUNT; t++) { | |
eb3414b4 TI |
653 | if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == |
654 | 0x00000000) | |
1da177e4 LT |
655 | break; |
656 | } | |
657 | /* wait for a SAFE time to write addr/data and then do it, dammit */ | |
658 | for (t = 0; t < POLL_COUNT; t++) { | |
eb3414b4 TI |
659 | if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == |
660 | 0x00010000) | |
1da177e4 LT |
661 | break; |
662 | } | |
6ebb8a4a CL |
663 | outl(ES_1371_CODEC_READS(reg) | flag, |
664 | ES_REG(ensoniq, 1371_CODEC)); | |
1da177e4 LT |
665 | /* restore SRC reg */ |
666 | snd_es1371_wait_src_ready(ensoniq); | |
667 | outl(x, ES_REG(ensoniq, 1371_SMPRATE)); | |
668 | /* wait for WIP again */ | |
669 | for (t = 0; t < POLL_COUNT; t++) { | |
670 | if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) | |
671 | break; | |
672 | } | |
673 | /* now wait for the stinkin' data (RDY) */ | |
674 | for (t = 0; t < POLL_COUNT; t++) { | |
93a3a100 TI |
675 | x = inl(ES_REG(ensoniq, 1371_CODEC)); |
676 | if (x & ES_1371_CODEC_RDY) { | |
6ebb8a4a CL |
677 | if (is_ev1938(ensoniq)) { |
678 | for (t = 0; t < 100; t++) | |
679 | inl(ES_REG(ensoniq, CONTROL)); | |
680 | x = inl(ES_REG(ensoniq, 1371_CODEC)); | |
681 | } | |
62932df8 | 682 | mutex_unlock(&ensoniq->src_mutex); |
1da177e4 LT |
683 | return ES_1371_CODEC_READ(x); |
684 | } | |
685 | } | |
62932df8 | 686 | mutex_unlock(&ensoniq->src_mutex); |
1da177e4 | 687 | if (++fail > 10) { |
7ddbd181 TI |
688 | dev_err(ensoniq->card->dev, |
689 | "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", | |
eb3414b4 TI |
690 | ES_REG(ensoniq, 1371_CODEC), reg, |
691 | inl(ES_REG(ensoniq, 1371_CODEC))); | |
1da177e4 LT |
692 | return 0; |
693 | } | |
694 | goto __again; | |
695 | } | |
696 | } | |
62932df8 | 697 | mutex_unlock(&ensoniq->src_mutex); |
7ddbd181 | 698 | dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n", |
eb3414b4 | 699 | ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); |
1da177e4 LT |
700 | return 0; |
701 | } | |
702 | ||
eb3414b4 | 703 | static void snd_es1371_codec_wait(struct snd_ac97 *ac97) |
072c0119 JK |
704 | { |
705 | msleep(750); | |
706 | snd_es1371_codec_read(ac97, AC97_RESET); | |
707 | snd_es1371_codec_read(ac97, AC97_VENDOR_ID1); | |
708 | snd_es1371_codec_read(ac97, AC97_VENDOR_ID2); | |
709 | msleep(50); | |
710 | } | |
711 | ||
eb3414b4 | 712 | static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate) |
1da177e4 | 713 | { |
40ddfe65 | 714 | unsigned int n, truncm, freq; |
1da177e4 | 715 | |
62932df8 | 716 | mutex_lock(&ensoniq->src_mutex); |
1da177e4 LT |
717 | n = rate / 3000; |
718 | if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) | |
719 | n--; | |
720 | truncm = (21 * n - 1) | 1; | |
721 | freq = ((48000UL << 15) / rate) * n; | |
1da177e4 LT |
722 | if (rate >= 24000) { |
723 | if (truncm > 239) | |
724 | truncm = 239; | |
725 | snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, | |
726 | (((239 - truncm) >> 1) << 9) | (n << 4)); | |
727 | } else { | |
728 | if (truncm > 119) | |
729 | truncm = 119; | |
730 | snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, | |
731 | 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); | |
732 | } | |
733 | snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, | |
eb3414b4 TI |
734 | (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + |
735 | ES_SMPREG_INT_REGS) & 0x00ff) | | |
736 | ((freq >> 5) & 0xfc00)); | |
1da177e4 LT |
737 | snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); |
738 | snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8); | |
739 | snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8); | |
62932df8 | 740 | mutex_unlock(&ensoniq->src_mutex); |
1da177e4 LT |
741 | } |
742 | ||
eb3414b4 | 743 | static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate) |
1da177e4 LT |
744 | { |
745 | unsigned int freq, r; | |
746 | ||
62932df8 | 747 | mutex_lock(&ensoniq->src_mutex); |
db433946 | 748 | freq = DIV_ROUND_CLOSEST(rate << 15, 3000); |
eb3414b4 TI |
749 | r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | |
750 | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | | |
751 | ES_1371_DIS_P1; | |
1da177e4 LT |
752 | outl(r, ES_REG(ensoniq, 1371_SMPRATE)); |
753 | snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, | |
eb3414b4 TI |
754 | (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + |
755 | ES_SMPREG_INT_REGS) & 0x00ff) | | |
1da177e4 LT |
756 | ((freq >> 5) & 0xfc00)); |
757 | snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); | |
eb3414b4 TI |
758 | r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | |
759 | ES_1371_DIS_P2 | ES_1371_DIS_R1)); | |
1da177e4 | 760 | outl(r, ES_REG(ensoniq, 1371_SMPRATE)); |
62932df8 | 761 | mutex_unlock(&ensoniq->src_mutex); |
1da177e4 LT |
762 | } |
763 | ||
eb3414b4 | 764 | static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate) |
1da177e4 LT |
765 | { |
766 | unsigned int freq, r; | |
767 | ||
62932df8 | 768 | mutex_lock(&ensoniq->src_mutex); |
db433946 | 769 | freq = DIV_ROUND_CLOSEST(rate << 15, 3000); |
eb3414b4 TI |
770 | r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | |
771 | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | | |
772 | ES_1371_DIS_P2; | |
1da177e4 LT |
773 | outl(r, ES_REG(ensoniq, 1371_SMPRATE)); |
774 | snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, | |
eb3414b4 TI |
775 | (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + |
776 | ES_SMPREG_INT_REGS) & 0x00ff) | | |
1da177e4 | 777 | ((freq >> 5) & 0xfc00)); |
eb3414b4 TI |
778 | snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, |
779 | freq & 0x7fff); | |
780 | r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | | |
781 | ES_1371_DIS_P1 | ES_1371_DIS_R1)); | |
1da177e4 | 782 | outl(r, ES_REG(ensoniq, 1371_SMPRATE)); |
62932df8 | 783 | mutex_unlock(&ensoniq->src_mutex); |
1da177e4 LT |
784 | } |
785 | ||
786 | #endif /* CHIP1371 */ | |
787 | ||
eb3414b4 | 788 | static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 789 | { |
eb3414b4 | 790 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1da177e4 LT |
791 | switch (cmd) { |
792 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
793 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
794 | { | |
795 | unsigned int what = 0; | |
eb3414b4 | 796 | struct snd_pcm_substream *s; |
ef991b95 | 797 | snd_pcm_group_for_each_entry(s, substream) { |
1da177e4 LT |
798 | if (s == ensoniq->playback1_substream) { |
799 | what |= ES_P1_PAUSE; | |
800 | snd_pcm_trigger_done(s, substream); | |
801 | } else if (s == ensoniq->playback2_substream) { | |
802 | what |= ES_P2_PAUSE; | |
803 | snd_pcm_trigger_done(s, substream); | |
804 | } else if (s == ensoniq->capture_substream) | |
805 | return -EINVAL; | |
806 | } | |
807 | spin_lock(&ensoniq->reg_lock); | |
808 | if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) | |
809 | ensoniq->sctrl |= what; | |
810 | else | |
811 | ensoniq->sctrl &= ~what; | |
812 | outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); | |
813 | spin_unlock(&ensoniq->reg_lock); | |
814 | break; | |
815 | } | |
816 | case SNDRV_PCM_TRIGGER_START: | |
817 | case SNDRV_PCM_TRIGGER_STOP: | |
818 | { | |
819 | unsigned int what = 0; | |
eb3414b4 | 820 | struct snd_pcm_substream *s; |
ef991b95 | 821 | snd_pcm_group_for_each_entry(s, substream) { |
1da177e4 LT |
822 | if (s == ensoniq->playback1_substream) { |
823 | what |= ES_DAC1_EN; | |
824 | snd_pcm_trigger_done(s, substream); | |
825 | } else if (s == ensoniq->playback2_substream) { | |
826 | what |= ES_DAC2_EN; | |
827 | snd_pcm_trigger_done(s, substream); | |
828 | } else if (s == ensoniq->capture_substream) { | |
829 | what |= ES_ADC_EN; | |
830 | snd_pcm_trigger_done(s, substream); | |
831 | } | |
832 | } | |
833 | spin_lock(&ensoniq->reg_lock); | |
834 | if (cmd == SNDRV_PCM_TRIGGER_START) | |
835 | ensoniq->ctrl |= what; | |
836 | else | |
837 | ensoniq->ctrl &= ~what; | |
838 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
839 | spin_unlock(&ensoniq->reg_lock); | |
840 | break; | |
841 | } | |
842 | default: | |
843 | return -EINVAL; | |
844 | } | |
845 | return 0; | |
846 | } | |
847 | ||
848 | /* | |
849 | * PCM part | |
850 | */ | |
851 | ||
eb3414b4 | 852 | static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 853 | { |
eb3414b4 TI |
854 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
855 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
856 | unsigned int mode = 0; |
857 | ||
858 | ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream); | |
859 | ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream); | |
860 | if (snd_pcm_format_width(runtime->format) == 16) | |
861 | mode |= 0x02; | |
862 | if (runtime->channels > 1) | |
863 | mode |= 0x01; | |
864 | spin_lock_irq(&ensoniq->reg_lock); | |
865 | ensoniq->ctrl &= ~ES_DAC1_EN; | |
866 | #ifdef CHIP1371 | |
867 | /* 48k doesn't need SRC (it breaks AC3-passthru) */ | |
868 | if (runtime->rate == 48000) | |
869 | ensoniq->ctrl |= ES_1373_BYPASS_P1; | |
870 | else | |
871 | ensoniq->ctrl &= ~ES_1373_BYPASS_P1; | |
872 | #endif | |
873 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
874 | outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); | |
875 | outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME)); | |
876 | outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE)); | |
877 | ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM); | |
878 | ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode); | |
879 | outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); | |
eb3414b4 TI |
880 | outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, |
881 | ES_REG(ensoniq, DAC1_COUNT)); | |
1da177e4 LT |
882 | #ifdef CHIP1370 |
883 | ensoniq->ctrl &= ~ES_1370_WTSRSELM; | |
884 | switch (runtime->rate) { | |
885 | case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break; | |
886 | case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break; | |
887 | case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break; | |
888 | case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break; | |
889 | default: snd_BUG(); | |
890 | } | |
891 | #endif | |
892 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
893 | spin_unlock_irq(&ensoniq->reg_lock); | |
894 | #ifndef CHIP1370 | |
895 | snd_es1371_dac1_rate(ensoniq, runtime->rate); | |
896 | #endif | |
897 | return 0; | |
898 | } | |
899 | ||
eb3414b4 | 900 | static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 901 | { |
eb3414b4 TI |
902 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
903 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
904 | unsigned int mode = 0; |
905 | ||
906 | ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream); | |
907 | ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream); | |
908 | if (snd_pcm_format_width(runtime->format) == 16) | |
909 | mode |= 0x02; | |
910 | if (runtime->channels > 1) | |
911 | mode |= 0x01; | |
912 | spin_lock_irq(&ensoniq->reg_lock); | |
913 | ensoniq->ctrl &= ~ES_DAC2_EN; | |
914 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
915 | outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); | |
916 | outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME)); | |
917 | outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE)); | |
918 | ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN | | |
919 | ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM); | |
920 | ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) | | |
921 | ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0); | |
922 | outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); | |
eb3414b4 TI |
923 | outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, |
924 | ES_REG(ensoniq, DAC2_COUNT)); | |
1da177e4 LT |
925 | #ifdef CHIP1370 |
926 | if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) { | |
927 | ensoniq->ctrl &= ~ES_1370_PCLKDIVM; | |
928 | ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); | |
929 | ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2; | |
930 | } | |
931 | #endif | |
932 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
933 | spin_unlock_irq(&ensoniq->reg_lock); | |
934 | #ifndef CHIP1370 | |
935 | snd_es1371_dac2_rate(ensoniq, runtime->rate); | |
936 | #endif | |
937 | return 0; | |
938 | } | |
939 | ||
eb3414b4 | 940 | static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 941 | { |
eb3414b4 TI |
942 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
943 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
944 | unsigned int mode = 0; |
945 | ||
946 | ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream); | |
947 | ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream); | |
948 | if (snd_pcm_format_width(runtime->format) == 16) | |
949 | mode |= 0x02; | |
950 | if (runtime->channels > 1) | |
951 | mode |= 0x01; | |
952 | spin_lock_irq(&ensoniq->reg_lock); | |
953 | ensoniq->ctrl &= ~ES_ADC_EN; | |
954 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
955 | outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); | |
956 | outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME)); | |
957 | outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE)); | |
958 | ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM); | |
959 | ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode); | |
960 | outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); | |
eb3414b4 TI |
961 | outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, |
962 | ES_REG(ensoniq, ADC_COUNT)); | |
1da177e4 LT |
963 | #ifdef CHIP1370 |
964 | if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) { | |
965 | ensoniq->ctrl &= ~ES_1370_PCLKDIVM; | |
966 | ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); | |
967 | ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE; | |
968 | } | |
969 | #endif | |
970 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
971 | spin_unlock_irq(&ensoniq->reg_lock); | |
972 | #ifndef CHIP1370 | |
973 | snd_es1371_adc_rate(ensoniq, runtime->rate); | |
974 | #endif | |
975 | return 0; | |
976 | } | |
977 | ||
eb3414b4 | 978 | static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 979 | { |
eb3414b4 | 980 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1da177e4 LT |
981 | size_t ptr; |
982 | ||
983 | spin_lock(&ensoniq->reg_lock); | |
984 | if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { | |
985 | outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); | |
986 | ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE))); | |
987 | ptr = bytes_to_frames(substream->runtime, ptr); | |
988 | } else { | |
989 | ptr = 0; | |
990 | } | |
991 | spin_unlock(&ensoniq->reg_lock); | |
992 | return ptr; | |
993 | } | |
994 | ||
eb3414b4 | 995 | static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 996 | { |
eb3414b4 | 997 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1da177e4 LT |
998 | size_t ptr; |
999 | ||
1000 | spin_lock(&ensoniq->reg_lock); | |
1001 | if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { | |
1002 | outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); | |
1003 | ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE))); | |
1004 | ptr = bytes_to_frames(substream->runtime, ptr); | |
1005 | } else { | |
1006 | ptr = 0; | |
1007 | } | |
1008 | spin_unlock(&ensoniq->reg_lock); | |
1009 | return ptr; | |
1010 | } | |
1011 | ||
eb3414b4 | 1012 | static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1013 | { |
eb3414b4 | 1014 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1015 | size_t ptr; |
1016 | ||
1017 | spin_lock(&ensoniq->reg_lock); | |
1018 | if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) { | |
1019 | outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); | |
1020 | ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE))); | |
1021 | ptr = bytes_to_frames(substream->runtime, ptr); | |
1022 | } else { | |
1023 | ptr = 0; | |
1024 | } | |
1025 | spin_unlock(&ensoniq->reg_lock); | |
1026 | return ptr; | |
1027 | } | |
1028 | ||
dee49895 | 1029 | static const struct snd_pcm_hardware snd_ensoniq_playback1 = |
1da177e4 LT |
1030 | { |
1031 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1032 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
1033 | SNDRV_PCM_INFO_MMAP_VALID | | |
1034 | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START), | |
1035 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, | |
1036 | .rates = | |
1037 | #ifndef CHIP1370 | |
1038 | SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, | |
1039 | #else | |
1040 | (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */ | |
1041 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | | |
1042 | SNDRV_PCM_RATE_44100), | |
1043 | #endif | |
1044 | .rate_min = 4000, | |
1045 | .rate_max = 48000, | |
1046 | .channels_min = 1, | |
1047 | .channels_max = 2, | |
1048 | .buffer_bytes_max = (128*1024), | |
1049 | .period_bytes_min = 64, | |
1050 | .period_bytes_max = (128*1024), | |
1051 | .periods_min = 1, | |
1052 | .periods_max = 1024, | |
1053 | .fifo_size = 0, | |
1054 | }; | |
1055 | ||
dee49895 | 1056 | static const struct snd_pcm_hardware snd_ensoniq_playback2 = |
1da177e4 LT |
1057 | { |
1058 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1059 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
1060 | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | | |
1061 | SNDRV_PCM_INFO_SYNC_START), | |
1062 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, | |
1063 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, | |
1064 | .rate_min = 4000, | |
1065 | .rate_max = 48000, | |
1066 | .channels_min = 1, | |
1067 | .channels_max = 2, | |
1068 | .buffer_bytes_max = (128*1024), | |
1069 | .period_bytes_min = 64, | |
1070 | .period_bytes_max = (128*1024), | |
1071 | .periods_min = 1, | |
1072 | .periods_max = 1024, | |
1073 | .fifo_size = 0, | |
1074 | }; | |
1075 | ||
dee49895 | 1076 | static const struct snd_pcm_hardware snd_ensoniq_capture = |
1da177e4 LT |
1077 | { |
1078 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1079 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
1080 | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), | |
1081 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, | |
1082 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, | |
1083 | .rate_min = 4000, | |
1084 | .rate_max = 48000, | |
1085 | .channels_min = 1, | |
1086 | .channels_max = 2, | |
1087 | .buffer_bytes_max = (128*1024), | |
1088 | .period_bytes_min = 64, | |
1089 | .period_bytes_max = (128*1024), | |
1090 | .periods_min = 1, | |
1091 | .periods_max = 1024, | |
1092 | .fifo_size = 0, | |
1093 | }; | |
1094 | ||
eb3414b4 | 1095 | static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream) |
1da177e4 | 1096 | { |
eb3414b4 TI |
1097 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1098 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1099 | |
1100 | ensoniq->mode |= ES_MODE_PLAY1; | |
1101 | ensoniq->playback1_substream = substream; | |
1102 | runtime->hw = snd_ensoniq_playback1; | |
1103 | snd_pcm_set_sync(substream); | |
1104 | spin_lock_irq(&ensoniq->reg_lock); | |
1105 | if (ensoniq->spdif && ensoniq->playback2_substream == NULL) | |
1106 | ensoniq->spdif_stream = ensoniq->spdif_default; | |
1107 | spin_unlock_irq(&ensoniq->reg_lock); | |
1108 | #ifdef CHIP1370 | |
1109 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
1110 | &snd_es1370_hw_constraints_rates); | |
1111 | #else | |
1112 | snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
1113 | &snd_es1371_hw_constraints_dac_clock); | |
1114 | #endif | |
1115 | return 0; | |
1116 | } | |
1117 | ||
eb3414b4 | 1118 | static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream) |
1da177e4 | 1119 | { |
eb3414b4 TI |
1120 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1121 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1122 | |
1123 | ensoniq->mode |= ES_MODE_PLAY2; | |
1124 | ensoniq->playback2_substream = substream; | |
1125 | runtime->hw = snd_ensoniq_playback2; | |
1126 | snd_pcm_set_sync(substream); | |
1127 | spin_lock_irq(&ensoniq->reg_lock); | |
1128 | if (ensoniq->spdif && ensoniq->playback1_substream == NULL) | |
1129 | ensoniq->spdif_stream = ensoniq->spdif_default; | |
1130 | spin_unlock_irq(&ensoniq->reg_lock); | |
1131 | #ifdef CHIP1370 | |
1132 | snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
1133 | &snd_es1370_hw_constraints_clock); | |
1134 | #else | |
1135 | snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
1136 | &snd_es1371_hw_constraints_dac_clock); | |
1137 | #endif | |
1138 | return 0; | |
1139 | } | |
1140 | ||
eb3414b4 | 1141 | static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 1142 | { |
eb3414b4 TI |
1143 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1144 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1145 | |
1146 | ensoniq->mode |= ES_MODE_CAPTURE; | |
1147 | ensoniq->capture_substream = substream; | |
1148 | runtime->hw = snd_ensoniq_capture; | |
1149 | snd_pcm_set_sync(substream); | |
1150 | #ifdef CHIP1370 | |
1151 | snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
1152 | &snd_es1370_hw_constraints_clock); | |
1153 | #else | |
1154 | snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
1155 | &snd_es1371_hw_constraints_adc_clock); | |
1156 | #endif | |
1157 | return 0; | |
1158 | } | |
1159 | ||
eb3414b4 | 1160 | static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream) |
1da177e4 | 1161 | { |
eb3414b4 | 1162 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1163 | |
1164 | ensoniq->playback1_substream = NULL; | |
1165 | ensoniq->mode &= ~ES_MODE_PLAY1; | |
1166 | return 0; | |
1167 | } | |
1168 | ||
eb3414b4 | 1169 | static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream) |
1da177e4 | 1170 | { |
eb3414b4 | 1171 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1172 | |
1173 | ensoniq->playback2_substream = NULL; | |
1174 | spin_lock_irq(&ensoniq->reg_lock); | |
1175 | #ifdef CHIP1370 | |
1176 | ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2; | |
1177 | #endif | |
1178 | ensoniq->mode &= ~ES_MODE_PLAY2; | |
1179 | spin_unlock_irq(&ensoniq->reg_lock); | |
1180 | return 0; | |
1181 | } | |
1182 | ||
eb3414b4 | 1183 | static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1184 | { |
eb3414b4 | 1185 | struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1186 | |
1187 | ensoniq->capture_substream = NULL; | |
1188 | spin_lock_irq(&ensoniq->reg_lock); | |
1189 | #ifdef CHIP1370 | |
1190 | ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE; | |
1191 | #endif | |
1192 | ensoniq->mode &= ~ES_MODE_CAPTURE; | |
1193 | spin_unlock_irq(&ensoniq->reg_lock); | |
1194 | return 0; | |
1195 | } | |
1196 | ||
6769e988 | 1197 | static const struct snd_pcm_ops snd_ensoniq_playback1_ops = { |
1da177e4 LT |
1198 | .open = snd_ensoniq_playback1_open, |
1199 | .close = snd_ensoniq_playback1_close, | |
1da177e4 LT |
1200 | .prepare = snd_ensoniq_playback1_prepare, |
1201 | .trigger = snd_ensoniq_trigger, | |
1202 | .pointer = snd_ensoniq_playback1_pointer, | |
1203 | }; | |
1204 | ||
6769e988 | 1205 | static const struct snd_pcm_ops snd_ensoniq_playback2_ops = { |
1da177e4 LT |
1206 | .open = snd_ensoniq_playback2_open, |
1207 | .close = snd_ensoniq_playback2_close, | |
1da177e4 LT |
1208 | .prepare = snd_ensoniq_playback2_prepare, |
1209 | .trigger = snd_ensoniq_trigger, | |
1210 | .pointer = snd_ensoniq_playback2_pointer, | |
1211 | }; | |
1212 | ||
6769e988 | 1213 | static const struct snd_pcm_ops snd_ensoniq_capture_ops = { |
1da177e4 LT |
1214 | .open = snd_ensoniq_capture_open, |
1215 | .close = snd_ensoniq_capture_close, | |
1da177e4 LT |
1216 | .prepare = snd_ensoniq_capture_prepare, |
1217 | .trigger = snd_ensoniq_trigger, | |
1218 | .pointer = snd_ensoniq_capture_pointer, | |
1219 | }; | |
1220 | ||
7fb6861d TI |
1221 | static const struct snd_pcm_chmap_elem surround_map[] = { |
1222 | { .channels = 1, | |
5efbc261 | 1223 | .map = { SNDRV_CHMAP_MONO } }, |
7fb6861d TI |
1224 | { .channels = 2, |
1225 | .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, | |
1226 | { } | |
1227 | }; | |
1228 | ||
50b8d94e | 1229 | static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device) |
1da177e4 | 1230 | { |
eb3414b4 | 1231 | struct snd_pcm *pcm; |
1da177e4 LT |
1232 | int err; |
1233 | ||
1fe4d42e | 1234 | err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm); |
1da177e4 LT |
1235 | if (err < 0) |
1236 | return err; | |
1237 | ||
1238 | #ifdef CHIP1370 | |
1239 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); | |
1240 | #else | |
1241 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); | |
1242 | #endif | |
1243 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops); | |
1244 | ||
1245 | pcm->private_data = ensoniq; | |
1da177e4 | 1246 | pcm->info_flags = 0; |
1fe4d42e | 1247 | strcpy(pcm->name, CHIP_NAME " DAC2/ADC"); |
1da177e4 LT |
1248 | ensoniq->pcm1 = pcm; |
1249 | ||
b22b2478 TI |
1250 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
1251 | &ensoniq->pci->dev, 64*1024, 128*1024); | |
1da177e4 | 1252 | |
7fb6861d TI |
1253 | #ifdef CHIP1370 |
1254 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
1255 | surround_map, 2, 0, NULL); | |
1256 | #else | |
1257 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
1258 | snd_pcm_std_chmaps, 2, 0, NULL); | |
1259 | #endif | |
50b8d94e | 1260 | return err; |
1da177e4 LT |
1261 | } |
1262 | ||
50b8d94e | 1263 | static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device) |
1da177e4 | 1264 | { |
eb3414b4 | 1265 | struct snd_pcm *pcm; |
1da177e4 LT |
1266 | int err; |
1267 | ||
1fe4d42e | 1268 | err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm); |
1da177e4 LT |
1269 | if (err < 0) |
1270 | return err; | |
1271 | ||
1272 | #ifdef CHIP1370 | |
1273 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); | |
1274 | #else | |
1275 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); | |
1276 | #endif | |
1277 | pcm->private_data = ensoniq; | |
1da177e4 | 1278 | pcm->info_flags = 0; |
1fe4d42e | 1279 | strcpy(pcm->name, CHIP_NAME " DAC1"); |
1da177e4 LT |
1280 | ensoniq->pcm2 = pcm; |
1281 | ||
b22b2478 TI |
1282 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
1283 | &ensoniq->pci->dev, 64*1024, 128*1024); | |
1da177e4 | 1284 | |
7fb6861d TI |
1285 | #ifdef CHIP1370 |
1286 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
1287 | snd_pcm_std_chmaps, 2, 0, NULL); | |
1288 | #else | |
1289 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
1290 | surround_map, 2, 0, NULL); | |
1291 | #endif | |
50b8d94e | 1292 | return err; |
1da177e4 LT |
1293 | } |
1294 | ||
1295 | /* | |
1296 | * Mixer section | |
1297 | */ | |
1298 | ||
1299 | /* | |
1300 | * ENS1371 mixer (including SPDIF interface) | |
1301 | */ | |
1302 | #ifdef CHIP1371 | |
eb3414b4 TI |
1303 | static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol, |
1304 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1305 | { |
1306 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1307 | uinfo->count = 1; | |
1308 | return 0; | |
1309 | } | |
1310 | ||
eb3414b4 TI |
1311 | static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol, |
1312 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1313 | { |
eb3414b4 | 1314 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1315 | spin_lock_irq(&ensoniq->reg_lock); |
1316 | ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff; | |
1317 | ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff; | |
1318 | ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff; | |
1319 | ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff; | |
1320 | spin_unlock_irq(&ensoniq->reg_lock); | |
1321 | return 0; | |
1322 | } | |
1323 | ||
eb3414b4 TI |
1324 | static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol, |
1325 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1326 | { |
eb3414b4 | 1327 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1328 | unsigned int val; |
1329 | int change; | |
1330 | ||
1331 | val = ((u32)ucontrol->value.iec958.status[0] << 0) | | |
1332 | ((u32)ucontrol->value.iec958.status[1] << 8) | | |
1333 | ((u32)ucontrol->value.iec958.status[2] << 16) | | |
1334 | ((u32)ucontrol->value.iec958.status[3] << 24); | |
1335 | spin_lock_irq(&ensoniq->reg_lock); | |
1336 | change = ensoniq->spdif_default != val; | |
1337 | ensoniq->spdif_default = val; | |
eb3414b4 TI |
1338 | if (change && ensoniq->playback1_substream == NULL && |
1339 | ensoniq->playback2_substream == NULL) | |
1da177e4 LT |
1340 | outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); |
1341 | spin_unlock_irq(&ensoniq->reg_lock); | |
1342 | return change; | |
1343 | } | |
1344 | ||
eb3414b4 TI |
1345 | static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol, |
1346 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 LT |
1347 | { |
1348 | ucontrol->value.iec958.status[0] = 0xff; | |
1349 | ucontrol->value.iec958.status[1] = 0xff; | |
1350 | ucontrol->value.iec958.status[2] = 0xff; | |
1351 | ucontrol->value.iec958.status[3] = 0xff; | |
1352 | return 0; | |
1353 | } | |
1354 | ||
eb3414b4 TI |
1355 | static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol, |
1356 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1357 | { |
eb3414b4 | 1358 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1359 | spin_lock_irq(&ensoniq->reg_lock); |
1360 | ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff; | |
1361 | ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff; | |
1362 | ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff; | |
1363 | ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff; | |
1364 | spin_unlock_irq(&ensoniq->reg_lock); | |
1365 | return 0; | |
1366 | } | |
1367 | ||
eb3414b4 TI |
1368 | static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol, |
1369 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1370 | { |
eb3414b4 | 1371 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1372 | unsigned int val; |
1373 | int change; | |
1374 | ||
1375 | val = ((u32)ucontrol->value.iec958.status[0] << 0) | | |
1376 | ((u32)ucontrol->value.iec958.status[1] << 8) | | |
1377 | ((u32)ucontrol->value.iec958.status[2] << 16) | | |
1378 | ((u32)ucontrol->value.iec958.status[3] << 24); | |
1379 | spin_lock_irq(&ensoniq->reg_lock); | |
1380 | change = ensoniq->spdif_stream != val; | |
1381 | ensoniq->spdif_stream = val; | |
eb3414b4 TI |
1382 | if (change && (ensoniq->playback1_substream != NULL || |
1383 | ensoniq->playback2_substream != NULL)) | |
1da177e4 LT |
1384 | outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); |
1385 | spin_unlock_irq(&ensoniq->reg_lock); | |
1386 | return change; | |
1387 | } | |
1388 | ||
1389 | #define ES1371_SPDIF(xname) \ | |
1390 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \ | |
1391 | .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put } | |
1392 | ||
a5ce8890 | 1393 | #define snd_es1371_spdif_info snd_ctl_boolean_mono_info |
1da177e4 | 1394 | |
eb3414b4 TI |
1395 | static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol, |
1396 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1397 | { |
eb3414b4 | 1398 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1399 | |
1400 | spin_lock_irq(&ensoniq->reg_lock); | |
1401 | ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0; | |
1402 | spin_unlock_irq(&ensoniq->reg_lock); | |
1403 | return 0; | |
1404 | } | |
1405 | ||
eb3414b4 TI |
1406 | static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol, |
1407 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1408 | { |
eb3414b4 | 1409 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1410 | unsigned int nval1, nval2; |
1411 | int change; | |
1412 | ||
1413 | nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0; | |
1414 | nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0; | |
1415 | spin_lock_irq(&ensoniq->reg_lock); | |
1416 | change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1; | |
1417 | ensoniq->ctrl &= ~ES_1373_SPDIF_THRU; | |
1418 | ensoniq->ctrl |= nval1; | |
1419 | ensoniq->cssr &= ~ES_1373_SPDIF_EN; | |
1420 | ensoniq->cssr |= nval2; | |
1421 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
1422 | outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); | |
1423 | spin_unlock_irq(&ensoniq->reg_lock); | |
1424 | return change; | |
1425 | } | |
1426 | ||
1427 | ||
1428 | /* spdif controls */ | |
b4e5e707 | 1429 | static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = { |
10e8d78a | 1430 | ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)), |
1da177e4 | 1431 | { |
5549d549 | 1432 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
1433 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), |
1434 | .info = snd_ens1373_spdif_info, | |
1435 | .get = snd_ens1373_spdif_default_get, | |
1436 | .put = snd_ens1373_spdif_default_put, | |
1437 | }, | |
1438 | { | |
1439 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
5549d549 | 1440 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
1441 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), |
1442 | .info = snd_ens1373_spdif_info, | |
1443 | .get = snd_ens1373_spdif_mask_get | |
1444 | }, | |
1445 | { | |
5549d549 | 1446 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
1447 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), |
1448 | .info = snd_ens1373_spdif_info, | |
1449 | .get = snd_ens1373_spdif_stream_get, | |
1450 | .put = snd_ens1373_spdif_stream_put | |
1451 | }, | |
1452 | }; | |
1453 | ||
1454 | ||
a5ce8890 | 1455 | #define snd_es1373_rear_info snd_ctl_boolean_mono_info |
1da177e4 | 1456 | |
eb3414b4 TI |
1457 | static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol, |
1458 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1459 | { |
eb3414b4 | 1460 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1461 | int val = 0; |
1462 | ||
1463 | spin_lock_irq(&ensoniq->reg_lock); | |
eb3414b4 TI |
1464 | if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26| |
1465 | ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26) | |
1da177e4 LT |
1466 | val = 1; |
1467 | ucontrol->value.integer.value[0] = val; | |
1468 | spin_unlock_irq(&ensoniq->reg_lock); | |
1469 | return 0; | |
1470 | } | |
1471 | ||
eb3414b4 TI |
1472 | static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol, |
1473 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1474 | { |
eb3414b4 | 1475 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1476 | unsigned int nval1; |
1477 | int change; | |
1478 | ||
eb3414b4 TI |
1479 | nval1 = ucontrol->value.integer.value[0] ? |
1480 | ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); | |
1da177e4 | 1481 | spin_lock_irq(&ensoniq->reg_lock); |
eb3414b4 TI |
1482 | change = (ensoniq->cssr & (ES_1373_REAR_BIT27| |
1483 | ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1; | |
1da177e4 LT |
1484 | ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24); |
1485 | ensoniq->cssr |= nval1; | |
1486 | outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); | |
1487 | spin_unlock_irq(&ensoniq->reg_lock); | |
1488 | return change; | |
1489 | } | |
1490 | ||
f3b827e0 | 1491 | static const struct snd_kcontrol_new snd_ens1373_rear = |
1da177e4 LT |
1492 | { |
1493 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
1494 | .name = "AC97 2ch->4ch Copy Switch", | |
1495 | .info = snd_es1373_rear_info, | |
1496 | .get = snd_es1373_rear_get, | |
1497 | .put = snd_es1373_rear_put, | |
1498 | }; | |
1499 | ||
a5ce8890 | 1500 | #define snd_es1373_line_info snd_ctl_boolean_mono_info |
1da177e4 | 1501 | |
eb3414b4 TI |
1502 | static int snd_es1373_line_get(struct snd_kcontrol *kcontrol, |
1503 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1504 | { |
eb3414b4 | 1505 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1506 | int val = 0; |
1507 | ||
1508 | spin_lock_irq(&ensoniq->reg_lock); | |
d23f0517 | 1509 | if (ensoniq->ctrl & ES_1371_GPIO_OUT(4)) |
1da177e4 LT |
1510 | val = 1; |
1511 | ucontrol->value.integer.value[0] = val; | |
1512 | spin_unlock_irq(&ensoniq->reg_lock); | |
1513 | return 0; | |
1514 | } | |
1515 | ||
eb3414b4 TI |
1516 | static int snd_es1373_line_put(struct snd_kcontrol *kcontrol, |
1517 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1518 | { |
eb3414b4 | 1519 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1520 | int changed; |
1521 | unsigned int ctrl; | |
1522 | ||
1523 | spin_lock_irq(&ensoniq->reg_lock); | |
1524 | ctrl = ensoniq->ctrl; | |
1525 | if (ucontrol->value.integer.value[0]) | |
1526 | ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */ | |
1527 | else | |
1528 | ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4); | |
1529 | changed = (ctrl != ensoniq->ctrl); | |
1530 | if (changed) | |
1531 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
1532 | spin_unlock_irq(&ensoniq->reg_lock); | |
1533 | return changed; | |
1534 | } | |
1535 | ||
f3b827e0 | 1536 | static const struct snd_kcontrol_new snd_ens1373_line = |
1da177e4 LT |
1537 | { |
1538 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
1539 | .name = "Line In->Rear Out Switch", | |
1540 | .info = snd_es1373_line_info, | |
1541 | .get = snd_es1373_line_get, | |
1542 | .put = snd_es1373_line_put, | |
1543 | }; | |
1544 | ||
eb3414b4 | 1545 | static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97) |
1da177e4 | 1546 | { |
eb3414b4 | 1547 | struct ensoniq *ensoniq = ac97->private_data; |
1da177e4 LT |
1548 | ensoniq->u.es1371.ac97 = NULL; |
1549 | } | |
1550 | ||
5da8fa25 | 1551 | struct es1371_quirk { |
1da177e4 LT |
1552 | unsigned short vid; /* vendor ID */ |
1553 | unsigned short did; /* device ID */ | |
1554 | unsigned char rev; /* revision */ | |
5da8fa25 TI |
1555 | }; |
1556 | ||
076c0e4f | 1557 | static int es1371_quirk_lookup(struct ensoniq *ensoniq, |
88e540a8 | 1558 | const struct es1371_quirk *list) |
5da8fa25 TI |
1559 | { |
1560 | while (list->vid != (unsigned short)PCI_ANY_ID) { | |
1561 | if (ensoniq->pci->vendor == list->vid && | |
1562 | ensoniq->pci->device == list->did && | |
1563 | ensoniq->rev == list->rev) | |
1564 | return 1; | |
1565 | list++; | |
1566 | } | |
1567 | return 0; | |
1568 | } | |
1569 | ||
7103e4a7 | 1570 | static const struct es1371_quirk es1371_spdif_present[] = { |
1da177e4 LT |
1571 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, |
1572 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, | |
1573 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, | |
1574 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, | |
1575 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, | |
1576 | { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } | |
1577 | }; | |
1578 | ||
88e540a8 | 1579 | static const struct snd_pci_quirk ens1373_line_quirk[] = { |
5da8fa25 TI |
1580 | SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */ |
1581 | SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */ | |
1582 | { } /* end */ | |
1583 | }; | |
1584 | ||
e23e7a14 BP |
1585 | static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq, |
1586 | int has_spdif, int has_line) | |
1da177e4 | 1587 | { |
eb3414b4 TI |
1588 | struct snd_card *card = ensoniq->card; |
1589 | struct snd_ac97_bus *pbus; | |
1590 | struct snd_ac97_template ac97; | |
5da8fa25 | 1591 | int err; |
51055da5 | 1592 | static const struct snd_ac97_bus_ops ops = { |
1da177e4 LT |
1593 | .write = snd_es1371_codec_write, |
1594 | .read = snd_es1371_codec_read, | |
072c0119 | 1595 | .wait = snd_es1371_codec_wait, |
1da177e4 LT |
1596 | }; |
1597 | ||
93a3a100 TI |
1598 | err = snd_ac97_bus(card, 0, &ops, NULL, &pbus); |
1599 | if (err < 0) | |
1da177e4 LT |
1600 | return err; |
1601 | ||
1602 | memset(&ac97, 0, sizeof(ac97)); | |
1603 | ac97.private_data = ensoniq; | |
1604 | ac97.private_free = snd_ensoniq_mixer_free_ac97; | |
462dba28 | 1605 | ac97.pci = ensoniq->pci; |
1da177e4 | 1606 | ac97.scaps = AC97_SCAP_AUDIO; |
93a3a100 TI |
1607 | err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97); |
1608 | if (err < 0) | |
1da177e4 | 1609 | return err; |
5da8fa25 TI |
1610 | if (has_spdif > 0 || |
1611 | (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) { | |
1612 | struct snd_kcontrol *kctl; | |
405b0a37 | 1613 | int i, is_spdif = 0; |
5da8fa25 TI |
1614 | |
1615 | ensoniq->spdif_default = ensoniq->spdif_stream = | |
1616 | SNDRV_PCM_DEFAULT_CON_SPDIF; | |
1617 | outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS)); | |
1618 | ||
1619 | if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF) | |
405b0a37 | 1620 | is_spdif++; |
5da8fa25 TI |
1621 | |
1622 | for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) { | |
1623 | kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq); | |
1624 | if (!kctl) | |
1625 | return -ENOMEM; | |
405b0a37 | 1626 | kctl->id.index = is_spdif; |
5da8fa25 TI |
1627 | err = snd_ctl_add(card, kctl); |
1628 | if (err < 0) | |
1629 | return err; | |
1da177e4 | 1630 | } |
5da8fa25 | 1631 | } |
1da177e4 LT |
1632 | if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) { |
1633 | /* mirror rear to front speakers */ | |
1634 | ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); | |
1635 | ensoniq->cssr |= ES_1373_REAR_BIT26; | |
1636 | err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq)); | |
1637 | if (err < 0) | |
1638 | return err; | |
1639 | } | |
5da8fa25 TI |
1640 | if (has_line > 0 || |
1641 | snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) { | |
1642 | err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, | |
1643 | ensoniq)); | |
1da177e4 LT |
1644 | if (err < 0) |
1645 | return err; | |
1646 | } | |
1647 | ||
1648 | return 0; | |
1649 | } | |
1650 | ||
1651 | #endif /* CHIP1371 */ | |
1652 | ||
1653 | /* generic control callbacks for ens1370 */ | |
1654 | #ifdef CHIP1370 | |
1655 | #define ENSONIQ_CONTROL(xname, mask) \ | |
1656 | { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \ | |
1657 | .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \ | |
1658 | .private_value = mask } | |
1659 | ||
a5ce8890 | 1660 | #define snd_ensoniq_control_info snd_ctl_boolean_mono_info |
1da177e4 | 1661 | |
eb3414b4 TI |
1662 | static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol, |
1663 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1664 | { |
eb3414b4 | 1665 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1666 | int mask = kcontrol->private_value; |
1667 | ||
1668 | spin_lock_irq(&ensoniq->reg_lock); | |
1669 | ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; | |
1670 | spin_unlock_irq(&ensoniq->reg_lock); | |
1671 | return 0; | |
1672 | } | |
1673 | ||
eb3414b4 TI |
1674 | static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol, |
1675 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1676 | { |
eb3414b4 | 1677 | struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1678 | int mask = kcontrol->private_value; |
1679 | unsigned int nval; | |
1680 | int change; | |
1681 | ||
1682 | nval = ucontrol->value.integer.value[0] ? mask : 0; | |
1683 | spin_lock_irq(&ensoniq->reg_lock); | |
1684 | change = (ensoniq->ctrl & mask) != nval; | |
1685 | ensoniq->ctrl &= ~mask; | |
1686 | ensoniq->ctrl |= nval; | |
1687 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
1688 | spin_unlock_irq(&ensoniq->reg_lock); | |
1689 | return change; | |
1690 | } | |
1691 | ||
1692 | /* | |
1693 | * ENS1370 mixer | |
1694 | */ | |
1695 | ||
b4e5e707 | 1696 | static const struct snd_kcontrol_new snd_es1370_controls[2] = { |
1da177e4 LT |
1697 | ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0), |
1698 | ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1) | |
1699 | }; | |
1700 | ||
1701 | #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls) | |
1702 | ||
eb3414b4 | 1703 | static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531) |
1da177e4 | 1704 | { |
eb3414b4 | 1705 | struct ensoniq *ensoniq = ak4531->private_data; |
1da177e4 LT |
1706 | ensoniq->u.es1370.ak4531 = NULL; |
1707 | } | |
1708 | ||
e23e7a14 | 1709 | static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq) |
1da177e4 | 1710 | { |
eb3414b4 TI |
1711 | struct snd_card *card = ensoniq->card; |
1712 | struct snd_ak4531 ak4531; | |
1da177e4 LT |
1713 | unsigned int idx; |
1714 | int err; | |
1715 | ||
1716 | /* try reset AK4531 */ | |
1717 | outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); | |
1718 | inw(ES_REG(ensoniq, 1370_CODEC)); | |
1719 | udelay(100); | |
1720 | outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); | |
1721 | inw(ES_REG(ensoniq, 1370_CODEC)); | |
1722 | udelay(100); | |
1723 | ||
1724 | memset(&ak4531, 0, sizeof(ak4531)); | |
1725 | ak4531.write = snd_es1370_codec_write; | |
1726 | ak4531.private_data = ensoniq; | |
1727 | ak4531.private_free = snd_ensoniq_mixer_free_ak4531; | |
93a3a100 TI |
1728 | err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531); |
1729 | if (err < 0) | |
1da177e4 LT |
1730 | return err; |
1731 | for (idx = 0; idx < ES1370_CONTROLS; idx++) { | |
1732 | err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq)); | |
1733 | if (err < 0) | |
1734 | return err; | |
1735 | } | |
1736 | return 0; | |
1737 | } | |
1738 | ||
1739 | #endif /* CHIP1370 */ | |
1740 | ||
1741 | #ifdef SUPPORT_JOYSTICK | |
1742 | ||
1743 | #ifdef CHIP1371 | |
7ddbd181 | 1744 | static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev) |
1da177e4 LT |
1745 | { |
1746 | switch (joystick_port[dev]) { | |
1747 | case 0: /* disabled */ | |
1748 | case 1: /* auto-detect */ | |
1749 | case 0x200: | |
1750 | case 0x208: | |
1751 | case 0x210: | |
1752 | case 0x218: | |
1753 | return joystick_port[dev]; | |
1754 | ||
1755 | default: | |
7ddbd181 TI |
1756 | dev_err(ensoniq->card->dev, |
1757 | "invalid joystick port %#x", joystick_port[dev]); | |
1da177e4 LT |
1758 | return 0; |
1759 | } | |
1760 | } | |
1761 | #else | |
7ddbd181 | 1762 | static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev) |
1da177e4 LT |
1763 | { |
1764 | return joystick[dev] ? 0x200 : 0; | |
1765 | } | |
1766 | #endif | |
1767 | ||
e23e7a14 | 1768 | static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev) |
1da177e4 LT |
1769 | { |
1770 | struct gameport *gp; | |
1771 | int io_port; | |
1772 | ||
7ddbd181 | 1773 | io_port = snd_ensoniq_get_joystick_port(ensoniq, dev); |
1da177e4 LT |
1774 | |
1775 | switch (io_port) { | |
1776 | case 0: | |
1777 | return -ENOSYS; | |
1778 | ||
1779 | case 1: /* auto_detect */ | |
1780 | for (io_port = 0x200; io_port <= 0x218; io_port += 8) | |
1781 | if (request_region(io_port, 8, "ens137x: gameport")) | |
1782 | break; | |
1783 | if (io_port > 0x218) { | |
7ddbd181 TI |
1784 | dev_warn(ensoniq->card->dev, |
1785 | "no gameport ports available\n"); | |
1da177e4 LT |
1786 | return -EBUSY; |
1787 | } | |
1788 | break; | |
1789 | ||
1790 | default: | |
1791 | if (!request_region(io_port, 8, "ens137x: gameport")) { | |
7ddbd181 TI |
1792 | dev_warn(ensoniq->card->dev, |
1793 | "gameport io port %#x in use\n", | |
eb3414b4 | 1794 | io_port); |
1da177e4 LT |
1795 | return -EBUSY; |
1796 | } | |
1797 | break; | |
1798 | } | |
1799 | ||
1800 | ensoniq->gameport = gp = gameport_allocate_port(); | |
1801 | if (!gp) { | |
7ddbd181 TI |
1802 | dev_err(ensoniq->card->dev, |
1803 | "cannot allocate memory for gameport\n"); | |
1da177e4 LT |
1804 | release_region(io_port, 8); |
1805 | return -ENOMEM; | |
1806 | } | |
1807 | ||
1808 | gameport_set_name(gp, "ES137x"); | |
1809 | gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci)); | |
1810 | gameport_set_dev_parent(gp, &ensoniq->pci->dev); | |
1811 | gp->io = io_port; | |
1812 | ||
1813 | ensoniq->ctrl |= ES_JYSTK_EN; | |
1814 | #ifdef CHIP1371 | |
1815 | ensoniq->ctrl &= ~ES_1371_JOY_ASELM; | |
1816 | ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8); | |
1817 | #endif | |
1818 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
1819 | ||
1820 | gameport_register_port(ensoniq->gameport); | |
1821 | ||
1822 | return 0; | |
1823 | } | |
1824 | ||
eb3414b4 | 1825 | static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) |
1da177e4 LT |
1826 | { |
1827 | if (ensoniq->gameport) { | |
1828 | int port = ensoniq->gameport->io; | |
1829 | ||
1830 | gameport_unregister_port(ensoniq->gameport); | |
1831 | ensoniq->gameport = NULL; | |
1832 | ensoniq->ctrl &= ~ES_JYSTK_EN; | |
1833 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
1834 | release_region(port, 8); | |
1835 | } | |
1836 | } | |
1837 | #else | |
eb3414b4 TI |
1838 | static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; } |
1839 | static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { } | |
1da177e4 LT |
1840 | #endif /* SUPPORT_JOYSTICK */ |
1841 | ||
1842 | /* | |
1843 | ||
1844 | */ | |
1845 | ||
eb3414b4 TI |
1846 | static void snd_ensoniq_proc_read(struct snd_info_entry *entry, |
1847 | struct snd_info_buffer *buffer) | |
1da177e4 | 1848 | { |
eb3414b4 | 1849 | struct ensoniq *ensoniq = entry->private_data; |
1da177e4 | 1850 | |
1fe4d42e | 1851 | snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n"); |
eb3414b4 TI |
1852 | snd_iprintf(buffer, "Joystick enable : %s\n", |
1853 | ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off"); | |
1da177e4 | 1854 | #ifdef CHIP1370 |
eb3414b4 TI |
1855 | snd_iprintf(buffer, "MIC +5V bias : %s\n", |
1856 | ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off"); | |
1857 | snd_iprintf(buffer, "Line In to AOUT : %s\n", | |
1858 | ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off"); | |
1da177e4 | 1859 | #else |
eb3414b4 TI |
1860 | snd_iprintf(buffer, "Joystick port : 0x%x\n", |
1861 | (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200); | |
1da177e4 LT |
1862 | #endif |
1863 | } | |
1864 | ||
e23e7a14 | 1865 | static void snd_ensoniq_proc_init(struct ensoniq *ensoniq) |
1da177e4 | 1866 | { |
47f2769b TI |
1867 | snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq, |
1868 | snd_ensoniq_proc_read); | |
1da177e4 LT |
1869 | } |
1870 | ||
1871 | /* | |
1872 | ||
1873 | */ | |
1874 | ||
10ed6eaf | 1875 | static void snd_ensoniq_free(struct snd_card *card) |
1da177e4 | 1876 | { |
10ed6eaf TI |
1877 | struct ensoniq *ensoniq = card->private_data; |
1878 | ||
1da177e4 | 1879 | snd_ensoniq_free_gameport(ensoniq); |
1da177e4 LT |
1880 | #ifdef CHIP1370 |
1881 | outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */ | |
1882 | outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ | |
1883 | #else | |
1884 | outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */ | |
1885 | outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ | |
1886 | #endif | |
1da177e4 LT |
1887 | } |
1888 | ||
1889 | #ifdef CHIP1371 | |
88e540a8 | 1890 | static const struct snd_pci_quirk es1371_amplifier_hack[] = { |
5da8fa25 TI |
1891 | SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */ |
1892 | SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */ | |
1893 | SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */ | |
1894 | SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */ | |
1895 | { } /* end */ | |
1da177e4 | 1896 | }; |
5da8fa25 | 1897 | |
88e540a8 | 1898 | static const struct es1371_quirk es1371_ac97_reset_hack[] = { |
1da177e4 LT |
1899 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, |
1900 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, | |
1901 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, | |
1902 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, | |
1903 | { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, | |
1904 | { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } | |
1905 | }; | |
1906 | #endif | |
1907 | ||
eb3414b4 | 1908 | static void snd_ensoniq_chip_init(struct ensoniq *ensoniq) |
f31a31b9 KB |
1909 | { |
1910 | #ifdef CHIP1371 | |
1911 | int idx; | |
f31a31b9 | 1912 | #endif |
eb3414b4 TI |
1913 | /* this code was part of snd_ensoniq_create before intruduction |
1914 | * of suspend/resume | |
1915 | */ | |
f31a31b9 KB |
1916 | #ifdef CHIP1370 |
1917 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
1918 | outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); | |
1919 | outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); | |
10ed6eaf | 1920 | outl(ensoniq->dma_bug->addr, ES_REG(ensoniq, PHANTOM_FRAME)); |
f31a31b9 KB |
1921 | outl(0, ES_REG(ensoniq, PHANTOM_COUNT)); |
1922 | #else | |
1923 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
1924 | outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); | |
1925 | outl(0, ES_REG(ensoniq, 1371_LEGACY)); | |
5da8fa25 TI |
1926 | if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) { |
1927 | outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); | |
1928 | /* need to delay around 20ms(bleech) to give | |
1929 | some CODECs enough time to wakeup */ | |
1930 | msleep(20); | |
1931 | } | |
f31a31b9 KB |
1932 | /* AC'97 warm reset to start the bitclk */ |
1933 | outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL)); | |
1934 | inl(ES_REG(ensoniq, CONTROL)); | |
1935 | udelay(20); | |
1936 | outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); | |
1937 | /* Init the sample rate converter */ | |
1938 | snd_es1371_wait_src_ready(ensoniq); | |
1939 | outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE)); | |
1940 | for (idx = 0; idx < 0x80; idx++) | |
1941 | snd_es1371_src_write(ensoniq, idx, 0); | |
1942 | snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); | |
1943 | snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); | |
1944 | snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); | |
1945 | snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); | |
1946 | snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12); | |
1947 | snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12); | |
1948 | snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12); | |
1949 | snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); | |
1950 | snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12); | |
1951 | snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); | |
1952 | snd_es1371_adc_rate(ensoniq, 22050); | |
1953 | snd_es1371_dac1_rate(ensoniq, 22050); | |
1954 | snd_es1371_dac2_rate(ensoniq, 22050); | |
1955 | /* WARNING: | |
1956 | * enabling the sample rate converter without properly programming | |
1957 | * its parameters causes the chip to lock up (the SRC busy bit will | |
1958 | * be stuck high, and I've found no way to rectify this other than | |
1959 | * power cycle) - Thomas Sailer | |
1960 | */ | |
1961 | snd_es1371_wait_src_ready(ensoniq); | |
1962 | outl(0, ES_REG(ensoniq, 1371_SMPRATE)); | |
1963 | /* try reset codec directly */ | |
1964 | outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC)); | |
1965 | #endif | |
1966 | outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL)); | |
1967 | outb(0x00, ES_REG(ensoniq, UART_RES)); | |
1968 | outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); | |
f31a31b9 KB |
1969 | } |
1970 | ||
68cb2b55 | 1971 | static int snd_ensoniq_suspend(struct device *dev) |
f31a31b9 | 1972 | { |
68cb2b55 | 1973 | struct snd_card *card = dev_get_drvdata(dev); |
fe8be107 | 1974 | struct ensoniq *ensoniq = card->private_data; |
f31a31b9 | 1975 | |
fe8be107 TI |
1976 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1977 | ||
f31a31b9 | 1978 | #ifdef CHIP1371 |
fe8be107 | 1979 | snd_ac97_suspend(ensoniq->u.es1371.ac97); |
f31a31b9 | 1980 | #else |
15f500a6 TI |
1981 | /* try to reset AK4531 */ |
1982 | outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); | |
1983 | inw(ES_REG(ensoniq, 1370_CODEC)); | |
1984 | udelay(100); | |
1985 | outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); | |
1986 | inw(ES_REG(ensoniq, 1370_CODEC)); | |
1987 | udelay(100); | |
fe8be107 | 1988 | snd_ak4531_suspend(ensoniq->u.es1370.ak4531); |
f31a31b9 | 1989 | #endif |
f31a31b9 KB |
1990 | return 0; |
1991 | } | |
1992 | ||
68cb2b55 | 1993 | static int snd_ensoniq_resume(struct device *dev) |
f31a31b9 | 1994 | { |
68cb2b55 | 1995 | struct snd_card *card = dev_get_drvdata(dev); |
fe8be107 | 1996 | struct ensoniq *ensoniq = card->private_data; |
f31a31b9 | 1997 | |
f31a31b9 KB |
1998 | snd_ensoniq_chip_init(ensoniq); |
1999 | ||
2000 | #ifdef CHIP1371 | |
fe8be107 | 2001 | snd_ac97_resume(ensoniq->u.es1371.ac97); |
f31a31b9 | 2002 | #else |
fe8be107 | 2003 | snd_ak4531_resume(ensoniq->u.es1370.ak4531); |
f31a31b9 | 2004 | #endif |
fe8be107 | 2005 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
f31a31b9 KB |
2006 | return 0; |
2007 | } | |
f31a31b9 | 2008 | |
fd1786bf | 2009 | static DEFINE_SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume); |
f31a31b9 | 2010 | |
e23e7a14 | 2011 | static int snd_ensoniq_create(struct snd_card *card, |
10ed6eaf | 2012 | struct pci_dev *pci) |
1da177e4 | 2013 | { |
10ed6eaf | 2014 | struct ensoniq *ensoniq = card->private_data; |
1da177e4 | 2015 | int err; |
1da177e4 | 2016 | |
10ed6eaf | 2017 | err = pcim_enable_device(pci); |
93a3a100 | 2018 | if (err < 0) |
1da177e4 | 2019 | return err; |
1da177e4 | 2020 | spin_lock_init(&ensoniq->reg_lock); |
62932df8 | 2021 | mutex_init(&ensoniq->src_mutex); |
1da177e4 LT |
2022 | ensoniq->card = card; |
2023 | ensoniq->pci = pci; | |
2024 | ensoniq->irq = -1; | |
93a3a100 | 2025 | err = pci_request_regions(pci, "Ensoniq AudioPCI"); |
10ed6eaf | 2026 | if (err < 0) |
1da177e4 | 2027 | return err; |
1da177e4 | 2028 | ensoniq->port = pci_resource_start(pci, 0); |
10ed6eaf TI |
2029 | if (devm_request_irq(&pci->dev, pci->irq, snd_audiopci_interrupt, |
2030 | IRQF_SHARED, KBUILD_MODNAME, ensoniq)) { | |
7ddbd181 | 2031 | dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); |
1da177e4 LT |
2032 | return -EBUSY; |
2033 | } | |
2034 | ensoniq->irq = pci->irq; | |
83720eef | 2035 | card->sync_irq = ensoniq->irq; |
1da177e4 | 2036 | #ifdef CHIP1370 |
10ed6eaf TI |
2037 | ensoniq->dma_bug = |
2038 | snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, 16); | |
2039 | if (!ensoniq->dma_bug) | |
2040 | return -ENOMEM; | |
1da177e4 LT |
2041 | #endif |
2042 | pci_set_master(pci); | |
44c10138 | 2043 | ensoniq->rev = pci->revision; |
1da177e4 LT |
2044 | #ifdef CHIP1370 |
2045 | #if 0 | |
eb3414b4 TI |
2046 | ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | |
2047 | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); | |
1da177e4 LT |
2048 | #else /* get microphone working */ |
2049 | ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); | |
2050 | #endif | |
2051 | ensoniq->sctrl = 0; | |
1da177e4 LT |
2052 | #else |
2053 | ensoniq->ctrl = 0; | |
2054 | ensoniq->sctrl = 0; | |
2055 | ensoniq->cssr = 0; | |
5da8fa25 TI |
2056 | if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack)) |
2057 | ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */ | |
2058 | ||
2059 | if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) | |
2060 | ensoniq->cssr |= ES_1371_ST_AC97_RST; | |
1da177e4 | 2061 | #endif |
f31a31b9 | 2062 | |
10ed6eaf | 2063 | card->private_free = snd_ensoniq_free; |
f31a31b9 | 2064 | snd_ensoniq_chip_init(ensoniq); |
1da177e4 | 2065 | |
1da177e4 | 2066 | snd_ensoniq_proc_init(ensoniq); |
1da177e4 LT |
2067 | return 0; |
2068 | } | |
2069 | ||
2070 | /* | |
2071 | * MIDI section | |
2072 | */ | |
2073 | ||
eb3414b4 | 2074 | static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq) |
1da177e4 | 2075 | { |
eb3414b4 | 2076 | struct snd_rawmidi *rmidi = ensoniq->rmidi; |
1da177e4 LT |
2077 | unsigned char status, mask, byte; |
2078 | ||
2079 | if (rmidi == NULL) | |
2080 | return; | |
2081 | /* do Rx at first */ | |
2082 | spin_lock(&ensoniq->reg_lock); | |
2083 | mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0; | |
2084 | while (mask) { | |
2085 | status = inb(ES_REG(ensoniq, UART_STATUS)); | |
2086 | if ((status & mask) == 0) | |
2087 | break; | |
2088 | byte = inb(ES_REG(ensoniq, UART_DATA)); | |
2089 | snd_rawmidi_receive(ensoniq->midi_input, &byte, 1); | |
2090 | } | |
2091 | spin_unlock(&ensoniq->reg_lock); | |
2092 | ||
2093 | /* do Tx at second */ | |
2094 | spin_lock(&ensoniq->reg_lock); | |
2095 | mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0; | |
2096 | while (mask) { | |
2097 | status = inb(ES_REG(ensoniq, UART_STATUS)); | |
2098 | if ((status & mask) == 0) | |
2099 | break; | |
2100 | if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) { | |
2101 | ensoniq->uartc &= ~ES_TXINTENM; | |
2102 | outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); | |
2103 | mask &= ~ES_TXRDY; | |
2104 | } else { | |
2105 | outb(byte, ES_REG(ensoniq, UART_DATA)); | |
2106 | } | |
2107 | } | |
2108 | spin_unlock(&ensoniq->reg_lock); | |
2109 | } | |
2110 | ||
eb3414b4 | 2111 | static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream) |
1da177e4 | 2112 | { |
eb3414b4 | 2113 | struct ensoniq *ensoniq = substream->rmidi->private_data; |
1da177e4 LT |
2114 | |
2115 | spin_lock_irq(&ensoniq->reg_lock); | |
2116 | ensoniq->uartm |= ES_MODE_INPUT; | |
2117 | ensoniq->midi_input = substream; | |
2118 | if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { | |
2119 | outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); | |
2120 | outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); | |
2121 | outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); | |
2122 | } | |
2123 | spin_unlock_irq(&ensoniq->reg_lock); | |
2124 | return 0; | |
2125 | } | |
2126 | ||
eb3414b4 | 2127 | static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream) |
1da177e4 | 2128 | { |
eb3414b4 | 2129 | struct ensoniq *ensoniq = substream->rmidi->private_data; |
1da177e4 LT |
2130 | |
2131 | spin_lock_irq(&ensoniq->reg_lock); | |
2132 | if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { | |
2133 | outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); | |
2134 | outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); | |
2135 | } else { | |
2136 | outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL)); | |
2137 | } | |
2138 | ensoniq->midi_input = NULL; | |
2139 | ensoniq->uartm &= ~ES_MODE_INPUT; | |
2140 | spin_unlock_irq(&ensoniq->reg_lock); | |
2141 | return 0; | |
2142 | } | |
2143 | ||
eb3414b4 | 2144 | static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream) |
1da177e4 | 2145 | { |
eb3414b4 | 2146 | struct ensoniq *ensoniq = substream->rmidi->private_data; |
1da177e4 LT |
2147 | |
2148 | spin_lock_irq(&ensoniq->reg_lock); | |
2149 | ensoniq->uartm |= ES_MODE_OUTPUT; | |
2150 | ensoniq->midi_output = substream; | |
2151 | if (!(ensoniq->uartm & ES_MODE_INPUT)) { | |
2152 | outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); | |
2153 | outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); | |
2154 | outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); | |
2155 | } | |
2156 | spin_unlock_irq(&ensoniq->reg_lock); | |
2157 | return 0; | |
2158 | } | |
2159 | ||
eb3414b4 | 2160 | static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream) |
1da177e4 | 2161 | { |
eb3414b4 | 2162 | struct ensoniq *ensoniq = substream->rmidi->private_data; |
1da177e4 LT |
2163 | |
2164 | spin_lock_irq(&ensoniq->reg_lock); | |
2165 | if (!(ensoniq->uartm & ES_MODE_INPUT)) { | |
2166 | outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); | |
2167 | outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); | |
2168 | } else { | |
2169 | outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL)); | |
2170 | } | |
2171 | ensoniq->midi_output = NULL; | |
2172 | ensoniq->uartm &= ~ES_MODE_OUTPUT; | |
2173 | spin_unlock_irq(&ensoniq->reg_lock); | |
2174 | return 0; | |
2175 | } | |
2176 | ||
eb3414b4 | 2177 | static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) |
1da177e4 LT |
2178 | { |
2179 | unsigned long flags; | |
eb3414b4 | 2180 | struct ensoniq *ensoniq = substream->rmidi->private_data; |
1da177e4 LT |
2181 | int idx; |
2182 | ||
2183 | spin_lock_irqsave(&ensoniq->reg_lock, flags); | |
2184 | if (up) { | |
2185 | if ((ensoniq->uartc & ES_RXINTEN) == 0) { | |
2186 | /* empty input FIFO */ | |
2187 | for (idx = 0; idx < 32; idx++) | |
2188 | inb(ES_REG(ensoniq, UART_DATA)); | |
2189 | ensoniq->uartc |= ES_RXINTEN; | |
2190 | outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); | |
2191 | } | |
2192 | } else { | |
2193 | if (ensoniq->uartc & ES_RXINTEN) { | |
2194 | ensoniq->uartc &= ~ES_RXINTEN; | |
2195 | outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); | |
2196 | } | |
2197 | } | |
2198 | spin_unlock_irqrestore(&ensoniq->reg_lock, flags); | |
2199 | } | |
2200 | ||
eb3414b4 | 2201 | static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) |
1da177e4 LT |
2202 | { |
2203 | unsigned long flags; | |
eb3414b4 | 2204 | struct ensoniq *ensoniq = substream->rmidi->private_data; |
1da177e4 LT |
2205 | unsigned char byte; |
2206 | ||
2207 | spin_lock_irqsave(&ensoniq->reg_lock, flags); | |
2208 | if (up) { | |
2209 | if (ES_TXINTENI(ensoniq->uartc) == 0) { | |
2210 | ensoniq->uartc |= ES_TXINTENO(1); | |
2211 | /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ | |
2212 | while (ES_TXINTENI(ensoniq->uartc) == 1 && | |
2213 | (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) { | |
2214 | if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { | |
2215 | ensoniq->uartc &= ~ES_TXINTENM; | |
2216 | } else { | |
2217 | outb(byte, ES_REG(ensoniq, UART_DATA)); | |
2218 | } | |
2219 | } | |
2220 | outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); | |
2221 | } | |
2222 | } else { | |
2223 | if (ES_TXINTENI(ensoniq->uartc) == 1) { | |
2224 | ensoniq->uartc &= ~ES_TXINTENM; | |
2225 | outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); | |
2226 | } | |
2227 | } | |
2228 | spin_unlock_irqrestore(&ensoniq->reg_lock, flags); | |
2229 | } | |
2230 | ||
485885b9 | 2231 | static const struct snd_rawmidi_ops snd_ensoniq_midi_output = |
1da177e4 LT |
2232 | { |
2233 | .open = snd_ensoniq_midi_output_open, | |
2234 | .close = snd_ensoniq_midi_output_close, | |
2235 | .trigger = snd_ensoniq_midi_output_trigger, | |
2236 | }; | |
2237 | ||
485885b9 | 2238 | static const struct snd_rawmidi_ops snd_ensoniq_midi_input = |
1da177e4 LT |
2239 | { |
2240 | .open = snd_ensoniq_midi_input_open, | |
2241 | .close = snd_ensoniq_midi_input_close, | |
2242 | .trigger = snd_ensoniq_midi_input_trigger, | |
2243 | }; | |
2244 | ||
50b8d94e | 2245 | static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device) |
1da177e4 | 2246 | { |
eb3414b4 | 2247 | struct snd_rawmidi *rmidi; |
1da177e4 LT |
2248 | int err; |
2249 | ||
93a3a100 TI |
2250 | err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi); |
2251 | if (err < 0) | |
1da177e4 | 2252 | return err; |
1fe4d42e | 2253 | strcpy(rmidi->name, CHIP_NAME); |
1da177e4 LT |
2254 | snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output); |
2255 | snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input); | |
eb3414b4 TI |
2256 | rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | |
2257 | SNDRV_RAWMIDI_INFO_DUPLEX; | |
1da177e4 LT |
2258 | rmidi->private_data = ensoniq; |
2259 | ensoniq->rmidi = rmidi; | |
1da177e4 LT |
2260 | return 0; |
2261 | } | |
2262 | ||
2263 | /* | |
2264 | * Interrupt handler | |
2265 | */ | |
2266 | ||
7d12e780 | 2267 | static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id) |
1da177e4 | 2268 | { |
eb3414b4 | 2269 | struct ensoniq *ensoniq = dev_id; |
1da177e4 LT |
2270 | unsigned int status, sctrl; |
2271 | ||
2272 | if (ensoniq == NULL) | |
2273 | return IRQ_NONE; | |
2274 | ||
2275 | status = inl(ES_REG(ensoniq, STATUS)); | |
2276 | if (!(status & ES_INTR)) | |
2277 | return IRQ_NONE; | |
2278 | ||
2279 | spin_lock(&ensoniq->reg_lock); | |
2280 | sctrl = ensoniq->sctrl; | |
2281 | if (status & ES_DAC1) | |
2282 | sctrl &= ~ES_P1_INT_EN; | |
2283 | if (status & ES_DAC2) | |
2284 | sctrl &= ~ES_P2_INT_EN; | |
2285 | if (status & ES_ADC) | |
2286 | sctrl &= ~ES_R1_INT_EN; | |
2287 | outl(sctrl, ES_REG(ensoniq, SERIAL)); | |
2288 | outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); | |
2289 | spin_unlock(&ensoniq->reg_lock); | |
2290 | ||
2291 | if (status & ES_UART) | |
2292 | snd_ensoniq_midi_interrupt(ensoniq); | |
2293 | if ((status & ES_DAC2) && ensoniq->playback2_substream) | |
2294 | snd_pcm_period_elapsed(ensoniq->playback2_substream); | |
2295 | if ((status & ES_ADC) && ensoniq->capture_substream) | |
2296 | snd_pcm_period_elapsed(ensoniq->capture_substream); | |
2297 | if ((status & ES_DAC1) && ensoniq->playback1_substream) | |
2298 | snd_pcm_period_elapsed(ensoniq->playback1_substream); | |
2299 | return IRQ_HANDLED; | |
2300 | } | |
2301 | ||
c2dc4693 TI |
2302 | static int __snd_audiopci_probe(struct pci_dev *pci, |
2303 | const struct pci_device_id *pci_id) | |
1da177e4 LT |
2304 | { |
2305 | static int dev; | |
eb3414b4 TI |
2306 | struct snd_card *card; |
2307 | struct ensoniq *ensoniq; | |
3b0cbc78 | 2308 | int err; |
1da177e4 LT |
2309 | |
2310 | if (dev >= SNDRV_CARDS) | |
2311 | return -ENODEV; | |
2312 | if (!enable[dev]) { | |
2313 | dev++; | |
2314 | return -ENOENT; | |
2315 | } | |
2316 | ||
10ed6eaf TI |
2317 | err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, |
2318 | sizeof(*ensoniq), &card); | |
e58de7ba TI |
2319 | if (err < 0) |
2320 | return err; | |
10ed6eaf | 2321 | ensoniq = card->private_data; |
1da177e4 | 2322 | |
10ed6eaf TI |
2323 | err = snd_ensoniq_create(card, pci); |
2324 | if (err < 0) | |
1da177e4 | 2325 | return err; |
1da177e4 | 2326 | |
1da177e4 | 2327 | #ifdef CHIP1370 |
93a3a100 | 2328 | err = snd_ensoniq_1370_mixer(ensoniq); |
10ed6eaf | 2329 | if (err < 0) |
1da177e4 | 2330 | return err; |
1da177e4 LT |
2331 | #endif |
2332 | #ifdef CHIP1371 | |
93a3a100 | 2333 | err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev]); |
10ed6eaf | 2334 | if (err < 0) |
1da177e4 | 2335 | return err; |
1da177e4 | 2336 | #endif |
93a3a100 | 2337 | err = snd_ensoniq_pcm(ensoniq, 0); |
10ed6eaf | 2338 | if (err < 0) |
1da177e4 | 2339 | return err; |
93a3a100 | 2340 | err = snd_ensoniq_pcm2(ensoniq, 1); |
10ed6eaf | 2341 | if (err < 0) |
1da177e4 | 2342 | return err; |
93a3a100 | 2343 | err = snd_ensoniq_midi(ensoniq, 0); |
10ed6eaf | 2344 | if (err < 0) |
1da177e4 | 2345 | return err; |
1da177e4 LT |
2346 | |
2347 | snd_ensoniq_create_gameport(ensoniq, dev); | |
2348 | ||
2349 | strcpy(card->driver, DRIVER_NAME); | |
2350 | ||
2351 | strcpy(card->shortname, "Ensoniq AudioPCI"); | |
2352 | sprintf(card->longname, "%s %s at 0x%lx, irq %i", | |
2353 | card->shortname, | |
2354 | card->driver, | |
2355 | ensoniq->port, | |
2356 | ensoniq->irq); | |
2357 | ||
93a3a100 | 2358 | err = snd_card_register(card); |
10ed6eaf | 2359 | if (err < 0) |
1da177e4 | 2360 | return err; |
1da177e4 LT |
2361 | |
2362 | pci_set_drvdata(pci, card); | |
2363 | dev++; | |
2364 | return 0; | |
2365 | } | |
2366 | ||
c2dc4693 TI |
2367 | static int snd_audiopci_probe(struct pci_dev *pci, |
2368 | const struct pci_device_id *pci_id) | |
2369 | { | |
2370 | return snd_card_free_on_error(&pci->dev, __snd_audiopci_probe(pci, pci_id)); | |
2371 | } | |
2372 | ||
e9f66d9b | 2373 | static struct pci_driver ens137x_driver = { |
3733e424 | 2374 | .name = KBUILD_MODNAME, |
1da177e4 LT |
2375 | .id_table = snd_audiopci_ids, |
2376 | .probe = snd_audiopci_probe, | |
68cb2b55 | 2377 | .driver = { |
fd1786bf | 2378 | .pm = &snd_ensoniq_pm, |
68cb2b55 | 2379 | }, |
1da177e4 LT |
2380 | }; |
2381 | ||
e9f66d9b | 2382 | module_pci_driver(ens137x_driver); |