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[ALSA] Remove xxx_t typedefs: PCI CS4281
[linux-2.6-block.git] / sound / pci / ens1370.c
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1da177e4
LT		 1/*
2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4 * Thomas Sailer <sailer@ife.ee.ethz.ch>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
f31a31b9
KB		 22/* Power-Management-Code ( CONFIG_PM )
23 * for ens1371 only ( FIXME )
24 * derived from cs4281.c, atiixp.c and via82xx.c
25 * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
26 * by Kurt J. Bosch
27 */
28
1da177e4
LT		 29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <linux/gameport.h>
37#include <linux/moduleparam.h>
38#include <sound/core.h>
39#include <sound/control.h>
40#include <sound/pcm.h>
41#include <sound/rawmidi.h>
42#ifdef CHIP1371
43#include <sound/ac97_codec.h>
44#else
45#include <sound/ak4531_codec.h>
46#endif
47#include <sound/initval.h>
48#include <sound/asoundef.h>
49
50#ifndef CHIP1371
51#undef CHIP1370
52#define CHIP1370
53#endif
54
55#ifdef CHIP1370
56#define DRIVER_NAME "ENS1370"
57#else
58#define DRIVER_NAME "ENS1371"
59#endif
60
61
62MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
63MODULE_LICENSE("GPL");
64#ifdef CHIP1370
65MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
66MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
67 "{Creative Labs,SB PCI64/128 (ES1370)}}");
68#endif
69#ifdef CHIP1371
70MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
71MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
72 "{Ensoniq,AudioPCI ES1373},"
73 "{Creative Labs,Ectiva EV1938},"
74 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
75 "{Creative Labs,Vibra PCI128},"
76 "{Ectiva,EV1938}}");
77#endif
78
79#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
80#define SUPPORT_JOYSTICK
81#endif
82
83static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
84static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
85static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
86#ifdef SUPPORT_JOYSTICK
87#ifdef CHIP1371
88static int joystick_port[SNDRV_CARDS];
89#else
90static int joystick[SNDRV_CARDS];
91#endif
92#endif
93
94module_param_array(index, int, NULL, 0444);
95MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
96module_param_array(id, charp, NULL, 0444);
97MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
98module_param_array(enable, bool, NULL, 0444);
99MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
100#ifdef SUPPORT_JOYSTICK
101#ifdef CHIP1371
102module_param_array(joystick_port, int, NULL, 0444);
103MODULE_PARM_DESC(joystick_port, "Joystick port address.");
104#else
105module_param_array(joystick, bool, NULL, 0444);
106MODULE_PARM_DESC(joystick, "Enable joystick.");
107#endif
108#endif /* SUPPORT_JOYSTICK */
109
1da177e4
LT		 110/* ES1371 chip ID */
111/* This is a little confusing because all ES1371 compatible chips have the
112 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
113 This is only significant if you want to enable features on the later parts.
114 Yes, I know it's stupid and why didn't we use the sub IDs?
115*/
116#define ES1371REV_ES1373_A 0x04
117#define ES1371REV_ES1373_B 0x06
118#define ES1371REV_CT5880_A 0x07
119#define CT5880REV_CT5880_C 0x02
120#define CT5880REV_CT5880_D 0x03 /* ??? -jk */
121#define CT5880REV_CT5880_E 0x04 /* mw */
122#define ES1371REV_ES1371_B 0x09
123#define EV1938REV_EV1938_A 0x00
124#define ES1371REV_ES1373_8 0x08
125
126/*
127 * Direct registers
128 */
129
130#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
131
132#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
133#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
134#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
135#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
136#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
137#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
138#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
139#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
140#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
141#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
142#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
143#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
144#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
145#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
146#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
147#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
148#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
149#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
150#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
151#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
152#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
153#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
154#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
155#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
156#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
157#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
158#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
159#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
160#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
161#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
162#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
163#define ES_1371_PDLEVM (0x03<<8) /* mask for above */
164#define ES_BREQ (1<<7) /* memory bus request enable */
165#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
166#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
167#define ES_ADC_EN (1<<4) /* ADC capture channel enable */
168#define ES_UART_EN (1<<3) /* UART enable */
169#define ES_JYSTK_EN (1<<2) /* Joystick module enable */
170#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
171#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
172#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
173#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
174#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
175#define ES_INTR (1<<31) /* Interrupt is pending */
176#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
177#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
178#define ES_1373_REAR_BIT26 (1<<26)
179#define ES_1373_REAR_BIT24 (1<<24)
180#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
181#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
182#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
183#define ES_1371_TEST (1<<16) /* test ASIC */
184#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
185#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
186#define ES_1370_CBUSY (1<<9) /* CODEC is busy */
187#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
188#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
189#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
190#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
191#define ES_1371_MPWR (1<<5) /* power level interrupt pending */
192#define ES_MCCB (1<<4) /* CCB interrupt pending */
193#define ES_UART (1<<3) /* UART interrupt pending */
194#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
195#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
196#define ES_ADC (1<<0) /* ADC channel interrupt pending */
197#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
198#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
199#define ES_RXINT (1<<7) /* RX interrupt occurred */
200#define ES_TXINT (1<<2) /* TX interrupt occurred */
201#define ES_TXRDY (1<<1) /* transmitter ready */
202#define ES_RXRDY (1<<0) /* receiver ready */
203#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
204#define ES_RXINTEN (1<<7) /* RX interrupt enable */
205#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
206#define ES_TXINTENM (0x03<<5) /* mask for above */
207#define ES_TXINTENI(i) (((i)>>5)&0x03)
208#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
209#define ES_CNTRLM (0x03<<0) /* mask for above */
210#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
211#define ES_TEST_MODE (1<<0) /* test mode enabled */
212#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
213#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
214#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
215#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
216#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
217#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
218#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
219#define ES_1371_CODEC_RDY (1<<31) /* codec ready */
220#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
221#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
222#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
223#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
224#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
225
226#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
227#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
228#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
229#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
230#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
231#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
232#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
233#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
234#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
235#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
236#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
237#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
238#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
239
240#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
241#define ES_1371_JFAST (1<<31) /* fast joystick timing */
242#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
243#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
244#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
245#define ES_1371_VMPUM (0x03<<27) /* mask for above */
246#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
247#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
248#define ES_1371_VCDCM (0x03<<25) /* mask for above */
249#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
250#define ES_1371_FIRQ (1<<24) /* force an interrupt */
251#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
252#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
253#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
254#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
255#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
256#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
257#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
258#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
259#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
260#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
261#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
262#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
263
264#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
265
266#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
267#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
268#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
269#define ES_P2_END_INCM (0x07<<19) /* mask for above */
270#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
271#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
272#define ES_P2_ST_INCM (0x07<<16) /* mask for above */
273#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
274#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
275#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
276#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
277#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
278#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
279#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
280#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
281#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
282#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
283#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
284#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
285#define ES_R1_MODEM (0x03<<4) /* mask for above */
286#define ES_R1_MODEI(i) (((i)>>4)&0x03)
287#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
288#define ES_P2_MODEM (0x03<<2) /* mask for above */
289#define ES_P2_MODEI(i) (((i)>>2)&0x03)
290#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
291#define ES_P1_MODEM (0x03<<0) /* mask for above */
292#define ES_P1_MODEI(i) (((i)>>0)&0x03)
293
294#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
295#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
296#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
297#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
298#define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
299#define ES_REG_COUNTM (0xffff<<0)
300#define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
301
302#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
303#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
304#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
305#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
306#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
307#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
308#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
309#define ES_REG_FCURR_COUNTM (0xffff<<16)
310#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
311#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
312#define ES_REG_FSIZEM (0xffff<<0)
313#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
314#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
315#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
316
317#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
318#define ES_REG_UF_VALID (1<<8)
319#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
320#define ES_REG_UF_BYTEM (0xff<<0)
321#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
322
323
324/*
325 * Pages
326 */
327
328#define ES_PAGE_DAC 0x0c
329#define ES_PAGE_ADC 0x0d
330#define ES_PAGE_UART 0x0e
331#define ES_PAGE_UART1 0x0f
332
333/*
334 * Sample rate converter addresses
335 */
336
337#define ES_SMPREG_DAC1 0x70
338#define ES_SMPREG_DAC2 0x74
339#define ES_SMPREG_ADC 0x78
340#define ES_SMPREG_VOL_ADC 0x6c
341#define ES_SMPREG_VOL_DAC1 0x7c
342#define ES_SMPREG_VOL_DAC2 0x7e
343#define ES_SMPREG_TRUNC_N 0x00
344#define ES_SMPREG_INT_REGS 0x01
345#define ES_SMPREG_ACCUM_FRAC 0x02
346#define ES_SMPREG_VFREQ_FRAC 0x03
347
348/*
349 * Some contants
350 */
351
352#define ES_1370_SRCLOCK 1411200
353#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
354
355/*
356 * Open modes
357 */
358
359#define ES_MODE_PLAY1 0x0001
360#define ES_MODE_PLAY2 0x0002
361#define ES_MODE_CAPTURE 0x0004
362
363#define ES_MODE_OUTPUT 0x0001 /* for MIDI */
364#define ES_MODE_INPUT 0x0002 /* for MIDI */
365
366/*
367
368 */
369
370typedef struct _snd_ensoniq ensoniq_t;
371
372struct _snd_ensoniq {
373 spinlock_t reg_lock;
374 struct semaphore src_mutex;
375
376 int irq;
377
378 unsigned long playback1size;
379 unsigned long playback2size;
380 unsigned long capture3size;
381
382 unsigned long port;
383 unsigned int mode;
384 unsigned int uartm; /* UART mode */
385
386 unsigned int ctrl; /* control register */
387 unsigned int sctrl; /* serial control register */
388 unsigned int cssr; /* control status register */
389 unsigned int uartc; /* uart control register */
390 unsigned int rev; /* chip revision */
391
392 union {
393#ifdef CHIP1371
394 struct {
395 ac97_t *ac97;
396 } es1371;
397#else
398 struct {
399 int pclkdiv_lock;
400 ak4531_t *ak4531;
401 } es1370;
402#endif
403 } u;
404
405 struct pci_dev *pci;
406 unsigned short subsystem_vendor_id;
407 unsigned short subsystem_device_id;
408 snd_card_t *card;
409 snd_pcm_t *pcm1; /* DAC1/ADC PCM */
410 snd_pcm_t *pcm2; /* DAC2 PCM */
411 snd_pcm_substream_t *playback1_substream;
412 snd_pcm_substream_t *playback2_substream;
413 snd_pcm_substream_t *capture_substream;
414 unsigned int p1_dma_size;
415 unsigned int p2_dma_size;
416 unsigned int c_dma_size;
417 unsigned int p1_period_size;
418 unsigned int p2_period_size;
419 unsigned int c_period_size;
420 snd_rawmidi_t *rmidi;
421 snd_rawmidi_substream_t *midi_input;
422 snd_rawmidi_substream_t *midi_output;
423
424 unsigned int spdif;
425 unsigned int spdif_default;
426 unsigned int spdif_stream;
427
428#ifdef CHIP1370
429 struct snd_dma_buffer dma_bug;
430#endif
431
432#ifdef SUPPORT_JOYSTICK
433 struct gameport *gameport;
434#endif
435};
436
437static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
438
439static struct pci_device_id snd_audiopci_ids[] = {
440#ifdef CHIP1370
441 { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1370 */
442#endif
443#ifdef CHIP1371
444 { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1371 */
445 { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1373 - CT5880 */
446 { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ectiva EV1938 */
447#endif
448 { 0, }
449};
450
451MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
452
453/*
454 * constants
455 */
456
457#define POLL_COUNT 0xa000
458
459#ifdef CHIP1370
460static unsigned int snd_es1370_fixed_rates[] =
461 {5512, 11025, 22050, 44100};
462static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = {
463 .count = 4,
464 .list = snd_es1370_fixed_rates,
465 .mask = 0,
466};
467static ratnum_t es1370_clock = {
468 .num = ES_1370_SRCLOCK,
469 .den_min = 29,
470 .den_max = 353,
471 .den_step = 1,
472};
473static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = {
474 .nrats = 1,
475 .rats = &es1370_clock,
476};
477#else
478static ratden_t es1371_dac_clock = {
479 .num_min = 3000 * (1 << 15),
480 .num_max = 48000 * (1 << 15),
481 .num_step = 3000,
482 .den = 1 << 15,
483};
484static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = {
485 .nrats = 1,
486 .rats = &es1371_dac_clock,
487};
488static ratnum_t es1371_adc_clock = {
489 .num = 48000 << 15,
490 .den_min = 32768,
491 .den_max = 393216,
492 .den_step = 1,
493};
494static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = {
495 .nrats = 1,
496 .rats = &es1371_adc_clock,
497};
498#endif
499static const unsigned int snd_ensoniq_sample_shift[] =
500 {0, 1, 1, 2};
501
502/*
503 * common I/O routines
504 */
505
506#ifdef CHIP1371
507
508static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq)
509{
510 unsigned int t, r = 0;
511
512 for (t = 0; t < POLL_COUNT; t++) {
513 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
514 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
515 return r;
516 cond_resched();
517 }
99b359ba 518 snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r);
1da177e4
LT		 519 return 0;
520}
521
522static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg)
523{
524 unsigned int temp, i, orig, r;
525
526 /* wait for ready */
527 temp = orig = snd_es1371_wait_src_ready(ensoniq);
528
529 /* expose the SRC state bits */
530 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
531 ES_1371_DIS_P2 | ES_1371_DIS_R1);
532 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
533 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
534
535 /* now, wait for busy and the correct time to read */
536 temp = snd_es1371_wait_src_ready(ensoniq);
537
538 if ((temp & 0x00870000) != 0x00010000) {
539 /* wait for the right state */
540 for (i = 0; i < POLL_COUNT; i++) {
541 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
542 if ((temp & 0x00870000) == 0x00010000)
543 break;
544 }
545 }
546
547 /* hide the state bits */
548 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
549 ES_1371_DIS_P2 | ES_1371_DIS_R1);
550 r |= ES_1371_SRC_RAM_ADDRO(reg);
551 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
552
553 return temp;
554}
555
556static void snd_es1371_src_write(ensoniq_t * ensoniq,
557 unsigned short reg, unsigned short data)
558{
559 unsigned int r;
560
561 r = snd_es1371_wait_src_ready(ensoniq) &
562 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
563 ES_1371_DIS_P2 | ES_1371_DIS_R1);
564 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
565 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
566}
567
568#endif /* CHIP1371 */
569
570#ifdef CHIP1370
571
572static void snd_es1370_codec_write(ak4531_t *ak4531,
573 unsigned short reg, unsigned short val)
574{
575 ensoniq_t *ensoniq = ak4531->private_data;
576 unsigned long end_time = jiffies + HZ / 10;
577
578#if 0
579 printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
580#endif
581 do {
582 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
583 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
584 return;
585 }
8433a509 586 schedule_timeout_uninterruptible(1);
1da177e4 587 } while (time_after(end_time, jiffies));
99b359ba 588 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS)));
1da177e4
LT		 589}
590
591#endif /* CHIP1370 */
592
593#ifdef CHIP1371
594
595static void snd_es1371_codec_write(ac97_t *ac97,
596 unsigned short reg, unsigned short val)
597{
598 ensoniq_t *ensoniq = ac97->private_data;
599 unsigned int t, x;
600
601 down(&ensoniq->src_mutex);
602 for (t = 0; t < POLL_COUNT; t++) {
603 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
604 /* save the current state for latter */
605 x = snd_es1371_wait_src_ready(ensoniq);
606 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
607 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
608 ES_REG(ensoniq, 1371_SMPRATE));
609 /* wait for not busy (state 0) first to avoid
610 transition states */
611 for (t = 0; t < POLL_COUNT; t++) {
612 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
613 break;
614 }
615 /* wait for a SAFE time to write addr/data and then do it, dammit */
616 for (t = 0; t < POLL_COUNT; t++) {
617 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
618 break;
619 }
620 outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
621 /* restore SRC reg */
622 snd_es1371_wait_src_ready(ensoniq);
623 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
624 up(&ensoniq->src_mutex);
625 return;
626 }
627 }
628 up(&ensoniq->src_mutex);
99b359ba 629 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
1da177e4
LT		 630}
631
632static unsigned short snd_es1371_codec_read(ac97_t *ac97,
633 unsigned short reg)
634{
635 ensoniq_t *ensoniq = ac97->private_data;
636 unsigned int t, x, fail = 0;
637
638 __again:
639 down(&ensoniq->src_mutex);
640 for (t = 0; t < POLL_COUNT; t++) {
641 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
642 /* save the current state for latter */
643 x = snd_es1371_wait_src_ready(ensoniq);
644 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
645 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
646 ES_REG(ensoniq, 1371_SMPRATE));
647 /* wait for not busy (state 0) first to avoid
648 transition states */
649 for (t = 0; t < POLL_COUNT; t++) {
650 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
651 break;
652 }
653 /* wait for a SAFE time to write addr/data and then do it, dammit */
654 for (t = 0; t < POLL_COUNT; t++) {
655 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
656 break;
657 }
658 outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
659 /* restore SRC reg */
660 snd_es1371_wait_src_ready(ensoniq);
661 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
662 /* wait for WIP again */
663 for (t = 0; t < POLL_COUNT; t++) {
664 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
665 break;
666 }
667 /* now wait for the stinkin' data (RDY) */
668 for (t = 0; t < POLL_COUNT; t++) {
669 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
670 up(&ensoniq->src_mutex);
671 return ES_1371_CODEC_READ(x);
672 }
673 }
674 up(&ensoniq->src_mutex);
675 if (++fail > 10) {
99b359ba 676 snd_printk(KERN_ERR "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC)));
1da177e4
LT		 677 return 0;
678 }
679 goto __again;
680 }
681 }
682 up(&ensoniq->src_mutex);
99b359ba 683 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
1da177e4
LT		 684 return 0;
685}
686
072c0119
JK		 687static void snd_es1371_codec_wait(ac97_t *ac97)
688{
689 msleep(750);
690 snd_es1371_codec_read(ac97, AC97_RESET);
691 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
692 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
693 msleep(50);
694}
695
1da177e4
LT		 696static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
697{
698 unsigned int n, truncm, freq, result;
699
700 down(&ensoniq->src_mutex);
701 n = rate / 3000;
702 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
703 n--;
704 truncm = (21 * n - 1) | 1;
705 freq = ((48000UL << 15) / rate) * n;
706 result = (48000UL << 15) / (freq / n);
707 if (rate >= 24000) {
708 if (truncm > 239)
709 truncm = 239;
710 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
711 (((239 - truncm) >> 1) << 9) | (n << 4));
712 } else {
713 if (truncm > 119)
714 truncm = 119;
715 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
716 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
717 }
718 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
719 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) |
720 ((freq >> 5) & 0xfc00));
721 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
722 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
723 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
724 up(&ensoniq->src_mutex);
725}
726
727static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate)
728{
729 unsigned int freq, r;
730
731 down(&ensoniq->src_mutex);
732 freq = ((rate << 15) + 1500) / 3000;
733 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1;
734 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
735 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
736 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) |
737 ((freq >> 5) & 0xfc00));
738 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
739 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1));
740 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
741 up(&ensoniq->src_mutex);
742}
743
744static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate)
745{
746 unsigned int freq, r;
747
748 down(&ensoniq->src_mutex);
749 freq = ((rate << 15) + 1500) / 3000;
750 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2;
751 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
752 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
753 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) |
754 ((freq >> 5) & 0xfc00));
755 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
756 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1));
757 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
758 up(&ensoniq->src_mutex);
759}
760
761#endif /* CHIP1371 */
762
763static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd)
764{
765 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
766 switch (cmd) {
767 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
768 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
769 {
770 unsigned int what = 0;
771 struct list_head *pos;
772 snd_pcm_substream_t *s;
773 snd_pcm_group_for_each(pos, substream) {
774 s = snd_pcm_group_substream_entry(pos);
775 if (s == ensoniq->playback1_substream) {
776 what |= ES_P1_PAUSE;
777 snd_pcm_trigger_done(s, substream);
778 } else if (s == ensoniq->playback2_substream) {
779 what |= ES_P2_PAUSE;
780 snd_pcm_trigger_done(s, substream);
781 } else if (s == ensoniq->capture_substream)
782 return -EINVAL;
783 }
784 spin_lock(&ensoniq->reg_lock);
785 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
786 ensoniq->sctrl |= what;
787 else
788 ensoniq->sctrl &= ~what;
789 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
790 spin_unlock(&ensoniq->reg_lock);
791 break;
792 }
793 case SNDRV_PCM_TRIGGER_START:
794 case SNDRV_PCM_TRIGGER_STOP:
795 {
796 unsigned int what = 0;
797 struct list_head *pos;
798 snd_pcm_substream_t *s;
799 snd_pcm_group_for_each(pos, substream) {
800 s = snd_pcm_group_substream_entry(pos);
801 if (s == ensoniq->playback1_substream) {
802 what |= ES_DAC1_EN;
803 snd_pcm_trigger_done(s, substream);
804 } else if (s == ensoniq->playback2_substream) {
805 what |= ES_DAC2_EN;
806 snd_pcm_trigger_done(s, substream);
807 } else if (s == ensoniq->capture_substream) {
808 what |= ES_ADC_EN;
809 snd_pcm_trigger_done(s, substream);
810 }
811 }
812 spin_lock(&ensoniq->reg_lock);
813 if (cmd == SNDRV_PCM_TRIGGER_START)
814 ensoniq->ctrl |= what;
815 else
816 ensoniq->ctrl &= ~what;
817 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
818 spin_unlock(&ensoniq->reg_lock);
819 break;
820 }
821 default:
822 return -EINVAL;
823 }
824 return 0;
825}
826
827/*
828 * PCM part
829 */
830
831static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream,
832 snd_pcm_hw_params_t * hw_params)
833{
834 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
835}
836
837static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream)
838{
839 return snd_pcm_lib_free_pages(substream);
840}
841
842static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream)
843{
844 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
845 snd_pcm_runtime_t *runtime = substream->runtime;
846 unsigned int mode = 0;
847
848 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
849 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
850 if (snd_pcm_format_width(runtime->format) == 16)
851 mode |= 0x02;
852 if (runtime->channels > 1)
853 mode |= 0x01;
854 spin_lock_irq(&ensoniq->reg_lock);
855 ensoniq->ctrl &= ~ES_DAC1_EN;
856#ifdef CHIP1371
857 /* 48k doesn't need SRC (it breaks AC3-passthru) */
858 if (runtime->rate == 48000)
859 ensoniq->ctrl |= ES_1373_BYPASS_P1;
860 else
861 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
862#endif
863 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
864 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
865 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
866 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
867 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
868 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
869 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
870 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT));
871#ifdef CHIP1370
872 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
873 switch (runtime->rate) {
874 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
875 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
876 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
877 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
878 default: snd_BUG();
879 }
880#endif
881 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
882 spin_unlock_irq(&ensoniq->reg_lock);
883#ifndef CHIP1370
884 snd_es1371_dac1_rate(ensoniq, runtime->rate);
885#endif
886 return 0;
887}
888
889static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream)
890{
891 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
892 snd_pcm_runtime_t *runtime = substream->runtime;
893 unsigned int mode = 0;
894
895 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
896 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
897 if (snd_pcm_format_width(runtime->format) == 16)
898 mode |= 0x02;
899 if (runtime->channels > 1)
900 mode |= 0x01;
901 spin_lock_irq(&ensoniq->reg_lock);
902 ensoniq->ctrl &= ~ES_DAC2_EN;
903 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
904 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
905 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
906 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
907 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
908 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
909 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
910 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
911 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
912 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT));
913#ifdef CHIP1370
914 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
915 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
916 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
917 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
918 }
919#endif
920 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
921 spin_unlock_irq(&ensoniq->reg_lock);
922#ifndef CHIP1370
923 snd_es1371_dac2_rate(ensoniq, runtime->rate);
924#endif
925 return 0;
926}
927
928static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream)
929{
930 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
931 snd_pcm_runtime_t *runtime = substream->runtime;
932 unsigned int mode = 0;
933
934 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
935 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
936 if (snd_pcm_format_width(runtime->format) == 16)
937 mode |= 0x02;
938 if (runtime->channels > 1)
939 mode |= 0x01;
940 spin_lock_irq(&ensoniq->reg_lock);
941 ensoniq->ctrl &= ~ES_ADC_EN;
942 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
943 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
944 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
945 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
946 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
947 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
948 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
949 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT));
950#ifdef CHIP1370
951 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
952 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
953 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
954 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
955 }
956#endif
957 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
958 spin_unlock_irq(&ensoniq->reg_lock);
959#ifndef CHIP1370
960 snd_es1371_adc_rate(ensoniq, runtime->rate);
961#endif
962 return 0;
963}
964
965static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream)
966{
967 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
968 size_t ptr;
969
970 spin_lock(&ensoniq->reg_lock);
971 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
972 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
973 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
974 ptr = bytes_to_frames(substream->runtime, ptr);
975 } else {
976 ptr = 0;
977 }
978 spin_unlock(&ensoniq->reg_lock);
979 return ptr;
980}
981
982static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream)
983{
984 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
985 size_t ptr;
986
987 spin_lock(&ensoniq->reg_lock);
988 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
989 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
990 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
991 ptr = bytes_to_frames(substream->runtime, ptr);
992 } else {
993 ptr = 0;
994 }
995 spin_unlock(&ensoniq->reg_lock);
996 return ptr;
997}
998
999static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream)
1000{
1001 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1002 size_t ptr;
1003
1004 spin_lock(&ensoniq->reg_lock);
1005 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1006 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1007 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1008 ptr = bytes_to_frames(substream->runtime, ptr);
1009 } else {
1010 ptr = 0;
1011 }
1012 spin_unlock(&ensoniq->reg_lock);
1013 return ptr;
1014}
1015
1016static snd_pcm_hardware_t snd_ensoniq_playback1 =
1017{
1018 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1019 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1020 SNDRV_PCM_INFO_MMAP_VALID |
1021 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1022 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1023 .rates =
1024#ifndef CHIP1370
1025 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1026#else
1027 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1028 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1029 SNDRV_PCM_RATE_44100),
1030#endif
1031 .rate_min = 4000,
1032 .rate_max = 48000,
1033 .channels_min = 1,
1034 .channels_max = 2,
1035 .buffer_bytes_max = (128*1024),
1036 .period_bytes_min = 64,
1037 .period_bytes_max = (128*1024),
1038 .periods_min = 1,
1039 .periods_max = 1024,
1040 .fifo_size = 0,
1041};
1042
1043static snd_pcm_hardware_t snd_ensoniq_playback2 =
1044{
1045 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1046 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1047 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1048 SNDRV_PCM_INFO_SYNC_START),
1049 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1050 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1051 .rate_min = 4000,
1052 .rate_max = 48000,
1053 .channels_min = 1,
1054 .channels_max = 2,
1055 .buffer_bytes_max = (128*1024),
1056 .period_bytes_min = 64,
1057 .period_bytes_max = (128*1024),
1058 .periods_min = 1,
1059 .periods_max = 1024,
1060 .fifo_size = 0,
1061};
1062
1063static snd_pcm_hardware_t snd_ensoniq_capture =
1064{
1065 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1066 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1067 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1068 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1069 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1070 .rate_min = 4000,
1071 .rate_max = 48000,
1072 .channels_min = 1,
1073 .channels_max = 2,
1074 .buffer_bytes_max = (128*1024),
1075 .period_bytes_min = 64,
1076 .period_bytes_max = (128*1024),
1077 .periods_min = 1,
1078 .periods_max = 1024,
1079 .fifo_size = 0,
1080};
1081
1082static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream)
1083{
1084 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1085 snd_pcm_runtime_t *runtime = substream->runtime;
1086
1087 ensoniq->mode |= ES_MODE_PLAY1;
1088 ensoniq->playback1_substream = substream;
1089 runtime->hw = snd_ensoniq_playback1;
1090 snd_pcm_set_sync(substream);
1091 spin_lock_irq(&ensoniq->reg_lock);
1092 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1093 ensoniq->spdif_stream = ensoniq->spdif_default;
1094 spin_unlock_irq(&ensoniq->reg_lock);
1095#ifdef CHIP1370
1096 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1097 &snd_es1370_hw_constraints_rates);
1098#else
1099 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1100 &snd_es1371_hw_constraints_dac_clock);
1101#endif
1102 return 0;
1103}
1104
1105static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream)
1106{
1107 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1108 snd_pcm_runtime_t *runtime = substream->runtime;
1109
1110 ensoniq->mode |= ES_MODE_PLAY2;
1111 ensoniq->playback2_substream = substream;
1112 runtime->hw = snd_ensoniq_playback2;
1113 snd_pcm_set_sync(substream);
1114 spin_lock_irq(&ensoniq->reg_lock);
1115 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1116 ensoniq->spdif_stream = ensoniq->spdif_default;
1117 spin_unlock_irq(&ensoniq->reg_lock);
1118#ifdef CHIP1370
1119 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1120 &snd_es1370_hw_constraints_clock);
1121#else
1122 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1123 &snd_es1371_hw_constraints_dac_clock);
1124#endif
1125 return 0;
1126}
1127
1128static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream)
1129{
1130 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1131 snd_pcm_runtime_t *runtime = substream->runtime;
1132
1133 ensoniq->mode |= ES_MODE_CAPTURE;
1134 ensoniq->capture_substream = substream;
1135 runtime->hw = snd_ensoniq_capture;
1136 snd_pcm_set_sync(substream);
1137#ifdef CHIP1370
1138 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1139 &snd_es1370_hw_constraints_clock);
1140#else
1141 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1142 &snd_es1371_hw_constraints_adc_clock);
1143#endif
1144 return 0;
1145}
1146
1147static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream)
1148{
1149 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1150
1151 ensoniq->playback1_substream = NULL;
1152 ensoniq->mode &= ~ES_MODE_PLAY1;
1153 return 0;
1154}
1155
1156static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream)
1157{
1158 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1159
1160 ensoniq->playback2_substream = NULL;
1161 spin_lock_irq(&ensoniq->reg_lock);
1162#ifdef CHIP1370
1163 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1164#endif
1165 ensoniq->mode &= ~ES_MODE_PLAY2;
1166 spin_unlock_irq(&ensoniq->reg_lock);
1167 return 0;
1168}
1169
1170static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream)
1171{
1172 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1173
1174 ensoniq->capture_substream = NULL;
1175 spin_lock_irq(&ensoniq->reg_lock);
1176#ifdef CHIP1370
1177 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1178#endif
1179 ensoniq->mode &= ~ES_MODE_CAPTURE;
1180 spin_unlock_irq(&ensoniq->reg_lock);
1181 return 0;
1182}
1183
1184static snd_pcm_ops_t snd_ensoniq_playback1_ops = {
1185 .open = snd_ensoniq_playback1_open,
1186 .close = snd_ensoniq_playback1_close,
1187 .ioctl = snd_pcm_lib_ioctl,
1188 .hw_params = snd_ensoniq_hw_params,
1189 .hw_free = snd_ensoniq_hw_free,
1190 .prepare = snd_ensoniq_playback1_prepare,
1191 .trigger = snd_ensoniq_trigger,
1192 .pointer = snd_ensoniq_playback1_pointer,
1193};
1194
1195static snd_pcm_ops_t snd_ensoniq_playback2_ops = {
1196 .open = snd_ensoniq_playback2_open,
1197 .close = snd_ensoniq_playback2_close,
1198 .ioctl = snd_pcm_lib_ioctl,
1199 .hw_params = snd_ensoniq_hw_params,
1200 .hw_free = snd_ensoniq_hw_free,
1201 .prepare = snd_ensoniq_playback2_prepare,
1202 .trigger = snd_ensoniq_trigger,
1203 .pointer = snd_ensoniq_playback2_pointer,
1204};
1205
1206static snd_pcm_ops_t snd_ensoniq_capture_ops = {
1207 .open = snd_ensoniq_capture_open,
1208 .close = snd_ensoniq_capture_close,
1209 .ioctl = snd_pcm_lib_ioctl,
1210 .hw_params = snd_ensoniq_hw_params,
1211 .hw_free = snd_ensoniq_hw_free,
1212 .prepare = snd_ensoniq_capture_prepare,
1213 .trigger = snd_ensoniq_trigger,
1214 .pointer = snd_ensoniq_capture_pointer,
1215};
1216
1da177e4
LT		 1217static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1218{
1219 snd_pcm_t *pcm;
1220 int err;
1221
1222 if (rpcm)
1223 *rpcm = NULL;
1224#ifdef CHIP1370
1225 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1226#else
1227 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1228#endif
1229 if (err < 0)
1230 return err;
1231
1232#ifdef CHIP1370
1233 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1234#else
1235 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1236#endif
1237 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1238
1239 pcm->private_data = ensoniq;
1da177e4
LT		 1240 pcm->info_flags = 0;
1241#ifdef CHIP1370
1242 strcpy(pcm->name, "ES1370 DAC2/ADC");
1243#else
1244 strcpy(pcm->name, "ES1371 DAC2/ADC");
1245#endif
1246 ensoniq->pcm1 = pcm;
1247
1248 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1249 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1250
1251 if (rpcm)
1252 *rpcm = pcm;
1253 return 0;
1254}
1255
1da177e4
LT		 1256static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1257{
1258 snd_pcm_t *pcm;
1259 int err;
1260
1261 if (rpcm)
1262 *rpcm = NULL;
1263#ifdef CHIP1370
1264 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1265#else
1266 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1267#endif
1268 if (err < 0)
1269 return err;
1270
1271#ifdef CHIP1370
1272 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1273#else
1274 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1275#endif
1276 pcm->private_data = ensoniq;
1da177e4
LT		 1277 pcm->info_flags = 0;
1278#ifdef CHIP1370
1279 strcpy(pcm->name, "ES1370 DAC1");
1280#else
1281 strcpy(pcm->name, "ES1371 DAC1");
1282#endif
1283 ensoniq->pcm2 = pcm;
1284
1285 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1286 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1287
1288 if (rpcm)
1289 *rpcm = pcm;
1290 return 0;
1291}
1292
1293/*
1294 * Mixer section
1295 */
1296
1297/*
1298 * ENS1371 mixer (including SPDIF interface)
1299 */
1300#ifdef CHIP1371
1301static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1302{
1303 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1304 uinfo->count = 1;
1305 return 0;
1306}
1307
1308static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol,
1309 snd_ctl_elem_value_t * ucontrol)
1310{
1311 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1312 spin_lock_irq(&ensoniq->reg_lock);
1313 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1314 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1315 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1316 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1317 spin_unlock_irq(&ensoniq->reg_lock);
1318 return 0;
1319}
1320
1321static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol,
1322 snd_ctl_elem_value_t * ucontrol)
1323{
1324 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1325 unsigned int val;
1326 int change;
1327
1328 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1329 ((u32)ucontrol->value.iec958.status[1] << 8) |
1330 ((u32)ucontrol->value.iec958.status[2] << 16) |
1331 ((u32)ucontrol->value.iec958.status[3] << 24);
1332 spin_lock_irq(&ensoniq->reg_lock);
1333 change = ensoniq->spdif_default != val;
1334 ensoniq->spdif_default = val;
1335 if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL)
1336 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1337 spin_unlock_irq(&ensoniq->reg_lock);
1338 return change;
1339}
1340
1341static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol,
1342 snd_ctl_elem_value_t * ucontrol)
1343{
1344 ucontrol->value.iec958.status[0] = 0xff;
1345 ucontrol->value.iec958.status[1] = 0xff;
1346 ucontrol->value.iec958.status[2] = 0xff;
1347 ucontrol->value.iec958.status[3] = 0xff;
1348 return 0;
1349}
1350
1351static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol,
1352 snd_ctl_elem_value_t * ucontrol)
1353{
1354 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1355 spin_lock_irq(&ensoniq->reg_lock);
1356 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1357 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1358 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1359 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1360 spin_unlock_irq(&ensoniq->reg_lock);
1361 return 0;
1362}
1363
1364static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol,
1365 snd_ctl_elem_value_t * ucontrol)
1366{
1367 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1368 unsigned int val;
1369 int change;
1370
1371 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1372 ((u32)ucontrol->value.iec958.status[1] << 8) |
1373 ((u32)ucontrol->value.iec958.status[2] << 16) |
1374 ((u32)ucontrol->value.iec958.status[3] << 24);
1375 spin_lock_irq(&ensoniq->reg_lock);
1376 change = ensoniq->spdif_stream != val;
1377 ensoniq->spdif_stream = val;
1378 if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL))
1379 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1380 spin_unlock_irq(&ensoniq->reg_lock);
1381 return change;
1382}
1383
1384#define ES1371_SPDIF(xname) \
1385{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1386 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1387
1388static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1389{
1390 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1391 uinfo->count = 1;
1392 uinfo->value.integer.min = 0;
1393 uinfo->value.integer.max = 1;
1394 return 0;
1395}
1396
1397static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1398{
1399 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1400
1401 spin_lock_irq(&ensoniq->reg_lock);
1402 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1403 spin_unlock_irq(&ensoniq->reg_lock);
1404 return 0;
1405}
1406
1407static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1408{
1409 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1410 unsigned int nval1, nval2;
1411 int change;
1412
1413 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1414 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1415 spin_lock_irq(&ensoniq->reg_lock);
1416 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1417 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1418 ensoniq->ctrl |= nval1;
1419 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1420 ensoniq->cssr |= nval2;
1421 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1422 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1423 spin_unlock_irq(&ensoniq->reg_lock);
1424 return change;
1425}
1426
1427
1428/* spdif controls */
1429static snd_kcontrol_new_t snd_es1371_mixer_spdif[] __devinitdata = {
10e8d78a 1430 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1da177e4 1431 {
5549d549 1432 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1433 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1434 .info = snd_ens1373_spdif_info,
1435 .get = snd_ens1373_spdif_default_get,
1436 .put = snd_ens1373_spdif_default_put,
1437 },
1438 {
1439 .access = SNDRV_CTL_ELEM_ACCESS_READ,
5549d549 1440 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1441 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1442 .info = snd_ens1373_spdif_info,
1443 .get = snd_ens1373_spdif_mask_get
1444 },
1445 {
5549d549 1446 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1447 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1448 .info = snd_ens1373_spdif_info,
1449 .get = snd_ens1373_spdif_stream_get,
1450 .put = snd_ens1373_spdif_stream_put
1451 },
1452};
1453
1454
1455static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1456{
1457 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1458 uinfo->count = 1;
1459 uinfo->value.integer.min = 0;
1460 uinfo->value.integer.max = 1;
1461 return 0;
1462}
1463
1464static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1465{
1466 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1467 int val = 0;
1468
1469 spin_lock_irq(&ensoniq->reg_lock);
1470 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1471 val = 1;
1472 ucontrol->value.integer.value[0] = val;
1473 spin_unlock_irq(&ensoniq->reg_lock);
1474 return 0;
1475}
1476
1477static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1478{
1479 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1480 unsigned int nval1;
1481 int change;
1482
1483 nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1484 spin_lock_irq(&ensoniq->reg_lock);
1485 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1486 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1487 ensoniq->cssr |= nval1;
1488 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1489 spin_unlock_irq(&ensoniq->reg_lock);
1490 return change;
1491}
1492
1493static snd_kcontrol_new_t snd_ens1373_rear __devinitdata =
1494{
1495 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1496 .name = "AC97 2ch->4ch Copy Switch",
1497 .info = snd_es1373_rear_info,
1498 .get = snd_es1373_rear_get,
1499 .put = snd_es1373_rear_put,
1500};
1501
1502static int snd_es1373_line_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1503{
1504 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1505 uinfo->count = 1;
1506 uinfo->value.integer.min = 0;
1507 uinfo->value.integer.max = 1;
1508 return 0;
1509}
1510
1511static int snd_es1373_line_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1512{
1513 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1514 int val = 0;
1515
1516 spin_lock_irq(&ensoniq->reg_lock);
1517 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1518 val = 1;
1519 ucontrol->value.integer.value[0] = val;
1520 spin_unlock_irq(&ensoniq->reg_lock);
1521 return 0;
1522}
1523
1524static int snd_es1373_line_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1525{
1526 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1527 int changed;
1528 unsigned int ctrl;
1529
1530 spin_lock_irq(&ensoniq->reg_lock);
1531 ctrl = ensoniq->ctrl;
1532 if (ucontrol->value.integer.value[0])
1533 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1534 else
1535 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1536 changed = (ctrl != ensoniq->ctrl);
1537 if (changed)
1538 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1539 spin_unlock_irq(&ensoniq->reg_lock);
1540 return changed;
1541}
1542
1543static snd_kcontrol_new_t snd_ens1373_line __devinitdata =
1544{
1545 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1546 .name = "Line In->Rear Out Switch",
1547 .info = snd_es1373_line_info,
1548 .get = snd_es1373_line_get,
1549 .put = snd_es1373_line_put,
1550};
1551
1552static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97)
1553{
1554 ensoniq_t *ensoniq = ac97->private_data;
1555 ensoniq->u.es1371.ac97 = NULL;
1556}
1557
1558static struct {
1559 unsigned short vid; /* vendor ID */
1560 unsigned short did; /* device ID */
1561 unsigned char rev; /* revision */
1562} es1371_spdif_present[] __devinitdata = {
1563 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1564 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1565 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1566 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1567 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1568 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1569};
1570
1571static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
1572{
1573 snd_card_t *card = ensoniq->card;
1574 ac97_bus_t *pbus;
1575 ac97_template_t ac97;
1576 int err, idx;
1577 static ac97_bus_ops_t ops = {
1578 .write = snd_es1371_codec_write,
1579 .read = snd_es1371_codec_read,
072c0119 1580 .wait = snd_es1371_codec_wait,
1da177e4
LT		 1581 };
1582
1583 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1584 return err;
1585
1586 memset(&ac97, 0, sizeof(ac97));
1587 ac97.private_data = ensoniq;
1588 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1589 ac97.scaps = AC97_SCAP_AUDIO;
1590 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1591 return err;
1592 for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1593 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1594 ensoniq->pci->device == es1371_spdif_present[idx].did &&
1595 ensoniq->rev == es1371_spdif_present[idx].rev) {
1596 snd_kcontrol_t *kctl;
1597 int i, index = 0;
1598
1599 ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF;
1600 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1601
1602 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1603 index++;
1604
1605 for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1606 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1607 if (! kctl)
1608 return -ENOMEM;
1609 kctl->id.index = index;
1610 if ((err = snd_ctl_add(card, kctl)) < 0)
1611 return err;
1612 }
1613 break;
1614 }
1615 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1616 /* mirror rear to front speakers */
1617 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1618 ensoniq->cssr |= ES_1373_REAR_BIT26;
1619 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1620 if (err < 0)
1621 return err;
1622 }
1623 if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1624 (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1625 ((ensoniq->subsystem_vendor_id == 0x1458) &&
1626 (ensoniq->subsystem_device_id == 0xa000))) { /* GA-8IEXP */
1627 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1628 if (err < 0)
1629 return err;
1630 }
1631
1632 return 0;
1633}
1634
1635#endif /* CHIP1371 */
1636
1637/* generic control callbacks for ens1370 */
1638#ifdef CHIP1370
1639#define ENSONIQ_CONTROL(xname, mask) \
1640{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1641 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1642 .private_value = mask }
1643
1644static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1645{
1646 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1647 uinfo->count = 1;
1648 uinfo->value.integer.min = 0;
1649 uinfo->value.integer.max = 1;
1650 return 0;
1651}
1652
1653static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1654{
1655 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1656 int mask = kcontrol->private_value;
1657
1658 spin_lock_irq(&ensoniq->reg_lock);
1659 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1660 spin_unlock_irq(&ensoniq->reg_lock);
1661 return 0;
1662}
1663
1664static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1665{
1666 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1667 int mask = kcontrol->private_value;
1668 unsigned int nval;
1669 int change;
1670
1671 nval = ucontrol->value.integer.value[0] ? mask : 0;
1672 spin_lock_irq(&ensoniq->reg_lock);
1673 change = (ensoniq->ctrl & mask) != nval;
1674 ensoniq->ctrl &= ~mask;
1675 ensoniq->ctrl |= nval;
1676 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1677 spin_unlock_irq(&ensoniq->reg_lock);
1678 return change;
1679}
1680
1681/*
1682 * ENS1370 mixer
1683 */
1684
1685static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = {
1686ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1687ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1688};
1689
1690#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1691
1692static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531)
1693{
1694 ensoniq_t *ensoniq = ak4531->private_data;
1695 ensoniq->u.es1370.ak4531 = NULL;
1696}
1697
1698static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq)
1699{
1700 snd_card_t *card = ensoniq->card;
1701 ak4531_t ak4531;
1702 unsigned int idx;
1703 int err;
1704
1705 /* try reset AK4531 */
1706 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1707 inw(ES_REG(ensoniq, 1370_CODEC));
1708 udelay(100);
1709 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1710 inw(ES_REG(ensoniq, 1370_CODEC));
1711 udelay(100);
1712
1713 memset(&ak4531, 0, sizeof(ak4531));
1714 ak4531.write = snd_es1370_codec_write;
1715 ak4531.private_data = ensoniq;
1716 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1717 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1718 return err;
1719 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1720 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1721 if (err < 0)
1722 return err;
1723 }
1724 return 0;
1725}
1726
1727#endif /* CHIP1370 */
1728
1729#ifdef SUPPORT_JOYSTICK
1730
1731#ifdef CHIP1371
1732static int __devinit snd_ensoniq_get_joystick_port(int dev)
1733{
1734 switch (joystick_port[dev]) {
1735 case 0: /* disabled */
1736 case 1: /* auto-detect */
1737 case 0x200:
1738 case 0x208:
1739 case 0x210:
1740 case 0x218:
1741 return joystick_port[dev];
1742
1743 default:
1744 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1745 return 0;
1746 }
1747}
1748#else
1749static inline int snd_ensoniq_get_joystick_port(int dev)
1750{
1751 return joystick[dev] ? 0x200 : 0;
1752}
1753#endif
1754
1755static int __devinit snd_ensoniq_create_gameport(ensoniq_t *ensoniq, int dev)
1756{
1757 struct gameport *gp;
1758 int io_port;
1759
1760 io_port = snd_ensoniq_get_joystick_port(dev);
1761
1762 switch (io_port) {
1763 case 0:
1764 return -ENOSYS;
1765
1766 case 1: /* auto_detect */
1767 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1768 if (request_region(io_port, 8, "ens137x: gameport"))
1769 break;
1770 if (io_port > 0x218) {
1771 printk(KERN_WARNING "ens137x: no gameport ports available\n");
1772 return -EBUSY;
1773 }
1774 break;
1775
1776 default:
1777 if (!request_region(io_port, 8, "ens137x: gameport")) {
1778 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n", io_port);
1779 return -EBUSY;
1780 }
1781 break;
1782 }
1783
1784 ensoniq->gameport = gp = gameport_allocate_port();
1785 if (!gp) {
1786 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1787 release_region(io_port, 8);
1788 return -ENOMEM;
1789 }
1790
1791 gameport_set_name(gp, "ES137x");
1792 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1793 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1794 gp->io = io_port;
1795
1796 ensoniq->ctrl |= ES_JYSTK_EN;
1797#ifdef CHIP1371
1798 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1799 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1800#endif
1801 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1802
1803 gameport_register_port(ensoniq->gameport);
1804
1805 return 0;
1806}
1807
1808static void snd_ensoniq_free_gameport(ensoniq_t *ensoniq)
1809{
1810 if (ensoniq->gameport) {
1811 int port = ensoniq->gameport->io;
1812
1813 gameport_unregister_port(ensoniq->gameport);
1814 ensoniq->gameport = NULL;
1815 ensoniq->ctrl &= ~ES_JYSTK_EN;
1816 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1817 release_region(port, 8);
1818 }
1819}
1820#else
1821static inline int snd_ensoniq_create_gameport(ensoniq_t *ensoniq, long port) { return -ENOSYS; }
1822static inline void snd_ensoniq_free_gameport(ensoniq_t *ensoniq) { }
1823#endif /* SUPPORT_JOYSTICK */
1824
1825/*
1826
1827 */
1828
1829static void snd_ensoniq_proc_read(snd_info_entry_t *entry,
1830 snd_info_buffer_t * buffer)
1831{
1832 ensoniq_t *ensoniq = entry->private_data;
1833
1834#ifdef CHIP1370
1835 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1836#else
1837 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1838#endif
1839 snd_iprintf(buffer, "Joystick enable : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1840#ifdef CHIP1370
1841 snd_iprintf(buffer, "MIC +5V bias : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1842 snd_iprintf(buffer, "Line In to AOUT : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1843#else
1844 snd_iprintf(buffer, "Joystick port : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1845#endif
1846}
1847
1848static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq)
1849{
1850 snd_info_entry_t *entry;
1851
1852 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1853 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1854}
1855
1856/*
1857
1858 */
1859
1860static int snd_ensoniq_free(ensoniq_t *ensoniq)
1861{
1862 snd_ensoniq_free_gameport(ensoniq);
1863 if (ensoniq->irq < 0)
1864 goto __hw_end;
1865#ifdef CHIP1370
1866 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1867 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1868#else
1869 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1870 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1871#endif
1872 synchronize_irq(ensoniq->irq);
1873 pci_set_power_state(ensoniq->pci, 3);
1874 __hw_end:
1875#ifdef CHIP1370
1876 if (ensoniq->dma_bug.area)
1877 snd_dma_free_pages(&ensoniq->dma_bug);
1878#endif
1879 if (ensoniq->irq >= 0)
1880 free_irq(ensoniq->irq, (void *)ensoniq);
1881 pci_release_regions(ensoniq->pci);
1882 pci_disable_device(ensoniq->pci);
1883 kfree(ensoniq);
1884 return 0;
1885}
1886
1887static int snd_ensoniq_dev_free(snd_device_t *device)
1888{
1889 ensoniq_t *ensoniq = device->device_data;
1890 return snd_ensoniq_free(ensoniq);
1891}
1892
1893#ifdef CHIP1371
1894static struct {
1895 unsigned short svid; /* subsystem vendor ID */
1896 unsigned short sdid; /* subsystem device ID */
1897} es1371_amplifier_hack[] = {
1898 { .svid = 0x107b, .sdid = 0x2150 }, /* Gateway Solo 2150 */
1899 { .svid = 0x13bd, .sdid = 0x100c }, /* EV1938 on Mebius PC-MJ100V */
1900 { .svid = 0x1102, .sdid = 0x5938 }, /* Targa Xtender300 */
1901 { .svid = 0x1102, .sdid = 0x8938 }, /* IPC Topnote G notebook */
1902 { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1903};
1904static struct {
1905 unsigned short vid; /* vendor ID */
1906 unsigned short did; /* device ID */
1907 unsigned char rev; /* revision */
1908} es1371_ac97_reset_hack[] = {
1909 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1910 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1911 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1912 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1913 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1914 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1915};
1916#endif
1917
f31a31b9
KB		 1918static void snd_ensoniq_chip_init(ensoniq_t * ensoniq)
1919{
1920#ifdef CHIP1371
1921 int idx;
1922 struct pci_dev *pci = ensoniq->pci;
1923#endif
1924// this code was part of snd_ensoniq_create before intruduction of suspend/resume
1925#ifdef CHIP1370
1926 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1927 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1928 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1929 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1930 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1931#else
1932 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1933 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1934 outl(0, ES_REG(ensoniq, 1371_LEGACY));
1935 for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1936 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
1937 pci->device == es1371_ac97_reset_hack[idx].did &&
1938 ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
1939 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1940 /* need to delay around 20ms(bleech) to give
1941 some CODECs enough time to wakeup */
1942 msleep(20);
1943 break;
1944 }
1945 /* AC'97 warm reset to start the bitclk */
1946 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1947 inl(ES_REG(ensoniq, CONTROL));
1948 udelay(20);
1949 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1950 /* Init the sample rate converter */
1951 snd_es1371_wait_src_ready(ensoniq);
1952 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1953 for (idx = 0; idx < 0x80; idx++)
1954 snd_es1371_src_write(ensoniq, idx, 0);
1955 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1956 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1957 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1958 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1959 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1960 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1961 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1962 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1963 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1964 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1965 snd_es1371_adc_rate(ensoniq, 22050);
1966 snd_es1371_dac1_rate(ensoniq, 22050);
1967 snd_es1371_dac2_rate(ensoniq, 22050);
1968 /* WARNING:
1969 * enabling the sample rate converter without properly programming
1970 * its parameters causes the chip to lock up (the SRC busy bit will
1971 * be stuck high, and I've found no way to rectify this other than
1972 * power cycle) - Thomas Sailer
1973 */
1974 snd_es1371_wait_src_ready(ensoniq);
1975 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
1976 /* try reset codec directly */
1977 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
1978#endif
1979 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
1980 outb(0x00, ES_REG(ensoniq, UART_RES));
1981 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1982 synchronize_irq(ensoniq->irq);
1983}
1984
1985#ifdef CONFIG_PM
1986static int snd_ensoniq_suspend (snd_card_t * card,
1987 pm_message_t state)
1988{
1989 ensoniq_t *ensoniq = card->pm_private_data;
1990
1991 snd_pcm_suspend_all(ensoniq->pcm1);
1992 snd_pcm_suspend_all(ensoniq->pcm2);
1993
1994#ifdef CHIP1371
1995 if (ensoniq->u.es1371.ac97)
1996 snd_ac97_suspend(ensoniq->u.es1371.ac97);
1997#else
1998 /* FIXME */
1999#endif
2000 pci_set_power_state(ensoniq->pci, 3);
2001 pci_disable_device(ensoniq->pci);
2002 // snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); // only 2.6.10
2003 return 0;
2004}
2005
2006static int snd_ensoniq_resume (snd_card_t * card
2007 )
2008{
2009 ensoniq_t *ensoniq = card->pm_private_data;
2010
2011 pci_enable_device(ensoniq->pci);
2012 pci_set_power_state(ensoniq->pci, 0);
2013 pci_set_master(ensoniq->pci);
2014
2015 snd_ensoniq_chip_init(ensoniq);
2016
2017#ifdef CHIP1371
2018 if (ensoniq->u.es1371.ac97)
2019 snd_ac97_resume(ensoniq->u.es1371.ac97);
2020#else
2021 /* FIXME */
2022#endif
2023 // snd_power_change_state(card, SNDRV_CTL_POWER_D0); // only 2.6.10
2024 return 0;
2025}
2026#endif /* CONFIG_PM */
2027
2028
1da177e4
LT		 2029static int __devinit snd_ensoniq_create(snd_card_t * card,
2030 struct pci_dev *pci,
2031 ensoniq_t ** rensoniq)
2032{
2033 ensoniq_t *ensoniq;
2034 unsigned short cmdw;
2035 unsigned char cmdb;
2036#ifdef CHIP1371
2037 int idx;
2038#endif
2039 int err;
2040 static snd_device_ops_t ops = {
2041 .dev_free = snd_ensoniq_dev_free,
2042 };
2043
2044 *rensoniq = NULL;
2045 if ((err = pci_enable_device(pci)) < 0)
2046 return err;
e560d8d8 2047 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
1da177e4
LT		 2048 if (ensoniq == NULL) {
2049 pci_disable_device(pci);
2050 return -ENOMEM;
2051 }
2052 spin_lock_init(&ensoniq->reg_lock);
2053 init_MUTEX(&ensoniq->src_mutex);
2054 ensoniq->card = card;
2055 ensoniq->pci = pci;
2056 ensoniq->irq = -1;
2057 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2058 kfree(ensoniq);
2059 pci_disable_device(pci);
2060 return err;
2061 }
2062 ensoniq->port = pci_resource_start(pci, 0);
2063 if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) {
99b359ba 2064 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2065 snd_ensoniq_free(ensoniq);
2066 return -EBUSY;
2067 }
2068 ensoniq->irq = pci->irq;
2069#ifdef CHIP1370
2070 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2071 16, &ensoniq->dma_bug) < 0) {
99b359ba 2072 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
1da177e4
LT		 2073 snd_ensoniq_free(ensoniq);
2074 return -EBUSY;
2075 }
2076#endif
2077 pci_set_master(pci);
2078 pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
2079 ensoniq->rev = cmdb;
2080 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
2081 ensoniq->subsystem_vendor_id = cmdw;
2082 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
2083 ensoniq->subsystem_device_id = cmdw;
2084#ifdef CHIP1370
2085#if 0
2086 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2087#else /* get microphone working */
2088 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2089#endif
2090 ensoniq->sctrl = 0;
1da177e4
LT		 2091#else
2092 ensoniq->ctrl = 0;
2093 ensoniq->sctrl = 0;
2094 ensoniq->cssr = 0;
2095 for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
2096 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
2097 ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2098 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2099 break;
2100 }
1da177e4
LT		 2101 for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2102 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2103 pci->device == es1371_ac97_reset_hack[idx].did &&
2104 ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
1da177e4 2105 ensoniq->cssr |= ES_1371_ST_AC97_RST;
1da177e4
LT		 2106 break;
2107 }
1da177e4 2108#endif
f31a31b9
KB		 2109
2110 snd_ensoniq_chip_init(ensoniq);
1da177e4
LT		 2111
2112 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2113 snd_ensoniq_free(ensoniq);
2114 return err;
2115 }
2116
2117 snd_ensoniq_proc_init(ensoniq);
2118
f31a31b9
KB		 2119 snd_card_set_pm_callback(card, snd_ensoniq_suspend, snd_ensoniq_resume, ensoniq);
2120
1da177e4
LT		 2121 snd_card_set_dev(card, &pci->dev);
2122
2123 *rensoniq = ensoniq;
2124 return 0;
2125}
2126
2127/*
2128 * MIDI section
2129 */
2130
2131static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq)
2132{
2133 snd_rawmidi_t * rmidi = ensoniq->rmidi;
2134 unsigned char status, mask, byte;
2135
2136 if (rmidi == NULL)
2137 return;
2138 /* do Rx at first */
2139 spin_lock(&ensoniq->reg_lock);
2140 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2141 while (mask) {
2142 status = inb(ES_REG(ensoniq, UART_STATUS));
2143 if ((status & mask) == 0)
2144 break;
2145 byte = inb(ES_REG(ensoniq, UART_DATA));
2146 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2147 }
2148 spin_unlock(&ensoniq->reg_lock);
2149
2150 /* do Tx at second */
2151 spin_lock(&ensoniq->reg_lock);
2152 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2153 while (mask) {
2154 status = inb(ES_REG(ensoniq, UART_STATUS));
2155 if ((status & mask) == 0)
2156 break;
2157 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2158 ensoniq->uartc &= ~ES_TXINTENM;
2159 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2160 mask &= ~ES_TXRDY;
2161 } else {
2162 outb(byte, ES_REG(ensoniq, UART_DATA));
2163 }
2164 }
2165 spin_unlock(&ensoniq->reg_lock);
2166}
2167
2168static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream)
2169{
2170 ensoniq_t *ensoniq = substream->rmidi->private_data;
2171
2172 spin_lock_irq(&ensoniq->reg_lock);
2173 ensoniq->uartm |= ES_MODE_INPUT;
2174 ensoniq->midi_input = substream;
2175 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2176 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2177 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2178 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2179 }
2180 spin_unlock_irq(&ensoniq->reg_lock);
2181 return 0;
2182}
2183
2184static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream)
2185{
2186 ensoniq_t *ensoniq = substream->rmidi->private_data;
2187
2188 spin_lock_irq(&ensoniq->reg_lock);
2189 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2190 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2191 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2192 } else {
2193 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2194 }
2195 ensoniq->midi_input = NULL;
2196 ensoniq->uartm &= ~ES_MODE_INPUT;
2197 spin_unlock_irq(&ensoniq->reg_lock);
2198 return 0;
2199}
2200
2201static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream)
2202{
2203 ensoniq_t *ensoniq = substream->rmidi->private_data;
2204
2205 spin_lock_irq(&ensoniq->reg_lock);
2206 ensoniq->uartm |= ES_MODE_OUTPUT;
2207 ensoniq->midi_output = substream;
2208 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2209 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2210 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2211 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2212 }
2213 spin_unlock_irq(&ensoniq->reg_lock);
2214 return 0;
2215}
2216
2217static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream)
2218{
2219 ensoniq_t *ensoniq = substream->rmidi->private_data;
2220
2221 spin_lock_irq(&ensoniq->reg_lock);
2222 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2223 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2224 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2225 } else {
2226 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2227 }
2228 ensoniq->midi_output = NULL;
2229 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2230 spin_unlock_irq(&ensoniq->reg_lock);
2231 return 0;
2232}
2233
2234static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2235{
2236 unsigned long flags;
2237 ensoniq_t *ensoniq = substream->rmidi->private_data;
2238 int idx;
2239
2240 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2241 if (up) {
2242 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2243 /* empty input FIFO */
2244 for (idx = 0; idx < 32; idx++)
2245 inb(ES_REG(ensoniq, UART_DATA));
2246 ensoniq->uartc |= ES_RXINTEN;
2247 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2248 }
2249 } else {
2250 if (ensoniq->uartc & ES_RXINTEN) {
2251 ensoniq->uartc &= ~ES_RXINTEN;
2252 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2253 }
2254 }
2255 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2256}
2257
2258static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2259{
2260 unsigned long flags;
2261 ensoniq_t *ensoniq = substream->rmidi->private_data;
2262 unsigned char byte;
2263
2264 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2265 if (up) {
2266 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2267 ensoniq->uartc |= ES_TXINTENO(1);
2268 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2269 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2270 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2271 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2272 ensoniq->uartc &= ~ES_TXINTENM;
2273 } else {
2274 outb(byte, ES_REG(ensoniq, UART_DATA));
2275 }
2276 }
2277 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2278 }
2279 } else {
2280 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2281 ensoniq->uartc &= ~ES_TXINTENM;
2282 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2283 }
2284 }
2285 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2286}
2287
2288static snd_rawmidi_ops_t snd_ensoniq_midi_output =
2289{
2290 .open = snd_ensoniq_midi_output_open,
2291 .close = snd_ensoniq_midi_output_close,
2292 .trigger = snd_ensoniq_midi_output_trigger,
2293};
2294
2295static snd_rawmidi_ops_t snd_ensoniq_midi_input =
2296{
2297 .open = snd_ensoniq_midi_input_open,
2298 .close = snd_ensoniq_midi_input_close,
2299 .trigger = snd_ensoniq_midi_input_trigger,
2300};
2301
2302static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi)
2303{
2304 snd_rawmidi_t *rmidi;
2305 int err;
2306
2307 if (rrawmidi)
2308 *rrawmidi = NULL;
2309 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2310 return err;
2311#ifdef CHIP1370
2312 strcpy(rmidi->name, "ES1370");
2313#else
2314 strcpy(rmidi->name, "ES1371");
2315#endif
2316 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2317 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2318 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2319 rmidi->private_data = ensoniq;
2320 ensoniq->rmidi = rmidi;
2321 if (rrawmidi)
2322 *rrawmidi = rmidi;
2323 return 0;
2324}
2325
2326/*
2327 * Interrupt handler
2328 */
2329
2330static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2331{
2332 ensoniq_t *ensoniq = dev_id;
2333 unsigned int status, sctrl;
2334
2335 if (ensoniq == NULL)
2336 return IRQ_NONE;
2337
2338 status = inl(ES_REG(ensoniq, STATUS));
2339 if (!(status & ES_INTR))
2340 return IRQ_NONE;
2341
2342 spin_lock(&ensoniq->reg_lock);
2343 sctrl = ensoniq->sctrl;
2344 if (status & ES_DAC1)
2345 sctrl &= ~ES_P1_INT_EN;
2346 if (status & ES_DAC2)
2347 sctrl &= ~ES_P2_INT_EN;
2348 if (status & ES_ADC)
2349 sctrl &= ~ES_R1_INT_EN;
2350 outl(sctrl, ES_REG(ensoniq, SERIAL));
2351 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2352 spin_unlock(&ensoniq->reg_lock);
2353
2354 if (status & ES_UART)
2355 snd_ensoniq_midi_interrupt(ensoniq);
2356 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2357 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2358 if ((status & ES_ADC) && ensoniq->capture_substream)
2359 snd_pcm_period_elapsed(ensoniq->capture_substream);
2360 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2361 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2362 return IRQ_HANDLED;
2363}
2364
2365static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2366 const struct pci_device_id *pci_id)
2367{
2368 static int dev;
2369 snd_card_t *card;
2370 ensoniq_t *ensoniq;
2371 int err, pcm_devs[2];
2372
2373 if (dev >= SNDRV_CARDS)
2374 return -ENODEV;
2375 if (!enable[dev]) {
2376 dev++;
2377 return -ENOENT;
2378 }
2379
2380 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2381 if (card == NULL)
2382 return -ENOMEM;
2383
2384 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2385 snd_card_free(card);
2386 return err;
2387 }
2388
2389 pcm_devs[0] = 0; pcm_devs[1] = 1;
2390#ifdef CHIP1370
2391 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2392 snd_card_free(card);
2393 return err;
2394 }
2395#endif
2396#ifdef CHIP1371
2397 if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2398 snd_card_free(card);
2399 return err;
2400 }
2401#endif
2402 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2403 snd_card_free(card);
2404 return err;
2405 }
2406 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2407 snd_card_free(card);
2408 return err;
2409 }
2410 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2411 snd_card_free(card);
2412 return err;
2413 }
2414
2415 snd_ensoniq_create_gameport(ensoniq, dev);
2416
2417 strcpy(card->driver, DRIVER_NAME);
2418
2419 strcpy(card->shortname, "Ensoniq AudioPCI");
2420 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2421 card->shortname,
2422 card->driver,
2423 ensoniq->port,
2424 ensoniq->irq);
2425
2426 if ((err = snd_card_register(card)) < 0) {
2427 snd_card_free(card);
2428 return err;
2429 }
2430
2431 pci_set_drvdata(pci, card);
2432 dev++;
2433 return 0;
2434}
2435
2436static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2437{
2438 snd_card_free(pci_get_drvdata(pci));
2439 pci_set_drvdata(pci, NULL);
2440}
2441
2442static struct pci_driver driver = {
2443 .name = DRIVER_NAME,
2444 .id_table = snd_audiopci_ids,
2445 .probe = snd_audiopci_probe,
2446 .remove = __devexit_p(snd_audiopci_remove),
f31a31b9 2447 SND_PCI_PM_CALLBACKS
1da177e4
LT		 2448};
2449
2450static int __init alsa_card_ens137x_init(void)
2451{
01d25d46 2452 return pci_register_driver(&driver);
1da177e4
LT		 2453}
2454
2455static void __exit alsa_card_ens137x_exit(void)
2456{
2457 pci_unregister_driver(&driver);
2458}
2459
2460module_init(alsa_card_ens137x_init)
2461module_exit(alsa_card_ens137x_exit)
Linux 6.x block layer and io_uring tree(s)