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[ALSA] ac97 - Add extra IDs for headphone autosense
[linux-2.6-block.git] / sound / pci / ens1370.c
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1da177e4
LT		 1/*
2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4 * Thomas Sailer <sailer@ife.ee.ethz.ch>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
f31a31b9
KB		 22/* Power-Management-Code ( CONFIG_PM )
23 * for ens1371 only ( FIXME )
24 * derived from cs4281.c, atiixp.c and via82xx.c
25 * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
26 * by Kurt J. Bosch
27 */
28
1da177e4
LT		 29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <linux/gameport.h>
37#include <linux/moduleparam.h>
38#include <sound/core.h>
39#include <sound/control.h>
40#include <sound/pcm.h>
41#include <sound/rawmidi.h>
42#ifdef CHIP1371
43#include <sound/ac97_codec.h>
44#else
45#include <sound/ak4531_codec.h>
46#endif
47#include <sound/initval.h>
48#include <sound/asoundef.h>
49
50#ifndef CHIP1371
51#undef CHIP1370
52#define CHIP1370
53#endif
54
55#ifdef CHIP1370
56#define DRIVER_NAME "ENS1370"
57#else
58#define DRIVER_NAME "ENS1371"
59#endif
60
61
62MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
63MODULE_LICENSE("GPL");
64#ifdef CHIP1370
65MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
66MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
67 "{Creative Labs,SB PCI64/128 (ES1370)}}");
68#endif
69#ifdef CHIP1371
70MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
71MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
72 "{Ensoniq,AudioPCI ES1373},"
73 "{Creative Labs,Ectiva EV1938},"
74 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
75 "{Creative Labs,Vibra PCI128},"
76 "{Ectiva,EV1938}}");
77#endif
78
79#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
80#define SUPPORT_JOYSTICK
81#endif
82
83static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
84static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
85static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
86#ifdef SUPPORT_JOYSTICK
87#ifdef CHIP1371
88static int joystick_port[SNDRV_CARDS];
89#else
90static int joystick[SNDRV_CARDS];
91#endif
92#endif
93
94module_param_array(index, int, NULL, 0444);
95MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
96module_param_array(id, charp, NULL, 0444);
97MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
98module_param_array(enable, bool, NULL, 0444);
99MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
100#ifdef SUPPORT_JOYSTICK
101#ifdef CHIP1371
102module_param_array(joystick_port, int, NULL, 0444);
103MODULE_PARM_DESC(joystick_port, "Joystick port address.");
104#else
105module_param_array(joystick, bool, NULL, 0444);
106MODULE_PARM_DESC(joystick, "Enable joystick.");
107#endif
108#endif /* SUPPORT_JOYSTICK */
109
1da177e4
LT		 110/* ES1371 chip ID */
111/* This is a little confusing because all ES1371 compatible chips have the
112 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
113 This is only significant if you want to enable features on the later parts.
114 Yes, I know it's stupid and why didn't we use the sub IDs?
115*/
116#define ES1371REV_ES1373_A 0x04
117#define ES1371REV_ES1373_B 0x06
118#define ES1371REV_CT5880_A 0x07
119#define CT5880REV_CT5880_C 0x02
120#define CT5880REV_CT5880_D 0x03 /* ??? -jk */
121#define CT5880REV_CT5880_E 0x04 /* mw */
122#define ES1371REV_ES1371_B 0x09
123#define EV1938REV_EV1938_A 0x00
124#define ES1371REV_ES1373_8 0x08
125
126/*
127 * Direct registers
128 */
129
130#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
131
132#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
133#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
134#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
135#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
136#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
137#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
138#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
139#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
140#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
141#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
142#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
143#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
144#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
145#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
146#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
147#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
148#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
149#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
150#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
151#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
152#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
153#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
154#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
155#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
156#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
157#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
158#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
159#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
160#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
161#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
162#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
163#define ES_1371_PDLEVM (0x03<<8) /* mask for above */
164#define ES_BREQ (1<<7) /* memory bus request enable */
165#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
166#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
167#define ES_ADC_EN (1<<4) /* ADC capture channel enable */
168#define ES_UART_EN (1<<3) /* UART enable */
169#define ES_JYSTK_EN (1<<2) /* Joystick module enable */
170#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
171#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
172#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
173#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
174#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
175#define ES_INTR (1<<31) /* Interrupt is pending */
176#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
177#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
178#define ES_1373_REAR_BIT26 (1<<26)
179#define ES_1373_REAR_BIT24 (1<<24)
180#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
181#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
182#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
183#define ES_1371_TEST (1<<16) /* test ASIC */
184#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
185#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
186#define ES_1370_CBUSY (1<<9) /* CODEC is busy */
187#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
188#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
189#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
190#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
191#define ES_1371_MPWR (1<<5) /* power level interrupt pending */
192#define ES_MCCB (1<<4) /* CCB interrupt pending */
193#define ES_UART (1<<3) /* UART interrupt pending */
194#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
195#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
196#define ES_ADC (1<<0) /* ADC channel interrupt pending */
197#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
198#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
199#define ES_RXINT (1<<7) /* RX interrupt occurred */
200#define ES_TXINT (1<<2) /* TX interrupt occurred */
201#define ES_TXRDY (1<<1) /* transmitter ready */
202#define ES_RXRDY (1<<0) /* receiver ready */
203#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
204#define ES_RXINTEN (1<<7) /* RX interrupt enable */
205#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
206#define ES_TXINTENM (0x03<<5) /* mask for above */
207#define ES_TXINTENI(i) (((i)>>5)&0x03)
208#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
209#define ES_CNTRLM (0x03<<0) /* mask for above */
210#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
211#define ES_TEST_MODE (1<<0) /* test mode enabled */
212#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
213#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
214#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
215#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
216#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
217#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
218#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
219#define ES_1371_CODEC_RDY (1<<31) /* codec ready */
220#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
221#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
222#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
223#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
224#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
225
226#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
227#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
228#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
229#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
230#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
231#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
232#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
233#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
234#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
235#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
236#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
237#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
238#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
239
240#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
241#define ES_1371_JFAST (1<<31) /* fast joystick timing */
242#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
243#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
244#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
245#define ES_1371_VMPUM (0x03<<27) /* mask for above */
246#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
247#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
248#define ES_1371_VCDCM (0x03<<25) /* mask for above */
249#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
250#define ES_1371_FIRQ (1<<24) /* force an interrupt */
251#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
252#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
253#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
254#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
255#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
256#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
257#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
258#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
259#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
260#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
261#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
262#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
263
264#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
265
266#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
267#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
268#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
269#define ES_P2_END_INCM (0x07<<19) /* mask for above */
270#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
271#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
272#define ES_P2_ST_INCM (0x07<<16) /* mask for above */
273#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
274#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
275#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
276#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
277#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
278#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
279#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
280#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
281#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
282#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
283#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
284#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
285#define ES_R1_MODEM (0x03<<4) /* mask for above */
286#define ES_R1_MODEI(i) (((i)>>4)&0x03)
287#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
288#define ES_P2_MODEM (0x03<<2) /* mask for above */
289#define ES_P2_MODEI(i) (((i)>>2)&0x03)
290#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
291#define ES_P1_MODEM (0x03<<0) /* mask for above */
292#define ES_P1_MODEI(i) (((i)>>0)&0x03)
293
294#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
295#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
296#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
297#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
298#define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
299#define ES_REG_COUNTM (0xffff<<0)
300#define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
301
302#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
303#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
304#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
305#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
306#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
307#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
308#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
309#define ES_REG_FCURR_COUNTM (0xffff<<16)
310#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
311#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
312#define ES_REG_FSIZEM (0xffff<<0)
313#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
314#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
315#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
316
317#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
318#define ES_REG_UF_VALID (1<<8)
319#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
320#define ES_REG_UF_BYTEM (0xff<<0)
321#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
322
323
324/*
325 * Pages
326 */
327
328#define ES_PAGE_DAC 0x0c
329#define ES_PAGE_ADC 0x0d
330#define ES_PAGE_UART 0x0e
331#define ES_PAGE_UART1 0x0f
332
333/*
334 * Sample rate converter addresses
335 */
336
337#define ES_SMPREG_DAC1 0x70
338#define ES_SMPREG_DAC2 0x74
339#define ES_SMPREG_ADC 0x78
340#define ES_SMPREG_VOL_ADC 0x6c
341#define ES_SMPREG_VOL_DAC1 0x7c
342#define ES_SMPREG_VOL_DAC2 0x7e
343#define ES_SMPREG_TRUNC_N 0x00
344#define ES_SMPREG_INT_REGS 0x01
345#define ES_SMPREG_ACCUM_FRAC 0x02
346#define ES_SMPREG_VFREQ_FRAC 0x03
347
348/*
349 * Some contants
350 */
351
352#define ES_1370_SRCLOCK 1411200
353#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
354
355/*
356 * Open modes
357 */
358
359#define ES_MODE_PLAY1 0x0001
360#define ES_MODE_PLAY2 0x0002
361#define ES_MODE_CAPTURE 0x0004
362
363#define ES_MODE_OUTPUT 0x0001 /* for MIDI */
364#define ES_MODE_INPUT 0x0002 /* for MIDI */
365
366/*
367
368 */
369
eb3414b4 370struct ensoniq {
1da177e4
LT		 371 spinlock_t reg_lock;
372 struct semaphore src_mutex;
373
374 int irq;
375
376 unsigned long playback1size;
377 unsigned long playback2size;
378 unsigned long capture3size;
379
380 unsigned long port;
381 unsigned int mode;
382 unsigned int uartm; /* UART mode */
383
384 unsigned int ctrl; /* control register */
385 unsigned int sctrl; /* serial control register */
386 unsigned int cssr; /* control status register */
387 unsigned int uartc; /* uart control register */
388 unsigned int rev; /* chip revision */
389
390 union {
391#ifdef CHIP1371
392 struct {
eb3414b4 393 struct snd_ac97 *ac97;
1da177e4
LT		 394 } es1371;
395#else
396 struct {
397 int pclkdiv_lock;
eb3414b4 398 struct snd_ak4531 *ak4531;
1da177e4
LT		 399 } es1370;
400#endif
401 } u;
402
403 struct pci_dev *pci;
404 unsigned short subsystem_vendor_id;
405 unsigned short subsystem_device_id;
eb3414b4
TI		 406 struct snd_card *card;
407 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
408 struct snd_pcm *pcm2; /* DAC2 PCM */
409 struct snd_pcm_substream *playback1_substream;
410 struct snd_pcm_substream *playback2_substream;
411 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 412 unsigned int p1_dma_size;
413 unsigned int p2_dma_size;
414 unsigned int c_dma_size;
415 unsigned int p1_period_size;
416 unsigned int p2_period_size;
417 unsigned int c_period_size;
eb3414b4
TI		 418 struct snd_rawmidi *rmidi;
419 struct snd_rawmidi_substream *midi_input;
420 struct snd_rawmidi_substream *midi_output;
1da177e4
LT		 421
422 unsigned int spdif;
423 unsigned int spdif_default;
424 unsigned int spdif_stream;
425
426#ifdef CHIP1370
427 struct snd_dma_buffer dma_bug;
428#endif
429
430#ifdef SUPPORT_JOYSTICK
431 struct gameport *gameport;
432#endif
433};
434
435static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
436
437static struct pci_device_id snd_audiopci_ids[] = {
438#ifdef CHIP1370
439 { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1370 */
440#endif
441#ifdef CHIP1371
442 { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1371 */
443 { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1373 - CT5880 */
444 { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ectiva EV1938 */
445#endif
446 { 0, }
447};
448
449MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
450
451/*
452 * constants
453 */
454
455#define POLL_COUNT 0xa000
456
457#ifdef CHIP1370
458static unsigned int snd_es1370_fixed_rates[] =
459 {5512, 11025, 22050, 44100};
eb3414b4 460static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
1da177e4
LT		 461 .count = 4,
462 .list = snd_es1370_fixed_rates,
463 .mask = 0,
464};
eb3414b4 465static struct snd_ratnum es1370_clock = {
1da177e4
LT		 466 .num = ES_1370_SRCLOCK,
467 .den_min = 29,
468 .den_max = 353,
469 .den_step = 1,
470};
eb3414b4 471static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
1da177e4
LT		 472 .nrats = 1,
473 .rats = &es1370_clock,
474};
475#else
eb3414b4 476static struct snd_ratden es1371_dac_clock = {
1da177e4
LT		 477 .num_min = 3000 * (1 << 15),
478 .num_max = 48000 * (1 << 15),
479 .num_step = 3000,
480 .den = 1 << 15,
481};
eb3414b4 482static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
1da177e4
LT		 483 .nrats = 1,
484 .rats = &es1371_dac_clock,
485};
eb3414b4 486static struct snd_ratnum es1371_adc_clock = {
1da177e4
LT		 487 .num = 48000 << 15,
488 .den_min = 32768,
489 .den_max = 393216,
490 .den_step = 1,
491};
eb3414b4 492static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
1da177e4
LT		 493 .nrats = 1,
494 .rats = &es1371_adc_clock,
495};
496#endif
497static const unsigned int snd_ensoniq_sample_shift[] =
498 {0, 1, 1, 2};
499
500/*
501 * common I/O routines
502 */
503
504#ifdef CHIP1371
505
eb3414b4 506static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
1da177e4
LT		 507{
508 unsigned int t, r = 0;
509
510 for (t = 0; t < POLL_COUNT; t++) {
511 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
512 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
513 return r;
514 cond_resched();
515 }
eb3414b4
TI		 516 snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n",
517 ES_REG(ensoniq, 1371_SMPRATE), r);
1da177e4
LT		 518 return 0;
519}
520
eb3414b4 521static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
1da177e4
LT		 522{
523 unsigned int temp, i, orig, r;
524
525 /* wait for ready */
526 temp = orig = snd_es1371_wait_src_ready(ensoniq);
527
528 /* expose the SRC state bits */
529 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
530 ES_1371_DIS_P2 | ES_1371_DIS_R1);
531 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
532 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
533
534 /* now, wait for busy and the correct time to read */
535 temp = snd_es1371_wait_src_ready(ensoniq);
536
537 if ((temp & 0x00870000) != 0x00010000) {
538 /* wait for the right state */
539 for (i = 0; i < POLL_COUNT; i++) {
540 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
541 if ((temp & 0x00870000) == 0x00010000)
542 break;
543 }
544 }
545
546 /* hide the state bits */
547 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
548 ES_1371_DIS_P2 | ES_1371_DIS_R1);
549 r |= ES_1371_SRC_RAM_ADDRO(reg);
550 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
551
552 return temp;
553}
554
eb3414b4 555static void snd_es1371_src_write(struct ensoniq * ensoniq,
1da177e4
LT		 556 unsigned short reg, unsigned short data)
557{
558 unsigned int r;
559
560 r = snd_es1371_wait_src_ready(ensoniq) &
561 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
562 ES_1371_DIS_P2 | ES_1371_DIS_R1);
563 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
564 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
565}
566
567#endif /* CHIP1371 */
568
569#ifdef CHIP1370
570
eb3414b4 571static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
1da177e4
LT		 572 unsigned short reg, unsigned short val)
573{
eb3414b4 574 struct ensoniq *ensoniq = ak4531->private_data;
1da177e4
LT		 575 unsigned long end_time = jiffies + HZ / 10;
576
577#if 0
eb3414b4
TI		 578 printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
579 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
1da177e4
LT		 580#endif
581 do {
582 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
583 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
584 return;
585 }
8433a509 586 schedule_timeout_uninterruptible(1);
1da177e4 587 } while (time_after(end_time, jiffies));
eb3414b4
TI		 588 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
589 inl(ES_REG(ensoniq, STATUS)));
1da177e4
LT		 590}
591
592#endif /* CHIP1370 */
593
594#ifdef CHIP1371
595
eb3414b4 596static void snd_es1371_codec_write(struct snd_ac97 *ac97,
1da177e4
LT		 597 unsigned short reg, unsigned short val)
598{
eb3414b4 599 struct ensoniq *ensoniq = ac97->private_data;
1da177e4
LT		 600 unsigned int t, x;
601
602 down(&ensoniq->src_mutex);
603 for (t = 0; t < POLL_COUNT; t++) {
604 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
605 /* save the current state for latter */
606 x = snd_es1371_wait_src_ready(ensoniq);
607 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
608 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
609 ES_REG(ensoniq, 1371_SMPRATE));
610 /* wait for not busy (state 0) first to avoid
611 transition states */
612 for (t = 0; t < POLL_COUNT; t++) {
eb3414b4
TI		 613 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
614 0x00000000)
1da177e4
LT		 615 break;
616 }
617 /* wait for a SAFE time to write addr/data and then do it, dammit */
618 for (t = 0; t < POLL_COUNT; t++) {
eb3414b4
TI		 619 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
620 0x00010000)
1da177e4
LT		 621 break;
622 }
623 outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
624 /* restore SRC reg */
625 snd_es1371_wait_src_ready(ensoniq);
626 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
627 up(&ensoniq->src_mutex);
628 return;
629 }
630 }
631 up(&ensoniq->src_mutex);
eb3414b4
TI		 632 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
633 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
1da177e4
LT		 634}
635
eb3414b4 636static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
1da177e4
LT		 637 unsigned short reg)
638{
eb3414b4 639 struct ensoniq *ensoniq = ac97->private_data;
1da177e4
LT		 640 unsigned int t, x, fail = 0;
641
642 __again:
643 down(&ensoniq->src_mutex);
644 for (t = 0; t < POLL_COUNT; t++) {
645 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
646 /* save the current state for latter */
647 x = snd_es1371_wait_src_ready(ensoniq);
648 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
649 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
650 ES_REG(ensoniq, 1371_SMPRATE));
651 /* wait for not busy (state 0) first to avoid
652 transition states */
653 for (t = 0; t < POLL_COUNT; t++) {
eb3414b4
TI		 654 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
655 0x00000000)
1da177e4
LT		 656 break;
657 }
658 /* wait for a SAFE time to write addr/data and then do it, dammit */
659 for (t = 0; t < POLL_COUNT; t++) {
eb3414b4
TI		 660 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
661 0x00010000)
1da177e4
LT		 662 break;
663 }
664 outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
665 /* restore SRC reg */
666 snd_es1371_wait_src_ready(ensoniq);
667 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
668 /* wait for WIP again */
669 for (t = 0; t < POLL_COUNT; t++) {
670 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
671 break;
672 }
673 /* now wait for the stinkin' data (RDY) */
674 for (t = 0; t < POLL_COUNT; t++) {
675 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
676 up(&ensoniq->src_mutex);
677 return ES_1371_CODEC_READ(x);
678 }
679 }
680 up(&ensoniq->src_mutex);
681 if (++fail > 10) {
eb3414b4
TI		 682 snd_printk(KERN_ERR "codec read timeout (final) "
683 "at 0x%lx, reg = 0x%x [0x%x]\n",
684 ES_REG(ensoniq, 1371_CODEC), reg,
685 inl(ES_REG(ensoniq, 1371_CODEC)));
1da177e4
LT		 686 return 0;
687 }
688 goto __again;
689 }
690 }
691 up(&ensoniq->src_mutex);
eb3414b4
TI		 692 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
693 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
1da177e4
LT		 694 return 0;
695}
696
eb3414b4 697static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
072c0119
JK		 698{
699 msleep(750);
700 snd_es1371_codec_read(ac97, AC97_RESET);
701 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
702 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
703 msleep(50);
704}
705
eb3414b4 706static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
1da177e4
LT		 707{
708 unsigned int n, truncm, freq, result;
709
710 down(&ensoniq->src_mutex);
711 n = rate / 3000;
712 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
713 n--;
714 truncm = (21 * n - 1) | 1;
715 freq = ((48000UL << 15) / rate) * n;
716 result = (48000UL << 15) / (freq / n);
717 if (rate >= 24000) {
718 if (truncm > 239)
719 truncm = 239;
720 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
721 (((239 - truncm) >> 1) << 9) | (n << 4));
722 } else {
723 if (truncm > 119)
724 truncm = 119;
725 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
726 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
727 }
728 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
eb3414b4
TI		 729 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
730 ES_SMPREG_INT_REGS) & 0x00ff) |
731 ((freq >> 5) & 0xfc00));
1da177e4
LT		 732 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
733 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
734 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
735 up(&ensoniq->src_mutex);
736}
737
eb3414b4 738static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
1da177e4
LT		 739{
740 unsigned int freq, r;
741
742 down(&ensoniq->src_mutex);
743 freq = ((rate << 15) + 1500) / 3000;
eb3414b4
TI		 744 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
745 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
746 ES_1371_DIS_P1;
1da177e4
LT		 747 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
748 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
eb3414b4
TI		 749 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
750 ES_SMPREG_INT_REGS) & 0x00ff) |
1da177e4
LT		 751 ((freq >> 5) & 0xfc00));
752 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
eb3414b4
TI		 753 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
754 ES_1371_DIS_P2 | ES_1371_DIS_R1));
1da177e4
LT		 755 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
756 up(&ensoniq->src_mutex);
757}
758
eb3414b4 759static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
1da177e4
LT		 760{
761 unsigned int freq, r;
762
763 down(&ensoniq->src_mutex);
764 freq = ((rate << 15) + 1500) / 3000;
eb3414b4
TI		 765 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
766 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
767 ES_1371_DIS_P2;
1da177e4
LT		 768 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
769 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
eb3414b4
TI		 770 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
771 ES_SMPREG_INT_REGS) & 0x00ff) |
1da177e4 772 ((freq >> 5) & 0xfc00));
eb3414b4
TI		 773 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
774 freq & 0x7fff);
775 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
776 ES_1371_DIS_P1 | ES_1371_DIS_R1));
1da177e4
LT		 777 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
778 up(&ensoniq->src_mutex);
779}
780
781#endif /* CHIP1371 */
782
eb3414b4 783static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 784{
eb3414b4 785 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 786 switch (cmd) {
787 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
788 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
789 {
790 unsigned int what = 0;
791 struct list_head *pos;
eb3414b4 792 struct snd_pcm_substream *s;
1da177e4
LT		 793 snd_pcm_group_for_each(pos, substream) {
794 s = snd_pcm_group_substream_entry(pos);
795 if (s == ensoniq->playback1_substream) {
796 what |= ES_P1_PAUSE;
797 snd_pcm_trigger_done(s, substream);
798 } else if (s == ensoniq->playback2_substream) {
799 what |= ES_P2_PAUSE;
800 snd_pcm_trigger_done(s, substream);
801 } else if (s == ensoniq->capture_substream)
802 return -EINVAL;
803 }
804 spin_lock(&ensoniq->reg_lock);
805 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
806 ensoniq->sctrl |= what;
807 else
808 ensoniq->sctrl &= ~what;
809 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
810 spin_unlock(&ensoniq->reg_lock);
811 break;
812 }
813 case SNDRV_PCM_TRIGGER_START:
814 case SNDRV_PCM_TRIGGER_STOP:
815 {
816 unsigned int what = 0;
817 struct list_head *pos;
eb3414b4 818 struct snd_pcm_substream *s;
1da177e4
LT		 819 snd_pcm_group_for_each(pos, substream) {
820 s = snd_pcm_group_substream_entry(pos);
821 if (s == ensoniq->playback1_substream) {
822 what |= ES_DAC1_EN;
823 snd_pcm_trigger_done(s, substream);
824 } else if (s == ensoniq->playback2_substream) {
825 what |= ES_DAC2_EN;
826 snd_pcm_trigger_done(s, substream);
827 } else if (s == ensoniq->capture_substream) {
828 what |= ES_ADC_EN;
829 snd_pcm_trigger_done(s, substream);
830 }
831 }
832 spin_lock(&ensoniq->reg_lock);
833 if (cmd == SNDRV_PCM_TRIGGER_START)
834 ensoniq->ctrl |= what;
835 else
836 ensoniq->ctrl &= ~what;
837 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
838 spin_unlock(&ensoniq->reg_lock);
839 break;
840 }
841 default:
842 return -EINVAL;
843 }
844 return 0;
845}
846
847/*
848 * PCM part
849 */
850
eb3414b4
TI		 851static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
852 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 853{
854 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
855}
856
eb3414b4 857static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 858{
859 return snd_pcm_lib_free_pages(substream);
860}
861
eb3414b4 862static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
1da177e4 863{
eb3414b4
TI		 864 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
865 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 866 unsigned int mode = 0;
867
868 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
869 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
870 if (snd_pcm_format_width(runtime->format) == 16)
871 mode |= 0x02;
872 if (runtime->channels > 1)
873 mode |= 0x01;
874 spin_lock_irq(&ensoniq->reg_lock);
875 ensoniq->ctrl &= ~ES_DAC1_EN;
876#ifdef CHIP1371
877 /* 48k doesn't need SRC (it breaks AC3-passthru) */
878 if (runtime->rate == 48000)
879 ensoniq->ctrl |= ES_1373_BYPASS_P1;
880 else
881 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
882#endif
883 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
884 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
885 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
886 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
887 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
888 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
889 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
eb3414b4
TI		 890 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
891 ES_REG(ensoniq, DAC1_COUNT));
1da177e4
LT		 892#ifdef CHIP1370
893 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
894 switch (runtime->rate) {
895 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
896 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
897 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
898 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
899 default: snd_BUG();
900 }
901#endif
902 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
903 spin_unlock_irq(&ensoniq->reg_lock);
904#ifndef CHIP1370
905 snd_es1371_dac1_rate(ensoniq, runtime->rate);
906#endif
907 return 0;
908}
909
eb3414b4 910static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
1da177e4 911{
eb3414b4
TI		 912 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
913 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 914 unsigned int mode = 0;
915
916 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
917 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
918 if (snd_pcm_format_width(runtime->format) == 16)
919 mode |= 0x02;
920 if (runtime->channels > 1)
921 mode |= 0x01;
922 spin_lock_irq(&ensoniq->reg_lock);
923 ensoniq->ctrl &= ~ES_DAC2_EN;
924 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
925 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
926 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
927 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
928 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
929 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
930 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
931 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
932 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
eb3414b4
TI		 933 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
934 ES_REG(ensoniq, DAC2_COUNT));
1da177e4
LT		 935#ifdef CHIP1370
936 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
937 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
938 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
939 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
940 }
941#endif
942 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
943 spin_unlock_irq(&ensoniq->reg_lock);
944#ifndef CHIP1370
945 snd_es1371_dac2_rate(ensoniq, runtime->rate);
946#endif
947 return 0;
948}
949
eb3414b4 950static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 951{
eb3414b4
TI		 952 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
953 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 954 unsigned int mode = 0;
955
956 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
957 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
958 if (snd_pcm_format_width(runtime->format) == 16)
959 mode |= 0x02;
960 if (runtime->channels > 1)
961 mode |= 0x01;
962 spin_lock_irq(&ensoniq->reg_lock);
963 ensoniq->ctrl &= ~ES_ADC_EN;
964 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
965 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
966 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
967 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
968 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
969 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
970 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
eb3414b4
TI		 971 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
972 ES_REG(ensoniq, ADC_COUNT));
1da177e4
LT		 973#ifdef CHIP1370
974 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
975 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
976 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
977 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
978 }
979#endif
980 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
981 spin_unlock_irq(&ensoniq->reg_lock);
982#ifndef CHIP1370
983 snd_es1371_adc_rate(ensoniq, runtime->rate);
984#endif
985 return 0;
986}
987
eb3414b4 988static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
1da177e4 989{
eb3414b4 990 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 991 size_t ptr;
992
993 spin_lock(&ensoniq->reg_lock);
994 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
995 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
996 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
997 ptr = bytes_to_frames(substream->runtime, ptr);
998 } else {
999 ptr = 0;
1000 }
1001 spin_unlock(&ensoniq->reg_lock);
1002 return ptr;
1003}
1004
eb3414b4 1005static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1da177e4 1006{
eb3414b4 1007 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1008 size_t ptr;
1009
1010 spin_lock(&ensoniq->reg_lock);
1011 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1012 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1013 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1014 ptr = bytes_to_frames(substream->runtime, ptr);
1015 } else {
1016 ptr = 0;
1017 }
1018 spin_unlock(&ensoniq->reg_lock);
1019 return ptr;
1020}
1021
eb3414b4 1022static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1023{
eb3414b4 1024 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1025 size_t ptr;
1026
1027 spin_lock(&ensoniq->reg_lock);
1028 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1029 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1030 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1031 ptr = bytes_to_frames(substream->runtime, ptr);
1032 } else {
1033 ptr = 0;
1034 }
1035 spin_unlock(&ensoniq->reg_lock);
1036 return ptr;
1037}
1038
eb3414b4 1039static struct snd_pcm_hardware snd_ensoniq_playback1 =
1da177e4
LT		 1040{
1041 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1042 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1043 SNDRV_PCM_INFO_MMAP_VALID |
1044 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1045 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1046 .rates =
1047#ifndef CHIP1370
1048 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1049#else
1050 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1051 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1052 SNDRV_PCM_RATE_44100),
1053#endif
1054 .rate_min = 4000,
1055 .rate_max = 48000,
1056 .channels_min = 1,
1057 .channels_max = 2,
1058 .buffer_bytes_max = (128*1024),
1059 .period_bytes_min = 64,
1060 .period_bytes_max = (128*1024),
1061 .periods_min = 1,
1062 .periods_max = 1024,
1063 .fifo_size = 0,
1064};
1065
eb3414b4 1066static struct snd_pcm_hardware snd_ensoniq_playback2 =
1da177e4
LT		 1067{
1068 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1069 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1070 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1071 SNDRV_PCM_INFO_SYNC_START),
1072 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1073 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1074 .rate_min = 4000,
1075 .rate_max = 48000,
1076 .channels_min = 1,
1077 .channels_max = 2,
1078 .buffer_bytes_max = (128*1024),
1079 .period_bytes_min = 64,
1080 .period_bytes_max = (128*1024),
1081 .periods_min = 1,
1082 .periods_max = 1024,
1083 .fifo_size = 0,
1084};
1085
eb3414b4 1086static struct snd_pcm_hardware snd_ensoniq_capture =
1da177e4
LT		 1087{
1088 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1089 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1090 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1091 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1092 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1093 .rate_min = 4000,
1094 .rate_max = 48000,
1095 .channels_min = 1,
1096 .channels_max = 2,
1097 .buffer_bytes_max = (128*1024),
1098 .period_bytes_min = 64,
1099 .period_bytes_max = (128*1024),
1100 .periods_min = 1,
1101 .periods_max = 1024,
1102 .fifo_size = 0,
1103};
1104
eb3414b4 1105static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1da177e4 1106{
eb3414b4
TI		 1107 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1108 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1109
1110 ensoniq->mode |= ES_MODE_PLAY1;
1111 ensoniq->playback1_substream = substream;
1112 runtime->hw = snd_ensoniq_playback1;
1113 snd_pcm_set_sync(substream);
1114 spin_lock_irq(&ensoniq->reg_lock);
1115 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1116 ensoniq->spdif_stream = ensoniq->spdif_default;
1117 spin_unlock_irq(&ensoniq->reg_lock);
1118#ifdef CHIP1370
1119 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1120 &snd_es1370_hw_constraints_rates);
1121#else
1122 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1123 &snd_es1371_hw_constraints_dac_clock);
1124#endif
1125 return 0;
1126}
1127
eb3414b4 1128static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1da177e4 1129{
eb3414b4
TI		 1130 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1131 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1132
1133 ensoniq->mode |= ES_MODE_PLAY2;
1134 ensoniq->playback2_substream = substream;
1135 runtime->hw = snd_ensoniq_playback2;
1136 snd_pcm_set_sync(substream);
1137 spin_lock_irq(&ensoniq->reg_lock);
1138 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1139 ensoniq->spdif_stream = ensoniq->spdif_default;
1140 spin_unlock_irq(&ensoniq->reg_lock);
1141#ifdef CHIP1370
1142 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1143 &snd_es1370_hw_constraints_clock);
1144#else
1145 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1146 &snd_es1371_hw_constraints_dac_clock);
1147#endif
1148 return 0;
1149}
1150
eb3414b4 1151static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1da177e4 1152{
eb3414b4
TI		 1153 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1154 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1155
1156 ensoniq->mode |= ES_MODE_CAPTURE;
1157 ensoniq->capture_substream = substream;
1158 runtime->hw = snd_ensoniq_capture;
1159 snd_pcm_set_sync(substream);
1160#ifdef CHIP1370
1161 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1162 &snd_es1370_hw_constraints_clock);
1163#else
1164 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1165 &snd_es1371_hw_constraints_adc_clock);
1166#endif
1167 return 0;
1168}
1169
eb3414b4 1170static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1da177e4 1171{
eb3414b4 1172 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1173
1174 ensoniq->playback1_substream = NULL;
1175 ensoniq->mode &= ~ES_MODE_PLAY1;
1176 return 0;
1177}
1178
eb3414b4 1179static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1da177e4 1180{
eb3414b4 1181 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1182
1183 ensoniq->playback2_substream = NULL;
1184 spin_lock_irq(&ensoniq->reg_lock);
1185#ifdef CHIP1370
1186 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1187#endif
1188 ensoniq->mode &= ~ES_MODE_PLAY2;
1189 spin_unlock_irq(&ensoniq->reg_lock);
1190 return 0;
1191}
1192
eb3414b4 1193static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1da177e4 1194{
eb3414b4 1195 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1da177e4
LT		 1196
1197 ensoniq->capture_substream = NULL;
1198 spin_lock_irq(&ensoniq->reg_lock);
1199#ifdef CHIP1370
1200 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1201#endif
1202 ensoniq->mode &= ~ES_MODE_CAPTURE;
1203 spin_unlock_irq(&ensoniq->reg_lock);
1204 return 0;
1205}
1206
eb3414b4 1207static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1da177e4
LT		 1208 .open = snd_ensoniq_playback1_open,
1209 .close = snd_ensoniq_playback1_close,
1210 .ioctl = snd_pcm_lib_ioctl,
1211 .hw_params = snd_ensoniq_hw_params,
1212 .hw_free = snd_ensoniq_hw_free,
1213 .prepare = snd_ensoniq_playback1_prepare,
1214 .trigger = snd_ensoniq_trigger,
1215 .pointer = snd_ensoniq_playback1_pointer,
1216};
1217
eb3414b4 1218static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1da177e4
LT		 1219 .open = snd_ensoniq_playback2_open,
1220 .close = snd_ensoniq_playback2_close,
1221 .ioctl = snd_pcm_lib_ioctl,
1222 .hw_params = snd_ensoniq_hw_params,
1223 .hw_free = snd_ensoniq_hw_free,
1224 .prepare = snd_ensoniq_playback2_prepare,
1225 .trigger = snd_ensoniq_trigger,
1226 .pointer = snd_ensoniq_playback2_pointer,
1227};
1228
eb3414b4 1229static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1da177e4
LT		 1230 .open = snd_ensoniq_capture_open,
1231 .close = snd_ensoniq_capture_close,
1232 .ioctl = snd_pcm_lib_ioctl,
1233 .hw_params = snd_ensoniq_hw_params,
1234 .hw_free = snd_ensoniq_hw_free,
1235 .prepare = snd_ensoniq_capture_prepare,
1236 .trigger = snd_ensoniq_trigger,
1237 .pointer = snd_ensoniq_capture_pointer,
1238};
1239
eb3414b4
TI		 1240static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1241 struct snd_pcm ** rpcm)
1da177e4 1242{
eb3414b4 1243 struct snd_pcm *pcm;
1da177e4
LT		 1244 int err;
1245
1246 if (rpcm)
1247 *rpcm = NULL;
1248#ifdef CHIP1370
1249 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1250#else
1251 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1252#endif
1253 if (err < 0)
1254 return err;
1255
1256#ifdef CHIP1370
1257 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1258#else
1259 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1260#endif
1261 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1262
1263 pcm->private_data = ensoniq;
1da177e4
LT		 1264 pcm->info_flags = 0;
1265#ifdef CHIP1370
1266 strcpy(pcm->name, "ES1370 DAC2/ADC");
1267#else
1268 strcpy(pcm->name, "ES1371 DAC2/ADC");
1269#endif
1270 ensoniq->pcm1 = pcm;
1271
1272 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1273 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1274
1275 if (rpcm)
1276 *rpcm = pcm;
1277 return 0;
1278}
1279
eb3414b4
TI		 1280static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1281 struct snd_pcm ** rpcm)
1da177e4 1282{
eb3414b4 1283 struct snd_pcm *pcm;
1da177e4
LT		 1284 int err;
1285
1286 if (rpcm)
1287 *rpcm = NULL;
1288#ifdef CHIP1370
1289 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1290#else
1291 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1292#endif
1293 if (err < 0)
1294 return err;
1295
1296#ifdef CHIP1370
1297 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1298#else
1299 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1300#endif
1301 pcm->private_data = ensoniq;
1da177e4
LT		 1302 pcm->info_flags = 0;
1303#ifdef CHIP1370
1304 strcpy(pcm->name, "ES1370 DAC1");
1305#else
1306 strcpy(pcm->name, "ES1371 DAC1");
1307#endif
1308 ensoniq->pcm2 = pcm;
1309
1310 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1311 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1312
1313 if (rpcm)
1314 *rpcm = pcm;
1315 return 0;
1316}
1317
1318/*
1319 * Mixer section
1320 */
1321
1322/*
1323 * ENS1371 mixer (including SPDIF interface)
1324 */
1325#ifdef CHIP1371
eb3414b4
TI		 1326static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1327 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1328{
1329 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1330 uinfo->count = 1;
1331 return 0;
1332}
1333
eb3414b4
TI		 1334static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1335 struct snd_ctl_elem_value *ucontrol)
1da177e4 1336{
eb3414b4 1337 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1338 spin_lock_irq(&ensoniq->reg_lock);
1339 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1340 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1341 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1342 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1343 spin_unlock_irq(&ensoniq->reg_lock);
1344 return 0;
1345}
1346
eb3414b4
TI		 1347static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1348 struct snd_ctl_elem_value *ucontrol)
1da177e4 1349{
eb3414b4 1350 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1351 unsigned int val;
1352 int change;
1353
1354 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1355 ((u32)ucontrol->value.iec958.status[1] << 8) |
1356 ((u32)ucontrol->value.iec958.status[2] << 16) |
1357 ((u32)ucontrol->value.iec958.status[3] << 24);
1358 spin_lock_irq(&ensoniq->reg_lock);
1359 change = ensoniq->spdif_default != val;
1360 ensoniq->spdif_default = val;
eb3414b4
TI		 1361 if (change && ensoniq->playback1_substream == NULL &&
1362 ensoniq->playback2_substream == NULL)
1da177e4
LT		 1363 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1364 spin_unlock_irq(&ensoniq->reg_lock);
1365 return change;
1366}
1367
eb3414b4
TI		 1368static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1369 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1370{
1371 ucontrol->value.iec958.status[0] = 0xff;
1372 ucontrol->value.iec958.status[1] = 0xff;
1373 ucontrol->value.iec958.status[2] = 0xff;
1374 ucontrol->value.iec958.status[3] = 0xff;
1375 return 0;
1376}
1377
eb3414b4
TI		 1378static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1379 struct snd_ctl_elem_value *ucontrol)
1da177e4 1380{
eb3414b4 1381 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1382 spin_lock_irq(&ensoniq->reg_lock);
1383 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1384 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1385 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1386 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1387 spin_unlock_irq(&ensoniq->reg_lock);
1388 return 0;
1389}
1390
eb3414b4
TI		 1391static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1392 struct snd_ctl_elem_value *ucontrol)
1da177e4 1393{
eb3414b4 1394 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1395 unsigned int val;
1396 int change;
1397
1398 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1399 ((u32)ucontrol->value.iec958.status[1] << 8) |
1400 ((u32)ucontrol->value.iec958.status[2] << 16) |
1401 ((u32)ucontrol->value.iec958.status[3] << 24);
1402 spin_lock_irq(&ensoniq->reg_lock);
1403 change = ensoniq->spdif_stream != val;
1404 ensoniq->spdif_stream = val;
eb3414b4
TI		 1405 if (change && (ensoniq->playback1_substream != NULL ||
1406 ensoniq->playback2_substream != NULL))
1da177e4
LT		 1407 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1408 spin_unlock_irq(&ensoniq->reg_lock);
1409 return change;
1410}
1411
1412#define ES1371_SPDIF(xname) \
1413{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1414 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1415
eb3414b4
TI		 1416static int snd_es1371_spdif_info(struct snd_kcontrol *kcontrol,
1417 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1418{
1419 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1420 uinfo->count = 1;
1421 uinfo->value.integer.min = 0;
1422 uinfo->value.integer.max = 1;
1423 return 0;
1424}
1425
eb3414b4
TI		 1426static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1427 struct snd_ctl_elem_value *ucontrol)
1da177e4 1428{
eb3414b4 1429 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1430
1431 spin_lock_irq(&ensoniq->reg_lock);
1432 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1433 spin_unlock_irq(&ensoniq->reg_lock);
1434 return 0;
1435}
1436
eb3414b4
TI		 1437static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1438 struct snd_ctl_elem_value *ucontrol)
1da177e4 1439{
eb3414b4 1440 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1441 unsigned int nval1, nval2;
1442 int change;
1443
1444 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1445 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1446 spin_lock_irq(&ensoniq->reg_lock);
1447 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1448 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1449 ensoniq->ctrl |= nval1;
1450 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1451 ensoniq->cssr |= nval2;
1452 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1453 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1454 spin_unlock_irq(&ensoniq->reg_lock);
1455 return change;
1456}
1457
1458
1459/* spdif controls */
eb3414b4 1460static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
10e8d78a 1461 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1da177e4 1462 {
5549d549 1463 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1464 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1465 .info = snd_ens1373_spdif_info,
1466 .get = snd_ens1373_spdif_default_get,
1467 .put = snd_ens1373_spdif_default_put,
1468 },
1469 {
1470 .access = SNDRV_CTL_ELEM_ACCESS_READ,
5549d549 1471 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1472 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1473 .info = snd_ens1373_spdif_info,
1474 .get = snd_ens1373_spdif_mask_get
1475 },
1476 {
5549d549 1477 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1478 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1479 .info = snd_ens1373_spdif_info,
1480 .get = snd_ens1373_spdif_stream_get,
1481 .put = snd_ens1373_spdif_stream_put
1482 },
1483};
1484
1485
eb3414b4
TI		 1486static int snd_es1373_rear_info(struct snd_kcontrol *kcontrol,
1487 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1488{
1489 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1490 uinfo->count = 1;
1491 uinfo->value.integer.min = 0;
1492 uinfo->value.integer.max = 1;
1493 return 0;
1494}
1495
eb3414b4
TI		 1496static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1497 struct snd_ctl_elem_value *ucontrol)
1da177e4 1498{
eb3414b4 1499 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1500 int val = 0;
1501
1502 spin_lock_irq(&ensoniq->reg_lock);
eb3414b4
TI		 1503 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1504 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1da177e4
LT		 1505 val = 1;
1506 ucontrol->value.integer.value[0] = val;
1507 spin_unlock_irq(&ensoniq->reg_lock);
1508 return 0;
1509}
1510
eb3414b4
TI		 1511static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1512 struct snd_ctl_elem_value *ucontrol)
1da177e4 1513{
eb3414b4 1514 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1515 unsigned int nval1;
1516 int change;
1517
eb3414b4
TI		 1518 nval1 = ucontrol->value.integer.value[0] ?
1519 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1da177e4 1520 spin_lock_irq(&ensoniq->reg_lock);
eb3414b4
TI		 1521 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1522 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1da177e4
LT		 1523 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1524 ensoniq->cssr |= nval1;
1525 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1526 spin_unlock_irq(&ensoniq->reg_lock);
1527 return change;
1528}
1529
eb3414b4 1530static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1da177e4
LT		 1531{
1532 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1533 .name = "AC97 2ch->4ch Copy Switch",
1534 .info = snd_es1373_rear_info,
1535 .get = snd_es1373_rear_get,
1536 .put = snd_es1373_rear_put,
1537};
1538
eb3414b4
TI		 1539static int snd_es1373_line_info(struct snd_kcontrol *kcontrol,
1540 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1541{
1542 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1543 uinfo->count = 1;
1544 uinfo->value.integer.min = 0;
1545 uinfo->value.integer.max = 1;
1546 return 0;
1547}
1548
eb3414b4
TI		 1549static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1550 struct snd_ctl_elem_value *ucontrol)
1da177e4 1551{
eb3414b4 1552 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1553 int val = 0;
1554
1555 spin_lock_irq(&ensoniq->reg_lock);
1556 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1557 val = 1;
1558 ucontrol->value.integer.value[0] = val;
1559 spin_unlock_irq(&ensoniq->reg_lock);
1560 return 0;
1561}
1562
eb3414b4
TI		 1563static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1564 struct snd_ctl_elem_value *ucontrol)
1da177e4 1565{
eb3414b4 1566 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1567 int changed;
1568 unsigned int ctrl;
1569
1570 spin_lock_irq(&ensoniq->reg_lock);
1571 ctrl = ensoniq->ctrl;
1572 if (ucontrol->value.integer.value[0])
1573 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1574 else
1575 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1576 changed = (ctrl != ensoniq->ctrl);
1577 if (changed)
1578 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1579 spin_unlock_irq(&ensoniq->reg_lock);
1580 return changed;
1581}
1582
eb3414b4 1583static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1da177e4
LT		 1584{
1585 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1586 .name = "Line In->Rear Out Switch",
1587 .info = snd_es1373_line_info,
1588 .get = snd_es1373_line_get,
1589 .put = snd_es1373_line_put,
1590};
1591
eb3414b4 1592static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1593{
eb3414b4 1594 struct ensoniq *ensoniq = ac97->private_data;
1da177e4
LT		 1595 ensoniq->u.es1371.ac97 = NULL;
1596}
1597
1598static struct {
1599 unsigned short vid; /* vendor ID */
1600 unsigned short did; /* device ID */
1601 unsigned char rev; /* revision */
1602} es1371_spdif_present[] __devinitdata = {
1603 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1604 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1605 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1606 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1607 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1608 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1609};
1610
eb3414b4 1611static int snd_ensoniq_1371_mixer(struct ensoniq * ensoniq)
1da177e4 1612{
eb3414b4
TI		 1613 struct snd_card *card = ensoniq->card;
1614 struct snd_ac97_bus *pbus;
1615 struct snd_ac97_template ac97;
1da177e4 1616 int err, idx;
eb3414b4 1617 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1618 .write = snd_es1371_codec_write,
1619 .read = snd_es1371_codec_read,
072c0119 1620 .wait = snd_es1371_codec_wait,
1da177e4
LT		 1621 };
1622
1623 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1624 return err;
1625
1626 memset(&ac97, 0, sizeof(ac97));
1627 ac97.private_data = ensoniq;
1628 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1629 ac97.scaps = AC97_SCAP_AUDIO;
1630 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1631 return err;
1632 for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1633 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1634 ensoniq->pci->device == es1371_spdif_present[idx].did &&
1635 ensoniq->rev == es1371_spdif_present[idx].rev) {
eb3414b4 1636 struct snd_kcontrol *kctl;
1da177e4
LT		 1637 int i, index = 0;
1638
eb3414b4
TI		 1639 ensoniq->spdif_default = ensoniq->spdif_stream =
1640 SNDRV_PCM_DEFAULT_CON_SPDIF;
1da177e4
LT		 1641 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1642
1643 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1644 index++;
1645
1646 for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1647 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1648 if (! kctl)
1649 return -ENOMEM;
1650 kctl->id.index = index;
1651 if ((err = snd_ctl_add(card, kctl)) < 0)
1652 return err;
1653 }
1654 break;
1655 }
1656 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1657 /* mirror rear to front speakers */
1658 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1659 ensoniq->cssr |= ES_1373_REAR_BIT26;
1660 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1661 if (err < 0)
1662 return err;
1663 }
1664 if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1665 (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1666 ((ensoniq->subsystem_vendor_id == 0x1458) &&
1667 (ensoniq->subsystem_device_id == 0xa000))) { /* GA-8IEXP */
1668 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1669 if (err < 0)
1670 return err;
1671 }
1672
1673 return 0;
1674}
1675
1676#endif /* CHIP1371 */
1677
1678/* generic control callbacks for ens1370 */
1679#ifdef CHIP1370
1680#define ENSONIQ_CONTROL(xname, mask) \
1681{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1682 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1683 .private_value = mask }
1684
eb3414b4
TI		 1685static int snd_ensoniq_control_info(struct snd_kcontrol *kcontrol,
1686 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1687{
1688 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1689 uinfo->count = 1;
1690 uinfo->value.integer.min = 0;
1691 uinfo->value.integer.max = 1;
1692 return 0;
1693}
1694
eb3414b4
TI		 1695static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1696 struct snd_ctl_elem_value *ucontrol)
1da177e4 1697{
eb3414b4 1698 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1699 int mask = kcontrol->private_value;
1700
1701 spin_lock_irq(&ensoniq->reg_lock);
1702 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1703 spin_unlock_irq(&ensoniq->reg_lock);
1704 return 0;
1705}
1706
eb3414b4
TI		 1707static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1708 struct snd_ctl_elem_value *ucontrol)
1da177e4 1709{
eb3414b4 1710 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1711 int mask = kcontrol->private_value;
1712 unsigned int nval;
1713 int change;
1714
1715 nval = ucontrol->value.integer.value[0] ? mask : 0;
1716 spin_lock_irq(&ensoniq->reg_lock);
1717 change = (ensoniq->ctrl & mask) != nval;
1718 ensoniq->ctrl &= ~mask;
1719 ensoniq->ctrl |= nval;
1720 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1721 spin_unlock_irq(&ensoniq->reg_lock);
1722 return change;
1723}
1724
1725/*
1726 * ENS1370 mixer
1727 */
1728
eb3414b4 1729static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1da177e4
LT		 1730ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1731ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1732};
1733
1734#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1735
eb3414b4 1736static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1da177e4 1737{
eb3414b4 1738 struct ensoniq *ensoniq = ak4531->private_data;
1da177e4
LT		 1739 ensoniq->u.es1370.ak4531 = NULL;
1740}
1741
eb3414b4 1742static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1da177e4 1743{
eb3414b4
TI		 1744 struct snd_card *card = ensoniq->card;
1745 struct snd_ak4531 ak4531;
1da177e4
LT		 1746 unsigned int idx;
1747 int err;
1748
1749 /* try reset AK4531 */
1750 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1751 inw(ES_REG(ensoniq, 1370_CODEC));
1752 udelay(100);
1753 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1754 inw(ES_REG(ensoniq, 1370_CODEC));
1755 udelay(100);
1756
1757 memset(&ak4531, 0, sizeof(ak4531));
1758 ak4531.write = snd_es1370_codec_write;
1759 ak4531.private_data = ensoniq;
1760 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1761 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1762 return err;
1763 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1764 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1765 if (err < 0)
1766 return err;
1767 }
1768 return 0;
1769}
1770
1771#endif /* CHIP1370 */
1772
1773#ifdef SUPPORT_JOYSTICK
1774
1775#ifdef CHIP1371
1776static int __devinit snd_ensoniq_get_joystick_port(int dev)
1777{
1778 switch (joystick_port[dev]) {
1779 case 0: /* disabled */
1780 case 1: /* auto-detect */
1781 case 0x200:
1782 case 0x208:
1783 case 0x210:
1784 case 0x218:
1785 return joystick_port[dev];
1786
1787 default:
1788 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1789 return 0;
1790 }
1791}
1792#else
1793static inline int snd_ensoniq_get_joystick_port(int dev)
1794{
1795 return joystick[dev] ? 0x200 : 0;
1796}
1797#endif
1798
eb3414b4 1799static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1da177e4
LT		 1800{
1801 struct gameport *gp;
1802 int io_port;
1803
1804 io_port = snd_ensoniq_get_joystick_port(dev);
1805
1806 switch (io_port) {
1807 case 0:
1808 return -ENOSYS;
1809
1810 case 1: /* auto_detect */
1811 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1812 if (request_region(io_port, 8, "ens137x: gameport"))
1813 break;
1814 if (io_port > 0x218) {
1815 printk(KERN_WARNING "ens137x: no gameport ports available\n");
1816 return -EBUSY;
1817 }
1818 break;
1819
1820 default:
1821 if (!request_region(io_port, 8, "ens137x: gameport")) {
eb3414b4
TI		 1822 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1823 io_port);
1da177e4
LT		 1824 return -EBUSY;
1825 }
1826 break;
1827 }
1828
1829 ensoniq->gameport = gp = gameport_allocate_port();
1830 if (!gp) {
1831 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1832 release_region(io_port, 8);
1833 return -ENOMEM;
1834 }
1835
1836 gameport_set_name(gp, "ES137x");
1837 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1838 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1839 gp->io = io_port;
1840
1841 ensoniq->ctrl |= ES_JYSTK_EN;
1842#ifdef CHIP1371
1843 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1844 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1845#endif
1846 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1847
1848 gameport_register_port(ensoniq->gameport);
1849
1850 return 0;
1851}
1852
eb3414b4 1853static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1da177e4
LT		 1854{
1855 if (ensoniq->gameport) {
1856 int port = ensoniq->gameport->io;
1857
1858 gameport_unregister_port(ensoniq->gameport);
1859 ensoniq->gameport = NULL;
1860 ensoniq->ctrl &= ~ES_JYSTK_EN;
1861 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1862 release_region(port, 8);
1863 }
1864}
1865#else
eb3414b4
TI		 1866static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1867static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1da177e4
LT		 1868#endif /* SUPPORT_JOYSTICK */
1869
1870/*
1871
1872 */
1873
eb3414b4
TI		 1874static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1875 struct snd_info_buffer *buffer)
1da177e4 1876{
eb3414b4 1877 struct ensoniq *ensoniq = entry->private_data;
1da177e4
LT		 1878
1879#ifdef CHIP1370
1880 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1881#else
1882 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1883#endif
eb3414b4
TI		 1884 snd_iprintf(buffer, "Joystick enable : %s\n",
1885 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1da177e4 1886#ifdef CHIP1370
eb3414b4
TI		 1887 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1888 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1889 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1890 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1da177e4 1891#else
eb3414b4
TI		 1892 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1893 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1da177e4
LT		 1894#endif
1895}
1896
eb3414b4 1897static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1da177e4 1898{
eb3414b4 1899 struct snd_info_entry *entry;
1da177e4
LT		 1900
1901 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1902 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1903}
1904
1905/*
1906
1907 */
1908
eb3414b4 1909static int snd_ensoniq_free(struct ensoniq *ensoniq)
1da177e4
LT		 1910{
1911 snd_ensoniq_free_gameport(ensoniq);
1912 if (ensoniq->irq < 0)
1913 goto __hw_end;
1914#ifdef CHIP1370
1915 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1916 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1917#else
1918 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1919 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1920#endif
1921 synchronize_irq(ensoniq->irq);
1922 pci_set_power_state(ensoniq->pci, 3);
1923 __hw_end:
1924#ifdef CHIP1370
1925 if (ensoniq->dma_bug.area)
1926 snd_dma_free_pages(&ensoniq->dma_bug);
1927#endif
1928 if (ensoniq->irq >= 0)
eb3414b4 1929 free_irq(ensoniq->irq, ensoniq);
1da177e4
LT		 1930 pci_release_regions(ensoniq->pci);
1931 pci_disable_device(ensoniq->pci);
1932 kfree(ensoniq);
1933 return 0;
1934}
1935
eb3414b4 1936static int snd_ensoniq_dev_free(struct snd_device *device)
1da177e4 1937{
eb3414b4 1938 struct ensoniq *ensoniq = device->device_data;
1da177e4
LT		 1939 return snd_ensoniq_free(ensoniq);
1940}
1941
1942#ifdef CHIP1371
1943static struct {
1944 unsigned short svid; /* subsystem vendor ID */
1945 unsigned short sdid; /* subsystem device ID */
1946} es1371_amplifier_hack[] = {
1947 { .svid = 0x107b, .sdid = 0x2150 }, /* Gateway Solo 2150 */
1948 { .svid = 0x13bd, .sdid = 0x100c }, /* EV1938 on Mebius PC-MJ100V */
1949 { .svid = 0x1102, .sdid = 0x5938 }, /* Targa Xtender300 */
1950 { .svid = 0x1102, .sdid = 0x8938 }, /* IPC Topnote G notebook */
1951 { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1952};
1953static struct {
1954 unsigned short vid; /* vendor ID */
1955 unsigned short did; /* device ID */
1956 unsigned char rev; /* revision */
1957} es1371_ac97_reset_hack[] = {
1958 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1959 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1960 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1961 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1962 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1963 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1964};
1965#endif
1966
eb3414b4 1967static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
f31a31b9
KB		 1968{
1969#ifdef CHIP1371
1970 int idx;
1971 struct pci_dev *pci = ensoniq->pci;
1972#endif
eb3414b4
TI		 1973 /* this code was part of snd_ensoniq_create before intruduction
1974 * of suspend/resume
1975 */
f31a31b9
KB		 1976#ifdef CHIP1370
1977 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1978 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1979 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1980 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1981 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1982#else
1983 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1984 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1985 outl(0, ES_REG(ensoniq, 1371_LEGACY));
1986 for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1987 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
1988 pci->device == es1371_ac97_reset_hack[idx].did &&
1989 ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
1990 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1991 /* need to delay around 20ms(bleech) to give
1992 some CODECs enough time to wakeup */
1993 msleep(20);
1994 break;
1995 }
1996 /* AC'97 warm reset to start the bitclk */
1997 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1998 inl(ES_REG(ensoniq, CONTROL));
1999 udelay(20);
2000 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2001 /* Init the sample rate converter */
2002 snd_es1371_wait_src_ready(ensoniq);
2003 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2004 for (idx = 0; idx < 0x80; idx++)
2005 snd_es1371_src_write(ensoniq, idx, 0);
2006 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2007 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2008 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2009 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2010 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2011 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2012 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2013 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2014 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2015 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2016 snd_es1371_adc_rate(ensoniq, 22050);
2017 snd_es1371_dac1_rate(ensoniq, 22050);
2018 snd_es1371_dac2_rate(ensoniq, 22050);
2019 /* WARNING:
2020 * enabling the sample rate converter without properly programming
2021 * its parameters causes the chip to lock up (the SRC busy bit will
2022 * be stuck high, and I've found no way to rectify this other than
2023 * power cycle) - Thomas Sailer
2024 */
2025 snd_es1371_wait_src_ready(ensoniq);
2026 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2027 /* try reset codec directly */
2028 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2029#endif
2030 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2031 outb(0x00, ES_REG(ensoniq, UART_RES));
2032 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2033 synchronize_irq(ensoniq->irq);
2034}
2035
2036#ifdef CONFIG_PM
fe8be107 2037static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state)
f31a31b9 2038{
fe8be107
TI		 2039 struct snd_card *card = pci_get_drvdata(pci);
2040 struct ensoniq *ensoniq = card->private_data;
f31a31b9 2041
fe8be107
TI		 2042 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2043
f31a31b9
KB		 2044 snd_pcm_suspend_all(ensoniq->pcm1);
2045 snd_pcm_suspend_all(ensoniq->pcm2);
2046
2047#ifdef CHIP1371
fe8be107 2048 snd_ac97_suspend(ensoniq->u.es1371.ac97);
f31a31b9 2049#else
fe8be107 2050 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
f31a31b9 2051#endif
fe8be107
TI		 2052 pci_set_power_state(pci, PCI_D3hot);
2053 pci_disable_device(pci);
2054 pci_save_state(pci);
f31a31b9
KB		 2055 return 0;
2056}
2057
fe8be107 2058static int snd_ensoniq_resume(struct pci_dev *pci)
f31a31b9 2059{
fe8be107
TI		 2060 struct snd_card *card = pci_get_drvdata(pci);
2061 struct ensoniq *ensoniq = card->private_data;
f31a31b9 2062
fe8be107
TI		 2063 pci_restore_state(pci);
2064 pci_enable_device(pci);
2065 pci_set_power_state(pci, PCI_D0);
2066 pci_set_master(pci);
f31a31b9
KB		 2067
2068 snd_ensoniq_chip_init(ensoniq);
2069
2070#ifdef CHIP1371
fe8be107 2071 snd_ac97_resume(ensoniq->u.es1371.ac97);
f31a31b9 2072#else
fe8be107 2073 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
f31a31b9 2074#endif
fe8be107 2075 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
f31a31b9
KB		 2076 return 0;
2077}
2078#endif /* CONFIG_PM */
2079
2080
eb3414b4 2081static int __devinit snd_ensoniq_create(struct snd_card *card,
1da177e4 2082 struct pci_dev *pci,
eb3414b4 2083 struct ensoniq ** rensoniq)
1da177e4 2084{
eb3414b4 2085 struct ensoniq *ensoniq;
1da177e4
LT		 2086 unsigned short cmdw;
2087 unsigned char cmdb;
2088#ifdef CHIP1371
2089 int idx;
2090#endif
2091 int err;
eb3414b4 2092 static struct snd_device_ops ops = {
1da177e4
LT		 2093 .dev_free = snd_ensoniq_dev_free,
2094 };
2095
2096 *rensoniq = NULL;
2097 if ((err = pci_enable_device(pci)) < 0)
2098 return err;
e560d8d8 2099 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
1da177e4
LT		 2100 if (ensoniq == NULL) {
2101 pci_disable_device(pci);
2102 return -ENOMEM;
2103 }
2104 spin_lock_init(&ensoniq->reg_lock);
2105 init_MUTEX(&ensoniq->src_mutex);
2106 ensoniq->card = card;
2107 ensoniq->pci = pci;
2108 ensoniq->irq = -1;
2109 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2110 kfree(ensoniq);
2111 pci_disable_device(pci);
2112 return err;
2113 }
2114 ensoniq->port = pci_resource_start(pci, 0);
eb3414b4
TI		 2115 if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ,
2116 "Ensoniq AudioPCI", ensoniq)) {
99b359ba 2117 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2118 snd_ensoniq_free(ensoniq);
2119 return -EBUSY;
2120 }
2121 ensoniq->irq = pci->irq;
2122#ifdef CHIP1370
2123 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2124 16, &ensoniq->dma_bug) < 0) {
99b359ba 2125 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
1da177e4
LT		 2126 snd_ensoniq_free(ensoniq);
2127 return -EBUSY;
2128 }
2129#endif
2130 pci_set_master(pci);
2131 pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
2132 ensoniq->rev = cmdb;
2133 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
2134 ensoniq->subsystem_vendor_id = cmdw;
2135 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
2136 ensoniq->subsystem_device_id = cmdw;
2137#ifdef CHIP1370
2138#if 0
eb3414b4
TI		 2139 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2140 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1da177e4
LT		 2141#else /* get microphone working */
2142 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2143#endif
2144 ensoniq->sctrl = 0;
1da177e4
LT		 2145#else
2146 ensoniq->ctrl = 0;
2147 ensoniq->sctrl = 0;
2148 ensoniq->cssr = 0;
2149 for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
2150 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
2151 ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2152 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2153 break;
2154 }
1da177e4
LT		 2155 for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2156 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2157 pci->device == es1371_ac97_reset_hack[idx].did &&
2158 ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
1da177e4 2159 ensoniq->cssr |= ES_1371_ST_AC97_RST;
1da177e4
LT		 2160 break;
2161 }
1da177e4 2162#endif
f31a31b9
KB		 2163
2164 snd_ensoniq_chip_init(ensoniq);
1da177e4
LT		 2165
2166 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2167 snd_ensoniq_free(ensoniq);
2168 return err;
2169 }
2170
2171 snd_ensoniq_proc_init(ensoniq);
2172
2173 snd_card_set_dev(card, &pci->dev);
2174
2175 *rensoniq = ensoniq;
2176 return 0;
2177}
2178
2179/*
2180 * MIDI section
2181 */
2182
eb3414b4 2183static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
1da177e4 2184{
eb3414b4 2185 struct snd_rawmidi *rmidi = ensoniq->rmidi;
1da177e4
LT		 2186 unsigned char status, mask, byte;
2187
2188 if (rmidi == NULL)
2189 return;
2190 /* do Rx at first */
2191 spin_lock(&ensoniq->reg_lock);
2192 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2193 while (mask) {
2194 status = inb(ES_REG(ensoniq, UART_STATUS));
2195 if ((status & mask) == 0)
2196 break;
2197 byte = inb(ES_REG(ensoniq, UART_DATA));
2198 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2199 }
2200 spin_unlock(&ensoniq->reg_lock);
2201
2202 /* do Tx at second */
2203 spin_lock(&ensoniq->reg_lock);
2204 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2205 while (mask) {
2206 status = inb(ES_REG(ensoniq, UART_STATUS));
2207 if ((status & mask) == 0)
2208 break;
2209 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2210 ensoniq->uartc &= ~ES_TXINTENM;
2211 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2212 mask &= ~ES_TXRDY;
2213 } else {
2214 outb(byte, ES_REG(ensoniq, UART_DATA));
2215 }
2216 }
2217 spin_unlock(&ensoniq->reg_lock);
2218}
2219
eb3414b4 2220static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
1da177e4 2221{
eb3414b4 2222 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2223
2224 spin_lock_irq(&ensoniq->reg_lock);
2225 ensoniq->uartm |= ES_MODE_INPUT;
2226 ensoniq->midi_input = substream;
2227 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2228 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2229 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2230 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2231 }
2232 spin_unlock_irq(&ensoniq->reg_lock);
2233 return 0;
2234}
2235
eb3414b4 2236static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
1da177e4 2237{
eb3414b4 2238 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2239
2240 spin_lock_irq(&ensoniq->reg_lock);
2241 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2242 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2243 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2244 } else {
2245 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2246 }
2247 ensoniq->midi_input = NULL;
2248 ensoniq->uartm &= ~ES_MODE_INPUT;
2249 spin_unlock_irq(&ensoniq->reg_lock);
2250 return 0;
2251}
2252
eb3414b4 2253static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
1da177e4 2254{
eb3414b4 2255 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2256
2257 spin_lock_irq(&ensoniq->reg_lock);
2258 ensoniq->uartm |= ES_MODE_OUTPUT;
2259 ensoniq->midi_output = substream;
2260 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2261 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2262 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2263 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2264 }
2265 spin_unlock_irq(&ensoniq->reg_lock);
2266 return 0;
2267}
2268
eb3414b4 2269static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
1da177e4 2270{
eb3414b4 2271 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2272
2273 spin_lock_irq(&ensoniq->reg_lock);
2274 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2275 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2276 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2277 } else {
2278 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2279 }
2280 ensoniq->midi_output = NULL;
2281 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2282 spin_unlock_irq(&ensoniq->reg_lock);
2283 return 0;
2284}
2285
eb3414b4 2286static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2287{
2288 unsigned long flags;
eb3414b4 2289 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2290 int idx;
2291
2292 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2293 if (up) {
2294 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2295 /* empty input FIFO */
2296 for (idx = 0; idx < 32; idx++)
2297 inb(ES_REG(ensoniq, UART_DATA));
2298 ensoniq->uartc |= ES_RXINTEN;
2299 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2300 }
2301 } else {
2302 if (ensoniq->uartc & ES_RXINTEN) {
2303 ensoniq->uartc &= ~ES_RXINTEN;
2304 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2305 }
2306 }
2307 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2308}
2309
eb3414b4 2310static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2311{
2312 unsigned long flags;
eb3414b4 2313 struct ensoniq *ensoniq = substream->rmidi->private_data;
1da177e4
LT		 2314 unsigned char byte;
2315
2316 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2317 if (up) {
2318 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2319 ensoniq->uartc |= ES_TXINTENO(1);
2320 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2321 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2322 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2323 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2324 ensoniq->uartc &= ~ES_TXINTENM;
2325 } else {
2326 outb(byte, ES_REG(ensoniq, UART_DATA));
2327 }
2328 }
2329 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2330 }
2331 } else {
2332 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2333 ensoniq->uartc &= ~ES_TXINTENM;
2334 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2335 }
2336 }
2337 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2338}
2339
eb3414b4 2340static struct snd_rawmidi_ops snd_ensoniq_midi_output =
1da177e4
LT		 2341{
2342 .open = snd_ensoniq_midi_output_open,
2343 .close = snd_ensoniq_midi_output_close,
2344 .trigger = snd_ensoniq_midi_output_trigger,
2345};
2346
eb3414b4 2347static struct snd_rawmidi_ops snd_ensoniq_midi_input =
1da177e4
LT		 2348{
2349 .open = snd_ensoniq_midi_input_open,
2350 .close = snd_ensoniq_midi_input_close,
2351 .trigger = snd_ensoniq_midi_input_trigger,
2352};
2353
eb3414b4
TI		 2354static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2355 struct snd_rawmidi **rrawmidi)
1da177e4 2356{
eb3414b4 2357 struct snd_rawmidi *rmidi;
1da177e4
LT		 2358 int err;
2359
2360 if (rrawmidi)
2361 *rrawmidi = NULL;
2362 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2363 return err;
2364#ifdef CHIP1370
2365 strcpy(rmidi->name, "ES1370");
2366#else
2367 strcpy(rmidi->name, "ES1371");
2368#endif
2369 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2370 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
eb3414b4
TI		 2371 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2372 SNDRV_RAWMIDI_INFO_DUPLEX;
1da177e4
LT		 2373 rmidi->private_data = ensoniq;
2374 ensoniq->rmidi = rmidi;
2375 if (rrawmidi)
2376 *rrawmidi = rmidi;
2377 return 0;
2378}
2379
2380/*
2381 * Interrupt handler
2382 */
2383
2384static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2385{
eb3414b4 2386 struct ensoniq *ensoniq = dev_id;
1da177e4
LT		 2387 unsigned int status, sctrl;
2388
2389 if (ensoniq == NULL)
2390 return IRQ_NONE;
2391
2392 status = inl(ES_REG(ensoniq, STATUS));
2393 if (!(status & ES_INTR))
2394 return IRQ_NONE;
2395
2396 spin_lock(&ensoniq->reg_lock);
2397 sctrl = ensoniq->sctrl;
2398 if (status & ES_DAC1)
2399 sctrl &= ~ES_P1_INT_EN;
2400 if (status & ES_DAC2)
2401 sctrl &= ~ES_P2_INT_EN;
2402 if (status & ES_ADC)
2403 sctrl &= ~ES_R1_INT_EN;
2404 outl(sctrl, ES_REG(ensoniq, SERIAL));
2405 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2406 spin_unlock(&ensoniq->reg_lock);
2407
2408 if (status & ES_UART)
2409 snd_ensoniq_midi_interrupt(ensoniq);
2410 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2411 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2412 if ((status & ES_ADC) && ensoniq->capture_substream)
2413 snd_pcm_period_elapsed(ensoniq->capture_substream);
2414 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2415 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2416 return IRQ_HANDLED;
2417}
2418
2419static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2420 const struct pci_device_id *pci_id)
2421{
2422 static int dev;
eb3414b4
TI		 2423 struct snd_card *card;
2424 struct ensoniq *ensoniq;
1da177e4
LT		 2425 int err, pcm_devs[2];
2426
2427 if (dev >= SNDRV_CARDS)
2428 return -ENODEV;
2429 if (!enable[dev]) {
2430 dev++;
2431 return -ENOENT;
2432 }
2433
2434 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2435 if (card == NULL)
2436 return -ENOMEM;
2437
2438 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2439 snd_card_free(card);
2440 return err;
2441 }
fe8be107 2442 card->private_data = ensoniq;
1da177e4
LT		 2443
2444 pcm_devs[0] = 0; pcm_devs[1] = 1;
2445#ifdef CHIP1370
2446 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2447 snd_card_free(card);
2448 return err;
2449 }
2450#endif
2451#ifdef CHIP1371
2452 if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2453 snd_card_free(card);
2454 return err;
2455 }
2456#endif
2457 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2458 snd_card_free(card);
2459 return err;
2460 }
2461 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2462 snd_card_free(card);
2463 return err;
2464 }
2465 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2466 snd_card_free(card);
2467 return err;
2468 }
2469
2470 snd_ensoniq_create_gameport(ensoniq, dev);
2471
2472 strcpy(card->driver, DRIVER_NAME);
2473
2474 strcpy(card->shortname, "Ensoniq AudioPCI");
2475 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2476 card->shortname,
2477 card->driver,
2478 ensoniq->port,
2479 ensoniq->irq);
2480
2481 if ((err = snd_card_register(card)) < 0) {
2482 snd_card_free(card);
2483 return err;
2484 }
2485
2486 pci_set_drvdata(pci, card);
2487 dev++;
2488 return 0;
2489}
2490
2491static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2492{
2493 snd_card_free(pci_get_drvdata(pci));
2494 pci_set_drvdata(pci, NULL);
2495}
2496
2497static struct pci_driver driver = {
2498 .name = DRIVER_NAME,
2499 .id_table = snd_audiopci_ids,
2500 .probe = snd_audiopci_probe,
2501 .remove = __devexit_p(snd_audiopci_remove),
fe8be107
TI		 2502#ifdef CONFIG_PM
2503 .suspend = snd_ensoniq_suspend,
2504 .resume = snd_ensoniq_resume,
2505#endif
1da177e4
LT		 2506};
2507
2508static int __init alsa_card_ens137x_init(void)
2509{
01d25d46 2510 return pci_register_driver(&driver);
1da177e4
LT		 2511}
2512
2513static void __exit alsa_card_ens137x_exit(void)
2514{
2515 pci_unregister_driver(&driver);
2516}
2517
2518module_init(alsa_card_ens137x_init)
2519module_exit(alsa_card_ens137x_exit)
Linux 6.x block layer and io_uring tree(s)