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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 156
[linux-block.git] / sound / pci / emu10k1 / emu10k1x.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
4 * Driver EMU10K1X chips
5 *
6 * Parts of this code were adapted from audigyls.c driver which is
7 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
8 *
9 * BUGS:
10 * --
11 *
12 * TODO:
13 *
14 * Chips (SB0200 model):
15 * - EMU10K1X-DBQ
16 * - STAC 9708T
1da177e4 17 */
1da177e4
LT		 18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
9d2f928d 21#include <linux/dma-mapping.h>
1da177e4 22#include <linux/slab.h>
65a77217 23#include <linux/module.h>
1da177e4
LT		 24#include <sound/core.h>
25#include <sound/initval.h>
26#include <sound/pcm.h>
27#include <sound/ac97_codec.h>
28#include <sound/info.h>
29#include <sound/rawmidi.h>
30
31MODULE_AUTHOR("Francisco Moraes <fmoraes@nc.rr.com>");
32MODULE_DESCRIPTION("EMU10K1X");
33MODULE_LICENSE("GPL");
34MODULE_SUPPORTED_DEVICE("{{Dell Creative Labs,SB Live!}");
35
36// module parameters (see "Module Parameters")
37static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
38static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 39static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
1da177e4
LT		 40
41module_param_array(index, int, NULL, 0444);
42MODULE_PARM_DESC(index, "Index value for the EMU10K1X soundcard.");
43module_param_array(id, charp, NULL, 0444);
44MODULE_PARM_DESC(id, "ID string for the EMU10K1X soundcard.");
45module_param_array(enable, bool, NULL, 0444);
46MODULE_PARM_DESC(enable, "Enable the EMU10K1X soundcard.");
47
48
49// some definitions were borrowed from emu10k1 driver as they seem to be the same
50/************************************************************************************************/
51/* PCI function 0 registers, address = <val> + PCIBASE0 */
52/************************************************************************************************/
53
54#define PTR 0x00 /* Indexed register set pointer register */
55 /* NOTE: The CHANNELNUM and ADDRESS words can */
56 /* be modified independently of each other. */
57
58#define DATA 0x04 /* Indexed register set data register */
59
60#define IPR 0x08 /* Global interrupt pending register */
61 /* Clear pending interrupts by writing a 1 to */
62 /* the relevant bits and zero to the other bits */
63#define IPR_MIDITRANSBUFEMPTY 0x00000001 /* MIDI UART transmit buffer empty */
64#define IPR_MIDIRECVBUFEMPTY 0x00000002 /* MIDI UART receive buffer empty */
65#define IPR_CH_0_LOOP 0x00000800 /* Channel 0 loop */
66#define IPR_CH_0_HALF_LOOP 0x00000100 /* Channel 0 half loop */
67#define IPR_CAP_0_LOOP 0x00080000 /* Channel capture loop */
68#define IPR_CAP_0_HALF_LOOP 0x00010000 /* Channel capture half loop */
69
70#define INTE 0x0c /* Interrupt enable register */
71#define INTE_MIDITXENABLE 0x00000001 /* Enable MIDI transmit-buffer-empty interrupts */
72#define INTE_MIDIRXENABLE 0x00000002 /* Enable MIDI receive-buffer-empty interrupts */
73#define INTE_CH_0_LOOP 0x00000800 /* Channel 0 loop */
74#define INTE_CH_0_HALF_LOOP 0x00000100 /* Channel 0 half loop */
75#define INTE_CAP_0_LOOP 0x00080000 /* Channel capture loop */
76#define INTE_CAP_0_HALF_LOOP 0x00010000 /* Channel capture half loop */
77
78#define HCFG 0x14 /* Hardware config register */
79
80#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
81 /* NOTE: This should generally never be used. */
82#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
83 /* Should be set to 1 when the EMU10K1 is */
84 /* completely initialized. */
85#define GPIO 0x18 /* Defaults: 00001080-Analog, 00001000-SPDIF. */
86
87
88#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
89
90#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
91
92/********************************************************************************************************/
93/* Emu10k1x pointer-offset register set, accessed through the PTR and DATA registers */
94/********************************************************************************************************/
95#define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */
96 /* One list entry: 4 bytes for DMA address,
97 * 4 bytes for period_size << 16.
98 * One list entry is 8 bytes long.
99 * One list entry for each period in the buffer.
100 */
101#define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
102#define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */
b595076a 103#define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA address */
1da177e4
LT		 104#define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size */
105#define PLAYBACK_POINTER 0x06 /* Playback period pointer. Sample currently in DAC */
106#define PLAYBACK_UNKNOWN1 0x07
107#define PLAYBACK_UNKNOWN2 0x08
108
109/* Only one capture channel supported */
110#define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */
111#define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */
112#define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */
113#define CAPTURE_UNKNOWN 0x13
114
115/* From 0x20 - 0x3f, last samples played on each channel */
116
117#define TRIGGER_CHANNEL 0x40 /* Trigger channel playback */
118#define TRIGGER_CHANNEL_0 0x00000001 /* Trigger channel 0 */
119#define TRIGGER_CHANNEL_1 0x00000002 /* Trigger channel 1 */
120#define TRIGGER_CHANNEL_2 0x00000004 /* Trigger channel 2 */
121#define TRIGGER_CAPTURE 0x00000100 /* Trigger capture channel */
122
123#define ROUTING 0x41 /* Setup sound routing ? */
124#define ROUTING_FRONT_LEFT 0x00000001
125#define ROUTING_FRONT_RIGHT 0x00000002
126#define ROUTING_REAR_LEFT 0x00000004
127#define ROUTING_REAR_RIGHT 0x00000008
128#define ROUTING_CENTER_LFE 0x00010000
129
130#define SPCS0 0x42 /* SPDIF output Channel Status 0 register */
131
132#define SPCS1 0x43 /* SPDIF output Channel Status 1 register */
133
134#define SPCS2 0x44 /* SPDIF output Channel Status 2 register */
135
136#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
137#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
138#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
139#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
140#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
141#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
142#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
143#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
144#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
145#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
146#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
147#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
148#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
149#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
150#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
151#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
152#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
153#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
154#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
155#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
156#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
157#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
158#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
159
160#define SPDIF_SELECT 0x45 /* Enables SPDIF or Analogue outputs 0-Analogue, 0x700-SPDIF */
161
162/* This is the MPU port on the card */
163#define MUDATA 0x47
164#define MUCMD 0x48
165#define MUSTAT MUCMD
166
167/* From 0x50 - 0x5f, last samples captured */
168
ddcecf6b 169/*
1da177e4
LT		 170 * The hardware has 3 channels for playback and 1 for capture.
171 * - channel 0 is the front channel
172 * - channel 1 is the rear channel
af901ca1 173 * - channel 2 is the center/lfe channel
1da177e4
LT		 174 * Volume is controlled by the AC97 for the front and rear channels by
175 * the PCM Playback Volume, Sigmatel Surround Playback Volume and
176 * Surround Playback Volume. The Sigmatel 4-Speaker Stereo switch affects
177 * the front/rear channel mixing in the REAR OUT jack. When using the
178 * 4-Speaker Stereo, both front and rear channels will be mixed in the
179 * REAR OUT.
180 * The center/lfe channel has no volume control and cannot be muted during
181 * playback.
182 */
183
4b32f1aa
TI		 184struct emu10k1x_voice {
185 struct emu10k1x *emu;
1da177e4
LT		 186 int number;
187 int use;
188
4b32f1aa 189 struct emu10k1x_pcm *epcm;
1da177e4
LT		 190};
191
4b32f1aa
TI		 192struct emu10k1x_pcm {
193 struct emu10k1x *emu;
194 struct snd_pcm_substream *substream;
195 struct emu10k1x_voice *voice;
1da177e4
LT		 196 unsigned short running;
197};
198
4b32f1aa
TI		 199struct emu10k1x_midi {
200 struct emu10k1x *emu;
201 struct snd_rawmidi *rmidi;
202 struct snd_rawmidi_substream *substream_input;
203 struct snd_rawmidi_substream *substream_output;
1da177e4
LT		 204 unsigned int midi_mode;
205 spinlock_t input_lock;
206 spinlock_t output_lock;
207 spinlock_t open_lock;
208 int tx_enable, rx_enable;
209 int port;
210 int ipr_tx, ipr_rx;
4b32f1aa
TI		 211 void (*interrupt)(struct emu10k1x *emu, unsigned int status);
212};
1da177e4
LT		 213
214// definition of the chip-specific record
4b32f1aa
TI		 215struct emu10k1x {
216 struct snd_card *card;
1da177e4
LT		 217 struct pci_dev *pci;
218
219 unsigned long port;
220 struct resource *res_port;
221 int irq;
222
01f681da 223 unsigned char revision; /* chip revision */
1da177e4
LT		 224 unsigned int serial; /* serial number */
225 unsigned short model; /* subsystem id */
226
227 spinlock_t emu_lock;
228 spinlock_t voice_lock;
229
4b32f1aa
TI		 230 struct snd_ac97 *ac97;
231 struct snd_pcm *pcm;
1da177e4 232
4b32f1aa
TI		 233 struct emu10k1x_voice voices[3];
234 struct emu10k1x_voice capture_voice;
1da177e4
LT		 235 u32 spdif_bits[3]; // SPDIF out setup
236
237 struct snd_dma_buffer dma_buffer;
238
4b32f1aa 239 struct emu10k1x_midi midi;
1da177e4
LT		 240};
241
242/* hardware definition */
7c0ddf06 243static const struct snd_pcm_hardware snd_emu10k1x_playback_hw = {
1da177e4
LT		 244 .info = (SNDRV_PCM_INFO_MMAP |
245 SNDRV_PCM_INFO_INTERLEAVED |
246 SNDRV_PCM_INFO_BLOCK_TRANSFER |
247 SNDRV_PCM_INFO_MMAP_VALID),
248 .formats = SNDRV_PCM_FMTBIT_S16_LE,
249 .rates = SNDRV_PCM_RATE_48000,
250 .rate_min = 48000,
251 .rate_max = 48000,
252 .channels_min = 2,
253 .channels_max = 2,
254 .buffer_bytes_max = (32*1024),
255 .period_bytes_min = 64,
256 .period_bytes_max = (16*1024),
257 .periods_min = 2,
258 .periods_max = 8,
259 .fifo_size = 0,
260};
261
7c0ddf06 262static const struct snd_pcm_hardware snd_emu10k1x_capture_hw = {
1da177e4
LT		 263 .info = (SNDRV_PCM_INFO_MMAP |
264 SNDRV_PCM_INFO_INTERLEAVED |
265 SNDRV_PCM_INFO_BLOCK_TRANSFER |
266 SNDRV_PCM_INFO_MMAP_VALID),
267 .formats = SNDRV_PCM_FMTBIT_S16_LE,
268 .rates = SNDRV_PCM_RATE_48000,
269 .rate_min = 48000,
270 .rate_max = 48000,
271 .channels_min = 2,
272 .channels_max = 2,
273 .buffer_bytes_max = (32*1024),
274 .period_bytes_min = 64,
275 .period_bytes_max = (16*1024),
276 .periods_min = 2,
277 .periods_max = 2,
278 .fifo_size = 0,
279};
280
4b32f1aa 281static unsigned int snd_emu10k1x_ptr_read(struct emu10k1x * emu,
1da177e4
LT		 282 unsigned int reg,
283 unsigned int chn)
284{
285 unsigned long flags;
286 unsigned int regptr, val;
287
288 regptr = (reg << 16) | chn;
289
290 spin_lock_irqsave(&emu->emu_lock, flags);
291 outl(regptr, emu->port + PTR);
292 val = inl(emu->port + DATA);
293 spin_unlock_irqrestore(&emu->emu_lock, flags);
294 return val;
295}
296
4b32f1aa 297static void snd_emu10k1x_ptr_write(struct emu10k1x *emu,
1da177e4
LT		 298 unsigned int reg,
299 unsigned int chn,
300 unsigned int data)
301{
302 unsigned int regptr;
303 unsigned long flags;
304
305 regptr = (reg << 16) | chn;
306
307 spin_lock_irqsave(&emu->emu_lock, flags);
308 outl(regptr, emu->port + PTR);
309 outl(data, emu->port + DATA);
310 spin_unlock_irqrestore(&emu->emu_lock, flags);
311}
312
4b32f1aa 313static void snd_emu10k1x_intr_enable(struct emu10k1x *emu, unsigned int intrenb)
1da177e4
LT		 314{
315 unsigned long flags;
f2948fc2
HH		 316 unsigned int intr_enable;
317
1da177e4 318 spin_lock_irqsave(&emu->emu_lock, flags);
f2948fc2
HH		 319 intr_enable = inl(emu->port + INTE) | intrenb;
320 outl(intr_enable, emu->port + INTE);
1da177e4
LT		 321 spin_unlock_irqrestore(&emu->emu_lock, flags);
322}
323
4b32f1aa 324static void snd_emu10k1x_intr_disable(struct emu10k1x *emu, unsigned int intrenb)
1da177e4
LT		 325{
326 unsigned long flags;
f2948fc2
HH		 327 unsigned int intr_enable;
328
1da177e4 329 spin_lock_irqsave(&emu->emu_lock, flags);
f2948fc2
HH		 330 intr_enable = inl(emu->port + INTE) & ~intrenb;
331 outl(intr_enable, emu->port + INTE);
1da177e4
LT		 332 spin_unlock_irqrestore(&emu->emu_lock, flags);
333}
334
4b32f1aa 335static void snd_emu10k1x_gpio_write(struct emu10k1x *emu, unsigned int value)
1da177e4
LT		 336{
337 unsigned long flags;
338
339 spin_lock_irqsave(&emu->emu_lock, flags);
340 outl(value, emu->port + GPIO);
341 spin_unlock_irqrestore(&emu->emu_lock, flags);
342}
343
4b32f1aa 344static void snd_emu10k1x_pcm_free_substream(struct snd_pcm_runtime *runtime)
1da177e4 345{
4d572776 346 kfree(runtime->private_data);
1da177e4
LT		 347}
348
4b32f1aa 349static void snd_emu10k1x_pcm_interrupt(struct emu10k1x *emu, struct emu10k1x_voice *voice)
1da177e4 350{
4b32f1aa 351 struct emu10k1x_pcm *epcm;
1da177e4
LT		 352
353 if ((epcm = voice->epcm) == NULL)
354 return;
355 if (epcm->substream == NULL)
356 return;
357#if 0
26bc6964
TI		 358 dev_info(emu->card->dev,
359 "IRQ: position = 0x%x, period = 0x%x, size = 0x%x\n",
1da177e4
LT		 360 epcm->substream->ops->pointer(epcm->substream),
361 snd_pcm_lib_period_bytes(epcm->substream),
362 snd_pcm_lib_buffer_bytes(epcm->substream));
363#endif
364 snd_pcm_period_elapsed(epcm->substream);
365}
366
367/* open callback */
4b32f1aa 368static int snd_emu10k1x_playback_open(struct snd_pcm_substream *substream)
1da177e4 369{
4b32f1aa
TI		 370 struct emu10k1x *chip = snd_pcm_substream_chip(substream);
371 struct emu10k1x_pcm *epcm;
372 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 373 int err;
374
375 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) {
376 return err;
377 }
378 if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
379 return err;
380
e560d8d8 381 epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
1da177e4
LT		 382 if (epcm == NULL)
383 return -ENOMEM;
384 epcm->emu = chip;
385 epcm->substream = substream;
386
387 runtime->private_data = epcm;
388 runtime->private_free = snd_emu10k1x_pcm_free_substream;
389
390 runtime->hw = snd_emu10k1x_playback_hw;
391
392 return 0;
393}
394
395/* close callback */
4b32f1aa 396static int snd_emu10k1x_playback_close(struct snd_pcm_substream *substream)
1da177e4
LT		 397{
398 return 0;
399}
400
401/* hw_params callback */
4b32f1aa
TI		 402static int snd_emu10k1x_pcm_hw_params(struct snd_pcm_substream *substream,
403 struct snd_pcm_hw_params *hw_params)
1da177e4 404{
4b32f1aa
TI		 405 struct snd_pcm_runtime *runtime = substream->runtime;
406 struct emu10k1x_pcm *epcm = runtime->private_data;
1da177e4
LT		 407
408 if (! epcm->voice) {
409 epcm->voice = &epcm->emu->voices[substream->pcm->device];
410 epcm->voice->use = 1;
411 epcm->voice->epcm = epcm;
412 }
413
414 return snd_pcm_lib_malloc_pages(substream,
415 params_buffer_bytes(hw_params));
416}
417
418/* hw_free callback */
4b32f1aa 419static int snd_emu10k1x_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4 420{
4b32f1aa
TI		 421 struct snd_pcm_runtime *runtime = substream->runtime;
422 struct emu10k1x_pcm *epcm;
1da177e4
LT		 423
424 if (runtime->private_data == NULL)
425 return 0;
426
427 epcm = runtime->private_data;
428
429 if (epcm->voice) {
430 epcm->voice->use = 0;
431 epcm->voice->epcm = NULL;
432 epcm->voice = NULL;
433 }
434
435 return snd_pcm_lib_free_pages(substream);
436}
437
438/* prepare callback */
4b32f1aa 439static int snd_emu10k1x_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 440{
4b32f1aa
TI		 441 struct emu10k1x *emu = snd_pcm_substream_chip(substream);
442 struct snd_pcm_runtime *runtime = substream->runtime;
443 struct emu10k1x_pcm *epcm = runtime->private_data;
1da177e4
LT		 444 int voice = epcm->voice->number;
445 u32 *table_base = (u32 *)(emu->dma_buffer.area+1024*voice);
446 u32 period_size_bytes = frames_to_bytes(runtime, runtime->period_size);
447 int i;
448
9f4bd5dd 449 for(i = 0; i < runtime->periods; i++) {
1da177e4
LT		 450 *table_base++=runtime->dma_addr+(i*period_size_bytes);
451 *table_base++=period_size_bytes<<16;
452 }
453
454 snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_ADDR, voice, emu->dma_buffer.addr+1024*voice);
455 snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_SIZE, voice, (runtime->periods - 1) << 19);
456 snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_PTR, voice, 0);
457 snd_emu10k1x_ptr_write(emu, PLAYBACK_POINTER, voice, 0);
458 snd_emu10k1x_ptr_write(emu, PLAYBACK_UNKNOWN1, voice, 0);
459 snd_emu10k1x_ptr_write(emu, PLAYBACK_UNKNOWN2, voice, 0);
460 snd_emu10k1x_ptr_write(emu, PLAYBACK_DMA_ADDR, voice, runtime->dma_addr);
461
462 snd_emu10k1x_ptr_write(emu, PLAYBACK_PERIOD_SIZE, voice, frames_to_bytes(runtime, runtime->period_size)<<16);
463
464 return 0;
465}
466
467/* trigger callback */
4b32f1aa 468static int snd_emu10k1x_pcm_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 469 int cmd)
470{
4b32f1aa
TI		 471 struct emu10k1x *emu = snd_pcm_substream_chip(substream);
472 struct snd_pcm_runtime *runtime = substream->runtime;
473 struct emu10k1x_pcm *epcm = runtime->private_data;
1da177e4
LT		 474 int channel = epcm->voice->number;
475 int result = 0;
476
26bc6964
TI		 477 /*
478 dev_dbg(emu->card->dev,
479 "trigger - emu10k1x = 0x%x, cmd = %i, pointer = %d\n",
480 (int)emu, cmd, (int)substream->ops->pointer(substream));
481 */
1da177e4
LT		 482
483 switch (cmd) {
484 case SNDRV_PCM_TRIGGER_START:
485 if(runtime->periods == 2)
486 snd_emu10k1x_intr_enable(emu, (INTE_CH_0_LOOP | INTE_CH_0_HALF_LOOP) << channel);
487 else
488 snd_emu10k1x_intr_enable(emu, INTE_CH_0_LOOP << channel);
489 epcm->running = 1;
490 snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0)|(TRIGGER_CHANNEL_0<<channel));
491 break;
492 case SNDRV_PCM_TRIGGER_STOP:
493 epcm->running = 0;
494 snd_emu10k1x_intr_disable(emu, (INTE_CH_0_LOOP | INTE_CH_0_HALF_LOOP) << channel);
495 snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0) & ~(TRIGGER_CHANNEL_0<<channel));
496 break;
497 default:
498 result = -EINVAL;
499 break;
500 }
501 return result;
502}
503
504/* pointer callback */
505static snd_pcm_uframes_t
4b32f1aa 506snd_emu10k1x_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 507{
4b32f1aa
TI		 508 struct emu10k1x *emu = snd_pcm_substream_chip(substream);
509 struct snd_pcm_runtime *runtime = substream->runtime;
510 struct emu10k1x_pcm *epcm = runtime->private_data;
1da177e4
LT		 511 int channel = epcm->voice->number;
512 snd_pcm_uframes_t ptr = 0, ptr1 = 0, ptr2= 0,ptr3 = 0,ptr4 = 0;
513
514 if (!epcm->running)
515 return 0;
516
517 ptr3 = snd_emu10k1x_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
518 ptr1 = snd_emu10k1x_ptr_read(emu, PLAYBACK_POINTER, channel);
519 ptr4 = snd_emu10k1x_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
520
521 if(ptr4 == 0 && ptr1 == frames_to_bytes(runtime, runtime->buffer_size))
522 return 0;
523
524 if (ptr3 != ptr4)
525 ptr1 = snd_emu10k1x_ptr_read(emu, PLAYBACK_POINTER, channel);
526 ptr2 = bytes_to_frames(runtime, ptr1);
527 ptr2 += (ptr4 >> 3) * runtime->period_size;
528 ptr = ptr2;
529
530 if (ptr >= runtime->buffer_size)
531 ptr -= runtime->buffer_size;
532
533 return ptr;
534}
535
536/* operators */
6769e988 537static const struct snd_pcm_ops snd_emu10k1x_playback_ops = {
1da177e4
LT		 538 .open = snd_emu10k1x_playback_open,
539 .close = snd_emu10k1x_playback_close,
540 .ioctl = snd_pcm_lib_ioctl,
541 .hw_params = snd_emu10k1x_pcm_hw_params,
542 .hw_free = snd_emu10k1x_pcm_hw_free,
543 .prepare = snd_emu10k1x_pcm_prepare,
544 .trigger = snd_emu10k1x_pcm_trigger,
545 .pointer = snd_emu10k1x_pcm_pointer,
546};
547
548/* open_capture callback */
4b32f1aa 549static int snd_emu10k1x_pcm_open_capture(struct snd_pcm_substream *substream)
1da177e4 550{
4b32f1aa
TI		 551 struct emu10k1x *chip = snd_pcm_substream_chip(substream);
552 struct emu10k1x_pcm *epcm;
553 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 554 int err;
555
556 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
557 return err;
558 if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
559 return err;
560
e560d8d8 561 epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
1da177e4
LT		 562 if (epcm == NULL)
563 return -ENOMEM;
564
565 epcm->emu = chip;
566 epcm->substream = substream;
567
568 runtime->private_data = epcm;
569 runtime->private_free = snd_emu10k1x_pcm_free_substream;
570
571 runtime->hw = snd_emu10k1x_capture_hw;
572
573 return 0;
574}
575
576/* close callback */
4b32f1aa 577static int snd_emu10k1x_pcm_close_capture(struct snd_pcm_substream *substream)
1da177e4
LT		 578{
579 return 0;
580}
581
582/* hw_params callback */
4b32f1aa
TI		 583static int snd_emu10k1x_pcm_hw_params_capture(struct snd_pcm_substream *substream,
584 struct snd_pcm_hw_params *hw_params)
1da177e4 585{
4b32f1aa
TI		 586 struct snd_pcm_runtime *runtime = substream->runtime;
587 struct emu10k1x_pcm *epcm = runtime->private_data;
1da177e4
LT		 588
589 if (! epcm->voice) {
590 if (epcm->emu->capture_voice.use)
591 return -EBUSY;
592 epcm->voice = &epcm->emu->capture_voice;
593 epcm->voice->epcm = epcm;
594 epcm->voice->use = 1;
595 }
596
597 return snd_pcm_lib_malloc_pages(substream,
598 params_buffer_bytes(hw_params));
599}
600
601/* hw_free callback */
4b32f1aa 602static int snd_emu10k1x_pcm_hw_free_capture(struct snd_pcm_substream *substream)
1da177e4 603{
4b32f1aa 604 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 605
4b32f1aa 606 struct emu10k1x_pcm *epcm;
1da177e4
LT		 607
608 if (runtime->private_data == NULL)
609 return 0;
610 epcm = runtime->private_data;
611
612 if (epcm->voice) {
613 epcm->voice->use = 0;
614 epcm->voice->epcm = NULL;
615 epcm->voice = NULL;
616 }
617
618 return snd_pcm_lib_free_pages(substream);
619}
620
621/* prepare capture callback */
4b32f1aa 622static int snd_emu10k1x_pcm_prepare_capture(struct snd_pcm_substream *substream)
1da177e4 623{
4b32f1aa
TI		 624 struct emu10k1x *emu = snd_pcm_substream_chip(substream);
625 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 626
627 snd_emu10k1x_ptr_write(emu, CAPTURE_DMA_ADDR, 0, runtime->dma_addr);
628 snd_emu10k1x_ptr_write(emu, CAPTURE_BUFFER_SIZE, 0, frames_to_bytes(runtime, runtime->buffer_size)<<16); // buffer size in bytes
629 snd_emu10k1x_ptr_write(emu, CAPTURE_POINTER, 0, 0);
630 snd_emu10k1x_ptr_write(emu, CAPTURE_UNKNOWN, 0, 0);
631
632 return 0;
633}
634
635/* trigger_capture callback */
4b32f1aa 636static int snd_emu10k1x_pcm_trigger_capture(struct snd_pcm_substream *substream,
1da177e4
LT		 637 int cmd)
638{
4b32f1aa
TI		 639 struct emu10k1x *emu = snd_pcm_substream_chip(substream);
640 struct snd_pcm_runtime *runtime = substream->runtime;
641 struct emu10k1x_pcm *epcm = runtime->private_data;
1da177e4
LT		 642 int result = 0;
643
644 switch (cmd) {
645 case SNDRV_PCM_TRIGGER_START:
646 snd_emu10k1x_intr_enable(emu, INTE_CAP_0_LOOP |
647 INTE_CAP_0_HALF_LOOP);
648 snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0)|TRIGGER_CAPTURE);
649 epcm->running = 1;
650 break;
651 case SNDRV_PCM_TRIGGER_STOP:
652 epcm->running = 0;
653 snd_emu10k1x_intr_disable(emu, INTE_CAP_0_LOOP |
654 INTE_CAP_0_HALF_LOOP);
655 snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0) & ~(TRIGGER_CAPTURE));
656 break;
657 default:
658 result = -EINVAL;
659 break;
660 }
661 return result;
662}
663
664/* pointer_capture callback */
665static snd_pcm_uframes_t
4b32f1aa 666snd_emu10k1x_pcm_pointer_capture(struct snd_pcm_substream *substream)
1da177e4 667{
4b32f1aa
TI		 668 struct emu10k1x *emu = snd_pcm_substream_chip(substream);
669 struct snd_pcm_runtime *runtime = substream->runtime;
670 struct emu10k1x_pcm *epcm = runtime->private_data;
1da177e4
LT		 671 snd_pcm_uframes_t ptr;
672
673 if (!epcm->running)
674 return 0;
675
676 ptr = bytes_to_frames(runtime, snd_emu10k1x_ptr_read(emu, CAPTURE_POINTER, 0));
677 if (ptr >= runtime->buffer_size)
678 ptr -= runtime->buffer_size;
679
680 return ptr;
681}
682
6769e988 683static const struct snd_pcm_ops snd_emu10k1x_capture_ops = {
1da177e4
LT		 684 .open = snd_emu10k1x_pcm_open_capture,
685 .close = snd_emu10k1x_pcm_close_capture,
686 .ioctl = snd_pcm_lib_ioctl,
687 .hw_params = snd_emu10k1x_pcm_hw_params_capture,
688 .hw_free = snd_emu10k1x_pcm_hw_free_capture,
689 .prepare = snd_emu10k1x_pcm_prepare_capture,
690 .trigger = snd_emu10k1x_pcm_trigger_capture,
691 .pointer = snd_emu10k1x_pcm_pointer_capture,
692};
693
4b32f1aa 694static unsigned short snd_emu10k1x_ac97_read(struct snd_ac97 *ac97,
1da177e4
LT		 695 unsigned short reg)
696{
4b32f1aa 697 struct emu10k1x *emu = ac97->private_data;
1da177e4
LT		 698 unsigned long flags;
699 unsigned short val;
700
701 spin_lock_irqsave(&emu->emu_lock, flags);
702 outb(reg, emu->port + AC97ADDRESS);
703 val = inw(emu->port + AC97DATA);
704 spin_unlock_irqrestore(&emu->emu_lock, flags);
705 return val;
706}
707
4b32f1aa 708static void snd_emu10k1x_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 709 unsigned short reg, unsigned short val)
710{
4b32f1aa 711 struct emu10k1x *emu = ac97->private_data;
1da177e4
LT		 712 unsigned long flags;
713
714 spin_lock_irqsave(&emu->emu_lock, flags);
715 outb(reg, emu->port + AC97ADDRESS);
716 outw(val, emu->port + AC97DATA);
717 spin_unlock_irqrestore(&emu->emu_lock, flags);
718}
719
4b32f1aa 720static int snd_emu10k1x_ac97(struct emu10k1x *chip)
1da177e4 721{
4b32f1aa
TI		 722 struct snd_ac97_bus *pbus;
723 struct snd_ac97_template ac97;
1da177e4 724 int err;
4b32f1aa 725 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 726 .write = snd_emu10k1x_ac97_write,
727 .read = snd_emu10k1x_ac97_read,
728 };
729
730 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
731 return err;
732 pbus->no_vra = 1; /* we don't need VRA */
733
734 memset(&ac97, 0, sizeof(ac97));
735 ac97.private_data = chip;
736 ac97.scaps = AC97_SCAP_NO_SPDIF;
737 return snd_ac97_mixer(pbus, &ac97, &chip->ac97);
738}
739
4b32f1aa 740static int snd_emu10k1x_free(struct emu10k1x *chip)
1da177e4
LT		 741{
742 snd_emu10k1x_ptr_write(chip, TRIGGER_CHANNEL, 0, 0);
743 // disable interrupts
744 outl(0, chip->port + INTE);
745 // disable audio
746 outl(HCFG_LOCKSOUNDCACHE, chip->port + HCFG);
747
ebf029da 748 /* release the irq */
1da177e4 749 if (chip->irq >= 0)
437a5a46 750 free_irq(chip->irq, chip);
1da177e4 751
ebf029da
TI		 752 // release the i/o port
753 release_and_free_resource(chip->res_port);
754
1da177e4
LT		 755 // release the DMA
756 if (chip->dma_buffer.area) {
757 snd_dma_free_pages(&chip->dma_buffer);
758 }
759
760 pci_disable_device(chip->pci);
761
762 // release the data
763 kfree(chip);
764 return 0;
765}
766
4b32f1aa 767static int snd_emu10k1x_dev_free(struct snd_device *device)
1da177e4 768{
4b32f1aa 769 struct emu10k1x *chip = device->device_data;
1da177e4
LT		 770 return snd_emu10k1x_free(chip);
771}
772
7d12e780 773static irqreturn_t snd_emu10k1x_interrupt(int irq, void *dev_id)
1da177e4
LT		 774{
775 unsigned int status;
776
4b32f1aa
TI		 777 struct emu10k1x *chip = dev_id;
778 struct emu10k1x_voice *pvoice = chip->voices;
1da177e4
LT		 779 int i;
780 int mask;
781
782 status = inl(chip->port + IPR);
783
89173bd4
TI		 784 if (! status)
785 return IRQ_NONE;
786
787 // capture interrupt
788 if (status & (IPR_CAP_0_LOOP | IPR_CAP_0_HALF_LOOP)) {
f2948fc2
HH		 789 struct emu10k1x_voice *cap_voice = &chip->capture_voice;
790 if (cap_voice->use)
791 snd_emu10k1x_pcm_interrupt(chip, cap_voice);
89173bd4
TI		 792 else
793 snd_emu10k1x_intr_disable(chip,
794 INTE_CAP_0_LOOP |
795 INTE_CAP_0_HALF_LOOP);
796 }
1da177e4 797
89173bd4
TI		 798 mask = IPR_CH_0_LOOP|IPR_CH_0_HALF_LOOP;
799 for (i = 0; i < 3; i++) {
800 if (status & mask) {
801 if (pvoice->use)
802 snd_emu10k1x_pcm_interrupt(chip, pvoice);
803 else
804 snd_emu10k1x_intr_disable(chip, mask);
1da177e4 805 }
89173bd4
TI		 806 pvoice++;
807 mask <<= 1;
808 }
1da177e4 809
89173bd4
TI		 810 if (status & (IPR_MIDITRANSBUFEMPTY|IPR_MIDIRECVBUFEMPTY)) {
811 if (chip->midi.interrupt)
812 chip->midi.interrupt(chip, status);
813 else
814 snd_emu10k1x_intr_disable(chip, INTE_MIDITXENABLE|INTE_MIDIRXENABLE);
1da177e4 815 }
89173bd4
TI		 816
817 // acknowledge the interrupt if necessary
818 outl(status, chip->port + IPR);
1da177e4 819
26bc6964 820 /* dev_dbg(chip->card->dev, "interrupt %08x\n", status); */
1da177e4
LT		 821 return IRQ_HANDLED;
822}
823
3adc497f
TI		 824static const struct snd_pcm_chmap_elem surround_map[] = {
825 { .channels = 2,
826 .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
827 { }
828};
829
830static const struct snd_pcm_chmap_elem clfe_map[] = {
831 { .channels = 2,
832 .map = { SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE } },
833 { }
834};
835
bb814c39 836static int snd_emu10k1x_pcm(struct emu10k1x *emu, int device)
1da177e4 837{
4b32f1aa 838 struct snd_pcm *pcm;
3adc497f 839 const struct snd_pcm_chmap_elem *map = NULL;
1da177e4
LT		 840 int err;
841 int capture = 0;
842
1da177e4
LT		 843 if (device == 0)
844 capture = 1;
845
846 if ((err = snd_pcm_new(emu->card, "emu10k1x", device, 1, capture, &pcm)) < 0)
847 return err;
848
849 pcm->private_data = emu;
1da177e4
LT		 850
851 switch(device) {
852 case 0:
853 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1x_playback_ops);
854 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_emu10k1x_capture_ops);
855 break;
856 case 1:
857 case 2:
858 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1x_playback_ops);
859 break;
860 }
861
862 pcm->info_flags = 0;
1da177e4
LT		 863 switch(device) {
864 case 0:
865 strcpy(pcm->name, "EMU10K1X Front");
3adc497f 866 map = snd_pcm_std_chmaps;
1da177e4
LT		 867 break;
868 case 1:
869 strcpy(pcm->name, "EMU10K1X Rear");
3adc497f 870 map = surround_map;
1da177e4
LT		 871 break;
872 case 2:
873 strcpy(pcm->name, "EMU10K1X Center/LFE");
3adc497f 874 map = clfe_map;
1da177e4
LT		 875 break;
876 }
877 emu->pcm = pcm;
878
879 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
880 snd_dma_pci_data(emu->pci),
881 32*1024, 32*1024);
882
bb814c39 883 return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, map, 2,
3adc497f 884 1 << 2, NULL);
1da177e4
LT		 885}
886
e23e7a14
BP		 887static int snd_emu10k1x_create(struct snd_card *card,
888 struct pci_dev *pci,
889 struct emu10k1x **rchip)
1da177e4 890{
4b32f1aa 891 struct emu10k1x *chip;
1da177e4
LT		 892 int err;
893 int ch;
4b32f1aa 894 static struct snd_device_ops ops = {
1da177e4
LT		 895 .dev_free = snd_emu10k1x_dev_free,
896 };
9d2f928d 897
1da177e4 898 *rchip = NULL;
9d2f928d 899
1da177e4
LT		 900 if ((err = pci_enable_device(pci)) < 0)
901 return err;
ce0b6201
YH		 902 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
903 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
26bc6964 904 dev_err(card->dev, "error to set 28bit mask DMA\n");
1da177e4
LT		 905 pci_disable_device(pci);
906 return -ENXIO;
907 }
9d2f928d 908
e560d8d8 909 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 910 if (chip == NULL) {
911 pci_disable_device(pci);
912 return -ENOMEM;
913 }
9d2f928d 914
1da177e4
LT		 915 chip->card = card;
916 chip->pci = pci;
917 chip->irq = -1;
918
919 spin_lock_init(&chip->emu_lock);
920 spin_lock_init(&chip->voice_lock);
921
922 chip->port = pci_resource_start(pci, 0);
923 if ((chip->res_port = request_region(chip->port, 8,
924 "EMU10K1X")) == NULL) {
26bc6964
TI		 925 dev_err(card->dev, "cannot allocate the port 0x%lx\n",
926 chip->port);
1da177e4
LT		 927 snd_emu10k1x_free(chip);
928 return -EBUSY;
929 }
930
931 if (request_irq(pci->irq, snd_emu10k1x_interrupt,
934c2b6d 932 IRQF_SHARED, KBUILD_MODNAME, chip)) {
26bc6964 933 dev_err(card->dev, "cannot grab irq %d\n", pci->irq);
1da177e4
LT		 934 snd_emu10k1x_free(chip);
935 return -EBUSY;
936 }
937 chip->irq = pci->irq;
938
939 if(snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
940 4 * 1024, &chip->dma_buffer) < 0) {
941 snd_emu10k1x_free(chip);
942 return -ENOMEM;
943 }
944
945 pci_set_master(pci);
946 /* read revision & serial */
44c10138 947 chip->revision = pci->revision;
1da177e4
LT		 948 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &chip->serial);
949 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &chip->model);
26bc6964 950 dev_info(card->dev, "Model %04x Rev %08x Serial %08x\n", chip->model,
1da177e4
LT		 951 chip->revision, chip->serial);
952
953 outl(0, chip->port + INTE);
954
955 for(ch = 0; ch < 3; ch++) {
956 chip->voices[ch].emu = chip;
957 chip->voices[ch].number = ch;
958 }
959
960 /*
961 * Init to 0x02109204 :
962 * Clock accuracy = 0 (1000ppm)
963 * Sample Rate = 2 (48kHz)
964 * Audio Channel = 1 (Left of 2)
965 * Source Number = 0 (Unspecified)
966 * Generation Status = 1 (Original for Cat Code 12)
967 * Cat Code = 12 (Digital Signal Mixer)
968 * Mode = 0 (Mode 0)
969 * Emphasis = 0 (None)
970 * CP = 1 (Copyright unasserted)
971 * AN = 0 (Audio data)
972 * P = 0 (Consumer)
973 */
974 snd_emu10k1x_ptr_write(chip, SPCS0, 0,
975 chip->spdif_bits[0] =
976 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
977 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
978 SPCS_GENERATIONSTATUS | 0x00001200 |
979 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
980 snd_emu10k1x_ptr_write(chip, SPCS1, 0,
981 chip->spdif_bits[1] =
982 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
983 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
984 SPCS_GENERATIONSTATUS | 0x00001200 |
985 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
986 snd_emu10k1x_ptr_write(chip, SPCS2, 0,
987 chip->spdif_bits[2] =
988 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
989 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
990 SPCS_GENERATIONSTATUS | 0x00001200 |
991 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
992
993 snd_emu10k1x_ptr_write(chip, SPDIF_SELECT, 0, 0x700); // disable SPDIF
994 snd_emu10k1x_ptr_write(chip, ROUTING, 0, 0x1003F); // routing
995 snd_emu10k1x_gpio_write(chip, 0x1080); // analog mode
996
997 outl(HCFG_LOCKSOUNDCACHE|HCFG_AUDIOENABLE, chip->port+HCFG);
998
999 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
1000 chip, &ops)) < 0) {
1001 snd_emu10k1x_free(chip);
1002 return err;
1003 }
1004 *rchip = chip;
1005 return 0;
1006}
1007
4b32f1aa
TI		 1008static void snd_emu10k1x_proc_reg_read(struct snd_info_entry *entry,
1009 struct snd_info_buffer *buffer)
1da177e4 1010{
4b32f1aa 1011 struct emu10k1x *emu = entry->private_data;
1da177e4
LT		 1012 unsigned long value,value1,value2;
1013 unsigned long flags;
1014 int i;
1015
1016 snd_iprintf(buffer, "Registers:\n\n");
1017 for(i = 0; i < 0x20; i+=4) {
1018 spin_lock_irqsave(&emu->emu_lock, flags);
1019 value = inl(emu->port + i);
1020 spin_unlock_irqrestore(&emu->emu_lock, flags);
1021 snd_iprintf(buffer, "Register %02X: %08lX\n", i, value);
1022 }
1023 snd_iprintf(buffer, "\nRegisters\n\n");
1024 for(i = 0; i <= 0x48; i++) {
1025 value = snd_emu10k1x_ptr_read(emu, i, 0);
1026 if(i < 0x10 || (i >= 0x20 && i < 0x40)) {
1027 value1 = snd_emu10k1x_ptr_read(emu, i, 1);
1028 value2 = snd_emu10k1x_ptr_read(emu, i, 2);
1029 snd_iprintf(buffer, "%02X: %08lX %08lX %08lX\n", i, value, value1, value2);
1030 } else {
1031 snd_iprintf(buffer, "%02X: %08lX\n", i, value);
1032 }
1033 }
1034}
1035
4b32f1aa
TI		 1036static void snd_emu10k1x_proc_reg_write(struct snd_info_entry *entry,
1037 struct snd_info_buffer *buffer)
1da177e4 1038{
4b32f1aa 1039 struct emu10k1x *emu = entry->private_data;
1da177e4
LT		 1040 char line[64];
1041 unsigned int reg, channel_id , val;
1042
1043 while (!snd_info_get_line(buffer, line, sizeof(line))) {
1044 if (sscanf(line, "%x %x %x", &reg, &channel_id, &val) != 3)
1045 continue;
1046
84ed1a19 1047 if (reg < 0x49 && val <= 0xffffffff && channel_id <= 2)
1da177e4
LT		 1048 snd_emu10k1x_ptr_write(emu, reg, channel_id, val);
1049 }
1050}
1051
e23e7a14 1052static int snd_emu10k1x_proc_init(struct emu10k1x *emu)
1da177e4 1053{
47f2769b
TI		 1054 snd_card_rw_proc_new(emu->card, "emu10k1x_regs", emu,
1055 snd_emu10k1x_proc_reg_read,
1056 snd_emu10k1x_proc_reg_write);
1da177e4
LT		 1057 return 0;
1058}
1059
a5ce8890 1060#define snd_emu10k1x_shared_spdif_info snd_ctl_boolean_mono_info
1da177e4 1061
4b32f1aa
TI		 1062static int snd_emu10k1x_shared_spdif_get(struct snd_kcontrol *kcontrol,
1063 struct snd_ctl_elem_value *ucontrol)
1da177e4 1064{
4b32f1aa 1065 struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1066
1067 ucontrol->value.integer.value[0] = (snd_emu10k1x_ptr_read(emu, SPDIF_SELECT, 0) == 0x700) ? 0 : 1;
1068
1069 return 0;
1070}
1071
4b32f1aa
TI		 1072static int snd_emu10k1x_shared_spdif_put(struct snd_kcontrol *kcontrol,
1073 struct snd_ctl_elem_value *ucontrol)
1da177e4 1074{
4b32f1aa 1075 struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1076 unsigned int val;
1077 int change = 0;
1078
1079 val = ucontrol->value.integer.value[0] ;
1080
1081 if (val) {
1082 // enable spdif output
1083 snd_emu10k1x_ptr_write(emu, SPDIF_SELECT, 0, 0x000);
1084 snd_emu10k1x_ptr_write(emu, ROUTING, 0, 0x700);
1085 snd_emu10k1x_gpio_write(emu, 0x1000);
1086 } else {
1087 // disable spdif output
1088 snd_emu10k1x_ptr_write(emu, SPDIF_SELECT, 0, 0x700);
1089 snd_emu10k1x_ptr_write(emu, ROUTING, 0, 0x1003F);
1090 snd_emu10k1x_gpio_write(emu, 0x1080);
1091 }
1092 return change;
1093}
1094
f3b827e0 1095static const struct snd_kcontrol_new snd_emu10k1x_shared_spdif =
1da177e4
LT		 1096{
1097 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1098 .name = "Analog/Digital Output Jack",
1099 .info = snd_emu10k1x_shared_spdif_info,
1100 .get = snd_emu10k1x_shared_spdif_get,
1101 .put = snd_emu10k1x_shared_spdif_put
1102};
1103
4b32f1aa 1104static int snd_emu10k1x_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1105{
1106 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1107 uinfo->count = 1;
1108 return 0;
1109}
1110
4b32f1aa
TI		 1111static int snd_emu10k1x_spdif_get(struct snd_kcontrol *kcontrol,
1112 struct snd_ctl_elem_value *ucontrol)
1da177e4 1113{
4b32f1aa 1114 struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1115 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1116
1117 ucontrol->value.iec958.status[0] = (emu->spdif_bits[idx] >> 0) & 0xff;
1118 ucontrol->value.iec958.status[1] = (emu->spdif_bits[idx] >> 8) & 0xff;
1119 ucontrol->value.iec958.status[2] = (emu->spdif_bits[idx] >> 16) & 0xff;
1120 ucontrol->value.iec958.status[3] = (emu->spdif_bits[idx] >> 24) & 0xff;
1121 return 0;
1122}
1123
4b32f1aa
TI		 1124static int snd_emu10k1x_spdif_get_mask(struct snd_kcontrol *kcontrol,
1125 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1126{
1127 ucontrol->value.iec958.status[0] = 0xff;
1128 ucontrol->value.iec958.status[1] = 0xff;
1129 ucontrol->value.iec958.status[2] = 0xff;
1130 ucontrol->value.iec958.status[3] = 0xff;
1131 return 0;
1132}
1133
4b32f1aa
TI		 1134static int snd_emu10k1x_spdif_put(struct snd_kcontrol *kcontrol,
1135 struct snd_ctl_elem_value *ucontrol)
1da177e4 1136{
4b32f1aa 1137 struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1138 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1139 int change;
1140 unsigned int val;
1141
1142 val = (ucontrol->value.iec958.status[0] << 0) |
1143 (ucontrol->value.iec958.status[1] << 8) |
1144 (ucontrol->value.iec958.status[2] << 16) |
1145 (ucontrol->value.iec958.status[3] << 24);
1146 change = val != emu->spdif_bits[idx];
1147 if (change) {
1148 snd_emu10k1x_ptr_write(emu, SPCS0 + idx, 0, val);
1149 emu->spdif_bits[idx] = val;
1150 }
1151 return change;
1152}
1153
f3b827e0 1154static const struct snd_kcontrol_new snd_emu10k1x_spdif_mask_control =
1da177e4
LT		 1155{
1156 .access = SNDRV_CTL_ELEM_ACCESS_READ,
5549d549 1157 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1158 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1159 .count = 3,
1160 .info = snd_emu10k1x_spdif_info,
1161 .get = snd_emu10k1x_spdif_get_mask
1162};
1163
f3b827e0 1164static const struct snd_kcontrol_new snd_emu10k1x_spdif_control =
1da177e4 1165{
5549d549 1166 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1167 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1168 .count = 3,
1169 .info = snd_emu10k1x_spdif_info,
1170 .get = snd_emu10k1x_spdif_get,
1171 .put = snd_emu10k1x_spdif_put
1172};
1173
e23e7a14 1174static int snd_emu10k1x_mixer(struct emu10k1x *emu)
1da177e4
LT		 1175{
1176 int err;
4b32f1aa
TI		 1177 struct snd_kcontrol *kctl;
1178 struct snd_card *card = emu->card;
1da177e4
LT		 1179
1180 if ((kctl = snd_ctl_new1(&snd_emu10k1x_spdif_mask_control, emu)) == NULL)
1181 return -ENOMEM;
1182 if ((err = snd_ctl_add(card, kctl)))
1183 return err;
1184 if ((kctl = snd_ctl_new1(&snd_emu10k1x_shared_spdif, emu)) == NULL)
1185 return -ENOMEM;
1186 if ((err = snd_ctl_add(card, kctl)))
1187 return err;
1188 if ((kctl = snd_ctl_new1(&snd_emu10k1x_spdif_control, emu)) == NULL)
1189 return -ENOMEM;
1190 if ((err = snd_ctl_add(card, kctl)))
1191 return err;
1192
1193 return 0;
1194}
1195
1196#define EMU10K1X_MIDI_MODE_INPUT (1<<0)
1197#define EMU10K1X_MIDI_MODE_OUTPUT (1<<1)
1198
4b32f1aa 1199static inline unsigned char mpu401_read(struct emu10k1x *emu, struct emu10k1x_midi *mpu, int idx)
1da177e4
LT		 1200{
1201 return (unsigned char)snd_emu10k1x_ptr_read(emu, mpu->port + idx, 0);
1202}
1203
4b32f1aa 1204static inline void mpu401_write(struct emu10k1x *emu, struct emu10k1x_midi *mpu, int data, int idx)
1da177e4
LT		 1205{
1206 snd_emu10k1x_ptr_write(emu, mpu->port + idx, 0, data);
1207}
1208
1209#define mpu401_write_data(emu, mpu, data) mpu401_write(emu, mpu, data, 0)
1210#define mpu401_write_cmd(emu, mpu, data) mpu401_write(emu, mpu, data, 1)
1211#define mpu401_read_data(emu, mpu) mpu401_read(emu, mpu, 0)
1212#define mpu401_read_stat(emu, mpu) mpu401_read(emu, mpu, 1)
1213
1214#define mpu401_input_avail(emu,mpu) (!(mpu401_read_stat(emu,mpu) & 0x80))
1215#define mpu401_output_ready(emu,mpu) (!(mpu401_read_stat(emu,mpu) & 0x40))
1216
1217#define MPU401_RESET 0xff
1218#define MPU401_ENTER_UART 0x3f
1219#define MPU401_ACK 0xfe
1220
4b32f1aa 1221static void mpu401_clear_rx(struct emu10k1x *emu, struct emu10k1x_midi *mpu)
1da177e4
LT		 1222{
1223 int timeout = 100000;
1224 for (; timeout > 0 && mpu401_input_avail(emu, mpu); timeout--)
1225 mpu401_read_data(emu, mpu);
1226#ifdef CONFIG_SND_DEBUG
1227 if (timeout <= 0)
26bc6964
TI		 1228 dev_err(emu->card->dev,
1229 "cmd: clear rx timeout (status = 0x%x)\n",
1230 mpu401_read_stat(emu, mpu));
1da177e4
LT		 1231#endif
1232}
1233
1234/*
1235
1236 */
1237
4b32f1aa
TI		 1238static void do_emu10k1x_midi_interrupt(struct emu10k1x *emu,
1239 struct emu10k1x_midi *midi, unsigned int status)
1da177e4
LT		 1240{
1241 unsigned char byte;
1242
1243 if (midi->rmidi == NULL) {
1244 snd_emu10k1x_intr_disable(emu, midi->tx_enable | midi->rx_enable);
1245 return;
1246 }
1247
1248 spin_lock(&midi->input_lock);
1249 if ((status & midi->ipr_rx) && mpu401_input_avail(emu, midi)) {
1250 if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
1251 mpu401_clear_rx(emu, midi);
1252 } else {
1253 byte = mpu401_read_data(emu, midi);
1254 if (midi->substream_input)
1255 snd_rawmidi_receive(midi->substream_input, &byte, 1);
1256 }
1257 }
1258 spin_unlock(&midi->input_lock);
1259
1260 spin_lock(&midi->output_lock);
1261 if ((status & midi->ipr_tx) && mpu401_output_ready(emu, midi)) {
1262 if (midi->substream_output &&
1263 snd_rawmidi_transmit(midi->substream_output, &byte, 1) == 1) {
1264 mpu401_write_data(emu, midi, byte);
1265 } else {
1266 snd_emu10k1x_intr_disable(emu, midi->tx_enable);
1267 }
1268 }
1269 spin_unlock(&midi->output_lock);
1270}
1271
4b32f1aa 1272static void snd_emu10k1x_midi_interrupt(struct emu10k1x *emu, unsigned int status)
1da177e4
LT		 1273{
1274 do_emu10k1x_midi_interrupt(emu, &emu->midi, status);
1275}
1276
b130807d 1277static int snd_emu10k1x_midi_cmd(struct emu10k1x * emu,
4b32f1aa 1278 struct emu10k1x_midi *midi, unsigned char cmd, int ack)
1da177e4
LT		 1279{
1280 unsigned long flags;
1281 int timeout, ok;
1282
1283 spin_lock_irqsave(&midi->input_lock, flags);
1284 mpu401_write_data(emu, midi, 0x00);
1285 /* mpu401_clear_rx(emu, midi); */
1286
1287 mpu401_write_cmd(emu, midi, cmd);
1288 if (ack) {
1289 ok = 0;
1290 timeout = 10000;
1291 while (!ok && timeout-- > 0) {
1292 if (mpu401_input_avail(emu, midi)) {
1293 if (mpu401_read_data(emu, midi) == MPU401_ACK)
1294 ok = 1;
1295 }
1296 }
1297 if (!ok && mpu401_read_data(emu, midi) == MPU401_ACK)
1298 ok = 1;
1299 } else {
1300 ok = 1;
1301 }
1302 spin_unlock_irqrestore(&midi->input_lock, flags);
b130807d 1303 if (!ok) {
26bc6964
TI		 1304 dev_err(emu->card->dev,
1305 "midi_cmd: 0x%x failed at 0x%lx (status = 0x%x, data = 0x%x)!!!\n",
1da177e4
LT		 1306 cmd, emu->port,
1307 mpu401_read_stat(emu, midi),
1308 mpu401_read_data(emu, midi));
b130807d
RD		 1309 return 1;
1310 }
1311 return 0;
1da177e4
LT		 1312}
1313
4b32f1aa 1314static int snd_emu10k1x_midi_input_open(struct snd_rawmidi_substream *substream)
1da177e4 1315{
4b32f1aa
TI		 1316 struct emu10k1x *emu;
1317 struct emu10k1x_midi *midi = substream->rmidi->private_data;
1da177e4
LT		 1318 unsigned long flags;
1319
1320 emu = midi->emu;
da3cec35
TI		 1321 if (snd_BUG_ON(!emu))
1322 return -ENXIO;
1da177e4
LT		 1323 spin_lock_irqsave(&midi->open_lock, flags);
1324 midi->midi_mode |= EMU10K1X_MIDI_MODE_INPUT;
1325 midi->substream_input = substream;
1326 if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT)) {
1327 spin_unlock_irqrestore(&midi->open_lock, flags);
b130807d
RD		 1328 if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 1))
1329 goto error_out;
1330 if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_ENTER_UART, 1))
1331 goto error_out;
1da177e4
LT		 1332 } else {
1333 spin_unlock_irqrestore(&midi->open_lock, flags);
1334 }
1335 return 0;
b130807d
RD		 1336
1337error_out:
1338 return -EIO;
1da177e4
LT		 1339}
1340
4b32f1aa 1341static int snd_emu10k1x_midi_output_open(struct snd_rawmidi_substream *substream)
1da177e4 1342{
4b32f1aa
TI		 1343 struct emu10k1x *emu;
1344 struct emu10k1x_midi *midi = substream->rmidi->private_data;
1da177e4
LT		 1345 unsigned long flags;
1346
1347 emu = midi->emu;
da3cec35
TI		 1348 if (snd_BUG_ON(!emu))
1349 return -ENXIO;
1da177e4
LT		 1350 spin_lock_irqsave(&midi->open_lock, flags);
1351 midi->midi_mode |= EMU10K1X_MIDI_MODE_OUTPUT;
1352 midi->substream_output = substream;
1353 if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
1354 spin_unlock_irqrestore(&midi->open_lock, flags);
b130807d
RD		 1355 if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 1))
1356 goto error_out;
1357 if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_ENTER_UART, 1))
1358 goto error_out;
1da177e4
LT		 1359 } else {
1360 spin_unlock_irqrestore(&midi->open_lock, flags);
1361 }
1362 return 0;
b130807d
RD		 1363
1364error_out:
1365 return -EIO;
1da177e4
LT		 1366}
1367
4b32f1aa 1368static int snd_emu10k1x_midi_input_close(struct snd_rawmidi_substream *substream)
1da177e4 1369{
4b32f1aa
TI		 1370 struct emu10k1x *emu;
1371 struct emu10k1x_midi *midi = substream->rmidi->private_data;
1da177e4 1372 unsigned long flags;
b130807d 1373 int err = 0;
1da177e4
LT		 1374
1375 emu = midi->emu;
da3cec35
TI		 1376 if (snd_BUG_ON(!emu))
1377 return -ENXIO;
1da177e4
LT		 1378 spin_lock_irqsave(&midi->open_lock, flags);
1379 snd_emu10k1x_intr_disable(emu, midi->rx_enable);
1380 midi->midi_mode &= ~EMU10K1X_MIDI_MODE_INPUT;
1381 midi->substream_input = NULL;
1382 if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT)) {
1383 spin_unlock_irqrestore(&midi->open_lock, flags);
b130807d 1384 err = snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 0);
1da177e4
LT		 1385 } else {
1386 spin_unlock_irqrestore(&midi->open_lock, flags);
1387 }
b130807d 1388 return err;
1da177e4
LT		 1389}
1390
4b32f1aa 1391static int snd_emu10k1x_midi_output_close(struct snd_rawmidi_substream *substream)
1da177e4 1392{
4b32f1aa
TI		 1393 struct emu10k1x *emu;
1394 struct emu10k1x_midi *midi = substream->rmidi->private_data;
1da177e4 1395 unsigned long flags;
b130807d 1396 int err = 0;
1da177e4
LT		 1397
1398 emu = midi->emu;
da3cec35
TI		 1399 if (snd_BUG_ON(!emu))
1400 return -ENXIO;
1da177e4
LT		 1401 spin_lock_irqsave(&midi->open_lock, flags);
1402 snd_emu10k1x_intr_disable(emu, midi->tx_enable);
1403 midi->midi_mode &= ~EMU10K1X_MIDI_MODE_OUTPUT;
1404 midi->substream_output = NULL;
1405 if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
1406 spin_unlock_irqrestore(&midi->open_lock, flags);
b130807d 1407 err = snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 0);
1da177e4
LT		 1408 } else {
1409 spin_unlock_irqrestore(&midi->open_lock, flags);
1410 }
b130807d 1411 return err;
1da177e4
LT		 1412}
1413
4b32f1aa 1414static void snd_emu10k1x_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4 1415{
4b32f1aa
TI		 1416 struct emu10k1x *emu;
1417 struct emu10k1x_midi *midi = substream->rmidi->private_data;
1da177e4 1418 emu = midi->emu;
da3cec35
TI		 1419 if (snd_BUG_ON(!emu))
1420 return;
1da177e4
LT		 1421
1422 if (up)
1423 snd_emu10k1x_intr_enable(emu, midi->rx_enable);
1424 else
1425 snd_emu10k1x_intr_disable(emu, midi->rx_enable);
1426}
1427
4b32f1aa 1428static void snd_emu10k1x_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4 1429{
4b32f1aa
TI		 1430 struct emu10k1x *emu;
1431 struct emu10k1x_midi *midi = substream->rmidi->private_data;
1da177e4
LT		 1432 unsigned long flags;
1433
1434 emu = midi->emu;
da3cec35
TI		 1435 if (snd_BUG_ON(!emu))
1436 return;
1da177e4
LT		 1437
1438 if (up) {
1439 int max = 4;
1440 unsigned char byte;
1441
1442 /* try to send some amount of bytes here before interrupts */
1443 spin_lock_irqsave(&midi->output_lock, flags);
1444 while (max > 0) {
1445 if (mpu401_output_ready(emu, midi)) {
1446 if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT) ||
1447 snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1448 /* no more data */
1449 spin_unlock_irqrestore(&midi->output_lock, flags);
1450 return;
1451 }
1452 mpu401_write_data(emu, midi, byte);
1453 max--;
1454 } else {
1455 break;
1456 }
1457 }
1458 spin_unlock_irqrestore(&midi->output_lock, flags);
1459 snd_emu10k1x_intr_enable(emu, midi->tx_enable);
1460 } else {
1461 snd_emu10k1x_intr_disable(emu, midi->tx_enable);
1462 }
1463}
1464
1465/*
1466
1467 */
1468
485885b9 1469static const struct snd_rawmidi_ops snd_emu10k1x_midi_output =
1da177e4
LT		 1470{
1471 .open = snd_emu10k1x_midi_output_open,
1472 .close = snd_emu10k1x_midi_output_close,
1473 .trigger = snd_emu10k1x_midi_output_trigger,
1474};
1475
485885b9 1476static const struct snd_rawmidi_ops snd_emu10k1x_midi_input =
1da177e4
LT		 1477{
1478 .open = snd_emu10k1x_midi_input_open,
1479 .close = snd_emu10k1x_midi_input_close,
1480 .trigger = snd_emu10k1x_midi_input_trigger,
1481};
1482
4b32f1aa 1483static void snd_emu10k1x_midi_free(struct snd_rawmidi *rmidi)
1da177e4 1484{
4b32f1aa 1485 struct emu10k1x_midi *midi = rmidi->private_data;
1da177e4
LT		 1486 midi->interrupt = NULL;
1487 midi->rmidi = NULL;
1488}
1489
e23e7a14
BP		 1490static int emu10k1x_midi_init(struct emu10k1x *emu,
1491 struct emu10k1x_midi *midi, int device,
1492 char *name)
1da177e4 1493{
4b32f1aa 1494 struct snd_rawmidi *rmidi;
1da177e4
LT		 1495 int err;
1496
1497 if ((err = snd_rawmidi_new(emu->card, name, device, 1, 1, &rmidi)) < 0)
1498 return err;
1499 midi->emu = emu;
1500 spin_lock_init(&midi->open_lock);
1501 spin_lock_init(&midi->input_lock);
1502 spin_lock_init(&midi->output_lock);
1503 strcpy(rmidi->name, name);
1504 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_emu10k1x_midi_output);
1505 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_emu10k1x_midi_input);
1506 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1507 SNDRV_RAWMIDI_INFO_INPUT |
1508 SNDRV_RAWMIDI_INFO_DUPLEX;
1509 rmidi->private_data = midi;
1510 rmidi->private_free = snd_emu10k1x_midi_free;
1511 midi->rmidi = rmidi;
1512 return 0;
1513}
1514
e23e7a14 1515static int snd_emu10k1x_midi(struct emu10k1x *emu)
1da177e4 1516{
4b32f1aa 1517 struct emu10k1x_midi *midi = &emu->midi;
1da177e4
LT		 1518 int err;
1519
1520 if ((err = emu10k1x_midi_init(emu, midi, 0, "EMU10K1X MPU-401 (UART)")) < 0)
1521 return err;
1522
1523 midi->tx_enable = INTE_MIDITXENABLE;
1524 midi->rx_enable = INTE_MIDIRXENABLE;
1525 midi->port = MUDATA;
1526 midi->ipr_tx = IPR_MIDITRANSBUFEMPTY;
1527 midi->ipr_rx = IPR_MIDIRECVBUFEMPTY;
1528 midi->interrupt = snd_emu10k1x_midi_interrupt;
1529 return 0;
1530}
1531
e23e7a14
BP		 1532static int snd_emu10k1x_probe(struct pci_dev *pci,
1533 const struct pci_device_id *pci_id)
1da177e4
LT		 1534{
1535 static int dev;
4b32f1aa
TI		 1536 struct snd_card *card;
1537 struct emu10k1x *chip;
1da177e4
LT		 1538 int err;
1539
1540 if (dev >= SNDRV_CARDS)
1541 return -ENODEV;
1542 if (!enable[dev]) {
1543 dev++;
1544 return -ENOENT;
1545 }
1546
60c5772b
TI		 1547 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1548 0, &card);
e58de7ba
TI		 1549 if (err < 0)
1550 return err;
1da177e4
LT		 1551
1552 if ((err = snd_emu10k1x_create(card, pci, &chip)) < 0) {
1553 snd_card_free(card);
1554 return err;
1555 }
1556
bb814c39 1557 if ((err = snd_emu10k1x_pcm(chip, 0)) < 0) {
1da177e4
LT		 1558 snd_card_free(card);
1559 return err;
1560 }
bb814c39 1561 if ((err = snd_emu10k1x_pcm(chip, 1)) < 0) {
1da177e4
LT		 1562 snd_card_free(card);
1563 return err;
1564 }
bb814c39 1565 if ((err = snd_emu10k1x_pcm(chip, 2)) < 0) {
1da177e4
LT		 1566 snd_card_free(card);
1567 return err;
1568 }
1569
1570 if ((err = snd_emu10k1x_ac97(chip)) < 0) {
1571 snd_card_free(card);
1572 return err;
1573 }
1574
1575 if ((err = snd_emu10k1x_mixer(chip)) < 0) {
1576 snd_card_free(card);
1577 return err;
1578 }
1579
1580 if ((err = snd_emu10k1x_midi(chip)) < 0) {
1581 snd_card_free(card);
1582 return err;
1583 }
1584
1585 snd_emu10k1x_proc_init(chip);
1586
1587 strcpy(card->driver, "EMU10K1X");
1588 strcpy(card->shortname, "Dell Sound Blaster Live!");
1589 sprintf(card->longname, "%s at 0x%lx irq %i",
1590 card->shortname, chip->port, chip->irq);
1591
1592 if ((err = snd_card_register(card)) < 0) {
1593 snd_card_free(card);
1594 return err;
1595 }
1596
1597 pci_set_drvdata(pci, card);
1598 dev++;
1599 return 0;
1600}
1601
e23e7a14 1602static void snd_emu10k1x_remove(struct pci_dev *pci)
1da177e4
LT		 1603{
1604 snd_card_free(pci_get_drvdata(pci));
1da177e4
LT		 1605}
1606
1607// PCI IDs
9baa3c34 1608static const struct pci_device_id snd_emu10k1x_ids[] = {
0d7392e5 1609 { PCI_VDEVICE(CREATIVE, 0x0006), 0 }, /* Dell OEM version (EMU10K1) */
1da177e4
LT		 1610 { 0, }
1611};
1612MODULE_DEVICE_TABLE(pci, snd_emu10k1x_ids);
1613
1614// pci_driver definition
e9f66d9b 1615static struct pci_driver emu10k1x_driver = {
3733e424 1616 .name = KBUILD_MODNAME,
1da177e4
LT		 1617 .id_table = snd_emu10k1x_ids,
1618 .probe = snd_emu10k1x_probe,
e23e7a14 1619 .remove = snd_emu10k1x_remove,
1da177e4
LT		 1620};
1621
e9f66d9b 1622module_pci_driver(emu10k1x_driver);
Linux 6.x block layer and io_uring tree(s)