projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[ALSA] Add description of imac-intel model
[linux-2.6-block.git] / sound / pci / emu10k1 / emu10k1_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
3 * Creative Labs, Inc.
4 * Routines for control of EMU10K1 chips
5 *
9f4bd5dd 6 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
1da177e4 7 * Added support for Audigy 2 Value.
9f4bd5dd
JCD		 8 * Added EMU 1010 support.
9 * General bug fixes and enhancements.
1da177e4
LT		 10 *
11 *
12 * BUGS:
13 * --
14 *
15 * TODO:
16 * --
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 */
33
34#include <sound/driver.h>
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/slab.h>
40#include <linux/vmalloc.h>
62932df8
IM		 41#include <linux/mutex.h>
42
1da177e4
LT		 43
44#include <sound/core.h>
45#include <sound/emu10k1.h>
9f4bd5dd 46#include <linux/firmware.h>
1da177e4 47#include "p16v.h"
e2b15f8f 48#include "tina2.h"
184c1e2c 49#include "p17v.h"
1da177e4 50
19b99fba 51
1da177e4
LT		 52/*************************************************************************
53 * EMU10K1 init / done
54 *************************************************************************/
55
eb4698f3 56void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int ch)
1da177e4
LT		 57{
58 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
59 snd_emu10k1_ptr_write(emu, IP, ch, 0);
60 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
61 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
62 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
63 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
64 snd_emu10k1_ptr_write(emu, CCR, ch, 0);
65
66 snd_emu10k1_ptr_write(emu, PSST, ch, 0);
67 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
68 snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
69 snd_emu10k1_ptr_write(emu, Z1, ch, 0);
70 snd_emu10k1_ptr_write(emu, Z2, ch, 0);
71 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
72
73 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
74 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
75 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
76 snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
77 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
78 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
79 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
80 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
81
82 /*** these are last so OFF prevents writing ***/
83 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
84 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
85 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
86 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
87 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
88
89 /* Audigy extra stuffs */
90 if (emu->audigy) {
91 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
92 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
93 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
94 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
95 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
96 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
97 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
98 }
99}
100
18f3c59f
JCD		 101static unsigned int spi_dac_init[] = {
102 0x00ff,
103 0x02ff,
104 0x0400,
105 0x0520,
106 0x0600,
107 0x08ff,
108 0x0aff,
109 0x0cff,
110 0x0eff,
111 0x10ff,
112 0x1200,
113 0x1400,
114 0x1480,
115 0x1800,
116 0x1aff,
117 0x1cff,
118 0x1e00,
119 0x0530,
120 0x0602,
121 0x0622,
122 0x1400,
123};
184c1e2c
JCD		 124
125static unsigned int i2c_adc_init[][2] = {
126 { 0x17, 0x00 }, /* Reset */
127 { 0x07, 0x00 }, /* Timeout */
128 { 0x0b, 0x22 }, /* Interface control */
129 { 0x0c, 0x22 }, /* Master mode control */
130 { 0x0d, 0x08 }, /* Powerdown control */
131 { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */
132 { 0x0f, 0xcf }, /* Attenuation Right 0.5dB steps */
133 { 0x10, 0x7b }, /* ALC Control 1 */
134 { 0x11, 0x00 }, /* ALC Control 2 */
135 { 0x12, 0x32 }, /* ALC Control 3 */
136 { 0x13, 0x00 }, /* Noise gate control */
137 { 0x14, 0xa6 }, /* Limiter control */
138 { 0x15, ADC_MUX_2 }, /* ADC Mixer control. Mic for Audigy 2 ZS Notebook */
139};
18f3c59f 140
09668b44 141static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
1da177e4 142{
1da177e4 143 unsigned int silent_page;
09668b44 144 int ch;
184c1e2c 145 u32 tmp;
1da177e4
LT		 146
147 /* disable audio and lock cache */
09668b44
TI		 148 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
149 emu->port + HCFG);
1da177e4
LT		 150
151 /* reset recording buffers */
152 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
153 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
154 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
155 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
156 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
157 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
158
159 /* disable channel interrupt */
160 outl(0, emu->port + INTE);
161 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
162 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
163 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
164 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
165
166 if (emu->audigy){
167 /* set SPDIF bypass mode */
168 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
169 /* enable rear left + rear right AC97 slots */
09668b44
TI		 170 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT |
171 AC97SLOT_REAR_LEFT);
1da177e4
LT		 172 }
173
174 /* init envelope engine */
09668b44 175 for (ch = 0; ch < NUM_G; ch++)
1da177e4 176 snd_emu10k1_voice_init(emu, ch);
1da177e4 177
09668b44
TI		 178 snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]);
179 snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]);
180 snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]);
1da177e4 181
2b637da5 182 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
1da177e4 183 /* Hacks for Alice3 to work independent of haP16V driver */
1da177e4
LT		 184 //Setup SRCMulti_I2S SamplingRate
185 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
186 tmp &= 0xfffff1ff;
187 tmp |= (0x2<<9);
188 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
189
190 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
191 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14);
192 /* Setup SRCMulti Input Audio Enable */
193 /* Use 0xFFFFFFFF to enable P16V sounds. */
194 snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF);
195
196 /* Enabled Phased (8-channel) P16V playback */
197 outl(0x0201, emu->port + HCFG2);
198 /* Set playback routing. */
fd9a98ec 199 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4);
1da177e4 200 }
e0474e53 201 if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */
1da177e4 202 /* Hacks for Alice3 to work independent of haP16V driver */
09668b44 203 snd_printk(KERN_INFO "Audigy2 value: Special config.\n");
1da177e4
LT		 204 //Setup SRCMulti_I2S SamplingRate
205 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
206 tmp &= 0xfffff1ff;
207 tmp |= (0x2<<9);
208 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
209
210 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
211 outl(0x600000, emu->port + 0x20);
212 outl(0x14, emu->port + 0x24);
213
214 /* Setup SRCMulti Input Audio Enable */
215 outl(0x7b0000, emu->port + 0x20);
216 outl(0xFF000000, emu->port + 0x24);
217
218 /* Setup SPDIF Out Audio Enable */
219 /* The Audigy 2 Value has a separate SPDIF out,
220 * so no need for a mixer switch
221 */
222 outl(0x7a0000, emu->port + 0x20);
223 outl(0xFF000000, emu->port + 0x24);
224 tmp = inl(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
225 outl(tmp, emu->port + A_IOCFG);
226 }
27fe864e 227 if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */
18f3c59f
JCD		 228 int size, n;
229
230 size = ARRAY_SIZE(spi_dac_init);
9f4bd5dd 231 for (n = 0; n < size; n++)
18f3c59f
JCD		 232 snd_emu10k1_spi_write(emu, spi_dac_init[n]);
233
27fe864e 234 snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10);
ccadc3e3
JCD		 235 /* Enable GPIOs
236 * GPIO0: Unknown
237 * GPIO1: Speakers-enabled.
238 * GPIO2: Unknown
239 * GPIO3: Unknown
240 * GPIO4: IEC958 Output on.
241 * GPIO5: Unknown
242 * GPIO6: Unknown
243 * GPIO7: Unknown
244 */
245 outl(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */
246
27fe864e 247 }
184c1e2c
JCD		 248 if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */
249 int size, n;
250
251 snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f);
252 tmp = inl(emu->port + A_IOCFG);
253 outl(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */
254 tmp = inl(emu->port + A_IOCFG);
255 size = ARRAY_SIZE(i2c_adc_init);
256 for (n = 0; n < size; n++)
257 snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]);
258 for (n=0; n < 4; n++) {
259 emu->i2c_capture_volume[n][0]= 0xcf;
260 emu->i2c_capture_volume[n][1]= 0xcf;
261 }
262
263 }
264
27fe864e 265
1da177e4
LT		 266 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
267 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
268 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
269
270 silent_page = (emu->silent_page.addr << 1) | MAP_PTI_MASK;
271 for (ch = 0; ch < NUM_G; ch++) {
272 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
273 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
274 }
275
9f4bd5dd
JCD		 276 if (emu->card_capabilities->emu1010) {
277 outl(HCFG_AUTOMUTE_ASYNC |
278 HCFG_EMU32_SLAVE |
279 HCFG_AUDIOENABLE, emu->port + HCFG);
1da177e4
LT		 280 /*
281 * Hokay, setup HCFG
282 * Mute Disable Audio = 0
283 * Lock Tank Memory = 1
284 * Lock Sound Memory = 0
285 * Auto Mute = 1
286 */
9f4bd5dd 287 } else if (emu->audigy) {
1da177e4
LT		 288 if (emu->revision == 4) /* audigy2 */
289 outl(HCFG_AUDIOENABLE |
290 HCFG_AC3ENABLE_CDSPDIF |
291 HCFG_AC3ENABLE_GPSPDIF |
292 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
293 else
294 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
e0474e53
JCD		 295 /* FIXME: Remove all these emu->model and replace it with a card recognition parameter,
296 * e.g. card_capabilities->joystick */
1da177e4
LT		 297 } else if (emu->model == 0x20 ||
298 emu->model == 0xc400 ||
299 (emu->model == 0x21 && emu->revision < 6))
300 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
301 else
302 // With on-chip joystick
303 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
304
305 if (enable_ir) { /* enable IR for SB Live */
9f4bd5dd
JCD		 306 if (emu->card_capabilities->emu1010) {
307 ; /* Disable all access to A_IOCFG for the emu1010 */
184c1e2c
JCD		 308 } else if (emu->card_capabilities->i2c_adc) {
309 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
19b99fba 310 } else if (emu->audigy) {
1da177e4
LT		 311 unsigned int reg = inl(emu->port + A_IOCFG);
312 outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
313 udelay(500);
314 outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
315 udelay(100);
316 outl(reg, emu->port + A_IOCFG);
317 } else {
318 unsigned int reg = inl(emu->port + HCFG);
319 outl(reg | HCFG_GPOUT2, emu->port + HCFG);
320 udelay(500);
321 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
322 udelay(100);
323 outl(reg, emu->port + HCFG);
324 }
325 }
326
9f4bd5dd
JCD		 327 if (emu->card_capabilities->emu1010) {
328 ; /* Disable all access to A_IOCFG for the emu1010 */
184c1e2c
JCD		 329 } else if (emu->card_capabilities->i2c_adc) {
330 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
19b99fba 331 } else if (emu->audigy) { /* enable analog output */
1da177e4
LT		 332 unsigned int reg = inl(emu->port + A_IOCFG);
333 outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
334 }
335
09668b44
TI		 336 return 0;
337}
1da177e4 338
09668b44
TI		 339static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu)
340{
1da177e4
LT		 341 /*
342 * Enable the audio bit
343 */
344 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
345
346 /* Enable analog/digital outs on audigy */
9f4bd5dd
JCD		 347 if (emu->card_capabilities->emu1010) {
348 ; /* Disable all access to A_IOCFG for the emu1010 */
184c1e2c
JCD		 349 } else if (emu->card_capabilities->i2c_adc) {
350 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
19b99fba 351 } else if (emu->audigy) {
1da177e4
LT		 352 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
353
e0474e53 354 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
1da177e4
LT		 355 /* Unmute Analog now. Set GPO6 to 1 for Apollo.
356 * This has to be done after init ALice3 I2SOut beyond 48KHz.
357 * So, sequence is important. */
358 outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
e0474e53 359 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */
1da177e4
LT		 360 /* Unmute Analog now. */
361 outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
362 } else {
363 /* Disable routing from AC97 line out to Front speakers */
364 outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
365 }
366 }
367
368#if 0
369 {
370 unsigned int tmp;
371 /* FIXME: the following routine disables LiveDrive-II !! */
372 // TOSLink detection
373 emu->tos_link = 0;
374 tmp = inl(emu->port + HCFG);
375 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
376 outl(tmp|0x800, emu->port + HCFG);
377 udelay(50);
378 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
379 emu->tos_link = 1;
380 outl(tmp, emu->port + HCFG);
381 }
382 }
383 }
384#endif
385
386 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
1da177e4
LT		 387}
388
09668b44 389int snd_emu10k1_done(struct snd_emu10k1 * emu)
1da177e4
LT		 390{
391 int ch;
392
393 outl(0, emu->port + INTE);
394
395 /*
396 * Shutdown the chip
397 */
398 for (ch = 0; ch < NUM_G; ch++)
399 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
400 for (ch = 0; ch < NUM_G; ch++) {
401 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
402 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
403 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
404 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
405 }
406
407 /* reset recording buffers */
408 snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
409 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
410 snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
411 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
412 snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
413 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
414 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
415 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
416 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
417 if (emu->audigy)
418 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
419 else
420 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
421
422 /* disable channel interrupt */
423 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
424 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
425 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
426 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
427
1da177e4
LT		 428 /* disable audio and lock cache */
429 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
430 snd_emu10k1_ptr_write(emu, PTB, 0, 0);
431
1da177e4
LT		 432 return 0;
433}
434
435/*************************************************************************
436 * ECARD functional implementation
437 *************************************************************************/
438
439/* In A1 Silicon, these bits are in the HC register */
440#define HOOKN_BIT (1L << 12)
441#define HANDN_BIT (1L << 11)
442#define PULSEN_BIT (1L << 10)
443
444#define EC_GDI1 (1 << 13)
445#define EC_GDI0 (1 << 14)
446
447#define EC_NUM_CONTROL_BITS 20
448
449#define EC_AC3_DATA_SELN 0x0001L
450#define EC_EE_DATA_SEL 0x0002L
451#define EC_EE_CNTRL_SELN 0x0004L
452#define EC_EECLK 0x0008L
453#define EC_EECS 0x0010L
454#define EC_EESDO 0x0020L
455#define EC_TRIM_CSN 0x0040L
456#define EC_TRIM_SCLK 0x0080L
457#define EC_TRIM_SDATA 0x0100L
458#define EC_TRIM_MUTEN 0x0200L
459#define EC_ADCCAL 0x0400L
460#define EC_ADCRSTN 0x0800L
461#define EC_DACCAL 0x1000L
462#define EC_DACMUTEN 0x2000L
463#define EC_LEDN 0x4000L
464
465#define EC_SPDIF0_SEL_SHIFT 15
466#define EC_SPDIF1_SEL_SHIFT 17
467#define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
468#define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
469#define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
470#define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
471#define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
472 * be incremented any time the EEPROM's
473 * format is changed. */
474
475#define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
476
477/* Addresses for special values stored in to EEPROM */
478#define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
479#define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
480#define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
481
482#define EC_LAST_PROMFILE_ADDR 0x2f
483
484#define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
485 * can be up to 30 characters in length
486 * and is stored as a NULL-terminated
487 * ASCII string. Any unused bytes must be
488 * filled with zeros */
489#define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
490
491
492/* Most of this stuff is pretty self-evident. According to the hardware
493 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
494 * offset problem. Weird.
495 */
496#define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
497 EC_TRIM_CSN)
498
499
500#define EC_DEFAULT_ADC_GAIN 0xC4C4
501#define EC_DEFAULT_SPDIF0_SEL 0x0
502#define EC_DEFAULT_SPDIF1_SEL 0x4
503
504/**************************************************************************
505 * @func Clock bits into the Ecard's control latch. The Ecard uses a
506 * control latch will is loaded bit-serially by toggling the Modem control
507 * lines from function 2 on the E8010. This function hides these details
508 * and presents the illusion that we are actually writing to a distinct
509 * register.
510 */
511
eb4698f3 512static void snd_emu10k1_ecard_write(struct snd_emu10k1 * emu, unsigned int value)
1da177e4
LT		 513{
514 unsigned short count;
515 unsigned int data;
516 unsigned long hc_port;
517 unsigned int hc_value;
518
519 hc_port = emu->port + HCFG;
520 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
521 outl(hc_value, hc_port);
522
523 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
524
525 /* Set up the value */
526 data = ((value & 0x1) ? PULSEN_BIT : 0);
527 value >>= 1;
528
529 outl(hc_value | data, hc_port);
530
531 /* Clock the shift register */
532 outl(hc_value | data | HANDN_BIT, hc_port);
533 outl(hc_value | data, hc_port);
534 }
535
536 /* Latch the bits */
537 outl(hc_value | HOOKN_BIT, hc_port);
538 outl(hc_value, hc_port);
539}
540
541/**************************************************************************
542 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
543 * trim value consists of a 16bit value which is composed of two
544 * 8 bit gain/trim values, one for the left channel and one for the
545 * right channel. The following table maps from the Gain/Attenuation
546 * value in decibels into the corresponding bit pattern for a single
547 * channel.
548 */
549
eb4698f3 550static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 * emu,
1da177e4
LT		 551 unsigned short gain)
552{
553 unsigned int bit;
554
555 /* Enable writing to the TRIM registers */
556 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
557
558 /* Do it again to insure that we meet hold time requirements */
559 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
560
561 for (bit = (1 << 15); bit; bit >>= 1) {
562 unsigned int value;
563
564 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
565
566 if (gain & bit)
567 value |= EC_TRIM_SDATA;
568
569 /* Clock the bit */
570 snd_emu10k1_ecard_write(emu, value);
571 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
572 snd_emu10k1_ecard_write(emu, value);
573 }
574
575 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
576}
577
f40b6890 578static int snd_emu10k1_ecard_init(struct snd_emu10k1 * emu)
1da177e4
LT		 579{
580 unsigned int hc_value;
581
582 /* Set up the initial settings */
583 emu->ecard_ctrl = EC_RAW_RUN_MODE |
584 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
585 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
586
587 /* Step 0: Set the codec type in the hardware control register
588 * and enable audio output */
589 hc_value = inl(emu->port + HCFG);
590 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
591 inl(emu->port + HCFG);
592
593 /* Step 1: Turn off the led and deassert TRIM_CS */
594 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
595
596 /* Step 2: Calibrate the ADC and DAC */
597 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
598
599 /* Step 3: Wait for awhile; XXX We can't get away with this
600 * under a real operating system; we'll need to block and wait that
601 * way. */
602 snd_emu10k1_wait(emu, 48000);
603
604 /* Step 4: Switch off the DAC and ADC calibration. Note
605 * That ADC_CAL is actually an inverted signal, so we assert
606 * it here to stop calibration. */
607 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
608
609 /* Step 4: Switch into run mode */
610 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
611
612 /* Step 5: Set the analog input gain */
613 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
614
615 return 0;
616}
617
f40b6890 618static int snd_emu10k1_cardbus_init(struct snd_emu10k1 * emu)
d83c671f
JCD		 619{
620 unsigned long special_port;
621 unsigned int value;
622
623 /* Special initialisation routine
624 * before the rest of the IO-Ports become active.
625 */
626 special_port = emu->port + 0x38;
627 value = inl(special_port);
628 outl(0x00d00000, special_port);
629 value = inl(special_port);
630 outl(0x00d00001, special_port);
631 value = inl(special_port);
632 outl(0x00d0005f, special_port);
633 value = inl(special_port);
634 outl(0x00d0007f, special_port);
635 value = inl(special_port);
636 outl(0x0090007f, special_port);
637 value = inl(special_port);
638
e2b15f8f 639 snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */
d83c671f
JCD		 640 return 0;
641}
642
9f4bd5dd 643static int snd_emu1010_load_firmware(struct snd_emu10k1 * emu, const char * filename)
19b99fba 644{
9f4bd5dd
JCD		 645 int err;
646 int n, i;
647 int reg;
648 int value;
649 const struct firmware *fw_entry;
650
651 if ((err = request_firmware(&fw_entry, filename, &emu->pci->dev)) != 0) {
652 snd_printk(KERN_ERR "firmware: %s not found. Err=%d\n",filename, err);
653 return err;
654 }
bbb53551 655 snd_printk(KERN_INFO "firmware size=0x%zx\n", fw_entry->size);
9f4bd5dd
JCD		 656 if (fw_entry->size != 0x133a4) {
657 snd_printk(KERN_ERR "firmware: %s wrong size.\n",filename);
658 return -EINVAL;
659 }
19b99fba 660
9f4bd5dd
JCD		 661 /* The FPGA is a Xilinx Spartan IIE XC2S50E */
662 /* GPIO7 -> FPGA PGMN
663 * GPIO6 -> FPGA CCLK
664 * GPIO5 -> FPGA DIN
665 * FPGA CONFIG OFF -> FPGA PGMN
666 */
667 outl(0x00, emu->port + A_IOCFG); /* Set PGMN low for 1uS. */
668 udelay(1);
669 outl(0x80, emu->port + A_IOCFG); /* Leave bit 7 set during netlist setup. */
670 udelay(100); /* Allow FPGA memory to clean */
671 for(n = 0; n < fw_entry->size; n++) {
672 value=fw_entry->data[n];
673 for(i = 0; i < 8; i++) {
674 reg = 0x80;
675 if (value & 0x1)
676 reg = reg | 0x20;
677 value = value >> 1;
678 outl(reg, emu->port + A_IOCFG);
679 outl(reg | 0x40, emu->port + A_IOCFG);
680 }
681 }
682 /* After programming, set GPIO bit 4 high again. */
683 outl(0x10, emu->port + A_IOCFG);
684
19b99fba 685
9f4bd5dd 686 release_firmware(fw_entry);
19b99fba
JCD		 687 return 0;
688}
689
9f4bd5dd 690static int snd_emu10k1_emu1010_init(struct snd_emu10k1 * emu)
19b99fba
JCD		 691{
692 unsigned int i;
9f4bd5dd
JCD		 693 int tmp,tmp2;
694 int reg;
695 int err;
696 const char *hana_filename = "emu/hana.fw";
697 const char *dock_filename = "emu/audio_dock.fw";
698
699 snd_printk(KERN_INFO "emu1010: Special config.\n");
700 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
701 * Lock Sound Memory Cache, Lock Tank Memory Cache,
702 * Mute all codecs.
703 */
19b99fba 704 outl(0x0005a00c, emu->port + HCFG);
9f4bd5dd
JCD		 705 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
706 * Lock Tank Memory Cache,
707 * Mute all codecs.
708 */
709 outl(0x0005a004, emu->port + HCFG);
710 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
711 * Mute all codecs.
712 */
19b99fba 713 outl(0x0005a000, emu->port + HCFG);
9f4bd5dd
JCD		 714 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
715 * Mute all codecs.
716 */
19b99fba
JCD		 717 outl(0x0005a000, emu->port + HCFG);
718
9f4bd5dd
JCD		 719 /* Disable 48Volt power to Audio Dock */
720 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0 );
721
722 /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */
723 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg );
724 snd_printdd("reg1=0x%x\n",reg);
725 if (reg == 0x55) {
726 /* FPGA netlist already present so clear it */
727 /* Return to programming mode */
728
729 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02 );
19b99fba 730 }
9f4bd5dd
JCD		 731 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg );
732 snd_printdd("reg2=0x%x\n",reg);
733 if (reg == 0x55) {
734 /* FPGA failed to return to programming mode */
735 return -ENODEV;
19b99fba 736 }
9f4bd5dd
JCD		 737 snd_printk(KERN_INFO "emu1010: EMU_HANA_ID=0x%x\n",reg);
738 if ((err = snd_emu1010_load_firmware(emu, hana_filename)) != 0) {
739 snd_printk(KERN_INFO "emu1010: Loading Hana Firmware file %s failed\n", hana_filename);
740 return err;
19b99fba 741 }
9f4bd5dd
JCD		 742
743 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
744 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg );
745 if (reg != 0x55) {
746 /* FPGA failed to be programmed */
747 snd_printk(KERN_INFO "emu1010: Loading Hana Firmware file failed, reg=0x%x\n", reg);
748 return -ENODEV;
19b99fba 749 }
19b99fba 750
9f4bd5dd
JCD		 751 snd_printk(KERN_INFO "emu1010: Hana Firmware loaded\n");
752 snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp );
753 snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2 );
754 snd_printk("Hana ver:%d.%d\n",tmp ,tmp2);
755 /* Enable 48Volt power to Audio Dock */
756 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON );
757
758 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg );
759 snd_printk(KERN_INFO "emu1010: Card options=0x%x\n",reg);
760 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg );
761 snd_printk(KERN_INFO "emu1010: Card options=0x%x\n",reg);
762 snd_emu1010_fpga_read(emu, EMU_HANA_OPTICAL_TYPE, &tmp );
763 /* ADAT input. */
764 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x01 );
9148cc50 765 snd_emu1010_fpga_read(emu, EMU_HANA_ADC_PADS, &tmp );
9f4bd5dd 766 /* Set no attenuation on Audio Dock pads. */
9148cc50
JCD		 767 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00 );
768 emu->emu1010.adc_pads = 0x00;
9f4bd5dd
JCD		 769 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp );
770 /* Unmute Audio dock DACs, Headphone source DAC-4. */
771 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30 );
772 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12 );
9148cc50
JCD		 773 snd_emu1010_fpga_read(emu, EMU_HANA_DAC_PADS, &tmp );
774 /* DAC PADs. */
775 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f );
776 emu->emu1010.dac_pads = 0x0f;
9f4bd5dd
JCD		 777 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp );
778 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30 );
779 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp );
780 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */
781 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10 );
782 /* MIDI routing */
9148cc50 783 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19 );
9f4bd5dd 784 /* Unknown. */
9148cc50 785 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c );
9f4bd5dd
JCD		 786 /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); // IRQ Enable: All on */
787 /* IRQ Enable: All off */
788 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00 );
789
790 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg );
791 snd_printk(KERN_INFO "emu1010: Card options3=0x%x\n",reg);
792 /* Default WCLK set to 48kHz. */
793 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00 );
794 /* Word Clock source, Internal 48kHz x1 */
795 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K );
796 //snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X );
797 /* Audio Dock LEDs. */
798 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12 );
19b99fba 799
9f4bd5dd
JCD		 800#if 0
801 /* For 96kHz */
802 snd_emu1010_fpga_link_dst_src_write(emu,
803 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
804 snd_emu1010_fpga_link_dst_src_write(emu,
805 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
806 snd_emu1010_fpga_link_dst_src_write(emu,
807 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2);
808 snd_emu1010_fpga_link_dst_src_write(emu,
809 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2);
810#endif
811#if 0
812 /* For 192kHz */
813 snd_emu1010_fpga_link_dst_src_write(emu,
814 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
815 snd_emu1010_fpga_link_dst_src_write(emu,
816 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
817 snd_emu1010_fpga_link_dst_src_write(emu,
818 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
819 snd_emu1010_fpga_link_dst_src_write(emu,
820 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2);
821 snd_emu1010_fpga_link_dst_src_write(emu,
822 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3);
823 snd_emu1010_fpga_link_dst_src_write(emu,
824 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3);
825 snd_emu1010_fpga_link_dst_src_write(emu,
826 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4);
827 snd_emu1010_fpga_link_dst_src_write(emu,
828 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4);
829#endif
830#if 1
831 /* For 48kHz */
832 snd_emu1010_fpga_link_dst_src_write(emu,
833 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1);
834 snd_emu1010_fpga_link_dst_src_write(emu,
835 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1);
836 snd_emu1010_fpga_link_dst_src_write(emu,
837 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
838 snd_emu1010_fpga_link_dst_src_write(emu,
839 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2);
840 snd_emu1010_fpga_link_dst_src_write(emu,
841 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1);
842 snd_emu1010_fpga_link_dst_src_write(emu,
843 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1);
844 snd_emu1010_fpga_link_dst_src_write(emu,
845 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1);
846 snd_emu1010_fpga_link_dst_src_write(emu,
847 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1);
848#endif
849#if 0
850 /* Original */
851 snd_emu1010_fpga_link_dst_src_write(emu,
852 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT);
853 snd_emu1010_fpga_link_dst_src_write(emu,
854 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1);
855 snd_emu1010_fpga_link_dst_src_write(emu,
856 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2);
857 snd_emu1010_fpga_link_dst_src_write(emu,
858 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3);
859 snd_emu1010_fpga_link_dst_src_write(emu,
860 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4);
861 snd_emu1010_fpga_link_dst_src_write(emu,
862 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5);
863 snd_emu1010_fpga_link_dst_src_write(emu,
864 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6);
865 snd_emu1010_fpga_link_dst_src_write(emu,
866 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7);
867 snd_emu1010_fpga_link_dst_src_write(emu,
868 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1);
869 snd_emu1010_fpga_link_dst_src_write(emu,
870 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1);
871 snd_emu1010_fpga_link_dst_src_write(emu,
872 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2);
873 snd_emu1010_fpga_link_dst_src_write(emu,
874 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2);
875#endif
876 for (i = 0;i < 0x20; i++ ) {
877 /* AudioDock Elink <- Silence */
878 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100+i, EMU_SRC_SILENCE);
879 }
880 for (i = 0;i < 4; i++) {
881 /* Hana SPDIF Out <- Silence */
882 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200+i, EMU_SRC_SILENCE);
883 }
884 for (i = 0;i < 7; i++) {
885 /* Hamoa DAC <- Silence */
886 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300+i, EMU_SRC_SILENCE);
887 }
888 for (i = 0;i < 7; i++) {
889 /* Hana ADAT Out <- Silence */
890 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE);
891 }
892 snd_emu1010_fpga_link_dst_src_write(emu,
893 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1);
894 snd_emu1010_fpga_link_dst_src_write(emu,
895 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1);
896 snd_emu1010_fpga_link_dst_src_write(emu,
897 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1);
898 snd_emu1010_fpga_link_dst_src_write(emu,
899 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1);
900 snd_emu1010_fpga_link_dst_src_write(emu,
901 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1);
902 snd_emu1010_fpga_link_dst_src_write(emu,
903 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1);
904 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01 ); // Unmute all
905
906 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp );
907
908 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
909 * Lock Sound Memory Cache, Lock Tank Memory Cache,
910 * Mute all codecs.
911 */
912 outl(0x0000a000, emu->port + HCFG);
913 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
914 * Lock Sound Memory Cache, Lock Tank Memory Cache,
915 * Un-Mute all codecs.
916 */
19b99fba 917 outl(0x0000a001, emu->port + HCFG);
9f4bd5dd 918
19b99fba
JCD		 919 /* Initial boot complete. Now patches */
920
9f4bd5dd 921 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp );
9148cc50
JCD		 922 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19 ); /* MIDI Route */
923 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c ); /* Unknown */
924 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19 ); /* MIDI Route */
925 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c ); /* Unknown */
9f4bd5dd
JCD		 926 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp );
927 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10 ); /* SPDIF Format spdif (or 0x11 for aes/ebu) */
928
929 /* Delay to allow Audio Dock to settle */
930 msleep(100);
931 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp ); /* IRQ Status */
932 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg ); /* OPTIONS: Which cards are attached to the EMU */
933 /* FIXME: The loading of this should be able to happen any time,
934 * as the user can plug/unplug it at any time
935 */
936 if (reg & (EMU_HANA_OPTION_DOCK_ONLINE | EMU_HANA_OPTION_DOCK_OFFLINE) ) {
937 /* Audio Dock attached */
938 /* Return to Audio Dock programming mode */
939 snd_printk(KERN_INFO "emu1010: Loading Audio Dock Firmware\n");
940 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, EMU_HANA_FPGA_CONFIG_AUDIODOCK );
941 if ((err = snd_emu1010_load_firmware(emu, dock_filename)) != 0) {
942 return err;
943 }
9f4bd5dd
JCD		 944 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0 );
945 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &reg );
946 snd_printk(KERN_INFO "emu1010: EMU_HANA+DOCK_IRQ_STATUS=0x%x\n",reg);
947 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
948 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg );
949 snd_printk(KERN_INFO "emu1010: EMU_HANA+DOCK_ID=0x%x\n",reg);
950 if (reg != 0x55) {
951 /* FPGA failed to be programmed */
952 snd_printk(KERN_INFO "emu1010: Loading Audio Dock Firmware file failed, reg=0x%x\n", reg);
953 return 0;
954 return -ENODEV;
955 }
9148cc50
JCD		 956 snd_printk(KERN_INFO "emu1010: Audio Dock Firmware loaded\n");
957 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp );
958 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2 );
959 snd_printk("Audio Dock ver:%d.%d\n",tmp ,tmp2);
9f4bd5dd
JCD		 960 }
961#if 0
962 snd_emu1010_fpga_link_dst_src_write(emu,
963 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */
964 snd_emu1010_fpga_link_dst_src_write(emu,
965 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */
966 snd_emu1010_fpga_link_dst_src_write(emu,
967 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */
968 snd_emu1010_fpga_link_dst_src_write(emu,
969 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */
970#endif
971 /* Default outputs */
972 snd_emu1010_fpga_link_dst_src_write(emu,
973 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
974 emu->emu1010.output_source[0] = 21;
975 snd_emu1010_fpga_link_dst_src_write(emu,
976 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
977 emu->emu1010.output_source[1] = 22;
978 snd_emu1010_fpga_link_dst_src_write(emu,
979 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
980 emu->emu1010.output_source[2] = 23;
981 snd_emu1010_fpga_link_dst_src_write(emu,
982 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
983 emu->emu1010.output_source[3] = 24;
984 snd_emu1010_fpga_link_dst_src_write(emu,
985 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
986 emu->emu1010.output_source[4] = 25;
987 snd_emu1010_fpga_link_dst_src_write(emu,
988 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
989 emu->emu1010.output_source[5] = 26;
990 snd_emu1010_fpga_link_dst_src_write(emu,
991 EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6);
992 emu->emu1010.output_source[6] = 27;
993 snd_emu1010_fpga_link_dst_src_write(emu,
994 EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7);
995 emu->emu1010.output_source[7] = 28;
996 snd_emu1010_fpga_link_dst_src_write(emu,
997 EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
998 emu->emu1010.output_source[8] = 21;
999 snd_emu1010_fpga_link_dst_src_write(emu,
1000 EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1001 emu->emu1010.output_source[9] = 22;
1002 snd_emu1010_fpga_link_dst_src_write(emu,
1003 EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
1004 emu->emu1010.output_source[10] = 21;
1005 snd_emu1010_fpga_link_dst_src_write(emu,
1006 EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1007 emu->emu1010.output_source[11] = 22;
1008 snd_emu1010_fpga_link_dst_src_write(emu,
1009 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
1010 emu->emu1010.output_source[12] = 21;
1011 snd_emu1010_fpga_link_dst_src_write(emu,
1012 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1013 emu->emu1010.output_source[13] = 22;
1014 snd_emu1010_fpga_link_dst_src_write(emu,
1015 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
1016 emu->emu1010.output_source[14] = 21;
1017 snd_emu1010_fpga_link_dst_src_write(emu,
1018 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1019 emu->emu1010.output_source[15] = 22;
1020 snd_emu1010_fpga_link_dst_src_write(emu,
1021 EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
1022 emu->emu1010.output_source[16] = 21;
1023 snd_emu1010_fpga_link_dst_src_write(emu,
1024 EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1);
1025 emu->emu1010.output_source[17] = 22;
1026 snd_emu1010_fpga_link_dst_src_write(emu,
1027 EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2);
1028 emu->emu1010.output_source[18] = 23;
1029 snd_emu1010_fpga_link_dst_src_write(emu,
1030 EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3);
1031 emu->emu1010.output_source[19] = 24;
1032 snd_emu1010_fpga_link_dst_src_write(emu,
1033 EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4);
1034 emu->emu1010.output_source[20] = 25;
1035 snd_emu1010_fpga_link_dst_src_write(emu,
1036 EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5);
1037 emu->emu1010.output_source[21] = 26;
1038 snd_emu1010_fpga_link_dst_src_write(emu,
1039 EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6);
1040 emu->emu1010.output_source[22] = 27;
1041 snd_emu1010_fpga_link_dst_src_write(emu,
1042 EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7);
1043 emu->emu1010.output_source[23] = 28;
1044
1045 /* TEMP: Select SPDIF in/out */
1046 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); /* Output spdif */
1047
1048 /* TEMP: Select 48kHz SPDIF out */
1049 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */
1050 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x0); /* Default fallback clock 48kHz */
1051 /* Word Clock source, Internal 48kHz x1 */
1052 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K );
1053 //snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X );
b0dbdaea 1054 emu->emu1010.internal_clock = 1; /* 48000 */
9f4bd5dd
JCD		 1055 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);/* Set LEDs on Audio Dock */
1056 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x1); /* Unmute all */
1057 //snd_emu1010_fpga_write(emu, 0x7, 0x0); /* Mute all */
1058 //snd_emu1010_fpga_write(emu, 0x7, 0x1); /* Unmute all */
1059 //snd_emu1010_fpga_write(emu, 0xe, 0x12); /* Set LEDs on Audio Dock */
19b99fba
JCD		 1060
1061 return 0;
1062}
1da177e4
LT		 1063/*
1064 * Create the EMU10K1 instance
1065 */
1066
09668b44
TI		 1067#ifdef CONFIG_PM
1068static int alloc_pm_buffer(struct snd_emu10k1 *emu);
1069static void free_pm_buffer(struct snd_emu10k1 *emu);
1070#endif
1071
eb4698f3 1072static int snd_emu10k1_free(struct snd_emu10k1 *emu)
1da177e4
LT		 1073{
1074 if (emu->port) { /* avoid access to already used hardware */
1075 snd_emu10k1_fx8010_tram_setup(emu, 0);
1076 snd_emu10k1_done(emu);
09668b44
TI		 1077 /* remove reserved page */
1078 if (emu->reserved_page) {
1079 snd_emu10k1_synth_free(emu, (struct snd_util_memblk *)emu->reserved_page);
1080 emu->reserved_page = NULL;
1081 }
1082 snd_emu10k1_free_efx(emu);
1da177e4 1083 }
9f4bd5dd
JCD		 1084 if (emu->card_capabilities->emu1010) {
1085 /* Disable 48Volt power to Audio Dock */
1086 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0 );
1087 }
1da177e4
LT		 1088 if (emu->memhdr)
1089 snd_util_memhdr_free(emu->memhdr);
1090 if (emu->silent_page.area)
1091 snd_dma_free_pages(&emu->silent_page);
1092 if (emu->ptb_pages.area)
1093 snd_dma_free_pages(&emu->ptb_pages);
1094 vfree(emu->page_ptr_table);
1095 vfree(emu->page_addr_table);
09668b44
TI		 1096#ifdef CONFIG_PM
1097 free_pm_buffer(emu);
1098#endif
1da177e4 1099 if (emu->irq >= 0)
437a5a46 1100 free_irq(emu->irq, emu);
1da177e4
LT		 1101 if (emu->port)
1102 pci_release_regions(emu->pci);
2b637da5 1103 if (emu->card_capabilities->ca0151_chip) /* P16V */
1da177e4 1104 snd_p16v_free(emu);
09668b44 1105 pci_disable_device(emu->pci);
1da177e4
LT		 1106 kfree(emu);
1107 return 0;
1108}
1109
eb4698f3 1110static int snd_emu10k1_dev_free(struct snd_device *device)
1da177e4 1111{
eb4698f3 1112 struct snd_emu10k1 *emu = device->device_data;
1da177e4
LT		 1113 return snd_emu10k1_free(emu);
1114}
1115
eb4698f3 1116static struct snd_emu_chip_details emu_chip_details[] = {
1da177e4 1117 /* Audigy 2 Value AC3 out does not work yet. Need to find out how to turn off interpolators.*/
88dc0e5d 1118 /* Tested by James@superbug.co.uk 3rd July 2005 */
54efc96d
JCD		 1119 /* DSP: CA0108-IAT
1120 * DAC: CS4382-KQ
1121 * ADC: Philips 1361T
1122 * AC97: STAC9750
1123 * CA0151: None
1124 */
1da177e4
LT		 1125 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
1126 .driver = "Audigy2", .name = "Audigy 2 Value [SB0400]",
aec72e0a 1127 .id = "Audigy2",
1da177e4
LT		 1128 .emu10k2_chip = 1,
1129 .ca0108_chip = 1,
2668907a
PZ		 1130 .spk71 = 1,
1131 .ac97_chip = 1} ,
21fdddea
JCD		 1132 /* Audigy4 (Not PRO) SB0610 */
1133 /* Tested by James@superbug.co.uk 4th April 2006 */
1134 /* A_IOCFG bits
1135 * Output
1136 * 0: ?
1137 * 1: ?
1138 * 2: ?
1139 * 3: 0 - Digital Out, 1 - Line in
1140 * 4: ?
1141 * 5: ?
1142 * 6: ?
1143 * 7: ?
1144 * Input
1145 * 8: ?
1146 * 9: ?
1147 * A: Green jack sense (Front)
1148 * B: ?
1149 * C: Black jack sense (Rear/Side Right)
1150 * D: Yellow jack sense (Center/LFE/Side Left)
1151 * E: ?
1152 * F: ?
1153 *
1154 * Digital Out/Line in switch using A_IOCFG bit 3 (0x08)
1155 * 0 - Digital Out
1156 * 1 - Line in
1157 */
1158 /* Mic input not tested.
1159 * Analog CD input not tested
1160 * Digital Out not tested.
1161 * Line in working.
1162 * Audio output 5.1 working. Side outputs not working.
1163 */
1164 /* DSP: CA10300-IAT LF
1165 * DAC: Cirrus Logic CS4382-KQZ
1166 * ADC: Philips 1361T
1167 * AC97: Sigmatel STAC9750
1168 * CA0151: None
1169 */
1170 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102,
1171 .driver = "Audigy2", .name = "Audigy 4 [SB0610]",
1172 .id = "Audigy2",
1173 .emu10k2_chip = 1,
1174 .ca0108_chip = 1,
1175 .spk71 = 1,
1176 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1177 .ac97_chip = 1} ,
d83c671f 1178 /* Audigy 2 ZS Notebook Cardbus card.*/
184c1e2c 1179 /* Tested by James@superbug.co.uk 6th November 2006 */
f951fd3c
JCD		 1180 /* Audio output 7.1/Headphones working.
1181 * Digital output working. (AC3 not checked, only PCM)
184c1e2c
JCD		 1182 * Audio Mic/Line inputs working.
1183 * Digital input not tested.
f951fd3c 1184 */
21fdddea 1185 /* DSP: Tina2
f951fd3c
JCD		 1186 * DAC: Wolfson WM8768/WM8568
1187 * ADC: Wolfson WM8775
1188 * AC97: None
1189 * CA0151: None
1190 */
184c1e2c
JCD		 1191 /* Tested by James@superbug.co.uk 4th April 2006 */
1192 /* A_IOCFG bits
1193 * Output
1194 * 0: Not Used
1195 * 1: 0 = Mute all the 7.1 channel out. 1 = unmute.
1196 * 2: Analog input 0 = line in, 1 = mic in
1197 * 3: Not Used
1198 * 4: Digital output 0 = off, 1 = on.
1199 * 5: Not Used
1200 * 6: Not Used
1201 * 7: Not Used
1202 * Input
1203 * All bits 1 (0x3fxx) means nothing plugged in.
1204 * 8-9: 0 = Line in/Mic, 2 = Optical in, 3 = Nothing.
1205 * A-B: 0 = Headphones, 2 = Optical out, 3 = Nothing.
1206 * C-D: 2 = Front/Rear/etc, 3 = nothing.
1207 * E-F: Always 0
1208 *
1209 */
d83c671f
JCD		 1210 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102,
1211 .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]",
1212 .id = "Audigy2",
1213 .emu10k2_chip = 1,
1214 .ca0108_chip = 1,
1215 .ca_cardbus_chip = 1,
27fe864e 1216 .spi_dac = 1,
184c1e2c 1217 .i2c_adc = 1,
d83c671f 1218 .spk71 = 1} ,
1da177e4
LT		 1219 {.vendor = 0x1102, .device = 0x0008,
1220 .driver = "Audigy2", .name = "Audigy 2 Value [Unknown]",
aec72e0a 1221 .id = "Audigy2",
1da177e4 1222 .emu10k2_chip = 1,
2668907a
PZ		 1223 .ca0108_chip = 1,
1224 .ac97_chip = 1} ,
7c1d549a
JCD		 1225 /* Tested by James@superbug.co.uk 8th July 2005. No sound available yet. */
1226 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102,
9f4bd5dd
JCD		 1227 .driver = "Audigy2", .name = "E-mu 1010 [4001]",
1228 .id = "EMU1010",
7c1d549a
JCD		 1229 .emu10k2_chip = 1,
1230 .ca0102_chip = 1,
9f4bd5dd
JCD		 1231 .spk71 = 1,
1232 .emu1010 = 1} ,
88dc0e5d 1233 /* Tested by James@superbug.co.uk 3rd July 2005 */
1da177e4
LT		 1234 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102,
1235 .driver = "Audigy2", .name = "Audigy 4 PRO [SB0380]",
aec72e0a 1236 .id = "Audigy2",
1da177e4
LT		 1237 .emu10k2_chip = 1,
1238 .ca0102_chip = 1,
1239 .ca0151_chip = 1,
1240 .spk71 = 1,
1241 .spdif_bug = 1,
1242 .ac97_chip = 1} ,
f6f8bb64 1243 /* Tested by shane-alsa@cm.nu 5th Nov 2005 */
5b0e4985
JCD		 1244 /* The 0x20061102 does have SB0350 written on it
1245 * Just like 0x20021102
1246 */
f6f8bb64 1247 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102,
5b0e4985 1248 .driver = "Audigy2", .name = "Audigy 2 [SB0350b]",
f6f8bb64
LR		 1249 .id = "Audigy2",
1250 .emu10k2_chip = 1,
1251 .ca0102_chip = 1,
1252 .ca0151_chip = 1,
1253 .spk71 = 1,
1254 .spdif_bug = 1,
1255 .ac97_chip = 1} ,
1da177e4
LT		 1256 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102,
1257 .driver = "Audigy2", .name = "Audigy 2 ZS [SB0350]",
aec72e0a 1258 .id = "Audigy2",
1da177e4
LT		 1259 .emu10k2_chip = 1,
1260 .ca0102_chip = 1,
1261 .ca0151_chip = 1,
1262 .spk71 = 1,
1263 .spdif_bug = 1,
1264 .ac97_chip = 1} ,
1265 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102,
1266 .driver = "Audigy2", .name = "Audigy 2 ZS [2001]",
aec72e0a 1267 .id = "Audigy2",
1da177e4
LT		 1268 .emu10k2_chip = 1,
1269 .ca0102_chip = 1,
1270 .ca0151_chip = 1,
1271 .spk71 = 1,
1272 .spdif_bug = 1,
1273 .ac97_chip = 1} ,
54efc96d
JCD		 1274 /* Audigy 2 */
1275 /* Tested by James@superbug.co.uk 3rd July 2005 */
1276 /* DSP: CA0102-IAT
1277 * DAC: CS4382-KQ
1278 * ADC: Philips 1361T
1279 * AC97: STAC9721
1280 * CA0151: Yes
1281 */
1da177e4
LT		 1282 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102,
1283 .driver = "Audigy2", .name = "Audigy 2 [SB0240]",
aec72e0a 1284 .id = "Audigy2",
1da177e4
LT		 1285 .emu10k2_chip = 1,
1286 .ca0102_chip = 1,
1287 .ca0151_chip = 1,
1288 .spk71 = 1,
1289 .spdif_bug = 1,
11b3a755 1290 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1da177e4
LT		 1291 .ac97_chip = 1} ,
1292 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102,
1293 .driver = "Audigy2", .name = "Audigy 2 EX [1005]",
aec72e0a 1294 .id = "Audigy2",
1da177e4
LT		 1295 .emu10k2_chip = 1,
1296 .ca0102_chip = 1,
1297 .ca0151_chip = 1,
2f020aa7 1298 .spk71 = 1,
1da177e4 1299 .spdif_bug = 1} ,
264f9577
JCD		 1300 /* Dell OEM/Creative Labs Audigy 2 ZS */
1301 /* See ALSA bug#1365 */
1302 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102,
1303 .driver = "Audigy2", .name = "Audigy 2 ZS [SB0353]",
1304 .id = "Audigy2",
1305 .emu10k2_chip = 1,
1306 .ca0102_chip = 1,
1307 .ca0151_chip = 1,
1308 .spk71 = 1,
1309 .spdif_bug = 1,
1310 .ac97_chip = 1} ,
1da177e4
LT		 1311 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102,
1312 .driver = "Audigy2", .name = "Audigy 2 Platinum [SB0240P]",
aec72e0a 1313 .id = "Audigy2",
1da177e4
LT		 1314 .emu10k2_chip = 1,
1315 .ca0102_chip = 1,
1316 .ca0151_chip = 1,
1317 .spk71 = 1,
1318 .spdif_bug = 1,
3271b7b2 1319 .adc_1361t = 1, /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */
1da177e4 1320 .ac97_chip = 1} ,
bdaed502
TI		 1321 {.vendor = 0x1102, .device = 0x0004, .revision = 0x04,
1322 .driver = "Audigy2", .name = "Audigy 2 [Unknown]",
1323 .id = "Audigy2",
1324 .emu10k2_chip = 1,
1325 .ca0102_chip = 1,
1326 .ca0151_chip = 1,
1327 .spdif_bug = 1,
1328 .ac97_chip = 1} ,
ae3a72d8
JCD		 1329 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
1330 .driver = "Audigy", .name = "Audigy 1 [SB0090]",
aec72e0a 1331 .id = "Audigy",
56f5ceed
JCD		 1332 .emu10k2_chip = 1,
1333 .ca0102_chip = 1,
2668907a 1334 .ac97_chip = 1} ,
ae3a72d8
JCD		 1335 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102,
1336 .driver = "Audigy", .name = "Audigy 1 ES [SB0160]",
2668907a
PZ		 1337 .id = "Audigy",
1338 .emu10k2_chip = 1,
1339 .ca0102_chip = 1,
ae3a72d8 1340 .spdif_bug = 1,
2668907a 1341 .ac97_chip = 1} ,
a6c17ec8
AP		 1342 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102,
1343 .driver = "Audigy", .name = "Audigy 1 [SB0090]",
1344 .id = "Audigy",
1345 .emu10k2_chip = 1,
1346 .ca0102_chip = 1,
1347 .ac97_chip = 1} ,
1da177e4 1348 {.vendor = 0x1102, .device = 0x0004,
bdaed502 1349 .driver = "Audigy", .name = "Audigy 1 [Unknown]",
aec72e0a 1350 .id = "Audigy",
1da177e4
LT		 1351 .emu10k2_chip = 1,
1352 .ca0102_chip = 1,
2668907a 1353 .ac97_chip = 1} ,
a6f6192b
JCD		 1354 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806B1102,
1355 .driver = "EMU10K1", .name = "SBLive! [SB0105]",
f7de9cfd
MM		 1356 .id = "Live",
1357 .emu10k1_chip = 1,
1358 .ac97_chip = 1,
1359 .sblive51 = 1} ,
a6f6192b
JCD		 1360 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806A1102,
1361 .driver = "EMU10K1", .name = "SBLive! Value [SB0103]",
aec72e0a 1362 .id = "Live",
1da177e4 1363 .emu10k1_chip = 1,
2b637da5
LR		 1364 .ac97_chip = 1,
1365 .sblive51 = 1} ,
a6f6192b
JCD		 1366 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102,
1367 .driver = "EMU10K1", .name = "SBLive! Value [SB0101]",
2b6b22f3
JCD		 1368 .id = "Live",
1369 .emu10k1_chip = 1,
1370 .ac97_chip = 1,
1371 .sblive51 = 1} ,
0ba656d0
JCD		 1372 /* Tested by ALSA bug#1680 26th December 2005 */
1373 /* note: It really has SB0220 written on the card. */
1374 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102,
1375 .driver = "EMU10K1", .name = "SB Live 5.1 Dell OEM [SB0220]",
1376 .id = "Live",
1377 .emu10k1_chip = 1,
1378 .ac97_chip = 1,
1379 .sblive51 = 1} ,
c6c0b841
LR		 1380 /* Tested by Thomas Zehetbauer 27th Aug 2005 */
1381 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102,
1382 .driver = "EMU10K1", .name = "SB Live 5.1 [SB0220]",
1383 .id = "Live",
1384 .emu10k1_chip = 1,
1385 .ac97_chip = 1,
1386 .sblive51 = 1} ,
a8ee7295
GT		 1387 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102,
1388 .driver = "EMU10K1", .name = "SB Live 5.1 [SB0220]",
1389 .id = "Live",
1390 .emu10k1_chip = 1,
1391 .ac97_chip = 1,
1392 .sblive51 = 1} ,
a6f6192b
JCD		 1393 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
1394 .driver = "EMU10K1", .name = "SB Live 5.1",
2b6b22f3
JCD		 1395 .id = "Live",
1396 .emu10k1_chip = 1,
1397 .ac97_chip = 1,
1398 .sblive51 = 1} ,
afe0f1f6 1399 /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */
a6f6192b 1400 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
f12aa40c 1401 .driver = "EMU10K1", .name = "SBLive 5.1 [SB0060]",
2b6b22f3
JCD		 1402 .id = "Live",
1403 .emu10k1_chip = 1,
f12aa40c
TI		 1404 .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum
1405 * share the same IDs!
1406 */
2b6b22f3 1407 .sblive51 = 1} ,
a6f6192b
JCD		 1408 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102,
1409 .driver = "EMU10K1", .name = "SBLive! Value [CT4850]",
2b6b22f3
JCD		 1410 .id = "Live",
1411 .emu10k1_chip = 1,
1412 .ac97_chip = 1,
1413 .sblive51 = 1} ,
a6f6192b
JCD		 1414 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
1415 .driver = "EMU10K1", .name = "SBLive! Platinum [CT4760P]",
1416 .id = "Live",
1417 .emu10k1_chip = 1,
1418 .ac97_chip = 1} ,
1419 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102,
1420 .driver = "EMU10K1", .name = "SBLive! Value [CT4871]",
2b6b22f3
JCD		 1421 .id = "Live",
1422 .emu10k1_chip = 1,
1423 .ac97_chip = 1,
1424 .sblive51 = 1} ,
1425 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102,
1426 .driver = "EMU10K1", .name = "SBLive! Value [CT4831]",
1427 .id = "Live",
1428 .emu10k1_chip = 1,
1429 .ac97_chip = 1,
1430 .sblive51 = 1} ,
a6f6192b
JCD		 1431 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102,
1432 .driver = "EMU10K1", .name = "SBLive! Value [CT4870]",
aec72e0a 1433 .id = "Live",
2b637da5
LR		 1434 .emu10k1_chip = 1,
1435 .ac97_chip = 1,
1436 .sblive51 = 1} ,
88dc0e5d 1437 /* Tested by James@superbug.co.uk 3rd July 2005 */
a6f6192b
JCD		 1438 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
1439 .driver = "EMU10K1", .name = "SBLive! Value [CT4832]",
2b6b22f3
JCD		 1440 .id = "Live",
1441 .emu10k1_chip = 1,
1442 .ac97_chip = 1,
1443 .sblive51 = 1} ,
a6f6192b
JCD		 1444 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102,
1445 .driver = "EMU10K1", .name = "SBLive! Value [CT4830]",
2b6b22f3
JCD		 1446 .id = "Live",
1447 .emu10k1_chip = 1,
1448 .ac97_chip = 1,
1449 .sblive51 = 1} ,
a6f6192b
JCD		 1450 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102,
1451 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]",
2b6b22f3
JCD		 1452 .id = "Live",
1453 .emu10k1_chip = 1,
1454 .ac97_chip = 1,
1455 .sblive51 = 1} ,
a6f6192b
JCD		 1456 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102,
1457 .driver = "EMU10K1", .name = "SBLive! Value [CT4780]",
2b6b22f3
JCD		 1458 .id = "Live",
1459 .emu10k1_chip = 1,
1460 .ac97_chip = 1,
1461 .sblive51 = 1} ,
a6f6192b
JCD		 1462 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
1463 .driver = "EMU10K1", .name = "E-mu APS [4001]",
1464 .id = "APS",
2b6b22f3 1465 .emu10k1_chip = 1,
a6f6192b
JCD		 1466 .ecard = 1} ,
1467 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102,
1468 .driver = "EMU10K1", .name = "SBLive! [CT4620]",
2b6b22f3
JCD		 1469 .id = "Live",
1470 .emu10k1_chip = 1,
1471 .ac97_chip = 1,
1472 .sblive51 = 1} ,
a6f6192b
JCD		 1473 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102,
1474 .driver = "EMU10K1", .name = "SBLive! Value [CT4670]",
2b6b22f3
JCD		 1475 .id = "Live",
1476 .emu10k1_chip = 1,
1477 .ac97_chip = 1,
1478 .sblive51 = 1} ,
1da177e4
LT		 1479 {.vendor = 0x1102, .device = 0x0002,
1480 .driver = "EMU10K1", .name = "SB Live [Unknown]",
aec72e0a 1481 .id = "Live",
1da177e4 1482 .emu10k1_chip = 1,
2b637da5
LR		 1483 .ac97_chip = 1,
1484 .sblive51 = 1} ,
1da177e4
LT		 1485 { } /* terminator */
1486};
1487
eb4698f3 1488int __devinit snd_emu10k1_create(struct snd_card *card,
1da177e4
LT		 1489 struct pci_dev * pci,
1490 unsigned short extin_mask,
1491 unsigned short extout_mask,
1492 long max_cache_bytes,
1493 int enable_ir,
e66bc8b2 1494 uint subsystem,
eb4698f3 1495 struct snd_emu10k1 ** remu)
1da177e4 1496{
eb4698f3 1497 struct snd_emu10k1 *emu;
09668b44 1498 int idx, err;
1da177e4
LT		 1499 int is_audigy;
1500 unsigned char revision;
09668b44 1501 unsigned int silent_page;
eb4698f3
TI		 1502 const struct snd_emu_chip_details *c;
1503 static struct snd_device_ops ops = {
1da177e4
LT		 1504 .dev_free = snd_emu10k1_dev_free,
1505 };
1506
1507 *remu = NULL;
1508
1509 /* enable PCI device */
1510 if ((err = pci_enable_device(pci)) < 0)
1511 return err;
1512
e560d8d8 1513 emu = kzalloc(sizeof(*emu), GFP_KERNEL);
1da177e4
LT		 1514 if (emu == NULL) {
1515 pci_disable_device(pci);
1516 return -ENOMEM;
1517 }
1518 emu->card = card;
1519 spin_lock_init(&emu->reg_lock);
1520 spin_lock_init(&emu->emu_lock);
1521 spin_lock_init(&emu->voice_lock);
1522 spin_lock_init(&emu->synth_lock);
1523 spin_lock_init(&emu->memblk_lock);
62932df8 1524 mutex_init(&emu->fx8010.lock);
1da177e4
LT		 1525 INIT_LIST_HEAD(&emu->mapped_link_head);
1526 INIT_LIST_HEAD(&emu->mapped_order_link_head);
1527 emu->pci = pci;
1528 emu->irq = -1;
1529 emu->synth = NULL;
1530 emu->get_synth_voice = NULL;
1531 /* read revision & serial */
1532 pci_read_config_byte(pci, PCI_REVISION_ID, &revision);
1533 emu->revision = revision;
1534 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
1535 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
1da177e4
LT		 1536 snd_printdd("vendor=0x%x, device=0x%x, subsystem_vendor_id=0x%x, subsystem_id=0x%x\n",pci->vendor, pci->device, emu->serial, emu->model);
1537
1538 for (c = emu_chip_details; c->vendor; c++) {
1539 if (c->vendor == pci->vendor && c->device == pci->device) {
e66bc8b2
JCD		 1540 if (subsystem) {
1541 if (c->subsystem && (c->subsystem == subsystem) ) {
1542 break;
1543 } else continue;
1544 } else {
1545 if (c->subsystem && (c->subsystem != emu->serial) )
1546 continue;
1547 if (c->revision && c->revision != emu->revision)
1548 continue;
1549 }
bdaed502 1550 break;
1da177e4
LT		 1551 }
1552 }
1553 if (c->vendor == 0) {
1554 snd_printk(KERN_ERR "emu10k1: Card not recognised\n");
1555 kfree(emu);
1556 pci_disable_device(pci);
1557 return -ENOENT;
1558 }
1559 emu->card_capabilities = c;
e66bc8b2 1560 if (c->subsystem && !subsystem)
1da177e4 1561 snd_printdd("Sound card name=%s\n", c->name);
e66bc8b2
JCD		 1562 else if (subsystem)
1563 snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x. Forced to subsytem=0x%x\n",
1564 c->name, pci->vendor, pci->device, emu->serial, c->subsystem);
1565 else
1566 snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x.\n",
1567 c->name, pci->vendor, pci->device, emu->serial);
1da177e4 1568
85a655d6
TI		 1569 if (!*card->id && c->id) {
1570 int i, n = 0;
aec72e0a 1571 strlcpy(card->id, c->id, sizeof(card->id));
85a655d6
TI		 1572 for (;;) {
1573 for (i = 0; i < snd_ecards_limit; i++) {
1574 if (snd_cards[i] && !strcmp(snd_cards[i]->id, card->id))
1575 break;
1576 }
1577 if (i >= snd_ecards_limit)
1578 break;
1579 n++;
1580 if (n >= SNDRV_CARDS)
1581 break;
1582 snprintf(card->id, sizeof(card->id), "%s_%d", c->id, n);
1583 }
1584 }
aec72e0a 1585
1da177e4
LT		 1586 is_audigy = emu->audigy = c->emu10k2_chip;
1587
1588 /* set the DMA transfer mask */
1589 emu->dma_mask = is_audigy ? AUDIGY_DMA_MASK : EMU10K1_DMA_MASK;
1590 if (pci_set_dma_mask(pci, emu->dma_mask) < 0 ||
1591 pci_set_consistent_dma_mask(pci, emu->dma_mask) < 0) {
1592 snd_printk(KERN_ERR "architecture does not support PCI busmaster DMA with mask 0x%lx\n", emu->dma_mask);
1593 kfree(emu);
1594 pci_disable_device(pci);
1595 return -ENXIO;
1596 }
1597 if (is_audigy)
1598 emu->gpr_base = A_FXGPREGBASE;
1599 else
1600 emu->gpr_base = FXGPREGBASE;
1601
1602 if ((err = pci_request_regions(pci, "EMU10K1")) < 0) {
1603 kfree(emu);
1604 pci_disable_device(pci);
1605 return err;
1606 }
1607 emu->port = pci_resource_start(pci, 0);
1608
437a5a46
TI		 1609 if (request_irq(pci->irq, snd_emu10k1_interrupt, IRQF_SHARED,
1610 "EMU10K1", emu)) {
09668b44
TI		 1611 err = -EBUSY;
1612 goto error;
1da177e4
LT		 1613 }
1614 emu->irq = pci->irq;
1615
1616 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
1617 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1618 32 * 1024, &emu->ptb_pages) < 0) {
09668b44
TI		 1619 err = -ENOMEM;
1620 goto error;
1da177e4
LT		 1621 }
1622
1623 emu->page_ptr_table = (void **)vmalloc(emu->max_cache_pages * sizeof(void*));
1624 emu->page_addr_table = (unsigned long*)vmalloc(emu->max_cache_pages * sizeof(unsigned long));
1625 if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
09668b44
TI		 1626 err = -ENOMEM;
1627 goto error;
1da177e4
LT		 1628 }
1629
1630 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1631 EMUPAGESIZE, &emu->silent_page) < 0) {
09668b44
TI		 1632 err = -ENOMEM;
1633 goto error;
1da177e4
LT		 1634 }
1635 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
1636 if (emu->memhdr == NULL) {
09668b44
TI		 1637 err = -ENOMEM;
1638 goto error;
1da177e4 1639 }
eb4698f3
TI		 1640 emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) -
1641 sizeof(struct snd_util_memblk);
1da177e4
LT		 1642
1643 pci_set_master(pci);
1644
1da177e4
LT		 1645 emu->fx8010.fxbus_mask = 0x303f;
1646 if (extin_mask == 0)
1647 extin_mask = 0x3fcf;
1648 if (extout_mask == 0)
1649 extout_mask = 0x7fff;
1650 emu->fx8010.extin_mask = extin_mask;
1651 emu->fx8010.extout_mask = extout_mask;
09668b44 1652 emu->enable_ir = enable_ir;
1da177e4 1653
2b637da5 1654 if (emu->card_capabilities->ecard) {
09668b44
TI		 1655 if ((err = snd_emu10k1_ecard_init(emu)) < 0)
1656 goto error;
d83c671f 1657 } else if (emu->card_capabilities->ca_cardbus_chip) {
09668b44
TI		 1658 if ((err = snd_emu10k1_cardbus_init(emu)) < 0)
1659 goto error;
9f4bd5dd
JCD		 1660 } else if (emu->card_capabilities->emu1010) {
1661 if ((err = snd_emu10k1_emu1010_init(emu)) < 0) {
19b99fba
JCD		 1662 snd_emu10k1_free(emu);
1663 return err;
1664 }
1da177e4
LT		 1665 } else {
1666 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
1667 does not support this, it shouldn't do any harm */
1668 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
1669 }
1670
09668b44
TI		 1671 /* initialize TRAM setup */
1672 emu->fx8010.itram_size = (16 * 1024)/2;
1673 emu->fx8010.etram_pages.area = NULL;
1674 emu->fx8010.etram_pages.bytes = 0;
1da177e4 1675
09668b44
TI		 1676 /*
1677 * Init to 0x02109204 :
1678 * Clock accuracy = 0 (1000ppm)
1679 * Sample Rate = 2 (48kHz)
1680 * Audio Channel = 1 (Left of 2)
1681 * Source Number = 0 (Unspecified)
1682 * Generation Status = 1 (Original for Cat Code 12)
1683 * Cat Code = 12 (Digital Signal Mixer)
1684 * Mode = 0 (Mode 0)
1685 * Emphasis = 0 (None)
1686 * CP = 1 (Copyright unasserted)
1687 * AN = 0 (Audio data)
1688 * P = 0 (Consumer)
1689 */
1690 emu->spdif_bits[0] = emu->spdif_bits[1] =
1691 emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
1692 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
1693 SPCS_GENERATIONSTATUS | 0x00001200 |
1694 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
1695
1696 emu->reserved_page = (struct snd_emu10k1_memblk *)
1697 snd_emu10k1_synth_alloc(emu, 4096);
1698 if (emu->reserved_page)
1699 emu->reserved_page->map_locked = 1;
1700
1701 /* Clear silent pages and set up pointers */
1702 memset(emu->silent_page.area, 0, PAGE_SIZE);
1703 silent_page = emu->silent_page.addr << 1;
1704 for (idx = 0; idx < MAXPAGES; idx++)
1705 ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
1706
1707 /* set up voice indices */
1708 for (idx = 0; idx < NUM_G; idx++) {
1709 emu->voices[idx].emu = emu;
1710 emu->voices[idx].number = idx;
1da177e4
LT		 1711 }
1712
09668b44
TI		 1713 if ((err = snd_emu10k1_init(emu, enable_ir, 0)) < 0)
1714 goto error;
1715#ifdef CONFIG_PM
1716 if ((err = alloc_pm_buffer(emu)) < 0)
1717 goto error;
1718#endif
1719
1720 /* Initialize the effect engine */
1721 if ((err = snd_emu10k1_init_efx(emu)) < 0)
1722 goto error;
1723 snd_emu10k1_audio_enable(emu);
1724
1725 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops)) < 0)
1726 goto error;
1727
adf1b3d2 1728#ifdef CONFIG_PROC_FS
1da177e4 1729 snd_emu10k1_proc_init(emu);
adf1b3d2 1730#endif
1da177e4
LT		 1731
1732 snd_card_set_dev(card, &pci->dev);
1733 *remu = emu;
1734 return 0;
09668b44
TI		 1735
1736 error:
1737 snd_emu10k1_free(emu);
1738 return err;
1da177e4
LT		 1739}
1740
09668b44
TI		 1741#ifdef CONFIG_PM
1742static unsigned char saved_regs[] = {
1743 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
1744 FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL,
1745 ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2,
1746 TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA,
1747 MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2,
1748 SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX,
1749 0xff /* end */
1750};
1751static unsigned char saved_regs_audigy[] = {
1752 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_SAMPLE_RATE,
1753 A_FXRT2, A_SENDAMOUNTS, A_FXRT1,
1754 0xff /* end */
1755};
1756
1757static int __devinit alloc_pm_buffer(struct snd_emu10k1 *emu)
1758{
1759 int size;
1760
1761 size = ARRAY_SIZE(saved_regs);
1762 if (emu->audigy)
1763 size += ARRAY_SIZE(saved_regs_audigy);
1764 emu->saved_ptr = vmalloc(4 * NUM_G * size);
1765 if (! emu->saved_ptr)
1766 return -ENOMEM;
1767 if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0)
1768 return -ENOMEM;
1769 if (emu->card_capabilities->ca0151_chip &&
1770 snd_p16v_alloc_pm_buffer(emu) < 0)
1771 return -ENOMEM;
1772 return 0;
1773}
1774
1775static void free_pm_buffer(struct snd_emu10k1 *emu)
1776{
1777 vfree(emu->saved_ptr);
1778 snd_emu10k1_efx_free_pm_buffer(emu);
1779 if (emu->card_capabilities->ca0151_chip)
1780 snd_p16v_free_pm_buffer(emu);
1781}
1782
1783void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu)
1784{
1785 int i;
1786 unsigned char *reg;
1787 unsigned int *val;
1788
1789 val = emu->saved_ptr;
1790 for (reg = saved_regs; *reg != 0xff; reg++)
1791 for (i = 0; i < NUM_G; i++, val++)
1792 *val = snd_emu10k1_ptr_read(emu, *reg, i);
1793 if (emu->audigy) {
1794 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
1795 for (i = 0; i < NUM_G; i++, val++)
1796 *val = snd_emu10k1_ptr_read(emu, *reg, i);
1797 }
1798 if (emu->audigy)
1799 emu->saved_a_iocfg = inl(emu->port + A_IOCFG);
1800 emu->saved_hcfg = inl(emu->port + HCFG);
1801}
1802
1803void snd_emu10k1_resume_init(struct snd_emu10k1 *emu)
1804{
1805 if (emu->card_capabilities->ecard)
1806 snd_emu10k1_ecard_init(emu);
f40b6890
TI		 1807 else if (emu->card_capabilities->ca_cardbus_chip)
1808 snd_emu10k1_cardbus_init(emu);
9f4bd5dd
JCD		 1809 else if (emu->card_capabilities->emu1010)
1810 snd_emu10k1_emu1010_init(emu);
09668b44
TI		 1811 else
1812 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
1813 snd_emu10k1_init(emu, emu->enable_ir, 1);
1814}
1815
1816void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu)
1817{
1818 int i;
1819 unsigned char *reg;
1820 unsigned int *val;
1821
1822 snd_emu10k1_audio_enable(emu);
1823
1824 /* resore for spdif */
1825 if (emu->audigy)
4130d59b
AP		 1826 outl(emu->saved_a_iocfg, emu->port + A_IOCFG);
1827 outl(emu->saved_hcfg, emu->port + HCFG);
09668b44
TI		 1828
1829 val = emu->saved_ptr;
1830 for (reg = saved_regs; *reg != 0xff; reg++)
1831 for (i = 0; i < NUM_G; i++, val++)
1832 snd_emu10k1_ptr_write(emu, *reg, i, *val);
1833 if (emu->audigy) {
1834 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
1835 for (i = 0; i < NUM_G; i++, val++)
1836 snd_emu10k1_ptr_write(emu, *reg, i, *val);
1837 }
1838}
1839#endif
Linux 6.x block layer and io_uring tree(s)