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dd7b254d GP |
1 | /**************************************************************************** |
2 | ||
3 | Copyright Echo Digital Audio Corporation (c) 1998 - 2004 | |
4 | All rights reserved | |
5 | www.echoaudio.com | |
6 | ||
7 | This file is part of Echo Digital Audio's generic driver library. | |
8 | ||
9 | Echo Digital Audio's generic driver library is free software; | |
10 | you can redistribute it and/or modify it under the terms of | |
11 | the GNU General Public License as published by the Free Software Foundation. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. | |
22 | ||
23 | ************************************************************************* | |
24 | ||
25 | Translation from C++ and adaptation for use in ALSA-Driver | |
26 | were made by Giuliano Pochini <pochini@shiny.it> | |
27 | ||
28 | ****************************************************************************/ | |
29 | ||
30 | ||
31 | static int write_control_reg(struct echoaudio *chip, u32 value, char force); | |
32 | static int set_input_clock(struct echoaudio *chip, u16 clock); | |
33 | static int set_professional_spdif(struct echoaudio *chip, char prof); | |
34 | static int set_digital_mode(struct echoaudio *chip, u8 mode); | |
35 | static int load_asic_generic(struct echoaudio *chip, u32 cmd, | |
36 | const struct firmware *asic); | |
37 | static int check_asic_status(struct echoaudio *chip); | |
38 | ||
39 | ||
40 | static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id) | |
41 | { | |
42 | int err; | |
43 | ||
44 | DE_INIT(("init_hw() - Layla24\n")); | |
da3cec35 TI |
45 | if (snd_BUG_ON((subdevice_id & 0xfff0) != LAYLA24)) |
46 | return -ENODEV; | |
dd7b254d GP |
47 | |
48 | if ((err = init_dsp_comm_page(chip))) { | |
49 | DE_INIT(("init_hw - could not initialize DSP comm page\n")); | |
50 | return err; | |
51 | } | |
52 | ||
53 | chip->device_id = device_id; | |
54 | chip->subdevice_id = subdevice_id; | |
55 | chip->bad_board = TRUE; | |
56 | chip->has_midi = TRUE; | |
57 | chip->dsp_code_to_load = &card_fw[FW_LAYLA24_DSP]; | |
58 | chip->input_clock_types = | |
59 | ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF | | |
60 | ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT; | |
61 | chip->digital_modes = | |
62 | ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA | | |
63 | ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL | | |
64 | ECHOCAPS_HAS_DIGITAL_MODE_ADAT; | |
65 | chip->digital_mode = DIGITAL_MODE_SPDIF_RCA; | |
66 | chip->professional_spdif = FALSE; | |
67 | chip->digital_in_automute = TRUE; | |
68 | ||
69 | if ((err = load_firmware(chip)) < 0) | |
70 | return err; | |
71 | chip->bad_board = FALSE; | |
72 | ||
73 | if ((err = init_line_levels(chip)) < 0) | |
74 | return err; | |
75 | ||
76 | err = set_digital_mode(chip, DIGITAL_MODE_SPDIF_RCA); | |
da3cec35 TI |
77 | if (err < 0) |
78 | return err; | |
dd7b254d GP |
79 | err = set_professional_spdif(chip, TRUE); |
80 | ||
81 | DE_INIT(("init_hw done\n")); | |
82 | return err; | |
83 | } | |
84 | ||
85 | ||
86 | ||
87 | static u32 detect_input_clocks(const struct echoaudio *chip) | |
88 | { | |
89 | u32 clocks_from_dsp, clock_bits; | |
90 | ||
91 | /* Map the DSP clock detect bits to the generic driver clock detect bits */ | |
92 | clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); | |
93 | ||
94 | clock_bits = ECHO_CLOCK_BIT_INTERNAL; | |
95 | ||
96 | if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF) | |
97 | clock_bits |= ECHO_CLOCK_BIT_SPDIF; | |
98 | ||
99 | if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT) | |
100 | clock_bits |= ECHO_CLOCK_BIT_ADAT; | |
101 | ||
102 | if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD) | |
103 | clock_bits |= ECHO_CLOCK_BIT_WORD; | |
104 | ||
105 | return clock_bits; | |
106 | } | |
107 | ||
108 | ||
109 | ||
110 | /* Layla24 has an ASIC on the PCI card and another ASIC in the external box; | |
111 | both need to be loaded. */ | |
112 | static int load_asic(struct echoaudio *chip) | |
113 | { | |
114 | int err; | |
115 | ||
116 | if (chip->asic_loaded) | |
117 | return 1; | |
118 | ||
119 | DE_INIT(("load_asic\n")); | |
120 | ||
121 | /* Give the DSP a few milliseconds to settle down */ | |
122 | mdelay(10); | |
123 | ||
124 | /* Load the ASIC for the PCI card */ | |
125 | err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC, | |
126 | &card_fw[FW_LAYLA24_1_ASIC]); | |
127 | if (err < 0) | |
128 | return err; | |
129 | ||
130 | chip->asic_code = &card_fw[FW_LAYLA24_2S_ASIC]; | |
131 | ||
132 | /* Now give the new ASIC a little time to set up */ | |
133 | mdelay(10); | |
134 | ||
135 | /* Do the external one */ | |
136 | err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC, | |
137 | &card_fw[FW_LAYLA24_2S_ASIC]); | |
138 | if (err < 0) | |
139 | return FALSE; | |
140 | ||
141 | /* Now give the external ASIC a little time to set up */ | |
142 | mdelay(10); | |
143 | ||
144 | /* See if it worked */ | |
145 | err = check_asic_status(chip); | |
146 | ||
147 | /* Set up the control register if the load succeeded - | |
148 | 48 kHz, internal clock, S/PDIF RCA mode */ | |
149 | if (!err) | |
150 | err = write_control_reg(chip, GML_CONVERTER_ENABLE | GML_48KHZ, | |
151 | TRUE); | |
152 | ||
153 | DE_INIT(("load_asic() done\n")); | |
154 | return err; | |
155 | } | |
156 | ||
157 | ||
158 | ||
159 | static int set_sample_rate(struct echoaudio *chip, u32 rate) | |
160 | { | |
161 | u32 control_reg, clock, base_rate; | |
162 | ||
da3cec35 TI |
163 | if (snd_BUG_ON(rate >= 50000 && |
164 | chip->digital_mode == DIGITAL_MODE_ADAT)) | |
165 | return -EINVAL; | |
dd7b254d GP |
166 | |
167 | /* Only set the clock for internal mode. */ | |
168 | if (chip->input_clock != ECHO_CLOCK_INTERNAL) { | |
169 | DE_ACT(("set_sample_rate: Cannot set sample rate - " | |
170 | "clock not set to CLK_CLOCKININTERNAL\n")); | |
171 | /* Save the rate anyhow */ | |
172 | chip->comm_page->sample_rate = cpu_to_le32(rate); | |
173 | chip->sample_rate = rate; | |
174 | return 0; | |
175 | } | |
176 | ||
177 | /* Get the control register & clear the appropriate bits */ | |
178 | control_reg = le32_to_cpu(chip->comm_page->control_register); | |
179 | control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; | |
180 | ||
181 | clock = 0; | |
182 | ||
183 | switch (rate) { | |
184 | case 96000: | |
185 | clock = GML_96KHZ; | |
186 | break; | |
187 | case 88200: | |
188 | clock = GML_88KHZ; | |
189 | break; | |
190 | case 48000: | |
191 | clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; | |
192 | break; | |
193 | case 44100: | |
194 | clock = GML_44KHZ; | |
195 | /* Professional mode */ | |
196 | if (control_reg & GML_SPDIF_PRO_MODE) | |
197 | clock |= GML_SPDIF_SAMPLE_RATE0; | |
198 | break; | |
199 | case 32000: | |
200 | clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 | | |
201 | GML_SPDIF_SAMPLE_RATE1; | |
202 | break; | |
203 | case 22050: | |
204 | clock = GML_22KHZ; | |
205 | break; | |
206 | case 16000: | |
207 | clock = GML_16KHZ; | |
208 | break; | |
209 | case 11025: | |
210 | clock = GML_11KHZ; | |
211 | break; | |
212 | case 8000: | |
213 | clock = GML_8KHZ; | |
214 | break; | |
215 | default: | |
216 | /* If this is a non-standard rate, then the driver needs to | |
217 | use Layla24's special "continuous frequency" mode */ | |
218 | clock = LAYLA24_CONTINUOUS_CLOCK; | |
219 | if (rate > 50000) { | |
220 | base_rate = rate >> 1; | |
221 | control_reg |= GML_DOUBLE_SPEED_MODE; | |
222 | } else { | |
223 | base_rate = rate; | |
224 | } | |
225 | ||
226 | if (base_rate < 25000) | |
227 | base_rate = 25000; | |
228 | ||
229 | if (wait_handshake(chip)) | |
230 | return -EIO; | |
231 | ||
232 | chip->comm_page->sample_rate = | |
233 | cpu_to_le32(LAYLA24_MAGIC_NUMBER / base_rate - 2); | |
234 | ||
235 | clear_handshake(chip); | |
236 | send_vector(chip, DSP_VC_SET_LAYLA24_FREQUENCY_REG); | |
237 | } | |
238 | ||
239 | control_reg |= clock; | |
240 | ||
241 | chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP ? */ | |
242 | chip->sample_rate = rate; | |
243 | DE_ACT(("set_sample_rate: %d clock %d\n", rate, control_reg)); | |
244 | ||
245 | return write_control_reg(chip, control_reg, FALSE); | |
246 | } | |
247 | ||
248 | ||
249 | ||
250 | static int set_input_clock(struct echoaudio *chip, u16 clock) | |
251 | { | |
252 | u32 control_reg, clocks_from_dsp; | |
253 | ||
254 | /* Mask off the clock select bits */ | |
255 | control_reg = le32_to_cpu(chip->comm_page->control_register) & | |
256 | GML_CLOCK_CLEAR_MASK; | |
257 | clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); | |
258 | ||
259 | /* Pick the new clock */ | |
260 | switch (clock) { | |
261 | case ECHO_CLOCK_INTERNAL: | |
262 | DE_ACT(("Set Layla24 clock to INTERNAL\n")); | |
263 | chip->input_clock = ECHO_CLOCK_INTERNAL; | |
264 | return set_sample_rate(chip, chip->sample_rate); | |
265 | case ECHO_CLOCK_SPDIF: | |
266 | if (chip->digital_mode == DIGITAL_MODE_ADAT) | |
267 | return -EAGAIN; | |
268 | control_reg |= GML_SPDIF_CLOCK; | |
269 | /* Layla24 doesn't support 96KHz S/PDIF */ | |
270 | control_reg &= ~GML_DOUBLE_SPEED_MODE; | |
271 | DE_ACT(("Set Layla24 clock to SPDIF\n")); | |
272 | break; | |
273 | case ECHO_CLOCK_WORD: | |
274 | control_reg |= GML_WORD_CLOCK; | |
275 | if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96) | |
276 | control_reg |= GML_DOUBLE_SPEED_MODE; | |
277 | else | |
278 | control_reg &= ~GML_DOUBLE_SPEED_MODE; | |
279 | DE_ACT(("Set Layla24 clock to WORD\n")); | |
280 | break; | |
281 | case ECHO_CLOCK_ADAT: | |
282 | if (chip->digital_mode != DIGITAL_MODE_ADAT) | |
283 | return -EAGAIN; | |
284 | control_reg |= GML_ADAT_CLOCK; | |
285 | control_reg &= ~GML_DOUBLE_SPEED_MODE; | |
286 | DE_ACT(("Set Layla24 clock to ADAT\n")); | |
287 | break; | |
288 | default: | |
289 | DE_ACT(("Input clock 0x%x not supported for Layla24\n", clock)); | |
290 | return -EINVAL; | |
291 | } | |
292 | ||
293 | chip->input_clock = clock; | |
294 | return write_control_reg(chip, control_reg, TRUE); | |
295 | } | |
296 | ||
297 | ||
298 | ||
299 | /* Depending on what digital mode you want, Layla24 needs different ASICs | |
300 | loaded. This function checks the ASIC needed for the new mode and sees | |
301 | if it matches the one already loaded. */ | |
302 | static int switch_asic(struct echoaudio *chip, const struct firmware *asic) | |
303 | { | |
304 | s8 *monitors; | |
305 | ||
306 | /* Check to see if this is already loaded */ | |
307 | if (asic != chip->asic_code) { | |
52978be6 AD |
308 | monitors = kmemdup(chip->comm_page->monitors, |
309 | MONITOR_ARRAY_SIZE, GFP_KERNEL); | |
dd7b254d GP |
310 | if (! monitors) |
311 | return -ENOMEM; | |
312 | ||
dd7b254d GP |
313 | memset(chip->comm_page->monitors, ECHOGAIN_MUTED, |
314 | MONITOR_ARRAY_SIZE); | |
315 | ||
316 | /* Load the desired ASIC */ | |
317 | if (load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC, | |
318 | asic) < 0) { | |
319 | memcpy(chip->comm_page->monitors, monitors, | |
320 | MONITOR_ARRAY_SIZE); | |
321 | kfree(monitors); | |
322 | return -EIO; | |
323 | } | |
324 | chip->asic_code = asic; | |
325 | memcpy(chip->comm_page->monitors, monitors, MONITOR_ARRAY_SIZE); | |
326 | kfree(monitors); | |
327 | } | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | ||
333 | ||
334 | static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode) | |
335 | { | |
336 | u32 control_reg; | |
337 | int err, incompatible_clock; | |
338 | const struct firmware *asic; | |
339 | ||
340 | /* Set clock to "internal" if it's not compatible with the new mode */ | |
341 | incompatible_clock = FALSE; | |
342 | switch (mode) { | |
343 | case DIGITAL_MODE_SPDIF_OPTICAL: | |
344 | case DIGITAL_MODE_SPDIF_RCA: | |
345 | if (chip->input_clock == ECHO_CLOCK_ADAT) | |
346 | incompatible_clock = TRUE; | |
347 | asic = &card_fw[FW_LAYLA24_2S_ASIC]; | |
348 | break; | |
349 | case DIGITAL_MODE_ADAT: | |
350 | if (chip->input_clock == ECHO_CLOCK_SPDIF) | |
351 | incompatible_clock = TRUE; | |
352 | asic = &card_fw[FW_LAYLA24_2A_ASIC]; | |
353 | break; | |
354 | default: | |
355 | DE_ACT(("Digital mode not supported: %d\n", mode)); | |
356 | return -EINVAL; | |
357 | } | |
358 | ||
359 | if (incompatible_clock) { /* Switch to 48KHz, internal */ | |
360 | chip->sample_rate = 48000; | |
361 | spin_lock_irq(&chip->lock); | |
362 | set_input_clock(chip, ECHO_CLOCK_INTERNAL); | |
363 | spin_unlock_irq(&chip->lock); | |
364 | } | |
365 | ||
366 | /* switch_asic() can sleep */ | |
367 | if (switch_asic(chip, asic) < 0) | |
368 | return -EIO; | |
369 | ||
370 | spin_lock_irq(&chip->lock); | |
371 | ||
372 | /* Tweak the control register */ | |
373 | control_reg = le32_to_cpu(chip->comm_page->control_register); | |
374 | control_reg &= GML_DIGITAL_MODE_CLEAR_MASK; | |
375 | ||
376 | switch (mode) { | |
377 | case DIGITAL_MODE_SPDIF_OPTICAL: | |
378 | control_reg |= GML_SPDIF_OPTICAL_MODE; | |
379 | break; | |
380 | case DIGITAL_MODE_SPDIF_RCA: | |
381 | /* GML_SPDIF_OPTICAL_MODE bit cleared */ | |
382 | break; | |
383 | case DIGITAL_MODE_ADAT: | |
384 | control_reg |= GML_ADAT_MODE; | |
385 | control_reg &= ~GML_DOUBLE_SPEED_MODE; | |
386 | break; | |
387 | } | |
388 | ||
389 | err = write_control_reg(chip, control_reg, TRUE); | |
390 | spin_unlock_irq(&chip->lock); | |
391 | if (err < 0) | |
392 | return err; | |
393 | chip->digital_mode = mode; | |
394 | ||
395 | DE_ACT(("set_digital_mode to %d\n", mode)); | |
396 | return incompatible_clock; | |
397 | } |