[linux-2.6-block.git] / sound / pci / echoaudio / echoaudio_3g.c

/****************************************************************************

   Copyright Echo Digital Audio Corporation (c) 1998 - 2004
   All rights reserved
   www.echoaudio.com

   This file is part of Echo Digital Audio's generic driver library.

   Echo Digital Audio's generic driver library is free software;
   you can redistribute it and/or modify it under the terms of
   the GNU General Public License as published by the Free Software
   Foundation.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330, Boston,
   MA  02111-1307, USA.

   *************************************************************************

 Translation from C++ and adaptation for use in ALSA-Driver
 were made by Giuliano Pochini <pochini@shiny.it>

****************************************************************************/


/* These functions are common for all "3G" cards */


static int check_asic_status(struct echoaudio *chip)
{
	u32 box_status;

	if (wait_handshake(chip))
		return -EIO;

	chip->comm_page->ext_box_status =
		__constant_cpu_to_le32(E3G_ASIC_NOT_LOADED);
	chip->asic_loaded = FALSE;
	clear_handshake(chip);
	send_vector(chip, DSP_VC_TEST_ASIC);

	if (wait_handshake(chip)) {
		chip->dsp_code = NULL;
		return -EIO;
	}

	box_status = le32_to_cpu(chip->comm_page->ext_box_status);
	DE_INIT(("box_status=%x\n", box_status));
	if (box_status == E3G_ASIC_NOT_LOADED)
		return -ENODEV;

	chip->asic_loaded = TRUE;
	return box_status & E3G_BOX_TYPE_MASK;
}


static inline u32 get_frq_reg(struct echoaudio *chip)
{
	return le32_to_cpu(chip->comm_page->e3g_frq_register);
}


/* Most configuration of 3G cards is accomplished by writing the control
register. write_control_reg sends the new control register value to the DSP. */
static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq,
			     char force)
{
	if (wait_handshake(chip))
		return -EIO;

	DE_ACT(("WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq));

	ctl = cpu_to_le32(ctl);
	frq = cpu_to_le32(frq);

	if (ctl != chip->comm_page->control_register ||
	    frq != chip->comm_page->e3g_frq_register || force) {
		chip->comm_page->e3g_frq_register = frq;
		chip->comm_page->control_register = ctl;
		clear_handshake(chip);
		return send_vector(chip, DSP_VC_WRITE_CONTROL_REG);
	}

	DE_ACT(("WriteControlReg: not written, no change\n"));
	return 0;
}


/* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */
static int set_digital_mode(struct echoaudio *chip, u8 mode)
{
	u8 previous_mode;
	int err, i, o;

	/* All audio channels must be closed before changing the digital mode */
	if (snd_BUG_ON(chip->pipe_alloc_mask))
		return -EAGAIN;

	if (snd_BUG_ON(!(chip->digital_modes & (1 << mode))))
		return -EINVAL;

	previous_mode = chip->digital_mode;
	err = dsp_set_digital_mode(chip, mode);

	/* If we successfully changed the digital mode from or to ADAT,
	 * then make sure all output, input and monitor levels are
	 * updated by the DSP comm object. */
	if (err >= 0 && previous_mode != mode &&
	    (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) {
		spin_lock_irq(&chip->lock);
		for (o = 0; o < num_busses_out(chip); o++)
			for (i = 0; i < num_busses_in(chip); i++)
				set_monitor_gain(chip, o, i,
						 chip->monitor_gain[o][i]);

#ifdef ECHOCARD_HAS_INPUT_GAIN
		for (i = 0; i < num_busses_in(chip); i++)
			set_input_gain(chip, i, chip->input_gain[i]);
		update_input_line_level(chip);
#endif

		for (o = 0; o < num_busses_out(chip); o++)
			set_output_gain(chip, o, chip->output_gain[o]);
		update_output_line_level(chip);
		spin_unlock_irq(&chip->lock);
	}

	return err;
}


static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
{
	control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;

	switch (rate) {
	case 32000 :
		control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
		break;
	case 44100 :
		if (chip->professional_spdif)
			control_reg |= E3G_SPDIF_SAMPLE_RATE0;
		break;
	case 48000 :
		control_reg |= E3G_SPDIF_SAMPLE_RATE1;
		break;
	}

	if (chip->professional_spdif)
		control_reg |= E3G_SPDIF_PRO_MODE;

	if (chip->non_audio_spdif)
		control_reg |= E3G_SPDIF_NOT_AUDIO;

	control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
		E3G_SPDIF_COPY_PERMIT;

	return control_reg;
}


/* Set the S/PDIF output format */
static int set_professional_spdif(struct echoaudio *chip, char prof)
{
	u32 control_reg;

	control_reg = le32_to_cpu(chip->comm_page->control_register);
	chip->professional_spdif = prof;
	control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
	return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
}


/* detect_input_clocks() returns a bitmask consisting of all the input clocks
currently connected to the hardware; this changes as the user connects and
disconnects clock inputs. You should use this information to determine which
clocks the user is allowed to select. */
static u32 detect_input_clocks(const struct echoaudio *chip)
{
	u32 clocks_from_dsp, clock_bits;

	/* Map the DSP clock detect bits to the generic driver clock
	 * detect bits */
	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);

	clock_bits = ECHO_CLOCK_BIT_INTERNAL;

	if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD)
		clock_bits |= ECHO_CLOCK_BIT_WORD;

	switch(chip->digital_mode) {
	case DIGITAL_MODE_SPDIF_RCA:
	case DIGITAL_MODE_SPDIF_OPTICAL:
		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF)
			clock_bits |= ECHO_CLOCK_BIT_SPDIF;
		break;
	case DIGITAL_MODE_ADAT:
		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_ADAT)
			clock_bits |= ECHO_CLOCK_BIT_ADAT;
		break;
	}

	return clock_bits;
}


static int load_asic(struct echoaudio *chip)
{
	int box_type, err;

	if (chip->asic_loaded)
		return 0;

	/* Give the DSP a few milliseconds to settle down */
	mdelay(2);

	err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC,
				&card_fw[FW_3G_ASIC]);
	if (err < 0)
		return err;

	chip->asic_code = &card_fw[FW_3G_ASIC];

	/* Now give the new ASIC some time to set up */
	msleep(1000);
	/* See if it worked */
	box_type = check_asic_status(chip);

	/* Set up the control register if the load succeeded -
	 * 48 kHz, internal clock, S/PDIF RCA mode */
	if (box_type >= 0) {
		err = write_control_reg(chip, E3G_48KHZ,
					E3G_FREQ_REG_DEFAULT, TRUE);
		if (err < 0)
			return err;
	}

	return box_type;
}


static int set_sample_rate(struct echoaudio *chip, u32 rate)
{
	u32 control_reg, clock, base_rate, frq_reg;

	/* Only set the clock for internal mode. */
	if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
		DE_ACT(("set_sample_rate: Cannot set sample rate - "
			"clock not set to CLK_CLOCKININTERNAL\n"));
		/* Save the rate anyhow */
		chip->comm_page->sample_rate = cpu_to_le32(rate);
		chip->sample_rate = rate;
		set_input_clock(chip, chip->input_clock);
		return 0;
	}

	if (snd_BUG_ON(rate >= 50000 &&
		       chip->digital_mode == DIGITAL_MODE_ADAT))
		return -EINVAL;

	clock = 0;
	control_reg = le32_to_cpu(chip->comm_page->control_register);
	control_reg &= E3G_CLOCK_CLEAR_MASK;

	switch (rate) {
	case 96000:
		clock = E3G_96KHZ;
		break;
	case 88200:
		clock = E3G_88KHZ;
		break;
	case 48000:
		clock = E3G_48KHZ;
		break;
	case 44100:
		clock = E3G_44KHZ;
		break;
	case 32000:
		clock = E3G_32KHZ;
		break;
	default:
		clock = E3G_CONTINUOUS_CLOCK;
		if (rate > 50000)
			clock |= E3G_DOUBLE_SPEED_MODE;
		break;
	}

	control_reg |= clock;
	control_reg = set_spdif_bits(chip, control_reg, rate);

	base_rate = rate;
	if (base_rate > 50000)
		base_rate /= 2;
	if (base_rate < 32000)
		base_rate = 32000;

	frq_reg = E3G_MAGIC_NUMBER / base_rate - 2;
	if (frq_reg > E3G_FREQ_REG_MAX)
		frq_reg = E3G_FREQ_REG_MAX;

	chip->comm_page->sample_rate = cpu_to_le32(rate);	/* ignored by the DSP */
	chip->sample_rate = rate;
	DE_ACT(("SetSampleRate: %d clock %x\n", rate, control_reg));

	/* Tell the DSP about it - DSP reads both control reg & freq reg */
	return write_control_reg(chip, control_reg, frq_reg, 0);
}


/* Set the sample clock source to internal, S/PDIF, ADAT */
static int set_input_clock(struct echoaudio *chip, u16 clock)
{
	u32 control_reg, clocks_from_dsp;

	DE_ACT(("set_input_clock:\n"));

	/* Mask off the clock select bits */
	control_reg = le32_to_cpu(chip->comm_page->control_register) &
		E3G_CLOCK_CLEAR_MASK;
	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);

	switch (clock) {
	case ECHO_CLOCK_INTERNAL:
		DE_ACT(("Set Echo3G clock to INTERNAL\n"));
		chip->input_clock = ECHO_CLOCK_INTERNAL;
		return set_sample_rate(chip, chip->sample_rate);
	case ECHO_CLOCK_SPDIF:
		if (chip->digital_mode == DIGITAL_MODE_ADAT)
			return -EAGAIN;
		DE_ACT(("Set Echo3G clock to SPDIF\n"));
		control_reg |= E3G_SPDIF_CLOCK;
		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF96)
			control_reg |= E3G_DOUBLE_SPEED_MODE;
		else
			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
		break;
	case ECHO_CLOCK_ADAT:
		if (chip->digital_mode != DIGITAL_MODE_ADAT)
			return -EAGAIN;
		DE_ACT(("Set Echo3G clock to ADAT\n"));
		control_reg |= E3G_ADAT_CLOCK;
		control_reg &= ~E3G_DOUBLE_SPEED_MODE;
		break;
	case ECHO_CLOCK_WORD:
		DE_ACT(("Set Echo3G clock to WORD\n"));
		control_reg |= E3G_WORD_CLOCK;
		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD96)
			control_reg |= E3G_DOUBLE_SPEED_MODE;
		else
			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
		break;
	default:
		DE_ACT(("Input clock 0x%x not supported for Echo3G\n", clock));
		return -EINVAL;
	}

	chip->input_clock = clock;
	return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
}


static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
{
	u32 control_reg;
	int err, incompatible_clock;

	/* Set clock to "internal" if it's not compatible with the new mode */
	incompatible_clock = FALSE;
	switch (mode) {
	case DIGITAL_MODE_SPDIF_OPTICAL:
	case DIGITAL_MODE_SPDIF_RCA:
		if (chip->input_clock == ECHO_CLOCK_ADAT)
			incompatible_clock = TRUE;
		break;
	case DIGITAL_MODE_ADAT:
		if (chip->input_clock == ECHO_CLOCK_SPDIF)
			incompatible_clock = TRUE;
		break;
	default:
		DE_ACT(("Digital mode not supported: %d\n", mode));
		return -EINVAL;
	}

	spin_lock_irq(&chip->lock);

	if (incompatible_clock) {
		chip->sample_rate = 48000;
		set_input_clock(chip, ECHO_CLOCK_INTERNAL);
	}

	/* Clear the current digital mode */
	control_reg = le32_to_cpu(chip->comm_page->control_register);
	control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;

	/* Tweak the control reg */
	switch (mode) {
	case DIGITAL_MODE_SPDIF_OPTICAL:
		control_reg |= E3G_SPDIF_OPTICAL_MODE;
		break;
	case DIGITAL_MODE_SPDIF_RCA:
		/* E3G_SPDIF_OPTICAL_MODE bit cleared */
		break;
	case DIGITAL_MODE_ADAT:
		control_reg |= E3G_ADAT_MODE;
		control_reg &= ~E3G_DOUBLE_SPEED_MODE;	/* @@ useless */
		break;
	}

	err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
	spin_unlock_irq(&chip->lock);
	if (err < 0)
		return err;
	chip->digital_mode = mode;

	DE_ACT(("set_digital_mode(%d)\n", chip->digital_mode));
	return incompatible_clock;
}
Commit	Line	Data
dd7b254d GP	1	/****************************************************************************
	2
	3	Copyright Echo Digital Audio Corporation (c) 1998 - 2004
	4	All rights reserved
	5	www.echoaudio.com
	6
	7	This file is part of Echo Digital Audio's generic driver library.
	8
	9	Echo Digital Audio's generic driver library is free software;
	10	you can redistribute it and/or modify it under the terms of
	11	the GNU General Public License as published by the Free Software
	12	Foundation.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program; if not, write to the Free Software
	21	Foundation, Inc., 59 Temple Place - Suite 330, Boston,
	22	MA 02111-1307, USA.
	23
	24	*************************************************************************
	25
	26	Translation from C++ and adaptation for use in ALSA-Driver
	27	were made by Giuliano Pochini <pochini@shiny.it>
	28
	29	****************************************************************************/
	30
	31
	32
	33	/* These functions are common for all "3G" cards */
	34
	35
	36	static int check_asic_status(struct echoaudio *chip)
	37	{
	38	u32 box_status;
	39
	40	if (wait_handshake(chip))
	41	return -EIO;
	42
	43	chip->comm_page->ext_box_status =
	44	__constant_cpu_to_le32(E3G_ASIC_NOT_LOADED);
	45	chip->asic_loaded = FALSE;
	46	clear_handshake(chip);
	47	send_vector(chip, DSP_VC_TEST_ASIC);
	48
	49	if (wait_handshake(chip)) {
	50	chip->dsp_code = NULL;
	51	return -EIO;
	52	}
	53
	54	box_status = le32_to_cpu(chip->comm_page->ext_box_status);
	55	DE_INIT(("box_status=%x\n", box_status));
	56	if (box_status == E3G_ASIC_NOT_LOADED)
	57	return -ENODEV;
	58
	59	chip->asic_loaded = TRUE;
	60	return box_status & E3G_BOX_TYPE_MASK;
	61	}
	62
	63
	64
65	static inline u32 get_frq_reg(struct echoaudio *chip)
66	{
67	return le32_to_cpu(chip->comm_page->e3g_frq_register);
68	}
69
70
71
72	/* Most configuration of 3G cards is accomplished by writing the control
73	register. write_control_reg sends the new control register value to the DSP. */
74	static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq,
75	char force)
76	{
77	if (wait_handshake(chip))
78	return -EIO;
79
80	DE_ACT(("WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq));
81
82	ctl = cpu_to_le32(ctl);
83	frq = cpu_to_le32(frq);
84
85	if (ctl != chip->comm_page->control_register \|\|
86	frq != chip->comm_page->e3g_frq_register \|\| force) {
87	chip->comm_page->e3g_frq_register = frq;
88	chip->comm_page->control_register = ctl;
89	clear_handshake(chip);
90	return send_vector(chip, DSP_VC_WRITE_CONTROL_REG);
91	}
92
93	DE_ACT(("WriteControlReg: not written, no change\n"));
94	return 0;
95	}
96
97
98
99	/* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */
100	static int set_digital_mode(struct echoaudio *chip, u8 mode)
101	{
102	u8 previous_mode;
103	int err, i, o;
104
105	/* All audio channels must be closed before changing the digital mode */
da3cec35 TI	106	if (snd_BUG_ON(chip->pipe_alloc_mask))
da3cec35 TI	107	return -EAGAIN;
dd7b254d	108
da3cec35 TI	109	if (snd_BUG_ON(!(chip->digital_modes & (1 << mode))))
da3cec35 TI	110	return -EINVAL;
dd7b254d GP	111
	112	previous_mode = chip->digital_mode;
	113	err = dsp_set_digital_mode(chip, mode);
	114
	115	/* If we successfully changed the digital mode from or to ADAT,
	116	* then make sure all output, input and monitor levels are
	117	* updated by the DSP comm object. */
	118	if (err >= 0 && previous_mode != mode &&
	119	(previous_mode == DIGITAL_MODE_ADAT \|\| mode == DIGITAL_MODE_ADAT)) {
	120	spin_lock_irq(&chip->lock);
	121	for (o = 0; o < num_busses_out(chip); o++)
	122	for (i = 0; i < num_busses_in(chip); i++)
	123	set_monitor_gain(chip, o, i,
	124	chip->monitor_gain[o][i]);
	125
	126	#ifdef ECHOCARD_HAS_INPUT_GAIN
	127	for (i = 0; i < num_busses_in(chip); i++)
	128	set_input_gain(chip, i, chip->input_gain[i]);
	129	update_input_line_level(chip);
	130	#endif
	131
	132	for (o = 0; o < num_busses_out(chip); o++)
	133	set_output_gain(chip, o, chip->output_gain[o]);
	134	update_output_line_level(chip);
	135	spin_unlock_irq(&chip->lock);
	136	}
	137
	138	return err;
	139	}
	140
	141
	142
	143	static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
	144	{
	145	control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
	146
	147	switch (rate) {
	148	case 32000 :
	149	control_reg \|= E3G_SPDIF_SAMPLE_RATE0 \| E3G_SPDIF_SAMPLE_RATE1;
	150	break;
	151	case 44100 :
	152	if (chip->professional_spdif)
	153	control_reg \|= E3G_SPDIF_SAMPLE_RATE0;
	154	break;
	155	case 48000 :
	156	control_reg \|= E3G_SPDIF_SAMPLE_RATE1;
	157	break;
	158	}
	159
	160	if (chip->professional_spdif)
	161	control_reg \|= E3G_SPDIF_PRO_MODE;
	162
	163	if (chip->non_audio_spdif)
	164	control_reg \|= E3G_SPDIF_NOT_AUDIO;
	165
	166	control_reg \|= E3G_SPDIF_24_BIT \| E3G_SPDIF_TWO_CHANNEL \|
	167	E3G_SPDIF_COPY_PERMIT;
	168
	169	return control_reg;
	170	}
	171
	172
	173
	174	/* Set the S/PDIF output format */
175	static int set_professional_spdif(struct echoaudio *chip, char prof)
176	{
177	u32 control_reg;
178
179	control_reg = le32_to_cpu(chip->comm_page->control_register);
180	chip->professional_spdif = prof;
181	control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
182	return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
183	}
184
185
186
187	/* detect_input_clocks() returns a bitmask consisting of all the input clocks
188	currently connected to the hardware; this changes as the user connects and
189	disconnects clock inputs. You should use this information to determine which
190	clocks the user is allowed to select. */
191	static u32 detect_input_clocks(const struct echoaudio *chip)
192	{
193	u32 clocks_from_dsp, clock_bits;
194
195	/* Map the DSP clock detect bits to the generic driver clock
196	* detect bits */
197	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
198
199	clock_bits = ECHO_CLOCK_BIT_INTERNAL;
200
201	if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD)
202	clock_bits \|= ECHO_CLOCK_BIT_WORD;
203
204	switch(chip->digital_mode) {
205	case DIGITAL_MODE_SPDIF_RCA:
206	case DIGITAL_MODE_SPDIF_OPTICAL:
207	if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF)
208	clock_bits \|= ECHO_CLOCK_BIT_SPDIF;
209	break;
210	case DIGITAL_MODE_ADAT:
211	if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_ADAT)
212	clock_bits \|= ECHO_CLOCK_BIT_ADAT;
213	break;
214	}
215
216	return clock_bits;
217	}
218
219
220
221	static int load_asic(struct echoaudio *chip)
222	{
223	int box_type, err;
224
225	if (chip->asic_loaded)
226	return 0;
227
228	/* Give the DSP a few milliseconds to settle down */
229	mdelay(2);
230
231	err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC,
232	&card_fw[FW_3G_ASIC]);
233	if (err < 0)
234	return err;
235
236	chip->asic_code = &card_fw[FW_3G_ASIC];
237
59ae9d05 GP	238	/* Now give the new ASIC some time to set up */
59ae9d05 GP	239	msleep(1000);
dd7b254d GP	240	/* See if it worked */
	241	box_type = check_asic_status(chip);
	242
	243	/* Set up the control register if the load succeeded -
	244	* 48 kHz, internal clock, S/PDIF RCA mode */
	245	if (box_type >= 0) {
	246	err = write_control_reg(chip, E3G_48KHZ,
	247	E3G_FREQ_REG_DEFAULT, TRUE);
	248	if (err < 0)
	249	return err;
	250	}
	251
	252	return box_type;
	253	}
	254
	255
	256
	257	static int set_sample_rate(struct echoaudio *chip, u32 rate)
	258	{
	259	u32 control_reg, clock, base_rate, frq_reg;
	260
	261	/* Only set the clock for internal mode. */
	262	if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
	263	DE_ACT(("set_sample_rate: Cannot set sample rate - "
	264	"clock not set to CLK_CLOCKININTERNAL\n"));
	265	/* Save the rate anyhow */
	266	chip->comm_page->sample_rate = cpu_to_le32(rate);
	267	chip->sample_rate = rate;
	268	set_input_clock(chip, chip->input_clock);
	269	return 0;
	270	}
	271
da3cec35 TI	272	if (snd_BUG_ON(rate >= 50000 &&
	273	chip->digital_mode == DIGITAL_MODE_ADAT))
	274	return -EINVAL;
dd7b254d GP	275
	276	clock = 0;
	277	control_reg = le32_to_cpu(chip->comm_page->control_register);
	278	control_reg &= E3G_CLOCK_CLEAR_MASK;
	279
	280	switch (rate) {
	281	case 96000:
	282	clock = E3G_96KHZ;
	283	break;
	284	case 88200:
	285	clock = E3G_88KHZ;
	286	break;
	287	case 48000:
	288	clock = E3G_48KHZ;
	289	break;
	290	case 44100:
	291	clock = E3G_44KHZ;
	292	break;
	293	case 32000:
	294	clock = E3G_32KHZ;
	295	break;
	296	default:
	297	clock = E3G_CONTINUOUS_CLOCK;
	298	if (rate > 50000)
	299	clock \|= E3G_DOUBLE_SPEED_MODE;
	300	break;
	301	}
	302
	303	control_reg \|= clock;
	304	control_reg = set_spdif_bits(chip, control_reg, rate);
	305
	306	base_rate = rate;
	307	if (base_rate > 50000)
	308	base_rate /= 2;
	309	if (base_rate < 32000)
	310	base_rate = 32000;
	311
	312	frq_reg = E3G_MAGIC_NUMBER / base_rate - 2;
	313	if (frq_reg > E3G_FREQ_REG_MAX)
	314	frq_reg = E3G_FREQ_REG_MAX;
	315
	316	chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
	317	chip->sample_rate = rate;
	318	DE_ACT(("SetSampleRate: %d clock %x\n", rate, control_reg));
	319
	320	/* Tell the DSP about it - DSP reads both control reg & freq reg */
	321	return write_control_reg(chip, control_reg, frq_reg, 0);
	322	}
	323
	324
	325
	326	/* Set the sample clock source to internal, S/PDIF, ADAT */
	327	static int set_input_clock(struct echoaudio *chip, u16 clock)
	328	{
	329	u32 control_reg, clocks_from_dsp;
	330
	331	DE_ACT(("set_input_clock:\n"));
	332
	333	/* Mask off the clock select bits */
	334	control_reg = le32_to_cpu(chip->comm_page->control_register) &
	335	E3G_CLOCK_CLEAR_MASK;
	336	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
	337
	338	switch (clock) {
339	case ECHO_CLOCK_INTERNAL:
340	DE_ACT(("Set Echo3G clock to INTERNAL\n"));
341	chip->input_clock = ECHO_CLOCK_INTERNAL;
342	return set_sample_rate(chip, chip->sample_rate);
343	case ECHO_CLOCK_SPDIF:
344	if (chip->digital_mode == DIGITAL_MODE_ADAT)
345	return -EAGAIN;
346	DE_ACT(("Set Echo3G clock to SPDIF\n"));
347	control_reg \|= E3G_SPDIF_CLOCK;
348	if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF96)
349	control_reg \|= E3G_DOUBLE_SPEED_MODE;
350	else
351	control_reg &= ~E3G_DOUBLE_SPEED_MODE;
352	break;
353	case ECHO_CLOCK_ADAT:
354	if (chip->digital_mode != DIGITAL_MODE_ADAT)
355	return -EAGAIN;
356	DE_ACT(("Set Echo3G clock to ADAT\n"));
357	control_reg \|= E3G_ADAT_CLOCK;
358	control_reg &= ~E3G_DOUBLE_SPEED_MODE;
359	break;
360	case ECHO_CLOCK_WORD:
361	DE_ACT(("Set Echo3G clock to WORD\n"));
362	control_reg \|= E3G_WORD_CLOCK;
363	if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD96)
364	control_reg \|= E3G_DOUBLE_SPEED_MODE;
365	else
366	control_reg &= ~E3G_DOUBLE_SPEED_MODE;
367	break;
368	default:
369	DE_ACT(("Input clock 0x%x not supported for Echo3G\n", clock));
370	return -EINVAL;
371	}
372
373	chip->input_clock = clock;
374	return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
375	}
376
377
378
379	static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
380	{
381	u32 control_reg;
382	int err, incompatible_clock;
383
384	/* Set clock to "internal" if it's not compatible with the new mode */
385	incompatible_clock = FALSE;
386	switch (mode) {
387	case DIGITAL_MODE_SPDIF_OPTICAL:
388	case DIGITAL_MODE_SPDIF_RCA:
389	if (chip->input_clock == ECHO_CLOCK_ADAT)
390	incompatible_clock = TRUE;
391	break;
392	case DIGITAL_MODE_ADAT:
393	if (chip->input_clock == ECHO_CLOCK_SPDIF)
394	incompatible_clock = TRUE;
395	break;
396	default:
397	DE_ACT(("Digital mode not supported: %d\n", mode));
398	return -EINVAL;
399	}
400
401	spin_lock_irq(&chip->lock);
402
403	if (incompatible_clock) {
404	chip->sample_rate = 48000;
405	set_input_clock(chip, ECHO_CLOCK_INTERNAL);
406	}
407
408	/* Clear the current digital mode */
409	control_reg = le32_to_cpu(chip->comm_page->control_register);
410	control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
411
412	/* Tweak the control reg */
413	switch (mode) {
414	case DIGITAL_MODE_SPDIF_OPTICAL:
415	control_reg \|= E3G_SPDIF_OPTICAL_MODE;
416	break;
417	case DIGITAL_MODE_SPDIF_RCA:
418	/* E3G_SPDIF_OPTICAL_MODE bit cleared */
419	break;
420	case DIGITAL_MODE_ADAT:
421	control_reg \|= E3G_ADAT_MODE;
422	control_reg &= ~E3G_DOUBLE_SPEED_MODE; /* @@ useless */
423	break;
424	}
425
426	err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
427	spin_unlock_irq(&chip->lock);
428	if (err < 0)
429	return err;
430	chip->digital_mode = mode;
431
432	DE_ACT(("set_digital_mode(%d)\n", chip->digital_mode));
433	return incompatible_clock;
434	}