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ALSA: pci: Avoid non-standard macro usage
[linux-2.6-block.git] / sound / pci / cs46xx / cs46xx_lib.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 2/*
c1017a4c 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 4 * Abramo Bagnara <abramo@alsa-project.org>
5 * Cirrus Logic, Inc.
6 * Routines for control of Cirrus Logic CS461x chips
7 *
8 * KNOWN BUGS:
9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
10 * and the SPDIF get somewhat "distorcionated", or/and left right channel
11 * are swapped. To get around this problem when it happens, mute and unmute
561de31a 12 * the SPDIF input mixer control.
1da177e4
LT		 13 * - On the Hercules Game Theater XP the amplifier are sometimes turned
14 * off on inadecuate moments which causes distorcions on sound.
15 *
16 * TODO:
17 * - Secondary CODEC on some soundcards
18 * - SPDIF input support for other sample rates then 48khz
19 * - Posibility to mix the SPDIF output with analog sources.
20 * - PCM channels for Center and LFE on secondary codec
21 *
22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
23 * is default configuration), no SPDIF, no secondary codec, no
24 * multi channel PCM. But known to work.
25 *
26 * FINALLY: A credit to the developers Tom and Jordan
27 * at Cirrus for have helping me out with the DSP, however we
28 * still don't have sufficient documentation and technical
29 * references to be able to implement all fancy feutures
30 * supported by the cs46xx DSP's.
31 * Benny <benny@hostmobility.com>
1da177e4
LT		 32 */
33
1da177e4
LT		 34#include <linux/delay.h>
35#include <linux/pci.h>
36#include <linux/pm.h>
37#include <linux/init.h>
38#include <linux/interrupt.h>
39#include <linux/slab.h>
40#include <linux/gameport.h>
62932df8 41#include <linux/mutex.h>
d81a6d71 42#include <linux/export.h>
ad233a5f
TI		 43#include <linux/module.h>
44#include <linux/firmware.h>
45#include <linux/vmalloc.h>
6cbbfe1c 46#include <linux/io.h>
1da177e4
LT		 47
48#include <sound/core.h>
49#include <sound/control.h>
50#include <sound/info.h>
51#include <sound/pcm.h>
52#include <sound/pcm_params.h>
81fcb170 53#include "cs46xx.h"
1da177e4 54
1da177e4
LT		 55#include "cs46xx_lib.h"
56#include "dsp_spos.h"
57
3d19f804 58static void amp_voyetra(struct snd_cs46xx *chip, int change);
1da177e4
LT		 59
60#ifdef CONFIG_SND_CS46XX_NEW_DSP
a6f9dec2
BG		 61static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
62static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
63static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
64static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
65static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
66static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
1da177e4
LT		 67#endif
68
a6f9dec2
BG		 69static const struct snd_pcm_ops snd_cs46xx_playback_ops;
70static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
71static const struct snd_pcm_ops snd_cs46xx_capture_ops;
72static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
1da177e4 73
3d19f804 74static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
1da177e4
LT		 75 unsigned short reg,
76 int codec_index)
77{
78 int count;
79 unsigned short result,tmp;
80 u32 offset = 0;
da3cec35
TI		 81
82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
83 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
de64c0ee 84 return 0xffff;
1da177e4
LT		 85
86 chip->active_ctrl(chip, 1);
87
88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
89 offset = CS46XX_SECONDARY_CODEC_OFFSET;
90
91 /*
92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
96 * 5. if DCV not cleared, break and return error
97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
98 */
99
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
101
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
2b96a7f1 104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
1da177e4
LT		 105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
106 msleep(50);
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
109
110 }
111
112 /*
113 * Setup the AC97 control registers on the CS461x to send the
114 * appropriate command to the AC97 to perform the read.
115 * ACCAD = Command Address Register = 46Ch
116 * ACCDA = Command Data Register = 470h
117 * ACCTL = Control Register = 460h
118 * set DCV - will clear when process completed
119 * set CRW - Read command
120 * set VFRM - valid frame enabled
121 * set ESYN - ASYNC generation enabled
122 * set RSTN - ARST# inactive, AC97 codec not reset
123 */
124
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
129 ACCTL_VFRM | ACCTL_ESYN |
130 ACCTL_RSTN);
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
132 ACCTL_VFRM | ACCTL_ESYN |
133 ACCTL_RSTN);
134 } else {
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
137 ACCTL_RSTN);
138 }
139
140 /*
141 * Wait for the read to occur.
142 */
143 for (count = 0; count < 1000; count++) {
144 /*
145 * First, we want to wait for a short time.
146 */
147 udelay(10);
148 /*
149 * Now, check to see if the read has completed.
150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
151 */
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
153 goto ok1;
154 }
155
2b96a7f1
TI		 156 dev_err(chip->card->dev,
157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
1da177e4
LT		 158 result = 0xffff;
159 goto end;
160
161 ok1:
162 /*
163 * Wait for the valid status bit to go active.
164 */
165 for (count = 0; count < 100; count++) {
166 /*
167 * Read the AC97 status register.
168 * ACSTS = Status Register = 464h
169 * VSTS - Valid Status
170 */
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
172 goto ok2;
173 udelay(10);
174 }
175
2b96a7f1
TI		 176 dev_err(chip->card->dev,
177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
178 codec_index, reg);
1da177e4
LT		 179 result = 0xffff;
180 goto end;
181
182 ok2:
183 /*
184 * Read the data returned from the AC97 register.
185 * ACSDA = Status Data Register = 474h
186 */
187#if 0
2b96a7f1
TI		 188 dev_dbg(chip->card->dev,
189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
1da177e4
LT		 190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
192#endif
193
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
196 end:
197 chip->active_ctrl(chip, -1);
198 return result;
199}
200
3d19f804 201static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
1da177e4
LT		 202 unsigned short reg)
203{
3d19f804 204 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 205 unsigned short val;
206 int codec_index = ac97->num;
207
da3cec35
TI		 208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
209 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
210 return 0xffff;
1da177e4
LT		 211
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
213
214 return val;
215}
216
217
3d19f804 218static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
1da177e4
LT		 219 unsigned short reg,
220 unsigned short val,
221 int codec_index)
222{
223 int count;
224
da3cec35
TI		 225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
226 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
227 return;
1da177e4
LT		 228
229 chip->active_ctrl(chip, 1);
230
231 /*
232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
234 * 3. Write ACCTL = Control Register = 460h for initiating the write
235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
236 * 5. if DCV not cleared, break and return error
237 */
238
239 /*
240 * Setup the AC97 control registers on the CS461x to send the
241 * appropriate command to the AC97 to perform the read.
242 * ACCAD = Command Address Register = 46Ch
243 * ACCDA = Command Data Register = 470h
244 * ACCTL = Control Register = 460h
245 * set DCV - will clear when process completed
246 * reset CRW - Write command
247 * set VFRM - valid frame enabled
248 * set ESYN - ASYNC generation enabled
249 * set RSTN - ARST# inactive, AC97 codec not reset
250 */
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
254
255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
257 ACCTL_ESYN | ACCTL_RSTN);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
259 ACCTL_ESYN | ACCTL_RSTN);
260 } else {
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
263 }
264
265 for (count = 0; count < 4000; count++) {
266 /*
267 * First, we want to wait for a short time.
268 */
269 udelay(10);
270 /*
271 * Now, check to see if the write has completed.
272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
273 */
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
275 goto end;
276 }
277 }
2b96a7f1
TI		 278 dev_err(chip->card->dev,
279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
280 codec_index, reg, val);
1da177e4
LT		 281 end:
282 chip->active_ctrl(chip, -1);
283}
284
3d19f804 285static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 286 unsigned short reg,
287 unsigned short val)
288{
3d19f804 289 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 290 int codec_index = ac97->num;
291
da3cec35
TI		 292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
293 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
294 return;
1da177e4
LT		 295
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
297}
298
299
300/*
301 * Chip initialization
302 */
303
3d19f804 304int snd_cs46xx_download(struct snd_cs46xx *chip,
1da177e4
LT		 305 u32 *src,
306 unsigned long offset,
307 unsigned long len)
308{
309 void __iomem *dst;
310 unsigned int bank = offset >> 16;
311 offset = offset & 0xffff;
312
da3cec35
TI		 313 if (snd_BUG_ON((offset & 3) || (len & 3)))
314 return -EINVAL;
1da177e4
LT		 315 dst = chip->region.idx[bank+1].remap_addr + offset;
316 len /= sizeof(u32);
317
318 /* writel already converts 32-bit value to right endianess */
319 while (len-- > 0) {
320 writel(*src++, dst);
321 dst += sizeof(u32);
322 }
323 return 0;
324}
325
ad233a5f
TI		 326static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
327{
328#ifdef __LITTLE_ENDIAN
329 memcpy(dst, src, len);
330#else
331 u32 *_dst = dst;
332 const __le32 *_src = src;
333 len /= 4;
334 while (len-- > 0)
335 *_dst++ = le32_to_cpu(*_src++);
336#endif
337}
338
1da177e4
LT		 339#ifdef CONFIG_SND_CS46XX_NEW_DSP
340
ad233a5f
TI		 341static const char *module_names[CS46XX_DSP_MODULES] = {
342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
343};
344
345MODULE_FIRMWARE("cs46xx/cwc4630");
346MODULE_FIRMWARE("cs46xx/cwcasync");
347MODULE_FIRMWARE("cs46xx/cwcsnoop");
348MODULE_FIRMWARE("cs46xx/cwcbinhack");
349MODULE_FIRMWARE("cs46xx/cwcdma");
350
351static void free_module_desc(struct dsp_module_desc *module)
352{
353 if (!module)
354 return;
355 kfree(module->module_name);
356 kfree(module->symbol_table.symbols);
357 if (module->segments) {
358 int i;
359 for (i = 0; i < module->nsegments; i++)
360 kfree(module->segments[i].data);
361 kfree(module->segments);
362 }
b75b1518 363 kfree(module);
ad233a5f
TI		 364}
365
366/* firmware binary format:
367 * le32 nsymbols;
368 * struct {
369 * le32 address;
370 * char symbol_name[DSP_MAX_SYMBOL_NAME];
371 * le32 symbol_type;
372 * } symbols[nsymbols];
373 * le32 nsegments;
374 * struct {
375 * le32 segment_type;
376 * le32 offset;
377 * le32 size;
378 * le32 data[size];
379 * } segments[nsegments];
380 */
381
382static int load_firmware(struct snd_cs46xx *chip,
383 struct dsp_module_desc **module_ret,
384 const char *fw_name)
385{
386 int i, err;
387 unsigned int nums, fwlen, fwsize;
388 const __le32 *fwdat;
389 struct dsp_module_desc *module = NULL;
390 const struct firmware *fw;
391 char fw_path[32];
392
393 sprintf(fw_path, "cs46xx/%s", fw_name);
394 err = request_firmware(&fw, fw_path, &chip->pci->dev);
395 if (err < 0)
396 return err;
397 fwsize = fw->size / 4;
398 if (fwsize < 2) {
399 err = -EINVAL;
400 goto error;
401 }
402
403 err = -ENOMEM;
404 module = kzalloc(sizeof(*module), GFP_KERNEL);
405 if (!module)
406 goto error;
407 module->module_name = kstrdup(fw_name, GFP_KERNEL);
408 if (!module->module_name)
409 goto error;
410
411 fwlen = 0;
412 fwdat = (const __le32 *)fw->data;
413 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
414 if (nums >= 40)
415 goto error_inval;
416 module->symbol_table.symbols =
417 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
418 if (!module->symbol_table.symbols)
419 goto error;
420 for (i = 0; i < nums; i++) {
421 struct dsp_symbol_entry *entry =
422 &module->symbol_table.symbols[i];
423 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
424 goto error_inval;
425 entry->address = le32_to_cpu(fwdat[fwlen++]);
426 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
427 fwlen += DSP_MAX_SYMBOL_NAME / 4;
428 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
429 }
430
431 if (fwlen >= fwsize)
432 goto error_inval;
433 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
434 if (nums > 10)
435 goto error_inval;
436 module->segments =
437 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
438 if (!module->segments)
439 goto error;
440 for (i = 0; i < nums; i++) {
441 struct dsp_segment_desc *entry = &module->segments[i];
442 if (fwlen + 3 > fwsize)
443 goto error_inval;
444 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
445 entry->offset = le32_to_cpu(fwdat[fwlen++]);
446 entry->size = le32_to_cpu(fwdat[fwlen++]);
447 if (fwlen + entry->size > fwsize)
448 goto error_inval;
6da2ec56 449 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
ad233a5f
TI		 450 if (!entry->data)
451 goto error;
452 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
453 fwlen += entry->size;
454 }
455
456 *module_ret = module;
457 release_firmware(fw);
458 return 0;
459
460 error_inval:
461 err = -EINVAL;
462 error:
463 free_module_desc(module);
464 release_firmware(fw);
465 return err;
466}
1da177e4 467
3d19f804 468int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
1da177e4
LT		 469 unsigned long offset,
470 unsigned long len)
471{
472 void __iomem *dst;
473 unsigned int bank = offset >> 16;
474 offset = offset & 0xffff;
475
da3cec35
TI		 476 if (snd_BUG_ON((offset & 3) || (len & 3)))
477 return -EINVAL;
1da177e4
LT		 478 dst = chip->region.idx[bank+1].remap_addr + offset;
479 len /= sizeof(u32);
480
481 /* writel already converts 32-bit value to right endianess */
482 while (len-- > 0) {
483 writel(0, dst);
484 dst += sizeof(u32);
485 }
486 return 0;
487}
488
489#else /* old DSP image */
490
ad233a5f
TI		 491struct ba1_struct {
492 struct {
493 u32 offset;
494 u32 size;
495 } memory[BA1_MEMORY_COUNT];
496 u32 map[BA1_DWORD_SIZE];
497};
498
499MODULE_FIRMWARE("cs46xx/ba1");
500
501static int load_firmware(struct snd_cs46xx *chip)
502{
503 const struct firmware *fw;
504 int i, size, err;
505
506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
507 if (err < 0)
508 return err;
509 if (fw->size != sizeof(*chip->ba1)) {
510 err = -EINVAL;
511 goto error;
512 }
513
514 chip->ba1 = vmalloc(sizeof(*chip->ba1));
515 if (!chip->ba1) {
516 err = -ENOMEM;
517 goto error;
518 }
519
520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
521
522 /* sanity check */
523 size = 0;
524 for (i = 0; i < BA1_MEMORY_COUNT; i++)
525 size += chip->ba1->memory[i].size;
526 if (size > BA1_DWORD_SIZE * 4)
527 err = -EINVAL;
528
529 error:
530 release_firmware(fw);
531 return err;
532}
1da177e4 533
3d19f804 534int snd_cs46xx_download_image(struct snd_cs46xx *chip)
1da177e4
LT		 535{
536 int idx, err;
ad233a5f
TI		 537 unsigned int offset = 0;
538 struct ba1_struct *ba1 = chip->ba1;
1da177e4
LT		 539
540 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
ad233a5f
TI		 541 err = snd_cs46xx_download(chip,
542 &ba1->map[offset],
543 ba1->memory[idx].offset,
544 ba1->memory[idx].size);
545 if (err < 0)
1da177e4 546 return err;
ad233a5f 547 offset += ba1->memory[idx].size >> 2;
1da177e4
LT		 548 }
549 return 0;
550}
551#endif /* CONFIG_SND_CS46XX_NEW_DSP */
552
553/*
554 * Chip reset
555 */
556
3d19f804 557static void snd_cs46xx_reset(struct snd_cs46xx *chip)
1da177e4
LT		 558{
559 int idx;
560
561 /*
562 * Write the reset bit of the SP control register.
563 */
564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
565
566 /*
567 * Write the control register.
568 */
569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
570
571 /*
572 * Clear the trap registers.
573 */
574 for (idx = 0; idx < 8; idx++) {
575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
577 }
578 snd_cs46xx_poke(chip, BA1_DREG, 0);
579
580 /*
581 * Set the frame timer to reflect the number of cycles per frame.
582 */
583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
584}
585
3d19f804 586static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
1da177e4
LT		 587{
588 u32 i, status = 0;
589 /*
590 * Make sure the previous FIFO write operation has completed.
591 */
592 for(i = 0; i < 50; i++){
593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
594
595 if( !(status & SERBST_WBSY) )
596 break;
597
598 mdelay(retry_timeout);
599 }
600
601 if(status & SERBST_WBSY) {
2b96a7f1
TI		 602 dev_err(chip->card->dev,
603 "failure waiting for FIFO command to complete\n");
1da177e4
LT		 604 return -EINVAL;
605 }
606
607 return 0;
608}
609
3d19f804 610static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
1da177e4
LT		 611{
612 int idx, powerdown = 0;
613 unsigned int tmp;
614
615 /*
616 * See if the devices are powered down. If so, we must power them up first
617 * or they will not respond.
618 */
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
620 if (!(tmp & CLKCR1_SWCE)) {
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
622 powerdown = 1;
623 }
624
625 /*
626 * We want to clear out the serial port FIFOs so we don't end up playing
627 * whatever random garbage happens to be in them. We fill the sample FIFOS
628 * with zero (silence).
629 */
630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
631
632 /*
633 * Fill all 256 sample FIFO locations.
634 */
635 for (idx = 0; idx < 0xFF; idx++) {
636 /*
637 * Make sure the previous FIFO write operation has completed.
638 */
639 if (cs46xx_wait_for_fifo(chip,1)) {
2b96a7f1
TI		 640 dev_dbg(chip->card->dev,
641 "failed waiting for FIFO at addr (%02X)\n",
642 idx);
1da177e4
LT		 643
644 if (powerdown)
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
646
647 break;
648 }
649 /*
650 * Write the serial port FIFO index.
651 */
652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
653 /*
654 * Tell the serial port to load the new value into the FIFO location.
655 */
656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
657 }
658 /*
659 * Now, if we powered up the devices, then power them back down again.
660 * This is kinda ugly, but should never happen.
661 */
662 if (powerdown)
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
664}
665
3d19f804 666static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
1da177e4
LT		 667{
668 int cnt;
669
670 /*
671 * Set the frame timer to reflect the number of cycles per frame.
672 */
673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
674 /*
675 * Turn on the run, run at frame, and DMA enable bits in the local copy of
676 * the SP control register.
677 */
678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
679 /*
680 * Wait until the run at frame bit resets itself in the SP control
681 * register.
682 */
683 for (cnt = 0; cnt < 25; cnt++) {
684 udelay(50);
685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
686 break;
687 }
688
689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
2b96a7f1 690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
1da177e4
LT		 691}
692
3d19f804 693static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
1da177e4
LT		 694{
695 /*
696 * Turn off the run, run at frame, and DMA enable bits in the local copy of
697 * the SP control register.
698 */
699 snd_cs46xx_poke(chip, BA1_SPCR, 0);
700}
701
702/*
703 * Sample rate routines
704 */
705
706#define GOF_PER_SEC 200
707
3d19f804 708static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
1da177e4
LT		 709{
710 unsigned long flags;
711 unsigned int tmp1, tmp2;
712 unsigned int phiIncr;
713 unsigned int correctionPerGOF, correctionPerSec;
714
715 /*
716 * Compute the values used to drive the actual sample rate conversion.
717 * The following formulas are being computed, using inline assembly
718 * since we need to use 64 bit arithmetic to compute the values:
719 *
720 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
721 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
722 * GOF_PER_SEC)
723 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
724 * GOF_PER_SEC * correctionPerGOF
725 *
726 * i.e.
727 *
728 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
729 * correctionPerGOF:correctionPerSec =
730 * dividend:remainder(ulOther / GOF_PER_SEC)
731 */
732 tmp1 = rate << 16;
733 phiIncr = tmp1 / 48000;
734 tmp1 -= phiIncr * 48000;
735 tmp1 <<= 10;
736 phiIncr <<= 10;
737 tmp2 = tmp1 / 48000;
738 phiIncr += tmp2;
739 tmp1 -= tmp2 * 48000;
740 correctionPerGOF = tmp1 / GOF_PER_SEC;
741 tmp1 -= correctionPerGOF * GOF_PER_SEC;
742 correctionPerSec = tmp1;
743
744 /*
745 * Fill in the SampleRateConverter control block.
746 */
747 spin_lock_irqsave(&chip->reg_lock, flags);
748 snd_cs46xx_poke(chip, BA1_PSRC,
749 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
750 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
752}
753
3d19f804 754static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
1da177e4
LT		 755{
756 unsigned long flags;
757 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
758 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
759 unsigned int frameGroupLength, cnt;
760
761 /*
762 * We can only decimate by up to a factor of 1/9th the hardware rate.
763 * Correct the value if an attempt is made to stray outside that limit.
764 */
765 if ((rate * 9) < 48000)
766 rate = 48000 / 9;
767
768 /*
769 * We can not capture at at rate greater than the Input Rate (48000).
770 * Return an error if an attempt is made to stray outside that limit.
771 */
772 if (rate > 48000)
773 rate = 48000;
774
775 /*
776 * Compute the values used to drive the actual sample rate conversion.
777 * The following formulas are being computed, using inline assembly
778 * since we need to use 64 bit arithmetic to compute the values:
779 *
780 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
781 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
782 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
783 * GOF_PER_SEC)
784 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
785 * GOF_PER_SEC * correctionPerGOF
786 * initialDelay = ceil((24 * Fs,in) / Fs,out)
787 *
788 * i.e.
789 *
790 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
791 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
792 * correctionPerGOF:correctionPerSec =
793 * dividend:remainder(ulOther / GOF_PER_SEC)
794 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
795 */
796
797 tmp1 = rate << 16;
798 coeffIncr = tmp1 / 48000;
799 tmp1 -= coeffIncr * 48000;
800 tmp1 <<= 7;
801 coeffIncr <<= 7;
802 coeffIncr += tmp1 / 48000;
803 coeffIncr ^= 0xFFFFFFFF;
804 coeffIncr++;
805 tmp1 = 48000 << 16;
806 phiIncr = tmp1 / rate;
807 tmp1 -= phiIncr * rate;
808 tmp1 <<= 10;
809 phiIncr <<= 10;
810 tmp2 = tmp1 / rate;
811 phiIncr += tmp2;
812 tmp1 -= tmp2 * rate;
813 correctionPerGOF = tmp1 / GOF_PER_SEC;
814 tmp1 -= correctionPerGOF * GOF_PER_SEC;
815 correctionPerSec = tmp1;
816 initialDelay = ((48000 * 24) + rate - 1) / rate;
817
818 /*
819 * Fill in the VariDecimate control block.
820 */
821 spin_lock_irqsave(&chip->reg_lock, flags);
822 snd_cs46xx_poke(chip, BA1_CSRC,
823 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
824 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
825 snd_cs46xx_poke(chip, BA1_CD,
826 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
827 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
829
830 /*
831 * Figure out the frame group length for the write back task. Basically,
832 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
833 * the output sample rate.
834 */
835 frameGroupLength = 1;
836 for (cnt = 2; cnt <= 64; cnt *= 2) {
837 if (((rate / cnt) * cnt) != rate)
838 frameGroupLength *= 2;
839 }
840 if (((rate / 3) * 3) != rate) {
841 frameGroupLength *= 3;
842 }
843 for (cnt = 5; cnt <= 125; cnt *= 5) {
844 if (((rate / cnt) * cnt) != rate)
845 frameGroupLength *= 5;
846 }
847
848 /*
849 * Fill in the WriteBack control block.
850 */
851 spin_lock_irqsave(&chip->reg_lock, flags);
852 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
853 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
854 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
855 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
856 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
857 spin_unlock_irqrestore(&chip->reg_lock, flags);
858}
859
860/*
861 * PCM part
862 */
863
3d19f804
TI		 864static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
865 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 866{
3d19f804
TI		 867 struct snd_pcm_runtime *runtime = substream->runtime;
868 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
1da177e4
LT		 869 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
870}
871
3d19f804 872static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
1da177e4 873{
3d19f804
TI		 874 struct snd_pcm_runtime *runtime = substream->runtime;
875 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
cebf6bfe
TI		 876 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
877 snd_cs46xx_pb_trans_copy);
1da177e4
LT		 878}
879
3d19f804
TI		 880static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
881 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 882{
3d19f804
TI		 883 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
884 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 885 memcpy(runtime->dma_area + rec->sw_data,
886 chip->capt.hw_buf.area + rec->hw_data, bytes);
887}
888
3d19f804 889static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
1da177e4 890{
3d19f804 891 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
cebf6bfe
TI		 892 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
893 snd_cs46xx_cp_trans_copy);
1da177e4
LT		 894}
895
3d19f804 896static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
1da177e4 897{
3d19f804 898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 899 size_t ptr;
3d19f804 900 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
da3cec35
TI		 901
902 if (snd_BUG_ON(!cpcm->pcm_channel))
903 return -ENXIO;
1da177e4
LT		 904
905#ifdef CONFIG_SND_CS46XX_NEW_DSP
906 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
907#else
908 ptr = snd_cs46xx_peek(chip, BA1_PBA);
909#endif
910 ptr -= cpcm->hw_buf.addr;
911 return ptr >> cpcm->shift;
912}
913
3d19f804 914static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
1da177e4 915{
3d19f804 916 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 917 size_t ptr;
3d19f804 918 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 919
920#ifdef CONFIG_SND_CS46XX_NEW_DSP
da3cec35
TI		 921 if (snd_BUG_ON(!cpcm->pcm_channel))
922 return -ENXIO;
1da177e4
LT		 923 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
924#else
925 ptr = snd_cs46xx_peek(chip, BA1_PBA);
926#endif
927 ptr -= cpcm->hw_buf.addr;
928 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
929}
930
3d19f804 931static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
1da177e4 932{
3d19f804 933 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 934 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
935 return ptr >> chip->capt.shift;
936}
937
3d19f804 938static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
1da177e4 939{
3d19f804 940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
942 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
943}
944
3d19f804 945static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 946 int cmd)
947{
3d19f804
TI		 948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
949 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
1da177e4
LT		 950 int result = 0;
951
952#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 953 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 954 if (! cpcm->pcm_channel) {
955 return -ENXIO;
956 }
957#endif
958 switch (cmd) {
959 case SNDRV_PCM_TRIGGER_START:
960 case SNDRV_PCM_TRIGGER_RESUME:
961#ifdef CONFIG_SND_CS46XX_NEW_DSP
962 /* magic value to unmute PCM stream playback volume */
963 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
964 SCBVolumeCtrl) << 2, 0x80008000);
965
966 if (cpcm->pcm_channel->unlinked)
967 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
968
969 if (substream->runtime->periods != CS46XX_FRAGS)
970 snd_cs46xx_playback_transfer(substream);
971#else
972 spin_lock(&chip->reg_lock);
973 if (substream->runtime->periods != CS46XX_FRAGS)
974 snd_cs46xx_playback_transfer(substream);
975 { unsigned int tmp;
976 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
977 tmp &= 0x0000ffff;
978 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
979 }
980 spin_unlock(&chip->reg_lock);
981#endif
982 break;
983 case SNDRV_PCM_TRIGGER_STOP:
984 case SNDRV_PCM_TRIGGER_SUSPEND:
985#ifdef CONFIG_SND_CS46XX_NEW_DSP
986 /* magic mute channel */
987 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
988 SCBVolumeCtrl) << 2, 0xffffffff);
989
990 if (!cpcm->pcm_channel->unlinked)
991 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
992#else
993 spin_lock(&chip->reg_lock);
994 { unsigned int tmp;
995 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
996 tmp &= 0x0000ffff;
997 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
998 }
999 spin_unlock(&chip->reg_lock);
1000#endif
1001 break;
1002 default:
1003 result = -EINVAL;
1004 break;
1005 }
1006
1007 return result;
1008}
1009
3d19f804 1010static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1011 int cmd)
1012{
3d19f804 1013 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1014 unsigned int tmp;
1015 int result = 0;
1016
1017 spin_lock(&chip->reg_lock);
1018 switch (cmd) {
1019 case SNDRV_PCM_TRIGGER_START:
1020 case SNDRV_PCM_TRIGGER_RESUME:
1021 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1022 tmp &= 0xffff0000;
1023 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1024 break;
1025 case SNDRV_PCM_TRIGGER_STOP:
1026 case SNDRV_PCM_TRIGGER_SUSPEND:
1027 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1028 tmp &= 0xffff0000;
1029 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1030 break;
1031 default:
1032 result = -EINVAL;
1033 break;
1034 }
1035 spin_unlock(&chip->reg_lock);
1036
1037 return result;
1038}
1039
1040#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1041static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1da177e4
LT		 1042 int sample_rate)
1043{
1044
1045 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1046 if ( cpcm->pcm_channel == NULL) {
1047 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1048 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1049 if (cpcm->pcm_channel == NULL) {
2b96a7f1
TI		 1050 dev_err(chip->card->dev,
1051 "failed to create virtual PCM channel\n");
1da177e4
LT		 1052 return -ENOMEM;
1053 }
1054 cpcm->pcm_channel->sample_rate = sample_rate;
1055 } else
1056 /* if sample rate is changed */
1057 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1058 int unlinked = cpcm->pcm_channel->unlinked;
1059 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1060
1061 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
1062 cpcm->hw_buf.addr,
1063 cpcm->pcm_channel_id)) == NULL) {
2b96a7f1
TI		 1064 dev_err(chip->card->dev,
1065 "failed to re-create virtual PCM channel\n");
1da177e4
LT		 1066 return -ENOMEM;
1067 }
1068
1069 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1070 cpcm->pcm_channel->sample_rate = sample_rate;
1071 }
1072
1073 return 0;
1074}
1075#endif
1076
1077
3d19f804
TI		 1078static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1079 struct snd_pcm_hw_params *hw_params)
1da177e4 1080{
3d19f804
TI		 1081 struct snd_pcm_runtime *runtime = substream->runtime;
1082 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1083 int err;
1084#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1085 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1086 int sample_rate = params_rate(hw_params);
1087 int period_size = params_period_bytes(hw_params);
1088#endif
1089 cpcm = runtime->private_data;
1090
1091#ifdef CONFIG_SND_CS46XX_NEW_DSP
da3cec35
TI		 1092 if (snd_BUG_ON(!sample_rate))
1093 return -ENXIO;
1da177e4 1094
62932df8 1095 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1096
1097 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
62932df8 1098 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1099 return -ENXIO;
1100 }
1101
da3cec35 1102 snd_BUG_ON(!cpcm->pcm_channel);
1da177e4 1103 if (!cpcm->pcm_channel) {
62932df8 1104 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1105 return -ENXIO;
1106 }
1107
1108
1109 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
62932df8 1110 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1111 return -EINVAL;
1112 }
1113
2b96a7f1
TI		 1114 dev_dbg(chip->card->dev,
1115 "period_size (%d), periods (%d) buffer_size(%d)\n",
1da177e4
LT		 1116 period_size, params_periods(hw_params),
1117 params_buffer_bytes(hw_params));
1118#endif
1119
1120 if (params_periods(hw_params) == CS46XX_FRAGS) {
1121 if (runtime->dma_area != cpcm->hw_buf.area)
1122 snd_pcm_lib_free_pages(substream);
1123 runtime->dma_area = cpcm->hw_buf.area;
1124 runtime->dma_addr = cpcm->hw_buf.addr;
1125 runtime->dma_bytes = cpcm->hw_buf.bytes;
1126
1127
1128#ifdef CONFIG_SND_CS46XX_NEW_DSP
1129 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1130 substream->ops = &snd_cs46xx_playback_ops;
1131 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1132 substream->ops = &snd_cs46xx_playback_rear_ops;
1133 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1134 substream->ops = &snd_cs46xx_playback_clfe_ops;
1135 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1136 substream->ops = &snd_cs46xx_playback_iec958_ops;
1137 } else {
da3cec35 1138 snd_BUG();
1da177e4
LT		 1139 }
1140#else
1141 substream->ops = &snd_cs46xx_playback_ops;
1142#endif
1143
1144 } else {
1145 if (runtime->dma_area == cpcm->hw_buf.area) {
1146 runtime->dma_area = NULL;
1147 runtime->dma_addr = 0;
1148 runtime->dma_bytes = 0;
1149 }
1150 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1151#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1152 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1153#endif
1154 return err;
1155 }
1156
1157#ifdef CONFIG_SND_CS46XX_NEW_DSP
1158 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1159 substream->ops = &snd_cs46xx_playback_indirect_ops;
1160 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1161 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1162 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1163 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1164 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1165 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1166 } else {
da3cec35 1167 snd_BUG();
1da177e4
LT		 1168 }
1169#else
1170 substream->ops = &snd_cs46xx_playback_indirect_ops;
1171#endif
1172
1173 }
1174
1175#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1176 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1177#endif
1178
1179 return 0;
1180}
1181
3d19f804 1182static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1da177e4 1183{
3d19f804
TI		 1184 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1185 struct snd_pcm_runtime *runtime = substream->runtime;
1186 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1187
1188 cpcm = runtime->private_data;
1189
1190 /* if play_back open fails, then this function
1191 is called and cpcm can actually be NULL here */
1192 if (!cpcm) return -ENXIO;
1193
1194 if (runtime->dma_area != cpcm->hw_buf.area)
1195 snd_pcm_lib_free_pages(substream);
1196
1197 runtime->dma_area = NULL;
1198 runtime->dma_addr = 0;
1199 runtime->dma_bytes = 0;
1200
1201 return 0;
1202}
1203
3d19f804 1204static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1205{
1206 unsigned int tmp;
1207 unsigned int pfie;
3d19f804
TI		 1208 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1209 struct snd_pcm_runtime *runtime = substream->runtime;
1210 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1211
1212 cpcm = runtime->private_data;
1213
1214#ifdef CONFIG_SND_CS46XX_NEW_DSP
da3cec35
TI		 1215 if (snd_BUG_ON(!cpcm->pcm_channel))
1216 return -ENXIO;
1da177e4
LT		 1217
1218 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1219 pfie &= ~0x0000f03f;
1220#else
1221 /* old dsp */
1222 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1223 pfie &= ~0x0000f03f;
1224#endif
1225
1226 cpcm->shift = 2;
1227 /* if to convert from stereo to mono */
1228 if (runtime->channels == 1) {
1229 cpcm->shift--;
1230 pfie |= 0x00002000;
1231 }
1232 /* if to convert from 8 bit to 16 bit */
1233 if (snd_pcm_format_width(runtime->format) == 8) {
1234 cpcm->shift--;
1235 pfie |= 0x00001000;
1236 }
1237 /* if to convert to unsigned */
1238 if (snd_pcm_format_unsigned(runtime->format))
1239 pfie |= 0x00008000;
1240
1241 /* Never convert byte order when sample stream is 8 bit */
1242 if (snd_pcm_format_width(runtime->format) != 8) {
1243 /* convert from big endian to little endian */
1244 if (snd_pcm_format_big_endian(runtime->format))
1245 pfie |= 0x00004000;
1246 }
1247
1248 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1249 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1250 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1251
1252#ifdef CONFIG_SND_CS46XX_NEW_DSP
1253
1254 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1255 tmp &= ~0x000003ff;
1256 tmp |= (4 << cpcm->shift) - 1;
1257 /* playback transaction count register */
1258 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1259
1260 /* playback format && interrupt enable */
1261 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1262#else
1263 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1264 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1265 tmp &= ~0x000003ff;
1266 tmp |= (4 << cpcm->shift) - 1;
1267 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1268 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1269 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1270#endif
1271
1272 return 0;
1273}
1274
3d19f804
TI		 1275static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1276 struct snd_pcm_hw_params *hw_params)
1da177e4 1277{
3d19f804
TI		 1278 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1279 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1280 int err;
1281
1282#ifdef CONFIG_SND_CS46XX_NEW_DSP
1283 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1284#endif
1285 if (runtime->periods == CS46XX_FRAGS) {
1286 if (runtime->dma_area != chip->capt.hw_buf.area)
1287 snd_pcm_lib_free_pages(substream);
1288 runtime->dma_area = chip->capt.hw_buf.area;
1289 runtime->dma_addr = chip->capt.hw_buf.addr;
1290 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1291 substream->ops = &snd_cs46xx_capture_ops;
1292 } else {
1293 if (runtime->dma_area == chip->capt.hw_buf.area) {
1294 runtime->dma_area = NULL;
1295 runtime->dma_addr = 0;
1296 runtime->dma_bytes = 0;
1297 }
1298 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1299 return err;
1300 substream->ops = &snd_cs46xx_capture_indirect_ops;
1301 }
1302
1303 return 0;
1304}
1305
3d19f804 1306static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1da177e4 1307{
3d19f804
TI		 1308 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1309 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1310
1311 if (runtime->dma_area != chip->capt.hw_buf.area)
1312 snd_pcm_lib_free_pages(substream);
1313 runtime->dma_area = NULL;
1314 runtime->dma_addr = 0;
1315 runtime->dma_bytes = 0;
1316
1317 return 0;
1318}
1319
3d19f804 1320static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1321{
3d19f804
TI		 1322 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1323 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1324
1325 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1326 chip->capt.shift = 2;
1327 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1328 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1329 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1330 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1331
1332 return 0;
1333}
1334
7d12e780 1335static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1da177e4 1336{
3d19f804 1337 struct snd_cs46xx *chip = dev_id;
1da177e4
LT		 1338 u32 status1;
1339#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1340 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1341 u32 status2;
1342 int i;
3d19f804 1343 struct snd_cs46xx_pcm *cpcm = NULL;
1da177e4
LT		 1344#endif
1345
1346 /*
1347 * Read the Interrupt Status Register to clear the interrupt
1348 */
1349 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1350 if ((status1 & 0x7fffffff) == 0) {
1351 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1352 return IRQ_NONE;
1353 }
1354
1355#ifdef CONFIG_SND_CS46XX_NEW_DSP
1356 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1357
1358 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1359 if (i <= 15) {
1360 if ( status1 & (1 << i) ) {
1361 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1362 if (chip->capt.substream)
1363 snd_pcm_period_elapsed(chip->capt.substream);
1364 } else {
1365 if (ins->pcm_channels[i].active &&
1366 ins->pcm_channels[i].private_data &&
1367 !ins->pcm_channels[i].unlinked) {
1368 cpcm = ins->pcm_channels[i].private_data;
1369 snd_pcm_period_elapsed(cpcm->substream);
1370 }
1371 }
1372 }
1373 } else {
1374 if ( status2 & (1 << (i - 16))) {
1375 if (ins->pcm_channels[i].active &&
1376 ins->pcm_channels[i].private_data &&
1377 !ins->pcm_channels[i].unlinked) {
1378 cpcm = ins->pcm_channels[i].private_data;
1379 snd_pcm_period_elapsed(cpcm->substream);
1380 }
1381 }
1382 }
1383 }
1384
1385#else
1386 /* old dsp */
1387 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1388 if (chip->playback_pcm->substream)
1389 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1390 }
1391 if ((status1 & HISR_VC1) && chip->pcm) {
1392 if (chip->capt.substream)
1393 snd_pcm_period_elapsed(chip->capt.substream);
1394 }
1395#endif
1396
1397 if ((status1 & HISR_MIDI) && chip->rmidi) {
1398 unsigned char c;
1399
1400 spin_lock(&chip->reg_lock);
1401 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1402 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1403 if ((chip->midcr & MIDCR_RIE) == 0)
1404 continue;
1405 snd_rawmidi_receive(chip->midi_input, &c, 1);
1406 }
1407 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1408 if ((chip->midcr & MIDCR_TIE) == 0)
1409 break;
1410 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1411 chip->midcr &= ~MIDCR_TIE;
1412 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1413 break;
1414 }
1415 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1416 }
1417 spin_unlock(&chip->reg_lock);
1418 }
1419 /*
1420 * EOI to the PCI part....reenables interrupts
1421 */
1422 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1423
1424 return IRQ_HANDLED;
1425}
1426
114d3549 1427static const struct snd_pcm_hardware snd_cs46xx_playback =
1da177e4
LT		 1428{
1429 .info = (SNDRV_PCM_INFO_MMAP |
1430 SNDRV_PCM_INFO_INTERLEAVED |
41e4845c 1431 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
b81e7732
TI		 1432 /*SNDRV_PCM_INFO_RESUME*/ |
1433 SNDRV_PCM_INFO_SYNC_APPLPTR),
1da177e4
LT		 1434 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1435 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1436 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1437 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1438 .rate_min = 5500,
1439 .rate_max = 48000,
1440 .channels_min = 1,
1441 .channels_max = 2,
1442 .buffer_bytes_max = (256 * 1024),
1443 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1444 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1445 .periods_min = CS46XX_FRAGS,
1446 .periods_max = 1024,
1447 .fifo_size = 0,
1448};
1449
114d3549 1450static const struct snd_pcm_hardware snd_cs46xx_capture =
1da177e4
LT		 1451{
1452 .info = (SNDRV_PCM_INFO_MMAP |
1453 SNDRV_PCM_INFO_INTERLEAVED |
41e4845c 1454 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
b81e7732
TI		 1455 /*SNDRV_PCM_INFO_RESUME*/ |
1456 SNDRV_PCM_INFO_SYNC_APPLPTR),
1da177e4
LT		 1457 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1458 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1459 .rate_min = 5500,
1460 .rate_max = 48000,
1461 .channels_min = 2,
1462 .channels_max = 2,
1463 .buffer_bytes_max = (256 * 1024),
1464 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1465 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1466 .periods_min = CS46XX_FRAGS,
1467 .periods_max = 1024,
1468 .fifo_size = 0,
1469};
1470
1471#ifdef CONFIG_SND_CS46XX_NEW_DSP
1472
54e848ce 1473static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1da177e4 1474
54e848ce 1475static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1da177e4
LT		 1476 .count = ARRAY_SIZE(period_sizes),
1477 .list = period_sizes,
1478 .mask = 0
1479};
1480
1481#endif
1482
3d19f804 1483static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1da177e4 1484{
4d572776 1485 kfree(runtime->private_data);
1da177e4
LT		 1486}
1487
3d19f804 1488static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1da177e4 1489{
3d19f804
TI		 1490 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1491 struct snd_cs46xx_pcm * cpcm;
1492 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1493
e560d8d8 1494 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1da177e4
LT		 1495 if (cpcm == NULL)
1496 return -ENOMEM;
6974f8ad 1497 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1da177e4
LT		 1498 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1499 kfree(cpcm);
1500 return -ENOMEM;
1501 }
1502
1503 runtime->hw = snd_cs46xx_playback;
1504 runtime->private_data = cpcm;
1505 runtime->private_free = snd_cs46xx_pcm_free_substream;
1506
1507 cpcm->substream = substream;
1508#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1509 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1510 cpcm->pcm_channel = NULL;
1511 cpcm->pcm_channel_id = pcm_channel_id;
1512
1513
1514 snd_pcm_hw_constraint_list(runtime, 0,
1515 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1516 &hw_constraints_period_sizes);
1517
62932df8 1518 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1519#else
1520 chip->playback_pcm = cpcm; /* HACK */
1521#endif
1522
1523 if (chip->accept_valid)
1524 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1525 chip->active_ctrl(chip, 1);
1526
1527 return 0;
1528}
1529
3d19f804 1530static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1da177e4 1531{
2b96a7f1 1532 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1da177e4
LT		 1533 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1534}
1535
1536#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1537static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1da177e4 1538{
2b96a7f1 1539 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1da177e4
LT		 1540 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1541}
1542
3d19f804 1543static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1da177e4 1544{
2b96a7f1 1545 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1da177e4
LT		 1546 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1547}
1548
3d19f804 1549static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1da177e4 1550{
3d19f804 1551 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 1552
2b96a7f1 1553 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1da177e4 1554
62932df8 1555 mutex_lock(&chip->spos_mutex);
1da177e4 1556 cs46xx_iec958_pre_open (chip);
62932df8 1557 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1558
1559 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1560}
1561
3d19f804 1562static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1da177e4 1563
3d19f804 1564static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1da177e4
LT		 1565{
1566 int err;
3d19f804 1567 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 1568
2b96a7f1 1569 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1da177e4
LT		 1570
1571 err = snd_cs46xx_playback_close(substream);
1572
62932df8 1573 mutex_lock(&chip->spos_mutex);
1da177e4 1574 cs46xx_iec958_post_close (chip);
62932df8 1575 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1576
1577 return err;
1578}
1579#endif
1580
3d19f804 1581static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1da177e4 1582{
3d19f804 1583 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 1584
6974f8ad 1585 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1da177e4
LT		 1586 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1587 return -ENOMEM;
1588 chip->capt.substream = substream;
1589 substream->runtime->hw = snd_cs46xx_capture;
1590
1591 if (chip->accept_valid)
1592 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1593
1594 chip->active_ctrl(chip, 1);
1595
1596#ifdef CONFIG_SND_CS46XX_NEW_DSP
1597 snd_pcm_hw_constraint_list(substream->runtime, 0,
1598 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1599 &hw_constraints_period_sizes);
1600#endif
1601 return 0;
1602}
1603
3d19f804 1604static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1da177e4 1605{
3d19f804
TI		 1606 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1607 struct snd_pcm_runtime *runtime = substream->runtime;
1608 struct snd_cs46xx_pcm * cpcm;
1da177e4
LT		 1609
1610 cpcm = runtime->private_data;
1611
1612 /* when playback_open fails, then cpcm can be NULL */
1613 if (!cpcm) return -ENXIO;
1614
1615#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 1616 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 1617 if (cpcm->pcm_channel) {
1618 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1619 cpcm->pcm_channel = NULL;
1620 }
62932df8 1621 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 1622#else
1623 chip->playback_pcm = NULL;
1624#endif
1625
1626 cpcm->substream = NULL;
1627 snd_dma_free_pages(&cpcm->hw_buf);
1628 chip->active_ctrl(chip, -1);
1629
1630 return 0;
1631}
1632
3d19f804 1633static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1da177e4 1634{
3d19f804 1635 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1636
1637 chip->capt.substream = NULL;
1638 snd_dma_free_pages(&chip->capt.hw_buf);
1639 chip->active_ctrl(chip, -1);
1640
1641 return 0;
1642}
1643
1644#ifdef CONFIG_SND_CS46XX_NEW_DSP
a6f9dec2 1645static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1da177e4
LT		 1646 .open = snd_cs46xx_playback_open_rear,
1647 .close = snd_cs46xx_playback_close,
1648 .ioctl = snd_pcm_lib_ioctl,
1649 .hw_params = snd_cs46xx_playback_hw_params,
1650 .hw_free = snd_cs46xx_playback_hw_free,
1651 .prepare = snd_cs46xx_playback_prepare,
1652 .trigger = snd_cs46xx_playback_trigger,
1653 .pointer = snd_cs46xx_playback_direct_pointer,
1654};
1655
a6f9dec2 1656static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1da177e4
LT		 1657 .open = snd_cs46xx_playback_open_rear,
1658 .close = snd_cs46xx_playback_close,
1659 .ioctl = snd_pcm_lib_ioctl,
1660 .hw_params = snd_cs46xx_playback_hw_params,
1661 .hw_free = snd_cs46xx_playback_hw_free,
1662 .prepare = snd_cs46xx_playback_prepare,
1663 .trigger = snd_cs46xx_playback_trigger,
1664 .pointer = snd_cs46xx_playback_indirect_pointer,
1665 .ack = snd_cs46xx_playback_transfer,
1666};
1667
a6f9dec2 1668static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1da177e4
LT		 1669 .open = snd_cs46xx_playback_open_clfe,
1670 .close = snd_cs46xx_playback_close,
1671 .ioctl = snd_pcm_lib_ioctl,
1672 .hw_params = snd_cs46xx_playback_hw_params,
1673 .hw_free = snd_cs46xx_playback_hw_free,
1674 .prepare = snd_cs46xx_playback_prepare,
1675 .trigger = snd_cs46xx_playback_trigger,
1676 .pointer = snd_cs46xx_playback_direct_pointer,
1677};
1678
a6f9dec2 1679static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1da177e4
LT		 1680 .open = snd_cs46xx_playback_open_clfe,
1681 .close = snd_cs46xx_playback_close,
1682 .ioctl = snd_pcm_lib_ioctl,
1683 .hw_params = snd_cs46xx_playback_hw_params,
1684 .hw_free = snd_cs46xx_playback_hw_free,
1685 .prepare = snd_cs46xx_playback_prepare,
1686 .trigger = snd_cs46xx_playback_trigger,
1687 .pointer = snd_cs46xx_playback_indirect_pointer,
1688 .ack = snd_cs46xx_playback_transfer,
1689};
1690
a6f9dec2 1691static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1da177e4
LT		 1692 .open = snd_cs46xx_playback_open_iec958,
1693 .close = snd_cs46xx_playback_close_iec958,
1694 .ioctl = snd_pcm_lib_ioctl,
1695 .hw_params = snd_cs46xx_playback_hw_params,
1696 .hw_free = snd_cs46xx_playback_hw_free,
1697 .prepare = snd_cs46xx_playback_prepare,
1698 .trigger = snd_cs46xx_playback_trigger,
1699 .pointer = snd_cs46xx_playback_direct_pointer,
1700};
1701
a6f9dec2 1702static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1da177e4
LT		 1703 .open = snd_cs46xx_playback_open_iec958,
1704 .close = snd_cs46xx_playback_close_iec958,
1705 .ioctl = snd_pcm_lib_ioctl,
1706 .hw_params = snd_cs46xx_playback_hw_params,
1707 .hw_free = snd_cs46xx_playback_hw_free,
1708 .prepare = snd_cs46xx_playback_prepare,
1709 .trigger = snd_cs46xx_playback_trigger,
1710 .pointer = snd_cs46xx_playback_indirect_pointer,
1711 .ack = snd_cs46xx_playback_transfer,
1712};
1713
1714#endif
1715
a6f9dec2 1716static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1da177e4
LT		 1717 .open = snd_cs46xx_playback_open,
1718 .close = snd_cs46xx_playback_close,
1719 .ioctl = snd_pcm_lib_ioctl,
1720 .hw_params = snd_cs46xx_playback_hw_params,
1721 .hw_free = snd_cs46xx_playback_hw_free,
1722 .prepare = snd_cs46xx_playback_prepare,
1723 .trigger = snd_cs46xx_playback_trigger,
1724 .pointer = snd_cs46xx_playback_direct_pointer,
1725};
1726
a6f9dec2 1727static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1da177e4
LT		 1728 .open = snd_cs46xx_playback_open,
1729 .close = snd_cs46xx_playback_close,
1730 .ioctl = snd_pcm_lib_ioctl,
1731 .hw_params = snd_cs46xx_playback_hw_params,
1732 .hw_free = snd_cs46xx_playback_hw_free,
1733 .prepare = snd_cs46xx_playback_prepare,
1734 .trigger = snd_cs46xx_playback_trigger,
1735 .pointer = snd_cs46xx_playback_indirect_pointer,
1736 .ack = snd_cs46xx_playback_transfer,
1737};
1738
a6f9dec2 1739static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1da177e4
LT		 1740 .open = snd_cs46xx_capture_open,
1741 .close = snd_cs46xx_capture_close,
1742 .ioctl = snd_pcm_lib_ioctl,
1743 .hw_params = snd_cs46xx_capture_hw_params,
1744 .hw_free = snd_cs46xx_capture_hw_free,
1745 .prepare = snd_cs46xx_capture_prepare,
1746 .trigger = snd_cs46xx_capture_trigger,
1747 .pointer = snd_cs46xx_capture_direct_pointer,
1748};
1749
a6f9dec2 1750static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1da177e4
LT		 1751 .open = snd_cs46xx_capture_open,
1752 .close = snd_cs46xx_capture_close,
1753 .ioctl = snd_pcm_lib_ioctl,
1754 .hw_params = snd_cs46xx_capture_hw_params,
1755 .hw_free = snd_cs46xx_capture_hw_free,
1756 .prepare = snd_cs46xx_capture_prepare,
1757 .trigger = snd_cs46xx_capture_trigger,
1758 .pointer = snd_cs46xx_capture_indirect_pointer,
1759 .ack = snd_cs46xx_capture_transfer,
1760};
1761
1da177e4 1762#ifdef CONFIG_SND_CS46XX_NEW_DSP
1da177e4
LT		 1763#define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1764#else
1765#define MAX_PLAYBACK_CHANNELS 1
1766#endif
1767
72134c4d 1768int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1da177e4 1769{
3d19f804 1770 struct snd_pcm *pcm;
1da177e4
LT		 1771 int err;
1772
1da177e4
LT		 1773 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1774 return err;
1775
1776 pcm->private_data = chip;
1da177e4
LT		 1777
1778 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1779 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1780
1781 /* global setup */
1782 pcm->info_flags = 0;
1783 strcpy(pcm->name, "CS46xx");
1784 chip->pcm = pcm;
1785
1786 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
6974f8ad
TI		 1787 &chip->pci->dev,
1788 64*1024, 256*1024);
1da177e4 1789
1da177e4
LT		 1790 return 0;
1791}
1792
1793
1794#ifdef CONFIG_SND_CS46XX_NEW_DSP
72134c4d 1795int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1da177e4 1796{
3d19f804 1797 struct snd_pcm *pcm;
1da177e4
LT		 1798 int err;
1799
1da177e4
LT		 1800 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1801 return err;
1802
1803 pcm->private_data = chip;
1da177e4
LT		 1804
1805 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1806
1807 /* global setup */
1808 pcm->info_flags = 0;
1809 strcpy(pcm->name, "CS46xx - Rear");
1810 chip->pcm_rear = pcm;
1811
1812 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
6974f8ad
TI		 1813 &chip->pci->dev,
1814 64*1024, 256*1024);
1da177e4 1815
1da177e4
LT		 1816 return 0;
1817}
1818
72134c4d 1819int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1da177e4 1820{
3d19f804 1821 struct snd_pcm *pcm;
1da177e4
LT		 1822 int err;
1823
1da177e4
LT		 1824 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1825 return err;
1826
1827 pcm->private_data = chip;
1da177e4
LT		 1828
1829 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1830
1831 /* global setup */
1832 pcm->info_flags = 0;
1833 strcpy(pcm->name, "CS46xx - Center LFE");
1834 chip->pcm_center_lfe = pcm;
1835
1836 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
6974f8ad
TI		 1837 &chip->pci->dev,
1838 64*1024, 256*1024);
1da177e4 1839
1da177e4
LT		 1840 return 0;
1841}
1842
72134c4d 1843int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1da177e4 1844{
3d19f804 1845 struct snd_pcm *pcm;
1da177e4
LT		 1846 int err;
1847
1da177e4
LT		 1848 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1849 return err;
1850
1851 pcm->private_data = chip;
1da177e4
LT		 1852
1853 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1854
1855 /* global setup */
1856 pcm->info_flags = 0;
1857 strcpy(pcm->name, "CS46xx - IEC958");
b43ddca4 1858 chip->pcm_iec958 = pcm;
1da177e4
LT		 1859
1860 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
6974f8ad
TI		 1861 &chip->pci->dev,
1862 64*1024, 256*1024);
1da177e4 1863
1da177e4
LT		 1864 return 0;
1865}
1866#endif
1867
1868/*
1869 * Mixer routines
1870 */
3d19f804 1871static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1872{
3d19f804 1873 struct snd_cs46xx *chip = bus->private_data;
1da177e4
LT		 1874
1875 chip->ac97_bus = NULL;
1876}
1877
3d19f804 1878static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1879{
3d19f804 1880 struct snd_cs46xx *chip = ac97->private_data;
1da177e4 1881
da3cec35
TI		 1882 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1883 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1884 return;
1da177e4
LT		 1885
1886 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1887 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1888 chip->eapd_switch = NULL;
1889 }
1890 else
1891 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1892}
1893
3d19f804
TI		 1894static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1895 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1896{
1897 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1898 uinfo->count = 2;
1899 uinfo->value.integer.min = 0;
1900 uinfo->value.integer.max = 0x7fff;
1901 return 0;
1902}
1903
3d19f804 1904static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1905{
3d19f804 1906 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1907 int reg = kcontrol->private_value;
1908 unsigned int val = snd_cs46xx_peek(chip, reg);
1909 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1910 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1911 return 0;
1912}
1913
3d19f804 1914static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1915{
3d19f804 1916 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1917 int reg = kcontrol->private_value;
1918 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1919 (0xffff - ucontrol->value.integer.value[1]));
1920 unsigned int old = snd_cs46xx_peek(chip, reg);
1921 int change = (old != val);
1922
1923 if (change) {
1924 snd_cs46xx_poke(chip, reg, val);
1925 }
1926
1927 return change;
1928}
1929
1930#ifdef CONFIG_SND_CS46XX_NEW_DSP
1931
3d19f804 1932static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1933{
3d19f804 1934 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1935
1936 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1937 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1938
1939 return 0;
1940}
1941
3d19f804 1942static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1943{
3d19f804 1944 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1945 int change = 0;
1946
1947 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1948 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1949 cs46xx_dsp_set_dac_volume(chip,
1950 ucontrol->value.integer.value[0],
1951 ucontrol->value.integer.value[1]);
1952 change = 1;
1953 }
1954
1955 return change;
1956}
1957
1958#if 0
3d19f804 1959static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1960{
3d19f804 1961 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1962
1963 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1964 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1965 return 0;
1966}
1967
3d19f804 1968static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1969{
3d19f804 1970 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1971 int change = 0;
1972
1973 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1974 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1975 cs46xx_dsp_set_iec958_volume (chip,
1976 ucontrol->value.integer.value[0],
1977 ucontrol->value.integer.value[1]);
1978 change = 1;
1979 }
1980
1981 return change;
1982}
1983#endif
1984
a5ce8890 1985#define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1da177e4 1986
3d19f804
TI		 1987static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1988 struct snd_ctl_elem_value *ucontrol)
1da177e4 1989{
3d19f804 1990 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1991 int reg = kcontrol->private_value;
1992
1993 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1994 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1995 else
1996 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1997
1998 return 0;
1999}
2000
3d19f804
TI		 2001static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
2002 struct snd_ctl_elem_value *ucontrol)
1da177e4 2003{
3d19f804 2004 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2005 int change, res;
2006
2007 switch (kcontrol->private_value) {
2008 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
62932df8 2009 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2010 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2011 if (ucontrol->value.integer.value[0] && !change)
2012 cs46xx_dsp_enable_spdif_out(chip);
2013 else if (change && !ucontrol->value.integer.value[0])
2014 cs46xx_dsp_disable_spdif_out(chip);
2015
2016 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
62932df8 2017 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2018 break;
2019 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2020 change = chip->dsp_spos_instance->spdif_status_in;
2021 if (ucontrol->value.integer.value[0] && !change) {
2022 cs46xx_dsp_enable_spdif_in(chip);
2023 /* restore volume */
2024 }
2025 else if (change && !ucontrol->value.integer.value[0])
2026 cs46xx_dsp_disable_spdif_in(chip);
2027
2028 res = (change != chip->dsp_spos_instance->spdif_status_in);
2029 break;
2030 default:
2031 res = -EINVAL;
da3cec35 2032 snd_BUG(); /* should never happen ... */
1da177e4
LT		 2033 }
2034
2035 return res;
2036}
2037
3d19f804
TI		 2038static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2039 struct snd_ctl_elem_value *ucontrol)
1da177e4 2040{
3d19f804
TI		 2041 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2042 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2043
2044 if (ins->adc_input != NULL)
2045 ucontrol->value.integer.value[0] = 1;
2046 else
2047 ucontrol->value.integer.value[0] = 0;
2048
2049 return 0;
2050}
2051
3d19f804
TI		 2052static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2053 struct snd_ctl_elem_value *ucontrol)
1da177e4 2054{
3d19f804
TI		 2055 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2056 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2057 int change = 0;
2058
2059 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2060 cs46xx_dsp_enable_adc_capture(chip);
2061 change = 1;
2062 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2063 cs46xx_dsp_disable_adc_capture(chip);
2064 change = 1;
2065 }
2066 return change;
2067}
2068
3d19f804
TI		 2069static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2070 struct snd_ctl_elem_value *ucontrol)
1da177e4 2071{
3d19f804
TI		 2072 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2073 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2074
2075 if (ins->pcm_input != NULL)
2076 ucontrol->value.integer.value[0] = 1;
2077 else
2078 ucontrol->value.integer.value[0] = 0;
2079
2080 return 0;
2081}
2082
2083
3d19f804
TI		 2084static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2085 struct snd_ctl_elem_value *ucontrol)
1da177e4 2086{
3d19f804
TI		 2087 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2088 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2089 int change = 0;
2090
2091 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2092 cs46xx_dsp_enable_pcm_capture(chip);
2093 change = 1;
2094 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2095 cs46xx_dsp_disable_pcm_capture(chip);
2096 change = 1;
2097 }
2098
2099 return change;
2100}
2101
3d19f804
TI		 2102static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2103 struct snd_ctl_elem_value *ucontrol)
1da177e4 2104{
3d19f804 2105 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2106
2107 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2108
2109 if (val1 & EGPIODR_GPOE0)
2110 ucontrol->value.integer.value[0] = 1;
2111 else
2112 ucontrol->value.integer.value[0] = 0;
2113
2114 return 0;
2115}
2116
2117/*
2118 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2119 */
3d19f804
TI		 2120static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2121 struct snd_ctl_elem_value *ucontrol)
1da177e4 2122{
3d19f804 2123 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2124 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2125 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2126
2127 if (ucontrol->value.integer.value[0]) {
2128 /* optical is default */
2129 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2130 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2131 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2132 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2133 } else {
2134 /* coaxial */
2135 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2136 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2137 }
2138
2139 /* checking diff from the EGPIO direction register
2140 should be enough */
2141 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2142}
2143
2144
3d19f804 2145static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2146{
2147 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2148 uinfo->count = 1;
2149 return 0;
2150}
2151
3d19f804
TI		 2152static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2153 struct snd_ctl_elem_value *ucontrol)
1da177e4 2154{
3d19f804
TI		 2155 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2156 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4 2157
62932df8 2158 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2159 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2160 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2161 ucontrol->value.iec958.status[2] = 0;
2162 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
62932df8 2163 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2164
2165 return 0;
2166}
2167
3d19f804
TI		 2168static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2169 struct snd_ctl_elem_value *ucontrol)
1da177e4 2170{
3d19f804
TI		 2171 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2172 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2173 unsigned int val;
2174 int change;
2175
62932df8 2176 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2177 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2178 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2179 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2180 /* left and right validity bit */
2181 (1 << 13) | (1 << 12);
2182
2183
2184 change = (unsigned int)ins->spdif_csuv_default != val;
2185 ins->spdif_csuv_default = val;
2186
2187 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2188 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2189
62932df8 2190 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2191
2192 return change;
2193}
2194
3d19f804
TI		 2195static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2196 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2197{
2198 ucontrol->value.iec958.status[0] = 0xff;
2199 ucontrol->value.iec958.status[1] = 0xff;
2200 ucontrol->value.iec958.status[2] = 0x00;
2201 ucontrol->value.iec958.status[3] = 0xff;
2202 return 0;
2203}
2204
3d19f804
TI		 2205static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2206 struct snd_ctl_elem_value *ucontrol)
1da177e4 2207{
3d19f804
TI		 2208 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2209 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4 2210
62932df8 2211 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2212 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2213 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2214 ucontrol->value.iec958.status[2] = 0;
2215 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
62932df8 2216 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2217
2218 return 0;
2219}
2220
3d19f804
TI		 2221static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2222 struct snd_ctl_elem_value *ucontrol)
1da177e4 2223{
3d19f804
TI		 2224 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2225 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2226 unsigned int val;
2227 int change;
2228
62932df8 2229 mutex_lock(&chip->spos_mutex);
1da177e4
LT		 2230 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2231 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2232 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2233 /* left and right validity bit */
2234 (1 << 13) | (1 << 12);
2235
2236
2237 change = ins->spdif_csuv_stream != val;
2238 ins->spdif_csuv_stream = val;
2239
2240 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2241 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2242
62932df8 2243 mutex_unlock(&chip->spos_mutex);
1da177e4
LT		 2244
2245 return change;
2246}
2247
2248#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2249
2250
e23e7a14 2251static struct snd_kcontrol_new snd_cs46xx_controls[] = {
1da177e4
LT		 2252{
2253 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2254 .name = "DAC Volume",
2255 .info = snd_cs46xx_vol_info,
2256#ifndef CONFIG_SND_CS46XX_NEW_DSP
2257 .get = snd_cs46xx_vol_get,
2258 .put = snd_cs46xx_vol_put,
2259 .private_value = BA1_PVOL,
2260#else
2261 .get = snd_cs46xx_vol_dac_get,
2262 .put = snd_cs46xx_vol_dac_put,
2263#endif
2264},
2265
2266{
2267 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2268 .name = "ADC Volume",
2269 .info = snd_cs46xx_vol_info,
2270 .get = snd_cs46xx_vol_get,
2271 .put = snd_cs46xx_vol_put,
2272#ifndef CONFIG_SND_CS46XX_NEW_DSP
2273 .private_value = BA1_CVOL,
2274#else
2275 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2276#endif
2277},
2278#ifdef CONFIG_SND_CS46XX_NEW_DSP
2279{
2280 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2281 .name = "ADC Capture Switch",
2282 .info = snd_mixer_boolean_info,
2283 .get = snd_cs46xx_adc_capture_get,
2284 .put = snd_cs46xx_adc_capture_put
2285},
2286{
2287 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2288 .name = "DAC Capture Switch",
2289 .info = snd_mixer_boolean_info,
2290 .get = snd_cs46xx_pcm_capture_get,
2291 .put = snd_cs46xx_pcm_capture_put
2292},
2293{
2294 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2295 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
1da177e4
LT		 2296 .info = snd_mixer_boolean_info,
2297 .get = snd_cs46xx_iec958_get,
2298 .put = snd_cs46xx_iec958_put,
2299 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2300},
2301{
2302 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2303 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
1da177e4
LT		 2304 .info = snd_mixer_boolean_info,
2305 .get = snd_cs46xx_iec958_get,
2306 .put = snd_cs46xx_iec958_put,
2307 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2308},
2309#if 0
2310/* Input IEC958 volume does not work for the moment. (Benny) */
2311{
2312 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2313 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
1da177e4
LT		 2314 .info = snd_cs46xx_vol_info,
2315 .get = snd_cs46xx_vol_iec958_get,
2316 .put = snd_cs46xx_vol_iec958_put,
2317 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2318},
2319#endif
2320{
2321 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2322 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2323 .info = snd_cs46xx_spdif_info,
2324 .get = snd_cs46xx_spdif_default_get,
2325 .put = snd_cs46xx_spdif_default_put,
2326},
2327{
2328 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2329 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2330 .info = snd_cs46xx_spdif_info,
2331 .get = snd_cs46xx_spdif_mask_get,
2332 .access = SNDRV_CTL_ELEM_ACCESS_READ
2333},
2334{
2335 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2336 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2337 .info = snd_cs46xx_spdif_info,
2338 .get = snd_cs46xx_spdif_stream_get,
2339 .put = snd_cs46xx_spdif_stream_put
2340},
2341
1da177e4
LT		 2342#endif
2343};
2344
2345#ifdef CONFIG_SND_CS46XX_NEW_DSP
2346/* set primary cs4294 codec into Extended Audio Mode */
3d19f804
TI		 2347static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2348 struct snd_ctl_elem_value *ucontrol)
1da177e4 2349{
3d19f804 2350 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2351 unsigned short val;
2352 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2353 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2354 return 0;
2355}
2356
3d19f804
TI		 2357static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2358 struct snd_ctl_elem_value *ucontrol)
1da177e4 2359{
3d19f804 2360 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2361 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2362 AC97_CSR_ACMODE, 0x200,
2363 ucontrol->value.integer.value[0] ? 0 : 0x200);
2364}
2365
30b5817e 2366static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
1da177e4
LT		 2367 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2368 .name = "Duplicate Front",
2369 .info = snd_mixer_boolean_info,
2370 .get = snd_cs46xx_front_dup_get,
2371 .put = snd_cs46xx_front_dup_put,
2372};
2373#endif
2374
2375#ifdef CONFIG_SND_CS46XX_NEW_DSP
2376/* Only available on the Hercules Game Theater XP soundcard */
f40b6890 2377static struct snd_kcontrol_new snd_hercules_controls[] = {
1da177e4
LT		 2378{
2379 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2380 .name = "Optical/Coaxial SPDIF Input Switch",
2381 .info = snd_mixer_boolean_info,
2382 .get = snd_herc_spdif_select_get,
2383 .put = snd_herc_spdif_select_put,
2384},
2385};
2386
2387
3d19f804 2388static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
1da177e4
LT		 2389{
2390 unsigned long end_time;
2391 int err;
2392
2393 /* reset to defaults */
2394 snd_ac97_write(ac97, AC97_RESET, 0);
2395
2396 /* set the desired CODEC mode */
2397 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2b96a7f1 2398 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
04510a74 2399 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
1da177e4 2400 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2b96a7f1 2401 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
04510a74 2402 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
1da177e4 2403 } else {
da3cec35 2404 snd_BUG(); /* should never happen ... */
1da177e4
LT		 2405 }
2406
2407 udelay(50);
2408
2409 /* it's necessary to wait awhile until registers are accessible after RESET */
2410 /* because the PCM or MASTER volume registers can be modified, */
2411 /* the REC_GAIN register is used for tests */
2412 end_time = jiffies + HZ;
2413 do {
2414 unsigned short ext_mid;
2415
2416 /* use preliminary reads to settle the communication */
2417 snd_ac97_read(ac97, AC97_RESET);
2418 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2419 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2420 /* modem? */
2421 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2422 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2423 return;
2424
2425 /* test if we can write to the record gain volume register */
7fb2d723 2426 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
1da177e4
LT		 2427 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2428 return;
2429
ef21ca24 2430 msleep(10);
1da177e4
LT		 2431 } while (time_after_eq(end_time, jiffies));
2432
2b96a7f1
TI		 2433 dev_err(ac97->bus->card->dev,
2434 "CS46xx secondary codec doesn't respond!\n");
1da177e4
LT		 2435}
2436#endif
2437
e23e7a14 2438static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
1da177e4
LT		 2439{
2440 int idx, err;
3d19f804 2441 struct snd_ac97_template ac97;
1da177e4
LT		 2442
2443 memset(&ac97, 0, sizeof(ac97));
2444 ac97.private_data = chip;
2445 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2446 ac97.num = codec;
2447 if (chip->amplifier_ctrl == amp_voyetra)
2448 ac97.scaps = AC97_SCAP_INV_EAPD;
2449
2450 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2451 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2452 udelay(10);
2453 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2b96a7f1 2454 dev_dbg(chip->card->dev,
16f0f01d 2455 "secondary codec not present\n");
1da177e4
LT		 2456 return -ENXIO;
2457 }
2458 }
2459
2460 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2461 for (idx = 0; idx < 100; ++idx) {
2462 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2463 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2464 return err;
2465 }
ef21ca24 2466 msleep(10);
1da177e4 2467 }
2b96a7f1 2468 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
1da177e4
LT		 2469 return -ENXIO;
2470}
2471
e23e7a14 2472int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
1da177e4 2473{
3d19f804
TI		 2474 struct snd_card *card = chip->card;
2475 struct snd_ctl_elem_id id;
1da177e4
LT		 2476 int err;
2477 unsigned int idx;
3d19f804 2478 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 2479#ifdef CONFIG_SND_CS46XX_NEW_DSP
2480 .reset = snd_cs46xx_codec_reset,
2481#endif
2482 .write = snd_cs46xx_ac97_write,
2483 .read = snd_cs46xx_ac97_read,
2484 };
2485
2486 /* detect primary codec */
2487 chip->nr_ac97_codecs = 0;
2b96a7f1 2488 dev_dbg(chip->card->dev, "detecting primary codec\n");
1da177e4
LT		 2489 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2490 return err;
2491 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2492
2493 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2494 return -ENXIO;
2495 chip->nr_ac97_codecs = 1;
2496
2497#ifdef CONFIG_SND_CS46XX_NEW_DSP
16f0f01d 2498 dev_dbg(chip->card->dev, "detecting secondary codec\n");
1da177e4
LT		 2499 /* try detect a secondary codec */
2500 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2501 chip->nr_ac97_codecs = 2;
2502#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2503
2504 /* add cs4630 mixer controls */
2505 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
3d19f804 2506 struct snd_kcontrol *kctl;
1da177e4 2507 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
67ed4161
CL		 2508 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2509 kctl->id.device = spdif_device;
1da177e4
LT		 2510 if ((err = snd_ctl_add(card, kctl)) < 0)
2511 return err;
2512 }
2513
2514 /* get EAPD mixer switch (for voyetra hack) */
2515 memset(&id, 0, sizeof(id));
2516 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2517 strcpy(id.name, "External Amplifier");
2518 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2519
2520#ifdef CONFIG_SND_CS46XX_NEW_DSP
2521 if (chip->nr_ac97_codecs == 1) {
2522 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
eed273b7 2523 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
1da177e4
LT		 2524 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2525 if (err < 0)
2526 return err;
2527 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2528 AC97_CSR_ACMODE, 0x200);
2529 }
2530 }
2531 /* do soundcard specific mixer setup */
2532 if (chip->mixer_init) {
2b96a7f1 2533 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
1da177e4
LT		 2534 chip->mixer_init(chip);
2535 }
2536#endif
2537
2538 /* turn on amplifier */
2539 chip->amplifier_ctrl(chip, 1);
2540
2541 return 0;
2542}
2543
2544/*
2545 * RawMIDI interface
2546 */
2547
3d19f804 2548static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
1da177e4
LT		 2549{
2550 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2551 udelay(100);
2552 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2553}
2554
3d19f804 2555static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
1da177e4 2556{
3d19f804 2557 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2558
2559 chip->active_ctrl(chip, 1);
2560 spin_lock_irq(&chip->reg_lock);
2561 chip->uartm |= CS46XX_MODE_INPUT;
2562 chip->midcr |= MIDCR_RXE;
2563 chip->midi_input = substream;
2564 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2565 snd_cs46xx_midi_reset(chip);
2566 } else {
2567 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2568 }
2569 spin_unlock_irq(&chip->reg_lock);
2570 return 0;
2571}
2572
3d19f804 2573static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
1da177e4 2574{
3d19f804 2575 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2576
2577 spin_lock_irq(&chip->reg_lock);
2578 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2579 chip->midi_input = NULL;
2580 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2581 snd_cs46xx_midi_reset(chip);
2582 } else {
2583 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2584 }
2585 chip->uartm &= ~CS46XX_MODE_INPUT;
2586 spin_unlock_irq(&chip->reg_lock);
2587 chip->active_ctrl(chip, -1);
2588 return 0;
2589}
2590
3d19f804 2591static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
1da177e4 2592{
3d19f804 2593 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2594
2595 chip->active_ctrl(chip, 1);
2596
2597 spin_lock_irq(&chip->reg_lock);
2598 chip->uartm |= CS46XX_MODE_OUTPUT;
2599 chip->midcr |= MIDCR_TXE;
2600 chip->midi_output = substream;
2601 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2602 snd_cs46xx_midi_reset(chip);
2603 } else {
2604 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2605 }
2606 spin_unlock_irq(&chip->reg_lock);
2607 return 0;
2608}
2609
3d19f804 2610static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
1da177e4 2611{
3d19f804 2612 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2613
2614 spin_lock_irq(&chip->reg_lock);
2615 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2616 chip->midi_output = NULL;
2617 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2618 snd_cs46xx_midi_reset(chip);
2619 } else {
2620 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2621 }
2622 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2623 spin_unlock_irq(&chip->reg_lock);
2624 chip->active_ctrl(chip, -1);
2625 return 0;
2626}
2627
3d19f804 2628static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2629{
2630 unsigned long flags;
3d19f804 2631 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2632
2633 spin_lock_irqsave(&chip->reg_lock, flags);
2634 if (up) {
2635 if ((chip->midcr & MIDCR_RIE) == 0) {
2636 chip->midcr |= MIDCR_RIE;
2637 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2638 }
2639 } else {
2640 if (chip->midcr & MIDCR_RIE) {
2641 chip->midcr &= ~MIDCR_RIE;
2642 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2643 }
2644 }
2645 spin_unlock_irqrestore(&chip->reg_lock, flags);
2646}
2647
3d19f804 2648static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2649{
2650 unsigned long flags;
3d19f804 2651 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2652 unsigned char byte;
2653
2654 spin_lock_irqsave(&chip->reg_lock, flags);
2655 if (up) {
2656 if ((chip->midcr & MIDCR_TIE) == 0) {
2657 chip->midcr |= MIDCR_TIE;
2658 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2659 while ((chip->midcr & MIDCR_TIE) &&
2660 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2661 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2662 chip->midcr &= ~MIDCR_TIE;
2663 } else {
2664 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2665 }
2666 }
2667 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2668 }
2669 } else {
2670 if (chip->midcr & MIDCR_TIE) {
2671 chip->midcr &= ~MIDCR_TIE;
2672 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2673 }
2674 }
2675 spin_unlock_irqrestore(&chip->reg_lock, flags);
2676}
2677
485885b9 2678static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
1da177e4
LT		 2679{
2680 .open = snd_cs46xx_midi_output_open,
2681 .close = snd_cs46xx_midi_output_close,
2682 .trigger = snd_cs46xx_midi_output_trigger,
2683};
2684
485885b9 2685static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
1da177e4
LT		 2686{
2687 .open = snd_cs46xx_midi_input_open,
2688 .close = snd_cs46xx_midi_input_close,
2689 .trigger = snd_cs46xx_midi_input_trigger,
2690};
2691
72134c4d 2692int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
1da177e4 2693{
3d19f804 2694 struct snd_rawmidi *rmidi;
1da177e4
LT		 2695 int err;
2696
1da177e4
LT		 2697 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2698 return err;
2699 strcpy(rmidi->name, "CS46XX");
2700 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2701 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2702 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2703 rmidi->private_data = chip;
2704 chip->rmidi = rmidi;
1da177e4
LT		 2705 return 0;
2706}
2707
2708
2709/*
2710 * gameport interface
2711 */
2712
b2fac073 2713#if IS_REACHABLE(CONFIG_GAMEPORT)
1da177e4
LT		 2714
2715static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2716{
3d19f804 2717 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4 2718
da3cec35
TI		 2719 if (snd_BUG_ON(!chip))
2720 return;
1da177e4
LT		 2721 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2722}
2723
2724static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2725{
3d19f804 2726 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4 2727
da3cec35
TI		 2728 if (snd_BUG_ON(!chip))
2729 return 0;
1da177e4
LT		 2730 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2731}
2732
2733static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2734{
3d19f804 2735 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4
LT		 2736 unsigned js1, js2, jst;
2737
da3cec35
TI		 2738 if (snd_BUG_ON(!chip))
2739 return 0;
1da177e4
LT		 2740
2741 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2742 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2743 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2744
2745 *buttons = (~jst >> 4) & 0x0F;
2746
2747 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2748 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2749 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2750 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2751
2752 for(jst=0;jst<4;++jst)
2753 if(axes[jst]==0xFFFF) axes[jst] = -1;
2754 return 0;
2755}
2756
2757static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2758{
2759 switch (mode) {
2760 case GAMEPORT_MODE_COOKED:
2761 return 0;
2762 case GAMEPORT_MODE_RAW:
2763 return 0;
2764 default:
2765 return -1;
2766 }
2767 return 0;
2768}
2769
e23e7a14 2770int snd_cs46xx_gameport(struct snd_cs46xx *chip)
1da177e4
LT		 2771{
2772 struct gameport *gp;
2773
2774 chip->gameport = gp = gameport_allocate_port();
2775 if (!gp) {
2b96a7f1
TI		 2776 dev_err(chip->card->dev,
2777 "cannot allocate memory for gameport\n");
1da177e4
LT		 2778 return -ENOMEM;
2779 }
2780
2781 gameport_set_name(gp, "CS46xx Gameport");
2782 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2783 gameport_set_dev_parent(gp, &chip->pci->dev);
2784 gameport_set_port_data(gp, chip);
2785
2786 gp->open = snd_cs46xx_gameport_open;
2787 gp->read = snd_cs46xx_gameport_read;
2788 gp->trigger = snd_cs46xx_gameport_trigger;
2789 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2790
2791 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2792 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2793
2794 gameport_register_port(gp);
2795
2796 return 0;
2797}
2798
3d19f804 2799static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
1da177e4
LT		 2800{
2801 if (chip->gameport) {
2802 gameport_unregister_port(chip->gameport);
2803 chip->gameport = NULL;
2804 }
2805}
2806#else
e23e7a14 2807int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
3d19f804 2808static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
1da177e4
LT		 2809#endif /* CONFIG_GAMEPORT */
2810
95bb6258 2811#ifdef CONFIG_SND_PROC_FS
1da177e4
LT		 2812/*
2813 * proc interface
2814 */
2815
24e4a121
TI		 2816static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2817 void *file_private_data,
2818 struct file *file, char __user *buf,
2819 size_t count, loff_t pos)
1da177e4 2820{
3d19f804 2821 struct snd_cs46xx_region *region = entry->private_data;
1da177e4 2822
d97e1b78
TI		 2823 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2824 return -EFAULT;
2825 return count;
1da177e4
LT		 2826}
2827
2828static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2829 .read = snd_cs46xx_io_read,
2830};
2831
e23e7a14 2832static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
1da177e4 2833{
3d19f804 2834 struct snd_info_entry *entry;
1da177e4
LT		 2835 int idx;
2836
2837 for (idx = 0; idx < 5; idx++) {
3d19f804 2838 struct snd_cs46xx_region *region = &chip->region.idx[idx];
1da177e4
LT		 2839 if (! snd_card_proc_new(card, region->name, &entry)) {
2840 entry->content = SNDRV_INFO_CONTENT_DATA;
2841 entry->private_data = chip;
2842 entry->c.ops = &snd_cs46xx_proc_io_ops;
2843 entry->size = region->size;
6a73cf46 2844 entry->mode = S_IFREG | 0400;
1da177e4
LT		 2845 }
2846 }
2847#ifdef CONFIG_SND_CS46XX_NEW_DSP
2848 cs46xx_dsp_proc_init(card, chip);
2849#endif
2850 return 0;
2851}
2852
3d19f804 2853static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
1da177e4
LT		 2854{
2855#ifdef CONFIG_SND_CS46XX_NEW_DSP
2856 cs46xx_dsp_proc_done(chip);
2857#endif
2858 return 0;
2859}
95bb6258 2860#else /* !CONFIG_SND_PROC_FS */
adf1b3d2
TI		 2861#define snd_cs46xx_proc_init(card, chip)
2862#define snd_cs46xx_proc_done(chip)
2863#endif
1da177e4
LT		 2864
2865/*
2866 * stop the h/w
2867 */
3d19f804 2868static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
1da177e4
LT		 2869{
2870 unsigned int tmp;
2871
2872 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2873 tmp &= ~0x0000f03f;
2874 tmp |= 0x00000010;
2875 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2876
2877 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2878 tmp &= ~0x0000003f;
2879 tmp |= 0x00000011;
2880 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2881
2882 /*
2883 * Stop playback DMA.
2884 */
2885 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2886 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2887
2888 /*
2889 * Stop capture DMA.
2890 */
2891 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2892 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2893
2894 /*
2895 * Reset the processor.
2896 */
2897 snd_cs46xx_reset(chip);
2898
2899 snd_cs46xx_proc_stop(chip);
2900
2901 /*
2902 * Power down the PLL.
2903 */
2904 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2905
2906 /*
2907 * Turn off the Processor by turning off the software clock enable flag in
2908 * the clock control register.
2909 */
2910 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2911 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2912}
2913
2914
3d19f804 2915static int snd_cs46xx_free(struct snd_cs46xx *chip)
1da177e4
LT		 2916{
2917 int idx;
2918
da3cec35
TI		 2919 if (snd_BUG_ON(!chip))
2920 return -EINVAL;
1da177e4
LT		 2921
2922 if (chip->active_ctrl)
2923 chip->active_ctrl(chip, 1);
2924
2925 snd_cs46xx_remove_gameport(chip);
2926
2927 if (chip->amplifier_ctrl)
2928 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2929
2930 snd_cs46xx_proc_done(chip);
2931
2932 if (chip->region.idx[0].resource)
2933 snd_cs46xx_hw_stop(chip);
2934
0a50d2b2
TI		 2935 if (chip->irq >= 0)
2936 free_irq(chip->irq, chip);
2937
ebf029da
TI		 2938 if (chip->active_ctrl)
2939 chip->active_ctrl(chip, -chip->amplifier);
2940
1da177e4 2941 for (idx = 0; idx < 5; idx++) {
3d19f804 2942 struct snd_cs46xx_region *region = &chip->region.idx[idx];
ff6defa6
ME		 2943
2944 iounmap(region->remap_addr);
b1d5776d 2945 release_and_free_resource(region->resource);
1da177e4 2946 }
1da177e4 2947
1da177e4
LT		 2948#ifdef CONFIG_SND_CS46XX_NEW_DSP
2949 if (chip->dsp_spos_instance) {
2950 cs46xx_dsp_spos_destroy(chip);
2951 chip->dsp_spos_instance = NULL;
2952 }
ad233a5f
TI		 2953 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2954 free_module_desc(chip->modules[idx]);
2955#else
2956 vfree(chip->ba1);
1da177e4
LT		 2957#endif
2958
c7561cd8 2959#ifdef CONFIG_PM_SLEEP
89f157d9
TI		 2960 kfree(chip->saved_regs);
2961#endif
2962
1da177e4
LT		 2963 pci_disable_device(chip->pci);
2964 kfree(chip);
2965 return 0;
2966}
2967
3d19f804 2968static int snd_cs46xx_dev_free(struct snd_device *device)
1da177e4 2969{
3d19f804 2970 struct snd_cs46xx *chip = device->device_data;
1da177e4
LT		 2971 return snd_cs46xx_free(chip);
2972}
2973
2974/*
2975 * initialize chip
2976 */
3d19f804 2977static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
1da177e4
LT		 2978{
2979 int timeout;
2980
2981 /*
2982 * First, blast the clock control register to zero so that the PLL starts
2983 * out in a known state, and blast the master serial port control register
2984 * to zero so that the serial ports also start out in a known state.
2985 */
2986 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2987 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2988
2989 /*
2990 * If we are in AC97 mode, then we must set the part to a host controlled
2991 * AC-link. Otherwise, we won't be able to bring up the link.
2992 */
2993#ifdef CONFIG_SND_CS46XX_NEW_DSP
2994 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2995 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2996 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2997#else
2998 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2999#endif
3000
3001 /*
3002 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3003 * spec) and then drive it high. This is done for non AC97 modes since
3004 * there might be logic external to the CS461x that uses the ARST# line
3005 * for a reset.
3006 */
3007 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3008#ifdef CONFIG_SND_CS46XX_NEW_DSP
3009 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3010#endif
3011 udelay(50);
3012 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3013#ifdef CONFIG_SND_CS46XX_NEW_DSP
3014 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3015#endif
3016
3017 /*
3018 * The first thing we do here is to enable sync generation. As soon
3019 * as we start receiving bit clock, we'll start producing the SYNC
3020 * signal.
3021 */
3022 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3023#ifdef CONFIG_SND_CS46XX_NEW_DSP
3024 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3025#endif
3026
3027 /*
3028 * Now wait for a short while to allow the AC97 part to start
3029 * generating bit clock (so we don't try to start the PLL without an
3030 * input clock).
3031 */
3032 mdelay(10);
3033
3034 /*
3035 * Set the serial port timing configuration, so that
3036 * the clock control circuit gets its clock from the correct place.
3037 */
3038 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3039
3040 /*
3041 * Write the selected clock control setup to the hardware. Do not turn on
3042 * SWCE yet (if requested), so that the devices clocked by the output of
3043 * PLL are not clocked until the PLL is stable.
3044 */
3045 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3046 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3047 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3048
3049 /*
3050 * Power up the PLL.
3051 */
3052 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3053
3054 /*
3055 * Wait until the PLL has stabilized.
3056 */
ef21ca24 3057 msleep(100);
1da177e4
LT		 3058
3059 /*
3060 * Turn on clocking of the core so that we can setup the serial ports.
3061 */
3062 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3063
3064 /*
3065 * Enable FIFO Host Bypass
3066 */
3067 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3068
3069 /*
3070 * Fill the serial port FIFOs with silence.
3071 */
3072 snd_cs46xx_clear_serial_FIFOs(chip);
3073
3074 /*
3075 * Set the serial port FIFO pointer to the first sample in the FIFO.
3076 */
3077 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3078
3079 /*
3080 * Write the serial port configuration to the part. The master
3081 * enable bit is not set until all other values have been written.
3082 */
3083 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3084 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3085 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3086
3087
3088#ifdef CONFIG_SND_CS46XX_NEW_DSP
3089 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3090 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3091 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3092 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3093 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3094#endif
3095
3096 mdelay(5);
3097
3098
3099 /*
3100 * Wait for the codec ready signal from the AC97 codec.
3101 */
3102 timeout = 150;
3103 while (timeout-- > 0) {
3104 /*
3105 * Read the AC97 status register to see if we've seen a CODEC READY
3106 * signal from the AC97 codec.
3107 */
3108 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3109 goto ok1;
ef21ca24 3110 msleep(10);
1da177e4
LT		 3111 }
3112
3113
2b96a7f1
TI		 3114 dev_err(chip->card->dev,
3115 "create - never read codec ready from AC'97\n");
3116 dev_err(chip->card->dev,
3117 "it is not probably bug, try to use CS4236 driver\n");
1da177e4
LT		 3118 return -EIO;
3119 ok1:
3120#ifdef CONFIG_SND_CS46XX_NEW_DSP
3121 {
3122 int count;
3123 for (count = 0; count < 150; count++) {
3124 /* First, we want to wait for a short time. */
3125 udelay(25);
3126
3127 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3128 break;
3129 }
3130
3131 /*
3132 * Make sure CODEC is READY.
3133 */
3134 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
2b96a7f1
TI		 3135 dev_dbg(chip->card->dev,
3136 "never read card ready from secondary AC'97\n");
1da177e4
LT		 3137 }
3138#endif
3139
3140 /*
3141 * Assert the vaid frame signal so that we can start sending commands
3142 * to the AC97 codec.
3143 */
3144 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3145#ifdef CONFIG_SND_CS46XX_NEW_DSP
3146 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3147#endif
3148
3149
3150 /*
3151 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3152 * the codec is pumping ADC data across the AC-link.
3153 */
3154 timeout = 150;
3155 while (timeout-- > 0) {
3156 /*
3157 * Read the input slot valid register and see if input slots 3 and
3158 * 4 are valid yet.
3159 */
3160 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3161 goto ok2;
ef21ca24 3162 msleep(10);
1da177e4
LT		 3163 }
3164
3165#ifndef CONFIG_SND_CS46XX_NEW_DSP
2b96a7f1
TI		 3166 dev_err(chip->card->dev,
3167 "create - never read ISV3 & ISV4 from AC'97\n");
1da177e4
LT		 3168 return -EIO;
3169#else
3170 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3171 Reloading the driver may help, if there's other soundcards
3172 with the same problem I would like to know. (Benny) */
3173
2b96a7f1
TI		 3174 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3175 dev_err(chip->card->dev,
3176 "Try reloading the ALSA driver, if you find something\n");
3177 dev_err(chip->card->dev,
3178 "broken or not working on your soundcard upon\n");
3179 dev_err(chip->card->dev,
3180 "this message please report to alsa-devel@alsa-project.org\n");
1da177e4
LT		 3181
3182 return -EIO;
3183#endif
3184 ok2:
3185
3186 /*
3187 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3188 * commense the transfer of digital audio data to the AC97 codec.
3189 */
3190
3191 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3192
3193
3194 /*
3195 * Power down the DAC and ADC. We will power them up (if) when we need
3196 * them.
3197 */
3198 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3199
3200 /*
3201 * Turn off the Processor by turning off the software clock enable flag in
3202 * the clock control register.
3203 */
3204 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3205 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3206
3207 return 0;
3208}
3209
3210/*
3211 * start and load DSP
3212 */
89f157d9
TI		 3213
3214static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3215{
3216 unsigned int tmp;
3217
3218 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3219
3220 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3221 tmp &= ~0x0000f03f;
3222 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3223
3224 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3225 tmp &= ~0x0000003f;
3226 tmp |= 0x00000001;
3227 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3228}
3229
e23e7a14 3230int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
1da177e4
LT		 3231{
3232 unsigned int tmp;
ad233a5f
TI		 3233#ifdef CONFIG_SND_CS46XX_NEW_DSP
3234 int i;
3235#endif
3236 int err;
3237
1da177e4
LT		 3238 /*
3239 * Reset the processor.
3240 */
3241 snd_cs46xx_reset(chip);
3242 /*
3243 * Download the image to the processor.
3244 */
3245#ifdef CONFIG_SND_CS46XX_NEW_DSP
ad233a5f
TI		 3246 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3247 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3248 if (err < 0) {
2b96a7f1 3249 dev_err(chip->card->dev, "firmware load error [%s]\n",
ad233a5f
TI		 3250 module_names[i]);
3251 return err;
3252 }
3253 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3254 if (err < 0) {
2b96a7f1 3255 dev_err(chip->card->dev, "image download error [%s]\n",
ad233a5f
TI		 3256 module_names[i]);
3257 return err;
3258 }
1da177e4
LT		 3259 }
3260
3261 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3262 return -EIO;
3263#else
ad233a5f
TI		 3264 err = load_firmware(chip);
3265 if (err < 0)
3266 return err;
3267
1da177e4 3268 /* old image */
ad233a5f
TI		 3269 err = snd_cs46xx_download_image(chip);
3270 if (err < 0) {
2b96a7f1 3271 dev_err(chip->card->dev, "image download error\n");
ad233a5f 3272 return err;
1da177e4
LT		 3273 }
3274
3275 /*
3276 * Stop playback DMA.
3277 */
3278 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3279 chip->play_ctl = tmp & 0xffff0000;
3280 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3281#endif
3282
3283 /*
3284 * Stop capture DMA.
3285 */
3286 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3287 chip->capt.ctl = tmp & 0x0000ffff;
3288 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3289
3290 mdelay(5);
3291
3292 snd_cs46xx_set_play_sample_rate(chip, 8000);
3293 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3294
3295 snd_cs46xx_proc_start(chip);
3296
89f157d9 3297 cs46xx_enable_stream_irqs(chip);
1da177e4
LT		 3298
3299#ifndef CONFIG_SND_CS46XX_NEW_DSP
3300 /* set the attenuation to 0dB */
3301 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3302 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3303#endif
3304
3305 return 0;
3306}
3307
3308
3309/*
3310 * AMP control - null AMP
3311 */
3312
3d19f804 3313static void amp_none(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3314{
3315}
3316
3317#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 3318static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
1da177e4
LT		 3319{
3320
3321 u32 idx, valid_slots,tmp,powerdown = 0;
3322 u16 modem_power,pin_config,logic_type;
3323
2b96a7f1 3324 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
1da177e4
LT		 3325
3326 /*
3327 * See if the devices are powered down. If so, we must power them up first
3328 * or they will not respond.
3329 */
3330 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3331
3332 if (!(tmp & CLKCR1_SWCE)) {
3333 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3334 powerdown = 1;
3335 }
3336
3337 /*
3338 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3339 * stuff.
3340 */
3341 if(chip->nr_ac97_codecs != 2) {
2b96a7f1
TI		 3342 dev_err(chip->card->dev,
3343 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
1da177e4
LT		 3344 return -EINVAL;
3345 }
3346
3347 modem_power = snd_cs46xx_codec_read (chip,
3348 AC97_EXTENDED_MSTATUS,
3349 CS46XX_SECONDARY_CODEC_INDEX);
3350 modem_power &=0xFEFF;
3351
3352 snd_cs46xx_codec_write(chip,
3353 AC97_EXTENDED_MSTATUS, modem_power,
3354 CS46XX_SECONDARY_CODEC_INDEX);
3355
3356 /*
3357 * Set GPIO pin's 7 and 8 so that they are configured for output.
3358 */
3359 pin_config = snd_cs46xx_codec_read (chip,
3360 AC97_GPIO_CFG,
3361 CS46XX_SECONDARY_CODEC_INDEX);
3362 pin_config &=0x27F;
3363
3364 snd_cs46xx_codec_write(chip,
3365 AC97_GPIO_CFG, pin_config,
3366 CS46XX_SECONDARY_CODEC_INDEX);
3367
3368 /*
3369 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3370 */
3371
3372 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3373 CS46XX_SECONDARY_CODEC_INDEX);
3374 logic_type &=0x27F;
3375
3376 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3377 CS46XX_SECONDARY_CODEC_INDEX);
3378
3379 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3380 valid_slots |= 0x200;
3381 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3382
3383 if ( cs46xx_wait_for_fifo(chip,1) ) {
2b96a7f1 3384 dev_dbg(chip->card->dev, "FIFO is busy\n");
1da177e4
LT		 3385
3386 return -EINVAL;
3387 }
3388
3389 /*
3390 * Fill slots 12 with the correct value for the GPIO pins.
3391 */
3392 for(idx = 0x90; idx <= 0x9F; idx++) {
3393 /*
3394 * Initialize the fifo so that bits 7 and 8 are on.
3395 *
3396 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3397 * the left. 0x1800 corresponds to bits 7 and 8.
3398 */
3399 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3400
3401 /*
3402 * Wait for command to complete
3403 */
3404 if ( cs46xx_wait_for_fifo(chip,200) ) {
2b96a7f1
TI		 3405 dev_dbg(chip->card->dev,
3406 "failed waiting for FIFO at addr (%02X)\n",
3407 idx);
1da177e4
LT		 3408
3409 return -EINVAL;
3410 }
3411
3412 /*
3413 * Write the serial port FIFO index.
3414 */
3415 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3416
3417 /*
3418 * Tell the serial port to load the new value into the FIFO location.
3419 */
3420 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3421 }
3422
3423 /* wait for last command to complete */
3424 cs46xx_wait_for_fifo(chip,200);
3425
3426 /*
3427 * Now, if we powered up the devices, then power them back down again.
3428 * This is kinda ugly, but should never happen.
3429 */
3430 if (powerdown)
3431 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3432
3433 return 0;
3434}
3435#endif
3436
3437/*
3438 * Crystal EAPD mode
3439 */
3440
3d19f804 3441static void amp_voyetra(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3442{
3443 /* Manage the EAPD bit on the Crystal 4297
3444 and the Analog AD1885 */
3445
3446#ifdef CONFIG_SND_CS46XX_NEW_DSP
3447 int old = chip->amplifier;
3448#endif
3449 int oval, val;
3450
3451 chip->amplifier += change;
3452 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3453 CS46XX_PRIMARY_CODEC_INDEX);
3454 val = oval;
3455 if (chip->amplifier) {
3456 /* Turn the EAPD amp on */
3457 val |= 0x8000;
3458 } else {
3459 /* Turn the EAPD amp off */
3460 val &= ~0x8000;
3461 }
3462 if (val != oval) {
3463 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3464 CS46XX_PRIMARY_CODEC_INDEX);
3465 if (chip->eapd_switch)
3466 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3467 &chip->eapd_switch->id);
3468 }
3469
3470#ifdef CONFIG_SND_CS46XX_NEW_DSP
3471 if (chip->amplifier && !old) {
3472 voyetra_setup_eapd_slot(chip);
3473 }
3474#endif
3475}
3476
3d19f804 3477static void hercules_init(struct snd_cs46xx *chip)
1da177e4
LT		 3478{
3479 /* default: AMP off, and SPDIF input optical */
3480 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3481 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3482}
3483
3484
3485/*
3486 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3487 */
3d19f804 3488static void amp_hercules(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3489{
3490 int old = chip->amplifier;
3491 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3492 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3493
3494 chip->amplifier += change;
3495 if (chip->amplifier && !old) {
2b96a7f1 3496 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
1da177e4
LT		 3497
3498 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3499 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3500 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3501 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3502 } else if (old && !chip->amplifier) {
2b96a7f1 3503 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
1da177e4
LT		 3504 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3505 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3506 }
3507}
3508
3d19f804 3509static void voyetra_mixer_init (struct snd_cs46xx *chip)
1da177e4 3510{
2b96a7f1 3511 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
1da177e4
LT		 3512
3513 /* Enable SPDIF out */
3514 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3515 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3516}
3517
3d19f804 3518static void hercules_mixer_init (struct snd_cs46xx *chip)
1da177e4
LT		 3519{
3520#ifdef CONFIG_SND_CS46XX_NEW_DSP
3521 unsigned int idx;
3522 int err;
3d19f804 3523 struct snd_card *card = chip->card;
1da177e4
LT		 3524#endif
3525
3526 /* set EGPIO to default */
3527 hercules_init(chip);
3528
2b96a7f1 3529 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
1da177e4
LT		 3530
3531#ifdef CONFIG_SND_CS46XX_NEW_DSP
f40b6890
TI		 3532 if (chip->in_suspend)
3533 return;
3534
1da177e4 3535 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3d19f804 3536 struct snd_kcontrol *kctl;
1da177e4
LT		 3537
3538 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3539 if ((err = snd_ctl_add(card, kctl)) < 0) {
2b96a7f1
TI		 3540 dev_err(card->dev,
3541 "failed to initialize Hercules mixer (%d)\n",
3542 err);
1da177e4
LT		 3543 break;
3544 }
3545 }
3546#endif
3547}
3548
3549
3550#if 0
3551/*
3552 * Untested
3553 */
3554
3d19f804 3555static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3556{
3557 chip->amplifier += change;
3558
3559 if (chip->amplifier) {
3560 /* Switch the GPIO pins 7 and 8 to open drain */
3561 snd_cs46xx_codec_write(chip, 0x4C,
3562 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3563 snd_cs46xx_codec_write(chip, 0x4E,
3564 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3565 /* Now wake the AMP (this might be backwards) */
3566 snd_cs46xx_codec_write(chip, 0x54,
3567 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3568 } else {
3569 snd_cs46xx_codec_write(chip, 0x54,
3570 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3571 }
3572}
3573#endif
3574
3575
1da177e4
LT		 3576/*
3577 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3578 * whenever we need to beat on the chip.
3579 *
3580 * The original idea and code for this hack comes from David Kaiser at
3581 * Linuxcare. Perhaps one day Crystal will document their chips well
3582 * enough to make them useful.
3583 */
3584
3d19f804 3585static void clkrun_hack(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3586{
3587 u16 control, nval;
3588
0dd119f7 3589 if (!chip->acpi_port)
1da177e4
LT		 3590 return;
3591
3592 chip->amplifier += change;
3593
3594 /* Read ACPI port */
3595 nval = control = inw(chip->acpi_port + 0x10);
3596
3597 /* Flip CLKRUN off while running */
3598 if (! chip->amplifier)
3599 nval |= 0x2000;
3600 else
3601 nval &= ~0x2000;
3602 if (nval != control)
3603 outw(nval, chip->acpi_port + 0x10);
3604}
3605
3606
3607/*
3608 * detect intel piix4
3609 */
3d19f804 3610static void clkrun_init(struct snd_cs46xx *chip)
1da177e4 3611{
0dd119f7 3612 struct pci_dev *pdev;
1da177e4
LT		 3613 u8 pp;
3614
0dd119f7
JS		 3615 chip->acpi_port = 0;
3616
3617 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3618 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3619 if (pdev == NULL)
1da177e4
LT		 3620 return; /* Not a thinkpad thats for sure */
3621
3622 /* Find the control port */
0dd119f7 3623 pci_read_config_byte(pdev, 0x41, &pp);
1da177e4 3624 chip->acpi_port = pp << 8;
0dd119f7 3625 pci_dev_put(pdev);
1da177e4
LT		 3626}
3627
3628
3629/*
3630 * Card subid table
3631 */
3632
3633struct cs_card_type
3634{
3635 u16 vendor;
3636 u16 id;
3637 char *name;
3d19f804
TI		 3638 void (*init)(struct snd_cs46xx *);
3639 void (*amp)(struct snd_cs46xx *, int);
3640 void (*active)(struct snd_cs46xx *, int);
3641 void (*mixer_init)(struct snd_cs46xx *);
1da177e4
LT		 3642};
3643
e23e7a14 3644static struct cs_card_type cards[] = {
1da177e4
LT		 3645 {
3646 .vendor = 0x1489,
3647 .id = 0x7001,
3648 .name = "Genius Soundmaker 128 value",
3649 /* nothing special */
3650 },
3651 {
3652 .vendor = 0x5053,
3653 .id = 0x3357,
3654 .name = "Voyetra",
3655 .amp = amp_voyetra,
3656 .mixer_init = voyetra_mixer_init,
3657 },
3658 {
3659 .vendor = 0x1071,
3660 .id = 0x6003,
3661 .name = "Mitac MI6020/21",
3662 .amp = amp_voyetra,
3663 },
b636a1d9 3664 /* Hercules Game Theatre XP */
1da177e4 3665 {
b636a1d9 3666 .vendor = 0x14af, /* Guillemot Corporation */
1da177e4
LT		 3667 .id = 0x0050,
3668 .name = "Hercules Game Theatre XP",
3669 .amp = amp_hercules,
3670 .mixer_init = hercules_mixer_init,
3671 },
3672 {
3673 .vendor = 0x1681,
3674 .id = 0x0050,
3675 .name = "Hercules Game Theatre XP",
3676 .amp = amp_hercules,
3677 .mixer_init = hercules_mixer_init,
3678 },
3679 {
3680 .vendor = 0x1681,
3681 .id = 0x0051,
3682 .name = "Hercules Game Theatre XP",
3683 .amp = amp_hercules,
3684 .mixer_init = hercules_mixer_init,
3685
3686 },
3687 {
3688 .vendor = 0x1681,
3689 .id = 0x0052,
3690 .name = "Hercules Game Theatre XP",
3691 .amp = amp_hercules,
3692 .mixer_init = hercules_mixer_init,
3693 },
3694 {
3695 .vendor = 0x1681,
3696 .id = 0x0053,
3697 .name = "Hercules Game Theatre XP",
3698 .amp = amp_hercules,
3699 .mixer_init = hercules_mixer_init,
3700 },
3701 {
3702 .vendor = 0x1681,
3703 .id = 0x0054,
3704 .name = "Hercules Game Theatre XP",
3705 .amp = amp_hercules,
3706 .mixer_init = hercules_mixer_init,
3707 },
b636a1d9
VM		 3708 /* Herculess Fortissimo */
3709 {
3710 .vendor = 0x1681,
3711 .id = 0xa010,
3712 .name = "Hercules Gamesurround Fortissimo II",
3713 },
3714 {
3715 .vendor = 0x1681,
3716 .id = 0xa011,
3717 .name = "Hercules Gamesurround Fortissimo III 7.1",
3718 },
1da177e4 3719 /* Teratec */
b636a1d9
VM		 3720 {
3721 .vendor = 0x153b,
3722 .id = 0x112e,
3723 .name = "Terratec DMX XFire 1024",
3724 },
1da177e4
LT		 3725 {
3726 .vendor = 0x153b,
3727 .id = 0x1136,
3728 .name = "Terratec SiXPack 5.1",
3729 },
3730 /* Not sure if the 570 needs the clkrun hack */
3731 {
3732 .vendor = PCI_VENDOR_ID_IBM,
3733 .id = 0x0132,
3734 .name = "Thinkpad 570",
3735 .init = clkrun_init,
3736 .active = clkrun_hack,
3737 },
3738 {
3739 .vendor = PCI_VENDOR_ID_IBM,
3740 .id = 0x0153,
3741 .name = "Thinkpad 600X/A20/T20",
3742 .init = clkrun_init,
3743 .active = clkrun_hack,
3744 },
3745 {
3746 .vendor = PCI_VENDOR_ID_IBM,
3747 .id = 0x1010,
3748 .name = "Thinkpad 600E (unsupported)",
3749 },
3750 {} /* terminator */
3751};
3752
3753
3754/*
3755 * APM support
3756 */
c7561cd8 3757#ifdef CONFIG_PM_SLEEP
89f157d9
TI		 3758static unsigned int saved_regs[] = {
3759 BA0_ACOSV,
41116e92 3760 /*BA0_ASER_FADDR,*/
89f157d9
TI		 3761 BA0_ASER_MASTER,
3762 BA1_PVOL,
3763 BA1_CVOL,
3764};
3765
68cb2b55 3766static int snd_cs46xx_suspend(struct device *dev)
1da177e4 3767{
68cb2b55 3768 struct snd_card *card = dev_get_drvdata(dev);
cb28e45b 3769 struct snd_cs46xx *chip = card->private_data;
89f157d9 3770 int i, amp_saved;
1da177e4 3771
cb28e45b 3772 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
f40b6890 3773 chip->in_suspend = 1;
1da177e4
LT		 3774 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3775 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3776
3777 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
cb28e45b 3778 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
1da177e4 3779
89f157d9
TI		 3780 /* save some registers */
3781 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3782 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3783
1da177e4
LT		 3784 amp_saved = chip->amplifier;
3785 /* turn off amp */
3786 chip->amplifier_ctrl(chip, -chip->amplifier);
3787 snd_cs46xx_hw_stop(chip);
3788 /* disable CLKRUN */
3789 chip->active_ctrl(chip, -chip->amplifier);
3790 chip->amplifier = amp_saved; /* restore the status */
1da177e4
LT		 3791 return 0;
3792}
3793
68cb2b55 3794static int snd_cs46xx_resume(struct device *dev)
1da177e4 3795{
68cb2b55 3796 struct snd_card *card = dev_get_drvdata(dev);
cb28e45b 3797 struct snd_cs46xx *chip = card->private_data;
480cf663
TI		 3798 int amp_saved;
3799#ifdef CONFIG_SND_CS46XX_NEW_DSP
3800 int i;
3801#endif
cf944ee5 3802 unsigned int tmp;
1da177e4 3803
1da177e4
LT		 3804 amp_saved = chip->amplifier;
3805 chip->amplifier = 0;
3806 chip->active_ctrl(chip, 1); /* force to on */
3807
3808 snd_cs46xx_chip_init(chip);
3809
89f157d9
TI		 3810 snd_cs46xx_reset(chip);
3811#ifdef CONFIG_SND_CS46XX_NEW_DSP
3812 cs46xx_dsp_resume(chip);
3813 /* restore some registers */
3814 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3815 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3816#else
3817 snd_cs46xx_download_image(chip);
3818#endif
3819
1da177e4
LT		 3820#if 0
3821 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3822 chip->ac97_general_purpose);
3823 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3824 chip->ac97_powerdown);
3825 mdelay(10);
3826 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3827 chip->ac97_powerdown);
3828 mdelay(5);
3829#endif
3830
3831 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
cb28e45b 3832 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
1da177e4 3833
cf944ee5
FZ		 3834 /*
3835 * Stop capture DMA.
3836 */
3837 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3838 chip->capt.ctl = tmp & 0x0000ffff;
3839 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3840
3841 mdelay(5);
3842
89f157d9
TI		 3843 /* reset playback/capture */
3844 snd_cs46xx_set_play_sample_rate(chip, 8000);
3845 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3846 snd_cs46xx_proc_start(chip);
3847
3848 cs46xx_enable_stream_irqs(chip);
3849
1da177e4
LT		 3850 if (amp_saved)
3851 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3852 else
3853 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3854 chip->amplifier = amp_saved;
f40b6890 3855 chip->in_suspend = 0;
cb28e45b 3856 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 3857 return 0;
3858}
68cb2b55
TI		 3859
3860SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
c7561cd8 3861#endif /* CONFIG_PM_SLEEP */
1da177e4
LT		 3862
3863
3864/*
3865 */
3866
e23e7a14
BP		 3867int snd_cs46xx_create(struct snd_card *card,
3868 struct pci_dev *pci,
1da177e4 3869 int external_amp, int thinkpad,
e23e7a14 3870 struct snd_cs46xx **rchip)
1da177e4 3871{
3d19f804 3872 struct snd_cs46xx *chip;
1da177e4 3873 int err, idx;
3d19f804 3874 struct snd_cs46xx_region *region;
1da177e4
LT		 3875 struct cs_card_type *cp;
3876 u16 ss_card, ss_vendor;
3d19f804 3877 static struct snd_device_ops ops = {
1da177e4
LT		 3878 .dev_free = snd_cs46xx_dev_free,
3879 };
3880
3881 *rchip = NULL;
3882
3883 /* enable PCI device */
3884 if ((err = pci_enable_device(pci)) < 0)
3885 return err;
3886
e560d8d8 3887 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 3888 if (chip == NULL) {
3889 pci_disable_device(pci);
3890 return -ENOMEM;
3891 }
3892 spin_lock_init(&chip->reg_lock);
3893#ifdef CONFIG_SND_CS46XX_NEW_DSP
62932df8 3894 mutex_init(&chip->spos_mutex);
1da177e4
LT		 3895#endif
3896 chip->card = card;
3897 chip->pci = pci;
3898 chip->irq = -1;
3899 chip->ba0_addr = pci_resource_start(pci, 0);
3900 chip->ba1_addr = pci_resource_start(pci, 1);
3901 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3902 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
2b96a7f1
TI		 3903 dev_err(chip->card->dev,
3904 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3d19f804 3905 chip->ba0_addr, chip->ba1_addr);
1da177e4
LT		 3906 snd_cs46xx_free(chip);
3907 return -ENOMEM;
3908 }
3909
3910 region = &chip->region.name.ba0;
3911 strcpy(region->name, "CS46xx_BA0");
3912 region->base = chip->ba0_addr;
3913 region->size = CS46XX_BA0_SIZE;
3914
3915 region = &chip->region.name.data0;
3916 strcpy(region->name, "CS46xx_BA1_data0");
3917 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3918 region->size = CS46XX_BA1_DATA0_SIZE;
3919
3920 region = &chip->region.name.data1;
3921 strcpy(region->name, "CS46xx_BA1_data1");
3922 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3923 region->size = CS46XX_BA1_DATA1_SIZE;
3924
3925 region = &chip->region.name.pmem;
3926 strcpy(region->name, "CS46xx_BA1_pmem");
3927 region->base = chip->ba1_addr + BA1_SP_PMEM;
3928 region->size = CS46XX_BA1_PRG_SIZE;
3929
3930 region = &chip->region.name.reg;
3931 strcpy(region->name, "CS46xx_BA1_reg");
3932 region->base = chip->ba1_addr + BA1_SP_REG;
3933 region->size = CS46XX_BA1_REG_SIZE;
3934
3935 /* set up amp and clkrun hack */
3936 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3937 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3938
3939 for (cp = &cards[0]; cp->name; cp++) {
3940 if (cp->vendor == ss_vendor && cp->id == ss_card) {
2b96a7f1
TI		 3941 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3942 cp->name);
1da177e4
LT		 3943
3944 chip->amplifier_ctrl = cp->amp;
3945 chip->active_ctrl = cp->active;
3946 chip->mixer_init = cp->mixer_init;
3947
3948 if (cp->init)
3949 cp->init(chip);
3950 break;
3951 }
3952 }
3953
3954 if (external_amp) {
2b96a7f1
TI		 3955 dev_info(chip->card->dev,
3956 "Crystal EAPD support forced on.\n");
1da177e4
LT		 3957 chip->amplifier_ctrl = amp_voyetra;
3958 }
3959
3960 if (thinkpad) {
2b96a7f1
TI		 3961 dev_info(chip->card->dev,
3962 "Activating CLKRUN hack for Thinkpad.\n");
1da177e4
LT		 3963 chip->active_ctrl = clkrun_hack;
3964 clkrun_init(chip);
3965 }
3966
3967 if (chip->amplifier_ctrl == NULL)
3968 chip->amplifier_ctrl = amp_none;
3969 if (chip->active_ctrl == NULL)
3970 chip->active_ctrl = amp_none;
3971
3972 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3973
3974 pci_set_master(pci);
3975
3976 for (idx = 0; idx < 5; idx++) {
3977 region = &chip->region.idx[idx];
3d19f804
TI		 3978 if ((region->resource = request_mem_region(region->base, region->size,
3979 region->name)) == NULL) {
2b96a7f1
TI		 3980 dev_err(chip->card->dev,
3981 "unable to request memory region 0x%lx-0x%lx\n",
3d19f804 3982 region->base, region->base + region->size - 1);
1da177e4
LT		 3983 snd_cs46xx_free(chip);
3984 return -EBUSY;
3985 }
3986 region->remap_addr = ioremap_nocache(region->base, region->size);
3987 if (region->remap_addr == NULL) {
2b96a7f1
TI		 3988 dev_err(chip->card->dev,
3989 "%s ioremap problem\n", region->name);
1da177e4
LT		 3990 snd_cs46xx_free(chip);
3991 return -ENOMEM;
3992 }
3993 }
3994
437a5a46 3995 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
934c2b6d 3996 KBUILD_MODNAME, chip)) {
2b96a7f1 3997 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 3998 snd_cs46xx_free(chip);
3999 return -EBUSY;
4000 }
4001 chip->irq = pci->irq;
4002
4003#ifdef CONFIG_SND_CS46XX_NEW_DSP
4004 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
4005 if (chip->dsp_spos_instance == NULL) {
4006 snd_cs46xx_free(chip);
4007 return -ENOMEM;
4008 }
4009#endif
4010
4011 err = snd_cs46xx_chip_init(chip);
4012 if (err < 0) {
4013 snd_cs46xx_free(chip);
4014 return err;
4015 }
4016
4017 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4018 snd_cs46xx_free(chip);
4019 return err;
4020 }
4021
4022 snd_cs46xx_proc_init(card, chip);
4023
c7561cd8 4024#ifdef CONFIG_PM_SLEEP
6da2ec56
KC		 4025 chip->saved_regs = kmalloc_array(ARRAY_SIZE(saved_regs),
4026 sizeof(*chip->saved_regs),
4027 GFP_KERNEL);
89f157d9
TI		 4028 if (!chip->saved_regs) {
4029 snd_cs46xx_free(chip);
4030 return -ENOMEM;
4031 }
4032#endif
4033
1da177e4
LT		 4034 chip->active_ctrl(chip, -1); /* disable CLKRUN */
4035
1da177e4
LT		 4036 *rchip = chip;
4037 return 0;
4038}
Linux 6.x block layer and io_uring tree(s)