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Merge branch 'work.file' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux-2.6-block.git] / sound / pci / cs4281.c
CommitLineData
1da177e4
LT		 1/*
2 * Driver for Cirrus Logic CS4281 based PCI soundcard
c1017a4c 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
1da177e4
LT		 4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
6cbbfe1c 22#include <linux/io.h>
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/pci.h>
27#include <linux/slab.h>
28#include <linux/gameport.h>
65a77217 29#include <linux/module.h>
1da177e4
LT		 30#include <sound/core.h>
31#include <sound/control.h>
32#include <sound/pcm.h>
33#include <sound/rawmidi.h>
34#include <sound/ac97_codec.h>
9f6ab250 35#include <sound/tlv.h>
1da177e4
LT		 36#include <sound/opl3.h>
37#include <sound/initval.h>
38
39
c1017a4c 40MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
1da177e4
LT		 41MODULE_DESCRIPTION("Cirrus Logic CS4281");
42MODULE_LICENSE("GPL");
43MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
44
45static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
46static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5
RR		 47static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
48static bool dual_codec[SNDRV_CARDS]; /* dual codec */
1da177e4
LT		 49
50module_param_array(index, int, NULL, 0444);
51MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
52module_param_array(id, charp, NULL, 0444);
53MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
54module_param_array(enable, bool, NULL, 0444);
55MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
56module_param_array(dual_codec, bool, NULL, 0444);
57MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
58
1da177e4
LT		 59/*
60 * Direct registers
61 */
62
63#define CS4281_BA0_SIZE 0x1000
64#define CS4281_BA1_SIZE 0x10000
65
66/*
67 * BA0 registers
68 */
69#define BA0_HISR 0x0000 /* Host Interrupt Status Register */
70#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
71#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
72#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
73#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
74#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
75#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
76#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
77#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
78#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
79#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
80#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
81#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
82
83#define BA0_HICR 0x0008 /* Host Interrupt Control Register */
84#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
85#define BA0_HICR_IEV (1<<0) /* INTENA Value */
86#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
87
88#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
89 /* Use same contants as for BA0_HISR */
90
91#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
92
93#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
94#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
95#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
96#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
97
98#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
99#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
100#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
101#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
102#define BA0_HDSR_DRUN (1<<15) /* DMA Running */
103#define BA0_HDSR_RQ (1<<7) /* Pending Request */
104
105#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
106#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
107#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
108#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
109#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
110#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
111#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
112#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
113#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
114#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
115#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
116#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
117#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
118#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
119#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
120#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
121#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
122#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
123#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
124#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
125#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
126#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
127#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
128#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
129
130#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
131#define BA0_DMR_POLL (1<<28) /* Enable poll mode */
132#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
133#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
134#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
135#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
136#define BA0_DMR_USIGN (1<<19) /* Unsigned */
137#define BA0_DMR_BEND (1<<18) /* Big Endian */
138#define BA0_DMR_MONO (1<<17) /* Mono */
139#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
140#define BA0_DMR_TYPE_DEMAND (0<<6)
141#define BA0_DMR_TYPE_SINGLE (1<<6)
142#define BA0_DMR_TYPE_BLOCK (2<<6)
143#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
144#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
145#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
146#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
147#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
148#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
149
150#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
151#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
152#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
153
154#define BA0_FCR0 0x0180 /* FIFO Control 0 */
155#define BA0_FCR1 0x0184 /* FIFO Control 1 */
156#define BA0_FCR2 0x0188 /* FIFO Control 2 */
157#define BA0_FCR3 0x018c /* FIFO Control 3 */
158
159#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
160#define BA0_FCR_DACZ (1<<30) /* DAC Zero */
161#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
162#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
163#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
164#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
165#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
166
167#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
168#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
169#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
170#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
171
172#define BA0_FCHS 0x020c /* FIFO Channel Status */
173#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
174#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
175#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
176#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
177#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
178#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
179#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
180#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
181
182#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
183#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
184#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
185#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
186
187#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
188#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
189#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
190#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
191#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
192#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
193#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
194#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
195
196#define BA0_PMCS 0x0344 /* Power Management Control/Status */
197#define BA0_CWPR 0x03e0 /* Configuration Write Protect */
a488e033 198
1da177e4 199#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
a488e033
AP		 200#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
201
1da177e4
LT		 202#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
203
204#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
205#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
206#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
207#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
208#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
209#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
210#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
211#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
212#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
213#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
214
215#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
216#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
217#define BA0_IISR 0x03f4 /* ISA Interrupt Select */
218#define BA0_TMS 0x03f8 /* Test Register */
219#define BA0_SSVID 0x03fc /* Subsystem ID register */
220
221#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
222#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
223#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
224#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
225#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
226#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
227#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
228
229#define BA0_FRR 0x0410 /* Feature Reporting Register */
230#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
231
232#define BA0_SERMC 0x0420 /* Serial Port Master Control */
233#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
234#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
235#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
236#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
237#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
238#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
239#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
240#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
241#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
242#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
243#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
244#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
245
246#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
247#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
248#define BA0_SERC1_AC97 (1<<1)
249#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
250
251#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
252#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
253#define BA0_SERC2_AC97 (1<<1)
254#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
255
256#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
257
258#define BA0_ACCTL 0x0460 /* AC'97 Control */
259#define BA0_ACCTL_TC (1<<6) /* Target Codec */
260#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
261#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
262#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
263#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
264
265#define BA0_ACSTS 0x0464 /* AC'97 Status */
266#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
267#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
268
269#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
270#define BA0_ACOSV_SLV(x) (1<<((x)-3))
271
272#define BA0_ACCAD 0x046c /* AC'97 Command Address */
273#define BA0_ACCDA 0x0470 /* AC'97 Command Data */
274
275#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
276#define BA0_ACISV_SLV(x) (1<<((x)-3))
277
278#define BA0_ACSAD 0x0478 /* AC'97 Status Address */
279#define BA0_ACSDA 0x047c /* AC'97 Status Data */
280#define BA0_JSPT 0x0480 /* Joystick poll/trigger */
281#define BA0_JSCTL 0x0484 /* Joystick control */
282#define BA0_JSC1 0x0488 /* Joystick control */
283#define BA0_JSC2 0x048c /* Joystick control */
284#define BA0_JSIO 0x04a0
285
286#define BA0_MIDCR 0x0490 /* MIDI Control */
287#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
288#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
289#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
290#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
291#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
292#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
293
294#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
295
296#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
297#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
298#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
299#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
300#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
301
302#define BA0_MIDWP 0x0498 /* MIDI Write */
303#define BA0_MIDRP 0x049c /* MIDI Read (ro) */
304
305#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
306#define BA0_AODSD1_NDS(x) (1<<((x)-3))
307
308#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
309#define BA0_AODSD2_NDS(x) (1<<((x)-3))
310
311#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
312#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
313#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
314#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
315#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
316#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
317#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
318#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
319#define BA0_FMDP 0x0734 /* FM Data Port */
320#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
321#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
322
323#define BA0_SSPM 0x0740 /* Sound System Power Management */
324#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
325#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
326#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
327#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
328#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
329#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
330
331#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
332#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
333
334#define BA0_SSCR 0x074c /* Sound System Control Register */
335#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
336#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
337#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
338#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
339#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
340#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
341#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
342#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
343#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
344
345#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
346#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
347#define BA0_SRCSA 0x075c /* SRC Slot Assignments */
348#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
349#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
350#define BA0_PASR 0x0768 /* playback sample rate */
351#define BA0_CASR 0x076C /* capture sample rate */
352
353/* Source Slot Numbers - Playback */
354#define SRCSLOT_LEFT_PCM_PLAYBACK 0
355#define SRCSLOT_RIGHT_PCM_PLAYBACK 1
356#define SRCSLOT_PHONE_LINE_1_DAC 2
357#define SRCSLOT_CENTER_PCM_PLAYBACK 3
358#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
359#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
360#define SRCSLOT_LFE_PCM_PLAYBACK 6
361#define SRCSLOT_PHONE_LINE_2_DAC 7
362#define SRCSLOT_HEADSET_DAC 8
363#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
364#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
365
366/* Source Slot Numbers - Capture */
367#define SRCSLOT_LEFT_PCM_RECORD 10
368#define SRCSLOT_RIGHT_PCM_RECORD 11
369#define SRCSLOT_PHONE_LINE_1_ADC 12
370#define SRCSLOT_MIC_ADC 13
371#define SRCSLOT_PHONE_LINE_2_ADC 17
372#define SRCSLOT_HEADSET_ADC 18
373#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
374#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
375#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
376#define SRCSLOT_SECONDARY_MIC_ADC 23
377#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
378#define SRCSLOT_SECONDARY_HEADSET_ADC 28
379
380/* Source Slot Numbers - Others */
381#define SRCSLOT_POWER_DOWN 31
382
383/* MIDI modes */
384#define CS4281_MODE_OUTPUT (1<<0)
385#define CS4281_MODE_INPUT (1<<1)
386
387/* joystick bits */
388/* Bits for JSPT */
389#define JSPT_CAX 0x00000001
390#define JSPT_CAY 0x00000002
391#define JSPT_CBX 0x00000004
392#define JSPT_CBY 0x00000008
393#define JSPT_BA1 0x00000010
394#define JSPT_BA2 0x00000020
395#define JSPT_BB1 0x00000040
396#define JSPT_BB2 0x00000080
397
398/* Bits for JSCTL */
399#define JSCTL_SP_MASK 0x00000003
400#define JSCTL_SP_SLOW 0x00000000
401#define JSCTL_SP_MEDIUM_SLOW 0x00000001
402#define JSCTL_SP_MEDIUM_FAST 0x00000002
403#define JSCTL_SP_FAST 0x00000003
404#define JSCTL_ARE 0x00000004
405
406/* Data register pairs masks */
407#define JSC1_Y1V_MASK 0x0000FFFF
408#define JSC1_X1V_MASK 0xFFFF0000
409#define JSC1_Y1V_SHIFT 0
410#define JSC1_X1V_SHIFT 16
411#define JSC2_Y2V_MASK 0x0000FFFF
412#define JSC2_X2V_MASK 0xFFFF0000
413#define JSC2_Y2V_SHIFT 0
414#define JSC2_X2V_SHIFT 16
415
416/* JS GPIO */
417#define JSIO_DAX 0x00000001
418#define JSIO_DAY 0x00000002
419#define JSIO_DBX 0x00000004
420#define JSIO_DBY 0x00000008
421#define JSIO_AXOE 0x00000010
422#define JSIO_AYOE 0x00000020
423#define JSIO_BXOE 0x00000040
424#define JSIO_BYOE 0x00000080
425
426/*
427 *
428 */
429
93e35f95
TI		 430struct cs4281_dma {
431 struct snd_pcm_substream *substream;
1da177e4
LT		 432 unsigned int regDBA; /* offset to DBA register */
433 unsigned int regDCA; /* offset to DCA register */
434 unsigned int regDBC; /* offset to DBC register */
435 unsigned int regDCC; /* offset to DCC register */
436 unsigned int regDMR; /* offset to DMR register */
437 unsigned int regDCR; /* offset to DCR register */
438 unsigned int regHDSR; /* offset to HDSR register */
439 unsigned int regFCR; /* offset to FCR register */
440 unsigned int regFSIC; /* offset to FSIC register */
441 unsigned int valDMR; /* DMA mode */
442 unsigned int valDCR; /* DMA command */
443 unsigned int valFCR; /* FIFO control */
444 unsigned int fifo_offset; /* FIFO offset within BA1 */
445 unsigned char left_slot; /* FIFO left slot */
446 unsigned char right_slot; /* FIFO right slot */
447 int frag; /* period number */
448};
449
450#define SUSPEND_REGISTERS 20
451
93e35f95 452struct cs4281 {
1da177e4
LT		 453 int irq;
454
455 void __iomem *ba0; /* virtual (accessible) address */
456 void __iomem *ba1; /* virtual (accessible) address */
457 unsigned long ba0_addr;
458 unsigned long ba1_addr;
459
460 int dual_codec;
461
93e35f95
TI		 462 struct snd_ac97_bus *ac97_bus;
463 struct snd_ac97 *ac97;
464 struct snd_ac97 *ac97_secondary;
1da177e4
LT		 465
466 struct pci_dev *pci;
93e35f95
TI		 467 struct snd_card *card;
468 struct snd_pcm *pcm;
469 struct snd_rawmidi *rmidi;
470 struct snd_rawmidi_substream *midi_input;
471 struct snd_rawmidi_substream *midi_output;
1da177e4 472
93e35f95 473 struct cs4281_dma dma[4];
1da177e4
LT		 474
475 unsigned char src_left_play_slot;
476 unsigned char src_right_play_slot;
477 unsigned char src_left_rec_slot;
478 unsigned char src_right_rec_slot;
479
480 unsigned int spurious_dhtc_irq;
481 unsigned int spurious_dtc_irq;
482
483 spinlock_t reg_lock;
484 unsigned int midcr;
485 unsigned int uartm;
486
487 struct gameport *gameport;
488
c7561cd8 489#ifdef CONFIG_PM_SLEEP
1da177e4
LT		 490 u32 suspend_regs[SUSPEND_REGISTERS];
491#endif
492
493};
494
7d12e780 495static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
1da177e4 496
9baa3c34 497static const struct pci_device_id snd_cs4281_ids[] = {
28d27aae 498 { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */
1da177e4
LT		 499 { 0, }
500};
501
502MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
503
504/*
505 * constants
506 */
507
508#define CS4281_FIFO_SIZE 32
509
510/*
511 * common I/O routines
512 */
513
93e35f95
TI		 514static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
515 unsigned int val)
1da177e4
LT		 516{
517 writel(val, chip->ba0 + offset);
518}
519
93e35f95 520static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
1da177e4
LT		 521{
522 return readl(chip->ba0 + offset);
523}
524
93e35f95 525static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 526 unsigned short reg, unsigned short val)
527{
528 /*
529 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
530 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
531 * 3. Write ACCTL = Control Register = 460h for initiating the write
532 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
533 * 5. if DCV not cleared, break and return error
534 */
93e35f95 535 struct cs4281 *chip = ac97->private_data;
1da177e4
LT		 536 int count;
537
538 /*
539 * Setup the AC97 control registers on the CS461x to send the
540 * appropriate command to the AC97 to perform the read.
541 * ACCAD = Command Address Register = 46Ch
542 * ACCDA = Command Data Register = 470h
543 * ACCTL = Control Register = 460h
544 * set DCV - will clear when process completed
545 * reset CRW - Write command
546 * set VFRM - valid frame enabled
547 * set ESYN - ASYNC generation enabled
548 * set RSTN - ARST# inactive, AC97 codec not reset
549 */
550 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
551 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
552 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
553 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
554 for (count = 0; count < 2000; count++) {
555 /*
556 * First, we want to wait for a short time.
557 */
558 udelay(10);
559 /*
560 * Now, check to see if the write has completed.
561 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
562 */
563 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
564 return;
565 }
566 }
b055e7b4
TI		 567 dev_err(chip->card->dev,
568 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
1da177e4
LT		 569}
570
93e35f95 571static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
1da177e4
LT		 572 unsigned short reg)
573{
93e35f95 574 struct cs4281 *chip = ac97->private_data;
1da177e4
LT		 575 int count;
576 unsigned short result;
577 // FIXME: volatile is necessary in the following due to a bug of
578 // some gcc versions
93e35f95 579 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
1da177e4
LT		 580
581 /*
582 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
583 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
584 * 3. Write ACCTL = Control Register = 460h for initiating the write
585 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
586 * 5. if DCV not cleared, break and return error
587 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
588 */
589
590 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
591
592 /*
593 * Setup the AC97 control registers on the CS461x to send the
594 * appropriate command to the AC97 to perform the read.
595 * ACCAD = Command Address Register = 46Ch
596 * ACCDA = Command Data Register = 470h
597 * ACCTL = Control Register = 460h
598 * set DCV - will clear when process completed
599 * set CRW - Read command
600 * set VFRM - valid frame enabled
601 * set ESYN - ASYNC generation enabled
602 * set RSTN - ARST# inactive, AC97 codec not reset
603 */
604
605 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
606 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
607 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
608 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
609 (ac97_num ? BA0_ACCTL_TC : 0));
610
611
612 /*
613 * Wait for the read to occur.
614 */
615 for (count = 0; count < 500; count++) {
616 /*
617 * First, we want to wait for a short time.
618 */
619 udelay(10);
620 /*
621 * Now, check to see if the read has completed.
622 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
623 */
624 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
625 goto __ok1;
626 }
627
b055e7b4
TI		 628 dev_err(chip->card->dev,
629 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
1da177e4
LT		 630 result = 0xffff;
631 goto __end;
632
633 __ok1:
634 /*
635 * Wait for the valid status bit to go active.
636 */
637 for (count = 0; count < 100; count++) {
638 /*
639 * Read the AC97 status register.
640 * ACSTS = Status Register = 464h
641 * VSTS - Valid Status
642 */
643 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
644 goto __ok2;
645 udelay(10);
646 }
647
b055e7b4
TI		 648 dev_err(chip->card->dev,
649 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
1da177e4
LT		 650 result = 0xffff;
651 goto __end;
652
653 __ok2:
654 /*
655 * Read the data returned from the AC97 register.
656 * ACSDA = Status Data Register = 474h
657 */
658 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
659
660 __end:
661 return result;
662}
663
664/*
665 * PCM part
666 */
667
93e35f95 668static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 669{
93e35f95
TI		 670 struct cs4281_dma *dma = substream->runtime->private_data;
671 struct cs4281 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 672
673 spin_lock(&chip->reg_lock);
674 switch (cmd) {
675 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
676 dma->valDCR |= BA0_DCR_MSK;
677 dma->valFCR |= BA0_FCR_FEN;
678 break;
679 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
680 dma->valDCR &= ~BA0_DCR_MSK;
681 dma->valFCR &= ~BA0_FCR_FEN;
682 break;
683 case SNDRV_PCM_TRIGGER_START:
684 case SNDRV_PCM_TRIGGER_RESUME:
685 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
686 dma->valDMR |= BA0_DMR_DMA;
687 dma->valDCR &= ~BA0_DCR_MSK;
688 dma->valFCR |= BA0_FCR_FEN;
689 break;
690 case SNDRV_PCM_TRIGGER_STOP:
691 case SNDRV_PCM_TRIGGER_SUSPEND:
692 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
693 dma->valDCR |= BA0_DCR_MSK;
694 dma->valFCR &= ~BA0_FCR_FEN;
695 /* Leave wave playback FIFO enabled for FM */
696 if (dma->regFCR != BA0_FCR0)
697 dma->valFCR &= ~BA0_FCR_FEN;
698 break;
699 default:
700 spin_unlock(&chip->reg_lock);
701 return -EINVAL;
702 }
703 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
704 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
705 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
706 spin_unlock(&chip->reg_lock);
707 return 0;
708}
709
710static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
711{
712 unsigned int val = ~0;
713
714 if (real_rate)
715 *real_rate = rate;
716 /* special "hardcoded" rates */
717 switch (rate) {
718 case 8000: return 5;
719 case 11025: return 4;
720 case 16000: return 3;
721 case 22050: return 2;
722 case 44100: return 1;
723 case 48000: return 0;
724 default:
725 goto __variable;
726 }
727 __variable:
728 val = 1536000 / rate;
729 if (real_rate)
730 *real_rate = 1536000 / val;
731 return val;
732}
733
93e35f95
TI		 734static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
735 struct snd_pcm_runtime *runtime,
736 int capture, int src)
1da177e4
LT		 737{
738 int rec_mono;
739
740 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
741 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
742 if (runtime->channels == 1)
743 dma->valDMR |= BA0_DMR_MONO;
744 if (snd_pcm_format_unsigned(runtime->format) > 0)
745 dma->valDMR |= BA0_DMR_USIGN;
746 if (snd_pcm_format_big_endian(runtime->format) > 0)
747 dma->valDMR |= BA0_DMR_BEND;
748 switch (snd_pcm_format_width(runtime->format)) {
749 case 8: dma->valDMR |= BA0_DMR_SIZE8;
750 if (runtime->channels == 1)
751 dma->valDMR |= BA0_DMR_SWAPC;
752 break;
753 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
754 }
755 dma->frag = 0; /* for workaround */
756 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
757 if (runtime->buffer_size != runtime->period_size)
758 dma->valDCR |= BA0_DCR_HTCIE;
759 /* Initialize DMA */
760 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
761 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
762 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
763 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
764 (chip->src_right_play_slot << 8) |
765 (chip->src_left_rec_slot << 16) |
766 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
767 if (!src)
768 goto __skip_src;
769 if (!capture) {
770 if (dma->left_slot == chip->src_left_play_slot) {
771 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
da3cec35 772 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
1da177e4
LT		 773 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
774 }
775 } else {
776 if (dma->left_slot == chip->src_left_rec_slot) {
777 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
da3cec35 778 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
1da177e4
LT		 779 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
780 }
781 }
782 __skip_src:
783 /* Deactivate wave playback FIFO before changing slot assignments */
784 if (dma->regFCR == BA0_FCR0)
785 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
786 /* Initialize FIFO */
787 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
788 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
789 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
790 BA0_FCR_OF(dma->fifo_offset);
791 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
792 /* Activate FIFO again for FM playback */
793 if (dma->regFCR == BA0_FCR0)
794 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
795 /* Clear FIFO Status and Interrupt Control Register */
796 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
797}
798
93e35f95
TI		 799static int snd_cs4281_hw_params(struct snd_pcm_substream *substream,
800 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 801{
802 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
803}
804
93e35f95 805static int snd_cs4281_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 806{
807 return snd_pcm_lib_free_pages(substream);
808}
809
93e35f95 810static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 811{
93e35f95
TI		 812 struct snd_pcm_runtime *runtime = substream->runtime;
813 struct cs4281_dma *dma = runtime->private_data;
814 struct cs4281 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 815
816 spin_lock_irq(&chip->reg_lock);
817 snd_cs4281_mode(chip, dma, runtime, 0, 1);
818 spin_unlock_irq(&chip->reg_lock);
819 return 0;
820}
821
93e35f95 822static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 823{
93e35f95
TI		 824 struct snd_pcm_runtime *runtime = substream->runtime;
825 struct cs4281_dma *dma = runtime->private_data;
826 struct cs4281 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 827
828 spin_lock_irq(&chip->reg_lock);
829 snd_cs4281_mode(chip, dma, runtime, 1, 1);
830 spin_unlock_irq(&chip->reg_lock);
831 return 0;
832}
833
93e35f95 834static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
1da177e4 835{
93e35f95
TI		 836 struct snd_pcm_runtime *runtime = substream->runtime;
837 struct cs4281_dma *dma = runtime->private_data;
838 struct cs4281 *chip = snd_pcm_substream_chip(substream);
1da177e4 839
ee419653 840 /*
b055e7b4
TI		 841 dev_dbg(chip->card->dev,
842 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
843 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
ee419653
TI		 844 jiffies);
845 */
1da177e4
LT		 846 return runtime->buffer_size -
847 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
848}
849
dee49895 850static const struct snd_pcm_hardware snd_cs4281_playback =
1da177e4 851{
b83f346b
CL		 852 .info = SNDRV_PCM_INFO_MMAP |
853 SNDRV_PCM_INFO_INTERLEAVED |
854 SNDRV_PCM_INFO_MMAP_VALID |
855 SNDRV_PCM_INFO_PAUSE |
856 SNDRV_PCM_INFO_RESUME,
1da177e4
LT		 857 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
858 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
859 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
860 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
861 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
862 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
863 .rate_min = 4000,
864 .rate_max = 48000,
865 .channels_min = 1,
866 .channels_max = 2,
867 .buffer_bytes_max = (512*1024),
868 .period_bytes_min = 64,
869 .period_bytes_max = (512*1024),
870 .periods_min = 1,
871 .periods_max = 2,
872 .fifo_size = CS4281_FIFO_SIZE,
873};
874
dee49895 875static const struct snd_pcm_hardware snd_cs4281_capture =
1da177e4 876{
b83f346b
CL		 877 .info = SNDRV_PCM_INFO_MMAP |
878 SNDRV_PCM_INFO_INTERLEAVED |
879 SNDRV_PCM_INFO_MMAP_VALID |
880 SNDRV_PCM_INFO_PAUSE |
881 SNDRV_PCM_INFO_RESUME,
1da177e4
LT		 882 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
883 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
884 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
885 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
886 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
887 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
888 .rate_min = 4000,
889 .rate_max = 48000,
890 .channels_min = 1,
891 .channels_max = 2,
892 .buffer_bytes_max = (512*1024),
893 .period_bytes_min = 64,
894 .period_bytes_max = (512*1024),
895 .periods_min = 1,
896 .periods_max = 2,
897 .fifo_size = CS4281_FIFO_SIZE,
898};
899
93e35f95 900static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
1da177e4 901{
93e35f95
TI		 902 struct cs4281 *chip = snd_pcm_substream_chip(substream);
903 struct snd_pcm_runtime *runtime = substream->runtime;
904 struct cs4281_dma *dma;
1da177e4
LT		 905
906 dma = &chip->dma[0];
907 dma->substream = substream;
908 dma->left_slot = 0;
909 dma->right_slot = 1;
910 runtime->private_data = dma;
911 runtime->hw = snd_cs4281_playback;
1da177e4
LT		 912 /* should be detected from the AC'97 layer, but it seems
913 that although CS4297A rev B reports 18-bit ADC resolution,
914 samples are 20-bit */
915 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
916 return 0;
917}
918
93e35f95 919static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
1da177e4 920{
93e35f95
TI		 921 struct cs4281 *chip = snd_pcm_substream_chip(substream);
922 struct snd_pcm_runtime *runtime = substream->runtime;
923 struct cs4281_dma *dma;
1da177e4
LT		 924
925 dma = &chip->dma[1];
926 dma->substream = substream;
927 dma->left_slot = 10;
928 dma->right_slot = 11;
929 runtime->private_data = dma;
930 runtime->hw = snd_cs4281_capture;
1da177e4
LT		 931 /* should be detected from the AC'97 layer, but it seems
932 that although CS4297A rev B reports 18-bit ADC resolution,
933 samples are 20-bit */
934 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
935 return 0;
936}
937
93e35f95 938static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
1da177e4 939{
93e35f95 940 struct cs4281_dma *dma = substream->runtime->private_data;
1da177e4
LT		 941
942 dma->substream = NULL;
943 return 0;
944}
945
93e35f95 946static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
1da177e4 947{
93e35f95 948 struct cs4281_dma *dma = substream->runtime->private_data;
1da177e4
LT		 949
950 dma->substream = NULL;
951 return 0;
952}
953
6769e988 954static const struct snd_pcm_ops snd_cs4281_playback_ops = {
1da177e4
LT		 955 .open = snd_cs4281_playback_open,
956 .close = snd_cs4281_playback_close,
957 .ioctl = snd_pcm_lib_ioctl,
958 .hw_params = snd_cs4281_hw_params,
959 .hw_free = snd_cs4281_hw_free,
960 .prepare = snd_cs4281_playback_prepare,
961 .trigger = snd_cs4281_trigger,
962 .pointer = snd_cs4281_pointer,
963};
964
6769e988 965static const struct snd_pcm_ops snd_cs4281_capture_ops = {
1da177e4
LT		 966 .open = snd_cs4281_capture_open,
967 .close = snd_cs4281_capture_close,
968 .ioctl = snd_pcm_lib_ioctl,
969 .hw_params = snd_cs4281_hw_params,
970 .hw_free = snd_cs4281_hw_free,
971 .prepare = snd_cs4281_capture_prepare,
972 .trigger = snd_cs4281_trigger,
973 .pointer = snd_cs4281_pointer,
974};
975
3e4f4776 976static int snd_cs4281_pcm(struct cs4281 *chip, int device)
1da177e4 977{
93e35f95 978 struct snd_pcm *pcm;
1da177e4
LT		 979 int err;
980
1da177e4
LT		 981 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
982 if (err < 0)
983 return err;
984
985 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
986 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
987
988 pcm->private_data = chip;
1da177e4
LT		 989 pcm->info_flags = 0;
990 strcpy(pcm->name, "CS4281");
991 chip->pcm = pcm;
992
993 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
994 snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
995
1da177e4
LT		 996 return 0;
997}
998
999/*
1000 * Mixer section
1001 */
1002
1003#define CS_VOL_MASK 0x1f
1004
93e35f95
TI		 1005static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
1006 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1007{
1008 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1009 uinfo->count = 2;
1010 uinfo->value.integer.min = 0;
1011 uinfo->value.integer.max = CS_VOL_MASK;
1012 return 0;
1013}
1014
93e35f95
TI		 1015static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_value *ucontrol)
1da177e4 1017{
93e35f95 1018 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1019 int regL = (kcontrol->private_value >> 16) & 0xffff;
1020 int regR = kcontrol->private_value & 0xffff;
1021 int volL, volR;
1022
1023 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1024 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1025
1026 ucontrol->value.integer.value[0] = volL;
1027 ucontrol->value.integer.value[1] = volR;
1028 return 0;
1029}
1030
93e35f95
TI		 1031static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
1032 struct snd_ctl_elem_value *ucontrol)
1da177e4 1033{
93e35f95 1034 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1035 int change = 0;
1036 int regL = (kcontrol->private_value >> 16) & 0xffff;
1037 int regR = kcontrol->private_value & 0xffff;
1038 int volL, volR;
1039
1040 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1041 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1042
1043 if (ucontrol->value.integer.value[0] != volL) {
1044 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1045 snd_cs4281_pokeBA0(chip, regL, volL);
1046 change = 1;
1047 }
e860f000 1048 if (ucontrol->value.integer.value[1] != volR) {
1da177e4
LT		 1049 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1050 snd_cs4281_pokeBA0(chip, regR, volR);
1051 change = 1;
1052 }
1053 return change;
1054}
1055
0cb29ea0 1056static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
9f6ab250 1057
f3b827e0 1058static const struct snd_kcontrol_new snd_cs4281_fm_vol =
1da177e4
LT		 1059{
1060 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1061 .name = "Synth Playback Volume",
1062 .info = snd_cs4281_info_volume,
1063 .get = snd_cs4281_get_volume,
1064 .put = snd_cs4281_put_volume,
1065 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
9f6ab250 1066 .tlv = { .p = db_scale_dsp },
1da177e4
LT		 1067};
1068
f3b827e0 1069static const struct snd_kcontrol_new snd_cs4281_pcm_vol =
1da177e4
LT		 1070{
1071 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1072 .name = "PCM Stream Playback Volume",
1073 .info = snd_cs4281_info_volume,
1074 .get = snd_cs4281_get_volume,
1075 .put = snd_cs4281_put_volume,
1076 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
9f6ab250 1077 .tlv = { .p = db_scale_dsp },
1da177e4
LT		 1078};
1079
93e35f95 1080static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1081{
93e35f95 1082 struct cs4281 *chip = bus->private_data;
1da177e4
LT		 1083 chip->ac97_bus = NULL;
1084}
1085
93e35f95 1086static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1087{
93e35f95 1088 struct cs4281 *chip = ac97->private_data;
1da177e4
LT		 1089 if (ac97->num)
1090 chip->ac97_secondary = NULL;
1091 else
1092 chip->ac97 = NULL;
1093}
1094
e23e7a14 1095static int snd_cs4281_mixer(struct cs4281 *chip)
1da177e4 1096{
93e35f95
TI		 1097 struct snd_card *card = chip->card;
1098 struct snd_ac97_template ac97;
1da177e4 1099 int err;
93e35f95 1100 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1101 .write = snd_cs4281_ac97_write,
1102 .read = snd_cs4281_ac97_read,
1103 };
1104
1105 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1106 return err;
1107 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1108
1109 memset(&ac97, 0, sizeof(ac97));
1110 ac97.private_data = chip;
1111 ac97.private_free = snd_cs4281_mixer_free_ac97;
1112 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1113 return err;
1114 if (chip->dual_codec) {
1115 ac97.num = 1;
1116 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1117 return err;
1118 }
1119 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1120 return err;
1121 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1122 return err;
1123 return 0;
1124}
1125
1126
1127/*
1128 * proc interface
1129 */
1130
93e35f95
TI		 1131static void snd_cs4281_proc_read(struct snd_info_entry *entry,
1132 struct snd_info_buffer *buffer)
1da177e4 1133{
93e35f95 1134 struct cs4281 *chip = entry->private_data;
1da177e4
LT		 1135
1136 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1137 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1138 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1139}
1140
24e4a121
TI		 1141static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1142 void *file_private_data,
1143 struct file *file, char __user *buf,
1144 size_t count, loff_t pos)
1da177e4 1145{
93e35f95 1146 struct cs4281 *chip = entry->private_data;
1da177e4 1147
d97e1b78
TI		 1148 if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1149 return -EFAULT;
1150 return count;
1da177e4
LT		 1151}
1152
24e4a121
TI		 1153static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1154 void *file_private_data,
1155 struct file *file, char __user *buf,
1156 size_t count, loff_t pos)
1da177e4 1157{
93e35f95 1158 struct cs4281 *chip = entry->private_data;
1da177e4 1159
d97e1b78
TI		 1160 if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1161 return -EFAULT;
1162 return count;
1da177e4
LT		 1163}
1164
1165static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1166 .read = snd_cs4281_BA0_read,
1167};
1168
1169static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1170 .read = snd_cs4281_BA1_read,
1171};
1172
e23e7a14 1173static void snd_cs4281_proc_init(struct cs4281 *chip)
1da177e4 1174{
93e35f95 1175 struct snd_info_entry *entry;
1da177e4 1176
47f2769b 1177 snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
1da177e4
LT		 1178 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1179 entry->content = SNDRV_INFO_CONTENT_DATA;
1180 entry->private_data = chip;
1181 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1182 entry->size = CS4281_BA0_SIZE;
1183 }
1184 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1185 entry->content = SNDRV_INFO_CONTENT_DATA;
1186 entry->private_data = chip;
1187 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1188 entry->size = CS4281_BA1_SIZE;
1189 }
1190}
1191
1192/*
1193 * joystick support
1194 */
1195
b2fac073 1196#if IS_REACHABLE(CONFIG_GAMEPORT)
1da177e4
LT		 1197
1198static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1199{
93e35f95 1200 struct cs4281 *chip = gameport_get_port_data(gameport);
1da177e4 1201
da3cec35
TI		 1202 if (snd_BUG_ON(!chip))
1203 return;
1da177e4
LT		 1204 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1205}
1206
1207static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1208{
93e35f95 1209 struct cs4281 *chip = gameport_get_port_data(gameport);
1da177e4 1210
da3cec35
TI		 1211 if (snd_BUG_ON(!chip))
1212 return 0;
1da177e4
LT		 1213 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1214}
1215
1216#ifdef COOKED_MODE
93e35f95
TI		 1217static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1218 int *axes, int *buttons)
1da177e4 1219{
93e35f95 1220 struct cs4281 *chip = gameport_get_port_data(gameport);
1da177e4
LT		 1221 unsigned js1, js2, jst;
1222
da3cec35
TI		 1223 if (snd_BUG_ON(!chip))
1224 return 0;
1da177e4
LT		 1225
1226 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1227 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1228 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1229
1230 *buttons = (~jst >> 4) & 0x0F;
1231
1232 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1233 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1234 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1235 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1236
1237 for (jst = 0; jst < 4; ++jst)
1238 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1239 return 0;
1240}
1241#else
1242#define snd_cs4281_gameport_cooked_read NULL
1243#endif
1244
1245static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1246{
1247 switch (mode) {
1248#ifdef COOKED_MODE
1249 case GAMEPORT_MODE_COOKED:
1250 return 0;
1251#endif
1252 case GAMEPORT_MODE_RAW:
1253 return 0;
1254 default:
1255 return -1;
1256 }
1257 return 0;
1258}
1259
e23e7a14 1260static int snd_cs4281_create_gameport(struct cs4281 *chip)
1da177e4
LT		 1261{
1262 struct gameport *gp;
1263
1264 chip->gameport = gp = gameport_allocate_port();
1265 if (!gp) {
b055e7b4
TI		 1266 dev_err(chip->card->dev,
1267 "cannot allocate memory for gameport\n");
1da177e4
LT		 1268 return -ENOMEM;
1269 }
1270
1271 gameport_set_name(gp, "CS4281 Gameport");
1272 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1273 gameport_set_dev_parent(gp, &chip->pci->dev);
1274 gp->open = snd_cs4281_gameport_open;
1275 gp->read = snd_cs4281_gameport_read;
1276 gp->trigger = snd_cs4281_gameport_trigger;
1277 gp->cooked_read = snd_cs4281_gameport_cooked_read;
1278 gameport_set_port_data(gp, chip);
1279
1280 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1281 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1282
1283 gameport_register_port(gp);
1284
1285 return 0;
1286}
1287
93e35f95 1288static void snd_cs4281_free_gameport(struct cs4281 *chip)
1da177e4
LT		 1289{
1290 if (chip->gameport) {
1291 gameport_unregister_port(chip->gameport);
1292 chip->gameport = NULL;
1293 }
1294}
1295#else
93e35f95
TI		 1296static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1297static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
66701170 1298#endif /* IS_REACHABLE(CONFIG_GAMEPORT) */
1da177e4 1299
93e35f95 1300static int snd_cs4281_free(struct cs4281 *chip)
1da177e4
LT		 1301{
1302 snd_cs4281_free_gameport(chip);
1303
1304 if (chip->irq >= 0)
1305 synchronize_irq(chip->irq);
1306
1307 /* Mask interrupts */
1308 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1309 /* Stop the DLL Clock logic. */
1310 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1311 /* Sound System Power Management - Turn Everything OFF */
1312 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1313 /* PCI interface - D3 state */
db10e7fb 1314 pci_set_power_state(chip->pci, PCI_D3hot);
1da177e4
LT		 1315
1316 if (chip->irq >= 0)
93e35f95 1317 free_irq(chip->irq, chip);
ff6defa6
ME		 1318 iounmap(chip->ba0);
1319 iounmap(chip->ba1);
1da177e4
LT		 1320 pci_release_regions(chip->pci);
1321 pci_disable_device(chip->pci);
1322
1323 kfree(chip);
1324 return 0;
1325}
1326
93e35f95 1327static int snd_cs4281_dev_free(struct snd_device *device)
1da177e4 1328{
93e35f95 1329 struct cs4281 *chip = device->device_data;
1da177e4
LT		 1330 return snd_cs4281_free(chip);
1331}
1332
93e35f95 1333static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1da177e4 1334
e23e7a14
BP		 1335static int snd_cs4281_create(struct snd_card *card,
1336 struct pci_dev *pci,
1337 struct cs4281 **rchip,
1338 int dual_codec)
1da177e4 1339{
93e35f95 1340 struct cs4281 *chip;
1da177e4
LT		 1341 unsigned int tmp;
1342 int err;
93e35f95 1343 static struct snd_device_ops ops = {
1da177e4
LT		 1344 .dev_free = snd_cs4281_dev_free,
1345 };
1346
1347 *rchip = NULL;
1348 if ((err = pci_enable_device(pci)) < 0)
1349 return err;
e560d8d8 1350 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1351 if (chip == NULL) {
1352 pci_disable_device(pci);
1353 return -ENOMEM;
1354 }
1355 spin_lock_init(&chip->reg_lock);
1356 chip->card = card;
1357 chip->pci = pci;
1358 chip->irq = -1;
1359 pci_set_master(pci);
1360 if (dual_codec < 0 || dual_codec > 3) {
b055e7b4 1361 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
1da177e4
LT		 1362 dual_codec = 0;
1363 }
1364 chip->dual_codec = dual_codec;
1365
1366 if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1367 kfree(chip);
1368 pci_disable_device(pci);
1369 return err;
1370 }
1371 chip->ba0_addr = pci_resource_start(pci, 0);
1372 chip->ba1_addr = pci_resource_start(pci, 1);
1373
2f5ad54e
AV		 1374 chip->ba0 = pci_ioremap_bar(pci, 0);
1375 chip->ba1 = pci_ioremap_bar(pci, 1);
688956f2
TI		 1376 if (!chip->ba0 || !chip->ba1) {
1377 snd_cs4281_free(chip);
1378 return -ENOMEM;
1379 }
1380
437a5a46 1381 if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
934c2b6d 1382 KBUILD_MODNAME, chip)) {
b055e7b4 1383 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 1384 snd_cs4281_free(chip);
1385 return -ENOMEM;
1386 }
1387 chip->irq = pci->irq;
1388
1da177e4
LT		 1389 tmp = snd_cs4281_chip_init(chip);
1390 if (tmp) {
1391 snd_cs4281_free(chip);
1392 return tmp;
1393 }
1394
1395 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1396 snd_cs4281_free(chip);
1397 return err;
1398 }
1399
1400 snd_cs4281_proc_init(chip);
1401
1da177e4
LT		 1402 *rchip = chip;
1403 return 0;
1404}
1405
93e35f95 1406static int snd_cs4281_chip_init(struct cs4281 *chip)
1da177e4
LT		 1407{
1408 unsigned int tmp;
38223daa 1409 unsigned long end_time;
1da177e4
LT		 1410 int retry_count = 2;
1411
a488e033
AP		 1412 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1413 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1414 if (tmp & BA0_EPPMC_FPDN)
1415 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1416
1da177e4
LT		 1417 __retry:
1418 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1419 if (tmp != BA0_CFLR_DEFAULT) {
1420 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1421 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1422 if (tmp != BA0_CFLR_DEFAULT) {
b055e7b4
TI		 1423 dev_err(chip->card->dev,
1424 "CFLR setup failed (0x%x)\n", tmp);
1da177e4
LT		 1425 return -EIO;
1426 }
1427 }
1428
1429 /* Set the 'Configuration Write Protect' register
1430 * to 4281h. Allows vendor-defined configuration
1431 * space between 0e4h and 0ffh to be written. */
1432 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1433
1434 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
b055e7b4
TI		 1435 dev_err(chip->card->dev,
1436 "SERC1 AC'97 check failed (0x%x)\n", tmp);
1da177e4
LT		 1437 return -EIO;
1438 }
1439 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
b055e7b4
TI		 1440 dev_err(chip->card->dev,
1441 "SERC2 AC'97 check failed (0x%x)\n", tmp);
1da177e4
LT		 1442 return -EIO;
1443 }
1444
1445 /* Sound System Power Management */
1446 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1447 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1448 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1449
1450 /* Serial Port Power Management */
1451 /* Blast the clock control register to zero so that the
1452 * PLL starts out in a known state, and blast the master serial
1453 * port control register to zero so that the serial ports also
1454 * start out in a known state. */
1455 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1456 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1457
1458 /* Make ESYN go to zero to turn off
1459 * the Sync pulse on the AC97 link. */
1460 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1461 udelay(50);
1462
1463 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1464 * spec) and then drive it high. This is done for non AC97 modes since
1465 * there might be logic external to the CS4281 that uses the ARST# line
1466 * for a reset. */
1467 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1468 udelay(50);
1469 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
c9a49bb1 1470 msleep(50);
1da177e4
LT		 1471
1472 if (chip->dual_codec)
1473 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1474
1475 /*
1476 * Set the serial port timing configuration.
1477 */
1478 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1479 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1480 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1481
1482 /*
1483 * Start the DLL Clock logic.
1484 */
1485 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
c9a49bb1 1486 msleep(50);
1da177e4
LT		 1487 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1488
1489 /*
1490 * Wait for the DLL ready signal from the clock logic.
1491 */
38223daa 1492 end_time = jiffies + HZ;
1da177e4
LT		 1493 do {
1494 /*
1495 * Read the AC97 status register to see if we've seen a CODEC
1496 * signal from the AC97 codec.
1497 */
1498 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1499 goto __ok0;
38223daa
TI		 1500 schedule_timeout_uninterruptible(1);
1501 } while (time_after_eq(end_time, jiffies));
1da177e4 1502
b055e7b4 1503 dev_err(chip->card->dev, "DLLRDY not seen\n");
1da177e4
LT		 1504 return -EIO;
1505
1506 __ok0:
1507
1508 /*
1509 * The first thing we do here is to enable sync generation. As soon
1510 * as we start receiving bit clock, we'll start producing the SYNC
1511 * signal.
1512 */
1513 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1514
1515 /*
1516 * Wait for the codec ready signal from the AC97 codec.
1517 */
38223daa 1518 end_time = jiffies + HZ;
1da177e4
LT		 1519 do {
1520 /*
1521 * Read the AC97 status register to see if we've seen a CODEC
1522 * signal from the AC97 codec.
1523 */
1524 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1525 goto __ok1;
38223daa
TI		 1526 schedule_timeout_uninterruptible(1);
1527 } while (time_after_eq(end_time, jiffies));
1da177e4 1528
b055e7b4
TI		 1529 dev_err(chip->card->dev,
1530 "never read codec ready from AC'97 (0x%x)\n",
1531 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1da177e4
LT		 1532 return -EIO;
1533
1534 __ok1:
1535 if (chip->dual_codec) {
38223daa 1536 end_time = jiffies + HZ;
1da177e4
LT		 1537 do {
1538 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1539 goto __codec2_ok;
38223daa
TI		 1540 schedule_timeout_uninterruptible(1);
1541 } while (time_after_eq(end_time, jiffies));
b055e7b4
TI		 1542 dev_info(chip->card->dev,
1543 "secondary codec doesn't respond. disable it...\n");
1da177e4
LT		 1544 chip->dual_codec = 0;
1545 __codec2_ok: ;
1546 }
1547
1548 /*
1549 * Assert the valid frame signal so that we can start sending commands
1550 * to the AC97 codec.
1551 */
1552
1553 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1554
1555 /*
1556 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1557 * the codec is pumping ADC data across the AC-link.
1558 */
1559
38223daa 1560 end_time = jiffies + HZ;
1da177e4
LT		 1561 do {
1562 /*
1563 * Read the input slot valid register and see if input slots 3
1564 * 4 are valid yet.
1565 */
1566 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1567 goto __ok2;
38223daa
TI		 1568 schedule_timeout_uninterruptible(1);
1569 } while (time_after_eq(end_time, jiffies));
1da177e4
LT		 1570
1571 if (--retry_count > 0)
1572 goto __retry;
b055e7b4 1573 dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1da177e4
LT		 1574 return -EIO;
1575
1576 __ok2:
1577
1578 /*
1579 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1580 * commense the transfer of digital audio data to the AC97 codec.
1581 */
1582 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1583
1584 /*
1585 * Initialize DMA structures
1586 */
1587 for (tmp = 0; tmp < 4; tmp++) {
93e35f95 1588 struct cs4281_dma *dma = &chip->dma[tmp];
1da177e4
LT		 1589 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1590 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1591 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1592 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1593 dma->regDMR = BA0_DMR0 + (tmp * 8);
1594 dma->regDCR = BA0_DCR0 + (tmp * 8);
1595 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1596 dma->regFCR = BA0_FCR0 + (tmp * 4);
1597 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1598 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1599 snd_cs4281_pokeBA0(chip, dma->regFCR,
1600 BA0_FCR_LS(31) |
1601 BA0_FCR_RS(31) |
1602 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1603 BA0_FCR_OF(dma->fifo_offset));
1604 }
1605
1606 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1607 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1608 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1609 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1610
1611 /* Activate wave playback FIFO for FM playback */
1612 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1613 BA0_FCR_RS(1) |
1614 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1615 BA0_FCR_OF(chip->dma[0].fifo_offset);
1616 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1617 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1618 (chip->src_right_play_slot << 8) |
1619 (chip->src_left_rec_slot << 16) |
1620 (chip->src_right_rec_slot << 24));
1621
1622 /* Initialize digital volume */
1623 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1624 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1625
1626 /* Enable IRQs */
1627 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1628 /* Unmask interrupts */
1629 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1630 BA0_HISR_MIDI |
1631 BA0_HISR_DMAI |
1632 BA0_HISR_DMA(0) |
1633 BA0_HISR_DMA(1) |
1634 BA0_HISR_DMA(2) |
1635 BA0_HISR_DMA(3)));
1636 synchronize_irq(chip->irq);
1637
1638 return 0;
1639}
1640
1641/*
1642 * MIDI section
1643 */
1644
93e35f95 1645static void snd_cs4281_midi_reset(struct cs4281 *chip)
1da177e4
LT		 1646{
1647 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1648 udelay(100);
1649 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1650}
1651
93e35f95 1652static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1da177e4 1653{
93e35f95 1654 struct cs4281 *chip = substream->rmidi->private_data;
1da177e4
LT		 1655
1656 spin_lock_irq(&chip->reg_lock);
1657 chip->midcr |= BA0_MIDCR_RXE;
1658 chip->midi_input = substream;
1659 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1660 snd_cs4281_midi_reset(chip);
1661 } else {
1662 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1663 }
1664 spin_unlock_irq(&chip->reg_lock);
1665 return 0;
1666}
1667
93e35f95 1668static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1da177e4 1669{
93e35f95 1670 struct cs4281 *chip = substream->rmidi->private_data;
1da177e4
LT		 1671
1672 spin_lock_irq(&chip->reg_lock);
1673 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1674 chip->midi_input = NULL;
1675 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1676 snd_cs4281_midi_reset(chip);
1677 } else {
1678 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1679 }
1680 chip->uartm &= ~CS4281_MODE_INPUT;
1681 spin_unlock_irq(&chip->reg_lock);
1682 return 0;
1683}
1684
93e35f95 1685static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1da177e4 1686{
93e35f95 1687 struct cs4281 *chip = substream->rmidi->private_data;
1da177e4
LT		 1688
1689 spin_lock_irq(&chip->reg_lock);
1690 chip->uartm |= CS4281_MODE_OUTPUT;
1691 chip->midcr |= BA0_MIDCR_TXE;
1692 chip->midi_output = substream;
1693 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1694 snd_cs4281_midi_reset(chip);
1695 } else {
1696 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1697 }
1698 spin_unlock_irq(&chip->reg_lock);
1699 return 0;
1700}
1701
93e35f95 1702static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1da177e4 1703{
93e35f95 1704 struct cs4281 *chip = substream->rmidi->private_data;
1da177e4
LT		 1705
1706 spin_lock_irq(&chip->reg_lock);
1707 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1708 chip->midi_output = NULL;
1709 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1710 snd_cs4281_midi_reset(chip);
1711 } else {
1712 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1713 }
1714 chip->uartm &= ~CS4281_MODE_OUTPUT;
1715 spin_unlock_irq(&chip->reg_lock);
1716 return 0;
1717}
1718
93e35f95 1719static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 1720{
1721 unsigned long flags;
93e35f95 1722 struct cs4281 *chip = substream->rmidi->private_data;
1da177e4
LT		 1723
1724 spin_lock_irqsave(&chip->reg_lock, flags);
1725 if (up) {
1726 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1727 chip->midcr |= BA0_MIDCR_RIE;
1728 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1729 }
1730 } else {
1731 if (chip->midcr & BA0_MIDCR_RIE) {
1732 chip->midcr &= ~BA0_MIDCR_RIE;
1733 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1734 }
1735 }
1736 spin_unlock_irqrestore(&chip->reg_lock, flags);
1737}
1738
93e35f95 1739static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 1740{
1741 unsigned long flags;
93e35f95 1742 struct cs4281 *chip = substream->rmidi->private_data;
1da177e4
LT		 1743 unsigned char byte;
1744
1745 spin_lock_irqsave(&chip->reg_lock, flags);
1746 if (up) {
1747 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1748 chip->midcr |= BA0_MIDCR_TIE;
1749 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1750 while ((chip->midcr & BA0_MIDCR_TIE) &&
1751 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1752 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1753 chip->midcr &= ~BA0_MIDCR_TIE;
1754 } else {
1755 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1756 }
1757 }
1758 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1759 }
1760 } else {
1761 if (chip->midcr & BA0_MIDCR_TIE) {
1762 chip->midcr &= ~BA0_MIDCR_TIE;
1763 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1764 }
1765 }
1766 spin_unlock_irqrestore(&chip->reg_lock, flags);
1767}
1768
485885b9 1769static const struct snd_rawmidi_ops snd_cs4281_midi_output =
1da177e4
LT		 1770{
1771 .open = snd_cs4281_midi_output_open,
1772 .close = snd_cs4281_midi_output_close,
1773 .trigger = snd_cs4281_midi_output_trigger,
1774};
1775
485885b9 1776static const struct snd_rawmidi_ops snd_cs4281_midi_input =
1da177e4
LT		 1777{
1778 .open = snd_cs4281_midi_input_open,
1779 .close = snd_cs4281_midi_input_close,
1780 .trigger = snd_cs4281_midi_input_trigger,
1781};
1782
3e4f4776 1783static int snd_cs4281_midi(struct cs4281 *chip, int device)
1da177e4 1784{
93e35f95 1785 struct snd_rawmidi *rmidi;
1da177e4
LT		 1786 int err;
1787
1da177e4
LT		 1788 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1789 return err;
1790 strcpy(rmidi->name, "CS4281");
1791 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1792 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1793 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1794 rmidi->private_data = chip;
1795 chip->rmidi = rmidi;
1da177e4
LT		 1796 return 0;
1797}
1798
1799/*
1800 * Interrupt handler
1801 */
1802
7d12e780 1803static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1da177e4 1804{
93e35f95 1805 struct cs4281 *chip = dev_id;
1da177e4 1806 unsigned int status, dma, val;
93e35f95 1807 struct cs4281_dma *cdma;
1da177e4
LT		 1808
1809 if (chip == NULL)
1810 return IRQ_NONE;
1811 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1812 if ((status & 0x7fffffff) == 0) {
1813 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1814 return IRQ_NONE;
1815 }
1816
1817 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1818 for (dma = 0; dma < 4; dma++)
1819 if (status & BA0_HISR_DMA(dma)) {
1820 cdma = &chip->dma[dma];
1821 spin_lock(&chip->reg_lock);
1822 /* ack DMA IRQ */
1823 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1824 /* workaround, sometimes CS4281 acknowledges */
1825 /* end or middle transfer position twice */
1826 cdma->frag++;
1827 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1828 cdma->frag--;
1829 chip->spurious_dhtc_irq++;
1830 spin_unlock(&chip->reg_lock);
1831 continue;
1832 }
1833 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1834 cdma->frag--;
1835 chip->spurious_dtc_irq++;
1836 spin_unlock(&chip->reg_lock);
1837 continue;
1838 }
1839 spin_unlock(&chip->reg_lock);
1840 snd_pcm_period_elapsed(cdma->substream);
1841 }
1842 }
1843
1844 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1845 unsigned char c;
1846
1847 spin_lock(&chip->reg_lock);
1848 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1849 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1850 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1851 continue;
1852 snd_rawmidi_receive(chip->midi_input, &c, 1);
1853 }
1854 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1855 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1856 break;
1857 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1858 chip->midcr &= ~BA0_MIDCR_TIE;
1859 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1860 break;
1861 }
1862 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1863 }
1864 spin_unlock(&chip->reg_lock);
1865 }
1866
1867 /* EOI to the PCI part... reenables interrupts */
1868 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1869
1870 return IRQ_HANDLED;
1871}
1872
1873
1874/*
1875 * OPL3 command
1876 */
93e35f95
TI		 1877static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1878 unsigned char val)
1da177e4
LT		 1879{
1880 unsigned long flags;
93e35f95 1881 struct cs4281 *chip = opl3->private_data;
1da177e4
LT		 1882 void __iomem *port;
1883
1884 if (cmd & OPL3_RIGHT)
1885 port = chip->ba0 + BA0_B1AP; /* right port */
1886 else
1887 port = chip->ba0 + BA0_B0AP; /* left port */
1888
1889 spin_lock_irqsave(&opl3->reg_lock, flags);
1890
1891 writel((unsigned int)cmd, port);
1892 udelay(10);
1893
1894 writel((unsigned int)val, port + 4);
1895 udelay(30);
1896
1897 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1898}
1899
e23e7a14
BP		 1900static int snd_cs4281_probe(struct pci_dev *pci,
1901 const struct pci_device_id *pci_id)
1da177e4
LT		 1902{
1903 static int dev;
93e35f95
TI		 1904 struct snd_card *card;
1905 struct cs4281 *chip;
1906 struct snd_opl3 *opl3;
1da177e4
LT		 1907 int err;
1908
1909 if (dev >= SNDRV_CARDS)
1910 return -ENODEV;
1911 if (!enable[dev]) {
1912 dev++;
1913 return -ENOENT;
1914 }
1915
60c5772b
TI		 1916 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1917 0, &card);
e58de7ba
TI		 1918 if (err < 0)
1919 return err;
1da177e4
LT		 1920
1921 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1922 snd_card_free(card);
1923 return err;
1924 }
38c0a158 1925 card->private_data = chip;
1da177e4
LT		 1926
1927 if ((err = snd_cs4281_mixer(chip)) < 0) {
1928 snd_card_free(card);
1929 return err;
1930 }
3e4f4776 1931 if ((err = snd_cs4281_pcm(chip, 0)) < 0) {
1da177e4
LT		 1932 snd_card_free(card);
1933 return err;
1934 }
3e4f4776 1935 if ((err = snd_cs4281_midi(chip, 0)) < 0) {
1da177e4
LT		 1936 snd_card_free(card);
1937 return err;
1938 }
1939 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1940 snd_card_free(card);
1941 return err;
1942 }
1943 opl3->private_data = chip;
1944 opl3->command = snd_cs4281_opl3_command;
1945 snd_opl3_init(opl3);
1946 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1947 snd_card_free(card);
1948 return err;
1949 }
1950 snd_cs4281_create_gameport(chip);
1951 strcpy(card->driver, "CS4281");
1952 strcpy(card->shortname, "Cirrus Logic CS4281");
1953 sprintf(card->longname, "%s at 0x%lx, irq %d",
1954 card->shortname,
1955 chip->ba0_addr,
1956 chip->irq);
1957
1958 if ((err = snd_card_register(card)) < 0) {
1959 snd_card_free(card);
1960 return err;
1961 }
1962
1963 pci_set_drvdata(pci, card);
1964 dev++;
1965 return 0;
1966}
1967
e23e7a14 1968static void snd_cs4281_remove(struct pci_dev *pci)
1da177e4
LT		 1969{
1970 snd_card_free(pci_get_drvdata(pci));
1da177e4
LT		 1971}
1972
1973/*
1974 * Power Management
1975 */
c7561cd8 1976#ifdef CONFIG_PM_SLEEP
1da177e4
LT		 1977
1978static int saved_regs[SUSPEND_REGISTERS] = {
1979 BA0_JSCTL,
1980 BA0_GPIOR,
1981 BA0_SSCR,
1982 BA0_MIDCR,
1983 BA0_SRCSA,
1984 BA0_PASR,
1985 BA0_CASR,
1986 BA0_DACSR,
1987 BA0_ADCSR,
1988 BA0_FMLVC,
1989 BA0_FMRVC,
1990 BA0_PPLVC,
1991 BA0_PPRVC,
1992};
1993
1994#define CLKCR1_CKRA 0x00010000L
1995
68cb2b55 1996static int cs4281_suspend(struct device *dev)
1da177e4 1997{
68cb2b55 1998 struct snd_card *card = dev_get_drvdata(dev);
38c0a158 1999 struct cs4281 *chip = card->private_data;
1da177e4
LT		 2000 u32 ulCLK;
2001 unsigned int i;
2002
38c0a158 2003 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
38c0a158
TI		 2004 snd_ac97_suspend(chip->ac97);
2005 snd_ac97_suspend(chip->ac97_secondary);
1da177e4
LT		 2006
2007 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2008 ulCLK |= CLKCR1_CKRA;
2009 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2010
2011 /* Disable interrupts. */
2012 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2013
2014 /* remember the status registers */
2015 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2016 if (saved_regs[i])
2017 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2018
2019 /* Turn off the serial ports. */
2020 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2021
2022 /* Power off FM, Joystick, AC link, */
2023 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2024
2025 /* DLL off. */
2026 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2027
2028 /* AC link off. */
2029 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2030
2031 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2032 ulCLK &= ~CLKCR1_CKRA;
2033 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1da177e4
LT		 2034 return 0;
2035}
2036
68cb2b55 2037static int cs4281_resume(struct device *dev)
1da177e4 2038{
68cb2b55 2039 struct snd_card *card = dev_get_drvdata(dev);
38c0a158 2040 struct cs4281 *chip = card->private_data;
1da177e4
LT		 2041 unsigned int i;
2042 u32 ulCLK;
2043
1da177e4
LT		 2044 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2045 ulCLK |= CLKCR1_CKRA;
2046 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2047
2048 snd_cs4281_chip_init(chip);
2049
2050 /* restore the status registers */
2051 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2052 if (saved_regs[i])
2053 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2054
38c0a158
TI		 2055 snd_ac97_resume(chip->ac97);
2056 snd_ac97_resume(chip->ac97_secondary);
1da177e4
LT		 2057
2058 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2059 ulCLK &= ~CLKCR1_CKRA;
2060 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2061
38c0a158 2062 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2063 return 0;
2064}
68cb2b55
TI		 2065
2066static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
2067#define CS4281_PM_OPS &cs4281_pm
2068#else
2069#define CS4281_PM_OPS NULL
c7561cd8 2070#endif /* CONFIG_PM_SLEEP */
1da177e4 2071
e9f66d9b 2072static struct pci_driver cs4281_driver = {
3733e424 2073 .name = KBUILD_MODNAME,
1da177e4
LT		 2074 .id_table = snd_cs4281_ids,
2075 .probe = snd_cs4281_probe,
e23e7a14 2076 .remove = snd_cs4281_remove,
68cb2b55
TI		 2077 .driver = {
2078 .pm = CS4281_PM_OPS,
2079 },
1da177e4
LT		 2080};
2081
e9f66d9b 2082module_pci_driver(cs4281_driver);
Linux 6.x block layer and io_uring tree(s)