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[SCSI] Mention scsi_scan_host() in scsi_mid_low_api.txt
[linux-2.6-block.git] / sound / pci / cs4281.c
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1da177e4
LT		 1/*
2 * Driver for Cirrus Logic CS4281 based PCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <sound/driver.h>
23#include <asm/io.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/gameport.h>
30#include <linux/moduleparam.h>
31#include <sound/core.h>
32#include <sound/control.h>
33#include <sound/pcm.h>
34#include <sound/rawmidi.h>
35#include <sound/ac97_codec.h>
36#include <sound/opl3.h>
37#include <sound/initval.h>
38
39
40MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
41MODULE_DESCRIPTION("Cirrus Logic CS4281");
42MODULE_LICENSE("GPL");
43MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
44
45static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
46static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
47static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
48static int dual_codec[SNDRV_CARDS]; /* dual codec */
49
50module_param_array(index, int, NULL, 0444);
51MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
52module_param_array(id, charp, NULL, 0444);
53MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
54module_param_array(enable, bool, NULL, 0444);
55MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
56module_param_array(dual_codec, bool, NULL, 0444);
57MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
58
1da177e4
LT		 59/*
60 * Direct registers
61 */
62
63#define CS4281_BA0_SIZE 0x1000
64#define CS4281_BA1_SIZE 0x10000
65
66/*
67 * BA0 registers
68 */
69#define BA0_HISR 0x0000 /* Host Interrupt Status Register */
70#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
71#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
72#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
73#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
74#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
75#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
76#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
77#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
78#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
79#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
80#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
81#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
82
83#define BA0_HICR 0x0008 /* Host Interrupt Control Register */
84#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
85#define BA0_HICR_IEV (1<<0) /* INTENA Value */
86#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
87
88#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
89 /* Use same contants as for BA0_HISR */
90
91#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
92
93#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
94#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
95#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
96#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
97
98#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
99#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
100#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
101#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
102#define BA0_HDSR_DRUN (1<<15) /* DMA Running */
103#define BA0_HDSR_RQ (1<<7) /* Pending Request */
104
105#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
106#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
107#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
108#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
109#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
110#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
111#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
112#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
113#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
114#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
115#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
116#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
117#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
118#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
119#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
120#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
121#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
122#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
123#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
124#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
125#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
126#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
127#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
128#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
129
130#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
131#define BA0_DMR_POLL (1<<28) /* Enable poll mode */
132#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
133#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
134#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
135#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
136#define BA0_DMR_USIGN (1<<19) /* Unsigned */
137#define BA0_DMR_BEND (1<<18) /* Big Endian */
138#define BA0_DMR_MONO (1<<17) /* Mono */
139#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
140#define BA0_DMR_TYPE_DEMAND (0<<6)
141#define BA0_DMR_TYPE_SINGLE (1<<6)
142#define BA0_DMR_TYPE_BLOCK (2<<6)
143#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
144#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
145#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
146#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
147#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
148#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
149
150#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
151#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
152#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
153
154#define BA0_FCR0 0x0180 /* FIFO Control 0 */
155#define BA0_FCR1 0x0184 /* FIFO Control 1 */
156#define BA0_FCR2 0x0188 /* FIFO Control 2 */
157#define BA0_FCR3 0x018c /* FIFO Control 3 */
158
159#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
160#define BA0_FCR_DACZ (1<<30) /* DAC Zero */
161#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
162#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
163#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
164#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
165#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
166
167#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
168#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
169#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
170#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
171
172#define BA0_FCHS 0x020c /* FIFO Channel Status */
173#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
174#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
175#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
176#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
177#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
178#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
179#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
180#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
181
182#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
183#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
184#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
185#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
186
187#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
188#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
189#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
190#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
191#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
192#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
193#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
194#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
195
196#define BA0_PMCS 0x0344 /* Power Management Control/Status */
197#define BA0_CWPR 0x03e0 /* Configuration Write Protect */
a488e033 198
1da177e4 199#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
a488e033
AP		 200#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
201
1da177e4
LT		 202#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
203
204#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
205#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
206#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
207#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
208#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
209#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
210#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
211#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
212#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
213#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
214
215#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
216#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
217#define BA0_IISR 0x03f4 /* ISA Interrupt Select */
218#define BA0_TMS 0x03f8 /* Test Register */
219#define BA0_SSVID 0x03fc /* Subsystem ID register */
220
221#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
222#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
223#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
224#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
225#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
226#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
227#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
228
229#define BA0_FRR 0x0410 /* Feature Reporting Register */
230#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
231
232#define BA0_SERMC 0x0420 /* Serial Port Master Control */
233#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
234#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
235#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
236#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
237#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
238#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
239#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
240#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
241#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
242#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
243#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
244#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
245
246#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
247#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
248#define BA0_SERC1_AC97 (1<<1)
249#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
250
251#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
252#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
253#define BA0_SERC2_AC97 (1<<1)
254#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
255
256#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
257
258#define BA0_ACCTL 0x0460 /* AC'97 Control */
259#define BA0_ACCTL_TC (1<<6) /* Target Codec */
260#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
261#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
262#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
263#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
264
265#define BA0_ACSTS 0x0464 /* AC'97 Status */
266#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
267#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
268
269#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
270#define BA0_ACOSV_SLV(x) (1<<((x)-3))
271
272#define BA0_ACCAD 0x046c /* AC'97 Command Address */
273#define BA0_ACCDA 0x0470 /* AC'97 Command Data */
274
275#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
276#define BA0_ACISV_SLV(x) (1<<((x)-3))
277
278#define BA0_ACSAD 0x0478 /* AC'97 Status Address */
279#define BA0_ACSDA 0x047c /* AC'97 Status Data */
280#define BA0_JSPT 0x0480 /* Joystick poll/trigger */
281#define BA0_JSCTL 0x0484 /* Joystick control */
282#define BA0_JSC1 0x0488 /* Joystick control */
283#define BA0_JSC2 0x048c /* Joystick control */
284#define BA0_JSIO 0x04a0
285
286#define BA0_MIDCR 0x0490 /* MIDI Control */
287#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
288#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
289#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
290#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
291#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
292#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
293
294#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
295
296#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
297#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
298#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
299#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
300#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
301
302#define BA0_MIDWP 0x0498 /* MIDI Write */
303#define BA0_MIDRP 0x049c /* MIDI Read (ro) */
304
305#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
306#define BA0_AODSD1_NDS(x) (1<<((x)-3))
307
308#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
309#define BA0_AODSD2_NDS(x) (1<<((x)-3))
310
311#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
312#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
313#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
314#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
315#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
316#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
317#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
318#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
319#define BA0_FMDP 0x0734 /* FM Data Port */
320#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
321#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
322
323#define BA0_SSPM 0x0740 /* Sound System Power Management */
324#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
325#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
326#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
327#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
328#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
329#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
330
331#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
332#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
333
334#define BA0_SSCR 0x074c /* Sound System Control Register */
335#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
336#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
337#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
338#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
339#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
340#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
341#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
342#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
343#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
344
345#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
346#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
347#define BA0_SRCSA 0x075c /* SRC Slot Assignments */
348#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
349#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
350#define BA0_PASR 0x0768 /* playback sample rate */
351#define BA0_CASR 0x076C /* capture sample rate */
352
353/* Source Slot Numbers - Playback */
354#define SRCSLOT_LEFT_PCM_PLAYBACK 0
355#define SRCSLOT_RIGHT_PCM_PLAYBACK 1
356#define SRCSLOT_PHONE_LINE_1_DAC 2
357#define SRCSLOT_CENTER_PCM_PLAYBACK 3
358#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
359#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
360#define SRCSLOT_LFE_PCM_PLAYBACK 6
361#define SRCSLOT_PHONE_LINE_2_DAC 7
362#define SRCSLOT_HEADSET_DAC 8
363#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
364#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
365
366/* Source Slot Numbers - Capture */
367#define SRCSLOT_LEFT_PCM_RECORD 10
368#define SRCSLOT_RIGHT_PCM_RECORD 11
369#define SRCSLOT_PHONE_LINE_1_ADC 12
370#define SRCSLOT_MIC_ADC 13
371#define SRCSLOT_PHONE_LINE_2_ADC 17
372#define SRCSLOT_HEADSET_ADC 18
373#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
374#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
375#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
376#define SRCSLOT_SECONDARY_MIC_ADC 23
377#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
378#define SRCSLOT_SECONDARY_HEADSET_ADC 28
379
380/* Source Slot Numbers - Others */
381#define SRCSLOT_POWER_DOWN 31
382
383/* MIDI modes */
384#define CS4281_MODE_OUTPUT (1<<0)
385#define CS4281_MODE_INPUT (1<<1)
386
387/* joystick bits */
388/* Bits for JSPT */
389#define JSPT_CAX 0x00000001
390#define JSPT_CAY 0x00000002
391#define JSPT_CBX 0x00000004
392#define JSPT_CBY 0x00000008
393#define JSPT_BA1 0x00000010
394#define JSPT_BA2 0x00000020
395#define JSPT_BB1 0x00000040
396#define JSPT_BB2 0x00000080
397
398/* Bits for JSCTL */
399#define JSCTL_SP_MASK 0x00000003
400#define JSCTL_SP_SLOW 0x00000000
401#define JSCTL_SP_MEDIUM_SLOW 0x00000001
402#define JSCTL_SP_MEDIUM_FAST 0x00000002
403#define JSCTL_SP_FAST 0x00000003
404#define JSCTL_ARE 0x00000004
405
406/* Data register pairs masks */
407#define JSC1_Y1V_MASK 0x0000FFFF
408#define JSC1_X1V_MASK 0xFFFF0000
409#define JSC1_Y1V_SHIFT 0
410#define JSC1_X1V_SHIFT 16
411#define JSC2_Y2V_MASK 0x0000FFFF
412#define JSC2_X2V_MASK 0xFFFF0000
413#define JSC2_Y2V_SHIFT 0
414#define JSC2_X2V_SHIFT 16
415
416/* JS GPIO */
417#define JSIO_DAX 0x00000001
418#define JSIO_DAY 0x00000002
419#define JSIO_DBX 0x00000004
420#define JSIO_DBY 0x00000008
421#define JSIO_AXOE 0x00000010
422#define JSIO_AYOE 0x00000020
423#define JSIO_BXOE 0x00000040
424#define JSIO_BYOE 0x00000080
425
426/*
427 *
428 */
429
430typedef struct snd_cs4281 cs4281_t;
431typedef struct snd_cs4281_dma cs4281_dma_t;
432
433struct snd_cs4281_dma {
434 snd_pcm_substream_t *substream;
435 unsigned int regDBA; /* offset to DBA register */
436 unsigned int regDCA; /* offset to DCA register */
437 unsigned int regDBC; /* offset to DBC register */
438 unsigned int regDCC; /* offset to DCC register */
439 unsigned int regDMR; /* offset to DMR register */
440 unsigned int regDCR; /* offset to DCR register */
441 unsigned int regHDSR; /* offset to HDSR register */
442 unsigned int regFCR; /* offset to FCR register */
443 unsigned int regFSIC; /* offset to FSIC register */
444 unsigned int valDMR; /* DMA mode */
445 unsigned int valDCR; /* DMA command */
446 unsigned int valFCR; /* FIFO control */
447 unsigned int fifo_offset; /* FIFO offset within BA1 */
448 unsigned char left_slot; /* FIFO left slot */
449 unsigned char right_slot; /* FIFO right slot */
450 int frag; /* period number */
451};
452
453#define SUSPEND_REGISTERS 20
454
455struct snd_cs4281 {
456 int irq;
457
458 void __iomem *ba0; /* virtual (accessible) address */
459 void __iomem *ba1; /* virtual (accessible) address */
460 unsigned long ba0_addr;
461 unsigned long ba1_addr;
462
463 int dual_codec;
464
465 ac97_bus_t *ac97_bus;
466 ac97_t *ac97;
467 ac97_t *ac97_secondary;
468
469 struct pci_dev *pci;
470 snd_card_t *card;
471 snd_pcm_t *pcm;
472 snd_rawmidi_t *rmidi;
473 snd_rawmidi_substream_t *midi_input;
474 snd_rawmidi_substream_t *midi_output;
475
476 cs4281_dma_t dma[4];
477
478 unsigned char src_left_play_slot;
479 unsigned char src_right_play_slot;
480 unsigned char src_left_rec_slot;
481 unsigned char src_right_rec_slot;
482
483 unsigned int spurious_dhtc_irq;
484 unsigned int spurious_dtc_irq;
485
486 spinlock_t reg_lock;
487 unsigned int midcr;
488 unsigned int uartm;
489
490 struct gameport *gameport;
491
492#ifdef CONFIG_PM
493 u32 suspend_regs[SUSPEND_REGISTERS];
494#endif
495
496};
497
498static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
499
500static struct pci_device_id snd_cs4281_ids[] = {
501 { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */
502 { 0, }
503};
504
505MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
506
507/*
508 * constants
509 */
510
511#define CS4281_FIFO_SIZE 32
512
513/*
514 * common I/O routines
515 */
516
517static void snd_cs4281_delay(unsigned int delay)
518{
519 if (delay > 999) {
520 unsigned long end_time;
521 delay = (delay * HZ) / 1000000;
522 if (delay < 1)
523 delay = 1;
524 end_time = jiffies + delay;
525 do {
8433a509 526 schedule_timeout_uninterruptible(1);
1da177e4
LT		 527 } while (time_after_eq(end_time, jiffies));
528 } else {
529 udelay(delay);
530 }
531}
532
77933d72 533static inline void snd_cs4281_delay_long(void)
1da177e4 534{
8433a509 535 schedule_timeout_uninterruptible(1);
1da177e4
LT		 536}
537
538static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
539{
540 writel(val, chip->ba0 + offset);
541}
542
543static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
544{
545 return readl(chip->ba0 + offset);
546}
547
548static void snd_cs4281_ac97_write(ac97_t *ac97,
549 unsigned short reg, unsigned short val)
550{
551 /*
552 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
553 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
554 * 3. Write ACCTL = Control Register = 460h for initiating the write
555 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
556 * 5. if DCV not cleared, break and return error
557 */
558 cs4281_t *chip = ac97->private_data;
559 int count;
560
561 /*
562 * Setup the AC97 control registers on the CS461x to send the
563 * appropriate command to the AC97 to perform the read.
564 * ACCAD = Command Address Register = 46Ch
565 * ACCDA = Command Data Register = 470h
566 * ACCTL = Control Register = 460h
567 * set DCV - will clear when process completed
568 * reset CRW - Write command
569 * set VFRM - valid frame enabled
570 * set ESYN - ASYNC generation enabled
571 * set RSTN - ARST# inactive, AC97 codec not reset
572 */
573 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
574 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
575 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
576 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
577 for (count = 0; count < 2000; count++) {
578 /*
579 * First, we want to wait for a short time.
580 */
581 udelay(10);
582 /*
583 * Now, check to see if the write has completed.
584 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
585 */
586 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
587 return;
588 }
589 }
590 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
591}
592
593static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
594 unsigned short reg)
595{
596 cs4281_t *chip = ac97->private_data;
597 int count;
598 unsigned short result;
599 // FIXME: volatile is necessary in the following due to a bug of
600 // some gcc versions
601 volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
602
603 /*
604 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
605 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
606 * 3. Write ACCTL = Control Register = 460h for initiating the write
607 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
608 * 5. if DCV not cleared, break and return error
609 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
610 */
611
612 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
613
614 /*
615 * Setup the AC97 control registers on the CS461x to send the
616 * appropriate command to the AC97 to perform the read.
617 * ACCAD = Command Address Register = 46Ch
618 * ACCDA = Command Data Register = 470h
619 * ACCTL = Control Register = 460h
620 * set DCV - will clear when process completed
621 * set CRW - Read command
622 * set VFRM - valid frame enabled
623 * set ESYN - ASYNC generation enabled
624 * set RSTN - ARST# inactive, AC97 codec not reset
625 */
626
627 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
628 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
629 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
630 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
631 (ac97_num ? BA0_ACCTL_TC : 0));
632
633
634 /*
635 * Wait for the read to occur.
636 */
637 for (count = 0; count < 500; count++) {
638 /*
639 * First, we want to wait for a short time.
640 */
641 udelay(10);
642 /*
643 * Now, check to see if the read has completed.
644 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
645 */
646 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
647 goto __ok1;
648 }
649
650 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
651 result = 0xffff;
652 goto __end;
653
654 __ok1:
655 /*
656 * Wait for the valid status bit to go active.
657 */
658 for (count = 0; count < 100; count++) {
659 /*
660 * Read the AC97 status register.
661 * ACSTS = Status Register = 464h
662 * VSTS - Valid Status
663 */
664 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
665 goto __ok2;
666 udelay(10);
667 }
668
669 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
670 result = 0xffff;
671 goto __end;
672
673 __ok2:
674 /*
675 * Read the data returned from the AC97 register.
676 * ACSDA = Status Data Register = 474h
677 */
678 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
679
680 __end:
681 return result;
682}
683
684/*
685 * PCM part
686 */
687
688static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
689{
690 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
691 cs4281_t *chip = snd_pcm_substream_chip(substream);
692
693 spin_lock(&chip->reg_lock);
694 switch (cmd) {
695 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
696 dma->valDCR |= BA0_DCR_MSK;
697 dma->valFCR |= BA0_FCR_FEN;
698 break;
699 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
700 dma->valDCR &= ~BA0_DCR_MSK;
701 dma->valFCR &= ~BA0_FCR_FEN;
702 break;
703 case SNDRV_PCM_TRIGGER_START:
704 case SNDRV_PCM_TRIGGER_RESUME:
705 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
706 dma->valDMR |= BA0_DMR_DMA;
707 dma->valDCR &= ~BA0_DCR_MSK;
708 dma->valFCR |= BA0_FCR_FEN;
709 break;
710 case SNDRV_PCM_TRIGGER_STOP:
711 case SNDRV_PCM_TRIGGER_SUSPEND:
712 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
713 dma->valDCR |= BA0_DCR_MSK;
714 dma->valFCR &= ~BA0_FCR_FEN;
715 /* Leave wave playback FIFO enabled for FM */
716 if (dma->regFCR != BA0_FCR0)
717 dma->valFCR &= ~BA0_FCR_FEN;
718 break;
719 default:
720 spin_unlock(&chip->reg_lock);
721 return -EINVAL;
722 }
723 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
724 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
725 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
726 spin_unlock(&chip->reg_lock);
727 return 0;
728}
729
730static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
731{
732 unsigned int val = ~0;
733
734 if (real_rate)
735 *real_rate = rate;
736 /* special "hardcoded" rates */
737 switch (rate) {
738 case 8000: return 5;
739 case 11025: return 4;
740 case 16000: return 3;
741 case 22050: return 2;
742 case 44100: return 1;
743 case 48000: return 0;
744 default:
745 goto __variable;
746 }
747 __variable:
748 val = 1536000 / rate;
749 if (real_rate)
750 *real_rate = 1536000 / val;
751 return val;
752}
753
754static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
755{
756 int rec_mono;
757
758 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
759 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
760 if (runtime->channels == 1)
761 dma->valDMR |= BA0_DMR_MONO;
762 if (snd_pcm_format_unsigned(runtime->format) > 0)
763 dma->valDMR |= BA0_DMR_USIGN;
764 if (snd_pcm_format_big_endian(runtime->format) > 0)
765 dma->valDMR |= BA0_DMR_BEND;
766 switch (snd_pcm_format_width(runtime->format)) {
767 case 8: dma->valDMR |= BA0_DMR_SIZE8;
768 if (runtime->channels == 1)
769 dma->valDMR |= BA0_DMR_SWAPC;
770 break;
771 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
772 }
773 dma->frag = 0; /* for workaround */
774 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
775 if (runtime->buffer_size != runtime->period_size)
776 dma->valDCR |= BA0_DCR_HTCIE;
777 /* Initialize DMA */
778 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
779 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
780 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
781 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
782 (chip->src_right_play_slot << 8) |
783 (chip->src_left_rec_slot << 16) |
784 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
785 if (!src)
786 goto __skip_src;
787 if (!capture) {
788 if (dma->left_slot == chip->src_left_play_slot) {
789 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
790 snd_assert(dma->right_slot == chip->src_right_play_slot, );
791 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
792 }
793 } else {
794 if (dma->left_slot == chip->src_left_rec_slot) {
795 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
796 snd_assert(dma->right_slot == chip->src_right_rec_slot, );
797 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
798 }
799 }
800 __skip_src:
801 /* Deactivate wave playback FIFO before changing slot assignments */
802 if (dma->regFCR == BA0_FCR0)
803 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
804 /* Initialize FIFO */
805 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
806 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
807 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
808 BA0_FCR_OF(dma->fifo_offset);
809 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
810 /* Activate FIFO again for FM playback */
811 if (dma->regFCR == BA0_FCR0)
812 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
813 /* Clear FIFO Status and Interrupt Control Register */
814 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
815}
816
817static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
818 snd_pcm_hw_params_t * hw_params)
819{
820 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
821}
822
823static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
824{
825 return snd_pcm_lib_free_pages(substream);
826}
827
828static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
829{
830 snd_pcm_runtime_t *runtime = substream->runtime;
831 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
832 cs4281_t *chip = snd_pcm_substream_chip(substream);
833
834 spin_lock_irq(&chip->reg_lock);
835 snd_cs4281_mode(chip, dma, runtime, 0, 1);
836 spin_unlock_irq(&chip->reg_lock);
837 return 0;
838}
839
840static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
841{
842 snd_pcm_runtime_t *runtime = substream->runtime;
843 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
844 cs4281_t *chip = snd_pcm_substream_chip(substream);
845
846 spin_lock_irq(&chip->reg_lock);
847 snd_cs4281_mode(chip, dma, runtime, 1, 1);
848 spin_unlock_irq(&chip->reg_lock);
849 return 0;
850}
851
852static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
853{
854 snd_pcm_runtime_t *runtime = substream->runtime;
855 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
856 cs4281_t *chip = snd_pcm_substream_chip(substream);
857
858 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
859 return runtime->buffer_size -
860 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
861}
862
863static snd_pcm_hardware_t snd_cs4281_playback =
864{
865 .info = (SNDRV_PCM_INFO_MMAP |
866 SNDRV_PCM_INFO_INTERLEAVED |
867 SNDRV_PCM_INFO_MMAP_VALID |
868 SNDRV_PCM_INFO_PAUSE |
869 SNDRV_PCM_INFO_RESUME |
870 SNDRV_PCM_INFO_SYNC_START),
871 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
872 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
873 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
874 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
875 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
876 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
877 .rate_min = 4000,
878 .rate_max = 48000,
879 .channels_min = 1,
880 .channels_max = 2,
881 .buffer_bytes_max = (512*1024),
882 .period_bytes_min = 64,
883 .period_bytes_max = (512*1024),
884 .periods_min = 1,
885 .periods_max = 2,
886 .fifo_size = CS4281_FIFO_SIZE,
887};
888
889static snd_pcm_hardware_t snd_cs4281_capture =
890{
891 .info = (SNDRV_PCM_INFO_MMAP |
892 SNDRV_PCM_INFO_INTERLEAVED |
893 SNDRV_PCM_INFO_MMAP_VALID |
894 SNDRV_PCM_INFO_PAUSE |
895 SNDRV_PCM_INFO_RESUME |
896 SNDRV_PCM_INFO_SYNC_START),
897 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
898 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
899 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
900 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
901 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
902 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
903 .rate_min = 4000,
904 .rate_max = 48000,
905 .channels_min = 1,
906 .channels_max = 2,
907 .buffer_bytes_max = (512*1024),
908 .period_bytes_min = 64,
909 .period_bytes_max = (512*1024),
910 .periods_min = 1,
911 .periods_max = 2,
912 .fifo_size = CS4281_FIFO_SIZE,
913};
914
915static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
916{
917 cs4281_t *chip = snd_pcm_substream_chip(substream);
918 snd_pcm_runtime_t *runtime = substream->runtime;
919 cs4281_dma_t *dma;
920
921 dma = &chip->dma[0];
922 dma->substream = substream;
923 dma->left_slot = 0;
924 dma->right_slot = 1;
925 runtime->private_data = dma;
926 runtime->hw = snd_cs4281_playback;
927 snd_pcm_set_sync(substream);
928 /* should be detected from the AC'97 layer, but it seems
929 that although CS4297A rev B reports 18-bit ADC resolution,
930 samples are 20-bit */
931 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
932 return 0;
933}
934
935static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
936{
937 cs4281_t *chip = snd_pcm_substream_chip(substream);
938 snd_pcm_runtime_t *runtime = substream->runtime;
939 cs4281_dma_t *dma;
940
941 dma = &chip->dma[1];
942 dma->substream = substream;
943 dma->left_slot = 10;
944 dma->right_slot = 11;
945 runtime->private_data = dma;
946 runtime->hw = snd_cs4281_capture;
947 snd_pcm_set_sync(substream);
948 /* should be detected from the AC'97 layer, but it seems
949 that although CS4297A rev B reports 18-bit ADC resolution,
950 samples are 20-bit */
951 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
952 return 0;
953}
954
955static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
956{
957 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
958
959 dma->substream = NULL;
960 return 0;
961}
962
963static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
964{
965 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
966
967 dma->substream = NULL;
968 return 0;
969}
970
971static snd_pcm_ops_t snd_cs4281_playback_ops = {
972 .open = snd_cs4281_playback_open,
973 .close = snd_cs4281_playback_close,
974 .ioctl = snd_pcm_lib_ioctl,
975 .hw_params = snd_cs4281_hw_params,
976 .hw_free = snd_cs4281_hw_free,
977 .prepare = snd_cs4281_playback_prepare,
978 .trigger = snd_cs4281_trigger,
979 .pointer = snd_cs4281_pointer,
980};
981
982static snd_pcm_ops_t snd_cs4281_capture_ops = {
983 .open = snd_cs4281_capture_open,
984 .close = snd_cs4281_capture_close,
985 .ioctl = snd_pcm_lib_ioctl,
986 .hw_params = snd_cs4281_hw_params,
987 .hw_free = snd_cs4281_hw_free,
988 .prepare = snd_cs4281_capture_prepare,
989 .trigger = snd_cs4281_trigger,
990 .pointer = snd_cs4281_pointer,
991};
992
993static void snd_cs4281_pcm_free(snd_pcm_t *pcm)
994{
995 cs4281_t *chip = pcm->private_data;
996 chip->pcm = NULL;
997 snd_pcm_lib_preallocate_free_for_all(pcm);
998}
999
1000static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
1001{
1002 snd_pcm_t *pcm;
1003 int err;
1004
1005 if (rpcm)
1006 *rpcm = NULL;
1007 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
1008 if (err < 0)
1009 return err;
1010
1011 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
1012 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
1013
1014 pcm->private_data = chip;
1015 pcm->private_free = snd_cs4281_pcm_free;
1016 pcm->info_flags = 0;
1017 strcpy(pcm->name, "CS4281");
1018 chip->pcm = pcm;
1019
1020 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1021 snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
1022
1023 if (rpcm)
1024 *rpcm = pcm;
1025 return 0;
1026}
1027
1028/*
1029 * Mixer section
1030 */
1031
1032#define CS_VOL_MASK 0x1f
1033
1034static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1035{
1036 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1037 uinfo->count = 2;
1038 uinfo->value.integer.min = 0;
1039 uinfo->value.integer.max = CS_VOL_MASK;
1040 return 0;
1041}
1042
1043static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1044{
1045 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1046 int regL = (kcontrol->private_value >> 16) & 0xffff;
1047 int regR = kcontrol->private_value & 0xffff;
1048 int volL, volR;
1049
1050 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1051 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1052
1053 ucontrol->value.integer.value[0] = volL;
1054 ucontrol->value.integer.value[1] = volR;
1055 return 0;
1056}
1057
1058static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1059{
1060 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1061 int change = 0;
1062 int regL = (kcontrol->private_value >> 16) & 0xffff;
1063 int regR = kcontrol->private_value & 0xffff;
1064 int volL, volR;
1065
1066 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1067 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1068
1069 if (ucontrol->value.integer.value[0] != volL) {
1070 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1071 snd_cs4281_pokeBA0(chip, regL, volL);
1072 change = 1;
1073 }
1074 if (ucontrol->value.integer.value[0] != volL) {
1075 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1076 snd_cs4281_pokeBA0(chip, regR, volR);
1077 change = 1;
1078 }
1079 return change;
1080}
1081
1082static snd_kcontrol_new_t snd_cs4281_fm_vol =
1083{
1084 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1085 .name = "Synth Playback Volume",
1086 .info = snd_cs4281_info_volume,
1087 .get = snd_cs4281_get_volume,
1088 .put = snd_cs4281_put_volume,
1089 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1090};
1091
1092static snd_kcontrol_new_t snd_cs4281_pcm_vol =
1093{
1094 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1095 .name = "PCM Stream Playback Volume",
1096 .info = snd_cs4281_info_volume,
1097 .get = snd_cs4281_get_volume,
1098 .put = snd_cs4281_put_volume,
1099 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1100};
1101
1102static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus)
1103{
1104 cs4281_t *chip = bus->private_data;
1105 chip->ac97_bus = NULL;
1106}
1107
1108static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
1109{
1110 cs4281_t *chip = ac97->private_data;
1111 if (ac97->num)
1112 chip->ac97_secondary = NULL;
1113 else
1114 chip->ac97 = NULL;
1115}
1116
1117static int __devinit snd_cs4281_mixer(cs4281_t * chip)
1118{
1119 snd_card_t *card = chip->card;
1120 ac97_template_t ac97;
1121 int err;
1122 static ac97_bus_ops_t ops = {
1123 .write = snd_cs4281_ac97_write,
1124 .read = snd_cs4281_ac97_read,
1125 };
1126
1127 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1128 return err;
1129 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1130
1131 memset(&ac97, 0, sizeof(ac97));
1132 ac97.private_data = chip;
1133 ac97.private_free = snd_cs4281_mixer_free_ac97;
1134 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1135 return err;
1136 if (chip->dual_codec) {
1137 ac97.num = 1;
1138 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1139 return err;
1140 }
1141 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1142 return err;
1143 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1144 return err;
1145 return 0;
1146}
1147
1148
1149/*
1150 * proc interface
1151 */
1152
1153static void snd_cs4281_proc_read(snd_info_entry_t *entry,
1154 snd_info_buffer_t * buffer)
1155{
1156 cs4281_t *chip = entry->private_data;
1157
1158 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1159 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1160 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1161}
1162
1163static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
1164 struct file *file, char __user *buf,
1165 unsigned long count, unsigned long pos)
1166{
1167 long size;
1168 cs4281_t *chip = entry->private_data;
1169
1170 size = count;
1171 if (pos + size > CS4281_BA0_SIZE)
1172 size = (long)CS4281_BA0_SIZE - pos;
1173 if (size > 0) {
1174 if (copy_to_user_fromio(buf, chip->ba0 + pos, size))
1175 return -EFAULT;
1176 }
1177 return size;
1178}
1179
1180static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
1181 struct file *file, char __user *buf,
1182 unsigned long count, unsigned long pos)
1183{
1184 long size;
1185 cs4281_t *chip = entry->private_data;
1186
1187 size = count;
1188 if (pos + size > CS4281_BA1_SIZE)
1189 size = (long)CS4281_BA1_SIZE - pos;
1190 if (size > 0) {
1191 if (copy_to_user_fromio(buf, chip->ba1 + pos, size))
1192 return -EFAULT;
1193 }
1194 return size;
1195}
1196
1197static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1198 .read = snd_cs4281_BA0_read,
1199};
1200
1201static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1202 .read = snd_cs4281_BA1_read,
1203};
1204
1205static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
1206{
1207 snd_info_entry_t *entry;
1208
1209 if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1210 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);
1211 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1212 entry->content = SNDRV_INFO_CONTENT_DATA;
1213 entry->private_data = chip;
1214 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1215 entry->size = CS4281_BA0_SIZE;
1216 }
1217 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1218 entry->content = SNDRV_INFO_CONTENT_DATA;
1219 entry->private_data = chip;
1220 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1221 entry->size = CS4281_BA1_SIZE;
1222 }
1223}
1224
1225/*
1226 * joystick support
1227 */
1228
1229#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1230
1231static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1232{
1233 cs4281_t *chip = gameport_get_port_data(gameport);
1234
1235 snd_assert(chip, return);
1236 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1237}
1238
1239static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1240{
1241 cs4281_t *chip = gameport_get_port_data(gameport);
1242
1243 snd_assert(chip, return 0);
1244 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1245}
1246
1247#ifdef COOKED_MODE
1248static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
1249{
1250 cs4281_t *chip = gameport_get_port_data(gameport);
1251 unsigned js1, js2, jst;
1252
1253 snd_assert(chip, return 0);
1254
1255 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1256 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1257 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1258
1259 *buttons = (~jst >> 4) & 0x0F;
1260
1261 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1262 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1263 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1264 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1265
1266 for (jst = 0; jst < 4; ++jst)
1267 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1268 return 0;
1269}
1270#else
1271#define snd_cs4281_gameport_cooked_read NULL
1272#endif
1273
1274static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1275{
1276 switch (mode) {
1277#ifdef COOKED_MODE
1278 case GAMEPORT_MODE_COOKED:
1279 return 0;
1280#endif
1281 case GAMEPORT_MODE_RAW:
1282 return 0;
1283 default:
1284 return -1;
1285 }
1286 return 0;
1287}
1288
1289static int __devinit snd_cs4281_create_gameport(cs4281_t *chip)
1290{
1291 struct gameport *gp;
1292
1293 chip->gameport = gp = gameport_allocate_port();
1294 if (!gp) {
1295 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n");
1296 return -ENOMEM;
1297 }
1298
1299 gameport_set_name(gp, "CS4281 Gameport");
1300 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1301 gameport_set_dev_parent(gp, &chip->pci->dev);
1302 gp->open = snd_cs4281_gameport_open;
1303 gp->read = snd_cs4281_gameport_read;
1304 gp->trigger = snd_cs4281_gameport_trigger;
1305 gp->cooked_read = snd_cs4281_gameport_cooked_read;
1306 gameport_set_port_data(gp, chip);
1307
1308 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1309 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1310
1311 gameport_register_port(gp);
1312
1313 return 0;
1314}
1315
1316static void snd_cs4281_free_gameport(cs4281_t *chip)
1317{
1318 if (chip->gameport) {
1319 gameport_unregister_port(chip->gameport);
1320 chip->gameport = NULL;
1321 }
1322}
1323#else
1324static inline int snd_cs4281_create_gameport(cs4281_t *chip) { return -ENOSYS; }
1325static inline void snd_cs4281_free_gameport(cs4281_t *chip) { }
1326#endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1327
1da177e4
LT		 1328static int snd_cs4281_free(cs4281_t *chip)
1329{
1330 snd_cs4281_free_gameport(chip);
1331
1332 if (chip->irq >= 0)
1333 synchronize_irq(chip->irq);
1334
1335 /* Mask interrupts */
1336 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1337 /* Stop the DLL Clock logic. */
1338 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1339 /* Sound System Power Management - Turn Everything OFF */
1340 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1341 /* PCI interface - D3 state */
1342 pci_set_power_state(chip->pci, 3);
1343
1344 if (chip->irq >= 0)
1345 free_irq(chip->irq, (void *)chip);
1346 if (chip->ba0)
1347 iounmap(chip->ba0);
1348 if (chip->ba1)
1349 iounmap(chip->ba1);
1350 pci_release_regions(chip->pci);
1351 pci_disable_device(chip->pci);
1352
1353 kfree(chip);
1354 return 0;
1355}
1356
1357static int snd_cs4281_dev_free(snd_device_t *device)
1358{
1359 cs4281_t *chip = device->device_data;
1360 return snd_cs4281_free(chip);
1361}
1362
1363static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
1364#ifdef CONFIG_PM
1365static int cs4281_suspend(snd_card_t *card, pm_message_t state);
1366static int cs4281_resume(snd_card_t *card);
1367#endif
1368
1369static int __devinit snd_cs4281_create(snd_card_t * card,
1370 struct pci_dev *pci,
1371 cs4281_t ** rchip,
1372 int dual_codec)
1373{
1374 cs4281_t *chip;
1375 unsigned int tmp;
1376 int err;
1377 static snd_device_ops_t ops = {
1378 .dev_free = snd_cs4281_dev_free,
1379 };
1380
1381 *rchip = NULL;
1382 if ((err = pci_enable_device(pci)) < 0)
1383 return err;
e560d8d8 1384 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1385 if (chip == NULL) {
1386 pci_disable_device(pci);
1387 return -ENOMEM;
1388 }
1389 spin_lock_init(&chip->reg_lock);
1390 chip->card = card;
1391 chip->pci = pci;
1392 chip->irq = -1;
1393 pci_set_master(pci);
1394 if (dual_codec < 0 || dual_codec > 3) {
1395 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1396 dual_codec = 0;
1397 }
1398 chip->dual_codec = dual_codec;
1399
1400 if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1401 kfree(chip);
1402 pci_disable_device(pci);
1403 return err;
1404 }
1405 chip->ba0_addr = pci_resource_start(pci, 0);
1406 chip->ba1_addr = pci_resource_start(pci, 1);
1407
1408 if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
1409 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1410 snd_cs4281_free(chip);
1411 return -ENOMEM;
1412 }
1413 chip->irq = pci->irq;
1414
1415 chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0));
1416 chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1));
1417 if (!chip->ba0 || !chip->ba1) {
1418 snd_cs4281_free(chip);
1419 return -ENOMEM;
1420 }
1421
1422 tmp = snd_cs4281_chip_init(chip);
1423 if (tmp) {
1424 snd_cs4281_free(chip);
1425 return tmp;
1426 }
1427
1428 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1429 snd_cs4281_free(chip);
1430 return err;
1431 }
1432
1433 snd_cs4281_proc_init(chip);
1434
1435 snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip);
1436
1437 snd_card_set_dev(card, &pci->dev);
1438
1439 *rchip = chip;
1440 return 0;
1441}
1442
1443static int snd_cs4281_chip_init(cs4281_t *chip)
1444{
1445 unsigned int tmp;
1446 int timeout;
1447 int retry_count = 2;
1448
a488e033
AP		 1449 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1450 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1451 if (tmp & BA0_EPPMC_FPDN)
1452 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1453
1da177e4
LT		 1454 __retry:
1455 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1456 if (tmp != BA0_CFLR_DEFAULT) {
1457 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1458 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1459 if (tmp != BA0_CFLR_DEFAULT) {
1460 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1461 return -EIO;
1462 }
1463 }
1464
1465 /* Set the 'Configuration Write Protect' register
1466 * to 4281h. Allows vendor-defined configuration
1467 * space between 0e4h and 0ffh to be written. */
1468 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1469
1470 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1471 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1472 return -EIO;
1473 }
1474 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1475 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1476 return -EIO;
1477 }
1478
1479 /* Sound System Power Management */
1480 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1481 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1482 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1483
1484 /* Serial Port Power Management */
1485 /* Blast the clock control register to zero so that the
1486 * PLL starts out in a known state, and blast the master serial
1487 * port control register to zero so that the serial ports also
1488 * start out in a known state. */
1489 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1490 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1491
1492 /* Make ESYN go to zero to turn off
1493 * the Sync pulse on the AC97 link. */
1494 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1495 udelay(50);
1496
1497 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1498 * spec) and then drive it high. This is done for non AC97 modes since
1499 * there might be logic external to the CS4281 that uses the ARST# line
1500 * for a reset. */
1501 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1502 udelay(50);
1503 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1504 snd_cs4281_delay(50000);
1505
1506 if (chip->dual_codec)
1507 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1508
1509 /*
1510 * Set the serial port timing configuration.
1511 */
1512 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1513 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1514 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1515
1516 /*
1517 * Start the DLL Clock logic.
1518 */
1519 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1520 snd_cs4281_delay(50000);
1521 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1522
1523 /*
1524 * Wait for the DLL ready signal from the clock logic.
1525 */
1526 timeout = HZ;
1527 do {
1528 /*
1529 * Read the AC97 status register to see if we've seen a CODEC
1530 * signal from the AC97 codec.
1531 */
1532 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1533 goto __ok0;
1534 snd_cs4281_delay_long();
1535 } while (timeout-- > 0);
1536
1537 snd_printk(KERN_ERR "DLLRDY not seen\n");
1538 return -EIO;
1539
1540 __ok0:
1541
1542 /*
1543 * The first thing we do here is to enable sync generation. As soon
1544 * as we start receiving bit clock, we'll start producing the SYNC
1545 * signal.
1546 */
1547 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1548
1549 /*
1550 * Wait for the codec ready signal from the AC97 codec.
1551 */
1552 timeout = HZ;
1553 do {
1554 /*
1555 * Read the AC97 status register to see if we've seen a CODEC
1556 * signal from the AC97 codec.
1557 */
1558 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1559 goto __ok1;
1560 snd_cs4281_delay_long();
1561 } while (timeout-- > 0);
1562
1563 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1564 return -EIO;
1565
1566 __ok1:
1567 if (chip->dual_codec) {
1568 timeout = HZ;
1569 do {
1570 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1571 goto __codec2_ok;
1572 snd_cs4281_delay_long();
1573 } while (timeout-- > 0);
1574 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1575 chip->dual_codec = 0;
1576 __codec2_ok: ;
1577 }
1578
1579 /*
1580 * Assert the valid frame signal so that we can start sending commands
1581 * to the AC97 codec.
1582 */
1583
1584 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1585
1586 /*
1587 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1588 * the codec is pumping ADC data across the AC-link.
1589 */
1590
1591 timeout = HZ;
1592 do {
1593 /*
1594 * Read the input slot valid register and see if input slots 3
1595 * 4 are valid yet.
1596 */
1597 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1598 goto __ok2;
1599 snd_cs4281_delay_long();
1600 } while (timeout-- > 0);
1601
1602 if (--retry_count > 0)
1603 goto __retry;
1604 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1605 return -EIO;
1606
1607 __ok2:
1608
1609 /*
1610 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1611 * commense the transfer of digital audio data to the AC97 codec.
1612 */
1613 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1614
1615 /*
1616 * Initialize DMA structures
1617 */
1618 for (tmp = 0; tmp < 4; tmp++) {
1619 cs4281_dma_t *dma = &chip->dma[tmp];
1620 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1621 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1622 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1623 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1624 dma->regDMR = BA0_DMR0 + (tmp * 8);
1625 dma->regDCR = BA0_DCR0 + (tmp * 8);
1626 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1627 dma->regFCR = BA0_FCR0 + (tmp * 4);
1628 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1629 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1630 snd_cs4281_pokeBA0(chip, dma->regFCR,
1631 BA0_FCR_LS(31) |
1632 BA0_FCR_RS(31) |
1633 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1634 BA0_FCR_OF(dma->fifo_offset));
1635 }
1636
1637 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1638 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1639 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1640 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1641
1642 /* Activate wave playback FIFO for FM playback */
1643 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1644 BA0_FCR_RS(1) |
1645 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1646 BA0_FCR_OF(chip->dma[0].fifo_offset);
1647 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1648 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1649 (chip->src_right_play_slot << 8) |
1650 (chip->src_left_rec_slot << 16) |
1651 (chip->src_right_rec_slot << 24));
1652
1653 /* Initialize digital volume */
1654 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1655 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1656
1657 /* Enable IRQs */
1658 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1659 /* Unmask interrupts */
1660 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1661 BA0_HISR_MIDI |
1662 BA0_HISR_DMAI |
1663 BA0_HISR_DMA(0) |
1664 BA0_HISR_DMA(1) |
1665 BA0_HISR_DMA(2) |
1666 BA0_HISR_DMA(3)));
1667 synchronize_irq(chip->irq);
1668
1669 return 0;
1670}
1671
1672/*
1673 * MIDI section
1674 */
1675
1676static void snd_cs4281_midi_reset(cs4281_t *chip)
1677{
1678 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1679 udelay(100);
1680 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1681}
1682
1683static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
1684{
1685 cs4281_t *chip = substream->rmidi->private_data;
1686
1687 spin_lock_irq(&chip->reg_lock);
1688 chip->midcr |= BA0_MIDCR_RXE;
1689 chip->midi_input = substream;
1690 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1691 snd_cs4281_midi_reset(chip);
1692 } else {
1693 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1694 }
1695 spin_unlock_irq(&chip->reg_lock);
1696 return 0;
1697}
1698
1699static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
1700{
1701 cs4281_t *chip = substream->rmidi->private_data;
1702
1703 spin_lock_irq(&chip->reg_lock);
1704 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1705 chip->midi_input = NULL;
1706 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1707 snd_cs4281_midi_reset(chip);
1708 } else {
1709 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1710 }
1711 chip->uartm &= ~CS4281_MODE_INPUT;
1712 spin_unlock_irq(&chip->reg_lock);
1713 return 0;
1714}
1715
1716static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
1717{
1718 cs4281_t *chip = substream->rmidi->private_data;
1719
1720 spin_lock_irq(&chip->reg_lock);
1721 chip->uartm |= CS4281_MODE_OUTPUT;
1722 chip->midcr |= BA0_MIDCR_TXE;
1723 chip->midi_output = substream;
1724 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1725 snd_cs4281_midi_reset(chip);
1726 } else {
1727 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1728 }
1729 spin_unlock_irq(&chip->reg_lock);
1730 return 0;
1731}
1732
1733static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
1734{
1735 cs4281_t *chip = substream->rmidi->private_data;
1736
1737 spin_lock_irq(&chip->reg_lock);
1738 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1739 chip->midi_output = NULL;
1740 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1741 snd_cs4281_midi_reset(chip);
1742 } else {
1743 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1744 }
1745 chip->uartm &= ~CS4281_MODE_OUTPUT;
1746 spin_unlock_irq(&chip->reg_lock);
1747 return 0;
1748}
1749
1750static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1751{
1752 unsigned long flags;
1753 cs4281_t *chip = substream->rmidi->private_data;
1754
1755 spin_lock_irqsave(&chip->reg_lock, flags);
1756 if (up) {
1757 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1758 chip->midcr |= BA0_MIDCR_RIE;
1759 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1760 }
1761 } else {
1762 if (chip->midcr & BA0_MIDCR_RIE) {
1763 chip->midcr &= ~BA0_MIDCR_RIE;
1764 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1765 }
1766 }
1767 spin_unlock_irqrestore(&chip->reg_lock, flags);
1768}
1769
1770static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1771{
1772 unsigned long flags;
1773 cs4281_t *chip = substream->rmidi->private_data;
1774 unsigned char byte;
1775
1776 spin_lock_irqsave(&chip->reg_lock, flags);
1777 if (up) {
1778 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1779 chip->midcr |= BA0_MIDCR_TIE;
1780 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1781 while ((chip->midcr & BA0_MIDCR_TIE) &&
1782 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1783 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1784 chip->midcr &= ~BA0_MIDCR_TIE;
1785 } else {
1786 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1787 }
1788 }
1789 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1790 }
1791 } else {
1792 if (chip->midcr & BA0_MIDCR_TIE) {
1793 chip->midcr &= ~BA0_MIDCR_TIE;
1794 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1795 }
1796 }
1797 spin_unlock_irqrestore(&chip->reg_lock, flags);
1798}
1799
1800static snd_rawmidi_ops_t snd_cs4281_midi_output =
1801{
1802 .open = snd_cs4281_midi_output_open,
1803 .close = snd_cs4281_midi_output_close,
1804 .trigger = snd_cs4281_midi_output_trigger,
1805};
1806
1807static snd_rawmidi_ops_t snd_cs4281_midi_input =
1808{
1809 .open = snd_cs4281_midi_input_open,
1810 .close = snd_cs4281_midi_input_close,
1811 .trigger = snd_cs4281_midi_input_trigger,
1812};
1813
1814static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
1815{
1816 snd_rawmidi_t *rmidi;
1817 int err;
1818
1819 if (rrawmidi)
1820 *rrawmidi = NULL;
1821 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1822 return err;
1823 strcpy(rmidi->name, "CS4281");
1824 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1825 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1826 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1827 rmidi->private_data = chip;
1828 chip->rmidi = rmidi;
1829 if (rrawmidi)
1830 *rrawmidi = rmidi;
1831 return 0;
1832}
1833
1834/*
1835 * Interrupt handler
1836 */
1837
1838static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1839{
1840 cs4281_t *chip = dev_id;
1841 unsigned int status, dma, val;
1842 cs4281_dma_t *cdma;
1843
1844 if (chip == NULL)
1845 return IRQ_NONE;
1846 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1847 if ((status & 0x7fffffff) == 0) {
1848 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1849 return IRQ_NONE;
1850 }
1851
1852 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1853 for (dma = 0; dma < 4; dma++)
1854 if (status & BA0_HISR_DMA(dma)) {
1855 cdma = &chip->dma[dma];
1856 spin_lock(&chip->reg_lock);
1857 /* ack DMA IRQ */
1858 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1859 /* workaround, sometimes CS4281 acknowledges */
1860 /* end or middle transfer position twice */
1861 cdma->frag++;
1862 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1863 cdma->frag--;
1864 chip->spurious_dhtc_irq++;
1865 spin_unlock(&chip->reg_lock);
1866 continue;
1867 }
1868 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1869 cdma->frag--;
1870 chip->spurious_dtc_irq++;
1871 spin_unlock(&chip->reg_lock);
1872 continue;
1873 }
1874 spin_unlock(&chip->reg_lock);
1875 snd_pcm_period_elapsed(cdma->substream);
1876 }
1877 }
1878
1879 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1880 unsigned char c;
1881
1882 spin_lock(&chip->reg_lock);
1883 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1884 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1885 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1886 continue;
1887 snd_rawmidi_receive(chip->midi_input, &c, 1);
1888 }
1889 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1890 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1891 break;
1892 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1893 chip->midcr &= ~BA0_MIDCR_TIE;
1894 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1895 break;
1896 }
1897 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1898 }
1899 spin_unlock(&chip->reg_lock);
1900 }
1901
1902 /* EOI to the PCI part... reenables interrupts */
1903 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1904
1905 return IRQ_HANDLED;
1906}
1907
1908
1909/*
1910 * OPL3 command
1911 */
1912static void snd_cs4281_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val)
1913{
1914 unsigned long flags;
1915 cs4281_t *chip = opl3->private_data;
1916 void __iomem *port;
1917
1918 if (cmd & OPL3_RIGHT)
1919 port = chip->ba0 + BA0_B1AP; /* right port */
1920 else
1921 port = chip->ba0 + BA0_B0AP; /* left port */
1922
1923 spin_lock_irqsave(&opl3->reg_lock, flags);
1924
1925 writel((unsigned int)cmd, port);
1926 udelay(10);
1927
1928 writel((unsigned int)val, port + 4);
1929 udelay(30);
1930
1931 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1932}
1933
1934static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1935 const struct pci_device_id *pci_id)
1936{
1937 static int dev;
1938 snd_card_t *card;
1939 cs4281_t *chip;
1940 opl3_t *opl3;
1941 int err;
1942
1943 if (dev >= SNDRV_CARDS)
1944 return -ENODEV;
1945 if (!enable[dev]) {
1946 dev++;
1947 return -ENOENT;
1948 }
1949
1950 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1951 if (card == NULL)
1952 return -ENOMEM;
1953
1954 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1955 snd_card_free(card);
1956 return err;
1957 }
1958
1959 if ((err = snd_cs4281_mixer(chip)) < 0) {
1960 snd_card_free(card);
1961 return err;
1962 }
1963 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1964 snd_card_free(card);
1965 return err;
1966 }
1967 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1968 snd_card_free(card);
1969 return err;
1970 }
1971 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1972 snd_card_free(card);
1973 return err;
1974 }
1975 opl3->private_data = chip;
1976 opl3->command = snd_cs4281_opl3_command;
1977 snd_opl3_init(opl3);
1978 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1979 snd_card_free(card);
1980 return err;
1981 }
1982 snd_cs4281_create_gameport(chip);
1983 strcpy(card->driver, "CS4281");
1984 strcpy(card->shortname, "Cirrus Logic CS4281");
1985 sprintf(card->longname, "%s at 0x%lx, irq %d",
1986 card->shortname,
1987 chip->ba0_addr,
1988 chip->irq);
1989
1990 if ((err = snd_card_register(card)) < 0) {
1991 snd_card_free(card);
1992 return err;
1993 }
1994
1995 pci_set_drvdata(pci, card);
1996 dev++;
1997 return 0;
1998}
1999
2000static void __devexit snd_cs4281_remove(struct pci_dev *pci)
2001{
2002 snd_card_free(pci_get_drvdata(pci));
2003 pci_set_drvdata(pci, NULL);
2004}
2005
2006/*
2007 * Power Management
2008 */
2009#ifdef CONFIG_PM
2010
2011static int saved_regs[SUSPEND_REGISTERS] = {
2012 BA0_JSCTL,
2013 BA0_GPIOR,
2014 BA0_SSCR,
2015 BA0_MIDCR,
2016 BA0_SRCSA,
2017 BA0_PASR,
2018 BA0_CASR,
2019 BA0_DACSR,
2020 BA0_ADCSR,
2021 BA0_FMLVC,
2022 BA0_FMRVC,
2023 BA0_PPLVC,
2024 BA0_PPRVC,
2025};
2026
2027#define CLKCR1_CKRA 0x00010000L
2028
2029static int cs4281_suspend(snd_card_t *card, pm_message_t state)
2030{
2031 cs4281_t *chip = card->pm_private_data;
2032 u32 ulCLK;
2033 unsigned int i;
2034
2035 snd_pcm_suspend_all(chip->pcm);
2036
2037 if (chip->ac97)
2038 snd_ac97_suspend(chip->ac97);
2039 if (chip->ac97_secondary)
2040 snd_ac97_suspend(chip->ac97_secondary);
2041
2042 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2043 ulCLK |= CLKCR1_CKRA;
2044 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2045
2046 /* Disable interrupts. */
2047 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2048
2049 /* remember the status registers */
2050 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2051 if (saved_regs[i])
2052 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2053
2054 /* Turn off the serial ports. */
2055 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2056
2057 /* Power off FM, Joystick, AC link, */
2058 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2059
2060 /* DLL off. */
2061 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2062
2063 /* AC link off. */
2064 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2065
2066 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2067 ulCLK &= ~CLKCR1_CKRA;
2068 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2069
2070 pci_disable_device(chip->pci);
2071 return 0;
2072}
2073
2074static int cs4281_resume(snd_card_t *card)
2075{
2076 cs4281_t *chip = card->pm_private_data;
2077 unsigned int i;
2078 u32 ulCLK;
2079
2080 pci_enable_device(chip->pci);
2081 pci_set_master(chip->pci);
2082
2083 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2084 ulCLK |= CLKCR1_CKRA;
2085 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2086
2087 snd_cs4281_chip_init(chip);
2088
2089 /* restore the status registers */
2090 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2091 if (saved_regs[i])
2092 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2093
2094 if (chip->ac97)
2095 snd_ac97_resume(chip->ac97);
2096 if (chip->ac97_secondary)
2097 snd_ac97_resume(chip->ac97_secondary);
2098
2099 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2100 ulCLK &= ~CLKCR1_CKRA;
2101 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2102
2103 return 0;
2104}
2105#endif /* CONFIG_PM */
2106
2107static struct pci_driver driver = {
2108 .name = "CS4281",
2109 .id_table = snd_cs4281_ids,
2110 .probe = snd_cs4281_probe,
2111 .remove = __devexit_p(snd_cs4281_remove),
2112 SND_PCI_PM_CALLBACKS
2113};
2114
2115static int __init alsa_card_cs4281_init(void)
2116{
01d25d46 2117 return pci_register_driver(&driver);
1da177e4
LT		 2118}
2119
2120static void __exit alsa_card_cs4281_exit(void)
2121{
2122 pci_unregister_driver(&driver);
2123}
2124
2125module_init(alsa_card_cs4281_init)
2126module_exit(alsa_card_cs4281_exit)
Linux 6.x block layer and io_uring tree(s)