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[ALSA] Remove xxx_t typedefs: PCI BT87x
[linux-2.6-block.git] / sound / pci / cmipci.c
CommitLineData
1da177e4
LT		 1/*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/* Does not work. Warning may block system in capture mode */
21/* #define USE_VAR48KRATE */
22
23#include <sound/driver.h>
24#include <asm/io.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/init.h>
28#include <linux/pci.h>
29#include <linux/slab.h>
30#include <linux/gameport.h>
31#include <linux/moduleparam.h>
32#include <sound/core.h>
33#include <sound/info.h>
34#include <sound/control.h>
35#include <sound/pcm.h>
36#include <sound/rawmidi.h>
37#include <sound/mpu401.h>
38#include <sound/opl3.h>
39#include <sound/sb.h>
40#include <sound/asoundef.h>
41#include <sound/initval.h>
42
43MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45MODULE_LICENSE("GPL");
46MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52#define SUPPORT_JOYSTICK 1
53#endif
54
55static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58static long mpu_port[SNDRV_CARDS];
59static long fm_port[SNDRV_CARDS];
60static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61#ifdef SUPPORT_JOYSTICK
62static int joystick_port[SNDRV_CARDS];
63#endif
64
65module_param_array(index, int, NULL, 0444);
66MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
67module_param_array(id, charp, NULL, 0444);
68MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
69module_param_array(enable, bool, NULL, 0444);
70MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
71module_param_array(mpu_port, long, NULL, 0444);
72MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73module_param_array(fm_port, long, NULL, 0444);
74MODULE_PARM_DESC(fm_port, "FM port.");
75module_param_array(soft_ac3, bool, NULL, 0444);
76MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
77#ifdef SUPPORT_JOYSTICK
78module_param_array(joystick_port, int, NULL, 0444);
79MODULE_PARM_DESC(joystick_port, "Joystick port address.");
80#endif
81
1da177e4
LT		 82/*
83 * CM8x38 registers definition
84 */
85
86#define CM_REG_FUNCTRL0 0x00
87#define CM_RST_CH1 0x00080000
88#define CM_RST_CH0 0x00040000
89#define CM_CHEN1 0x00020000 /* ch1: enable */
90#define CM_CHEN0 0x00010000 /* ch0: enable */
91#define CM_PAUSE1 0x00000008 /* ch1: pause */
92#define CM_PAUSE0 0x00000004 /* ch0: pause */
93#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
94#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
95
96#define CM_REG_FUNCTRL1 0x04
97#define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
98#define CM_ASFC_SHIFT 13
99#define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
100#define CM_DSFC_SHIFT 10
101#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
102#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
103#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
104#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
105#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
106#define CM_BREQ 0x00000010 /* bus master enabled */
107#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
108#define CM_UART_EN 0x00000004 /* UART */
109#define CM_JYSTK_EN 0x00000002 /* joy stick */
110
111#define CM_REG_CHFORMAT 0x08
112
113#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
114#define CM_CHB3D 0x20000000 /* 4 channels */
115
116#define CM_CHIP_MASK1 0x1f000000
117#define CM_CHIP_037 0x01000000
118
119#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
120#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
121#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
122/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
123
124#define CM_ADCBITLEN_MASK 0x0000C000
125#define CM_ADCBITLEN_16 0x00000000
126#define CM_ADCBITLEN_15 0x00004000
127#define CM_ADCBITLEN_14 0x00008000
128#define CM_ADCBITLEN_13 0x0000C000
129
130#define CM_ADCDACLEN_MASK 0x00003000
131#define CM_ADCDACLEN_060 0x00000000
132#define CM_ADCDACLEN_066 0x00001000
133#define CM_ADCDACLEN_130 0x00002000
134#define CM_ADCDACLEN_280 0x00003000
135
136#define CM_CH1_SRATE_176K 0x00000800
137#define CM_CH1_SRATE_88K 0x00000400
138#define CM_CH0_SRATE_176K 0x00000200
139#define CM_CH0_SRATE_88K 0x00000100
140
141#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
142
143#define CM_CH1FMT_MASK 0x0000000C
144#define CM_CH1FMT_SHIFT 2
145#define CM_CH0FMT_MASK 0x00000003
146#define CM_CH0FMT_SHIFT 0
147
148#define CM_REG_INT_HLDCLR 0x0C
149#define CM_CHIP_MASK2 0xff000000
150#define CM_CHIP_039 0x04000000
151#define CM_CHIP_039_6CH 0x01000000
152#define CM_CHIP_055 0x08000000
153#define CM_CHIP_8768 0x20000000
154#define CM_TDMA_INT_EN 0x00040000
155#define CM_CH1_INT_EN 0x00020000
156#define CM_CH0_INT_EN 0x00010000
157#define CM_INT_HOLD 0x00000002
158#define CM_INT_CLEAR 0x00000001
159
160#define CM_REG_INT_STATUS 0x10
161#define CM_INTR 0x80000000
162#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
163#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
164#define CM_UARTINT 0x00010000
165#define CM_LTDMAINT 0x00008000
166#define CM_HTDMAINT 0x00004000
167#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
168#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
169#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
170#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
171#define CM_CH1BUSY 0x00000008
172#define CM_CH0BUSY 0x00000004
173#define CM_CHINT1 0x00000002
174#define CM_CHINT0 0x00000001
175
176#define CM_REG_LEGACY_CTRL 0x14
177#define CM_NXCHG 0x80000000 /* h/w multi channels? */
178#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
179#define CM_VMPU_330 0x00000000
180#define CM_VMPU_320 0x20000000
181#define CM_VMPU_310 0x40000000
182#define CM_VMPU_300 0x60000000
183#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
184#define CM_VSBSEL_220 0x00000000
185#define CM_VSBSEL_240 0x04000000
186#define CM_VSBSEL_260 0x08000000
187#define CM_VSBSEL_280 0x0C000000
188#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
189#define CM_FMSEL_388 0x00000000
190#define CM_FMSEL_3C8 0x01000000
191#define CM_FMSEL_3E0 0x02000000
192#define CM_FMSEL_3E8 0x03000000
193#define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
194#define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
195#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
196#define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
197#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
198#define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
199
200#define CM_REG_MISC_CTRL 0x18
201#define CM_PWD 0x80000000
202#define CM_RESET 0x40000000
203#define CM_SFIL_MASK 0x30000000
204#define CM_TXVX 0x08000000
205#define CM_N4SPK3D 0x04000000 /* 4ch output */
206#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
207#define CM_SPDIF48K 0x01000000 /* write */
208#define CM_SPATUS48K 0x01000000 /* read */
209#define CM_ENDBDAC 0x00800000 /* enable dual dac */
210#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
211#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
212#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
213#define CM_FM_EN 0x00080000 /* enalbe FM */
214#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
215#define CM_VIDWPDSB 0x00010000
216#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
217#define CM_MASK_EN 0x00004000
218#define CM_VIDWPPRT 0x00002000
219#define CM_SFILENB 0x00001000
220#define CM_MMODE_MASK 0x00000E00
221#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
222#define CM_ENCENTER 0x00000080
223#define CM_FLINKON 0x00000040
224#define CM_FLINKOFF 0x00000020
225#define CM_MIDSMP 0x00000010
226#define CM_UPDDMA_MASK 0x0000000C
227#define CM_TWAIT_MASK 0x00000003
228
229 /* byte */
230#define CM_REG_MIXER0 0x20
231
232#define CM_REG_SB16_DATA 0x22
233#define CM_REG_SB16_ADDR 0x23
234
235#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
236#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
237#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
238#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
239
240#define CM_REG_MIXER1 0x24
241#define CM_FMMUTE 0x80 /* mute FM */
242#define CM_FMMUTE_SHIFT 7
243#define CM_WSMUTE 0x40 /* mute PCM */
244#define CM_WSMUTE_SHIFT 6
245#define CM_SPK4 0x20 /* lin-in -> rear line out */
246#define CM_SPK4_SHIFT 5
247#define CM_REAR2FRONT 0x10 /* exchange rear/front */
248#define CM_REAR2FRONT_SHIFT 4
249#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
250#define CM_WAVEINL_SHIFT 3
251#define CM_WAVEINR 0x04 /* digical wave rec. right */
252#define CM_WAVEINR_SHIFT 2
253#define CM_X3DEN 0x02 /* 3D surround enable */
254#define CM_X3DEN_SHIFT 1
255#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
256#define CM_CDPLAY_SHIFT 0
257
258#define CM_REG_MIXER2 0x25
259#define CM_RAUXREN 0x80 /* AUX right capture */
260#define CM_RAUXREN_SHIFT 7
261#define CM_RAUXLEN 0x40 /* AUX left capture */
262#define CM_RAUXLEN_SHIFT 6
263#define CM_VAUXRM 0x20 /* AUX right mute */
264#define CM_VAUXRM_SHIFT 5
265#define CM_VAUXLM 0x10 /* AUX left mute */
266#define CM_VAUXLM_SHIFT 4
267#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
268#define CM_VADMIC_SHIFT 1
269#define CM_MICGAINZ 0x01 /* mic boost */
270#define CM_MICGAINZ_SHIFT 0
271
272#define CM_REG_AUX_VOL 0x26
273#define CM_VAUXL_MASK 0xf0
274#define CM_VAUXR_MASK 0x0f
275
276#define CM_REG_MISC 0x27
277#define CM_XGPO1 0x20
278// #define CM_XGPBIO 0x04
279#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
280#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
281#define CM_SPDVALID 0x02 /* spdif input valid check */
282#define CM_DMAUTO 0x01
283
284#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
285/*
286 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
287 * or identical with AC97 codec?
288 */
289#define CM_REG_EXTERN_CODEC CM_REG_AC97
290
291/*
292 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
293 */
294#define CM_REG_MPU_PCI 0x40
295
296/*
297 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
298 */
299#define CM_REG_FM_PCI 0x50
300
301/*
2eff7ec8 302 * access from SB-mixer port
1da177e4
LT		 303 */
304#define CM_REG_EXTENT_IND 0xf0
305#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
306#define CM_VPHONE_SHIFT 5
307#define CM_VPHOM 0x10 /* Phone mute control */
308#define CM_VSPKM 0x08 /* Speaker mute control, default high */
309#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
310#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
2eff7ec8 311#define CM_VADMIC3 0x01 /* Mic record boost */
1da177e4
LT		 312
313/*
314 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
315 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
316 * unit (readonly?).
317 */
318#define CM_REG_PLL 0xf8
319
320/*
321 * extended registers
322 */
323#define CM_REG_CH0_FRAME1 0x80 /* base address */
324#define CM_REG_CH0_FRAME2 0x84
325#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
326#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
327#define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */
328#define CM_CHB3D8C 0x20 /* 7.1 channels support */
329#define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */
330#define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */
331#define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */
332#define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */
333#define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */
334
335/*
336 * size of i/o region
337 */
338#define CM_EXTENT_CODEC 0x100
339#define CM_EXTENT_MIDI 0x2
340#define CM_EXTENT_SYNTH 0x4
341
342
1da177e4
LT		 343/*
344 * channels for playback / capture
345 */
346#define CM_CH_PLAY 0
347#define CM_CH_CAPT 1
348
349/*
350 * flags to check device open/close
351 */
352#define CM_OPEN_NONE 0
353#define CM_OPEN_CH_MASK 0x01
354#define CM_OPEN_DAC 0x10
355#define CM_OPEN_ADC 0x20
356#define CM_OPEN_SPDIF 0x40
357#define CM_OPEN_MCHAN 0x80
358#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
359#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
360#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
361#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
362#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
363#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
364
365
366#if CM_CH_PLAY == 1
367#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
368#define CM_PLAYBACK_SPDF CM_SPDF_1
369#define CM_CAPTURE_SPDF CM_SPDF_0
370#else
371#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
372#define CM_PLAYBACK_SPDF CM_SPDF_0
373#define CM_CAPTURE_SPDF CM_SPDF_1
374#endif
375
376
377/*
378 * driver data
379 */
380
381typedef struct snd_stru_cmipci cmipci_t;
382typedef struct snd_stru_cmipci_pcm cmipci_pcm_t;
383
384struct snd_stru_cmipci_pcm {
385 snd_pcm_substream_t *substream;
386 int running; /* dac/adc running? */
387 unsigned int dma_size; /* in frames */
388 unsigned int period_size; /* in frames */
389 unsigned int offset; /* physical address of the buffer */
390 unsigned int fmt; /* format bits */
391 int ch; /* channel (0/1) */
392 unsigned int is_dac; /* is dac? */
393 int bytes_per_frame;
394 int shift;
395};
396
397/* mixer elements toggled/resumed during ac3 playback */
398struct cmipci_mixer_auto_switches {
399 const char *name; /* switch to toggle */
400 int toggle_on; /* value to change when ac3 mode */
401};
402static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
403 {"PCM Playback Switch", 0},
404 {"IEC958 Output Switch", 1},
405 {"IEC958 Mix Analog", 0},
406 // {"IEC958 Out To DAC", 1}, // no longer used
407 {"IEC958 Loop", 0},
408};
409#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
410
411struct snd_stru_cmipci {
412 snd_card_t *card;
413
414 struct pci_dev *pci;
415 unsigned int device; /* device ID */
416 int irq;
417
418 unsigned long iobase;
419 unsigned int ctrl; /* FUNCTRL0 current value */
420
421 snd_pcm_t *pcm; /* DAC/ADC PCM */
422 snd_pcm_t *pcm2; /* 2nd DAC */
423 snd_pcm_t *pcm_spdif; /* SPDIF */
424
425 int chip_version;
426 int max_channels;
427 unsigned int has_dual_dac: 1;
428 unsigned int can_ac3_sw: 1;
429 unsigned int can_ac3_hw: 1;
430 unsigned int can_multi_ch: 1;
431 unsigned int do_soft_ac3: 1;
432
433 unsigned int spdif_playback_avail: 1; /* spdif ready? */
434 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
435 int spdif_counter; /* for software AC3 */
436
437 unsigned int dig_status;
438 unsigned int dig_pcm_status;
439
440 snd_pcm_hardware_t *hw_info[3]; /* for playbacks */
441
442 int opened[2]; /* open mode */
443 struct semaphore open_mutex;
444
445 unsigned int mixer_insensitive: 1;
446 snd_kcontrol_t *mixer_res_ctl[CM_SAVED_MIXERS];
447 int mixer_res_status[CM_SAVED_MIXERS];
448
1da177e4
LT		 449 cmipci_pcm_t channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
450
451 /* external MIDI */
452 snd_rawmidi_t *rmidi;
453
454#ifdef SUPPORT_JOYSTICK
455 struct gameport *gameport;
456#endif
457
458 spinlock_t reg_lock;
459};
460
461
462/* read/write operations for dword register */
77933d72 463static inline void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data)
1da177e4
LT		 464{
465 outl(data, cm->iobase + cmd);
466}
77933d72
JJ		 467
468static inline unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd)
1da177e4
LT		 469{
470 return inl(cm->iobase + cmd);
471}
472
473/* read/write operations for word register */
77933d72 474static inline void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data)
1da177e4
LT		 475{
476 outw(data, cm->iobase + cmd);
477}
77933d72
JJ		 478
479static inline unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd)
1da177e4
LT		 480{
481 return inw(cm->iobase + cmd);
482}
483
484/* read/write operations for byte register */
77933d72 485static inline void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data)
1da177e4
LT		 486{
487 outb(data, cm->iobase + cmd);
488}
489
77933d72 490static inline unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd)
1da177e4
LT		 491{
492 return inb(cm->iobase + cmd);
493}
494
495/* bit operations for dword register */
01d25d46 496static int snd_cmipci_set_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
1da177e4 497{
01d25d46
TI		 498 unsigned int val, oval;
499 val = oval = inl(cm->iobase + cmd);
1da177e4 500 val |= flag;
01d25d46
TI		 501 if (val == oval)
502 return 0;
1da177e4 503 outl(val, cm->iobase + cmd);
01d25d46 504 return 1;
1da177e4
LT		 505}
506
01d25d46 507static int snd_cmipci_clear_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
1da177e4 508{
01d25d46
TI		 509 unsigned int val, oval;
510 val = oval = inl(cm->iobase + cmd);
1da177e4 511 val &= ~flag;
01d25d46
TI		 512 if (val == oval)
513 return 0;
1da177e4 514 outl(val, cm->iobase + cmd);
01d25d46 515 return 1;
1da177e4
LT		 516}
517
1da177e4 518/* bit operations for byte register */
01d25d46 519static int snd_cmipci_set_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
1da177e4 520{
01d25d46
TI		 521 unsigned char val, oval;
522 val = oval = inb(cm->iobase + cmd);
1da177e4 523 val |= flag;
01d25d46
TI		 524 if (val == oval)
525 return 0;
1da177e4 526 outb(val, cm->iobase + cmd);
01d25d46 527 return 1;
1da177e4
LT		 528}
529
01d25d46 530static int snd_cmipci_clear_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
1da177e4 531{
01d25d46
TI		 532 unsigned char val, oval;
533 val = oval = inb(cm->iobase + cmd);
1da177e4 534 val &= ~flag;
01d25d46
TI		 535 if (val == oval)
536 return 0;
1da177e4 537 outb(val, cm->iobase + cmd);
01d25d46 538 return 1;
1da177e4 539}
1da177e4
LT		 540
541
542/*
543 * PCM interface
544 */
545
546/*
547 * calculate frequency
548 */
549
550static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
551
552static unsigned int snd_cmipci_rate_freq(unsigned int rate)
553{
554 unsigned int i;
555 for (i = 0; i < ARRAY_SIZE(rates); i++) {
556 if (rates[i] == rate)
557 return i;
558 }
559 snd_BUG();
560 return 0;
561}
562
563#ifdef USE_VAR48KRATE
564/*
565 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
566 * does it this way .. maybe not. Never get any information from C-Media about
567 * that <werner@suse.de>.
568 */
569static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
570{
571 unsigned int delta, tolerance;
572 int xm, xn, xr;
573
574 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
575 rate <<= 1;
576 *n = -1;
577 if (*r > 0xff)
578 goto out;
579 tolerance = rate*CM_TOLERANCE_RATE;
580
581 for (xn = (1+2); xn < (0x1f+2); xn++) {
582 for (xm = (1+2); xm < (0xff+2); xm++) {
583 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
584
585 if (xr < rate)
586 delta = rate - xr;
587 else
588 delta = xr - rate;
589
590 /*
591 * If we found one, remember this,
592 * and try to find a closer one
593 */
594 if (delta < tolerance) {
595 tolerance = delta;
596 *m = xm - 2;
597 *n = xn - 2;
598 }
599 }
600 }
601out:
602 return (*n > -1);
603}
604
605/*
606 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
607 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
608 * at the register CM_REG_FUNCTRL1 (0x04).
609 * Problem: other ways are also possible (any information about that?)
610 */
611static void snd_cmipci_set_pll(cmipci_t *cm, unsigned int rate, unsigned int slot)
612{
613 unsigned int reg = CM_REG_PLL + slot;
614 /*
615 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
616 * for DSFC/ASFC (000 upto 111).
617 */
618
619 /* FIXME: Init (Do we've to set an other register first before programming?) */
620
621 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
622 snd_cmipci_write_b(cm, reg, rate>>8);
623 snd_cmipci_write_b(cm, reg, rate&0xff);
624
625 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
626}
627#endif /* USE_VAR48KRATE */
628
629static int snd_cmipci_hw_params(snd_pcm_substream_t * substream,
630 snd_pcm_hw_params_t * hw_params)
631{
632 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
633}
634
635static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t * substream,
636 snd_pcm_hw_params_t * hw_params)
637{
638 cmipci_t *cm = snd_pcm_substream_chip(substream);
639 if (params_channels(hw_params) > 2) {
640 down(&cm->open_mutex);
641 if (cm->opened[CM_CH_PLAY]) {
642 up(&cm->open_mutex);
643 return -EBUSY;
644 }
645 /* reserve the channel A */
646 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
647 up(&cm->open_mutex);
648 }
649 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
650}
651
652static void snd_cmipci_ch_reset(cmipci_t *cm, int ch)
653{
654 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
655 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
656 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
657 udelay(10);
658}
659
660static int snd_cmipci_hw_free(snd_pcm_substream_t * substream)
661{
662 return snd_pcm_lib_free_pages(substream);
663}
664
665
666/*
667 */
668
669static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
670static snd_pcm_hw_constraint_list_t hw_constraints_channels_4 = {
671 .count = 3,
672 .list = hw_channels,
673 .mask = 0,
674};
675static snd_pcm_hw_constraint_list_t hw_constraints_channels_6 = {
676 .count = 5,
677 .list = hw_channels,
678 .mask = 0,
679};
680static snd_pcm_hw_constraint_list_t hw_constraints_channels_8 = {
681 .count = 6,
682 .list = hw_channels,
683 .mask = 0,
684};
685
686static int set_dac_channels(cmipci_t *cm, cmipci_pcm_t *rec, int channels)
687{
688 if (channels > 2) {
689 if (! cm->can_multi_ch)
690 return -EINVAL;
691 if (rec->fmt != 0x03) /* stereo 16bit only */
692 return -EINVAL;
693
694 spin_lock_irq(&cm->reg_lock);
695 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
696 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
697 if (channels > 4) {
698 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
699 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
700 } else {
701 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
702 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
703 }
704 if (channels >= 6) {
705 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
706 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
707 } else {
708 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
709 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
710 }
711 if (cm->chip_version == 68) {
712 if (channels == 8) {
713 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
714 } else {
715 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
716 }
717 }
718 spin_unlock_irq(&cm->reg_lock);
719
720 } else {
721 if (cm->can_multi_ch) {
722 spin_lock_irq(&cm->reg_lock);
723 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
724 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
725 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
726 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
727 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
728 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
729 spin_unlock_irq(&cm->reg_lock);
730 }
731 }
732 return 0;
733}
734
735
736/*
737 * prepare playback/capture channel
738 * channel to be used must have been set in rec->ch.
739 */
740static int snd_cmipci_pcm_prepare(cmipci_t *cm, cmipci_pcm_t *rec,
741 snd_pcm_substream_t *substream)
742{
743 unsigned int reg, freq, val;
744 snd_pcm_runtime_t *runtime = substream->runtime;
745
746 rec->fmt = 0;
747 rec->shift = 0;
748 if (snd_pcm_format_width(runtime->format) >= 16) {
749 rec->fmt |= 0x02;
750 if (snd_pcm_format_width(runtime->format) > 16)
751 rec->shift++; /* 24/32bit */
752 }
753 if (runtime->channels > 1)
754 rec->fmt |= 0x01;
755 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
756 snd_printd("cannot set dac channels\n");
757 return -EINVAL;
758 }
759
760 rec->offset = runtime->dma_addr;
761 /* buffer and period sizes in frame */
762 rec->dma_size = runtime->buffer_size << rec->shift;
763 rec->period_size = runtime->period_size << rec->shift;
764 if (runtime->channels > 2) {
765 /* multi-channels */
766 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
767 rec->period_size = (rec->period_size * runtime->channels) / 2;
768 }
769
770 spin_lock_irq(&cm->reg_lock);
771
772 /* set buffer address */
773 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
774 snd_cmipci_write(cm, reg, rec->offset);
775 /* program sample counts */
776 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
777 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
778 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
779
780 /* set adc/dac flag */
781 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
782 if (rec->is_dac)
783 cm->ctrl &= ~val;
784 else
785 cm->ctrl |= val;
786 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
787 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
788
789 /* set sample rate */
790 freq = snd_cmipci_rate_freq(runtime->rate);
791 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
792 if (rec->ch) {
793 val &= ~CM_ASFC_MASK;
794 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
795 } else {
796 val &= ~CM_DSFC_MASK;
797 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
798 }
799 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
800 //snd_printd("cmipci: functrl1 = %08x\n", val);
801
802 /* set format */
803 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
804 if (rec->ch) {
805 val &= ~CM_CH1FMT_MASK;
806 val |= rec->fmt << CM_CH1FMT_SHIFT;
807 } else {
808 val &= ~CM_CH0FMT_MASK;
809 val |= rec->fmt << CM_CH0FMT_SHIFT;
810 }
811 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
812 //snd_printd("cmipci: chformat = %08x\n", val);
813
814 rec->running = 0;
815 spin_unlock_irq(&cm->reg_lock);
816
817 return 0;
818}
819
820/*
821 * PCM trigger/stop
822 */
823static int snd_cmipci_pcm_trigger(cmipci_t *cm, cmipci_pcm_t *rec,
824 snd_pcm_substream_t *substream, int cmd)
825{
826 unsigned int inthld, chen, reset, pause;
827 int result = 0;
828
829 inthld = CM_CH0_INT_EN << rec->ch;
830 chen = CM_CHEN0 << rec->ch;
831 reset = CM_RST_CH0 << rec->ch;
832 pause = CM_PAUSE0 << rec->ch;
833
834 spin_lock(&cm->reg_lock);
835 switch (cmd) {
836 case SNDRV_PCM_TRIGGER_START:
837 rec->running = 1;
838 /* set interrupt */
839 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
840 cm->ctrl |= chen;
841 /* enable channel */
842 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
843 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
844 break;
845 case SNDRV_PCM_TRIGGER_STOP:
846 rec->running = 0;
847 /* disable interrupt */
848 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
849 /* reset */
850 cm->ctrl &= ~chen;
851 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
852 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
853 break;
854 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
855 cm->ctrl |= pause;
856 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
857 break;
858 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
859 cm->ctrl &= ~pause;
860 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
861 break;
862 default:
863 result = -EINVAL;
864 break;
865 }
866 spin_unlock(&cm->reg_lock);
867 return result;
868}
869
870/*
871 * return the current pointer
872 */
873static snd_pcm_uframes_t snd_cmipci_pcm_pointer(cmipci_t *cm, cmipci_pcm_t *rec,
874 snd_pcm_substream_t *substream)
875{
876 size_t ptr;
877 unsigned int reg;
878 if (!rec->running)
879 return 0;
880#if 1 // this seems better..
881 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
882 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
883 ptr >>= rec->shift;
884#else
885 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
886 ptr = snd_cmipci_read(cm, reg) - rec->offset;
887 ptr = bytes_to_frames(substream->runtime, ptr);
888#endif
889 if (substream->runtime->channels > 2)
890 ptr = (ptr * 2) / substream->runtime->channels;
891 return ptr;
892}
893
894/*
895 * playback
896 */
897
898static int snd_cmipci_playback_trigger(snd_pcm_substream_t *substream,
899 int cmd)
900{
901 cmipci_t *cm = snd_pcm_substream_chip(substream);
902 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
903}
904
905static snd_pcm_uframes_t snd_cmipci_playback_pointer(snd_pcm_substream_t *substream)
906{
907 cmipci_t *cm = snd_pcm_substream_chip(substream);
908 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
909}
910
911
912
913/*
914 * capture
915 */
916
917static int snd_cmipci_capture_trigger(snd_pcm_substream_t *substream,
918 int cmd)
919{
920 cmipci_t *cm = snd_pcm_substream_chip(substream);
921 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
922}
923
924static snd_pcm_uframes_t snd_cmipci_capture_pointer(snd_pcm_substream_t *substream)
925{
926 cmipci_t *cm = snd_pcm_substream_chip(substream);
927 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
928}
929
930
931/*
932 * hw preparation for spdif
933 */
934
935static int snd_cmipci_spdif_default_info(snd_kcontrol_t *kcontrol,
936 snd_ctl_elem_info_t *uinfo)
937{
938 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
939 uinfo->count = 1;
940 return 0;
941}
942
943static int snd_cmipci_spdif_default_get(snd_kcontrol_t *kcontrol,
944 snd_ctl_elem_value_t *ucontrol)
945{
946 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
947 int i;
948
949 spin_lock_irq(&chip->reg_lock);
950 for (i = 0; i < 4; i++)
951 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
952 spin_unlock_irq(&chip->reg_lock);
953 return 0;
954}
955
956static int snd_cmipci_spdif_default_put(snd_kcontrol_t * kcontrol,
957 snd_ctl_elem_value_t * ucontrol)
958{
959 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
960 int i, change;
961 unsigned int val;
962
963 val = 0;
964 spin_lock_irq(&chip->reg_lock);
965 for (i = 0; i < 4; i++)
966 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
967 change = val != chip->dig_status;
968 chip->dig_status = val;
969 spin_unlock_irq(&chip->reg_lock);
970 return change;
971}
972
973static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata =
974{
975 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
976 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
977 .info = snd_cmipci_spdif_default_info,
978 .get = snd_cmipci_spdif_default_get,
979 .put = snd_cmipci_spdif_default_put
980};
981
982static int snd_cmipci_spdif_mask_info(snd_kcontrol_t *kcontrol,
983 snd_ctl_elem_info_t *uinfo)
984{
985 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
986 uinfo->count = 1;
987 return 0;
988}
989
990static int snd_cmipci_spdif_mask_get(snd_kcontrol_t * kcontrol,
991 snd_ctl_elem_value_t *ucontrol)
992{
993 ucontrol->value.iec958.status[0] = 0xff;
994 ucontrol->value.iec958.status[1] = 0xff;
995 ucontrol->value.iec958.status[2] = 0xff;
996 ucontrol->value.iec958.status[3] = 0xff;
997 return 0;
998}
999
1000static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata =
1001{
1002 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1003 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1004 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1005 .info = snd_cmipci_spdif_mask_info,
1006 .get = snd_cmipci_spdif_mask_get,
1007};
1008
1009static int snd_cmipci_spdif_stream_info(snd_kcontrol_t *kcontrol,
1010 snd_ctl_elem_info_t *uinfo)
1011{
1012 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1013 uinfo->count = 1;
1014 return 0;
1015}
1016
1017static int snd_cmipci_spdif_stream_get(snd_kcontrol_t *kcontrol,
1018 snd_ctl_elem_value_t *ucontrol)
1019{
1020 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1021 int i;
1022
1023 spin_lock_irq(&chip->reg_lock);
1024 for (i = 0; i < 4; i++)
1025 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1026 spin_unlock_irq(&chip->reg_lock);
1027 return 0;
1028}
1029
1030static int snd_cmipci_spdif_stream_put(snd_kcontrol_t *kcontrol,
1031 snd_ctl_elem_value_t *ucontrol)
1032{
1033 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1034 int i, change;
1035 unsigned int val;
1036
1037 val = 0;
1038 spin_lock_irq(&chip->reg_lock);
1039 for (i = 0; i < 4; i++)
1040 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1041 change = val != chip->dig_pcm_status;
1042 chip->dig_pcm_status = val;
1043 spin_unlock_irq(&chip->reg_lock);
1044 return change;
1045}
1046
1047static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata =
1048{
1049 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1050 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1051 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1052 .info = snd_cmipci_spdif_stream_info,
1053 .get = snd_cmipci_spdif_stream_get,
1054 .put = snd_cmipci_spdif_stream_put
1055};
1056
1057/*
1058 */
1059
1060/* save mixer setting and mute for AC3 playback */
1061static int save_mixer_state(cmipci_t *cm)
1062{
1063 if (! cm->mixer_insensitive) {
1064 snd_ctl_elem_value_t *val;
1065 unsigned int i;
1066
1067 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1068 if (!val)
1069 return -ENOMEM;
1070 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1071 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1072 if (ctl) {
1073 int event;
1074 memset(val, 0, sizeof(*val));
1075 ctl->get(ctl, val);
1076 cm->mixer_res_status[i] = val->value.integer.value[0];
1077 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1078 event = SNDRV_CTL_EVENT_MASK_INFO;
1079 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1080 ctl->put(ctl, val); /* toggle */
1081 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1082 }
1083 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1084 snd_ctl_notify(cm->card, event, &ctl->id);
1085 }
1086 }
1087 kfree(val);
1088 cm->mixer_insensitive = 1;
1089 }
1090 return 0;
1091}
1092
1093
1094/* restore the previously saved mixer status */
1095static void restore_mixer_state(cmipci_t *cm)
1096{
1097 if (cm->mixer_insensitive) {
1098 snd_ctl_elem_value_t *val;
1099 unsigned int i;
1100
1101 val = kmalloc(sizeof(*val), GFP_KERNEL);
1102 if (!val)
1103 return;
1104 cm->mixer_insensitive = 0; /* at first clear this;
1105 otherwise the changes will be ignored */
1106 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1107 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1108 if (ctl) {
1109 int event;
1110
1111 memset(val, 0, sizeof(*val));
1112 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1113 ctl->get(ctl, val);
1114 event = SNDRV_CTL_EVENT_MASK_INFO;
1115 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1116 val->value.integer.value[0] = cm->mixer_res_status[i];
1117 ctl->put(ctl, val);
1118 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1119 }
1120 snd_ctl_notify(cm->card, event, &ctl->id);
1121 }
1122 }
1123 kfree(val);
1124 }
1125}
1126
1127/* spinlock held! */
1128static void setup_ac3(cmipci_t *cm, snd_pcm_substream_t *subs, int do_ac3, int rate)
1129{
1130 if (do_ac3) {
1131 /* AC3EN for 037 */
1132 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1133 /* AC3EN for 039 */
1134 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1135
1136 if (cm->can_ac3_hw) {
1137 /* SPD24SEL for 037, 0x02 */
1138 /* SPD24SEL for 039, 0x20, but cannot be set */
1139 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1140 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1141 } else { /* can_ac3_sw */
1142 /* SPD32SEL for 037 & 039, 0x20 */
1143 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1144 /* set 176K sample rate to fix 033 HW bug */
1145 if (cm->chip_version == 33) {
1146 if (rate >= 48000) {
1147 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1148 } else {
1149 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1150 }
1151 }
1152 }
1153
1154 } else {
1155 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1156 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1157
1158 if (cm->can_ac3_hw) {
1159 /* chip model >= 37 */
1160 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1161 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1162 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1163 } else {
1164 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1165 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1166 }
1167 } else {
1168 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1169 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1170 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1171 }
1172 }
1173}
1174
1175static int setup_spdif_playback(cmipci_t *cm, snd_pcm_substream_t *subs, int up, int do_ac3)
1176{
1177 int rate, err;
1178
1179 rate = subs->runtime->rate;
1180
1181 if (up && do_ac3)
1182 if ((err = save_mixer_state(cm)) < 0)
1183 return err;
1184
1185 spin_lock_irq(&cm->reg_lock);
1186 cm->spdif_playback_avail = up;
1187 if (up) {
1188 /* they are controlled via "IEC958 Output Switch" */
1189 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1190 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1191 if (cm->spdif_playback_enabled)
1192 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1193 setup_ac3(cm, subs, do_ac3, rate);
1194
1195 if (rate == 48000)
1196 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1197 else
1198 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1199
1200 } else {
1201 /* they are controlled via "IEC958 Output Switch" */
1202 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1203 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1204 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1205 setup_ac3(cm, subs, 0, 0);
1206 }
1207 spin_unlock_irq(&cm->reg_lock);
1208 return 0;
1209}
1210
1211
1212/*
1213 * preparation
1214 */
1215
1216/* playback - enable spdif only on the certain condition */
1217static int snd_cmipci_playback_prepare(snd_pcm_substream_t *substream)
1218{
1219 cmipci_t *cm = snd_pcm_substream_chip(substream);
1220 int rate = substream->runtime->rate;
1221 int err, do_spdif, do_ac3 = 0;
1222
1223 do_spdif = ((rate == 44100 || rate == 48000) &&
1224 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1225 substream->runtime->channels == 2);
1226 if (do_spdif && cm->can_ac3_hw)
1227 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1228 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1229 return err;
1230 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1231}
1232
1233/* playback (via device #2) - enable spdif always */
1234static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t *substream)
1235{
1236 cmipci_t *cm = snd_pcm_substream_chip(substream);
1237 int err, do_ac3;
1238
1239 if (cm->can_ac3_hw)
1240 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1241 else
1242 do_ac3 = 1; /* doesn't matter */
1243 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1244 return err;
1245 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1246}
1247
1248static int snd_cmipci_playback_hw_free(snd_pcm_substream_t *substream)
1249{
1250 cmipci_t *cm = snd_pcm_substream_chip(substream);
1251 setup_spdif_playback(cm, substream, 0, 0);
1252 restore_mixer_state(cm);
1253 return snd_cmipci_hw_free(substream);
1254}
1255
1256/* capture */
1257static int snd_cmipci_capture_prepare(snd_pcm_substream_t *substream)
1258{
1259 cmipci_t *cm = snd_pcm_substream_chip(substream);
1260 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1261}
1262
1263/* capture with spdif (via device #2) */
1264static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t *substream)
1265{
1266 cmipci_t *cm = snd_pcm_substream_chip(substream);
1267
1268 spin_lock_irq(&cm->reg_lock);
1269 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1270 spin_unlock_irq(&cm->reg_lock);
1271
1272 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1273}
1274
1275static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t *subs)
1276{
1277 cmipci_t *cm = snd_pcm_substream_chip(subs);
1278
1279 spin_lock_irq(&cm->reg_lock);
1280 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1281 spin_unlock_irq(&cm->reg_lock);
1282
1283 return snd_cmipci_hw_free(subs);
1284}
1285
1286
1287/*
1288 * interrupt handler
1289 */
1290static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1291{
1292 cmipci_t *cm = dev_id;
1293 unsigned int status, mask = 0;
1294
1295 /* fastpath out, to ease interrupt sharing */
1296 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1297 if (!(status & CM_INTR))
1298 return IRQ_NONE;
1299
1300 /* acknowledge interrupt */
1301 spin_lock(&cm->reg_lock);
1302 if (status & CM_CHINT0)
1303 mask |= CM_CH0_INT_EN;
1304 if (status & CM_CHINT1)
1305 mask |= CM_CH1_INT_EN;
1306 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1307 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1308 spin_unlock(&cm->reg_lock);
1309
1310 if (cm->rmidi && (status & CM_UARTINT))
1311 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1312
1313 if (cm->pcm) {
1314 if ((status & CM_CHINT0) && cm->channel[0].running)
1315 snd_pcm_period_elapsed(cm->channel[0].substream);
1316 if ((status & CM_CHINT1) && cm->channel[1].running)
1317 snd_pcm_period_elapsed(cm->channel[1].substream);
1318 }
1319 return IRQ_HANDLED;
1320}
1321
1322/*
1323 * h/w infos
1324 */
1325
1326/* playback on channel A */
1327static snd_pcm_hardware_t snd_cmipci_playback =
1328{
1329 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1330 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1331 SNDRV_PCM_INFO_MMAP_VALID),
1332 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1333 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1334 .rate_min = 5512,
1335 .rate_max = 48000,
1336 .channels_min = 1,
1337 .channels_max = 2,
1338 .buffer_bytes_max = (128*1024),
1339 .period_bytes_min = 64,
1340 .period_bytes_max = (128*1024),
1341 .periods_min = 2,
1342 .periods_max = 1024,
1343 .fifo_size = 0,
1344};
1345
1346/* capture on channel B */
1347static snd_pcm_hardware_t snd_cmipci_capture =
1348{
1349 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1350 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1351 SNDRV_PCM_INFO_MMAP_VALID),
1352 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1353 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1354 .rate_min = 5512,
1355 .rate_max = 48000,
1356 .channels_min = 1,
1357 .channels_max = 2,
1358 .buffer_bytes_max = (128*1024),
1359 .period_bytes_min = 64,
1360 .period_bytes_max = (128*1024),
1361 .periods_min = 2,
1362 .periods_max = 1024,
1363 .fifo_size = 0,
1364};
1365
1366/* playback on channel B - stereo 16bit only? */
1367static snd_pcm_hardware_t snd_cmipci_playback2 =
1368{
1369 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1370 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1371 SNDRV_PCM_INFO_MMAP_VALID),
1372 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1373 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1374 .rate_min = 5512,
1375 .rate_max = 48000,
1376 .channels_min = 2,
1377 .channels_max = 2,
1378 .buffer_bytes_max = (128*1024),
1379 .period_bytes_min = 64,
1380 .period_bytes_max = (128*1024),
1381 .periods_min = 2,
1382 .periods_max = 1024,
1383 .fifo_size = 0,
1384};
1385
1386/* spdif playback on channel A */
1387static snd_pcm_hardware_t snd_cmipci_playback_spdif =
1388{
1389 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1390 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1391 SNDRV_PCM_INFO_MMAP_VALID),
1392 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1393 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1394 .rate_min = 44100,
1395 .rate_max = 48000,
1396 .channels_min = 2,
1397 .channels_max = 2,
1398 .buffer_bytes_max = (128*1024),
1399 .period_bytes_min = 64,
1400 .period_bytes_max = (128*1024),
1401 .periods_min = 2,
1402 .periods_max = 1024,
1403 .fifo_size = 0,
1404};
1405
1406/* spdif playback on channel A (32bit, IEC958 subframes) */
1407static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe =
1408{
1409 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1410 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1411 SNDRV_PCM_INFO_MMAP_VALID),
1412 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1413 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1414 .rate_min = 44100,
1415 .rate_max = 48000,
1416 .channels_min = 2,
1417 .channels_max = 2,
1418 .buffer_bytes_max = (128*1024),
1419 .period_bytes_min = 64,
1420 .period_bytes_max = (128*1024),
1421 .periods_min = 2,
1422 .periods_max = 1024,
1423 .fifo_size = 0,
1424};
1425
1426/* spdif capture on channel B */
1427static snd_pcm_hardware_t snd_cmipci_capture_spdif =
1428{
1429 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1430 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1431 SNDRV_PCM_INFO_MMAP_VALID),
1432 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1433 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1434 .rate_min = 44100,
1435 .rate_max = 48000,
1436 .channels_min = 2,
1437 .channels_max = 2,
1438 .buffer_bytes_max = (128*1024),
1439 .period_bytes_min = 64,
1440 .period_bytes_max = (128*1024),
1441 .periods_min = 2,
1442 .periods_max = 1024,
1443 .fifo_size = 0,
1444};
1445
1446/*
1447 * check device open/close
1448 */
1449static int open_device_check(cmipci_t *cm, int mode, snd_pcm_substream_t *subs)
1450{
1451 int ch = mode & CM_OPEN_CH_MASK;
1452
1453 /* FIXME: a file should wait until the device becomes free
1454 * when it's opened on blocking mode. however, since the current
1455 * pcm framework doesn't pass file pointer before actually opened,
1456 * we can't know whether blocking mode or not in open callback..
1457 */
1458 down(&cm->open_mutex);
1459 if (cm->opened[ch]) {
1460 up(&cm->open_mutex);
1461 return -EBUSY;
1462 }
1463 cm->opened[ch] = mode;
1464 cm->channel[ch].substream = subs;
1465 if (! (mode & CM_OPEN_DAC)) {
1466 /* disable dual DAC mode */
1467 cm->channel[ch].is_dac = 0;
1468 spin_lock_irq(&cm->reg_lock);
1469 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1470 spin_unlock_irq(&cm->reg_lock);
1471 }
1472 up(&cm->open_mutex);
1473 return 0;
1474}
1475
1476static void close_device_check(cmipci_t *cm, int mode)
1477{
1478 int ch = mode & CM_OPEN_CH_MASK;
1479
1480 down(&cm->open_mutex);
1481 if (cm->opened[ch] == mode) {
1482 if (cm->channel[ch].substream) {
1483 snd_cmipci_ch_reset(cm, ch);
1484 cm->channel[ch].running = 0;
1485 cm->channel[ch].substream = NULL;
1486 }
1487 cm->opened[ch] = 0;
1488 if (! cm->channel[ch].is_dac) {
1489 /* enable dual DAC mode again */
1490 cm->channel[ch].is_dac = 1;
1491 spin_lock_irq(&cm->reg_lock);
1492 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1493 spin_unlock_irq(&cm->reg_lock);
1494 }
1495 }
1496 up(&cm->open_mutex);
1497}
1498
1499/*
1500 */
1501
1502static int snd_cmipci_playback_open(snd_pcm_substream_t *substream)
1503{
1504 cmipci_t *cm = snd_pcm_substream_chip(substream);
1505 snd_pcm_runtime_t *runtime = substream->runtime;
1506 int err;
1507
1508 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1509 return err;
1510 runtime->hw = snd_cmipci_playback;
1511 runtime->hw.channels_max = cm->max_channels;
1512 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1513 cm->dig_pcm_status = cm->dig_status;
1514 return 0;
1515}
1516
1517static int snd_cmipci_capture_open(snd_pcm_substream_t *substream)
1518{
1519 cmipci_t *cm = snd_pcm_substream_chip(substream);
1520 snd_pcm_runtime_t *runtime = substream->runtime;
1521 int err;
1522
1523 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1524 return err;
1525 runtime->hw = snd_cmipci_capture;
1526 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1527 runtime->hw.rate_min = 41000;
1528 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1529 }
1530 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1531 return 0;
1532}
1533
1534static int snd_cmipci_playback2_open(snd_pcm_substream_t *substream)
1535{
1536 cmipci_t *cm = snd_pcm_substream_chip(substream);
1537 snd_pcm_runtime_t *runtime = substream->runtime;
1538 int err;
1539
1540 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1541 return err;
1542 runtime->hw = snd_cmipci_playback2;
1543 down(&cm->open_mutex);
1544 if (! cm->opened[CM_CH_PLAY]) {
1545 if (cm->can_multi_ch) {
1546 runtime->hw.channels_max = cm->max_channels;
1547 if (cm->max_channels == 4)
1548 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1549 else if (cm->max_channels == 6)
1550 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1551 else if (cm->max_channels == 8)
1552 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1553 }
1554 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1555 }
1556 up(&cm->open_mutex);
1557 return 0;
1558}
1559
1560static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t *substream)
1561{
1562 cmipci_t *cm = snd_pcm_substream_chip(substream);
1563 snd_pcm_runtime_t *runtime = substream->runtime;
1564 int err;
1565
1566 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1567 return err;
1568 if (cm->can_ac3_hw) {
1569 runtime->hw = snd_cmipci_playback_spdif;
1570 if (cm->chip_version >= 37)
1571 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1572 } else {
1573 runtime->hw = snd_cmipci_playback_iec958_subframe;
1574 }
1575 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1576 cm->dig_pcm_status = cm->dig_status;
1577 return 0;
1578}
1579
1580static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t * substream)
1581{
1582 cmipci_t *cm = snd_pcm_substream_chip(substream);
1583 snd_pcm_runtime_t *runtime = substream->runtime;
1584 int err;
1585
1586 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1587 return err;
1588 runtime->hw = snd_cmipci_capture_spdif;
1589 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1590 return 0;
1591}
1592
1593
1594/*
1595 */
1596
1597static int snd_cmipci_playback_close(snd_pcm_substream_t * substream)
1598{
1599 cmipci_t *cm = snd_pcm_substream_chip(substream);
1600 close_device_check(cm, CM_OPEN_PLAYBACK);
1601 return 0;
1602}
1603
1604static int snd_cmipci_capture_close(snd_pcm_substream_t * substream)
1605{
1606 cmipci_t *cm = snd_pcm_substream_chip(substream);
1607 close_device_check(cm, CM_OPEN_CAPTURE);
1608 return 0;
1609}
1610
1611static int snd_cmipci_playback2_close(snd_pcm_substream_t * substream)
1612{
1613 cmipci_t *cm = snd_pcm_substream_chip(substream);
1614 close_device_check(cm, CM_OPEN_PLAYBACK2);
1615 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1616 return 0;
1617}
1618
1619static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t * substream)
1620{
1621 cmipci_t *cm = snd_pcm_substream_chip(substream);
1622 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1623 return 0;
1624}
1625
1626static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t * substream)
1627{
1628 cmipci_t *cm = snd_pcm_substream_chip(substream);
1629 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1630 return 0;
1631}
1632
1633
1634/*
1635 */
1636
1637static snd_pcm_ops_t snd_cmipci_playback_ops = {
1638 .open = snd_cmipci_playback_open,
1639 .close = snd_cmipci_playback_close,
1640 .ioctl = snd_pcm_lib_ioctl,
1641 .hw_params = snd_cmipci_hw_params,
1642 .hw_free = snd_cmipci_playback_hw_free,
1643 .prepare = snd_cmipci_playback_prepare,
1644 .trigger = snd_cmipci_playback_trigger,
1645 .pointer = snd_cmipci_playback_pointer,
1646};
1647
1648static snd_pcm_ops_t snd_cmipci_capture_ops = {
1649 .open = snd_cmipci_capture_open,
1650 .close = snd_cmipci_capture_close,
1651 .ioctl = snd_pcm_lib_ioctl,
1652 .hw_params = snd_cmipci_hw_params,
1653 .hw_free = snd_cmipci_hw_free,
1654 .prepare = snd_cmipci_capture_prepare,
1655 .trigger = snd_cmipci_capture_trigger,
1656 .pointer = snd_cmipci_capture_pointer,
1657};
1658
1659static snd_pcm_ops_t snd_cmipci_playback2_ops = {
1660 .open = snd_cmipci_playback2_open,
1661 .close = snd_cmipci_playback2_close,
1662 .ioctl = snd_pcm_lib_ioctl,
1663 .hw_params = snd_cmipci_playback2_hw_params,
1664 .hw_free = snd_cmipci_hw_free,
1665 .prepare = snd_cmipci_capture_prepare, /* channel B */
1666 .trigger = snd_cmipci_capture_trigger, /* channel B */
1667 .pointer = snd_cmipci_capture_pointer, /* channel B */
1668};
1669
1670static snd_pcm_ops_t snd_cmipci_playback_spdif_ops = {
1671 .open = snd_cmipci_playback_spdif_open,
1672 .close = snd_cmipci_playback_spdif_close,
1673 .ioctl = snd_pcm_lib_ioctl,
1674 .hw_params = snd_cmipci_hw_params,
1675 .hw_free = snd_cmipci_playback_hw_free,
1676 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1677 .trigger = snd_cmipci_playback_trigger,
1678 .pointer = snd_cmipci_playback_pointer,
1679};
1680
1681static snd_pcm_ops_t snd_cmipci_capture_spdif_ops = {
1682 .open = snd_cmipci_capture_spdif_open,
1683 .close = snd_cmipci_capture_spdif_close,
1684 .ioctl = snd_pcm_lib_ioctl,
1685 .hw_params = snd_cmipci_hw_params,
1686 .hw_free = snd_cmipci_capture_spdif_hw_free,
1687 .prepare = snd_cmipci_capture_spdif_prepare,
1688 .trigger = snd_cmipci_capture_trigger,
1689 .pointer = snd_cmipci_capture_pointer,
1690};
1691
1692
1693/*
1694 */
1695
1da177e4
LT		 1696static int __devinit snd_cmipci_pcm_new(cmipci_t *cm, int device)
1697{
1698 snd_pcm_t *pcm;
1699 int err;
1700
1701 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1702 if (err < 0)
1703 return err;
1704
1705 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1706 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1707
1708 pcm->private_data = cm;
1da177e4
LT		 1709 pcm->info_flags = 0;
1710 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1711 cm->pcm = pcm;
1712
1713 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1714 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1715
1716 return 0;
1717}
1718
1719static int __devinit snd_cmipci_pcm2_new(cmipci_t *cm, int device)
1720{
1721 snd_pcm_t *pcm;
1722 int err;
1723
1724 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1725 if (err < 0)
1726 return err;
1727
1728 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1729
1730 pcm->private_data = cm;
1da177e4
LT		 1731 pcm->info_flags = 0;
1732 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1733 cm->pcm2 = pcm;
1734
1735 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1736 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1737
1738 return 0;
1739}
1740
1741static int __devinit snd_cmipci_pcm_spdif_new(cmipci_t *cm, int device)
1742{
1743 snd_pcm_t *pcm;
1744 int err;
1745
1746 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1747 if (err < 0)
1748 return err;
1749
1750 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1751 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1752
1753 pcm->private_data = cm;
1da177e4
LT		 1754 pcm->info_flags = 0;
1755 strcpy(pcm->name, "C-Media PCI IEC958");
1756 cm->pcm_spdif = pcm;
1757
1758 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1759 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1760
1761 return 0;
1762}
1763
1764/*
1765 * mixer interface:
1766 * - CM8338/8738 has a compatible mixer interface with SB16, but
1767 * lack of some elements like tone control, i/o gain and AGC.
1768 * - Access to native registers:
1769 * - A 3D switch
1770 * - Output mute switches
1771 */
1772
1773static void snd_cmipci_mixer_write(cmipci_t *s, unsigned char idx, unsigned char data)
1774{
1775 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1776 outb(data, s->iobase + CM_REG_SB16_DATA);
1777}
1778
1779static unsigned char snd_cmipci_mixer_read(cmipci_t *s, unsigned char idx)
1780{
1781 unsigned char v;
1782
1783 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1784 v = inb(s->iobase + CM_REG_SB16_DATA);
1785 return v;
1786}
1787
1788/*
1789 * general mixer element
1790 */
1791typedef struct cmipci_sb_reg {
1792 unsigned int left_reg, right_reg;
1793 unsigned int left_shift, right_shift;
1794 unsigned int mask;
1795 unsigned int invert: 1;
1796 unsigned int stereo: 1;
1797} cmipci_sb_reg_t;
1798
1799#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1800 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1801
1802#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1803{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1804 .info = snd_cmipci_info_volume, \
1805 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1806 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1807}
1808
1809#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1810#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1811#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1812#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1813
1814static void cmipci_sb_reg_decode(cmipci_sb_reg_t *r, unsigned long val)
1815{
1816 r->left_reg = val & 0xff;
1817 r->right_reg = (val >> 8) & 0xff;
1818 r->left_shift = (val >> 16) & 0x07;
1819 r->right_shift = (val >> 19) & 0x07;
1820 r->invert = (val >> 22) & 1;
1821 r->stereo = (val >> 23) & 1;
1822 r->mask = (val >> 24) & 0xff;
1823}
1824
1825static int snd_cmipci_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1826{
1827 cmipci_sb_reg_t reg;
1828
1829 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1830 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1831 uinfo->count = reg.stereo + 1;
1832 uinfo->value.integer.min = 0;
1833 uinfo->value.integer.max = reg.mask;
1834 return 0;
1835}
1836
1837static int snd_cmipci_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1838{
1839 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1840 cmipci_sb_reg_t reg;
1841 int val;
1842
1843 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1844 spin_lock_irq(&cm->reg_lock);
1845 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1846 if (reg.invert)
1847 val = reg.mask - val;
1848 ucontrol->value.integer.value[0] = val;
1849 if (reg.stereo) {
1850 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1851 if (reg.invert)
1852 val = reg.mask - val;
1853 ucontrol->value.integer.value[1] = val;
1854 }
1855 spin_unlock_irq(&cm->reg_lock);
1856 return 0;
1857}
1858
1859static int snd_cmipci_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1860{
1861 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1862 cmipci_sb_reg_t reg;
1863 int change;
1864 int left, right, oleft, oright;
1865
1866 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1867 left = ucontrol->value.integer.value[0] & reg.mask;
1868 if (reg.invert)
1869 left = reg.mask - left;
1870 left <<= reg.left_shift;
1871 if (reg.stereo) {
1872 right = ucontrol->value.integer.value[1] & reg.mask;
1873 if (reg.invert)
1874 right = reg.mask - right;
1875 right <<= reg.right_shift;
1876 } else
1877 right = 0;
1878 spin_lock_irq(&cm->reg_lock);
1879 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1880 left |= oleft & ~(reg.mask << reg.left_shift);
1881 change = left != oleft;
1882 if (reg.stereo) {
1883 if (reg.left_reg != reg.right_reg) {
1884 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1885 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1886 } else
1887 oright = left;
1888 right |= oright & ~(reg.mask << reg.right_shift);
1889 change |= right != oright;
1890 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1891 } else
1892 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1893 spin_unlock_irq(&cm->reg_lock);
1894 return change;
1895}
1896
1897/*
1898 * input route (left,right) -> (left,right)
1899 */
1900#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1901{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1902 .info = snd_cmipci_info_input_sw, \
1903 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1904 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1905}
1906
1907static int snd_cmipci_info_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1908{
1909 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1910 uinfo->count = 4;
1911 uinfo->value.integer.min = 0;
1912 uinfo->value.integer.max = 1;
1913 return 0;
1914}
1915
1916static int snd_cmipci_get_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1917{
1918 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1919 cmipci_sb_reg_t reg;
1920 int val1, val2;
1921
1922 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1923 spin_lock_irq(&cm->reg_lock);
1924 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1925 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1926 spin_unlock_irq(&cm->reg_lock);
1927 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1928 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1929 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1930 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1931 return 0;
1932}
1933
1934static int snd_cmipci_put_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1935{
1936 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1937 cmipci_sb_reg_t reg;
1938 int change;
1939 int val1, val2, oval1, oval2;
1940
1941 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1942 spin_lock_irq(&cm->reg_lock);
1943 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1944 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1945 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1946 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1947 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1948 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1949 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1950 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1951 change = val1 != oval1 || val2 != oval2;
1952 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1953 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1954 spin_unlock_irq(&cm->reg_lock);
1955 return change;
1956}
1957
1958/*
1959 * native mixer switches/volumes
1960 */
1961
1962#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1963{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1964 .info = snd_cmipci_info_native_mixer, \
1965 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1966 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
1967}
1968
1969#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
1970{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1971 .info = snd_cmipci_info_native_mixer, \
1972 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1973 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
1974}
1975
1976#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
1977{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1978 .info = snd_cmipci_info_native_mixer, \
1979 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1980 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
1981}
1982
1983#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
1984{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1985 .info = snd_cmipci_info_native_mixer, \
1986 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1987 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
1988}
1989
1990static int snd_cmipci_info_native_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1991{
1992 cmipci_sb_reg_t reg;
1993
1994 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1995 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1996 uinfo->count = reg.stereo + 1;
1997 uinfo->value.integer.min = 0;
1998 uinfo->value.integer.max = reg.mask;
1999 return 0;
2000
2001}
2002
2003static int snd_cmipci_get_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2004{
2005 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2006 cmipci_sb_reg_t reg;
2007 unsigned char oreg, val;
2008
2009 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2010 spin_lock_irq(&cm->reg_lock);
2011 oreg = inb(cm->iobase + reg.left_reg);
2012 val = (oreg >> reg.left_shift) & reg.mask;
2013 if (reg.invert)
2014 val = reg.mask - val;
2015 ucontrol->value.integer.value[0] = val;
2016 if (reg.stereo) {
2017 val = (oreg >> reg.right_shift) & reg.mask;
2018 if (reg.invert)
2019 val = reg.mask - val;
2020 ucontrol->value.integer.value[1] = val;
2021 }
2022 spin_unlock_irq(&cm->reg_lock);
2023 return 0;
2024}
2025
2026static int snd_cmipci_put_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2027{
2028 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2029 cmipci_sb_reg_t reg;
2030 unsigned char oreg, nreg, val;
2031
2032 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2033 spin_lock_irq(&cm->reg_lock);
2034 oreg = inb(cm->iobase + reg.left_reg);
2035 val = ucontrol->value.integer.value[0] & reg.mask;
2036 if (reg.invert)
2037 val = reg.mask - val;
2038 nreg = oreg & ~(reg.mask << reg.left_shift);
2039 nreg |= (val << reg.left_shift);
2040 if (reg.stereo) {
2041 val = ucontrol->value.integer.value[1] & reg.mask;
2042 if (reg.invert)
2043 val = reg.mask - val;
2044 nreg &= ~(reg.mask << reg.right_shift);
2045 nreg |= (val << reg.right_shift);
2046 }
2047 outb(nreg, cm->iobase + reg.left_reg);
2048 spin_unlock_irq(&cm->reg_lock);
2049 return (nreg != oreg);
2050}
2051
2052/*
2053 * special case - check mixer sensitivity
2054 */
2055static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2056{
2057 //cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2058 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2059}
2060
2061static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2062{
2063 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2064 if (cm->mixer_insensitive) {
2065 /* ignored */
2066 return 0;
2067 }
2068 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2069}
2070
2071
2072static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = {
2073 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2074 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2075 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2076 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2077 { /* switch with sensitivity */
2078 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2079 .name = "PCM Playback Switch",
2080 .info = snd_cmipci_info_native_mixer,
2081 .get = snd_cmipci_get_native_mixer_sensitive,
2082 .put = snd_cmipci_put_native_mixer_sensitive,
2083 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2084 },
2085 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2086 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2087 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2088 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2089 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2090 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2091 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2092 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2093 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2094 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2095 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2096 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2097 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2098 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2099 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2100 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2101 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2eff7ec8 2102 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
1da177e4 2103 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2eff7ec8
TI		 2104 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2105 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2106 CMIPCI_DOUBLE("PC Speaker Playnack Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2107 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
1da177e4
LT		 2108};
2109
2110/*
2111 * other switches
2112 */
2113
2114typedef struct snd_cmipci_switch_args {
2115 int reg; /* register index */
2116 unsigned int mask; /* mask bits */
2117 unsigned int mask_on; /* mask bits to turn on */
2118 unsigned int is_byte: 1; /* byte access? */
2119 unsigned int ac3_sensitive: 1; /* access forbidden during non-audio operation? */
2120} snd_cmipci_switch_args_t;
2121
2122static int snd_cmipci_uswitch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2123{
2124 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2125 uinfo->count = 1;
2126 uinfo->value.integer.min = 0;
2127 uinfo->value.integer.max = 1;
2128 return 0;
2129}
2130
2131static int _snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2132{
2133 unsigned int val;
2134 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2135
2136 spin_lock_irq(&cm->reg_lock);
2137 if (args->ac3_sensitive && cm->mixer_insensitive) {
2138 ucontrol->value.integer.value[0] = 0;
2139 spin_unlock_irq(&cm->reg_lock);
2140 return 0;
2141 }
2142 if (args->is_byte)
2143 val = inb(cm->iobase + args->reg);
2144 else
2145 val = snd_cmipci_read(cm, args->reg);
2146 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2147 spin_unlock_irq(&cm->reg_lock);
2148 return 0;
2149}
2150
2151static int snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2152{
2153 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2154 snd_assert(args != NULL, return -EINVAL);
2155 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2156}
2157
2158static int _snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2159{
2160 unsigned int val;
2161 int change;
2162 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2163
2164 spin_lock_irq(&cm->reg_lock);
2165 if (args->ac3_sensitive && cm->mixer_insensitive) {
2166 /* ignored */
2167 spin_unlock_irq(&cm->reg_lock);
2168 return 0;
2169 }
2170 if (args->is_byte)
2171 val = inb(cm->iobase + args->reg);
2172 else
2173 val = snd_cmipci_read(cm, args->reg);
2174 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2175 if (change) {
2176 val &= ~args->mask;
2177 if (ucontrol->value.integer.value[0])
2178 val |= args->mask_on;
2179 else
2180 val |= (args->mask & ~args->mask_on);
2181 if (args->is_byte)
2182 outb((unsigned char)val, cm->iobase + args->reg);
2183 else
2184 snd_cmipci_write(cm, args->reg, val);
2185 }
2186 spin_unlock_irq(&cm->reg_lock);
2187 return change;
2188}
2189
2190static int snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2191{
2192 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2193 snd_assert(args != NULL, return -EINVAL);
2194 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2195}
2196
2197#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2198static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \
2199 .reg = xreg, \
2200 .mask = xmask, \
2201 .mask_on = xmask_on, \
2202 .is_byte = xis_byte, \
2203 .ac3_sensitive = xac3, \
2204}
2205
2206#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2207 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2208
2209#if 0 /* these will be controlled in pcm device */
2210DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2211DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2212#endif
2213DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2214DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2215DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2216DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2217DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2218DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2219DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2220DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2221// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2222DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2223DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2224/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2225DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2226DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2227#if CM_CH_PLAY == 1
2228DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2229#else
2230DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2231#endif
2232DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
01d25d46
TI		 2233// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2234// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
1da177e4
LT		 2235// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2236DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2237
2238#define DEFINE_SWITCH(sname, stype, sarg) \
2239{ .name = sname, \
2240 .iface = stype, \
2241 .info = snd_cmipci_uswitch_info, \
2242 .get = snd_cmipci_uswitch_get, \
2243 .put = snd_cmipci_uswitch_put, \
2244 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2245}
2246
2247#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2248#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2249
2250
2251/*
2252 * callbacks for spdif output switch
2253 * needs toggle two registers..
2254 */
2255static int snd_cmipci_spdout_enable_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2256{
2257 int changed;
2258 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2259 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2260 return changed;
2261}
2262
2263static int snd_cmipci_spdout_enable_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2264{
2265 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
2266 int changed;
2267 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2268 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2269 if (changed) {
2270 if (ucontrol->value.integer.value[0]) {
2271 if (chip->spdif_playback_avail)
2272 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2273 } else {
2274 if (chip->spdif_playback_avail)
2275 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2276 }
2277 }
2278 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2279 return changed;
2280}
2281
2282
01d25d46
TI		 2283static int snd_cmipci_line_in_mode_info(snd_kcontrol_t *kcontrol,
2284 snd_ctl_elem_info_t *uinfo)
2285{
2286 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2287 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2288 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2289 uinfo->count = 1;
2290 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2291 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2292 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2293 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2294 return 0;
2295}
2296
2297static inline unsigned int get_line_in_mode(cmipci_t *cm)
2298{
2299 unsigned int val;
2300 if (cm->chip_version >= 39) {
2301 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2302 if (val & CM_LINE_AS_BASS)
2303 return 2;
2304 }
2305 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2306 if (val & CM_SPK4)
2307 return 1;
2308 return 0;
2309}
2310
2311static int snd_cmipci_line_in_mode_get(snd_kcontrol_t *kcontrol,
2312 snd_ctl_elem_value_t *ucontrol)
2313{
2314 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2315
2316 spin_lock_irq(&cm->reg_lock);
2317 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2318 spin_unlock_irq(&cm->reg_lock);
2319 return 0;
2320}
2321
2322static int snd_cmipci_line_in_mode_put(snd_kcontrol_t *kcontrol,
2323 snd_ctl_elem_value_t *ucontrol)
2324{
2325 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2326 int change;
2327
2328 spin_lock_irq(&cm->reg_lock);
2329 if (ucontrol->value.enumerated.item[0] == 2)
2330 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2331 else
2332 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2333 if (ucontrol->value.enumerated.item[0] == 1)
2334 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2335 else
2336 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2337 spin_unlock_irq(&cm->reg_lock);
2338 return change;
2339}
2340
2341static int snd_cmipci_mic_in_mode_info(snd_kcontrol_t *kcontrol,
2342 snd_ctl_elem_info_t *uinfo)
2343{
2344 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2345 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2346 uinfo->count = 1;
2347 uinfo->value.enumerated.items = 2;
2348 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2349 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2350 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2351 return 0;
2352}
2353
2354static int snd_cmipci_mic_in_mode_get(snd_kcontrol_t *kcontrol,
2355 snd_ctl_elem_value_t *ucontrol)
2356{
2357 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2358 /* same bit as spdi_phase */
2359 spin_lock_irq(&cm->reg_lock);
2360 ucontrol->value.enumerated.item[0] =
2361 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2362 spin_unlock_irq(&cm->reg_lock);
2363 return 0;
2364}
2365
2366static int snd_cmipci_mic_in_mode_put(snd_kcontrol_t *kcontrol,
2367 snd_ctl_elem_value_t *ucontrol)
2368{
2369 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2370 int change;
2371
2372 spin_lock_irq(&cm->reg_lock);
2373 if (ucontrol->value.enumerated.item[0])
2374 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2375 else
2376 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2377 spin_unlock_irq(&cm->reg_lock);
2378 return change;
2379}
2380
1da177e4
LT		 2381/* both for CM8338/8738 */
2382static snd_kcontrol_new_t snd_cmipci_mixer_switches[] __devinitdata = {
2383 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
01d25d46
TI		 2384 {
2385 .name = "Line-In Mode",
2386 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2387 .info = snd_cmipci_line_in_mode_info,
2388 .get = snd_cmipci_line_in_mode_get,
2389 .put = snd_cmipci_line_in_mode_put,
2390 },
1da177e4
LT		 2391};
2392
2393/* for non-multichannel chips */
2394static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata =
2395DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2396
2397/* only for CM8738 */
2398static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches[] __devinitdata = {
2399#if 0 /* controlled in pcm device */
2400 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2401 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2402 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2403#endif
2404 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2405 { .name = "IEC958 Output Switch",
2406 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2407 .info = snd_cmipci_uswitch_info,
2408 .get = snd_cmipci_spdout_enable_get,
2409 .put = snd_cmipci_spdout_enable_put,
2410 },
2411 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2412 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2413 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2414// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2415 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2416 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2417};
2418
2419/* only for model 033/037 */
2420static snd_kcontrol_new_t snd_cmipci_old_mixer_switches[] __devinitdata = {
2421 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2422 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2423 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2424};
2425
2426/* only for model 039 or later */
2427static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches[] __devinitdata = {
1da177e4
LT		 2428 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2429 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
01d25d46
TI		 2430 {
2431 .name = "Mic-In Mode",
2432 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2433 .info = snd_cmipci_mic_in_mode_info,
2434 .get = snd_cmipci_mic_in_mode_get,
2435 .put = snd_cmipci_mic_in_mode_put,
2436 }
1da177e4
LT		 2437};
2438
2439/* card control switches */
2440static snd_kcontrol_new_t snd_cmipci_control_switches[] __devinitdata = {
2441 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2442 DEFINE_CARD_SWITCH("Modem", modem),
2443};
2444
2445
2446static int __devinit snd_cmipci_mixer_new(cmipci_t *cm, int pcm_spdif_device)
2447{
2448 snd_card_t *card;
2449 snd_kcontrol_new_t *sw;
2450 snd_kcontrol_t *kctl;
2451 unsigned int idx;
2452 int err;
2453
2454 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2455
2456 card = cm->card;
2457
2458 strcpy(card->mixername, "CMedia PCI");
2459
2460 spin_lock_irq(&cm->reg_lock);
2461 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2462 spin_unlock_irq(&cm->reg_lock);
2463
2464 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2465 if (cm->chip_version == 68) { // 8768 has no PCM volume
2466 if (!strcmp(snd_cmipci_mixers[idx].name,
2467 "PCM Playback Volume"))
2468 continue;
2469 }
2470 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2471 return err;
2472 }
2473
2474 /* mixer switches */
2475 sw = snd_cmipci_mixer_switches;
2476 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2477 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2478 if (err < 0)
2479 return err;
2480 }
2481 if (! cm->can_multi_ch) {
2482 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2483 if (err < 0)
2484 return err;
2485 }
2486 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2487 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2488 sw = snd_cmipci_8738_mixer_switches;
2489 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2490 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2491 if (err < 0)
2492 return err;
2493 }
2494 if (cm->can_ac3_hw) {
2495 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2496 return err;
2497 kctl->id.device = pcm_spdif_device;
2498 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2499 return err;
2500 kctl->id.device = pcm_spdif_device;
2501 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2502 return err;
2503 kctl->id.device = pcm_spdif_device;
2504 }
2505 if (cm->chip_version <= 37) {
2506 sw = snd_cmipci_old_mixer_switches;
2507 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2508 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2509 if (err < 0)
2510 return err;
2511 }
2512 }
2513 }
2514 if (cm->chip_version >= 39) {
2515 sw = snd_cmipci_extra_mixer_switches;
2516 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2517 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2518 if (err < 0)
2519 return err;
2520 }
2521 }
2522
2523 /* card switches */
2524 sw = snd_cmipci_control_switches;
2525 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2526 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2527 if (err < 0)
2528 return err;
2529 }
2530
2531 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2532 snd_ctl_elem_id_t id;
2533 snd_kcontrol_t *ctl;
2534 memset(&id, 0, sizeof(id));
2535 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2536 strcpy(id.name, cm_saved_mixer[idx].name);
2537 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2538 cm->mixer_res_ctl[idx] = ctl;
2539 }
2540
2541 return 0;
2542}
2543
2544
2545/*
2546 * proc interface
2547 */
2548
2549#ifdef CONFIG_PROC_FS
2550static void snd_cmipci_proc_read(snd_info_entry_t *entry,
2551 snd_info_buffer_t *buffer)
2552{
2553 cmipci_t *cm = entry->private_data;
2554 int i;
2555
2556 snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2557 for (i = 0; i < 0x40; i++) {
2558 int v = inb(cm->iobase + i);
2559 if (i % 4 == 0)
2560 snd_iprintf(buffer, "%02x: ", i);
2561 snd_iprintf(buffer, "%02x", v);
2562 if (i % 4 == 3)
2563 snd_iprintf(buffer, "\n");
2564 else
2565 snd_iprintf(buffer, " ");
2566 }
2567}
2568
2569static void __devinit snd_cmipci_proc_init(cmipci_t *cm)
2570{
2571 snd_info_entry_t *entry;
2572
2573 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2574 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2575}
2576#else /* !CONFIG_PROC_FS */
2577static inline void snd_cmipci_proc_init(cmipci_t *cm) {}
2578#endif
2579
2580
2581static struct pci_device_id snd_cmipci_ids[] = {
2582 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2583 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2584 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2585 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2586 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2587 {0,},
2588};
2589
2590
2591/*
2592 * check chip version and capabilities
2593 * driver name is modified according to the chip model
2594 */
2595static void __devinit query_chip(cmipci_t *cm)
2596{
2597 unsigned int detect;
2598
2599 /* check reg 0Ch, bit 24-31 */
2600 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2601 if (! detect) {
2602 /* check reg 08h, bit 24-28 */
2603 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2604 if (! detect) {
2605 cm->chip_version = 33;
2606 cm->max_channels = 2;
2607 if (cm->do_soft_ac3)
2608 cm->can_ac3_sw = 1;
2609 else
2610 cm->can_ac3_hw = 1;
2611 cm->has_dual_dac = 1;
2612 } else {
2613 cm->chip_version = 37;
2614 cm->max_channels = 2;
2615 cm->can_ac3_hw = 1;
2616 cm->has_dual_dac = 1;
2617 }
2618 } else {
2619 /* check reg 0Ch, bit 26 */
2620 if (detect & CM_CHIP_8768) {
2621 cm->chip_version = 68;
2622 cm->max_channels = 8;
2623 cm->can_ac3_hw = 1;
2624 cm->has_dual_dac = 1;
2625 cm->can_multi_ch = 1;
2626 } else if (detect & CM_CHIP_055) {
2627 cm->chip_version = 55;
2628 cm->max_channels = 6;
2629 cm->can_ac3_hw = 1;
2630 cm->has_dual_dac = 1;
2631 cm->can_multi_ch = 1;
2632 } else if (detect & CM_CHIP_039) {
2633 cm->chip_version = 39;
2634 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2635 cm->max_channels = 6;
2636 else
2637 cm->max_channels = 4;
2638 cm->can_ac3_hw = 1;
2639 cm->has_dual_dac = 1;
2640 cm->can_multi_ch = 1;
2641 } else {
2642 printk(KERN_ERR "chip %x version not supported\n", detect);
2643 }
2644 }
2645}
2646
2647#ifdef SUPPORT_JOYSTICK
2648static int __devinit snd_cmipci_create_gameport(cmipci_t *cm, int dev)
2649{
2650 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2651 struct gameport *gp;
2652 struct resource *r = NULL;
2653 int i, io_port = 0;
2654
2655 if (joystick_port[dev] == 0)
2656 return -ENODEV;
2657
2658 if (joystick_port[dev] == 1) { /* auto-detect */
2659 for (i = 0; ports[i]; i++) {
2660 io_port = ports[i];
2661 r = request_region(io_port, 1, "CMIPCI gameport");
2662 if (r)
2663 break;
2664 }
2665 } else {
2666 io_port = joystick_port[dev];
2667 r = request_region(io_port, 1, "CMIPCI gameport");
2668 }
2669
2670 if (!r) {
2671 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2672 return -EBUSY;
2673 }
2674
2675 cm->gameport = gp = gameport_allocate_port();
2676 if (!gp) {
2677 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
b1d5776d 2678 release_and_free_resource(r);
1da177e4
LT		 2679 return -ENOMEM;
2680 }
2681 gameport_set_name(gp, "C-Media Gameport");
2682 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2683 gameport_set_dev_parent(gp, &cm->pci->dev);
2684 gp->io = io_port;
2685 gameport_set_port_data(gp, r);
2686
2687 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2688
2689 gameport_register_port(cm->gameport);
2690
2691 return 0;
2692}
2693
2694static void snd_cmipci_free_gameport(cmipci_t *cm)
2695{
2696 if (cm->gameport) {
2697 struct resource *r = gameport_get_port_data(cm->gameport);
2698
2699 gameport_unregister_port(cm->gameport);
2700 cm->gameport = NULL;
2701
2702 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
b1d5776d 2703 release_and_free_resource(r);
1da177e4
LT		 2704 }
2705}
2706#else
2707static inline int snd_cmipci_create_gameport(cmipci_t *cm, int dev) { return -ENOSYS; }
2708static inline void snd_cmipci_free_gameport(cmipci_t *cm) { }
2709#endif
2710
2711static int snd_cmipci_free(cmipci_t *cm)
2712{
2713 if (cm->irq >= 0) {
2714 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2715 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2716 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2717 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2718 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2719 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2720 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2721
2722 /* reset mixer */
2723 snd_cmipci_mixer_write(cm, 0, 0);
2724
2725 synchronize_irq(cm->irq);
2726
2727 free_irq(cm->irq, (void *)cm);
2728 }
2729
2730 snd_cmipci_free_gameport(cm);
2731 pci_release_regions(cm->pci);
2732 pci_disable_device(cm->pci);
2733 kfree(cm);
2734 return 0;
2735}
2736
2737static int snd_cmipci_dev_free(snd_device_t *device)
2738{
2739 cmipci_t *cm = device->device_data;
2740 return snd_cmipci_free(cm);
2741}
2742
5747e540
CL		 2743static int __devinit snd_cmipci_create_fm(cmipci_t *cm, long fm_port)
2744{
2745 long iosynth;
2746 unsigned int val;
2747 opl3_t *opl3;
2748 int err;
2749
2750 /* first try FM regs in PCI port range */
2751 iosynth = cm->iobase + CM_REG_FM_PCI;
2752 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2753 OPL3_HW_OPL3, 1, &opl3);
2754 if (err < 0) {
2755 /* then try legacy ports */
2756 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2757 iosynth = fm_port;
2758 switch (iosynth) {
2759 case 0x3E8: val |= CM_FMSEL_3E8; break;
2760 case 0x3E0: val |= CM_FMSEL_3E0; break;
2761 case 0x3C8: val |= CM_FMSEL_3C8; break;
2762 case 0x388: val |= CM_FMSEL_388; break;
2763 default:
2764 return 0;
2765 }
2766 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2767 /* enable FM */
2768 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2769
2770 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2771 OPL3_HW_OPL3, 0, &opl3) < 0) {
2772 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2773 "skipping...\n", iosynth);
2774 /* disable FM */
2775 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL,
2776 val & ~CM_FMSEL_MASK);
2777 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2778 return 0;
2779 }
2780 }
2781 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2782 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2783 return err;
2784 }
2785 return 0;
2786}
2787
1da177e4
LT		 2788static int __devinit snd_cmipci_create(snd_card_t *card, struct pci_dev *pci,
2789 int dev, cmipci_t **rcmipci)
2790{
2791 cmipci_t *cm;
2792 int err;
2793 static snd_device_ops_t ops = {
2794 .dev_free = snd_cmipci_dev_free,
2795 };
2796 unsigned int val = 0;
5747e540
CL		 2797 long iomidi;
2798 int integrated_midi;
1da177e4
LT		 2799 int pcm_index, pcm_spdif_index;
2800 static struct pci_device_id intel_82437vx[] = {
2801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2802 { },
2803 };
2804
2805 *rcmipci = NULL;
2806
2807 if ((err = pci_enable_device(pci)) < 0)
2808 return err;
2809
e560d8d8 2810 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
1da177e4
LT		 2811 if (cm == NULL) {
2812 pci_disable_device(pci);
2813 return -ENOMEM;
2814 }
2815
2816 spin_lock_init(&cm->reg_lock);
2817 init_MUTEX(&cm->open_mutex);
2818 cm->device = pci->device;
2819 cm->card = card;
2820 cm->pci = pci;
2821 cm->irq = -1;
2822 cm->channel[0].ch = 0;
2823 cm->channel[1].ch = 1;
2824 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2825
2826 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2827 kfree(cm);
2828 pci_disable_device(pci);
2829 return err;
2830 }
2831 cm->iobase = pci_resource_start(pci, 0);
2832
2833 if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, (void *)cm)) {
99b359ba 2834 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2835 snd_cmipci_free(cm);
2836 return -EBUSY;
2837 }
2838 cm->irq = pci->irq;
2839
2840 pci_set_master(cm->pci);
2841
2842 /*
2843 * check chip version, max channels and capabilities
2844 */
2845
2846 cm->chip_version = 0;
2847 cm->max_channels = 2;
2848 cm->do_soft_ac3 = soft_ac3[dev];
2849
2850 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2851 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2852 query_chip(cm);
2853 /* added -MCx suffix for chip supporting multi-channels */
2854 if (cm->can_multi_ch)
2855 sprintf(cm->card->driver + strlen(cm->card->driver),
2856 "-MC%d", cm->max_channels);
2857 else if (cm->can_ac3_sw)
2858 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2859
2860 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2861 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2862
2863#if CM_CH_PLAY == 1
2864 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2865#else
2866 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2867#endif
2868
2869 /* initialize codec registers */
2870 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2871 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2872 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2873 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2874 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2875
2876 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2877 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2878#if CM_CH_PLAY == 1
2879 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2880#else
2881 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2882#endif
2883 /* Set Bus Master Request */
2884 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2885
2886 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2887 switch (pci->device) {
2888 case PCI_DEVICE_ID_CMEDIA_CM8738:
2889 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2890 if (!pci_dev_present(intel_82437vx))
2891 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2892 break;
2893 default:
2894 break;
2895 }
2896
2897 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2898 snd_cmipci_free(cm);
2899 return err;
2900 }
2901
5747e540
CL		 2902 integrated_midi = snd_cmipci_read_b(cm, CM_REG_MPU_PCI) != 0xff;
2903 if (integrated_midi)
2904 iomidi = cm->iobase + CM_REG_MPU_PCI;
2905 else {
2906 iomidi = mpu_port[dev];
2907 switch (iomidi) {
2908 case 0x320: val = CM_VMPU_320; break;
2909 case 0x310: val = CM_VMPU_310; break;
2910 case 0x300: val = CM_VMPU_300; break;
2911 case 0x330: val = CM_VMPU_330; break;
2912 default:
2913 iomidi = 0; break;
2914 }
2915 if (iomidi > 0) {
2916 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2917 /* enable UART */
2918 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
1da177e4
LT		 2919 }
2920 }
5747e540
CL		 2921
2922 if ((err = snd_cmipci_create_fm(cm, fm_port[dev])) < 0)
2923 return err;
1da177e4
LT		 2924
2925 /* reset mixer */
2926 snd_cmipci_mixer_write(cm, 0, 0);
2927
2928 snd_cmipci_proc_init(cm);
2929
2930 /* create pcm devices */
2931 pcm_index = pcm_spdif_index = 0;
2932 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2933 return err;
2934 pcm_index++;
2935 if (cm->has_dual_dac) {
2936 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2937 return err;
2938 pcm_index++;
2939 }
2940 if (cm->can_ac3_hw || cm->can_ac3_sw) {
2941 pcm_spdif_index = pcm_index;
2942 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2943 return err;
2944 }
2945
2946 /* create mixer interface & switches */
2947 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2948 return err;
2949
2950 if (iomidi > 0) {
2951 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
5747e540 2952 iomidi, integrated_midi,
1da177e4
LT		 2953 cm->irq, 0, &cm->rmidi)) < 0) {
2954 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2955 }
2956 }
2957
2958#ifdef USE_VAR48KRATE
2959 for (val = 0; val < ARRAY_SIZE(rates); val++)
2960 snd_cmipci_set_pll(cm, rates[val], val);
2961
2962 /*
2963 * (Re-)Enable external switch spdo_48k
2964 */
2965 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2966#endif /* USE_VAR48KRATE */
2967
2968 if (snd_cmipci_create_gameport(cm, dev) < 0)
2969 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2970
2971 snd_card_set_dev(card, &pci->dev);
2972
2973 *rcmipci = cm;
2974 return 0;
2975}
2976
2977/*
2978 */
2979
2980MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
2981
2982static int __devinit snd_cmipci_probe(struct pci_dev *pci,
2983 const struct pci_device_id *pci_id)
2984{
2985 static int dev;
2986 snd_card_t *card;
2987 cmipci_t *cm;
2988 int err;
2989
2990 if (dev >= SNDRV_CARDS)
2991 return -ENODEV;
2992 if (! enable[dev]) {
2993 dev++;
2994 return -ENOENT;
2995 }
2996
2997 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2998 if (card == NULL)
2999 return -ENOMEM;
3000
3001 switch (pci->device) {
3002 case PCI_DEVICE_ID_CMEDIA_CM8738:
3003 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3004 strcpy(card->driver, "CMI8738");
3005 break;
3006 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3007 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3008 strcpy(card->driver, "CMI8338");
3009 break;
3010 default:
3011 strcpy(card->driver, "CMIPCI");
3012 break;
3013 }
3014
3015 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3016 snd_card_free(card);
3017 return err;
3018 }
3019
3020 sprintf(card->shortname, "C-Media PCI %s", card->driver);
3021 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
3022 card->shortname,
3023 cm->chip_version,
3024 cm->iobase,
3025 cm->irq);
3026
3027 //snd_printd("%s is detected\n", card->longname);
3028
3029 if ((err = snd_card_register(card)) < 0) {
3030 snd_card_free(card);
3031 return err;
3032 }
3033 pci_set_drvdata(pci, card);
3034 dev++;
3035 return 0;
3036
3037}
3038
3039static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3040{
3041 snd_card_free(pci_get_drvdata(pci));
3042 pci_set_drvdata(pci, NULL);
3043}
3044
3045
3046static struct pci_driver driver = {
3047 .name = "C-Media PCI",
3048 .id_table = snd_cmipci_ids,
3049 .probe = snd_cmipci_probe,
3050 .remove = __devexit_p(snd_cmipci_remove),
3051};
3052
3053static int __init alsa_card_cmipci_init(void)
3054{
01d25d46 3055 return pci_register_driver(&driver);
1da177e4
LT		 3056}
3057
3058static void __exit alsa_card_cmipci_exit(void)
3059{
3060 pci_unregister_driver(&driver);
3061}
3062
3063module_init(alsa_card_cmipci_init)
3064module_exit(alsa_card_cmipci_exit)
Linux 6.x block layer and io_uring tree(s)