Commit | Line | Data |
---|---|---|
1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * Driver for C-Media CMI8338 and 8738 PCI soundcards. | |
4 | * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de> | |
1da177e4 LT |
5 | */ |
6 | ||
7 | /* Does not work. Warning may block system in capture mode */ | |
8 | /* #define USE_VAR48KRATE */ | |
9 | ||
6cbbfe1c | 10 | #include <linux/io.h> |
1da177e4 LT |
11 | #include <linux/delay.h> |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/gameport.h> | |
65a77217 | 17 | #include <linux/module.h> |
62932df8 | 18 | #include <linux/mutex.h> |
1da177e4 LT |
19 | #include <sound/core.h> |
20 | #include <sound/info.h> | |
21 | #include <sound/control.h> | |
22 | #include <sound/pcm.h> | |
23 | #include <sound/rawmidi.h> | |
24 | #include <sound/mpu401.h> | |
25 | #include <sound/opl3.h> | |
26 | #include <sound/sb.h> | |
27 | #include <sound/asoundef.h> | |
28 | #include <sound/initval.h> | |
29 | ||
30 | MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); | |
31 | MODULE_DESCRIPTION("C-Media CMI8x38 PCI"); | |
32 | MODULE_LICENSE("GPL"); | |
1da177e4 | 33 | |
b2fac073 | 34 | #if IS_REACHABLE(CONFIG_GAMEPORT) |
1da177e4 LT |
35 | #define SUPPORT_JOYSTICK 1 |
36 | #endif | |
37 | ||
38 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
39 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
a67ff6a5 | 40 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ |
d8cac620 | 41 | static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1}; |
2f24d159 | 42 | static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; |
a67ff6a5 | 43 | static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; |
1da177e4 LT |
44 | #ifdef SUPPORT_JOYSTICK |
45 | static int joystick_port[SNDRV_CARDS]; | |
46 | #endif | |
47 | ||
48 | module_param_array(index, int, NULL, 0444); | |
49 | MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard."); | |
50 | module_param_array(id, charp, NULL, 0444); | |
51 | MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard."); | |
52 | module_param_array(enable, bool, NULL, 0444); | |
53 | MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard."); | |
6192c41f | 54 | module_param_hw_array(mpu_port, long, ioport, NULL, 0444); |
1da177e4 | 55 | MODULE_PARM_DESC(mpu_port, "MPU-401 port."); |
6192c41f | 56 | module_param_hw_array(fm_port, long, ioport, NULL, 0444); |
1da177e4 LT |
57 | MODULE_PARM_DESC(fm_port, "FM port."); |
58 | module_param_array(soft_ac3, bool, NULL, 0444); | |
25985edc | 59 | MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only)."); |
1da177e4 | 60 | #ifdef SUPPORT_JOYSTICK |
6192c41f | 61 | module_param_hw_array(joystick_port, int, ioport, NULL, 0444); |
1da177e4 LT |
62 | MODULE_PARM_DESC(joystick_port, "Joystick port address."); |
63 | #endif | |
64 | ||
1da177e4 LT |
65 | /* |
66 | * CM8x38 registers definition | |
67 | */ | |
68 | ||
69 | #define CM_REG_FUNCTRL0 0x00 | |
70 | #define CM_RST_CH1 0x00080000 | |
71 | #define CM_RST_CH0 0x00040000 | |
72 | #define CM_CHEN1 0x00020000 /* ch1: enable */ | |
73 | #define CM_CHEN0 0x00010000 /* ch0: enable */ | |
74 | #define CM_PAUSE1 0x00000008 /* ch1: pause */ | |
75 | #define CM_PAUSE0 0x00000004 /* ch0: pause */ | |
76 | #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */ | |
77 | #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */ | |
78 | ||
79 | #define CM_REG_FUNCTRL1 0x04 | |
a839a33d CL |
80 | #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */ |
81 | #define CM_DSFC_SHIFT 13 | |
82 | #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */ | |
83 | #define CM_ASFC_SHIFT 10 | |
1da177e4 LT |
84 | #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ |
85 | #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ | |
a839a33d | 86 | #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */ |
1da177e4 LT |
87 | #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ |
88 | #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ | |
89 | #define CM_BREQ 0x00000010 /* bus master enabled */ | |
90 | #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ | |
a839a33d CL |
91 | #define CM_UART_EN 0x00000004 /* legacy UART */ |
92 | #define CM_JYSTK_EN 0x00000002 /* legacy joystick */ | |
93 | #define CM_ZVPORT 0x00000001 /* ZVPORT */ | |
1da177e4 LT |
94 | |
95 | #define CM_REG_CHFORMAT 0x08 | |
96 | ||
97 | #define CM_CHB3D5C 0x80000000 /* 5,6 channels */ | |
a839a33d | 98 | #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */ |
1da177e4 LT |
99 | #define CM_CHB3D 0x20000000 /* 4 channels */ |
100 | ||
101 | #define CM_CHIP_MASK1 0x1f000000 | |
102 | #define CM_CHIP_037 0x01000000 | |
a839a33d CL |
103 | #define CM_SETLAT48 0x00800000 /* set latency timer 48h */ |
104 | #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */ | |
105 | #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */ | |
1da177e4 | 106 | #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ |
a839a33d | 107 | #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ |
1da177e4 LT |
108 | #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ |
109 | /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ | |
110 | ||
111 | #define CM_ADCBITLEN_MASK 0x0000C000 | |
112 | #define CM_ADCBITLEN_16 0x00000000 | |
113 | #define CM_ADCBITLEN_15 0x00004000 | |
114 | #define CM_ADCBITLEN_14 0x00008000 | |
115 | #define CM_ADCBITLEN_13 0x0000C000 | |
116 | ||
a839a33d | 117 | #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */ |
1da177e4 LT |
118 | #define CM_ADCDACLEN_060 0x00000000 |
119 | #define CM_ADCDACLEN_066 0x00001000 | |
120 | #define CM_ADCDACLEN_130 0x00002000 | |
121 | #define CM_ADCDACLEN_280 0x00003000 | |
122 | ||
a839a33d CL |
123 | #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */ |
124 | #define CM_ADCDLEN_ORIGINAL 0x00000000 | |
125 | #define CM_ADCDLEN_EXTRA 0x00001000 | |
126 | #define CM_ADCDLEN_24K 0x00002000 | |
127 | #define CM_ADCDLEN_WEIGHT 0x00003000 | |
128 | ||
1da177e4 | 129 | #define CM_CH1_SRATE_176K 0x00000800 |
8992e18d | 130 | #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */ |
1da177e4 LT |
131 | #define CM_CH1_SRATE_88K 0x00000400 |
132 | #define CM_CH0_SRATE_176K 0x00000200 | |
8992e18d | 133 | #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */ |
1da177e4 | 134 | #define CM_CH0_SRATE_88K 0x00000100 |
755c48ab TB |
135 | #define CM_CH0_SRATE_128K 0x00000300 |
136 | #define CM_CH0_SRATE_MASK 0x00000300 | |
1da177e4 LT |
137 | |
138 | #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ | |
a839a33d CL |
139 | #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */ |
140 | #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */ | |
141 | #define CM_SPDLOCKED 0x00000010 | |
1da177e4 | 142 | |
a839a33d | 143 | #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */ |
1da177e4 | 144 | #define CM_CH1FMT_SHIFT 2 |
a839a33d | 145 | #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */ |
1da177e4 LT |
146 | #define CM_CH0FMT_SHIFT 0 |
147 | ||
148 | #define CM_REG_INT_HLDCLR 0x0C | |
149 | #define CM_CHIP_MASK2 0xff000000 | |
a839a33d CL |
150 | #define CM_CHIP_8768 0x20000000 |
151 | #define CM_CHIP_055 0x08000000 | |
1da177e4 LT |
152 | #define CM_CHIP_039 0x04000000 |
153 | #define CM_CHIP_039_6CH 0x01000000 | |
a839a33d | 154 | #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */ |
1da177e4 LT |
155 | #define CM_TDMA_INT_EN 0x00040000 |
156 | #define CM_CH1_INT_EN 0x00020000 | |
157 | #define CM_CH0_INT_EN 0x00010000 | |
1da177e4 LT |
158 | |
159 | #define CM_REG_INT_STATUS 0x10 | |
160 | #define CM_INTR 0x80000000 | |
161 | #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */ | |
162 | #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */ | |
163 | #define CM_UARTINT 0x00010000 | |
164 | #define CM_LTDMAINT 0x00008000 | |
165 | #define CM_HTDMAINT 0x00004000 | |
166 | #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */ | |
167 | #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */ | |
168 | #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */ | |
169 | #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */ | |
170 | #define CM_CH1BUSY 0x00000008 | |
171 | #define CM_CH0BUSY 0x00000004 | |
172 | #define CM_CHINT1 0x00000002 | |
173 | #define CM_CHINT0 0x00000001 | |
174 | ||
175 | #define CM_REG_LEGACY_CTRL 0x14 | |
a839a33d | 176 | #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */ |
1da177e4 LT |
177 | #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ |
178 | #define CM_VMPU_330 0x00000000 | |
179 | #define CM_VMPU_320 0x20000000 | |
180 | #define CM_VMPU_310 0x40000000 | |
181 | #define CM_VMPU_300 0x60000000 | |
a839a33d | 182 | #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */ |
1da177e4 LT |
183 | #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ |
184 | #define CM_VSBSEL_220 0x00000000 | |
185 | #define CM_VSBSEL_240 0x04000000 | |
186 | #define CM_VSBSEL_260 0x08000000 | |
187 | #define CM_VSBSEL_280 0x0C000000 | |
188 | #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */ | |
189 | #define CM_FMSEL_388 0x00000000 | |
190 | #define CM_FMSEL_3C8 0x01000000 | |
191 | #define CM_FMSEL_3E0 0x02000000 | |
192 | #define CM_FMSEL_3E8 0x03000000 | |
a839a33d CL |
193 | #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */ |
194 | #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */ | |
1da177e4 | 195 | #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ |
a839a33d CL |
196 | #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */ |
197 | #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ | |
198 | #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */ | |
199 | #define CM_C_EECS 0x00040000 | |
200 | #define CM_C_EEDI46 0x00020000 | |
201 | #define CM_C_EECK46 0x00010000 | |
1da177e4 | 202 | #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ |
a839a33d CL |
203 | #define CM_CENTR2LIN 0x00004000 /* line-in as center out */ |
204 | #define CM_BASE2LIN 0x00002000 /* line-in as bass out */ | |
205 | #define CM_EXBASEN 0x00001000 /* external bass input enable */ | |
1da177e4 LT |
206 | |
207 | #define CM_REG_MISC_CTRL 0x18 | |
a839a33d | 208 | #define CM_PWD 0x80000000 /* power down */ |
1da177e4 | 209 | #define CM_RESET 0x40000000 |
a839a33d CL |
210 | #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */ |
211 | #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */ | |
212 | #define CM_TXVX 0x08000000 /* model 037? */ | |
213 | #define CM_N4SPK3D 0x04000000 /* copy front to rear */ | |
1da177e4 LT |
214 | #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ |
215 | #define CM_SPDIF48K 0x01000000 /* write */ | |
216 | #define CM_SPATUS48K 0x01000000 /* read */ | |
a839a33d | 217 | #define CM_ENDBDAC 0x00800000 /* enable double dac */ |
1da177e4 LT |
218 | #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ |
219 | #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ | |
a839a33d CL |
220 | #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */ |
221 | #define CM_FM_EN 0x00080000 /* enable legacy FM */ | |
1da177e4 | 222 | #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ |
a839a33d CL |
223 | #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */ |
224 | #define CM_VIDWPDSB 0x00010000 /* model 037? */ | |
1da177e4 | 225 | #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ |
a839a33d CL |
226 | #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */ |
227 | #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */ | |
228 | #define CM_VIDWPPRT 0x00002000 /* model 037? */ | |
229 | #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */ | |
230 | #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */ | |
1da177e4 LT |
231 | #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ |
232 | #define CM_ENCENTER 0x00000080 | |
56c36ca3 | 233 | #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */ |
a839a33d | 234 | #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */ |
56c36ca3 | 235 | #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */ |
a839a33d CL |
236 | #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */ |
237 | #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */ | |
238 | #define CM_UPDDMA_2048 0x00000000 | |
239 | #define CM_UPDDMA_1024 0x00000004 | |
240 | #define CM_UPDDMA_512 0x00000008 | |
241 | #define CM_UPDDMA_256 0x0000000C | |
242 | #define CM_TWAIT_MASK 0x00000003 /* model 037 */ | |
243 | #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */ | |
244 | #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */ | |
245 | ||
246 | #define CM_REG_TDMA_POSITION 0x1C | |
247 | #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */ | |
248 | #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */ | |
1da177e4 LT |
249 | |
250 | /* byte */ | |
251 | #define CM_REG_MIXER0 0x20 | |
a839a33d CL |
252 | #define CM_REG_SBVR 0x20 /* write: sb16 version */ |
253 | #define CM_REG_DEV 0x20 /* read: hardware device version */ | |
254 | ||
255 | #define CM_REG_MIXER21 0x21 | |
256 | #define CM_UNKNOWN_21_MASK 0x78 /* ? */ | |
257 | #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */ | |
258 | #define CM_PROINV 0x02 /* SBPro left/right channel switching */ | |
259 | #define CM_X_SB16 0x01 /* SB16 compatible */ | |
1da177e4 LT |
260 | |
261 | #define CM_REG_SB16_DATA 0x22 | |
262 | #define CM_REG_SB16_ADDR 0x23 | |
263 | ||
264 | #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */ | |
265 | #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */ | |
266 | #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */ | |
267 | #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */ | |
268 | ||
269 | #define CM_REG_MIXER1 0x24 | |
270 | #define CM_FMMUTE 0x80 /* mute FM */ | |
271 | #define CM_FMMUTE_SHIFT 7 | |
272 | #define CM_WSMUTE 0x40 /* mute PCM */ | |
273 | #define CM_WSMUTE_SHIFT 6 | |
a839a33d CL |
274 | #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */ |
275 | #define CM_REAR2LIN_SHIFT 5 | |
1da177e4 LT |
276 | #define CM_REAR2FRONT 0x10 /* exchange rear/front */ |
277 | #define CM_REAR2FRONT_SHIFT 4 | |
278 | #define CM_WAVEINL 0x08 /* digital wave rec. left chan */ | |
279 | #define CM_WAVEINL_SHIFT 3 | |
280 | #define CM_WAVEINR 0x04 /* digical wave rec. right */ | |
281 | #define CM_WAVEINR_SHIFT 2 | |
282 | #define CM_X3DEN 0x02 /* 3D surround enable */ | |
283 | #define CM_X3DEN_SHIFT 1 | |
284 | #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */ | |
285 | #define CM_CDPLAY_SHIFT 0 | |
286 | ||
287 | #define CM_REG_MIXER2 0x25 | |
288 | #define CM_RAUXREN 0x80 /* AUX right capture */ | |
289 | #define CM_RAUXREN_SHIFT 7 | |
290 | #define CM_RAUXLEN 0x40 /* AUX left capture */ | |
291 | #define CM_RAUXLEN_SHIFT 6 | |
292 | #define CM_VAUXRM 0x20 /* AUX right mute */ | |
293 | #define CM_VAUXRM_SHIFT 5 | |
294 | #define CM_VAUXLM 0x10 /* AUX left mute */ | |
295 | #define CM_VAUXLM_SHIFT 4 | |
296 | #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */ | |
297 | #define CM_VADMIC_SHIFT 1 | |
298 | #define CM_MICGAINZ 0x01 /* mic boost */ | |
299 | #define CM_MICGAINZ_SHIFT 0 | |
300 | ||
301 | #define CM_REG_AUX_VOL 0x26 | |
302 | #define CM_VAUXL_MASK 0xf0 | |
303 | #define CM_VAUXR_MASK 0x0f | |
304 | ||
305 | #define CM_REG_MISC 0x27 | |
a839a33d | 306 | #define CM_UNKNOWN_27_MASK 0xd8 /* ? */ |
1da177e4 LT |
307 | #define CM_XGPO1 0x20 |
308 | // #define CM_XGPBIO 0x04 | |
309 | #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */ | |
310 | #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ | |
311 | #define CM_SPDVALID 0x02 /* spdif input valid check */ | |
a839a33d | 312 | #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */ |
1da177e4 LT |
313 | |
314 | #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ | |
315 | /* | |
316 | * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738 | |
317 | * or identical with AC97 codec? | |
318 | */ | |
319 | #define CM_REG_EXTERN_CODEC CM_REG_AC97 | |
320 | ||
321 | /* | |
322 | * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6) | |
323 | */ | |
324 | #define CM_REG_MPU_PCI 0x40 | |
325 | ||
326 | /* | |
327 | * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6) | |
328 | */ | |
329 | #define CM_REG_FM_PCI 0x50 | |
330 | ||
331 | /* | |
2eff7ec8 | 332 | * access from SB-mixer port |
1da177e4 LT |
333 | */ |
334 | #define CM_REG_EXTENT_IND 0xf0 | |
335 | #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */ | |
336 | #define CM_VPHONE_SHIFT 5 | |
337 | #define CM_VPHOM 0x10 /* Phone mute control */ | |
338 | #define CM_VSPKM 0x08 /* Speaker mute control, default high */ | |
339 | #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ | |
340 | #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ | |
2eff7ec8 | 341 | #define CM_VADMIC3 0x01 /* Mic record boost */ |
1da177e4 LT |
342 | |
343 | /* | |
344 | * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738): | |
345 | * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL | |
346 | * unit (readonly?). | |
347 | */ | |
348 | #define CM_REG_PLL 0xf8 | |
349 | ||
350 | /* | |
351 | * extended registers | |
352 | */ | |
a839a33d CL |
353 | #define CM_REG_CH0_FRAME1 0x80 /* write: base address */ |
354 | #define CM_REG_CH0_FRAME2 0x84 /* read: current address */ | |
1da177e4 LT |
355 | #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ |
356 | #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ | |
a839a33d | 357 | |
cb60e5f5 | 358 | #define CM_REG_EXT_MISC 0x90 |
a839a33d CL |
359 | #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */ |
360 | #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */ | |
361 | #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */ | |
362 | #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */ | |
363 | #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */ | |
364 | #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */ | |
365 | #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */ | |
366 | #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */ | |
1da177e4 LT |
367 | |
368 | /* | |
369 | * size of i/o region | |
370 | */ | |
371 | #define CM_EXTENT_CODEC 0x100 | |
372 | #define CM_EXTENT_MIDI 0x2 | |
373 | #define CM_EXTENT_SYNTH 0x4 | |
374 | ||
375 | ||
1da177e4 LT |
376 | /* |
377 | * channels for playback / capture | |
378 | */ | |
379 | #define CM_CH_PLAY 0 | |
380 | #define CM_CH_CAPT 1 | |
381 | ||
382 | /* | |
383 | * flags to check device open/close | |
384 | */ | |
385 | #define CM_OPEN_NONE 0 | |
386 | #define CM_OPEN_CH_MASK 0x01 | |
387 | #define CM_OPEN_DAC 0x10 | |
388 | #define CM_OPEN_ADC 0x20 | |
389 | #define CM_OPEN_SPDIF 0x40 | |
390 | #define CM_OPEN_MCHAN 0x80 | |
391 | #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC) | |
392 | #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC) | |
393 | #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN) | |
394 | #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC) | |
395 | #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF) | |
396 | #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF) | |
397 | ||
398 | ||
399 | #if CM_CH_PLAY == 1 | |
400 | #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K | |
401 | #define CM_PLAYBACK_SPDF CM_SPDF_1 | |
402 | #define CM_CAPTURE_SPDF CM_SPDF_0 | |
403 | #else | |
404 | #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K | |
405 | #define CM_PLAYBACK_SPDF CM_SPDF_0 | |
406 | #define CM_CAPTURE_SPDF CM_SPDF_1 | |
407 | #endif | |
408 | ||
409 | ||
410 | /* | |
411 | * driver data | |
412 | */ | |
413 | ||
2cbdb686 TI |
414 | struct cmipci_pcm { |
415 | struct snd_pcm_substream *substream; | |
ebe9e289 CL |
416 | u8 running; /* dac/adc running? */ |
417 | u8 fmt; /* format bits */ | |
418 | u8 is_dac; | |
c36fd8c3 | 419 | u8 needs_silencing; |
1da177e4 | 420 | unsigned int dma_size; /* in frames */ |
ebe9e289 CL |
421 | unsigned int shift; |
422 | unsigned int ch; /* channel (0/1) */ | |
1da177e4 | 423 | unsigned int offset; /* physical address of the buffer */ |
1da177e4 LT |
424 | }; |
425 | ||
426 | /* mixer elements toggled/resumed during ac3 playback */ | |
427 | struct cmipci_mixer_auto_switches { | |
428 | const char *name; /* switch to toggle */ | |
429 | int toggle_on; /* value to change when ac3 mode */ | |
430 | }; | |
431 | static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = { | |
432 | {"PCM Playback Switch", 0}, | |
433 | {"IEC958 Output Switch", 1}, | |
434 | {"IEC958 Mix Analog", 0}, | |
435 | // {"IEC958 Out To DAC", 1}, // no longer used | |
436 | {"IEC958 Loop", 0}, | |
437 | }; | |
438 | #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer) | |
439 | ||
2cbdb686 TI |
440 | struct cmipci { |
441 | struct snd_card *card; | |
1da177e4 LT |
442 | |
443 | struct pci_dev *pci; | |
444 | unsigned int device; /* device ID */ | |
445 | int irq; | |
446 | ||
447 | unsigned long iobase; | |
448 | unsigned int ctrl; /* FUNCTRL0 current value */ | |
449 | ||
2cbdb686 TI |
450 | struct snd_pcm *pcm; /* DAC/ADC PCM */ |
451 | struct snd_pcm *pcm2; /* 2nd DAC */ | |
452 | struct snd_pcm *pcm_spdif; /* SPDIF */ | |
1da177e4 LT |
453 | |
454 | int chip_version; | |
455 | int max_channels; | |
1da177e4 LT |
456 | unsigned int can_ac3_sw: 1; |
457 | unsigned int can_ac3_hw: 1; | |
458 | unsigned int can_multi_ch: 1; | |
755c48ab | 459 | unsigned int can_96k: 1; /* samplerate above 48k */ |
1da177e4 LT |
460 | unsigned int do_soft_ac3: 1; |
461 | ||
462 | unsigned int spdif_playback_avail: 1; /* spdif ready? */ | |
463 | unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ | |
464 | int spdif_counter; /* for software AC3 */ | |
465 | ||
466 | unsigned int dig_status; | |
467 | unsigned int dig_pcm_status; | |
468 | ||
2cbdb686 | 469 | struct snd_pcm_hardware *hw_info[3]; /* for playbacks */ |
1da177e4 LT |
470 | |
471 | int opened[2]; /* open mode */ | |
62932df8 | 472 | struct mutex open_mutex; |
1da177e4 LT |
473 | |
474 | unsigned int mixer_insensitive: 1; | |
2cbdb686 | 475 | struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS]; |
1da177e4 LT |
476 | int mixer_res_status[CM_SAVED_MIXERS]; |
477 | ||
2cbdb686 | 478 | struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ |
1da177e4 LT |
479 | |
480 | /* external MIDI */ | |
2cbdb686 | 481 | struct snd_rawmidi *rmidi; |
1da177e4 LT |
482 | |
483 | #ifdef SUPPORT_JOYSTICK | |
484 | struct gameport *gameport; | |
485 | #endif | |
486 | ||
487 | spinlock_t reg_lock; | |
cb60e5f5 | 488 | |
c7561cd8 | 489 | #ifdef CONFIG_PM_SLEEP |
cb60e5f5 TI |
490 | unsigned int saved_regs[0x20]; |
491 | unsigned char saved_mixers[0x20]; | |
492 | #endif | |
1da177e4 LT |
493 | }; |
494 | ||
495 | ||
496 | /* read/write operations for dword register */ | |
2cbdb686 | 497 | static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data) |
1da177e4 LT |
498 | { |
499 | outl(data, cm->iobase + cmd); | |
500 | } | |
77933d72 | 501 | |
2cbdb686 | 502 | static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd) |
1da177e4 LT |
503 | { |
504 | return inl(cm->iobase + cmd); | |
505 | } | |
506 | ||
507 | /* read/write operations for word register */ | |
2cbdb686 | 508 | static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data) |
1da177e4 LT |
509 | { |
510 | outw(data, cm->iobase + cmd); | |
511 | } | |
77933d72 | 512 | |
2cbdb686 | 513 | static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd) |
1da177e4 LT |
514 | { |
515 | return inw(cm->iobase + cmd); | |
516 | } | |
517 | ||
518 | /* read/write operations for byte register */ | |
2cbdb686 | 519 | static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data) |
1da177e4 LT |
520 | { |
521 | outb(data, cm->iobase + cmd); | |
522 | } | |
523 | ||
2cbdb686 | 524 | static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd) |
1da177e4 LT |
525 | { |
526 | return inb(cm->iobase + cmd); | |
527 | } | |
528 | ||
529 | /* bit operations for dword register */ | |
2cbdb686 | 530 | static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) |
1da177e4 | 531 | { |
01d25d46 TI |
532 | unsigned int val, oval; |
533 | val = oval = inl(cm->iobase + cmd); | |
1da177e4 | 534 | val |= flag; |
01d25d46 TI |
535 | if (val == oval) |
536 | return 0; | |
1da177e4 | 537 | outl(val, cm->iobase + cmd); |
01d25d46 | 538 | return 1; |
1da177e4 LT |
539 | } |
540 | ||
2cbdb686 | 541 | static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) |
1da177e4 | 542 | { |
01d25d46 TI |
543 | unsigned int val, oval; |
544 | val = oval = inl(cm->iobase + cmd); | |
1da177e4 | 545 | val &= ~flag; |
01d25d46 TI |
546 | if (val == oval) |
547 | return 0; | |
1da177e4 | 548 | outl(val, cm->iobase + cmd); |
01d25d46 | 549 | return 1; |
1da177e4 LT |
550 | } |
551 | ||
1da177e4 | 552 | /* bit operations for byte register */ |
2cbdb686 | 553 | static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) |
1da177e4 | 554 | { |
01d25d46 TI |
555 | unsigned char val, oval; |
556 | val = oval = inb(cm->iobase + cmd); | |
1da177e4 | 557 | val |= flag; |
01d25d46 TI |
558 | if (val == oval) |
559 | return 0; | |
1da177e4 | 560 | outb(val, cm->iobase + cmd); |
01d25d46 | 561 | return 1; |
1da177e4 LT |
562 | } |
563 | ||
2cbdb686 | 564 | static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) |
1da177e4 | 565 | { |
01d25d46 TI |
566 | unsigned char val, oval; |
567 | val = oval = inb(cm->iobase + cmd); | |
1da177e4 | 568 | val &= ~flag; |
01d25d46 TI |
569 | if (val == oval) |
570 | return 0; | |
1da177e4 | 571 | outb(val, cm->iobase + cmd); |
01d25d46 | 572 | return 1; |
1da177e4 | 573 | } |
1da177e4 LT |
574 | |
575 | ||
576 | /* | |
577 | * PCM interface | |
578 | */ | |
579 | ||
580 | /* | |
581 | * calculate frequency | |
582 | */ | |
583 | ||
5f3aca10 | 584 | static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 }; |
1da177e4 LT |
585 | |
586 | static unsigned int snd_cmipci_rate_freq(unsigned int rate) | |
587 | { | |
588 | unsigned int i; | |
0f28eca3 | 589 | |
1da177e4 LT |
590 | for (i = 0; i < ARRAY_SIZE(rates); i++) { |
591 | if (rates[i] == rate) | |
592 | return i; | |
593 | } | |
594 | snd_BUG(); | |
595 | return 0; | |
596 | } | |
597 | ||
598 | #ifdef USE_VAR48KRATE | |
599 | /* | |
600 | * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???) | |
601 | * does it this way .. maybe not. Never get any information from C-Media about | |
602 | * that <werner@suse.de>. | |
603 | */ | |
604 | static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n) | |
605 | { | |
606 | unsigned int delta, tolerance; | |
607 | int xm, xn, xr; | |
608 | ||
609 | for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5)) | |
610 | rate <<= 1; | |
611 | *n = -1; | |
612 | if (*r > 0xff) | |
613 | goto out; | |
614 | tolerance = rate*CM_TOLERANCE_RATE; | |
615 | ||
616 | for (xn = (1+2); xn < (0x1f+2); xn++) { | |
617 | for (xm = (1+2); xm < (0xff+2); xm++) { | |
618 | xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn; | |
619 | ||
620 | if (xr < rate) | |
621 | delta = rate - xr; | |
622 | else | |
623 | delta = xr - rate; | |
624 | ||
625 | /* | |
626 | * If we found one, remember this, | |
627 | * and try to find a closer one | |
628 | */ | |
629 | if (delta < tolerance) { | |
630 | tolerance = delta; | |
631 | *m = xm - 2; | |
632 | *n = xn - 2; | |
633 | } | |
634 | } | |
635 | } | |
636 | out: | |
637 | return (*n > -1); | |
638 | } | |
639 | ||
640 | /* | |
25985edc LDM |
641 | * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff |
642 | * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen | |
1da177e4 LT |
643 | * at the register CM_REG_FUNCTRL1 (0x04). |
644 | * Problem: other ways are also possible (any information about that?) | |
645 | */ | |
2cbdb686 | 646 | static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot) |
1da177e4 LT |
647 | { |
648 | unsigned int reg = CM_REG_PLL + slot; | |
649 | /* | |
650 | * Guess that this programs at reg. 0x04 the pos 15:13/12:10 | |
25985edc | 651 | * for DSFC/ASFC (000 up to 111). |
1da177e4 LT |
652 | */ |
653 | ||
654 | /* FIXME: Init (Do we've to set an other register first before programming?) */ | |
655 | ||
656 | /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */ | |
657 | snd_cmipci_write_b(cm, reg, rate>>8); | |
658 | snd_cmipci_write_b(cm, reg, rate&0xff); | |
659 | ||
660 | /* FIXME: Setup (Do we've to set an other register first to enable this?) */ | |
661 | } | |
662 | #endif /* USE_VAR48KRATE */ | |
663 | ||
2cbdb686 TI |
664 | static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream, |
665 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 666 | { |
2cbdb686 | 667 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 | 668 | if (params_channels(hw_params) > 2) { |
62932df8 | 669 | mutex_lock(&cm->open_mutex); |
1da177e4 | 670 | if (cm->opened[CM_CH_PLAY]) { |
62932df8 | 671 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
672 | return -EBUSY; |
673 | } | |
674 | /* reserve the channel A */ | |
675 | cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; | |
62932df8 | 676 | mutex_unlock(&cm->open_mutex); |
1da177e4 | 677 | } |
d841e2e8 | 678 | return 0; |
1da177e4 LT |
679 | } |
680 | ||
2cbdb686 | 681 | static void snd_cmipci_ch_reset(struct cmipci *cm, int ch) |
1da177e4 LT |
682 | { |
683 | int reset = CM_RST_CH0 << (cm->channel[ch].ch); | |
684 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); | |
685 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); | |
686 | udelay(10); | |
687 | } | |
688 | ||
1da177e4 LT |
689 | |
690 | /* | |
691 | */ | |
692 | ||
0fac3195 TI |
693 | static const unsigned int hw_channels[] = {1, 2, 4, 6, 8}; |
694 | static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = { | |
1da177e4 LT |
695 | .count = 3, |
696 | .list = hw_channels, | |
697 | .mask = 0, | |
698 | }; | |
0fac3195 | 699 | static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = { |
35add1c2 | 700 | .count = 4, |
1da177e4 LT |
701 | .list = hw_channels, |
702 | .mask = 0, | |
703 | }; | |
0fac3195 | 704 | static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = { |
35add1c2 | 705 | .count = 5, |
1da177e4 LT |
706 | .list = hw_channels, |
707 | .mask = 0, | |
708 | }; | |
709 | ||
2cbdb686 | 710 | static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels) |
1da177e4 LT |
711 | { |
712 | if (channels > 2) { | |
8ffbc01e | 713 | if (!cm->can_multi_ch || !rec->ch) |
1da177e4 LT |
714 | return -EINVAL; |
715 | if (rec->fmt != 0x03) /* stereo 16bit only */ | |
716 | return -EINVAL; | |
8ffbc01e | 717 | } |
1da177e4 | 718 | |
8ffbc01e | 719 | if (cm->can_multi_ch) { |
1da177e4 | 720 | spin_lock_irq(&cm->reg_lock); |
8ffbc01e CL |
721 | if (channels > 2) { |
722 | snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); | |
723 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
1da177e4 | 724 | } else { |
8ffbc01e CL |
725 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); |
726 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
1da177e4 | 727 | } |
8ffbc01e CL |
728 | if (channels == 8) |
729 | snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C); | |
730 | else | |
731 | snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C); | |
732 | if (channels == 6) { | |
733 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); | |
1da177e4 | 734 | snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); |
1da177e4 | 735 | } else { |
1da177e4 LT |
736 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); |
737 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); | |
1da177e4 | 738 | } |
8ffbc01e CL |
739 | if (channels == 4) |
740 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); | |
741 | else | |
742 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); | |
743 | spin_unlock_irq(&cm->reg_lock); | |
1da177e4 LT |
744 | } |
745 | return 0; | |
746 | } | |
747 | ||
748 | ||
749 | /* | |
750 | * prepare playback/capture channel | |
751 | * channel to be used must have been set in rec->ch. | |
752 | */ | |
2cbdb686 TI |
753 | static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec, |
754 | struct snd_pcm_substream *substream) | |
1da177e4 | 755 | { |
755c48ab | 756 | unsigned int reg, freq, freq_ext, val; |
ebe9e289 | 757 | unsigned int period_size; |
2cbdb686 | 758 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
759 | |
760 | rec->fmt = 0; | |
761 | rec->shift = 0; | |
762 | if (snd_pcm_format_width(runtime->format) >= 16) { | |
763 | rec->fmt |= 0x02; | |
764 | if (snd_pcm_format_width(runtime->format) > 16) | |
765 | rec->shift++; /* 24/32bit */ | |
766 | } | |
767 | if (runtime->channels > 1) | |
768 | rec->fmt |= 0x01; | |
769 | if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { | |
40175bdb | 770 | dev_dbg(cm->card->dev, "cannot set dac channels\n"); |
1da177e4 LT |
771 | return -EINVAL; |
772 | } | |
773 | ||
774 | rec->offset = runtime->dma_addr; | |
775 | /* buffer and period sizes in frame */ | |
776 | rec->dma_size = runtime->buffer_size << rec->shift; | |
ebe9e289 | 777 | period_size = runtime->period_size << rec->shift; |
1da177e4 LT |
778 | if (runtime->channels > 2) { |
779 | /* multi-channels */ | |
780 | rec->dma_size = (rec->dma_size * runtime->channels) / 2; | |
ebe9e289 | 781 | period_size = (period_size * runtime->channels) / 2; |
1da177e4 LT |
782 | } |
783 | ||
784 | spin_lock_irq(&cm->reg_lock); | |
785 | ||
786 | /* set buffer address */ | |
787 | reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; | |
788 | snd_cmipci_write(cm, reg, rec->offset); | |
789 | /* program sample counts */ | |
790 | reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; | |
791 | snd_cmipci_write_w(cm, reg, rec->dma_size - 1); | |
ebe9e289 | 792 | snd_cmipci_write_w(cm, reg + 2, period_size - 1); |
1da177e4 LT |
793 | |
794 | /* set adc/dac flag */ | |
795 | val = rec->ch ? CM_CHADC1 : CM_CHADC0; | |
796 | if (rec->is_dac) | |
797 | cm->ctrl &= ~val; | |
798 | else | |
799 | cm->ctrl |= val; | |
800 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
40175bdb | 801 | /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */ |
1da177e4 LT |
802 | |
803 | /* set sample rate */ | |
755c48ab TB |
804 | freq = 0; |
805 | freq_ext = 0; | |
806 | if (runtime->rate > 48000) | |
807 | switch (runtime->rate) { | |
808 | case 88200: freq_ext = CM_CH0_SRATE_88K; break; | |
809 | case 96000: freq_ext = CM_CH0_SRATE_96K; break; | |
810 | case 128000: freq_ext = CM_CH0_SRATE_128K; break; | |
811 | default: snd_BUG(); break; | |
812 | } | |
813 | else | |
814 | freq = snd_cmipci_rate_freq(runtime->rate); | |
1da177e4 LT |
815 | val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); |
816 | if (rec->ch) { | |
1da177e4 LT |
817 | val &= ~CM_DSFC_MASK; |
818 | val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; | |
a839a33d CL |
819 | } else { |
820 | val &= ~CM_ASFC_MASK; | |
821 | val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; | |
1da177e4 LT |
822 | } |
823 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); | |
40175bdb | 824 | dev_dbg(cm->card->dev, "functrl1 = %08x\n", val); |
1da177e4 LT |
825 | |
826 | /* set format */ | |
827 | val = snd_cmipci_read(cm, CM_REG_CHFORMAT); | |
828 | if (rec->ch) { | |
829 | val &= ~CM_CH1FMT_MASK; | |
830 | val |= rec->fmt << CM_CH1FMT_SHIFT; | |
831 | } else { | |
832 | val &= ~CM_CH0FMT_MASK; | |
833 | val |= rec->fmt << CM_CH0FMT_SHIFT; | |
834 | } | |
755c48ab TB |
835 | if (cm->can_96k) { |
836 | val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); | |
837 | val |= freq_ext << (rec->ch * 2); | |
8992e18d | 838 | } |
1da177e4 | 839 | snd_cmipci_write(cm, CM_REG_CHFORMAT, val); |
40175bdb | 840 | dev_dbg(cm->card->dev, "chformat = %08x\n", val); |
1da177e4 | 841 | |
feb77712 TB |
842 | if (!rec->is_dac && cm->chip_version) { |
843 | if (runtime->rate > 44100) | |
844 | snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K); | |
845 | else | |
846 | snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K); | |
847 | } | |
848 | ||
1da177e4 LT |
849 | rec->running = 0; |
850 | spin_unlock_irq(&cm->reg_lock); | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
855 | /* | |
856 | * PCM trigger/stop | |
857 | */ | |
2cbdb686 | 858 | static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec, |
ebe9e289 | 859 | int cmd) |
1da177e4 LT |
860 | { |
861 | unsigned int inthld, chen, reset, pause; | |
862 | int result = 0; | |
863 | ||
864 | inthld = CM_CH0_INT_EN << rec->ch; | |
865 | chen = CM_CHEN0 << rec->ch; | |
866 | reset = CM_RST_CH0 << rec->ch; | |
867 | pause = CM_PAUSE0 << rec->ch; | |
868 | ||
869 | spin_lock(&cm->reg_lock); | |
870 | switch (cmd) { | |
871 | case SNDRV_PCM_TRIGGER_START: | |
872 | rec->running = 1; | |
873 | /* set interrupt */ | |
874 | snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); | |
875 | cm->ctrl |= chen; | |
876 | /* enable channel */ | |
877 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
40175bdb | 878 | dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); |
1da177e4 LT |
879 | break; |
880 | case SNDRV_PCM_TRIGGER_STOP: | |
881 | rec->running = 0; | |
882 | /* disable interrupt */ | |
883 | snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); | |
884 | /* reset */ | |
885 | cm->ctrl &= ~chen; | |
886 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); | |
887 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); | |
c36fd8c3 | 888 | rec->needs_silencing = rec->is_dac; |
1da177e4 LT |
889 | break; |
890 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
cb60e5f5 | 891 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 LT |
892 | cm->ctrl |= pause; |
893 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
894 | break; | |
895 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
cb60e5f5 | 896 | case SNDRV_PCM_TRIGGER_RESUME: |
1da177e4 LT |
897 | cm->ctrl &= ~pause; |
898 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
899 | break; | |
900 | default: | |
901 | result = -EINVAL; | |
902 | break; | |
903 | } | |
904 | spin_unlock(&cm->reg_lock); | |
905 | return result; | |
906 | } | |
907 | ||
908 | /* | |
909 | * return the current pointer | |
910 | */ | |
2cbdb686 TI |
911 | static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec, |
912 | struct snd_pcm_substream *substream) | |
1da177e4 LT |
913 | { |
914 | size_t ptr; | |
1c583063 CL |
915 | unsigned int reg, rem, tries; |
916 | ||
1da177e4 LT |
917 | if (!rec->running) |
918 | return 0; | |
919 | #if 1 // this seems better.. | |
920 | reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; | |
1c583063 CL |
921 | for (tries = 0; tries < 3; tries++) { |
922 | rem = snd_cmipci_read_w(cm, reg); | |
923 | if (rem < rec->dma_size) | |
924 | goto ok; | |
925 | } | |
40175bdb | 926 | dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem); |
1c583063 CL |
927 | return SNDRV_PCM_POS_XRUN; |
928 | ok: | |
929 | ptr = (rec->dma_size - (rem + 1)) >> rec->shift; | |
1da177e4 LT |
930 | #else |
931 | reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; | |
932 | ptr = snd_cmipci_read(cm, reg) - rec->offset; | |
933 | ptr = bytes_to_frames(substream->runtime, ptr); | |
934 | #endif | |
935 | if (substream->runtime->channels > 2) | |
936 | ptr = (ptr * 2) / substream->runtime->channels; | |
937 | return ptr; | |
938 | } | |
939 | ||
940 | /* | |
941 | * playback | |
942 | */ | |
943 | ||
2cbdb686 | 944 | static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
945 | int cmd) |
946 | { | |
2cbdb686 | 947 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
ebe9e289 | 948 | return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd); |
1da177e4 LT |
949 | } |
950 | ||
2cbdb686 | 951 | static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 952 | { |
2cbdb686 | 953 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
954 | return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream); |
955 | } | |
956 | ||
957 | ||
958 | ||
959 | /* | |
960 | * capture | |
961 | */ | |
962 | ||
2cbdb686 | 963 | static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
964 | int cmd) |
965 | { | |
2cbdb686 | 966 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
ebe9e289 | 967 | return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd); |
1da177e4 LT |
968 | } |
969 | ||
2cbdb686 | 970 | static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 971 | { |
2cbdb686 | 972 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
973 | return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream); |
974 | } | |
975 | ||
976 | ||
977 | /* | |
978 | * hw preparation for spdif | |
979 | */ | |
980 | ||
2cbdb686 TI |
981 | static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol, |
982 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
983 | { |
984 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
985 | uinfo->count = 1; | |
986 | return 0; | |
987 | } | |
988 | ||
2cbdb686 TI |
989 | static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol, |
990 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 991 | { |
2cbdb686 | 992 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
993 | int i; |
994 | ||
995 | spin_lock_irq(&chip->reg_lock); | |
996 | for (i = 0; i < 4; i++) | |
997 | ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff; | |
998 | spin_unlock_irq(&chip->reg_lock); | |
999 | return 0; | |
1000 | } | |
1001 | ||
2cbdb686 TI |
1002 | static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol, |
1003 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1004 | { |
2cbdb686 | 1005 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1006 | int i, change; |
1007 | unsigned int val; | |
1008 | ||
1009 | val = 0; | |
1010 | spin_lock_irq(&chip->reg_lock); | |
1011 | for (i = 0; i < 4; i++) | |
1012 | val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); | |
1013 | change = val != chip->dig_status; | |
1014 | chip->dig_status = val; | |
1015 | spin_unlock_irq(&chip->reg_lock); | |
1016 | return change; | |
1017 | } | |
1018 | ||
f3b827e0 | 1019 | static const struct snd_kcontrol_new snd_cmipci_spdif_default = |
1da177e4 LT |
1020 | { |
1021 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1022 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), | |
1023 | .info = snd_cmipci_spdif_default_info, | |
1024 | .get = snd_cmipci_spdif_default_get, | |
1025 | .put = snd_cmipci_spdif_default_put | |
1026 | }; | |
1027 | ||
2cbdb686 TI |
1028 | static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol, |
1029 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1030 | { |
1031 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1032 | uinfo->count = 1; | |
1033 | return 0; | |
1034 | } | |
1035 | ||
2cbdb686 TI |
1036 | static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol, |
1037 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 LT |
1038 | { |
1039 | ucontrol->value.iec958.status[0] = 0xff; | |
1040 | ucontrol->value.iec958.status[1] = 0xff; | |
1041 | ucontrol->value.iec958.status[2] = 0xff; | |
1042 | ucontrol->value.iec958.status[3] = 0xff; | |
1043 | return 0; | |
1044 | } | |
1045 | ||
f3b827e0 | 1046 | static const struct snd_kcontrol_new snd_cmipci_spdif_mask = |
1da177e4 LT |
1047 | { |
1048 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
67ed4161 | 1049 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
1050 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), |
1051 | .info = snd_cmipci_spdif_mask_info, | |
1052 | .get = snd_cmipci_spdif_mask_get, | |
1053 | }; | |
1054 | ||
2cbdb686 TI |
1055 | static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol, |
1056 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1057 | { |
1058 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1059 | uinfo->count = 1; | |
1060 | return 0; | |
1061 | } | |
1062 | ||
2cbdb686 TI |
1063 | static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol, |
1064 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1065 | { |
2cbdb686 | 1066 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1067 | int i; |
1068 | ||
1069 | spin_lock_irq(&chip->reg_lock); | |
1070 | for (i = 0; i < 4; i++) | |
1071 | ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff; | |
1072 | spin_unlock_irq(&chip->reg_lock); | |
1073 | return 0; | |
1074 | } | |
1075 | ||
2cbdb686 TI |
1076 | static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol, |
1077 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1078 | { |
2cbdb686 | 1079 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1080 | int i, change; |
1081 | unsigned int val; | |
1082 | ||
1083 | val = 0; | |
1084 | spin_lock_irq(&chip->reg_lock); | |
1085 | for (i = 0; i < 4; i++) | |
1086 | val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); | |
1087 | change = val != chip->dig_pcm_status; | |
1088 | chip->dig_pcm_status = val; | |
1089 | spin_unlock_irq(&chip->reg_lock); | |
1090 | return change; | |
1091 | } | |
1092 | ||
f3b827e0 | 1093 | static const struct snd_kcontrol_new snd_cmipci_spdif_stream = |
1da177e4 LT |
1094 | { |
1095 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, | |
1096 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1097 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), | |
1098 | .info = snd_cmipci_spdif_stream_info, | |
1099 | .get = snd_cmipci_spdif_stream_get, | |
1100 | .put = snd_cmipci_spdif_stream_put | |
1101 | }; | |
1102 | ||
1103 | /* | |
1104 | */ | |
1105 | ||
1106 | /* save mixer setting and mute for AC3 playback */ | |
2cbdb686 | 1107 | static int save_mixer_state(struct cmipci *cm) |
1da177e4 LT |
1108 | { |
1109 | if (! cm->mixer_insensitive) { | |
2cbdb686 | 1110 | struct snd_ctl_elem_value *val; |
1da177e4 LT |
1111 | unsigned int i; |
1112 | ||
0be51680 | 1113 | val = kmalloc(sizeof(*val), GFP_KERNEL); |
1da177e4 LT |
1114 | if (!val) |
1115 | return -ENOMEM; | |
1116 | for (i = 0; i < CM_SAVED_MIXERS; i++) { | |
2cbdb686 | 1117 | struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; |
1da177e4 LT |
1118 | if (ctl) { |
1119 | int event; | |
1120 | memset(val, 0, sizeof(*val)); | |
1121 | ctl->get(ctl, val); | |
1122 | cm->mixer_res_status[i] = val->value.integer.value[0]; | |
1123 | val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; | |
1124 | event = SNDRV_CTL_EVENT_MASK_INFO; | |
1125 | if (cm->mixer_res_status[i] != val->value.integer.value[0]) { | |
1126 | ctl->put(ctl, val); /* toggle */ | |
1127 | event |= SNDRV_CTL_EVENT_MASK_VALUE; | |
1128 | } | |
1129 | ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
1130 | snd_ctl_notify(cm->card, event, &ctl->id); | |
1131 | } | |
1132 | } | |
1133 | kfree(val); | |
1134 | cm->mixer_insensitive = 1; | |
1135 | } | |
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | ||
1140 | /* restore the previously saved mixer status */ | |
2cbdb686 | 1141 | static void restore_mixer_state(struct cmipci *cm) |
1da177e4 LT |
1142 | { |
1143 | if (cm->mixer_insensitive) { | |
2cbdb686 | 1144 | struct snd_ctl_elem_value *val; |
1da177e4 LT |
1145 | unsigned int i; |
1146 | ||
1147 | val = kmalloc(sizeof(*val), GFP_KERNEL); | |
1148 | if (!val) | |
1149 | return; | |
1150 | cm->mixer_insensitive = 0; /* at first clear this; | |
1151 | otherwise the changes will be ignored */ | |
1152 | for (i = 0; i < CM_SAVED_MIXERS; i++) { | |
2cbdb686 | 1153 | struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; |
1da177e4 LT |
1154 | if (ctl) { |
1155 | int event; | |
1156 | ||
1157 | memset(val, 0, sizeof(*val)); | |
1158 | ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
1159 | ctl->get(ctl, val); | |
1160 | event = SNDRV_CTL_EVENT_MASK_INFO; | |
1161 | if (val->value.integer.value[0] != cm->mixer_res_status[i]) { | |
1162 | val->value.integer.value[0] = cm->mixer_res_status[i]; | |
1163 | ctl->put(ctl, val); | |
1164 | event |= SNDRV_CTL_EVENT_MASK_VALUE; | |
1165 | } | |
1166 | snd_ctl_notify(cm->card, event, &ctl->id); | |
1167 | } | |
1168 | } | |
1169 | kfree(val); | |
1170 | } | |
1171 | } | |
1172 | ||
1173 | /* spinlock held! */ | |
2cbdb686 | 1174 | static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate) |
1da177e4 LT |
1175 | { |
1176 | if (do_ac3) { | |
1177 | /* AC3EN for 037 */ | |
1178 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); | |
1179 | /* AC3EN for 039 */ | |
1180 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); | |
1181 | ||
1182 | if (cm->can_ac3_hw) { | |
1183 | /* SPD24SEL for 037, 0x02 */ | |
1184 | /* SPD24SEL for 039, 0x20, but cannot be set */ | |
1185 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1186 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1187 | } else { /* can_ac3_sw */ | |
1188 | /* SPD32SEL for 037 & 039, 0x20 */ | |
1189 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1190 | /* set 176K sample rate to fix 033 HW bug */ | |
1191 | if (cm->chip_version == 33) { | |
1192 | if (rate >= 48000) { | |
1193 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); | |
1194 | } else { | |
1195 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); | |
1196 | } | |
1197 | } | |
1198 | } | |
1199 | ||
1200 | } else { | |
1201 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); | |
1202 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); | |
1203 | ||
1204 | if (cm->can_ac3_hw) { | |
1205 | /* chip model >= 37 */ | |
1206 | if (snd_pcm_format_width(subs->runtime->format) > 16) { | |
1207 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1208 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1209 | } else { | |
1210 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1211 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1212 | } | |
1213 | } else { | |
1214 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1215 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1216 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); | |
1217 | } | |
1218 | } | |
1219 | } | |
1220 | ||
2cbdb686 | 1221 | static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3) |
1da177e4 LT |
1222 | { |
1223 | int rate, err; | |
1224 | ||
1225 | rate = subs->runtime->rate; | |
1226 | ||
43795882 TI |
1227 | if (up && do_ac3) { |
1228 | err = save_mixer_state(cm); | |
1229 | if (err < 0) | |
1da177e4 | 1230 | return err; |
43795882 | 1231 | } |
1da177e4 LT |
1232 | |
1233 | spin_lock_irq(&cm->reg_lock); | |
1234 | cm->spdif_playback_avail = up; | |
1235 | if (up) { | |
1236 | /* they are controlled via "IEC958 Output Switch" */ | |
1237 | /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ | |
1238 | /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ | |
1239 | if (cm->spdif_playback_enabled) | |
1240 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
1241 | setup_ac3(cm, subs, do_ac3, rate); | |
1242 | ||
8992e18d | 1243 | if (rate == 48000 || rate == 96000) |
1da177e4 LT |
1244 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); |
1245 | else | |
1246 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); | |
8992e18d CL |
1247 | if (rate > 48000) |
1248 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); | |
1249 | else | |
1250 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); | |
1da177e4 LT |
1251 | } else { |
1252 | /* they are controlled via "IEC958 Output Switch" */ | |
1253 | /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ | |
1254 | /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ | |
8992e18d | 1255 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); |
1da177e4 LT |
1256 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); |
1257 | setup_ac3(cm, subs, 0, 0); | |
1258 | } | |
1259 | spin_unlock_irq(&cm->reg_lock); | |
1260 | return 0; | |
1261 | } | |
1262 | ||
1263 | ||
1264 | /* | |
1265 | * preparation | |
1266 | */ | |
1267 | ||
1268 | /* playback - enable spdif only on the certain condition */ | |
2cbdb686 | 1269 | static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1270 | { |
2cbdb686 | 1271 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1272 | int rate = substream->runtime->rate; |
1273 | int err, do_spdif, do_ac3 = 0; | |
1274 | ||
755c48ab | 1275 | do_spdif = (rate >= 44100 && rate <= 96000 && |
1da177e4 LT |
1276 | substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && |
1277 | substream->runtime->channels == 2); | |
1278 | if (do_spdif && cm->can_ac3_hw) | |
1279 | do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; | |
43795882 TI |
1280 | err = setup_spdif_playback(cm, substream, do_spdif, do_ac3); |
1281 | if (err < 0) | |
1da177e4 LT |
1282 | return err; |
1283 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); | |
1284 | } | |
1285 | ||
1286 | /* playback (via device #2) - enable spdif always */ | |
2cbdb686 | 1287 | static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1288 | { |
2cbdb686 | 1289 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1290 | int err, do_ac3; |
1291 | ||
1292 | if (cm->can_ac3_hw) | |
1293 | do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; | |
1294 | else | |
1295 | do_ac3 = 1; /* doesn't matter */ | |
43795882 TI |
1296 | err = setup_spdif_playback(cm, substream, 1, do_ac3); |
1297 | if (err < 0) | |
1da177e4 LT |
1298 | return err; |
1299 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); | |
1300 | } | |
1301 | ||
c36fd8c3 CL |
1302 | /* |
1303 | * Apparently, the samples last played on channel A stay in some buffer, even | |
1304 | * after the channel is reset, and get added to the data for the rear DACs when | |
1305 | * playing a multichannel stream on channel B. This is likely to generate | |
1306 | * wraparounds and thus distortions. | |
1307 | * To avoid this, we play at least one zero sample after the actual stream has | |
1308 | * stopped. | |
1309 | */ | |
1310 | static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec) | |
1311 | { | |
1312 | struct snd_pcm_runtime *runtime = rec->substream->runtime; | |
1313 | unsigned int reg, val; | |
1314 | ||
1315 | if (rec->needs_silencing && runtime && runtime->dma_area) { | |
1316 | /* set up a small silence buffer */ | |
1317 | memset(runtime->dma_area, 0, PAGE_SIZE); | |
1318 | reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; | |
1319 | val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16); | |
1320 | snd_cmipci_write(cm, reg, val); | |
1321 | ||
1322 | /* configure for 16 bits, 2 channels, 8 kHz */ | |
1323 | if (runtime->channels > 2) | |
1324 | set_dac_channels(cm, rec, 2); | |
1325 | spin_lock_irq(&cm->reg_lock); | |
1326 | val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); | |
1327 | val &= ~(CM_ASFC_MASK << (rec->ch * 3)); | |
1328 | val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3); | |
1329 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); | |
1330 | val = snd_cmipci_read(cm, CM_REG_CHFORMAT); | |
1331 | val &= ~(CM_CH0FMT_MASK << (rec->ch * 2)); | |
1332 | val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2); | |
755c48ab TB |
1333 | if (cm->can_96k) |
1334 | val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); | |
c36fd8c3 CL |
1335 | snd_cmipci_write(cm, CM_REG_CHFORMAT, val); |
1336 | ||
1337 | /* start stream (we don't need interrupts) */ | |
1338 | cm->ctrl |= CM_CHEN0 << rec->ch; | |
1339 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
1340 | spin_unlock_irq(&cm->reg_lock); | |
1341 | ||
1342 | msleep(1); | |
1343 | ||
1344 | /* stop and reset stream */ | |
1345 | spin_lock_irq(&cm->reg_lock); | |
1346 | cm->ctrl &= ~(CM_CHEN0 << rec->ch); | |
1347 | val = CM_RST_CH0 << rec->ch; | |
1348 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val); | |
1349 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val); | |
1350 | spin_unlock_irq(&cm->reg_lock); | |
1351 | ||
1352 | rec->needs_silencing = 0; | |
1353 | } | |
1354 | } | |
1355 | ||
2cbdb686 | 1356 | static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 1357 | { |
2cbdb686 | 1358 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1359 | setup_spdif_playback(cm, substream, 0, 0); |
1360 | restore_mixer_state(cm); | |
c36fd8c3 | 1361 | snd_cmipci_silence_hack(cm, &cm->channel[0]); |
d841e2e8 | 1362 | return 0; |
c36fd8c3 CL |
1363 | } |
1364 | ||
1365 | static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream) | |
1366 | { | |
1367 | struct cmipci *cm = snd_pcm_substream_chip(substream); | |
1368 | snd_cmipci_silence_hack(cm, &cm->channel[1]); | |
d841e2e8 | 1369 | return 0; |
1da177e4 LT |
1370 | } |
1371 | ||
1372 | /* capture */ | |
2cbdb686 | 1373 | static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1374 | { |
2cbdb686 | 1375 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1376 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); |
1377 | } | |
1378 | ||
1379 | /* capture with spdif (via device #2) */ | |
2cbdb686 | 1380 | static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1381 | { |
2cbdb686 | 1382 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1383 | |
1384 | spin_lock_irq(&cm->reg_lock); | |
1385 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); | |
755c48ab TB |
1386 | if (cm->can_96k) { |
1387 | if (substream->runtime->rate > 48000) | |
1388 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); | |
1389 | else | |
1390 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); | |
1391 | } | |
b46be727 TB |
1392 | if (snd_pcm_format_width(substream->runtime->format) > 16) |
1393 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1394 | else | |
1395 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1396 | ||
1da177e4 LT |
1397 | spin_unlock_irq(&cm->reg_lock); |
1398 | ||
1399 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); | |
1400 | } | |
1401 | ||
2cbdb686 | 1402 | static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs) |
1da177e4 | 1403 | { |
2cbdb686 | 1404 | struct cmipci *cm = snd_pcm_substream_chip(subs); |
1da177e4 LT |
1405 | |
1406 | spin_lock_irq(&cm->reg_lock); | |
1407 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); | |
b46be727 | 1408 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); |
1da177e4 LT |
1409 | spin_unlock_irq(&cm->reg_lock); |
1410 | ||
d841e2e8 | 1411 | return 0; |
1da177e4 LT |
1412 | } |
1413 | ||
1414 | ||
1415 | /* | |
1416 | * interrupt handler | |
1417 | */ | |
7d12e780 | 1418 | static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id) |
1da177e4 | 1419 | { |
2cbdb686 | 1420 | struct cmipci *cm = dev_id; |
1da177e4 LT |
1421 | unsigned int status, mask = 0; |
1422 | ||
1423 | /* fastpath out, to ease interrupt sharing */ | |
1424 | status = snd_cmipci_read(cm, CM_REG_INT_STATUS); | |
1425 | if (!(status & CM_INTR)) | |
1426 | return IRQ_NONE; | |
1427 | ||
1428 | /* acknowledge interrupt */ | |
1429 | spin_lock(&cm->reg_lock); | |
1430 | if (status & CM_CHINT0) | |
1431 | mask |= CM_CH0_INT_EN; | |
1432 | if (status & CM_CHINT1) | |
1433 | mask |= CM_CH1_INT_EN; | |
1434 | snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); | |
1435 | snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); | |
1436 | spin_unlock(&cm->reg_lock); | |
1437 | ||
1438 | if (cm->rmidi && (status & CM_UARTINT)) | |
7d12e780 | 1439 | snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data); |
1da177e4 LT |
1440 | |
1441 | if (cm->pcm) { | |
1442 | if ((status & CM_CHINT0) && cm->channel[0].running) | |
1443 | snd_pcm_period_elapsed(cm->channel[0].substream); | |
1444 | if ((status & CM_CHINT1) && cm->channel[1].running) | |
1445 | snd_pcm_period_elapsed(cm->channel[1].substream); | |
1446 | } | |
1447 | return IRQ_HANDLED; | |
1448 | } | |
1449 | ||
1450 | /* | |
1451 | * h/w infos | |
1452 | */ | |
1453 | ||
1454 | /* playback on channel A */ | |
dee49895 | 1455 | static const struct snd_pcm_hardware snd_cmipci_playback = |
1da177e4 LT |
1456 | { |
1457 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1458 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1459 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1460 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
1461 | .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, | |
1462 | .rate_min = 5512, | |
1463 | .rate_max = 48000, | |
1464 | .channels_min = 1, | |
1465 | .channels_max = 2, | |
1466 | .buffer_bytes_max = (128*1024), | |
1467 | .period_bytes_min = 64, | |
1468 | .period_bytes_max = (128*1024), | |
1469 | .periods_min = 2, | |
1470 | .periods_max = 1024, | |
1471 | .fifo_size = 0, | |
1472 | }; | |
1473 | ||
1474 | /* capture on channel B */ | |
dee49895 | 1475 | static const struct snd_pcm_hardware snd_cmipci_capture = |
1da177e4 LT |
1476 | { |
1477 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1478 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1479 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1480 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
1481 | .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, | |
1482 | .rate_min = 5512, | |
1483 | .rate_max = 48000, | |
1484 | .channels_min = 1, | |
1485 | .channels_max = 2, | |
1486 | .buffer_bytes_max = (128*1024), | |
1487 | .period_bytes_min = 64, | |
1488 | .period_bytes_max = (128*1024), | |
1489 | .periods_min = 2, | |
1490 | .periods_max = 1024, | |
1491 | .fifo_size = 0, | |
1492 | }; | |
1493 | ||
1494 | /* playback on channel B - stereo 16bit only? */ | |
dee49895 | 1495 | static const struct snd_pcm_hardware snd_cmipci_playback2 = |
1da177e4 LT |
1496 | { |
1497 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1498 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1499 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1500 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1501 | .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, | |
1502 | .rate_min = 5512, | |
1503 | .rate_max = 48000, | |
1504 | .channels_min = 2, | |
1505 | .channels_max = 2, | |
1506 | .buffer_bytes_max = (128*1024), | |
1507 | .period_bytes_min = 64, | |
1508 | .period_bytes_max = (128*1024), | |
1509 | .periods_min = 2, | |
1510 | .periods_max = 1024, | |
1511 | .fifo_size = 0, | |
1512 | }; | |
1513 | ||
1514 | /* spdif playback on channel A */ | |
dee49895 | 1515 | static const struct snd_pcm_hardware snd_cmipci_playback_spdif = |
1da177e4 LT |
1516 | { |
1517 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1518 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1519 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1520 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1521 | .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, | |
1522 | .rate_min = 44100, | |
1523 | .rate_max = 48000, | |
1524 | .channels_min = 2, | |
1525 | .channels_max = 2, | |
1526 | .buffer_bytes_max = (128*1024), | |
1527 | .period_bytes_min = 64, | |
1528 | .period_bytes_max = (128*1024), | |
1529 | .periods_min = 2, | |
1530 | .periods_max = 1024, | |
1531 | .fifo_size = 0, | |
1532 | }; | |
1533 | ||
1534 | /* spdif playback on channel A (32bit, IEC958 subframes) */ | |
dee49895 | 1535 | static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe = |
1da177e4 LT |
1536 | { |
1537 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1538 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1539 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1540 | .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, |
1541 | .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, | |
1542 | .rate_min = 44100, | |
1543 | .rate_max = 48000, | |
1544 | .channels_min = 2, | |
1545 | .channels_max = 2, | |
1546 | .buffer_bytes_max = (128*1024), | |
1547 | .period_bytes_min = 64, | |
1548 | .period_bytes_max = (128*1024), | |
1549 | .periods_min = 2, | |
1550 | .periods_max = 1024, | |
1551 | .fifo_size = 0, | |
1552 | }; | |
1553 | ||
1554 | /* spdif capture on channel B */ | |
dee49895 | 1555 | static const struct snd_pcm_hardware snd_cmipci_capture_spdif = |
1da177e4 LT |
1556 | { |
1557 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1558 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1559 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
b46be727 TB |
1560 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
1561 | SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, | |
1da177e4 LT |
1562 | .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, |
1563 | .rate_min = 44100, | |
1564 | .rate_max = 48000, | |
1565 | .channels_min = 2, | |
1566 | .channels_max = 2, | |
1567 | .buffer_bytes_max = (128*1024), | |
1568 | .period_bytes_min = 64, | |
1569 | .period_bytes_max = (128*1024), | |
1570 | .periods_min = 2, | |
1571 | .periods_max = 1024, | |
1572 | .fifo_size = 0, | |
1573 | }; | |
1574 | ||
0fac3195 | 1575 | static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050, |
755c48ab | 1576 | 32000, 44100, 48000, 88200, 96000, 128000 }; |
0fac3195 | 1577 | static const struct snd_pcm_hw_constraint_list hw_constraints_rates = { |
755c48ab TB |
1578 | .count = ARRAY_SIZE(rate_constraints), |
1579 | .list = rate_constraints, | |
1580 | .mask = 0, | |
1581 | }; | |
1582 | ||
1da177e4 LT |
1583 | /* |
1584 | * check device open/close | |
1585 | */ | |
2cbdb686 | 1586 | static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs) |
1da177e4 LT |
1587 | { |
1588 | int ch = mode & CM_OPEN_CH_MASK; | |
1589 | ||
1590 | /* FIXME: a file should wait until the device becomes free | |
1591 | * when it's opened on blocking mode. however, since the current | |
1592 | * pcm framework doesn't pass file pointer before actually opened, | |
1593 | * we can't know whether blocking mode or not in open callback.. | |
1594 | */ | |
62932df8 | 1595 | mutex_lock(&cm->open_mutex); |
1da177e4 | 1596 | if (cm->opened[ch]) { |
62932df8 | 1597 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
1598 | return -EBUSY; |
1599 | } | |
1600 | cm->opened[ch] = mode; | |
1601 | cm->channel[ch].substream = subs; | |
1602 | if (! (mode & CM_OPEN_DAC)) { | |
1603 | /* disable dual DAC mode */ | |
1604 | cm->channel[ch].is_dac = 0; | |
1605 | spin_lock_irq(&cm->reg_lock); | |
1606 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); | |
1607 | spin_unlock_irq(&cm->reg_lock); | |
1608 | } | |
62932df8 | 1609 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
1610 | return 0; |
1611 | } | |
1612 | ||
2cbdb686 | 1613 | static void close_device_check(struct cmipci *cm, int mode) |
1da177e4 LT |
1614 | { |
1615 | int ch = mode & CM_OPEN_CH_MASK; | |
1616 | ||
62932df8 | 1617 | mutex_lock(&cm->open_mutex); |
1da177e4 LT |
1618 | if (cm->opened[ch] == mode) { |
1619 | if (cm->channel[ch].substream) { | |
1620 | snd_cmipci_ch_reset(cm, ch); | |
1621 | cm->channel[ch].running = 0; | |
1622 | cm->channel[ch].substream = NULL; | |
1623 | } | |
1624 | cm->opened[ch] = 0; | |
1625 | if (! cm->channel[ch].is_dac) { | |
1626 | /* enable dual DAC mode again */ | |
1627 | cm->channel[ch].is_dac = 1; | |
1628 | spin_lock_irq(&cm->reg_lock); | |
1629 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); | |
1630 | spin_unlock_irq(&cm->reg_lock); | |
1631 | } | |
1632 | } | |
62932df8 | 1633 | mutex_unlock(&cm->open_mutex); |
1da177e4 LT |
1634 | } |
1635 | ||
1636 | /* | |
1637 | */ | |
1638 | ||
2cbdb686 | 1639 | static int snd_cmipci_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 1640 | { |
2cbdb686 TI |
1641 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1642 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1643 | int err; |
1644 | ||
43795882 TI |
1645 | err = open_device_check(cm, CM_OPEN_PLAYBACK, substream); |
1646 | if (err < 0) | |
1da177e4 LT |
1647 | return err; |
1648 | runtime->hw = snd_cmipci_playback; | |
8992e18d CL |
1649 | if (cm->chip_version == 68) { |
1650 | runtime->hw.rates |= SNDRV_PCM_RATE_88200 | | |
1651 | SNDRV_PCM_RATE_96000; | |
1652 | runtime->hw.rate_max = 96000; | |
755c48ab TB |
1653 | } else if (cm->chip_version == 55) { |
1654 | err = snd_pcm_hw_constraint_list(runtime, 0, | |
1655 | SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); | |
1656 | if (err < 0) | |
1657 | return err; | |
1658 | runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; | |
1659 | runtime->hw.rate_max = 128000; | |
8992e18d | 1660 | } |
1da177e4 LT |
1661 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); |
1662 | cm->dig_pcm_status = cm->dig_status; | |
1663 | return 0; | |
1664 | } | |
1665 | ||
2cbdb686 | 1666 | static int snd_cmipci_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 1667 | { |
2cbdb686 TI |
1668 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1669 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1670 | int err; |
1671 | ||
43795882 TI |
1672 | err = open_device_check(cm, CM_OPEN_CAPTURE, substream); |
1673 | if (err < 0) | |
1da177e4 LT |
1674 | return err; |
1675 | runtime->hw = snd_cmipci_capture; | |
1676 | if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording | |
1677 | runtime->hw.rate_min = 41000; | |
1678 | runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; | |
755c48ab TB |
1679 | } else if (cm->chip_version == 55) { |
1680 | err = snd_pcm_hw_constraint_list(runtime, 0, | |
1681 | SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); | |
1682 | if (err < 0) | |
1683 | return err; | |
1684 | runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; | |
1685 | runtime->hw.rate_max = 128000; | |
1da177e4 LT |
1686 | } |
1687 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); | |
1688 | return 0; | |
1689 | } | |
1690 | ||
2cbdb686 | 1691 | static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream) |
1da177e4 | 1692 | { |
2cbdb686 TI |
1693 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1694 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1695 | int err; |
1696 | ||
43795882 TI |
1697 | /* use channel B */ |
1698 | err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream); | |
1699 | if (err < 0) | |
1da177e4 LT |
1700 | return err; |
1701 | runtime->hw = snd_cmipci_playback2; | |
62932df8 | 1702 | mutex_lock(&cm->open_mutex); |
1da177e4 LT |
1703 | if (! cm->opened[CM_CH_PLAY]) { |
1704 | if (cm->can_multi_ch) { | |
1705 | runtime->hw.channels_max = cm->max_channels; | |
1706 | if (cm->max_channels == 4) | |
1707 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); | |
1708 | else if (cm->max_channels == 6) | |
1709 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); | |
1710 | else if (cm->max_channels == 8) | |
1711 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); | |
1712 | } | |
1da177e4 | 1713 | } |
62932df8 | 1714 | mutex_unlock(&cm->open_mutex); |
22a22f5a CL |
1715 | if (cm->chip_version == 68) { |
1716 | runtime->hw.rates |= SNDRV_PCM_RATE_88200 | | |
1717 | SNDRV_PCM_RATE_96000; | |
1718 | runtime->hw.rate_max = 96000; | |
755c48ab TB |
1719 | } else if (cm->chip_version == 55) { |
1720 | err = snd_pcm_hw_constraint_list(runtime, 0, | |
1721 | SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); | |
1722 | if (err < 0) | |
1723 | return err; | |
1724 | runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; | |
1725 | runtime->hw.rate_max = 128000; | |
22a22f5a CL |
1726 | } |
1727 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); | |
1da177e4 LT |
1728 | return 0; |
1729 | } | |
1730 | ||
2cbdb686 | 1731 | static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 | 1732 | { |
2cbdb686 TI |
1733 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1734 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1735 | int err; |
1736 | ||
43795882 TI |
1737 | /* use channel A */ |
1738 | err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream); | |
1739 | if (err < 0) | |
1da177e4 LT |
1740 | return err; |
1741 | if (cm->can_ac3_hw) { | |
1742 | runtime->hw = snd_cmipci_playback_spdif; | |
57bd68b8 | 1743 | if (cm->chip_version >= 37) { |
1da177e4 | 1744 | runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; |
57bd68b8 CL |
1745 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); |
1746 | } | |
755c48ab | 1747 | if (cm->can_96k) { |
8992e18d CL |
1748 | runtime->hw.rates |= SNDRV_PCM_RATE_88200 | |
1749 | SNDRV_PCM_RATE_96000; | |
1750 | runtime->hw.rate_max = 96000; | |
1751 | } | |
1da177e4 LT |
1752 | } else { |
1753 | runtime->hw = snd_cmipci_playback_iec958_subframe; | |
1754 | } | |
1755 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); | |
1756 | cm->dig_pcm_status = cm->dig_status; | |
1757 | return 0; | |
1758 | } | |
1759 | ||
2cbdb686 | 1760 | static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 | 1761 | { |
2cbdb686 TI |
1762 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1763 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1764 | int err; |
1765 | ||
43795882 TI |
1766 | /* use channel B */ |
1767 | err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream); | |
1768 | if (err < 0) | |
1da177e4 LT |
1769 | return err; |
1770 | runtime->hw = snd_cmipci_capture_spdif; | |
755c48ab TB |
1771 | if (cm->can_96k && !(cm->chip_version == 68)) { |
1772 | runtime->hw.rates |= SNDRV_PCM_RATE_88200 | | |
1773 | SNDRV_PCM_RATE_96000; | |
1774 | runtime->hw.rate_max = 96000; | |
1775 | } | |
1da177e4 LT |
1776 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); |
1777 | return 0; | |
1778 | } | |
1779 | ||
1780 | ||
1781 | /* | |
1782 | */ | |
1783 | ||
2cbdb686 | 1784 | static int snd_cmipci_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 1785 | { |
2cbdb686 | 1786 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1787 | close_device_check(cm, CM_OPEN_PLAYBACK); |
1788 | return 0; | |
1789 | } | |
1790 | ||
2cbdb686 | 1791 | static int snd_cmipci_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1792 | { |
2cbdb686 | 1793 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1794 | close_device_check(cm, CM_OPEN_CAPTURE); |
1795 | return 0; | |
1796 | } | |
1797 | ||
2cbdb686 | 1798 | static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream) |
1da177e4 | 1799 | { |
2cbdb686 | 1800 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1801 | close_device_check(cm, CM_OPEN_PLAYBACK2); |
1802 | close_device_check(cm, CM_OPEN_PLAYBACK_MULTI); | |
1803 | return 0; | |
1804 | } | |
1805 | ||
2cbdb686 | 1806 | static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream) |
1da177e4 | 1807 | { |
2cbdb686 | 1808 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1809 | close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK); |
1810 | return 0; | |
1811 | } | |
1812 | ||
2cbdb686 | 1813 | static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream) |
1da177e4 | 1814 | { |
2cbdb686 | 1815 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1816 | close_device_check(cm, CM_OPEN_SPDIF_CAPTURE); |
1817 | return 0; | |
1818 | } | |
1819 | ||
1820 | ||
1821 | /* | |
1822 | */ | |
1823 | ||
6769e988 | 1824 | static const struct snd_pcm_ops snd_cmipci_playback_ops = { |
1da177e4 LT |
1825 | .open = snd_cmipci_playback_open, |
1826 | .close = snd_cmipci_playback_close, | |
1da177e4 LT |
1827 | .hw_free = snd_cmipci_playback_hw_free, |
1828 | .prepare = snd_cmipci_playback_prepare, | |
1829 | .trigger = snd_cmipci_playback_trigger, | |
1830 | .pointer = snd_cmipci_playback_pointer, | |
1831 | }; | |
1832 | ||
6769e988 | 1833 | static const struct snd_pcm_ops snd_cmipci_capture_ops = { |
1da177e4 LT |
1834 | .open = snd_cmipci_capture_open, |
1835 | .close = snd_cmipci_capture_close, | |
1da177e4 LT |
1836 | .prepare = snd_cmipci_capture_prepare, |
1837 | .trigger = snd_cmipci_capture_trigger, | |
1838 | .pointer = snd_cmipci_capture_pointer, | |
1839 | }; | |
1840 | ||
6769e988 | 1841 | static const struct snd_pcm_ops snd_cmipci_playback2_ops = { |
1da177e4 LT |
1842 | .open = snd_cmipci_playback2_open, |
1843 | .close = snd_cmipci_playback2_close, | |
1da177e4 | 1844 | .hw_params = snd_cmipci_playback2_hw_params, |
c36fd8c3 | 1845 | .hw_free = snd_cmipci_playback2_hw_free, |
1da177e4 LT |
1846 | .prepare = snd_cmipci_capture_prepare, /* channel B */ |
1847 | .trigger = snd_cmipci_capture_trigger, /* channel B */ | |
1848 | .pointer = snd_cmipci_capture_pointer, /* channel B */ | |
1849 | }; | |
1850 | ||
6769e988 | 1851 | static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = { |
1da177e4 LT |
1852 | .open = snd_cmipci_playback_spdif_open, |
1853 | .close = snd_cmipci_playback_spdif_close, | |
1da177e4 LT |
1854 | .hw_free = snd_cmipci_playback_hw_free, |
1855 | .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */ | |
1856 | .trigger = snd_cmipci_playback_trigger, | |
1857 | .pointer = snd_cmipci_playback_pointer, | |
1858 | }; | |
1859 | ||
6769e988 | 1860 | static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = { |
1da177e4 LT |
1861 | .open = snd_cmipci_capture_spdif_open, |
1862 | .close = snd_cmipci_capture_spdif_close, | |
1da177e4 LT |
1863 | .hw_free = snd_cmipci_capture_spdif_hw_free, |
1864 | .prepare = snd_cmipci_capture_spdif_prepare, | |
1865 | .trigger = snd_cmipci_capture_trigger, | |
1866 | .pointer = snd_cmipci_capture_pointer, | |
1867 | }; | |
1868 | ||
1869 | ||
1870 | /* | |
1871 | */ | |
1872 | ||
e23e7a14 | 1873 | static int snd_cmipci_pcm_new(struct cmipci *cm, int device) |
1da177e4 | 1874 | { |
2cbdb686 | 1875 | struct snd_pcm *pcm; |
1da177e4 LT |
1876 | int err; |
1877 | ||
1878 | err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); | |
1879 | if (err < 0) | |
1880 | return err; | |
1881 | ||
1882 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); | |
1883 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); | |
1884 | ||
1885 | pcm->private_data = cm; | |
1da177e4 LT |
1886 | pcm->info_flags = 0; |
1887 | strcpy(pcm->name, "C-Media PCI DAC/ADC"); | |
1888 | cm->pcm = pcm; | |
1889 | ||
d841e2e8 TI |
1890 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
1891 | &cm->pci->dev, 64*1024, 128*1024); | |
1da177e4 LT |
1892 | |
1893 | return 0; | |
1894 | } | |
1895 | ||
e23e7a14 | 1896 | static int snd_cmipci_pcm2_new(struct cmipci *cm, int device) |
1da177e4 | 1897 | { |
2cbdb686 | 1898 | struct snd_pcm *pcm; |
1da177e4 LT |
1899 | int err; |
1900 | ||
1901 | err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); | |
1902 | if (err < 0) | |
1903 | return err; | |
1904 | ||
1905 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); | |
1906 | ||
1907 | pcm->private_data = cm; | |
1da177e4 LT |
1908 | pcm->info_flags = 0; |
1909 | strcpy(pcm->name, "C-Media PCI 2nd DAC"); | |
1910 | cm->pcm2 = pcm; | |
1911 | ||
d841e2e8 TI |
1912 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
1913 | &cm->pci->dev, 64*1024, 128*1024); | |
1da177e4 LT |
1914 | |
1915 | return 0; | |
1916 | } | |
1917 | ||
e23e7a14 | 1918 | static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device) |
1da177e4 | 1919 | { |
2cbdb686 | 1920 | struct snd_pcm *pcm; |
1da177e4 LT |
1921 | int err; |
1922 | ||
1923 | err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); | |
1924 | if (err < 0) | |
1925 | return err; | |
1926 | ||
1927 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); | |
1928 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); | |
1929 | ||
1930 | pcm->private_data = cm; | |
1da177e4 LT |
1931 | pcm->info_flags = 0; |
1932 | strcpy(pcm->name, "C-Media PCI IEC958"); | |
1933 | cm->pcm_spdif = pcm; | |
1934 | ||
d841e2e8 TI |
1935 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
1936 | &cm->pci->dev, 64*1024, 128*1024); | |
1da177e4 | 1937 | |
f49921b8 TI |
1938 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, |
1939 | snd_pcm_alt_chmaps, cm->max_channels, 0, | |
1940 | NULL); | |
1941 | if (err < 0) | |
1942 | return err; | |
1943 | ||
1da177e4 LT |
1944 | return 0; |
1945 | } | |
1946 | ||
1947 | /* | |
1948 | * mixer interface: | |
1949 | * - CM8338/8738 has a compatible mixer interface with SB16, but | |
1950 | * lack of some elements like tone control, i/o gain and AGC. | |
1951 | * - Access to native registers: | |
1952 | * - A 3D switch | |
1953 | * - Output mute switches | |
1954 | */ | |
1955 | ||
2cbdb686 | 1956 | static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data) |
1da177e4 LT |
1957 | { |
1958 | outb(idx, s->iobase + CM_REG_SB16_ADDR); | |
1959 | outb(data, s->iobase + CM_REG_SB16_DATA); | |
1960 | } | |
1961 | ||
2cbdb686 | 1962 | static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx) |
1da177e4 LT |
1963 | { |
1964 | unsigned char v; | |
1965 | ||
1966 | outb(idx, s->iobase + CM_REG_SB16_ADDR); | |
1967 | v = inb(s->iobase + CM_REG_SB16_DATA); | |
1968 | return v; | |
1969 | } | |
1970 | ||
1971 | /* | |
1972 | * general mixer element | |
1973 | */ | |
2cbdb686 | 1974 | struct cmipci_sb_reg { |
1da177e4 LT |
1975 | unsigned int left_reg, right_reg; |
1976 | unsigned int left_shift, right_shift; | |
1977 | unsigned int mask; | |
1978 | unsigned int invert: 1; | |
1979 | unsigned int stereo: 1; | |
2cbdb686 | 1980 | }; |
1da177e4 LT |
1981 | |
1982 | #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ | |
1983 | ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) | |
1984 | ||
1985 | #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ | |
1986 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1987 | .info = snd_cmipci_info_volume, \ | |
1988 | .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \ | |
1989 | .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ | |
1990 | } | |
1991 | ||
1992 | #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) | |
1993 | #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) | |
1994 | #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1) | |
1995 | #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0) | |
1996 | ||
2cbdb686 | 1997 | static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val) |
1da177e4 LT |
1998 | { |
1999 | r->left_reg = val & 0xff; | |
2000 | r->right_reg = (val >> 8) & 0xff; | |
2001 | r->left_shift = (val >> 16) & 0x07; | |
2002 | r->right_shift = (val >> 19) & 0x07; | |
2003 | r->invert = (val >> 22) & 1; | |
2004 | r->stereo = (val >> 23) & 1; | |
2005 | r->mask = (val >> 24) & 0xff; | |
2006 | } | |
2007 | ||
2cbdb686 TI |
2008 | static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol, |
2009 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 | 2010 | { |
2cbdb686 | 2011 | struct cmipci_sb_reg reg; |
1da177e4 LT |
2012 | |
2013 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2014 | uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2015 | uinfo->count = reg.stereo + 1; | |
2016 | uinfo->value.integer.min = 0; | |
2017 | uinfo->value.integer.max = reg.mask; | |
2018 | return 0; | |
2019 | } | |
2020 | ||
2cbdb686 TI |
2021 | static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol, |
2022 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2023 | { |
2cbdb686 TI |
2024 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2025 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2026 | int val; |
2027 | ||
2028 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2029 | spin_lock_irq(&cm->reg_lock); | |
2030 | val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; | |
2031 | if (reg.invert) | |
2032 | val = reg.mask - val; | |
2033 | ucontrol->value.integer.value[0] = val; | |
2034 | if (reg.stereo) { | |
2035 | val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; | |
2036 | if (reg.invert) | |
2037 | val = reg.mask - val; | |
9603cded | 2038 | ucontrol->value.integer.value[1] = val; |
1da177e4 LT |
2039 | } |
2040 | spin_unlock_irq(&cm->reg_lock); | |
2041 | return 0; | |
2042 | } | |
2043 | ||
2cbdb686 TI |
2044 | static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol, |
2045 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2046 | { |
2cbdb686 TI |
2047 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2048 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2049 | int change; |
2050 | int left, right, oleft, oright; | |
2051 | ||
2052 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2053 | left = ucontrol->value.integer.value[0] & reg.mask; | |
2054 | if (reg.invert) | |
2055 | left = reg.mask - left; | |
2056 | left <<= reg.left_shift; | |
2057 | if (reg.stereo) { | |
2058 | right = ucontrol->value.integer.value[1] & reg.mask; | |
2059 | if (reg.invert) | |
2060 | right = reg.mask - right; | |
2061 | right <<= reg.right_shift; | |
2062 | } else | |
2063 | right = 0; | |
2064 | spin_lock_irq(&cm->reg_lock); | |
2065 | oleft = snd_cmipci_mixer_read(cm, reg.left_reg); | |
2066 | left |= oleft & ~(reg.mask << reg.left_shift); | |
2067 | change = left != oleft; | |
2068 | if (reg.stereo) { | |
2069 | if (reg.left_reg != reg.right_reg) { | |
2070 | snd_cmipci_mixer_write(cm, reg.left_reg, left); | |
2071 | oright = snd_cmipci_mixer_read(cm, reg.right_reg); | |
2072 | } else | |
2073 | oright = left; | |
2074 | right |= oright & ~(reg.mask << reg.right_shift); | |
2075 | change |= right != oright; | |
2076 | snd_cmipci_mixer_write(cm, reg.right_reg, right); | |
2077 | } else | |
2078 | snd_cmipci_mixer_write(cm, reg.left_reg, left); | |
2079 | spin_unlock_irq(&cm->reg_lock); | |
2080 | return change; | |
2081 | } | |
2082 | ||
2083 | /* | |
2084 | * input route (left,right) -> (left,right) | |
2085 | */ | |
2086 | #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \ | |
2087 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2088 | .info = snd_cmipci_info_input_sw, \ | |
2089 | .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \ | |
2090 | .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ | |
2091 | } | |
2092 | ||
2cbdb686 TI |
2093 | static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol, |
2094 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
2095 | { |
2096 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
2097 | uinfo->count = 4; | |
2098 | uinfo->value.integer.min = 0; | |
2099 | uinfo->value.integer.max = 1; | |
2100 | return 0; | |
2101 | } | |
2102 | ||
2cbdb686 TI |
2103 | static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol, |
2104 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2105 | { |
2cbdb686 TI |
2106 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2107 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2108 | int val1, val2; |
2109 | ||
2110 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2111 | spin_lock_irq(&cm->reg_lock); | |
2112 | val1 = snd_cmipci_mixer_read(cm, reg.left_reg); | |
2113 | val2 = snd_cmipci_mixer_read(cm, reg.right_reg); | |
2114 | spin_unlock_irq(&cm->reg_lock); | |
2115 | ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; | |
2116 | ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; | |
2117 | ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; | |
2118 | ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; | |
2119 | return 0; | |
2120 | } | |
2121 | ||
2cbdb686 TI |
2122 | static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol, |
2123 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2124 | { |
2cbdb686 TI |
2125 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2126 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2127 | int change; |
2128 | int val1, val2, oval1, oval2; | |
2129 | ||
2130 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2131 | spin_lock_irq(&cm->reg_lock); | |
2132 | oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); | |
2133 | oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); | |
2134 | val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); | |
2135 | val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); | |
2136 | val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; | |
2137 | val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; | |
2138 | val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; | |
2139 | val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; | |
2140 | change = val1 != oval1 || val2 != oval2; | |
2141 | snd_cmipci_mixer_write(cm, reg.left_reg, val1); | |
2142 | snd_cmipci_mixer_write(cm, reg.right_reg, val2); | |
2143 | spin_unlock_irq(&cm->reg_lock); | |
2144 | return change; | |
2145 | } | |
2146 | ||
2147 | /* | |
2148 | * native mixer switches/volumes | |
2149 | */ | |
2150 | ||
2151 | #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ | |
2152 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2153 | .info = snd_cmipci_info_native_mixer, \ | |
2154 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
2155 | .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ | |
2156 | } | |
2157 | ||
2158 | #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ | |
2159 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2160 | .info = snd_cmipci_info_native_mixer, \ | |
2161 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
2162 | .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ | |
2163 | } | |
2164 | ||
2165 | #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ | |
2166 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2167 | .info = snd_cmipci_info_native_mixer, \ | |
2168 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
2169 | .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ | |
2170 | } | |
2171 | ||
2172 | #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ | |
2173 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
2174 | .info = snd_cmipci_info_native_mixer, \ | |
2175 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
2176 | .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ | |
2177 | } | |
2178 | ||
2cbdb686 TI |
2179 | static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol, |
2180 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 | 2181 | { |
2cbdb686 | 2182 | struct cmipci_sb_reg reg; |
1da177e4 LT |
2183 | |
2184 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2185 | uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2186 | uinfo->count = reg.stereo + 1; | |
2187 | uinfo->value.integer.min = 0; | |
2188 | uinfo->value.integer.max = reg.mask; | |
2189 | return 0; | |
2190 | ||
2191 | } | |
2192 | ||
2cbdb686 TI |
2193 | static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol, |
2194 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2195 | { |
2cbdb686 TI |
2196 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2197 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2198 | unsigned char oreg, val; |
2199 | ||
2200 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2201 | spin_lock_irq(&cm->reg_lock); | |
2202 | oreg = inb(cm->iobase + reg.left_reg); | |
2203 | val = (oreg >> reg.left_shift) & reg.mask; | |
2204 | if (reg.invert) | |
2205 | val = reg.mask - val; | |
2206 | ucontrol->value.integer.value[0] = val; | |
2207 | if (reg.stereo) { | |
2208 | val = (oreg >> reg.right_shift) & reg.mask; | |
2209 | if (reg.invert) | |
2210 | val = reg.mask - val; | |
2211 | ucontrol->value.integer.value[1] = val; | |
2212 | } | |
2213 | spin_unlock_irq(&cm->reg_lock); | |
2214 | return 0; | |
2215 | } | |
2216 | ||
2cbdb686 TI |
2217 | static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol, |
2218 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2219 | { |
2cbdb686 TI |
2220 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2221 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2222 | unsigned char oreg, nreg, val; |
2223 | ||
2224 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2225 | spin_lock_irq(&cm->reg_lock); | |
2226 | oreg = inb(cm->iobase + reg.left_reg); | |
2227 | val = ucontrol->value.integer.value[0] & reg.mask; | |
2228 | if (reg.invert) | |
2229 | val = reg.mask - val; | |
2230 | nreg = oreg & ~(reg.mask << reg.left_shift); | |
2231 | nreg |= (val << reg.left_shift); | |
2232 | if (reg.stereo) { | |
2233 | val = ucontrol->value.integer.value[1] & reg.mask; | |
2234 | if (reg.invert) | |
2235 | val = reg.mask - val; | |
2236 | nreg &= ~(reg.mask << reg.right_shift); | |
2237 | nreg |= (val << reg.right_shift); | |
2238 | } | |
2239 | outb(nreg, cm->iobase + reg.left_reg); | |
2240 | spin_unlock_irq(&cm->reg_lock); | |
2241 | return (nreg != oreg); | |
2242 | } | |
2243 | ||
2244 | /* | |
2245 | * special case - check mixer sensitivity | |
2246 | */ | |
2cbdb686 TI |
2247 | static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol, |
2248 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2249 | { |
2cbdb686 | 2250 | //struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2251 | return snd_cmipci_get_native_mixer(kcontrol, ucontrol); |
2252 | } | |
2253 | ||
2cbdb686 TI |
2254 | static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol, |
2255 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2256 | { |
2cbdb686 | 2257 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2258 | if (cm->mixer_insensitive) { |
2259 | /* ignored */ | |
2260 | return 0; | |
2261 | } | |
2262 | return snd_cmipci_put_native_mixer(kcontrol, ucontrol); | |
2263 | } | |
2264 | ||
2265 | ||
b4e5e707 | 2266 | static const struct snd_kcontrol_new snd_cmipci_mixers[] = { |
1da177e4 LT |
2267 | CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), |
2268 | CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), | |
2269 | CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), | |
2270 | //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), | |
2271 | { /* switch with sensitivity */ | |
2272 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2273 | .name = "PCM Playback Switch", | |
2274 | .info = snd_cmipci_info_native_mixer, | |
2275 | .get = snd_cmipci_get_native_mixer_sensitive, | |
2276 | .put = snd_cmipci_put_native_mixer_sensitive, | |
2277 | .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), | |
2278 | }, | |
2279 | CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), | |
2280 | CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), | |
2281 | CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), | |
2282 | CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), | |
2283 | CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), | |
2284 | CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), | |
2285 | CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), | |
2286 | CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), | |
2287 | CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), | |
2288 | CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), | |
2289 | CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), | |
2290 | CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), | |
2291 | CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), | |
d355c82a | 2292 | CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), |
1da177e4 LT |
2293 | CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), |
2294 | CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), | |
2295 | CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), | |
2eff7ec8 | 2296 | CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), |
1da177e4 | 2297 | CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), |
2eff7ec8 TI |
2298 | CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), |
2299 | CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), | |
d355c82a | 2300 | CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), |
2eff7ec8 | 2301 | CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), |
1da177e4 LT |
2302 | }; |
2303 | ||
2304 | /* | |
2305 | * other switches | |
2306 | */ | |
2307 | ||
2cbdb686 | 2308 | struct cmipci_switch_args { |
1da177e4 LT |
2309 | int reg; /* register index */ |
2310 | unsigned int mask; /* mask bits */ | |
2311 | unsigned int mask_on; /* mask bits to turn on */ | |
2312 | unsigned int is_byte: 1; /* byte access? */ | |
2cbdb686 TI |
2313 | unsigned int ac3_sensitive: 1; /* access forbidden during |
2314 | * non-audio operation? | |
2315 | */ | |
2316 | }; | |
1da177e4 | 2317 | |
a5ce8890 | 2318 | #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info |
1da177e4 | 2319 | |
2cbdb686 TI |
2320 | static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, |
2321 | struct snd_ctl_elem_value *ucontrol, | |
2322 | struct cmipci_switch_args *args) | |
1da177e4 LT |
2323 | { |
2324 | unsigned int val; | |
2cbdb686 | 2325 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2326 | |
2327 | spin_lock_irq(&cm->reg_lock); | |
2328 | if (args->ac3_sensitive && cm->mixer_insensitive) { | |
2329 | ucontrol->value.integer.value[0] = 0; | |
2330 | spin_unlock_irq(&cm->reg_lock); | |
2331 | return 0; | |
2332 | } | |
2333 | if (args->is_byte) | |
2334 | val = inb(cm->iobase + args->reg); | |
2335 | else | |
2336 | val = snd_cmipci_read(cm, args->reg); | |
2337 | ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; | |
2338 | spin_unlock_irq(&cm->reg_lock); | |
2339 | return 0; | |
2340 | } | |
2341 | ||
2cbdb686 TI |
2342 | static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, |
2343 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2344 | { |
2cbdb686 TI |
2345 | struct cmipci_switch_args *args; |
2346 | args = (struct cmipci_switch_args *)kcontrol->private_value; | |
da3cec35 TI |
2347 | if (snd_BUG_ON(!args)) |
2348 | return -EINVAL; | |
1da177e4 LT |
2349 | return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args); |
2350 | } | |
2351 | ||
2cbdb686 TI |
2352 | static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, |
2353 | struct snd_ctl_elem_value *ucontrol, | |
2354 | struct cmipci_switch_args *args) | |
1da177e4 LT |
2355 | { |
2356 | unsigned int val; | |
2357 | int change; | |
2cbdb686 | 2358 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2359 | |
2360 | spin_lock_irq(&cm->reg_lock); | |
2361 | if (args->ac3_sensitive && cm->mixer_insensitive) { | |
2362 | /* ignored */ | |
2363 | spin_unlock_irq(&cm->reg_lock); | |
2364 | return 0; | |
2365 | } | |
2366 | if (args->is_byte) | |
2367 | val = inb(cm->iobase + args->reg); | |
2368 | else | |
2369 | val = snd_cmipci_read(cm, args->reg); | |
8c670714 TB |
2370 | change = (val & args->mask) != (ucontrol->value.integer.value[0] ? |
2371 | args->mask_on : (args->mask & ~args->mask_on)); | |
1da177e4 LT |
2372 | if (change) { |
2373 | val &= ~args->mask; | |
2374 | if (ucontrol->value.integer.value[0]) | |
2375 | val |= args->mask_on; | |
2376 | else | |
2377 | val |= (args->mask & ~args->mask_on); | |
2378 | if (args->is_byte) | |
2379 | outb((unsigned char)val, cm->iobase + args->reg); | |
2380 | else | |
2381 | snd_cmipci_write(cm, args->reg, val); | |
2382 | } | |
2383 | spin_unlock_irq(&cm->reg_lock); | |
2384 | return change; | |
2385 | } | |
2386 | ||
2cbdb686 TI |
2387 | static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, |
2388 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2389 | { |
2cbdb686 TI |
2390 | struct cmipci_switch_args *args; |
2391 | args = (struct cmipci_switch_args *)kcontrol->private_value; | |
da3cec35 TI |
2392 | if (snd_BUG_ON(!args)) |
2393 | return -EINVAL; | |
1da177e4 LT |
2394 | return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args); |
2395 | } | |
2396 | ||
2397 | #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \ | |
2cbdb686 | 2398 | static struct cmipci_switch_args cmipci_switch_arg_##sname = { \ |
1da177e4 LT |
2399 | .reg = xreg, \ |
2400 | .mask = xmask, \ | |
2401 | .mask_on = xmask_on, \ | |
2402 | .is_byte = xis_byte, \ | |
2403 | .ac3_sensitive = xac3, \ | |
2404 | } | |
2405 | ||
2406 | #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \ | |
2407 | DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3) | |
2408 | ||
2409 | #if 0 /* these will be controlled in pcm device */ | |
2410 | DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0); | |
2411 | DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0); | |
2412 | #endif | |
2413 | DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0); | |
2414 | DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0); | |
2415 | DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0); | |
2416 | DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1); | |
2417 | DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0); | |
2418 | DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0); | |
2419 | DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1); | |
2420 | DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */ | |
2421 | // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1); | |
2422 | DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1); | |
2423 | DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0); | |
2424 | /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */ | |
2425 | DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0); | |
2426 | DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0); | |
2427 | #if CM_CH_PLAY == 1 | |
2428 | DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */ | |
2429 | #else | |
2430 | DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0); | |
2431 | #endif | |
2432 | DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); | |
a839a33d CL |
2433 | // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0); |
2434 | // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0); | |
1da177e4 LT |
2435 | // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ |
2436 | DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); | |
2437 | ||
2438 | #define DEFINE_SWITCH(sname, stype, sarg) \ | |
2439 | { .name = sname, \ | |
2440 | .iface = stype, \ | |
2441 | .info = snd_cmipci_uswitch_info, \ | |
2442 | .get = snd_cmipci_uswitch_get, \ | |
2443 | .put = snd_cmipci_uswitch_put, \ | |
2444 | .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\ | |
2445 | } | |
2446 | ||
2447 | #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg) | |
2448 | #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg) | |
2449 | ||
2450 | ||
2451 | /* | |
2452 | * callbacks for spdif output switch | |
2453 | * needs toggle two registers.. | |
2454 | */ | |
2cbdb686 TI |
2455 | static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol, |
2456 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 LT |
2457 | { |
2458 | int changed; | |
2459 | changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); | |
2460 | changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); | |
2461 | return changed; | |
2462 | } | |
2463 | ||
2cbdb686 TI |
2464 | static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol, |
2465 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2466 | { |
2cbdb686 | 2467 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2468 | int changed; |
2469 | changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); | |
2470 | changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); | |
2471 | if (changed) { | |
2472 | if (ucontrol->value.integer.value[0]) { | |
2473 | if (chip->spdif_playback_avail) | |
2474 | snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
2475 | } else { | |
2476 | if (chip->spdif_playback_avail) | |
2477 | snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
2478 | } | |
2479 | } | |
2480 | chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; | |
2481 | return changed; | |
2482 | } | |
2483 | ||
2484 | ||
2cbdb686 TI |
2485 | static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol, |
2486 | struct snd_ctl_elem_info *uinfo) | |
01d25d46 | 2487 | { |
2cbdb686 | 2488 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
60c4ce4a CL |
2489 | static const char *const texts[3] = { |
2490 | "Line-In", "Rear Output", "Bass Output" | |
2491 | }; | |
2492 | ||
2493 | return snd_ctl_enum_info(uinfo, 1, | |
2494 | cm->chip_version >= 39 ? 3 : 2, texts); | |
01d25d46 TI |
2495 | } |
2496 | ||
2cbdb686 | 2497 | static inline unsigned int get_line_in_mode(struct cmipci *cm) |
01d25d46 TI |
2498 | { |
2499 | unsigned int val; | |
2500 | if (cm->chip_version >= 39) { | |
2501 | val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); | |
a839a33d | 2502 | if (val & (CM_CENTR2LIN | CM_BASE2LIN)) |
01d25d46 TI |
2503 | return 2; |
2504 | } | |
2505 | val = snd_cmipci_read_b(cm, CM_REG_MIXER1); | |
a839a33d | 2506 | if (val & CM_REAR2LIN) |
01d25d46 TI |
2507 | return 1; |
2508 | return 0; | |
2509 | } | |
2510 | ||
2cbdb686 TI |
2511 | static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol, |
2512 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2513 | { |
2cbdb686 | 2514 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2515 | |
2516 | spin_lock_irq(&cm->reg_lock); | |
2517 | ucontrol->value.enumerated.item[0] = get_line_in_mode(cm); | |
2518 | spin_unlock_irq(&cm->reg_lock); | |
2519 | return 0; | |
2520 | } | |
2521 | ||
2cbdb686 TI |
2522 | static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol, |
2523 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2524 | { |
2cbdb686 | 2525 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2526 | int change; |
2527 | ||
2528 | spin_lock_irq(&cm->reg_lock); | |
2529 | if (ucontrol->value.enumerated.item[0] == 2) | |
a839a33d | 2530 | change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN); |
01d25d46 | 2531 | else |
a839a33d | 2532 | change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN); |
01d25d46 | 2533 | if (ucontrol->value.enumerated.item[0] == 1) |
a839a33d | 2534 | change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN); |
01d25d46 | 2535 | else |
a839a33d | 2536 | change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN); |
01d25d46 TI |
2537 | spin_unlock_irq(&cm->reg_lock); |
2538 | return change; | |
2539 | } | |
2540 | ||
2cbdb686 TI |
2541 | static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol, |
2542 | struct snd_ctl_elem_info *uinfo) | |
01d25d46 | 2543 | { |
60c4ce4a CL |
2544 | static const char *const texts[2] = { "Mic-In", "Center/LFE Output" }; |
2545 | ||
2546 | return snd_ctl_enum_info(uinfo, 1, 2, texts); | |
01d25d46 TI |
2547 | } |
2548 | ||
2cbdb686 TI |
2549 | static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol, |
2550 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2551 | { |
2cbdb686 | 2552 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2553 | /* same bit as spdi_phase */ |
2554 | spin_lock_irq(&cm->reg_lock); | |
2555 | ucontrol->value.enumerated.item[0] = | |
2556 | (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0; | |
2557 | spin_unlock_irq(&cm->reg_lock); | |
2558 | return 0; | |
2559 | } | |
2560 | ||
2cbdb686 TI |
2561 | static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol, |
2562 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2563 | { |
2cbdb686 | 2564 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2565 | int change; |
2566 | ||
2567 | spin_lock_irq(&cm->reg_lock); | |
2568 | if (ucontrol->value.enumerated.item[0]) | |
2569 | change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); | |
2570 | else | |
2571 | change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); | |
2572 | spin_unlock_irq(&cm->reg_lock); | |
2573 | return change; | |
2574 | } | |
2575 | ||
1da177e4 | 2576 | /* both for CM8338/8738 */ |
b4e5e707 | 2577 | static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = { |
1da177e4 | 2578 | DEFINE_MIXER_SWITCH("Four Channel Mode", fourch), |
01d25d46 TI |
2579 | { |
2580 | .name = "Line-In Mode", | |
2581 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2582 | .info = snd_cmipci_line_in_mode_info, | |
2583 | .get = snd_cmipci_line_in_mode_get, | |
2584 | .put = snd_cmipci_line_in_mode_put, | |
2585 | }, | |
1da177e4 LT |
2586 | }; |
2587 | ||
2588 | /* for non-multichannel chips */ | |
b4e5e707 | 2589 | static const struct snd_kcontrol_new snd_cmipci_nomulti_switch = |
1da177e4 LT |
2590 | DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac); |
2591 | ||
2592 | /* only for CM8738 */ | |
b4e5e707 | 2593 | static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = { |
1da177e4 LT |
2594 | #if 0 /* controlled in pcm device */ |
2595 | DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in), | |
2596 | DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out), | |
2597 | DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac), | |
2598 | #endif | |
2599 | // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), | |
2600 | { .name = "IEC958 Output Switch", | |
2601 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2602 | .info = snd_cmipci_uswitch_info, | |
2603 | .get = snd_cmipci_spdout_enable_get, | |
2604 | .put = snd_cmipci_spdout_enable_put, | |
2605 | }, | |
2606 | DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), | |
2607 | DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), | |
2608 | DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), | |
2609 | // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), | |
2610 | DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), | |
2611 | DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), | |
2612 | }; | |
2613 | ||
2614 | /* only for model 033/037 */ | |
b4e5e707 | 2615 | static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = { |
1da177e4 LT |
2616 | DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out), |
2617 | DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase), | |
2618 | DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1), | |
2619 | }; | |
2620 | ||
2621 | /* only for model 039 or later */ | |
b4e5e707 | 2622 | static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = { |
1da177e4 LT |
2623 | DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2), |
2624 | DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2), | |
01d25d46 TI |
2625 | { |
2626 | .name = "Mic-In Mode", | |
2627 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2628 | .info = snd_cmipci_mic_in_mode_info, | |
2629 | .get = snd_cmipci_mic_in_mode_get, | |
2630 | .put = snd_cmipci_mic_in_mode_put, | |
2631 | } | |
1da177e4 LT |
2632 | }; |
2633 | ||
2634 | /* card control switches */ | |
b4e5e707 | 2635 | static const struct snd_kcontrol_new snd_cmipci_modem_switch = |
69a07304 | 2636 | DEFINE_CARD_SWITCH("Modem", modem); |
1da177e4 LT |
2637 | |
2638 | ||
e23e7a14 | 2639 | static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device) |
1da177e4 | 2640 | { |
2cbdb686 | 2641 | struct snd_card *card; |
b4e5e707 | 2642 | const struct snd_kcontrol_new *sw; |
2cbdb686 | 2643 | struct snd_kcontrol *kctl; |
1da177e4 LT |
2644 | unsigned int idx; |
2645 | int err; | |
2646 | ||
da3cec35 TI |
2647 | if (snd_BUG_ON(!cm || !cm->card)) |
2648 | return -EINVAL; | |
1da177e4 LT |
2649 | |
2650 | card = cm->card; | |
2651 | ||
2652 | strcpy(card->mixername, "CMedia PCI"); | |
2653 | ||
2654 | spin_lock_irq(&cm->reg_lock); | |
2655 | snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ | |
2656 | spin_unlock_irq(&cm->reg_lock); | |
2657 | ||
2658 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { | |
2659 | if (cm->chip_version == 68) { // 8768 has no PCM volume | |
2660 | if (!strcmp(snd_cmipci_mixers[idx].name, | |
2661 | "PCM Playback Volume")) | |
2662 | continue; | |
2663 | } | |
43795882 TI |
2664 | err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm)); |
2665 | if (err < 0) | |
1da177e4 LT |
2666 | return err; |
2667 | } | |
2668 | ||
2669 | /* mixer switches */ | |
2670 | sw = snd_cmipci_mixer_switches; | |
2671 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { | |
2672 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2673 | if (err < 0) | |
2674 | return err; | |
2675 | } | |
2676 | if (! cm->can_multi_ch) { | |
2677 | err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); | |
2678 | if (err < 0) | |
2679 | return err; | |
2680 | } | |
2681 | if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || | |
2682 | cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { | |
2683 | sw = snd_cmipci_8738_mixer_switches; | |
2684 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { | |
2685 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2686 | if (err < 0) | |
2687 | return err; | |
2688 | } | |
2689 | if (cm->can_ac3_hw) { | |
43795882 | 2690 | kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm); |
f2f312ad | 2691 | kctl->id.device = pcm_spdif_device; |
43795882 TI |
2692 | err = snd_ctl_add(card, kctl); |
2693 | if (err < 0) | |
1da177e4 | 2694 | return err; |
43795882 | 2695 | kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm); |
f2f312ad | 2696 | kctl->id.device = pcm_spdif_device; |
43795882 TI |
2697 | err = snd_ctl_add(card, kctl); |
2698 | if (err < 0) | |
1da177e4 | 2699 | return err; |
43795882 | 2700 | kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm); |
f2f312ad | 2701 | kctl->id.device = pcm_spdif_device; |
43795882 TI |
2702 | err = snd_ctl_add(card, kctl); |
2703 | if (err < 0) | |
1da177e4 | 2704 | return err; |
1da177e4 LT |
2705 | } |
2706 | if (cm->chip_version <= 37) { | |
2707 | sw = snd_cmipci_old_mixer_switches; | |
2708 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { | |
2709 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2710 | if (err < 0) | |
2711 | return err; | |
2712 | } | |
2713 | } | |
2714 | } | |
2715 | if (cm->chip_version >= 39) { | |
2716 | sw = snd_cmipci_extra_mixer_switches; | |
2717 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { | |
2718 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2719 | if (err < 0) | |
2720 | return err; | |
2721 | } | |
2722 | } | |
2723 | ||
2724 | /* card switches */ | |
25543fa7 CL |
2725 | /* |
2726 | * newer chips don't have the register bits to force modem link | |
2727 | * detection; the bit that was FLINKON now mutes CH1 | |
2728 | */ | |
69a07304 CL |
2729 | if (cm->chip_version < 39) { |
2730 | err = snd_ctl_add(cm->card, | |
2731 | snd_ctl_new1(&snd_cmipci_modem_switch, cm)); | |
1da177e4 LT |
2732 | if (err < 0) |
2733 | return err; | |
2734 | } | |
2735 | ||
2736 | for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { | |
2cbdb686 | 2737 | struct snd_kcontrol *ctl; |
b6ba0aa4 | 2738 | ctl = snd_ctl_find_id_mixer(cm->card, cm_saved_mixer[idx].name); |
7dfa31ed | 2739 | if (ctl) |
1da177e4 LT |
2740 | cm->mixer_res_ctl[idx] = ctl; |
2741 | } | |
2742 | ||
2743 | return 0; | |
2744 | } | |
2745 | ||
2746 | ||
2747 | /* | |
2748 | * proc interface | |
2749 | */ | |
2750 | ||
2cbdb686 TI |
2751 | static void snd_cmipci_proc_read(struct snd_info_entry *entry, |
2752 | struct snd_info_buffer *buffer) | |
1da177e4 | 2753 | { |
2cbdb686 | 2754 | struct cmipci *cm = entry->private_data; |
54d030cc | 2755 | int i, v; |
1da177e4 | 2756 | |
54d030cc CL |
2757 | snd_iprintf(buffer, "%s\n", cm->card->longname); |
2758 | for (i = 0; i < 0x94; i++) { | |
2759 | if (i == 0x28) | |
2760 | i = 0x90; | |
2761 | v = inb(cm->iobase + i); | |
1da177e4 | 2762 | if (i % 4 == 0) |
54d030cc CL |
2763 | snd_iprintf(buffer, "\n%02x:", i); |
2764 | snd_iprintf(buffer, " %02x", v); | |
1da177e4 | 2765 | } |
54d030cc | 2766 | snd_iprintf(buffer, "\n"); |
1da177e4 LT |
2767 | } |
2768 | ||
e23e7a14 | 2769 | static void snd_cmipci_proc_init(struct cmipci *cm) |
1da177e4 | 2770 | { |
47f2769b | 2771 | snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read); |
1da177e4 | 2772 | } |
1da177e4 | 2773 | |
9baa3c34 | 2774 | static const struct pci_device_id snd_cmipci_ids[] = { |
28d27aae JP |
2775 | {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0}, |
2776 | {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0}, | |
2777 | {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0}, | |
2778 | {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0}, | |
2779 | {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0}, | |
1da177e4 LT |
2780 | {0,}, |
2781 | }; | |
2782 | ||
2783 | ||
2784 | /* | |
2785 | * check chip version and capabilities | |
2786 | * driver name is modified according to the chip model | |
2787 | */ | |
e23e7a14 | 2788 | static void query_chip(struct cmipci *cm) |
1da177e4 LT |
2789 | { |
2790 | unsigned int detect; | |
2791 | ||
2792 | /* check reg 0Ch, bit 24-31 */ | |
2793 | detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; | |
2794 | if (! detect) { | |
2795 | /* check reg 08h, bit 24-28 */ | |
2796 | detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; | |
133271fe CL |
2797 | switch (detect) { |
2798 | case 0: | |
1da177e4 | 2799 | cm->chip_version = 33; |
1da177e4 LT |
2800 | if (cm->do_soft_ac3) |
2801 | cm->can_ac3_sw = 1; | |
2802 | else | |
2803 | cm->can_ac3_hw = 1; | |
133271fe | 2804 | break; |
6935e688 | 2805 | case CM_CHIP_037: |
1da177e4 | 2806 | cm->chip_version = 37; |
1da177e4 | 2807 | cm->can_ac3_hw = 1; |
133271fe CL |
2808 | break; |
2809 | default: | |
2810 | cm->chip_version = 39; | |
2811 | cm->can_ac3_hw = 1; | |
2812 | break; | |
1da177e4 | 2813 | } |
133271fe | 2814 | cm->max_channels = 2; |
1da177e4 | 2815 | } else { |
133271fe | 2816 | if (detect & CM_CHIP_039) { |
1da177e4 LT |
2817 | cm->chip_version = 39; |
2818 | if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ | |
2819 | cm->max_channels = 6; | |
2820 | else | |
2821 | cm->max_channels = 4; | |
133271fe CL |
2822 | } else if (detect & CM_CHIP_8768) { |
2823 | cm->chip_version = 68; | |
2824 | cm->max_channels = 8; | |
755c48ab | 2825 | cm->can_96k = 1; |
1da177e4 | 2826 | } else { |
133271fe CL |
2827 | cm->chip_version = 55; |
2828 | cm->max_channels = 6; | |
755c48ab | 2829 | cm->can_96k = 1; |
1da177e4 | 2830 | } |
133271fe | 2831 | cm->can_ac3_hw = 1; |
133271fe | 2832 | cm->can_multi_ch = 1; |
1da177e4 LT |
2833 | } |
2834 | } | |
2835 | ||
2836 | #ifdef SUPPORT_JOYSTICK | |
e23e7a14 | 2837 | static int snd_cmipci_create_gameport(struct cmipci *cm, int dev) |
1da177e4 | 2838 | { |
5f3aca10 | 2839 | static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */ |
1da177e4 LT |
2840 | struct gameport *gp; |
2841 | struct resource *r = NULL; | |
2842 | int i, io_port = 0; | |
2843 | ||
2844 | if (joystick_port[dev] == 0) | |
2845 | return -ENODEV; | |
2846 | ||
2847 | if (joystick_port[dev] == 1) { /* auto-detect */ | |
2848 | for (i = 0; ports[i]; i++) { | |
2849 | io_port = ports[i]; | |
87e082ad TI |
2850 | r = devm_request_region(&cm->pci->dev, io_port, 1, |
2851 | "CMIPCI gameport"); | |
1da177e4 LT |
2852 | if (r) |
2853 | break; | |
2854 | } | |
2855 | } else { | |
2856 | io_port = joystick_port[dev]; | |
87e082ad TI |
2857 | r = devm_request_region(&cm->pci->dev, io_port, 1, |
2858 | "CMIPCI gameport"); | |
1da177e4 LT |
2859 | } |
2860 | ||
2861 | if (!r) { | |
40175bdb | 2862 | dev_warn(cm->card->dev, "cannot reserve joystick ports\n"); |
1da177e4 LT |
2863 | return -EBUSY; |
2864 | } | |
2865 | ||
2866 | cm->gameport = gp = gameport_allocate_port(); | |
2867 | if (!gp) { | |
40175bdb | 2868 | dev_err(cm->card->dev, "cannot allocate memory for gameport\n"); |
1da177e4 LT |
2869 | return -ENOMEM; |
2870 | } | |
2871 | gameport_set_name(gp, "C-Media Gameport"); | |
2872 | gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci)); | |
2873 | gameport_set_dev_parent(gp, &cm->pci->dev); | |
2874 | gp->io = io_port; | |
1da177e4 LT |
2875 | |
2876 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); | |
2877 | ||
2878 | gameport_register_port(cm->gameport); | |
2879 | ||
2880 | return 0; | |
2881 | } | |
2882 | ||
2cbdb686 | 2883 | static void snd_cmipci_free_gameport(struct cmipci *cm) |
1da177e4 LT |
2884 | { |
2885 | if (cm->gameport) { | |
1da177e4 LT |
2886 | gameport_unregister_port(cm->gameport); |
2887 | cm->gameport = NULL; | |
2888 | ||
2889 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); | |
1da177e4 LT |
2890 | } |
2891 | } | |
2892 | #else | |
2cbdb686 TI |
2893 | static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; } |
2894 | static inline void snd_cmipci_free_gameport(struct cmipci *cm) { } | |
1da177e4 LT |
2895 | #endif |
2896 | ||
87e082ad | 2897 | static void snd_cmipci_free(struct snd_card *card) |
1da177e4 | 2898 | { |
87e082ad | 2899 | struct cmipci *cm = card->private_data; |
1da177e4 | 2900 | |
87e082ad TI |
2901 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); |
2902 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); | |
2903 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ | |
2904 | snd_cmipci_ch_reset(cm, CM_CH_PLAY); | |
2905 | snd_cmipci_ch_reset(cm, CM_CH_CAPT); | |
2906 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ | |
2907 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); | |
1da177e4 | 2908 | |
87e082ad TI |
2909 | /* reset mixer */ |
2910 | snd_cmipci_mixer_write(cm, 0, 0); | |
1da177e4 LT |
2911 | |
2912 | snd_cmipci_free_gameport(cm); | |
1da177e4 LT |
2913 | } |
2914 | ||
e23e7a14 | 2915 | static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port) |
5747e540 CL |
2916 | { |
2917 | long iosynth; | |
2918 | unsigned int val; | |
2cbdb686 | 2919 | struct snd_opl3 *opl3; |
5747e540 CL |
2920 | int err; |
2921 | ||
2f24d159 TI |
2922 | if (!fm_port) |
2923 | goto disable_fm; | |
2924 | ||
c78c950d | 2925 | if (cm->chip_version >= 39) { |
45c41b48 CL |
2926 | /* first try FM regs in PCI port range */ |
2927 | iosynth = cm->iobase + CM_REG_FM_PCI; | |
2928 | err = snd_opl3_create(cm->card, iosynth, iosynth + 2, | |
2929 | OPL3_HW_OPL3, 1, &opl3); | |
2930 | } else { | |
2931 | err = -EIO; | |
2932 | } | |
5747e540 CL |
2933 | if (err < 0) { |
2934 | /* then try legacy ports */ | |
2935 | val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; | |
2936 | iosynth = fm_port; | |
2937 | switch (iosynth) { | |
2938 | case 0x3E8: val |= CM_FMSEL_3E8; break; | |
2939 | case 0x3E0: val |= CM_FMSEL_3E0; break; | |
2940 | case 0x3C8: val |= CM_FMSEL_3C8; break; | |
2941 | case 0x388: val |= CM_FMSEL_388; break; | |
2942 | default: | |
2f24d159 | 2943 | goto disable_fm; |
5747e540 CL |
2944 | } |
2945 | snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); | |
2946 | /* enable FM */ | |
2947 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); | |
2948 | ||
2949 | if (snd_opl3_create(cm->card, iosynth, iosynth + 2, | |
2950 | OPL3_HW_OPL3, 0, &opl3) < 0) { | |
40175bdb TI |
2951 | dev_err(cm->card->dev, |
2952 | "no OPL device at %#lx, skipping...\n", | |
2953 | iosynth); | |
2f24d159 | 2954 | goto disable_fm; |
5747e540 CL |
2955 | } |
2956 | } | |
43795882 TI |
2957 | err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); |
2958 | if (err < 0) { | |
40175bdb | 2959 | dev_err(cm->card->dev, "cannot create OPL3 hwdep\n"); |
5747e540 CL |
2960 | return err; |
2961 | } | |
2962 | return 0; | |
2f24d159 TI |
2963 | |
2964 | disable_fm: | |
2965 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK); | |
2966 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); | |
2967 | return 0; | |
5747e540 CL |
2968 | } |
2969 | ||
e23e7a14 | 2970 | static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci, |
87e082ad | 2971 | int dev) |
1da177e4 | 2972 | { |
87e082ad | 2973 | struct cmipci *cm = card->private_data; |
1da177e4 | 2974 | int err; |
d6426257 | 2975 | unsigned int val; |
395a434e | 2976 | long iomidi = 0; |
c9116ae4 | 2977 | int integrated_midi = 0; |
b7e054a7 | 2978 | char modelstr[16]; |
1da177e4 | 2979 | int pcm_index, pcm_spdif_index; |
9baa3c34 | 2980 | static const struct pci_device_id intel_82437vx[] = { |
1da177e4 LT |
2981 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, |
2982 | { }, | |
2983 | }; | |
2984 | ||
87e082ad | 2985 | err = pcim_enable_device(pci); |
43795882 | 2986 | if (err < 0) |
1da177e4 LT |
2987 | return err; |
2988 | ||
1da177e4 | 2989 | spin_lock_init(&cm->reg_lock); |
62932df8 | 2990 | mutex_init(&cm->open_mutex); |
1da177e4 LT |
2991 | cm->device = pci->device; |
2992 | cm->card = card; | |
2993 | cm->pci = pci; | |
2994 | cm->irq = -1; | |
2995 | cm->channel[0].ch = 0; | |
2996 | cm->channel[1].ch = 1; | |
2997 | cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ | |
2998 | ||
43795882 | 2999 | err = pci_request_regions(pci, card->driver); |
87e082ad | 3000 | if (err < 0) |
1da177e4 | 3001 | return err; |
1da177e4 LT |
3002 | cm->iobase = pci_resource_start(pci, 0); |
3003 | ||
87e082ad TI |
3004 | if (devm_request_irq(&pci->dev, pci->irq, snd_cmipci_interrupt, |
3005 | IRQF_SHARED, KBUILD_MODNAME, cm)) { | |
40175bdb | 3006 | dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); |
1da177e4 LT |
3007 | return -EBUSY; |
3008 | } | |
3009 | cm->irq = pci->irq; | |
3663984e | 3010 | card->sync_irq = cm->irq; |
87e082ad | 3011 | card->private_free = snd_cmipci_free; |
1da177e4 LT |
3012 | |
3013 | pci_set_master(cm->pci); | |
3014 | ||
3015 | /* | |
3016 | * check chip version, max channels and capabilities | |
3017 | */ | |
3018 | ||
3019 | cm->chip_version = 0; | |
3020 | cm->max_channels = 2; | |
3021 | cm->do_soft_ac3 = soft_ac3[dev]; | |
3022 | ||
3023 | if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && | |
3024 | pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) | |
3025 | query_chip(cm); | |
3026 | /* added -MCx suffix for chip supporting multi-channels */ | |
3027 | if (cm->can_multi_ch) | |
3028 | sprintf(cm->card->driver + strlen(cm->card->driver), | |
3029 | "-MC%d", cm->max_channels); | |
3030 | else if (cm->can_ac3_sw) | |
3031 | strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); | |
3032 | ||
3033 | cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; | |
3034 | cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; | |
3035 | ||
3036 | #if CM_CH_PLAY == 1 | |
3037 | cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */ | |
3038 | #else | |
3039 | cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */ | |
3040 | #endif | |
3041 | ||
3042 | /* initialize codec registers */ | |
3042ef75 CL |
3043 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET); |
3044 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET); | |
1da177e4 LT |
3045 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ |
3046 | snd_cmipci_ch_reset(cm, CM_CH_PLAY); | |
3047 | snd_cmipci_ch_reset(cm, CM_CH_CAPT); | |
3048 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ | |
3049 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); | |
3050 | ||
3051 | snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); | |
3052 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); | |
3053 | #if CM_CH_PLAY == 1 | |
3054 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
3055 | #else | |
3056 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
3057 | #endif | |
4ee72717 CL |
3058 | if (cm->chip_version) { |
3059 | snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */ | |
3060 | snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */ | |
3061 | } | |
1da177e4 LT |
3062 | /* Set Bus Master Request */ |
3063 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); | |
3064 | ||
3065 | /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ | |
3066 | switch (pci->device) { | |
3067 | case PCI_DEVICE_ID_CMEDIA_CM8738: | |
3068 | case PCI_DEVICE_ID_CMEDIA_CM8738B: | |
3069 | if (!pci_dev_present(intel_82437vx)) | |
3070 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); | |
3071 | break; | |
3072 | default: | |
3073 | break; | |
3074 | } | |
3075 | ||
d6426257 CL |
3076 | if (cm->chip_version < 68) { |
3077 | val = pci->device < 0x110 ? 8338 : 8738; | |
d6426257 CL |
3078 | } else { |
3079 | switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) { | |
3080 | case 0: | |
3081 | val = 8769; | |
3082 | break; | |
3083 | case 2: | |
3084 | val = 8762; | |
3085 | break; | |
3086 | default: | |
3087 | switch ((pci->subsystem_vendor << 16) | | |
3088 | pci->subsystem_device) { | |
3089 | case 0x13f69761: | |
3090 | case 0x584d3741: | |
3091 | case 0x584d3751: | |
3092 | case 0x584d3761: | |
3093 | case 0x584d3771: | |
3094 | case 0x72848384: | |
3095 | val = 8770; | |
3096 | break; | |
3097 | default: | |
3098 | val = 8768; | |
3099 | break; | |
3100 | } | |
3101 | } | |
d6426257 | 3102 | } |
b7e054a7 CL |
3103 | sprintf(card->shortname, "C-Media CMI%d", val); |
3104 | if (cm->chip_version < 68) | |
28329936 TI |
3105 | scnprintf(modelstr, sizeof(modelstr), |
3106 | " (model %d)", cm->chip_version); | |
b7e054a7 CL |
3107 | else |
3108 | modelstr[0] = '\0'; | |
28329936 TI |
3109 | scnprintf(card->longname, sizeof(card->longname), |
3110 | "%s%s at %#lx, irq %i", | |
3111 | card->shortname, modelstr, cm->iobase, cm->irq); | |
1e02d6ea | 3112 | |
c78c950d | 3113 | if (cm->chip_version >= 39) { |
c9116ae4 CL |
3114 | val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1); |
3115 | if (val != 0x00 && val != 0xff) { | |
d8cac620 TI |
3116 | if (mpu_port[dev]) |
3117 | iomidi = cm->iobase + CM_REG_MPU_PCI; | |
c9116ae4 CL |
3118 | integrated_midi = 1; |
3119 | } | |
3120 | } | |
3121 | if (!integrated_midi) { | |
c78c950d | 3122 | val = 0; |
5747e540 CL |
3123 | iomidi = mpu_port[dev]; |
3124 | switch (iomidi) { | |
3125 | case 0x320: val = CM_VMPU_320; break; | |
3126 | case 0x310: val = CM_VMPU_310; break; | |
3127 | case 0x300: val = CM_VMPU_300; break; | |
3128 | case 0x330: val = CM_VMPU_330; break; | |
3129 | default: | |
3130 | iomidi = 0; break; | |
3131 | } | |
3132 | if (iomidi > 0) { | |
3133 | snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); | |
3134 | /* enable UART */ | |
3135 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); | |
88039815 | 3136 | if (inb(iomidi + 1) == 0xff) { |
40175bdb TI |
3137 | dev_err(cm->card->dev, |
3138 | "cannot enable MPU-401 port at %#lx\n", | |
3139 | iomidi); | |
88039815 CL |
3140 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, |
3141 | CM_UART_EN); | |
3142 | iomidi = 0; | |
3143 | } | |
1da177e4 LT |
3144 | } |
3145 | } | |
5747e540 | 3146 | |
45c41b48 CL |
3147 | if (cm->chip_version < 68) { |
3148 | err = snd_cmipci_create_fm(cm, fm_port[dev]); | |
3149 | if (err < 0) | |
3150 | return err; | |
3151 | } | |
1da177e4 LT |
3152 | |
3153 | /* reset mixer */ | |
3154 | snd_cmipci_mixer_write(cm, 0, 0); | |
3155 | ||
3156 | snd_cmipci_proc_init(cm); | |
3157 | ||
3158 | /* create pcm devices */ | |
3159 | pcm_index = pcm_spdif_index = 0; | |
43795882 TI |
3160 | err = snd_cmipci_pcm_new(cm, pcm_index); |
3161 | if (err < 0) | |
1da177e4 LT |
3162 | return err; |
3163 | pcm_index++; | |
43795882 TI |
3164 | err = snd_cmipci_pcm2_new(cm, pcm_index); |
3165 | if (err < 0) | |
b080ebbf CL |
3166 | return err; |
3167 | pcm_index++; | |
1da177e4 LT |
3168 | if (cm->can_ac3_hw || cm->can_ac3_sw) { |
3169 | pcm_spdif_index = pcm_index; | |
43795882 TI |
3170 | err = snd_cmipci_pcm_spdif_new(cm, pcm_index); |
3171 | if (err < 0) | |
1da177e4 LT |
3172 | return err; |
3173 | } | |
3174 | ||
3175 | /* create mixer interface & switches */ | |
43795882 TI |
3176 | err = snd_cmipci_mixer_new(cm, pcm_spdif_index); |
3177 | if (err < 0) | |
1da177e4 LT |
3178 | return err; |
3179 | ||
3180 | if (iomidi > 0) { | |
43795882 TI |
3181 | err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, |
3182 | iomidi, | |
3183 | (integrated_midi ? | |
3184 | MPU401_INFO_INTEGRATED : 0) | | |
3185 | MPU401_INFO_IRQ_HOOK, | |
3186 | -1, &cm->rmidi); | |
3187 | if (err < 0) | |
40175bdb TI |
3188 | dev_err(cm->card->dev, |
3189 | "no UART401 device at 0x%lx\n", iomidi); | |
1da177e4 LT |
3190 | } |
3191 | ||
3192 | #ifdef USE_VAR48KRATE | |
3193 | for (val = 0; val < ARRAY_SIZE(rates); val++) | |
3194 | snd_cmipci_set_pll(cm, rates[val], val); | |
3195 | ||
3196 | /* | |
3197 | * (Re-)Enable external switch spdo_48k | |
3198 | */ | |
3199 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97); | |
3200 | #endif /* USE_VAR48KRATE */ | |
3201 | ||
3202 | if (snd_cmipci_create_gameport(cm, dev) < 0) | |
3203 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); | |
3204 | ||
1da177e4 LT |
3205 | return 0; |
3206 | } | |
3207 | ||
3208 | /* | |
3209 | */ | |
3210 | ||
3211 | MODULE_DEVICE_TABLE(pci, snd_cmipci_ids); | |
3212 | ||
e23e7a14 BP |
3213 | static int snd_cmipci_probe(struct pci_dev *pci, |
3214 | const struct pci_device_id *pci_id) | |
1da177e4 LT |
3215 | { |
3216 | static int dev; | |
2cbdb686 | 3217 | struct snd_card *card; |
1da177e4 LT |
3218 | int err; |
3219 | ||
3220 | if (dev >= SNDRV_CARDS) | |
3221 | return -ENODEV; | |
3222 | if (! enable[dev]) { | |
3223 | dev++; | |
3224 | return -ENOENT; | |
3225 | } | |
3226 | ||
87e082ad | 3227 | err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, |
bd5e2c22 | 3228 | sizeof(struct cmipci), &card); |
e58de7ba TI |
3229 | if (err < 0) |
3230 | return err; | |
1da177e4 LT |
3231 | |
3232 | switch (pci->device) { | |
3233 | case PCI_DEVICE_ID_CMEDIA_CM8738: | |
3234 | case PCI_DEVICE_ID_CMEDIA_CM8738B: | |
3235 | strcpy(card->driver, "CMI8738"); | |
3236 | break; | |
3237 | case PCI_DEVICE_ID_CMEDIA_CM8338A: | |
3238 | case PCI_DEVICE_ID_CMEDIA_CM8338B: | |
3239 | strcpy(card->driver, "CMI8338"); | |
3240 | break; | |
3241 | default: | |
3242 | strcpy(card->driver, "CMIPCI"); | |
3243 | break; | |
3244 | } | |
3245 | ||
87e082ad | 3246 | err = snd_cmipci_create(card, pci, dev); |
e17a85ec | 3247 | if (err < 0) |
a59396b1 | 3248 | goto error; |
1da177e4 | 3249 | |
e17a85ec ME |
3250 | err = snd_card_register(card); |
3251 | if (err < 0) | |
a59396b1 | 3252 | goto error; |
e17a85ec | 3253 | |
1da177e4 LT |
3254 | pci_set_drvdata(pci, card); |
3255 | dev++; | |
3256 | return 0; | |
a59396b1 TI |
3257 | |
3258 | error: | |
3259 | snd_card_free(card); | |
3260 | return err; | |
1da177e4 LT |
3261 | } |
3262 | ||
c7561cd8 | 3263 | #ifdef CONFIG_PM_SLEEP |
cb60e5f5 TI |
3264 | /* |
3265 | * power management | |
3266 | */ | |
5f3aca10 | 3267 | static const unsigned char saved_regs[] = { |
cb60e5f5 | 3268 | CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL, |
c14231cc | 3269 | CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL, |
cb60e5f5 TI |
3270 | CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2, |
3271 | CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC, | |
3272 | CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0, | |
3273 | }; | |
3274 | ||
5f3aca10 | 3275 | static const unsigned char saved_mixers[] = { |
cb60e5f5 TI |
3276 | SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1, |
3277 | SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1, | |
3278 | SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1, | |
3279 | SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1, | |
3280 | SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1, | |
3281 | SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV, | |
3282 | CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW, | |
3283 | SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, | |
3284 | }; | |
3285 | ||
68cb2b55 | 3286 | static int snd_cmipci_suspend(struct device *dev) |
cb60e5f5 | 3287 | { |
68cb2b55 | 3288 | struct snd_card *card = dev_get_drvdata(dev); |
cb60e5f5 TI |
3289 | struct cmipci *cm = card->private_data; |
3290 | int i; | |
3291 | ||
3292 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); | |
3293 | ||
cb60e5f5 TI |
3294 | /* save registers */ |
3295 | for (i = 0; i < ARRAY_SIZE(saved_regs); i++) | |
3296 | cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]); | |
3297 | for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) | |
3298 | cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]); | |
3299 | ||
3300 | /* disable ints */ | |
3301 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); | |
cb60e5f5 TI |
3302 | return 0; |
3303 | } | |
3304 | ||
68cb2b55 | 3305 | static int snd_cmipci_resume(struct device *dev) |
cb60e5f5 | 3306 | { |
68cb2b55 | 3307 | struct snd_card *card = dev_get_drvdata(dev); |
cb60e5f5 TI |
3308 | struct cmipci *cm = card->private_data; |
3309 | int i; | |
3310 | ||
cb60e5f5 TI |
3311 | /* reset / initialize to a sane state */ |
3312 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); | |
3313 | snd_cmipci_ch_reset(cm, CM_CH_PLAY); | |
3314 | snd_cmipci_ch_reset(cm, CM_CH_CAPT); | |
3315 | snd_cmipci_mixer_write(cm, 0, 0); | |
3316 | ||
3317 | /* restore registers */ | |
3318 | for (i = 0; i < ARRAY_SIZE(saved_regs); i++) | |
3319 | snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]); | |
3320 | for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) | |
3321 | snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]); | |
3322 | ||
3323 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); | |
3324 | return 0; | |
3325 | } | |
68cb2b55 TI |
3326 | |
3327 | static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume); | |
3328 | #define SND_CMIPCI_PM_OPS &snd_cmipci_pm | |
3329 | #else | |
3330 | #define SND_CMIPCI_PM_OPS NULL | |
c7561cd8 | 3331 | #endif /* CONFIG_PM_SLEEP */ |
cb60e5f5 | 3332 | |
e9f66d9b | 3333 | static struct pci_driver cmipci_driver = { |
3733e424 | 3334 | .name = KBUILD_MODNAME, |
1da177e4 LT |
3335 | .id_table = snd_cmipci_ids, |
3336 | .probe = snd_cmipci_probe, | |
68cb2b55 TI |
3337 | .driver = { |
3338 | .pm = SND_CMIPCI_PM_OPS, | |
3339 | }, | |
1da177e4 LT |
3340 | }; |
3341 | ||
e9f66d9b | 3342 | module_pci_driver(cmipci_driver); |