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[linux-2.6-block.git] / sound / pci / cmipci.c
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1da177e4
LT		 1/*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/* Does not work. Warning may block system in capture mode */
21/* #define USE_VAR48KRATE */
22
23#include <sound/driver.h>
24#include <asm/io.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/init.h>
28#include <linux/pci.h>
29#include <linux/slab.h>
30#include <linux/gameport.h>
31#include <linux/moduleparam.h>
32#include <sound/core.h>
33#include <sound/info.h>
34#include <sound/control.h>
35#include <sound/pcm.h>
36#include <sound/rawmidi.h>
37#include <sound/mpu401.h>
38#include <sound/opl3.h>
39#include <sound/sb.h>
40#include <sound/asoundef.h>
41#include <sound/initval.h>
42
43MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45MODULE_LICENSE("GPL");
46MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52#define SUPPORT_JOYSTICK 1
53#endif
54
55static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58static long mpu_port[SNDRV_CARDS];
59static long fm_port[SNDRV_CARDS];
60static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61#ifdef SUPPORT_JOYSTICK
62static int joystick_port[SNDRV_CARDS];
63#endif
64
65module_param_array(index, int, NULL, 0444);
66MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
67module_param_array(id, charp, NULL, 0444);
68MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
69module_param_array(enable, bool, NULL, 0444);
70MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
71module_param_array(mpu_port, long, NULL, 0444);
72MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73module_param_array(fm_port, long, NULL, 0444);
74MODULE_PARM_DESC(fm_port, "FM port.");
75module_param_array(soft_ac3, bool, NULL, 0444);
76MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
77#ifdef SUPPORT_JOYSTICK
78module_param_array(joystick_port, int, NULL, 0444);
79MODULE_PARM_DESC(joystick_port, "Joystick port address.");
80#endif
81
82#ifndef PCI_DEVICE_ID_CMEDIA_CM8738
83#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
84#endif
85#ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
86#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
87#endif
88
89/*
90 * CM8x38 registers definition
91 */
92
93#define CM_REG_FUNCTRL0 0x00
94#define CM_RST_CH1 0x00080000
95#define CM_RST_CH0 0x00040000
96#define CM_CHEN1 0x00020000 /* ch1: enable */
97#define CM_CHEN0 0x00010000 /* ch0: enable */
98#define CM_PAUSE1 0x00000008 /* ch1: pause */
99#define CM_PAUSE0 0x00000004 /* ch0: pause */
100#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
101#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
102
103#define CM_REG_FUNCTRL1 0x04
104#define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
105#define CM_ASFC_SHIFT 13
106#define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
107#define CM_DSFC_SHIFT 10
108#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
109#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
110#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
111#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
112#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
113#define CM_BREQ 0x00000010 /* bus master enabled */
114#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
115#define CM_UART_EN 0x00000004 /* UART */
116#define CM_JYSTK_EN 0x00000002 /* joy stick */
117
118#define CM_REG_CHFORMAT 0x08
119
120#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
121#define CM_CHB3D 0x20000000 /* 4 channels */
122
123#define CM_CHIP_MASK1 0x1f000000
124#define CM_CHIP_037 0x01000000
125
126#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
127#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
128#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
129/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
130
131#define CM_ADCBITLEN_MASK 0x0000C000
132#define CM_ADCBITLEN_16 0x00000000
133#define CM_ADCBITLEN_15 0x00004000
134#define CM_ADCBITLEN_14 0x00008000
135#define CM_ADCBITLEN_13 0x0000C000
136
137#define CM_ADCDACLEN_MASK 0x00003000
138#define CM_ADCDACLEN_060 0x00000000
139#define CM_ADCDACLEN_066 0x00001000
140#define CM_ADCDACLEN_130 0x00002000
141#define CM_ADCDACLEN_280 0x00003000
142
143#define CM_CH1_SRATE_176K 0x00000800
144#define CM_CH1_SRATE_88K 0x00000400
145#define CM_CH0_SRATE_176K 0x00000200
146#define CM_CH0_SRATE_88K 0x00000100
147
148#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
149
150#define CM_CH1FMT_MASK 0x0000000C
151#define CM_CH1FMT_SHIFT 2
152#define CM_CH0FMT_MASK 0x00000003
153#define CM_CH0FMT_SHIFT 0
154
155#define CM_REG_INT_HLDCLR 0x0C
156#define CM_CHIP_MASK2 0xff000000
157#define CM_CHIP_039 0x04000000
158#define CM_CHIP_039_6CH 0x01000000
159#define CM_CHIP_055 0x08000000
160#define CM_CHIP_8768 0x20000000
161#define CM_TDMA_INT_EN 0x00040000
162#define CM_CH1_INT_EN 0x00020000
163#define CM_CH0_INT_EN 0x00010000
164#define CM_INT_HOLD 0x00000002
165#define CM_INT_CLEAR 0x00000001
166
167#define CM_REG_INT_STATUS 0x10
168#define CM_INTR 0x80000000
169#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
170#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
171#define CM_UARTINT 0x00010000
172#define CM_LTDMAINT 0x00008000
173#define CM_HTDMAINT 0x00004000
174#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
175#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
176#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
177#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
178#define CM_CH1BUSY 0x00000008
179#define CM_CH0BUSY 0x00000004
180#define CM_CHINT1 0x00000002
181#define CM_CHINT0 0x00000001
182
183#define CM_REG_LEGACY_CTRL 0x14
184#define CM_NXCHG 0x80000000 /* h/w multi channels? */
185#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
186#define CM_VMPU_330 0x00000000
187#define CM_VMPU_320 0x20000000
188#define CM_VMPU_310 0x40000000
189#define CM_VMPU_300 0x60000000
190#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
191#define CM_VSBSEL_220 0x00000000
192#define CM_VSBSEL_240 0x04000000
193#define CM_VSBSEL_260 0x08000000
194#define CM_VSBSEL_280 0x0C000000
195#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
196#define CM_FMSEL_388 0x00000000
197#define CM_FMSEL_3C8 0x01000000
198#define CM_FMSEL_3E0 0x02000000
199#define CM_FMSEL_3E8 0x03000000
200#define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
201#define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
202#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
203#define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
204#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
205#define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
206
207#define CM_REG_MISC_CTRL 0x18
208#define CM_PWD 0x80000000
209#define CM_RESET 0x40000000
210#define CM_SFIL_MASK 0x30000000
211#define CM_TXVX 0x08000000
212#define CM_N4SPK3D 0x04000000 /* 4ch output */
213#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
214#define CM_SPDIF48K 0x01000000 /* write */
215#define CM_SPATUS48K 0x01000000 /* read */
216#define CM_ENDBDAC 0x00800000 /* enable dual dac */
217#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
218#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
219#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
220#define CM_FM_EN 0x00080000 /* enalbe FM */
221#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
222#define CM_VIDWPDSB 0x00010000
223#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
224#define CM_MASK_EN 0x00004000
225#define CM_VIDWPPRT 0x00002000
226#define CM_SFILENB 0x00001000
227#define CM_MMODE_MASK 0x00000E00
228#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
229#define CM_ENCENTER 0x00000080
230#define CM_FLINKON 0x00000040
231#define CM_FLINKOFF 0x00000020
232#define CM_MIDSMP 0x00000010
233#define CM_UPDDMA_MASK 0x0000000C
234#define CM_TWAIT_MASK 0x00000003
235
236 /* byte */
237#define CM_REG_MIXER0 0x20
238
239#define CM_REG_SB16_DATA 0x22
240#define CM_REG_SB16_ADDR 0x23
241
242#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
243#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
244#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
245#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
246
247#define CM_REG_MIXER1 0x24
248#define CM_FMMUTE 0x80 /* mute FM */
249#define CM_FMMUTE_SHIFT 7
250#define CM_WSMUTE 0x40 /* mute PCM */
251#define CM_WSMUTE_SHIFT 6
252#define CM_SPK4 0x20 /* lin-in -> rear line out */
253#define CM_SPK4_SHIFT 5
254#define CM_REAR2FRONT 0x10 /* exchange rear/front */
255#define CM_REAR2FRONT_SHIFT 4
256#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
257#define CM_WAVEINL_SHIFT 3
258#define CM_WAVEINR 0x04 /* digical wave rec. right */
259#define CM_WAVEINR_SHIFT 2
260#define CM_X3DEN 0x02 /* 3D surround enable */
261#define CM_X3DEN_SHIFT 1
262#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
263#define CM_CDPLAY_SHIFT 0
264
265#define CM_REG_MIXER2 0x25
266#define CM_RAUXREN 0x80 /* AUX right capture */
267#define CM_RAUXREN_SHIFT 7
268#define CM_RAUXLEN 0x40 /* AUX left capture */
269#define CM_RAUXLEN_SHIFT 6
270#define CM_VAUXRM 0x20 /* AUX right mute */
271#define CM_VAUXRM_SHIFT 5
272#define CM_VAUXLM 0x10 /* AUX left mute */
273#define CM_VAUXLM_SHIFT 4
274#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
275#define CM_VADMIC_SHIFT 1
276#define CM_MICGAINZ 0x01 /* mic boost */
277#define CM_MICGAINZ_SHIFT 0
278
279#define CM_REG_AUX_VOL 0x26
280#define CM_VAUXL_MASK 0xf0
281#define CM_VAUXR_MASK 0x0f
282
283#define CM_REG_MISC 0x27
284#define CM_XGPO1 0x20
285// #define CM_XGPBIO 0x04
286#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
287#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
288#define CM_SPDVALID 0x02 /* spdif input valid check */
289#define CM_DMAUTO 0x01
290
291#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
292/*
293 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
294 * or identical with AC97 codec?
295 */
296#define CM_REG_EXTERN_CODEC CM_REG_AC97
297
298/*
299 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
300 */
301#define CM_REG_MPU_PCI 0x40
302
303/*
304 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
305 */
306#define CM_REG_FM_PCI 0x50
307
308/*
309 * for CMI-8338 .. this is not valid for CMI-8738.
310 */
311#define CM_REG_EXTENT_IND 0xf0
312#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
313#define CM_VPHONE_SHIFT 5
314#define CM_VPHOM 0x10 /* Phone mute control */
315#define CM_VSPKM 0x08 /* Speaker mute control, default high */
316#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
317#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
318
319/*
320 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
321 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
322 * unit (readonly?).
323 */
324#define CM_REG_PLL 0xf8
325
326/*
327 * extended registers
328 */
329#define CM_REG_CH0_FRAME1 0x80 /* base address */
330#define CM_REG_CH0_FRAME2 0x84
331#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
332#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
333#define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */
334#define CM_CHB3D8C 0x20 /* 7.1 channels support */
335#define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */
336#define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */
337#define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */
338#define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */
339#define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */
340
341/*
342 * size of i/o region
343 */
344#define CM_EXTENT_CODEC 0x100
345#define CM_EXTENT_MIDI 0x2
346#define CM_EXTENT_SYNTH 0x4
347
348
349/*
350 * pci ids
351 */
352#ifndef PCI_VENDOR_ID_CMEDIA
353#define PCI_VENDOR_ID_CMEDIA 0x13F6
354#endif
355#ifndef PCI_DEVICE_ID_CMEDIA_CM8338A
356#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100
357#endif
358#ifndef PCI_DEVICE_ID_CMEDIA_CM8338B
359#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101
360#endif
361#ifndef PCI_DEVICE_ID_CMEDIA_CM8738
362#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
363#endif
364#ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
365#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
366#endif
367
368/*
369 * channels for playback / capture
370 */
371#define CM_CH_PLAY 0
372#define CM_CH_CAPT 1
373
374/*
375 * flags to check device open/close
376 */
377#define CM_OPEN_NONE 0
378#define CM_OPEN_CH_MASK 0x01
379#define CM_OPEN_DAC 0x10
380#define CM_OPEN_ADC 0x20
381#define CM_OPEN_SPDIF 0x40
382#define CM_OPEN_MCHAN 0x80
383#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
384#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
385#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
386#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
387#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
388#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
389
390
391#if CM_CH_PLAY == 1
392#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
393#define CM_PLAYBACK_SPDF CM_SPDF_1
394#define CM_CAPTURE_SPDF CM_SPDF_0
395#else
396#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
397#define CM_PLAYBACK_SPDF CM_SPDF_0
398#define CM_CAPTURE_SPDF CM_SPDF_1
399#endif
400
401
402/*
403 * driver data
404 */
405
406typedef struct snd_stru_cmipci cmipci_t;
407typedef struct snd_stru_cmipci_pcm cmipci_pcm_t;
408
409struct snd_stru_cmipci_pcm {
410 snd_pcm_substream_t *substream;
411 int running; /* dac/adc running? */
412 unsigned int dma_size; /* in frames */
413 unsigned int period_size; /* in frames */
414 unsigned int offset; /* physical address of the buffer */
415 unsigned int fmt; /* format bits */
416 int ch; /* channel (0/1) */
417 unsigned int is_dac; /* is dac? */
418 int bytes_per_frame;
419 int shift;
420};
421
422/* mixer elements toggled/resumed during ac3 playback */
423struct cmipci_mixer_auto_switches {
424 const char *name; /* switch to toggle */
425 int toggle_on; /* value to change when ac3 mode */
426};
427static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
428 {"PCM Playback Switch", 0},
429 {"IEC958 Output Switch", 1},
430 {"IEC958 Mix Analog", 0},
431 // {"IEC958 Out To DAC", 1}, // no longer used
432 {"IEC958 Loop", 0},
433};
434#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
435
436struct snd_stru_cmipci {
437 snd_card_t *card;
438
439 struct pci_dev *pci;
440 unsigned int device; /* device ID */
441 int irq;
442
443 unsigned long iobase;
444 unsigned int ctrl; /* FUNCTRL0 current value */
445
446 snd_pcm_t *pcm; /* DAC/ADC PCM */
447 snd_pcm_t *pcm2; /* 2nd DAC */
448 snd_pcm_t *pcm_spdif; /* SPDIF */
449
450 int chip_version;
451 int max_channels;
452 unsigned int has_dual_dac: 1;
453 unsigned int can_ac3_sw: 1;
454 unsigned int can_ac3_hw: 1;
455 unsigned int can_multi_ch: 1;
456 unsigned int do_soft_ac3: 1;
457
458 unsigned int spdif_playback_avail: 1; /* spdif ready? */
459 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
460 int spdif_counter; /* for software AC3 */
461
462 unsigned int dig_status;
463 unsigned int dig_pcm_status;
464
465 snd_pcm_hardware_t *hw_info[3]; /* for playbacks */
466
467 int opened[2]; /* open mode */
468 struct semaphore open_mutex;
469
470 unsigned int mixer_insensitive: 1;
471 snd_kcontrol_t *mixer_res_ctl[CM_SAVED_MIXERS];
472 int mixer_res_status[CM_SAVED_MIXERS];
473
474 opl3_t *opl3;
475 snd_hwdep_t *opl3hwdep;
476
477 cmipci_pcm_t channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
478
479 /* external MIDI */
480 snd_rawmidi_t *rmidi;
481
482#ifdef SUPPORT_JOYSTICK
483 struct gameport *gameport;
484#endif
485
486 spinlock_t reg_lock;
487};
488
489
490/* read/write operations for dword register */
491inline static void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data)
492{
493 outl(data, cm->iobase + cmd);
494}
495inline static unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd)
496{
497 return inl(cm->iobase + cmd);
498}
499
500/* read/write operations for word register */
501inline static void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data)
502{
503 outw(data, cm->iobase + cmd);
504}
505inline static unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd)
506{
507 return inw(cm->iobase + cmd);
508}
509
510/* read/write operations for byte register */
511inline static void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data)
512{
513 outb(data, cm->iobase + cmd);
514}
515
516inline static unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd)
517{
518 return inb(cm->iobase + cmd);
519}
520
521/* bit operations for dword register */
01d25d46 522static int snd_cmipci_set_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
1da177e4 523{
01d25d46
TI		 524 unsigned int val, oval;
525 val = oval = inl(cm->iobase + cmd);
1da177e4 526 val |= flag;
01d25d46
TI		 527 if (val == oval)
528 return 0;
1da177e4 529 outl(val, cm->iobase + cmd);
01d25d46 530 return 1;
1da177e4
LT		 531}
532
01d25d46 533static int snd_cmipci_clear_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
1da177e4 534{
01d25d46
TI		 535 unsigned int val, oval;
536 val = oval = inl(cm->iobase + cmd);
1da177e4 537 val &= ~flag;
01d25d46
TI		 538 if (val == oval)
539 return 0;
1da177e4 540 outl(val, cm->iobase + cmd);
01d25d46 541 return 1;
1da177e4
LT		 542}
543
1da177e4 544/* bit operations for byte register */
01d25d46 545static int snd_cmipci_set_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
1da177e4 546{
01d25d46
TI		 547 unsigned char val, oval;
548 val = oval = inb(cm->iobase + cmd);
1da177e4 549 val |= flag;
01d25d46
TI		 550 if (val == oval)
551 return 0;
1da177e4 552 outb(val, cm->iobase + cmd);
01d25d46 553 return 1;
1da177e4
LT		 554}
555
01d25d46 556static int snd_cmipci_clear_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
1da177e4 557{
01d25d46
TI		 558 unsigned char val, oval;
559 val = oval = inb(cm->iobase + cmd);
1da177e4 560 val &= ~flag;
01d25d46
TI		 561 if (val == oval)
562 return 0;
1da177e4 563 outb(val, cm->iobase + cmd);
01d25d46 564 return 1;
1da177e4 565}
1da177e4
LT		 566
567
568/*
569 * PCM interface
570 */
571
572/*
573 * calculate frequency
574 */
575
576static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
577
578static unsigned int snd_cmipci_rate_freq(unsigned int rate)
579{
580 unsigned int i;
581 for (i = 0; i < ARRAY_SIZE(rates); i++) {
582 if (rates[i] == rate)
583 return i;
584 }
585 snd_BUG();
586 return 0;
587}
588
589#ifdef USE_VAR48KRATE
590/*
591 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
592 * does it this way .. maybe not. Never get any information from C-Media about
593 * that <werner@suse.de>.
594 */
595static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
596{
597 unsigned int delta, tolerance;
598 int xm, xn, xr;
599
600 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
601 rate <<= 1;
602 *n = -1;
603 if (*r > 0xff)
604 goto out;
605 tolerance = rate*CM_TOLERANCE_RATE;
606
607 for (xn = (1+2); xn < (0x1f+2); xn++) {
608 for (xm = (1+2); xm < (0xff+2); xm++) {
609 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
610
611 if (xr < rate)
612 delta = rate - xr;
613 else
614 delta = xr - rate;
615
616 /*
617 * If we found one, remember this,
618 * and try to find a closer one
619 */
620 if (delta < tolerance) {
621 tolerance = delta;
622 *m = xm - 2;
623 *n = xn - 2;
624 }
625 }
626 }
627out:
628 return (*n > -1);
629}
630
631/*
632 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
633 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
634 * at the register CM_REG_FUNCTRL1 (0x04).
635 * Problem: other ways are also possible (any information about that?)
636 */
637static void snd_cmipci_set_pll(cmipci_t *cm, unsigned int rate, unsigned int slot)
638{
639 unsigned int reg = CM_REG_PLL + slot;
640 /*
641 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
642 * for DSFC/ASFC (000 upto 111).
643 */
644
645 /* FIXME: Init (Do we've to set an other register first before programming?) */
646
647 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
648 snd_cmipci_write_b(cm, reg, rate>>8);
649 snd_cmipci_write_b(cm, reg, rate&0xff);
650
651 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
652}
653#endif /* USE_VAR48KRATE */
654
655static int snd_cmipci_hw_params(snd_pcm_substream_t * substream,
656 snd_pcm_hw_params_t * hw_params)
657{
658 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
659}
660
661static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t * substream,
662 snd_pcm_hw_params_t * hw_params)
663{
664 cmipci_t *cm = snd_pcm_substream_chip(substream);
665 if (params_channels(hw_params) > 2) {
666 down(&cm->open_mutex);
667 if (cm->opened[CM_CH_PLAY]) {
668 up(&cm->open_mutex);
669 return -EBUSY;
670 }
671 /* reserve the channel A */
672 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
673 up(&cm->open_mutex);
674 }
675 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
676}
677
678static void snd_cmipci_ch_reset(cmipci_t *cm, int ch)
679{
680 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
681 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
682 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
683 udelay(10);
684}
685
686static int snd_cmipci_hw_free(snd_pcm_substream_t * substream)
687{
688 return snd_pcm_lib_free_pages(substream);
689}
690
691
692/*
693 */
694
695static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
696static snd_pcm_hw_constraint_list_t hw_constraints_channels_4 = {
697 .count = 3,
698 .list = hw_channels,
699 .mask = 0,
700};
701static snd_pcm_hw_constraint_list_t hw_constraints_channels_6 = {
702 .count = 5,
703 .list = hw_channels,
704 .mask = 0,
705};
706static snd_pcm_hw_constraint_list_t hw_constraints_channels_8 = {
707 .count = 6,
708 .list = hw_channels,
709 .mask = 0,
710};
711
712static int set_dac_channels(cmipci_t *cm, cmipci_pcm_t *rec, int channels)
713{
714 if (channels > 2) {
715 if (! cm->can_multi_ch)
716 return -EINVAL;
717 if (rec->fmt != 0x03) /* stereo 16bit only */
718 return -EINVAL;
719
720 spin_lock_irq(&cm->reg_lock);
721 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
722 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
723 if (channels > 4) {
724 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
725 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
726 } else {
727 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
728 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
729 }
730 if (channels >= 6) {
731 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
732 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
733 } else {
734 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
735 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
736 }
737 if (cm->chip_version == 68) {
738 if (channels == 8) {
739 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
740 } else {
741 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
742 }
743 }
744 spin_unlock_irq(&cm->reg_lock);
745
746 } else {
747 if (cm->can_multi_ch) {
748 spin_lock_irq(&cm->reg_lock);
749 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
750 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
751 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
752 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
753 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
754 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
755 spin_unlock_irq(&cm->reg_lock);
756 }
757 }
758 return 0;
759}
760
761
762/*
763 * prepare playback/capture channel
764 * channel to be used must have been set in rec->ch.
765 */
766static int snd_cmipci_pcm_prepare(cmipci_t *cm, cmipci_pcm_t *rec,
767 snd_pcm_substream_t *substream)
768{
769 unsigned int reg, freq, val;
770 snd_pcm_runtime_t *runtime = substream->runtime;
771
772 rec->fmt = 0;
773 rec->shift = 0;
774 if (snd_pcm_format_width(runtime->format) >= 16) {
775 rec->fmt |= 0x02;
776 if (snd_pcm_format_width(runtime->format) > 16)
777 rec->shift++; /* 24/32bit */
778 }
779 if (runtime->channels > 1)
780 rec->fmt |= 0x01;
781 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
782 snd_printd("cannot set dac channels\n");
783 return -EINVAL;
784 }
785
786 rec->offset = runtime->dma_addr;
787 /* buffer and period sizes in frame */
788 rec->dma_size = runtime->buffer_size << rec->shift;
789 rec->period_size = runtime->period_size << rec->shift;
790 if (runtime->channels > 2) {
791 /* multi-channels */
792 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
793 rec->period_size = (rec->period_size * runtime->channels) / 2;
794 }
795
796 spin_lock_irq(&cm->reg_lock);
797
798 /* set buffer address */
799 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
800 snd_cmipci_write(cm, reg, rec->offset);
801 /* program sample counts */
802 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
803 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
804 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
805
806 /* set adc/dac flag */
807 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
808 if (rec->is_dac)
809 cm->ctrl &= ~val;
810 else
811 cm->ctrl |= val;
812 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
813 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
814
815 /* set sample rate */
816 freq = snd_cmipci_rate_freq(runtime->rate);
817 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
818 if (rec->ch) {
819 val &= ~CM_ASFC_MASK;
820 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
821 } else {
822 val &= ~CM_DSFC_MASK;
823 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
824 }
825 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
826 //snd_printd("cmipci: functrl1 = %08x\n", val);
827
828 /* set format */
829 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
830 if (rec->ch) {
831 val &= ~CM_CH1FMT_MASK;
832 val |= rec->fmt << CM_CH1FMT_SHIFT;
833 } else {
834 val &= ~CM_CH0FMT_MASK;
835 val |= rec->fmt << CM_CH0FMT_SHIFT;
836 }
837 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
838 //snd_printd("cmipci: chformat = %08x\n", val);
839
840 rec->running = 0;
841 spin_unlock_irq(&cm->reg_lock);
842
843 return 0;
844}
845
846/*
847 * PCM trigger/stop
848 */
849static int snd_cmipci_pcm_trigger(cmipci_t *cm, cmipci_pcm_t *rec,
850 snd_pcm_substream_t *substream, int cmd)
851{
852 unsigned int inthld, chen, reset, pause;
853 int result = 0;
854
855 inthld = CM_CH0_INT_EN << rec->ch;
856 chen = CM_CHEN0 << rec->ch;
857 reset = CM_RST_CH0 << rec->ch;
858 pause = CM_PAUSE0 << rec->ch;
859
860 spin_lock(&cm->reg_lock);
861 switch (cmd) {
862 case SNDRV_PCM_TRIGGER_START:
863 rec->running = 1;
864 /* set interrupt */
865 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
866 cm->ctrl |= chen;
867 /* enable channel */
868 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
869 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
870 break;
871 case SNDRV_PCM_TRIGGER_STOP:
872 rec->running = 0;
873 /* disable interrupt */
874 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
875 /* reset */
876 cm->ctrl &= ~chen;
877 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
878 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
879 break;
880 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
881 cm->ctrl |= pause;
882 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
883 break;
884 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
885 cm->ctrl &= ~pause;
886 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
887 break;
888 default:
889 result = -EINVAL;
890 break;
891 }
892 spin_unlock(&cm->reg_lock);
893 return result;
894}
895
896/*
897 * return the current pointer
898 */
899static snd_pcm_uframes_t snd_cmipci_pcm_pointer(cmipci_t *cm, cmipci_pcm_t *rec,
900 snd_pcm_substream_t *substream)
901{
902 size_t ptr;
903 unsigned int reg;
904 if (!rec->running)
905 return 0;
906#if 1 // this seems better..
907 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
908 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
909 ptr >>= rec->shift;
910#else
911 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
912 ptr = snd_cmipci_read(cm, reg) - rec->offset;
913 ptr = bytes_to_frames(substream->runtime, ptr);
914#endif
915 if (substream->runtime->channels > 2)
916 ptr = (ptr * 2) / substream->runtime->channels;
917 return ptr;
918}
919
920/*
921 * playback
922 */
923
924static int snd_cmipci_playback_trigger(snd_pcm_substream_t *substream,
925 int cmd)
926{
927 cmipci_t *cm = snd_pcm_substream_chip(substream);
928 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
929}
930
931static snd_pcm_uframes_t snd_cmipci_playback_pointer(snd_pcm_substream_t *substream)
932{
933 cmipci_t *cm = snd_pcm_substream_chip(substream);
934 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
935}
936
937
938
939/*
940 * capture
941 */
942
943static int snd_cmipci_capture_trigger(snd_pcm_substream_t *substream,
944 int cmd)
945{
946 cmipci_t *cm = snd_pcm_substream_chip(substream);
947 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
948}
949
950static snd_pcm_uframes_t snd_cmipci_capture_pointer(snd_pcm_substream_t *substream)
951{
952 cmipci_t *cm = snd_pcm_substream_chip(substream);
953 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
954}
955
956
957/*
958 * hw preparation for spdif
959 */
960
961static int snd_cmipci_spdif_default_info(snd_kcontrol_t *kcontrol,
962 snd_ctl_elem_info_t *uinfo)
963{
964 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
965 uinfo->count = 1;
966 return 0;
967}
968
969static int snd_cmipci_spdif_default_get(snd_kcontrol_t *kcontrol,
970 snd_ctl_elem_value_t *ucontrol)
971{
972 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
973 int i;
974
975 spin_lock_irq(&chip->reg_lock);
976 for (i = 0; i < 4; i++)
977 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
978 spin_unlock_irq(&chip->reg_lock);
979 return 0;
980}
981
982static int snd_cmipci_spdif_default_put(snd_kcontrol_t * kcontrol,
983 snd_ctl_elem_value_t * ucontrol)
984{
985 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
986 int i, change;
987 unsigned int val;
988
989 val = 0;
990 spin_lock_irq(&chip->reg_lock);
991 for (i = 0; i < 4; i++)
992 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
993 change = val != chip->dig_status;
994 chip->dig_status = val;
995 spin_unlock_irq(&chip->reg_lock);
996 return change;
997}
998
999static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata =
1000{
1001 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1002 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1003 .info = snd_cmipci_spdif_default_info,
1004 .get = snd_cmipci_spdif_default_get,
1005 .put = snd_cmipci_spdif_default_put
1006};
1007
1008static int snd_cmipci_spdif_mask_info(snd_kcontrol_t *kcontrol,
1009 snd_ctl_elem_info_t *uinfo)
1010{
1011 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1012 uinfo->count = 1;
1013 return 0;
1014}
1015
1016static int snd_cmipci_spdif_mask_get(snd_kcontrol_t * kcontrol,
1017 snd_ctl_elem_value_t *ucontrol)
1018{
1019 ucontrol->value.iec958.status[0] = 0xff;
1020 ucontrol->value.iec958.status[1] = 0xff;
1021 ucontrol->value.iec958.status[2] = 0xff;
1022 ucontrol->value.iec958.status[3] = 0xff;
1023 return 0;
1024}
1025
1026static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata =
1027{
1028 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1029 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1030 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1031 .info = snd_cmipci_spdif_mask_info,
1032 .get = snd_cmipci_spdif_mask_get,
1033};
1034
1035static int snd_cmipci_spdif_stream_info(snd_kcontrol_t *kcontrol,
1036 snd_ctl_elem_info_t *uinfo)
1037{
1038 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1039 uinfo->count = 1;
1040 return 0;
1041}
1042
1043static int snd_cmipci_spdif_stream_get(snd_kcontrol_t *kcontrol,
1044 snd_ctl_elem_value_t *ucontrol)
1045{
1046 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1047 int i;
1048
1049 spin_lock_irq(&chip->reg_lock);
1050 for (i = 0; i < 4; i++)
1051 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1052 spin_unlock_irq(&chip->reg_lock);
1053 return 0;
1054}
1055
1056static int snd_cmipci_spdif_stream_put(snd_kcontrol_t *kcontrol,
1057 snd_ctl_elem_value_t *ucontrol)
1058{
1059 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1060 int i, change;
1061 unsigned int val;
1062
1063 val = 0;
1064 spin_lock_irq(&chip->reg_lock);
1065 for (i = 0; i < 4; i++)
1066 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1067 change = val != chip->dig_pcm_status;
1068 chip->dig_pcm_status = val;
1069 spin_unlock_irq(&chip->reg_lock);
1070 return change;
1071}
1072
1073static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata =
1074{
1075 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1076 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1077 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1078 .info = snd_cmipci_spdif_stream_info,
1079 .get = snd_cmipci_spdif_stream_get,
1080 .put = snd_cmipci_spdif_stream_put
1081};
1082
1083/*
1084 */
1085
1086/* save mixer setting and mute for AC3 playback */
1087static int save_mixer_state(cmipci_t *cm)
1088{
1089 if (! cm->mixer_insensitive) {
1090 snd_ctl_elem_value_t *val;
1091 unsigned int i;
1092
1093 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1094 if (!val)
1095 return -ENOMEM;
1096 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1097 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1098 if (ctl) {
1099 int event;
1100 memset(val, 0, sizeof(*val));
1101 ctl->get(ctl, val);
1102 cm->mixer_res_status[i] = val->value.integer.value[0];
1103 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1104 event = SNDRV_CTL_EVENT_MASK_INFO;
1105 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1106 ctl->put(ctl, val); /* toggle */
1107 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1108 }
1109 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1110 snd_ctl_notify(cm->card, event, &ctl->id);
1111 }
1112 }
1113 kfree(val);
1114 cm->mixer_insensitive = 1;
1115 }
1116 return 0;
1117}
1118
1119
1120/* restore the previously saved mixer status */
1121static void restore_mixer_state(cmipci_t *cm)
1122{
1123 if (cm->mixer_insensitive) {
1124 snd_ctl_elem_value_t *val;
1125 unsigned int i;
1126
1127 val = kmalloc(sizeof(*val), GFP_KERNEL);
1128 if (!val)
1129 return;
1130 cm->mixer_insensitive = 0; /* at first clear this;
1131 otherwise the changes will be ignored */
1132 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1133 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1134 if (ctl) {
1135 int event;
1136
1137 memset(val, 0, sizeof(*val));
1138 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1139 ctl->get(ctl, val);
1140 event = SNDRV_CTL_EVENT_MASK_INFO;
1141 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1142 val->value.integer.value[0] = cm->mixer_res_status[i];
1143 ctl->put(ctl, val);
1144 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1145 }
1146 snd_ctl_notify(cm->card, event, &ctl->id);
1147 }
1148 }
1149 kfree(val);
1150 }
1151}
1152
1153/* spinlock held! */
1154static void setup_ac3(cmipci_t *cm, snd_pcm_substream_t *subs, int do_ac3, int rate)
1155{
1156 if (do_ac3) {
1157 /* AC3EN for 037 */
1158 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1159 /* AC3EN for 039 */
1160 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1161
1162 if (cm->can_ac3_hw) {
1163 /* SPD24SEL for 037, 0x02 */
1164 /* SPD24SEL for 039, 0x20, but cannot be set */
1165 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1166 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1167 } else { /* can_ac3_sw */
1168 /* SPD32SEL for 037 & 039, 0x20 */
1169 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1170 /* set 176K sample rate to fix 033 HW bug */
1171 if (cm->chip_version == 33) {
1172 if (rate >= 48000) {
1173 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1174 } else {
1175 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1176 }
1177 }
1178 }
1179
1180 } else {
1181 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1182 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1183
1184 if (cm->can_ac3_hw) {
1185 /* chip model >= 37 */
1186 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1187 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1188 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1189 } else {
1190 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1191 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1192 }
1193 } else {
1194 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1195 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1196 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1197 }
1198 }
1199}
1200
1201static int setup_spdif_playback(cmipci_t *cm, snd_pcm_substream_t *subs, int up, int do_ac3)
1202{
1203 int rate, err;
1204
1205 rate = subs->runtime->rate;
1206
1207 if (up && do_ac3)
1208 if ((err = save_mixer_state(cm)) < 0)
1209 return err;
1210
1211 spin_lock_irq(&cm->reg_lock);
1212 cm->spdif_playback_avail = up;
1213 if (up) {
1214 /* they are controlled via "IEC958 Output Switch" */
1215 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1216 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1217 if (cm->spdif_playback_enabled)
1218 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1219 setup_ac3(cm, subs, do_ac3, rate);
1220
1221 if (rate == 48000)
1222 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1223 else
1224 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1225
1226 } else {
1227 /* they are controlled via "IEC958 Output Switch" */
1228 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1229 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1230 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1231 setup_ac3(cm, subs, 0, 0);
1232 }
1233 spin_unlock_irq(&cm->reg_lock);
1234 return 0;
1235}
1236
1237
1238/*
1239 * preparation
1240 */
1241
1242/* playback - enable spdif only on the certain condition */
1243static int snd_cmipci_playback_prepare(snd_pcm_substream_t *substream)
1244{
1245 cmipci_t *cm = snd_pcm_substream_chip(substream);
1246 int rate = substream->runtime->rate;
1247 int err, do_spdif, do_ac3 = 0;
1248
1249 do_spdif = ((rate == 44100 || rate == 48000) &&
1250 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1251 substream->runtime->channels == 2);
1252 if (do_spdif && cm->can_ac3_hw)
1253 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1254 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1255 return err;
1256 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1257}
1258
1259/* playback (via device #2) - enable spdif always */
1260static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t *substream)
1261{
1262 cmipci_t *cm = snd_pcm_substream_chip(substream);
1263 int err, do_ac3;
1264
1265 if (cm->can_ac3_hw)
1266 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1267 else
1268 do_ac3 = 1; /* doesn't matter */
1269 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1270 return err;
1271 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1272}
1273
1274static int snd_cmipci_playback_hw_free(snd_pcm_substream_t *substream)
1275{
1276 cmipci_t *cm = snd_pcm_substream_chip(substream);
1277 setup_spdif_playback(cm, substream, 0, 0);
1278 restore_mixer_state(cm);
1279 return snd_cmipci_hw_free(substream);
1280}
1281
1282/* capture */
1283static int snd_cmipci_capture_prepare(snd_pcm_substream_t *substream)
1284{
1285 cmipci_t *cm = snd_pcm_substream_chip(substream);
1286 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1287}
1288
1289/* capture with spdif (via device #2) */
1290static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t *substream)
1291{
1292 cmipci_t *cm = snd_pcm_substream_chip(substream);
1293
1294 spin_lock_irq(&cm->reg_lock);
1295 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1296 spin_unlock_irq(&cm->reg_lock);
1297
1298 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1299}
1300
1301static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t *subs)
1302{
1303 cmipci_t *cm = snd_pcm_substream_chip(subs);
1304
1305 spin_lock_irq(&cm->reg_lock);
1306 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1307 spin_unlock_irq(&cm->reg_lock);
1308
1309 return snd_cmipci_hw_free(subs);
1310}
1311
1312
1313/*
1314 * interrupt handler
1315 */
1316static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1317{
1318 cmipci_t *cm = dev_id;
1319 unsigned int status, mask = 0;
1320
1321 /* fastpath out, to ease interrupt sharing */
1322 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1323 if (!(status & CM_INTR))
1324 return IRQ_NONE;
1325
1326 /* acknowledge interrupt */
1327 spin_lock(&cm->reg_lock);
1328 if (status & CM_CHINT0)
1329 mask |= CM_CH0_INT_EN;
1330 if (status & CM_CHINT1)
1331 mask |= CM_CH1_INT_EN;
1332 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1333 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1334 spin_unlock(&cm->reg_lock);
1335
1336 if (cm->rmidi && (status & CM_UARTINT))
1337 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1338
1339 if (cm->pcm) {
1340 if ((status & CM_CHINT0) && cm->channel[0].running)
1341 snd_pcm_period_elapsed(cm->channel[0].substream);
1342 if ((status & CM_CHINT1) && cm->channel[1].running)
1343 snd_pcm_period_elapsed(cm->channel[1].substream);
1344 }
1345 return IRQ_HANDLED;
1346}
1347
1348/*
1349 * h/w infos
1350 */
1351
1352/* playback on channel A */
1353static snd_pcm_hardware_t snd_cmipci_playback =
1354{
1355 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1356 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1357 SNDRV_PCM_INFO_MMAP_VALID),
1358 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1359 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1360 .rate_min = 5512,
1361 .rate_max = 48000,
1362 .channels_min = 1,
1363 .channels_max = 2,
1364 .buffer_bytes_max = (128*1024),
1365 .period_bytes_min = 64,
1366 .period_bytes_max = (128*1024),
1367 .periods_min = 2,
1368 .periods_max = 1024,
1369 .fifo_size = 0,
1370};
1371
1372/* capture on channel B */
1373static snd_pcm_hardware_t snd_cmipci_capture =
1374{
1375 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1376 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1377 SNDRV_PCM_INFO_MMAP_VALID),
1378 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1379 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1380 .rate_min = 5512,
1381 .rate_max = 48000,
1382 .channels_min = 1,
1383 .channels_max = 2,
1384 .buffer_bytes_max = (128*1024),
1385 .period_bytes_min = 64,
1386 .period_bytes_max = (128*1024),
1387 .periods_min = 2,
1388 .periods_max = 1024,
1389 .fifo_size = 0,
1390};
1391
1392/* playback on channel B - stereo 16bit only? */
1393static snd_pcm_hardware_t snd_cmipci_playback2 =
1394{
1395 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1396 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1397 SNDRV_PCM_INFO_MMAP_VALID),
1398 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1399 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1400 .rate_min = 5512,
1401 .rate_max = 48000,
1402 .channels_min = 2,
1403 .channels_max = 2,
1404 .buffer_bytes_max = (128*1024),
1405 .period_bytes_min = 64,
1406 .period_bytes_max = (128*1024),
1407 .periods_min = 2,
1408 .periods_max = 1024,
1409 .fifo_size = 0,
1410};
1411
1412/* spdif playback on channel A */
1413static snd_pcm_hardware_t snd_cmipci_playback_spdif =
1414{
1415 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1416 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1417 SNDRV_PCM_INFO_MMAP_VALID),
1418 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1419 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1420 .rate_min = 44100,
1421 .rate_max = 48000,
1422 .channels_min = 2,
1423 .channels_max = 2,
1424 .buffer_bytes_max = (128*1024),
1425 .period_bytes_min = 64,
1426 .period_bytes_max = (128*1024),
1427 .periods_min = 2,
1428 .periods_max = 1024,
1429 .fifo_size = 0,
1430};
1431
1432/* spdif playback on channel A (32bit, IEC958 subframes) */
1433static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe =
1434{
1435 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1436 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1437 SNDRV_PCM_INFO_MMAP_VALID),
1438 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1439 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1440 .rate_min = 44100,
1441 .rate_max = 48000,
1442 .channels_min = 2,
1443 .channels_max = 2,
1444 .buffer_bytes_max = (128*1024),
1445 .period_bytes_min = 64,
1446 .period_bytes_max = (128*1024),
1447 .periods_min = 2,
1448 .periods_max = 1024,
1449 .fifo_size = 0,
1450};
1451
1452/* spdif capture on channel B */
1453static snd_pcm_hardware_t snd_cmipci_capture_spdif =
1454{
1455 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1456 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1457 SNDRV_PCM_INFO_MMAP_VALID),
1458 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1459 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1460 .rate_min = 44100,
1461 .rate_max = 48000,
1462 .channels_min = 2,
1463 .channels_max = 2,
1464 .buffer_bytes_max = (128*1024),
1465 .period_bytes_min = 64,
1466 .period_bytes_max = (128*1024),
1467 .periods_min = 2,
1468 .periods_max = 1024,
1469 .fifo_size = 0,
1470};
1471
1472/*
1473 * check device open/close
1474 */
1475static int open_device_check(cmipci_t *cm, int mode, snd_pcm_substream_t *subs)
1476{
1477 int ch = mode & CM_OPEN_CH_MASK;
1478
1479 /* FIXME: a file should wait until the device becomes free
1480 * when it's opened on blocking mode. however, since the current
1481 * pcm framework doesn't pass file pointer before actually opened,
1482 * we can't know whether blocking mode or not in open callback..
1483 */
1484 down(&cm->open_mutex);
1485 if (cm->opened[ch]) {
1486 up(&cm->open_mutex);
1487 return -EBUSY;
1488 }
1489 cm->opened[ch] = mode;
1490 cm->channel[ch].substream = subs;
1491 if (! (mode & CM_OPEN_DAC)) {
1492 /* disable dual DAC mode */
1493 cm->channel[ch].is_dac = 0;
1494 spin_lock_irq(&cm->reg_lock);
1495 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1496 spin_unlock_irq(&cm->reg_lock);
1497 }
1498 up(&cm->open_mutex);
1499 return 0;
1500}
1501
1502static void close_device_check(cmipci_t *cm, int mode)
1503{
1504 int ch = mode & CM_OPEN_CH_MASK;
1505
1506 down(&cm->open_mutex);
1507 if (cm->opened[ch] == mode) {
1508 if (cm->channel[ch].substream) {
1509 snd_cmipci_ch_reset(cm, ch);
1510 cm->channel[ch].running = 0;
1511 cm->channel[ch].substream = NULL;
1512 }
1513 cm->opened[ch] = 0;
1514 if (! cm->channel[ch].is_dac) {
1515 /* enable dual DAC mode again */
1516 cm->channel[ch].is_dac = 1;
1517 spin_lock_irq(&cm->reg_lock);
1518 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1519 spin_unlock_irq(&cm->reg_lock);
1520 }
1521 }
1522 up(&cm->open_mutex);
1523}
1524
1525/*
1526 */
1527
1528static int snd_cmipci_playback_open(snd_pcm_substream_t *substream)
1529{
1530 cmipci_t *cm = snd_pcm_substream_chip(substream);
1531 snd_pcm_runtime_t *runtime = substream->runtime;
1532 int err;
1533
1534 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1535 return err;
1536 runtime->hw = snd_cmipci_playback;
1537 runtime->hw.channels_max = cm->max_channels;
1538 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1539 cm->dig_pcm_status = cm->dig_status;
1540 return 0;
1541}
1542
1543static int snd_cmipci_capture_open(snd_pcm_substream_t *substream)
1544{
1545 cmipci_t *cm = snd_pcm_substream_chip(substream);
1546 snd_pcm_runtime_t *runtime = substream->runtime;
1547 int err;
1548
1549 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1550 return err;
1551 runtime->hw = snd_cmipci_capture;
1552 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1553 runtime->hw.rate_min = 41000;
1554 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1555 }
1556 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1557 return 0;
1558}
1559
1560static int snd_cmipci_playback2_open(snd_pcm_substream_t *substream)
1561{
1562 cmipci_t *cm = snd_pcm_substream_chip(substream);
1563 snd_pcm_runtime_t *runtime = substream->runtime;
1564 int err;
1565
1566 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1567 return err;
1568 runtime->hw = snd_cmipci_playback2;
1569 down(&cm->open_mutex);
1570 if (! cm->opened[CM_CH_PLAY]) {
1571 if (cm->can_multi_ch) {
1572 runtime->hw.channels_max = cm->max_channels;
1573 if (cm->max_channels == 4)
1574 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1575 else if (cm->max_channels == 6)
1576 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1577 else if (cm->max_channels == 8)
1578 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1579 }
1580 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1581 }
1582 up(&cm->open_mutex);
1583 return 0;
1584}
1585
1586static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t *substream)
1587{
1588 cmipci_t *cm = snd_pcm_substream_chip(substream);
1589 snd_pcm_runtime_t *runtime = substream->runtime;
1590 int err;
1591
1592 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1593 return err;
1594 if (cm->can_ac3_hw) {
1595 runtime->hw = snd_cmipci_playback_spdif;
1596 if (cm->chip_version >= 37)
1597 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1598 } else {
1599 runtime->hw = snd_cmipci_playback_iec958_subframe;
1600 }
1601 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1602 cm->dig_pcm_status = cm->dig_status;
1603 return 0;
1604}
1605
1606static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t * substream)
1607{
1608 cmipci_t *cm = snd_pcm_substream_chip(substream);
1609 snd_pcm_runtime_t *runtime = substream->runtime;
1610 int err;
1611
1612 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1613 return err;
1614 runtime->hw = snd_cmipci_capture_spdif;
1615 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1616 return 0;
1617}
1618
1619
1620/*
1621 */
1622
1623static int snd_cmipci_playback_close(snd_pcm_substream_t * substream)
1624{
1625 cmipci_t *cm = snd_pcm_substream_chip(substream);
1626 close_device_check(cm, CM_OPEN_PLAYBACK);
1627 return 0;
1628}
1629
1630static int snd_cmipci_capture_close(snd_pcm_substream_t * substream)
1631{
1632 cmipci_t *cm = snd_pcm_substream_chip(substream);
1633 close_device_check(cm, CM_OPEN_CAPTURE);
1634 return 0;
1635}
1636
1637static int snd_cmipci_playback2_close(snd_pcm_substream_t * substream)
1638{
1639 cmipci_t *cm = snd_pcm_substream_chip(substream);
1640 close_device_check(cm, CM_OPEN_PLAYBACK2);
1641 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1642 return 0;
1643}
1644
1645static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t * substream)
1646{
1647 cmipci_t *cm = snd_pcm_substream_chip(substream);
1648 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1649 return 0;
1650}
1651
1652static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t * substream)
1653{
1654 cmipci_t *cm = snd_pcm_substream_chip(substream);
1655 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1656 return 0;
1657}
1658
1659
1660/*
1661 */
1662
1663static snd_pcm_ops_t snd_cmipci_playback_ops = {
1664 .open = snd_cmipci_playback_open,
1665 .close = snd_cmipci_playback_close,
1666 .ioctl = snd_pcm_lib_ioctl,
1667 .hw_params = snd_cmipci_hw_params,
1668 .hw_free = snd_cmipci_playback_hw_free,
1669 .prepare = snd_cmipci_playback_prepare,
1670 .trigger = snd_cmipci_playback_trigger,
1671 .pointer = snd_cmipci_playback_pointer,
1672};
1673
1674static snd_pcm_ops_t snd_cmipci_capture_ops = {
1675 .open = snd_cmipci_capture_open,
1676 .close = snd_cmipci_capture_close,
1677 .ioctl = snd_pcm_lib_ioctl,
1678 .hw_params = snd_cmipci_hw_params,
1679 .hw_free = snd_cmipci_hw_free,
1680 .prepare = snd_cmipci_capture_prepare,
1681 .trigger = snd_cmipci_capture_trigger,
1682 .pointer = snd_cmipci_capture_pointer,
1683};
1684
1685static snd_pcm_ops_t snd_cmipci_playback2_ops = {
1686 .open = snd_cmipci_playback2_open,
1687 .close = snd_cmipci_playback2_close,
1688 .ioctl = snd_pcm_lib_ioctl,
1689 .hw_params = snd_cmipci_playback2_hw_params,
1690 .hw_free = snd_cmipci_hw_free,
1691 .prepare = snd_cmipci_capture_prepare, /* channel B */
1692 .trigger = snd_cmipci_capture_trigger, /* channel B */
1693 .pointer = snd_cmipci_capture_pointer, /* channel B */
1694};
1695
1696static snd_pcm_ops_t snd_cmipci_playback_spdif_ops = {
1697 .open = snd_cmipci_playback_spdif_open,
1698 .close = snd_cmipci_playback_spdif_close,
1699 .ioctl = snd_pcm_lib_ioctl,
1700 .hw_params = snd_cmipci_hw_params,
1701 .hw_free = snd_cmipci_playback_hw_free,
1702 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1703 .trigger = snd_cmipci_playback_trigger,
1704 .pointer = snd_cmipci_playback_pointer,
1705};
1706
1707static snd_pcm_ops_t snd_cmipci_capture_spdif_ops = {
1708 .open = snd_cmipci_capture_spdif_open,
1709 .close = snd_cmipci_capture_spdif_close,
1710 .ioctl = snd_pcm_lib_ioctl,
1711 .hw_params = snd_cmipci_hw_params,
1712 .hw_free = snd_cmipci_capture_spdif_hw_free,
1713 .prepare = snd_cmipci_capture_spdif_prepare,
1714 .trigger = snd_cmipci_capture_trigger,
1715 .pointer = snd_cmipci_capture_pointer,
1716};
1717
1718
1719/*
1720 */
1721
1722static void snd_cmipci_pcm_free(snd_pcm_t *pcm)
1723{
1724 snd_pcm_lib_preallocate_free_for_all(pcm);
1725}
1726
1727static int __devinit snd_cmipci_pcm_new(cmipci_t *cm, int device)
1728{
1729 snd_pcm_t *pcm;
1730 int err;
1731
1732 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1733 if (err < 0)
1734 return err;
1735
1736 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1737 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1738
1739 pcm->private_data = cm;
1740 pcm->private_free = snd_cmipci_pcm_free;
1741 pcm->info_flags = 0;
1742 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1743 cm->pcm = pcm;
1744
1745 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1746 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1747
1748 return 0;
1749}
1750
1751static int __devinit snd_cmipci_pcm2_new(cmipci_t *cm, int device)
1752{
1753 snd_pcm_t *pcm;
1754 int err;
1755
1756 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1757 if (err < 0)
1758 return err;
1759
1760 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1761
1762 pcm->private_data = cm;
1763 pcm->private_free = snd_cmipci_pcm_free;
1764 pcm->info_flags = 0;
1765 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1766 cm->pcm2 = pcm;
1767
1768 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1769 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1770
1771 return 0;
1772}
1773
1774static int __devinit snd_cmipci_pcm_spdif_new(cmipci_t *cm, int device)
1775{
1776 snd_pcm_t *pcm;
1777 int err;
1778
1779 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1780 if (err < 0)
1781 return err;
1782
1783 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1784 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1785
1786 pcm->private_data = cm;
1787 pcm->private_free = snd_cmipci_pcm_free;
1788 pcm->info_flags = 0;
1789 strcpy(pcm->name, "C-Media PCI IEC958");
1790 cm->pcm_spdif = pcm;
1791
1792 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1793 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1794
1795 return 0;
1796}
1797
1798/*
1799 * mixer interface:
1800 * - CM8338/8738 has a compatible mixer interface with SB16, but
1801 * lack of some elements like tone control, i/o gain and AGC.
1802 * - Access to native registers:
1803 * - A 3D switch
1804 * - Output mute switches
1805 */
1806
1807static void snd_cmipci_mixer_write(cmipci_t *s, unsigned char idx, unsigned char data)
1808{
1809 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1810 outb(data, s->iobase + CM_REG_SB16_DATA);
1811}
1812
1813static unsigned char snd_cmipci_mixer_read(cmipci_t *s, unsigned char idx)
1814{
1815 unsigned char v;
1816
1817 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1818 v = inb(s->iobase + CM_REG_SB16_DATA);
1819 return v;
1820}
1821
1822/*
1823 * general mixer element
1824 */
1825typedef struct cmipci_sb_reg {
1826 unsigned int left_reg, right_reg;
1827 unsigned int left_shift, right_shift;
1828 unsigned int mask;
1829 unsigned int invert: 1;
1830 unsigned int stereo: 1;
1831} cmipci_sb_reg_t;
1832
1833#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1834 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1835
1836#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1837{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1838 .info = snd_cmipci_info_volume, \
1839 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1840 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1841}
1842
1843#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1844#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1845#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1846#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1847
1848static void cmipci_sb_reg_decode(cmipci_sb_reg_t *r, unsigned long val)
1849{
1850 r->left_reg = val & 0xff;
1851 r->right_reg = (val >> 8) & 0xff;
1852 r->left_shift = (val >> 16) & 0x07;
1853 r->right_shift = (val >> 19) & 0x07;
1854 r->invert = (val >> 22) & 1;
1855 r->stereo = (val >> 23) & 1;
1856 r->mask = (val >> 24) & 0xff;
1857}
1858
1859static int snd_cmipci_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1860{
1861 cmipci_sb_reg_t reg;
1862
1863 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1864 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1865 uinfo->count = reg.stereo + 1;
1866 uinfo->value.integer.min = 0;
1867 uinfo->value.integer.max = reg.mask;
1868 return 0;
1869}
1870
1871static int snd_cmipci_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1872{
1873 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1874 cmipci_sb_reg_t reg;
1875 int val;
1876
1877 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1878 spin_lock_irq(&cm->reg_lock);
1879 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1880 if (reg.invert)
1881 val = reg.mask - val;
1882 ucontrol->value.integer.value[0] = val;
1883 if (reg.stereo) {
1884 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1885 if (reg.invert)
1886 val = reg.mask - val;
1887 ucontrol->value.integer.value[1] = val;
1888 }
1889 spin_unlock_irq(&cm->reg_lock);
1890 return 0;
1891}
1892
1893static int snd_cmipci_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1894{
1895 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1896 cmipci_sb_reg_t reg;
1897 int change;
1898 int left, right, oleft, oright;
1899
1900 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1901 left = ucontrol->value.integer.value[0] & reg.mask;
1902 if (reg.invert)
1903 left = reg.mask - left;
1904 left <<= reg.left_shift;
1905 if (reg.stereo) {
1906 right = ucontrol->value.integer.value[1] & reg.mask;
1907 if (reg.invert)
1908 right = reg.mask - right;
1909 right <<= reg.right_shift;
1910 } else
1911 right = 0;
1912 spin_lock_irq(&cm->reg_lock);
1913 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1914 left |= oleft & ~(reg.mask << reg.left_shift);
1915 change = left != oleft;
1916 if (reg.stereo) {
1917 if (reg.left_reg != reg.right_reg) {
1918 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1919 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1920 } else
1921 oright = left;
1922 right |= oright & ~(reg.mask << reg.right_shift);
1923 change |= right != oright;
1924 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1925 } else
1926 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1927 spin_unlock_irq(&cm->reg_lock);
1928 return change;
1929}
1930
1931/*
1932 * input route (left,right) -> (left,right)
1933 */
1934#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1935{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1936 .info = snd_cmipci_info_input_sw, \
1937 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1938 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1939}
1940
1941static int snd_cmipci_info_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1942{
1943 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1944 uinfo->count = 4;
1945 uinfo->value.integer.min = 0;
1946 uinfo->value.integer.max = 1;
1947 return 0;
1948}
1949
1950static int snd_cmipci_get_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1951{
1952 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1953 cmipci_sb_reg_t reg;
1954 int val1, val2;
1955
1956 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1957 spin_lock_irq(&cm->reg_lock);
1958 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1959 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1960 spin_unlock_irq(&cm->reg_lock);
1961 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1962 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1963 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1964 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1965 return 0;
1966}
1967
1968static int snd_cmipci_put_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1969{
1970 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1971 cmipci_sb_reg_t reg;
1972 int change;
1973 int val1, val2, oval1, oval2;
1974
1975 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1976 spin_lock_irq(&cm->reg_lock);
1977 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1978 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1979 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1980 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1981 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1982 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1983 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1984 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1985 change = val1 != oval1 || val2 != oval2;
1986 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1987 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1988 spin_unlock_irq(&cm->reg_lock);
1989 return change;
1990}
1991
1992/*
1993 * native mixer switches/volumes
1994 */
1995
1996#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1997{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1998 .info = snd_cmipci_info_native_mixer, \
1999 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2000 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2001}
2002
2003#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2004{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2005 .info = snd_cmipci_info_native_mixer, \
2006 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2007 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2008}
2009
2010#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2011{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2012 .info = snd_cmipci_info_native_mixer, \
2013 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2014 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2015}
2016
2017#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2018{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2019 .info = snd_cmipci_info_native_mixer, \
2020 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2021 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2022}
2023
2024static int snd_cmipci_info_native_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2025{
2026 cmipci_sb_reg_t reg;
2027
2028 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2029 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2030 uinfo->count = reg.stereo + 1;
2031 uinfo->value.integer.min = 0;
2032 uinfo->value.integer.max = reg.mask;
2033 return 0;
2034
2035}
2036
2037static int snd_cmipci_get_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2038{
2039 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2040 cmipci_sb_reg_t reg;
2041 unsigned char oreg, val;
2042
2043 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2044 spin_lock_irq(&cm->reg_lock);
2045 oreg = inb(cm->iobase + reg.left_reg);
2046 val = (oreg >> reg.left_shift) & reg.mask;
2047 if (reg.invert)
2048 val = reg.mask - val;
2049 ucontrol->value.integer.value[0] = val;
2050 if (reg.stereo) {
2051 val = (oreg >> reg.right_shift) & reg.mask;
2052 if (reg.invert)
2053 val = reg.mask - val;
2054 ucontrol->value.integer.value[1] = val;
2055 }
2056 spin_unlock_irq(&cm->reg_lock);
2057 return 0;
2058}
2059
2060static int snd_cmipci_put_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2061{
2062 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2063 cmipci_sb_reg_t reg;
2064 unsigned char oreg, nreg, val;
2065
2066 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2067 spin_lock_irq(&cm->reg_lock);
2068 oreg = inb(cm->iobase + reg.left_reg);
2069 val = ucontrol->value.integer.value[0] & reg.mask;
2070 if (reg.invert)
2071 val = reg.mask - val;
2072 nreg = oreg & ~(reg.mask << reg.left_shift);
2073 nreg |= (val << reg.left_shift);
2074 if (reg.stereo) {
2075 val = ucontrol->value.integer.value[1] & reg.mask;
2076 if (reg.invert)
2077 val = reg.mask - val;
2078 nreg &= ~(reg.mask << reg.right_shift);
2079 nreg |= (val << reg.right_shift);
2080 }
2081 outb(nreg, cm->iobase + reg.left_reg);
2082 spin_unlock_irq(&cm->reg_lock);
2083 return (nreg != oreg);
2084}
2085
2086/*
2087 * special case - check mixer sensitivity
2088 */
2089static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2090{
2091 //cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2092 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2093}
2094
2095static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2096{
2097 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2098 if (cm->mixer_insensitive) {
2099 /* ignored */
2100 return 0;
2101 }
2102 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2103}
2104
2105
2106static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = {
2107 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2108 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2109 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2110 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2111 { /* switch with sensitivity */
2112 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2113 .name = "PCM Playback Switch",
2114 .info = snd_cmipci_info_native_mixer,
2115 .get = snd_cmipci_get_native_mixer_sensitive,
2116 .put = snd_cmipci_put_native_mixer_sensitive,
2117 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2118 },
2119 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2120 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2121 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2122 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2123 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2124 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2125 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2126 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2127 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2128 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2129 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2130 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2131 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2132 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2133 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2134 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2135 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2136 CMIPCI_MIXER_SW_MONO("Mic Boost", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2137 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2138};
2139
2140/*
2141 * other switches
2142 */
2143
2144typedef struct snd_cmipci_switch_args {
2145 int reg; /* register index */
2146 unsigned int mask; /* mask bits */
2147 unsigned int mask_on; /* mask bits to turn on */
2148 unsigned int is_byte: 1; /* byte access? */
2149 unsigned int ac3_sensitive: 1; /* access forbidden during non-audio operation? */
2150} snd_cmipci_switch_args_t;
2151
2152static int snd_cmipci_uswitch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2153{
2154 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2155 uinfo->count = 1;
2156 uinfo->value.integer.min = 0;
2157 uinfo->value.integer.max = 1;
2158 return 0;
2159}
2160
2161static int _snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2162{
2163 unsigned int val;
2164 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2165
2166 spin_lock_irq(&cm->reg_lock);
2167 if (args->ac3_sensitive && cm->mixer_insensitive) {
2168 ucontrol->value.integer.value[0] = 0;
2169 spin_unlock_irq(&cm->reg_lock);
2170 return 0;
2171 }
2172 if (args->is_byte)
2173 val = inb(cm->iobase + args->reg);
2174 else
2175 val = snd_cmipci_read(cm, args->reg);
2176 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2177 spin_unlock_irq(&cm->reg_lock);
2178 return 0;
2179}
2180
2181static int snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2182{
2183 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2184 snd_assert(args != NULL, return -EINVAL);
2185 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2186}
2187
2188static int _snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2189{
2190 unsigned int val;
2191 int change;
2192 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2193
2194 spin_lock_irq(&cm->reg_lock);
2195 if (args->ac3_sensitive && cm->mixer_insensitive) {
2196 /* ignored */
2197 spin_unlock_irq(&cm->reg_lock);
2198 return 0;
2199 }
2200 if (args->is_byte)
2201 val = inb(cm->iobase + args->reg);
2202 else
2203 val = snd_cmipci_read(cm, args->reg);
2204 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2205 if (change) {
2206 val &= ~args->mask;
2207 if (ucontrol->value.integer.value[0])
2208 val |= args->mask_on;
2209 else
2210 val |= (args->mask & ~args->mask_on);
2211 if (args->is_byte)
2212 outb((unsigned char)val, cm->iobase + args->reg);
2213 else
2214 snd_cmipci_write(cm, args->reg, val);
2215 }
2216 spin_unlock_irq(&cm->reg_lock);
2217 return change;
2218}
2219
2220static int snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2221{
2222 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2223 snd_assert(args != NULL, return -EINVAL);
2224 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2225}
2226
2227#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2228static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \
2229 .reg = xreg, \
2230 .mask = xmask, \
2231 .mask_on = xmask_on, \
2232 .is_byte = xis_byte, \
2233 .ac3_sensitive = xac3, \
2234}
2235
2236#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2237 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2238
2239#if 0 /* these will be controlled in pcm device */
2240DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2241DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2242#endif
2243DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2244DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2245DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2246DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2247DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2248DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2249DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2250DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2251// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2252DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2253DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2254/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2255DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2256DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2257#if CM_CH_PLAY == 1
2258DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2259#else
2260DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2261#endif
2262DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
01d25d46
TI		 2263// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2264// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
1da177e4
LT		 2265// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2266DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2267
2268#define DEFINE_SWITCH(sname, stype, sarg) \
2269{ .name = sname, \
2270 .iface = stype, \
2271 .info = snd_cmipci_uswitch_info, \
2272 .get = snd_cmipci_uswitch_get, \
2273 .put = snd_cmipci_uswitch_put, \
2274 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2275}
2276
2277#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2278#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2279
2280
2281/*
2282 * callbacks for spdif output switch
2283 * needs toggle two registers..
2284 */
2285static int snd_cmipci_spdout_enable_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2286{
2287 int changed;
2288 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2289 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2290 return changed;
2291}
2292
2293static int snd_cmipci_spdout_enable_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2294{
2295 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
2296 int changed;
2297 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2298 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2299 if (changed) {
2300 if (ucontrol->value.integer.value[0]) {
2301 if (chip->spdif_playback_avail)
2302 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2303 } else {
2304 if (chip->spdif_playback_avail)
2305 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2306 }
2307 }
2308 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2309 return changed;
2310}
2311
2312
01d25d46
TI		 2313static int snd_cmipci_line_in_mode_info(snd_kcontrol_t *kcontrol,
2314 snd_ctl_elem_info_t *uinfo)
2315{
2316 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2317 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2318 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2319 uinfo->count = 1;
2320 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2321 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2322 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2323 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2324 return 0;
2325}
2326
2327static inline unsigned int get_line_in_mode(cmipci_t *cm)
2328{
2329 unsigned int val;
2330 if (cm->chip_version >= 39) {
2331 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2332 if (val & CM_LINE_AS_BASS)
2333 return 2;
2334 }
2335 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2336 if (val & CM_SPK4)
2337 return 1;
2338 return 0;
2339}
2340
2341static int snd_cmipci_line_in_mode_get(snd_kcontrol_t *kcontrol,
2342 snd_ctl_elem_value_t *ucontrol)
2343{
2344 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2345
2346 spin_lock_irq(&cm->reg_lock);
2347 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2348 spin_unlock_irq(&cm->reg_lock);
2349 return 0;
2350}
2351
2352static int snd_cmipci_line_in_mode_put(snd_kcontrol_t *kcontrol,
2353 snd_ctl_elem_value_t *ucontrol)
2354{
2355 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2356 int change;
2357
2358 spin_lock_irq(&cm->reg_lock);
2359 if (ucontrol->value.enumerated.item[0] == 2)
2360 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2361 else
2362 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2363 if (ucontrol->value.enumerated.item[0] == 1)
2364 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2365 else
2366 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2367 spin_unlock_irq(&cm->reg_lock);
2368 return change;
2369}
2370
2371static int snd_cmipci_mic_in_mode_info(snd_kcontrol_t *kcontrol,
2372 snd_ctl_elem_info_t *uinfo)
2373{
2374 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2375 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2376 uinfo->count = 1;
2377 uinfo->value.enumerated.items = 2;
2378 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2379 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2380 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2381 return 0;
2382}
2383
2384static int snd_cmipci_mic_in_mode_get(snd_kcontrol_t *kcontrol,
2385 snd_ctl_elem_value_t *ucontrol)
2386{
2387 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2388 /* same bit as spdi_phase */
2389 spin_lock_irq(&cm->reg_lock);
2390 ucontrol->value.enumerated.item[0] =
2391 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2392 spin_unlock_irq(&cm->reg_lock);
2393 return 0;
2394}
2395
2396static int snd_cmipci_mic_in_mode_put(snd_kcontrol_t *kcontrol,
2397 snd_ctl_elem_value_t *ucontrol)
2398{
2399 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2400 int change;
2401
2402 spin_lock_irq(&cm->reg_lock);
2403 if (ucontrol->value.enumerated.item[0])
2404 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2405 else
2406 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2407 spin_unlock_irq(&cm->reg_lock);
2408 return change;
2409}
2410
1da177e4
LT		 2411/* both for CM8338/8738 */
2412static snd_kcontrol_new_t snd_cmipci_mixer_switches[] __devinitdata = {
2413 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
01d25d46
TI		 2414 {
2415 .name = "Line-In Mode",
2416 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2417 .info = snd_cmipci_line_in_mode_info,
2418 .get = snd_cmipci_line_in_mode_get,
2419 .put = snd_cmipci_line_in_mode_put,
2420 },
1da177e4
LT		 2421};
2422
2423/* for non-multichannel chips */
2424static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata =
2425DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2426
2427/* only for CM8738 */
2428static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches[] __devinitdata = {
2429#if 0 /* controlled in pcm device */
2430 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2431 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2432 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2433#endif
2434 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2435 { .name = "IEC958 Output Switch",
2436 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2437 .info = snd_cmipci_uswitch_info,
2438 .get = snd_cmipci_spdout_enable_get,
2439 .put = snd_cmipci_spdout_enable_put,
2440 },
2441 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2442 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2443 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2444// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2445 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2446 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2447};
2448
2449/* only for model 033/037 */
2450static snd_kcontrol_new_t snd_cmipci_old_mixer_switches[] __devinitdata = {
2451 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2452 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2453 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2454};
2455
2456/* only for model 039 or later */
2457static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches[] __devinitdata = {
1da177e4
LT		 2458 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2459 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
01d25d46
TI		 2460 {
2461 .name = "Mic-In Mode",
2462 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2463 .info = snd_cmipci_mic_in_mode_info,
2464 .get = snd_cmipci_mic_in_mode_get,
2465 .put = snd_cmipci_mic_in_mode_put,
2466 }
1da177e4
LT		 2467};
2468
2469/* card control switches */
2470static snd_kcontrol_new_t snd_cmipci_control_switches[] __devinitdata = {
2471 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2472 DEFINE_CARD_SWITCH("Modem", modem),
2473};
2474
2475
2476static int __devinit snd_cmipci_mixer_new(cmipci_t *cm, int pcm_spdif_device)
2477{
2478 snd_card_t *card;
2479 snd_kcontrol_new_t *sw;
2480 snd_kcontrol_t *kctl;
2481 unsigned int idx;
2482 int err;
2483
2484 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2485
2486 card = cm->card;
2487
2488 strcpy(card->mixername, "CMedia PCI");
2489
2490 spin_lock_irq(&cm->reg_lock);
2491 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2492 spin_unlock_irq(&cm->reg_lock);
2493
2494 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2495 if (cm->chip_version == 68) { // 8768 has no PCM volume
2496 if (!strcmp(snd_cmipci_mixers[idx].name,
2497 "PCM Playback Volume"))
2498 continue;
2499 }
2500 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2501 return err;
2502 }
2503
2504 /* mixer switches */
2505 sw = snd_cmipci_mixer_switches;
2506 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2507 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2508 if (err < 0)
2509 return err;
2510 }
2511 if (! cm->can_multi_ch) {
2512 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2513 if (err < 0)
2514 return err;
2515 }
2516 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2517 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2518 sw = snd_cmipci_8738_mixer_switches;
2519 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2520 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2521 if (err < 0)
2522 return err;
2523 }
2524 if (cm->can_ac3_hw) {
2525 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2526 return err;
2527 kctl->id.device = pcm_spdif_device;
2528 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2529 return err;
2530 kctl->id.device = pcm_spdif_device;
2531 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2532 return err;
2533 kctl->id.device = pcm_spdif_device;
2534 }
2535 if (cm->chip_version <= 37) {
2536 sw = snd_cmipci_old_mixer_switches;
2537 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2538 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2539 if (err < 0)
2540 return err;
2541 }
2542 }
2543 }
2544 if (cm->chip_version >= 39) {
2545 sw = snd_cmipci_extra_mixer_switches;
2546 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2547 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2548 if (err < 0)
2549 return err;
2550 }
2551 }
2552
2553 /* card switches */
2554 sw = snd_cmipci_control_switches;
2555 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2556 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2557 if (err < 0)
2558 return err;
2559 }
2560
2561 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2562 snd_ctl_elem_id_t id;
2563 snd_kcontrol_t *ctl;
2564 memset(&id, 0, sizeof(id));
2565 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2566 strcpy(id.name, cm_saved_mixer[idx].name);
2567 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2568 cm->mixer_res_ctl[idx] = ctl;
2569 }
2570
2571 return 0;
2572}
2573
2574
2575/*
2576 * proc interface
2577 */
2578
2579#ifdef CONFIG_PROC_FS
2580static void snd_cmipci_proc_read(snd_info_entry_t *entry,
2581 snd_info_buffer_t *buffer)
2582{
2583 cmipci_t *cm = entry->private_data;
2584 int i;
2585
2586 snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2587 for (i = 0; i < 0x40; i++) {
2588 int v = inb(cm->iobase + i);
2589 if (i % 4 == 0)
2590 snd_iprintf(buffer, "%02x: ", i);
2591 snd_iprintf(buffer, "%02x", v);
2592 if (i % 4 == 3)
2593 snd_iprintf(buffer, "\n");
2594 else
2595 snd_iprintf(buffer, " ");
2596 }
2597}
2598
2599static void __devinit snd_cmipci_proc_init(cmipci_t *cm)
2600{
2601 snd_info_entry_t *entry;
2602
2603 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2604 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2605}
2606#else /* !CONFIG_PROC_FS */
2607static inline void snd_cmipci_proc_init(cmipci_t *cm) {}
2608#endif
2609
2610
2611static struct pci_device_id snd_cmipci_ids[] = {
2612 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2613 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2614 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2615 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2616 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2617 {0,},
2618};
2619
2620
2621/*
2622 * check chip version and capabilities
2623 * driver name is modified according to the chip model
2624 */
2625static void __devinit query_chip(cmipci_t *cm)
2626{
2627 unsigned int detect;
2628
2629 /* check reg 0Ch, bit 24-31 */
2630 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2631 if (! detect) {
2632 /* check reg 08h, bit 24-28 */
2633 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2634 if (! detect) {
2635 cm->chip_version = 33;
2636 cm->max_channels = 2;
2637 if (cm->do_soft_ac3)
2638 cm->can_ac3_sw = 1;
2639 else
2640 cm->can_ac3_hw = 1;
2641 cm->has_dual_dac = 1;
2642 } else {
2643 cm->chip_version = 37;
2644 cm->max_channels = 2;
2645 cm->can_ac3_hw = 1;
2646 cm->has_dual_dac = 1;
2647 }
2648 } else {
2649 /* check reg 0Ch, bit 26 */
2650 if (detect & CM_CHIP_8768) {
2651 cm->chip_version = 68;
2652 cm->max_channels = 8;
2653 cm->can_ac3_hw = 1;
2654 cm->has_dual_dac = 1;
2655 cm->can_multi_ch = 1;
2656 } else if (detect & CM_CHIP_055) {
2657 cm->chip_version = 55;
2658 cm->max_channels = 6;
2659 cm->can_ac3_hw = 1;
2660 cm->has_dual_dac = 1;
2661 cm->can_multi_ch = 1;
2662 } else if (detect & CM_CHIP_039) {
2663 cm->chip_version = 39;
2664 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2665 cm->max_channels = 6;
2666 else
2667 cm->max_channels = 4;
2668 cm->can_ac3_hw = 1;
2669 cm->has_dual_dac = 1;
2670 cm->can_multi_ch = 1;
2671 } else {
2672 printk(KERN_ERR "chip %x version not supported\n", detect);
2673 }
2674 }
2675}
2676
2677#ifdef SUPPORT_JOYSTICK
2678static int __devinit snd_cmipci_create_gameport(cmipci_t *cm, int dev)
2679{
2680 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2681 struct gameport *gp;
2682 struct resource *r = NULL;
2683 int i, io_port = 0;
2684
2685 if (joystick_port[dev] == 0)
2686 return -ENODEV;
2687
2688 if (joystick_port[dev] == 1) { /* auto-detect */
2689 for (i = 0; ports[i]; i++) {
2690 io_port = ports[i];
2691 r = request_region(io_port, 1, "CMIPCI gameport");
2692 if (r)
2693 break;
2694 }
2695 } else {
2696 io_port = joystick_port[dev];
2697 r = request_region(io_port, 1, "CMIPCI gameport");
2698 }
2699
2700 if (!r) {
2701 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2702 return -EBUSY;
2703 }
2704
2705 cm->gameport = gp = gameport_allocate_port();
2706 if (!gp) {
2707 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2708 release_resource(r);
2709 kfree_nocheck(r);
2710 return -ENOMEM;
2711 }
2712 gameport_set_name(gp, "C-Media Gameport");
2713 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2714 gameport_set_dev_parent(gp, &cm->pci->dev);
2715 gp->io = io_port;
2716 gameport_set_port_data(gp, r);
2717
2718 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2719
2720 gameport_register_port(cm->gameport);
2721
2722 return 0;
2723}
2724
2725static void snd_cmipci_free_gameport(cmipci_t *cm)
2726{
2727 if (cm->gameport) {
2728 struct resource *r = gameport_get_port_data(cm->gameport);
2729
2730 gameport_unregister_port(cm->gameport);
2731 cm->gameport = NULL;
2732
2733 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2734 release_resource(r);
2735 kfree_nocheck(r);
2736 }
2737}
2738#else
2739static inline int snd_cmipci_create_gameport(cmipci_t *cm, int dev) { return -ENOSYS; }
2740static inline void snd_cmipci_free_gameport(cmipci_t *cm) { }
2741#endif
2742
2743static int snd_cmipci_free(cmipci_t *cm)
2744{
2745 if (cm->irq >= 0) {
2746 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2747 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2748 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2749 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2750 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2751 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2752 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2753
2754 /* reset mixer */
2755 snd_cmipci_mixer_write(cm, 0, 0);
2756
2757 synchronize_irq(cm->irq);
2758
2759 free_irq(cm->irq, (void *)cm);
2760 }
2761
2762 snd_cmipci_free_gameport(cm);
2763 pci_release_regions(cm->pci);
2764 pci_disable_device(cm->pci);
2765 kfree(cm);
2766 return 0;
2767}
2768
2769static int snd_cmipci_dev_free(snd_device_t *device)
2770{
2771 cmipci_t *cm = device->device_data;
2772 return snd_cmipci_free(cm);
2773}
2774
2775static int __devinit snd_cmipci_create(snd_card_t *card, struct pci_dev *pci,
2776 int dev, cmipci_t **rcmipci)
2777{
2778 cmipci_t *cm;
2779 int err;
2780 static snd_device_ops_t ops = {
2781 .dev_free = snd_cmipci_dev_free,
2782 };
2783 unsigned int val = 0;
2784 long iomidi = mpu_port[dev];
2785 long iosynth = fm_port[dev];
2786 int pcm_index, pcm_spdif_index;
2787 static struct pci_device_id intel_82437vx[] = {
2788 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2789 { },
2790 };
2791
2792 *rcmipci = NULL;
2793
2794 if ((err = pci_enable_device(pci)) < 0)
2795 return err;
2796
2797 cm = kcalloc(1, sizeof(*cm), GFP_KERNEL);
2798 if (cm == NULL) {
2799 pci_disable_device(pci);
2800 return -ENOMEM;
2801 }
2802
2803 spin_lock_init(&cm->reg_lock);
2804 init_MUTEX(&cm->open_mutex);
2805 cm->device = pci->device;
2806 cm->card = card;
2807 cm->pci = pci;
2808 cm->irq = -1;
2809 cm->channel[0].ch = 0;
2810 cm->channel[1].ch = 1;
2811 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2812
2813 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2814 kfree(cm);
2815 pci_disable_device(pci);
2816 return err;
2817 }
2818 cm->iobase = pci_resource_start(pci, 0);
2819
2820 if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, (void *)cm)) {
2821 snd_printk("unable to grab IRQ %d\n", pci->irq);
2822 snd_cmipci_free(cm);
2823 return -EBUSY;
2824 }
2825 cm->irq = pci->irq;
2826
2827 pci_set_master(cm->pci);
2828
2829 /*
2830 * check chip version, max channels and capabilities
2831 */
2832
2833 cm->chip_version = 0;
2834 cm->max_channels = 2;
2835 cm->do_soft_ac3 = soft_ac3[dev];
2836
2837 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2838 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2839 query_chip(cm);
2840 /* added -MCx suffix for chip supporting multi-channels */
2841 if (cm->can_multi_ch)
2842 sprintf(cm->card->driver + strlen(cm->card->driver),
2843 "-MC%d", cm->max_channels);
2844 else if (cm->can_ac3_sw)
2845 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2846
2847 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2848 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2849
2850#if CM_CH_PLAY == 1
2851 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2852#else
2853 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2854#endif
2855
2856 /* initialize codec registers */
2857 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2858 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2859 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2860 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2861 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2862
2863 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2864 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2865#if CM_CH_PLAY == 1
2866 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2867#else
2868 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2869#endif
2870 /* Set Bus Master Request */
2871 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2872
2873 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2874 switch (pci->device) {
2875 case PCI_DEVICE_ID_CMEDIA_CM8738:
2876 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2877 if (!pci_dev_present(intel_82437vx))
2878 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2879 break;
2880 default:
2881 break;
2882 }
2883
2884 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2885 snd_cmipci_free(cm);
2886 return err;
2887 }
2888
2889 /* set MPU address */
2890 switch (iomidi) {
2891 case 0x320: val = CM_VMPU_320; break;
2892 case 0x310: val = CM_VMPU_310; break;
2893 case 0x300: val = CM_VMPU_300; break;
2894 case 0x330: val = CM_VMPU_330; break;
2895 default:
2896 iomidi = 0; break;
2897 }
2898 if (iomidi > 0) {
2899 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2900 /* enable UART */
2901 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2902 }
2903
2904 /* set FM address */
2905 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2906 switch (iosynth) {
2907 case 0x3E8: val |= CM_FMSEL_3E8; break;
2908 case 0x3E0: val |= CM_FMSEL_3E0; break;
2909 case 0x3C8: val |= CM_FMSEL_3C8; break;
2910 case 0x388: val |= CM_FMSEL_388; break;
2911 default:
2912 iosynth = 0; break;
2913 }
2914 if (iosynth > 0) {
2915 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2916 /* enable FM */
2917 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2918
2919 if (snd_opl3_create(card, iosynth, iosynth + 2,
2920 OPL3_HW_OPL3, 0, &cm->opl3) < 0) {
2921 printk(KERN_ERR "cmipci: no OPL device at 0x%lx, skipping...\n", iosynth);
2922 iosynth = 0;
2923 } else {
2924 if ((err = snd_opl3_hwdep_new(cm->opl3, 0, 1, &cm->opl3hwdep)) < 0) {
2925 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2926 return err;
2927 }
2928 }
2929 }
2930 if (! iosynth) {
2931 /* disable FM */
2932 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val & ~CM_FMSEL_MASK);
2933 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2934 }
2935
2936 /* reset mixer */
2937 snd_cmipci_mixer_write(cm, 0, 0);
2938
2939 snd_cmipci_proc_init(cm);
2940
2941 /* create pcm devices */
2942 pcm_index = pcm_spdif_index = 0;
2943 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2944 return err;
2945 pcm_index++;
2946 if (cm->has_dual_dac) {
2947 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2948 return err;
2949 pcm_index++;
2950 }
2951 if (cm->can_ac3_hw || cm->can_ac3_sw) {
2952 pcm_spdif_index = pcm_index;
2953 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2954 return err;
2955 }
2956
2957 /* create mixer interface & switches */
2958 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2959 return err;
2960
2961 if (iomidi > 0) {
2962 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
2963 iomidi, 0,
2964 cm->irq, 0, &cm->rmidi)) < 0) {
2965 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2966 }
2967 }
2968
2969#ifdef USE_VAR48KRATE
2970 for (val = 0; val < ARRAY_SIZE(rates); val++)
2971 snd_cmipci_set_pll(cm, rates[val], val);
2972
2973 /*
2974 * (Re-)Enable external switch spdo_48k
2975 */
2976 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2977#endif /* USE_VAR48KRATE */
2978
2979 if (snd_cmipci_create_gameport(cm, dev) < 0)
2980 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2981
2982 snd_card_set_dev(card, &pci->dev);
2983
2984 *rcmipci = cm;
2985 return 0;
2986}
2987
2988/*
2989 */
2990
2991MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
2992
2993static int __devinit snd_cmipci_probe(struct pci_dev *pci,
2994 const struct pci_device_id *pci_id)
2995{
2996 static int dev;
2997 snd_card_t *card;
2998 cmipci_t *cm;
2999 int err;
3000
3001 if (dev >= SNDRV_CARDS)
3002 return -ENODEV;
3003 if (! enable[dev]) {
3004 dev++;
3005 return -ENOENT;
3006 }
3007
3008 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3009 if (card == NULL)
3010 return -ENOMEM;
3011
3012 switch (pci->device) {
3013 case PCI_DEVICE_ID_CMEDIA_CM8738:
3014 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3015 strcpy(card->driver, "CMI8738");
3016 break;
3017 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3018 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3019 strcpy(card->driver, "CMI8338");
3020 break;
3021 default:
3022 strcpy(card->driver, "CMIPCI");
3023 break;
3024 }
3025
3026 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3027 snd_card_free(card);
3028 return err;
3029 }
3030
3031 sprintf(card->shortname, "C-Media PCI %s", card->driver);
3032 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
3033 card->shortname,
3034 cm->chip_version,
3035 cm->iobase,
3036 cm->irq);
3037
3038 //snd_printd("%s is detected\n", card->longname);
3039
3040 if ((err = snd_card_register(card)) < 0) {
3041 snd_card_free(card);
3042 return err;
3043 }
3044 pci_set_drvdata(pci, card);
3045 dev++;
3046 return 0;
3047
3048}
3049
3050static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3051{
3052 snd_card_free(pci_get_drvdata(pci));
3053 pci_set_drvdata(pci, NULL);
3054}
3055
3056
3057static struct pci_driver driver = {
3058 .name = "C-Media PCI",
3059 .id_table = snd_cmipci_ids,
3060 .probe = snd_cmipci_probe,
3061 .remove = __devexit_p(snd_cmipci_remove),
3062};
3063
3064static int __init alsa_card_cmipci_init(void)
3065{
01d25d46 3066 return pci_register_driver(&driver);
1da177e4
LT		 3067}
3068
3069static void __exit alsa_card_cmipci_exit(void)
3070{
3071 pci_unregister_driver(&driver);
3072}
3073
3074module_init(alsa_card_cmipci_init)
3075module_exit(alsa_card_cmipci_exit)
Linux 6.x block layer and io_uring tree(s)