Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168). | |
adf5931f | 3 | * Copyright (C) 2002, 2005 - 2010 by Andreas Mohr <andi AT lisas.de> |
1da177e4 LT |
4 | * |
5 | * Framework borrowed from Bart Hartgers's als4000.c. | |
6 | * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801), | |
7 | * found in a Fujitsu-Siemens PC ("Cordant", aluminum case). | |
8 | * Other versions are: | |
9 | * PCI168 A(W), sub ID 1800 | |
10 | * PCI168 A/AP, sub ID 8000 | |
11 | * Please give me feedback in case you try my driver with one of these!! | |
12 | * | |
dfbf9511 AM |
13 | * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download |
14 | * (XP/Vista do not support this card at all but every Linux distribution | |
15 | * has very good support out of the box; | |
16 | * just to make sure that the right people hit this and get to know that, | |
17 | * despite the high level of Internet ignorance - as usual :-P - | |
78df617a | 18 | * about very good support for this card - on Linux!) |
dfbf9511 | 19 | * |
1da177e4 LT |
20 | * GPL LICENSE |
21 | * This program is free software; you can redistribute it and/or modify | |
22 | * it under the terms of the GNU General Public License as published by | |
23 | * the Free Software Foundation; either version 2 of the License, or | |
24 | * (at your option) any later version. | |
25 | * | |
26 | * This program is distributed in the hope that it will be useful, | |
27 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
28 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
29 | * GNU General Public License for more details. | |
30 | ||
31 | * You should have received a copy of the GNU General Public License | |
32 | * along with this program; if not, write to the Free Software | |
33 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
34 | * | |
35 | * NOTES | |
36 | * Since Aztech does not provide any chipset documentation, | |
37 | * even on repeated request to various addresses, | |
38 | * and the answer that was finally given was negative | |
39 | * (and I was stupid enough to manage to get hold of a PCI168 soundcard | |
40 | * in the first place >:-P}), | |
41 | * I was forced to base this driver on reverse engineering | |
42 | * (3 weeks' worth of evenings filled with driver work). | |
e2f87260 | 43 | * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros) |
1da177e4 | 44 | * |
02330fba AM |
45 | * It is quite likely that the AZF3328 chip is the PCI cousin of the |
46 | * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs. | |
47 | * | |
1da177e4 | 48 | * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name |
02330fba AM |
49 | * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec, |
50 | * Fincitec acquired by National Semiconductor in 2002, together with the | |
51 | * Fincitec-related company ARSmikro) has the following features: | |
1da177e4 | 52 | * |
02330fba AM |
53 | * - compatibility & compliance: |
54 | * - Microsoft PC 97 ("PC 97 Hardware Design Guide", | |
55 | * http://www.microsoft.com/whdc/archive/pcguides.mspx) | |
56 | * - Microsoft PC 98 Baseline Audio | |
57 | * - MPU401 UART | |
58 | * - Sound Blaster Emulation (DOS Box) | |
1da177e4 | 59 | * - builtin AC97 conformant codec (SNR over 80dB) |
13769e3f AM |
60 | * Note that "conformant" != "compliant"!! this chip's mixer register layout |
61 | * *differs* from the standard AC97 layout: | |
62 | * they chose to not implement the headphone register (which is not a | |
63 | * problem since it's merely optional), yet when doing this, they committed | |
64 | * the grave sin of letting other registers follow immediately instead of | |
65 | * keeping a headphone dummy register, thereby shifting the mixer register | |
66 | * addresses illegally. So far unfortunately it looks like the very flexible | |
67 | * ALSA AC97 support is still not enough to easily compensate for such a | |
68 | * grave layout violation despite all tweaks and quirks mechanisms it offers. | |
02330fba | 69 | * - builtin genuine OPL3 - verified to work fine, 20080506 |
1da177e4 | 70 | * - full duplex 16bit playback/record at independent sampling rate |
02330fba AM |
71 | * - MPU401 (+ legacy address support, claimed by one official spec sheet) |
72 | * FIXME: how to enable legacy addr?? | |
1da177e4 | 73 | * - game port (legacy address support) |
e24a121a | 74 | * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven |
02330fba AM |
75 | * features supported). - See common term "Digital Enhanced Game Port"... |
76 | * (probably DirectInput 3.0 spec - confirm) | |
77 | * - builtin 3D enhancement (said to be YAMAHA Ymersion) | |
1da177e4 | 78 | * - built-in General DirectX timer having a 20 bits counter |
d91c64c8 | 79 | * with 1us resolution (see below!) |
02330fba | 80 | * - I2S serial output port for external DAC |
dfbf9511 | 81 | * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?] |
1da177e4 LT |
82 | * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI |
83 | * - supports hardware volume control | |
84 | * - single chip low cost solution (128 pin QFP) | |
dfbf9511 | 85 | * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip] |
1da177e4 | 86 | * required for Microsoft's logo compliance (FIXME: where?) |
02330fba AM |
87 | * At least the Trident 4D Wave DX has one bit somewhere |
88 | * to enable writes to PCI subsystem VID registers, that should be it. | |
89 | * This might easily be in extended PCI reg space, since PCI168 also has | |
90 | * some custom data starting at 0x80. What kind of config settings | |
91 | * are located in our extended PCI space anyway?? | |
1da177e4 | 92 | * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms |
dfbf9511 | 93 | * [TDA1517P chip] |
1da177e4 | 94 | * |
d91c64c8 AM |
95 | * Note that this driver now is actually *better* than the Windows driver, |
96 | * since it additionally supports the card's 1MHz DirectX timer - just try | |
97 | * the following snd-seq module parameters etc.: | |
98 | * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0 | |
99 | * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0 | |
100 | * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000 | |
101 | * - "timidity -iAv -B2,8 -Os -EFreverb=0" | |
102 | * - "pmidi -p 128:0 jazz.mid" | |
103 | * | |
02330fba AM |
104 | * OPL3 hardware playback testing, try something like: |
105 | * cat /proc/asound/hwdep | |
106 | * and | |
107 | * aconnect -o | |
108 | * Then use | |
109 | * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3 | |
110 | * where x,y is the xx-yy number as given in hwdep. | |
111 | * Then try | |
112 | * pmidi -p a:b jazz.mid | |
113 | * where a:b is the client number plus 0 usually, as given by aconnect above. | |
114 | * Oh, and make sure to unmute the FM mixer control (doh!) | |
115 | * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!) | |
116 | * despite no CPU activity, possibly due to hindering ACPI idling somehow. | |
117 | * Shouldn't be a problem of the AZF3328 chip itself, I'd hope. | |
118 | * Higher PCM / FM mixer levels seem to conflict (causes crackling), | |
119 | * at least sometimes. Maybe even use with hardware sequencer timer above :) | |
120 | * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too. | |
121 | * | |
1da177e4 LT |
122 | * Certain PCI versions of this card are susceptible to DMA traffic underruns |
123 | * in some systems (resulting in sound crackling/clicking/popping), | |
124 | * probably because they don't have a DMA FIFO buffer or so. | |
125 | * Overview (PCI ID/PCI subID/PCI rev.): | |
126 | * - no DMA crackling on SiS735: 0x50DC/0x1801/16 | |
127 | * - unknown performance: 0x50DC/0x1801/10 | |
d91c64c8 AM |
128 | * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler) |
129 | * | |
1da177e4 LT |
130 | * Crackling happens with VIA chipsets or, in my case, an SiS735, which is |
131 | * supposed to be very fast and supposed to get rid of crackling much | |
132 | * better than a VIA, yet ironically I still get crackling, like many other | |
133 | * people with the same chipset. | |
134 | * Possible remedies: | |
02330fba AM |
135 | * - use speaker (amplifier) output instead of headphone output |
136 | * (in case crackling is due to overloaded output clipping) | |
1da177e4 LT |
137 | * - plug card into a different PCI slot, preferrably one that isn't shared |
138 | * too much (this helps a lot, but not completely!) | |
139 | * - get rid of PCI VGA card, use AGP instead | |
140 | * - upgrade or downgrade BIOS | |
141 | * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX) | |
142 | * Not too helpful. | |
143 | * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS | |
02330fba | 144 | * |
1da177e4 | 145 | * BUGS |
02330fba | 146 | * - full-duplex might *still* be problematic, however a recent test was fine |
e24a121a AM |
147 | * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated |
148 | * if you set PCM output switch to "pre 3D" instead of "post 3D". | |
149 | * If this can't be set, then get a mixer application that Isn't Stupid (tm) | |
150 | * (e.g. kmix, gamix) - unfortunately several are!! | |
02330fba AM |
151 | * - locking is not entirely clean, especially the audio stream activity |
152 | * ints --> may be racy | |
153 | * - an _unconnected_ secondary joystick at the gameport will be reported | |
154 | * to be "active" (floating values, not precisely -1) due to the way we need | |
155 | * to read the Digital Enhanced Game Port. Not sure whether it is fixable. | |
156 | * | |
1da177e4 | 157 | * TODO |
dfbf9511 AM |
158 | * - use PCI_VDEVICE |
159 | * - verify driver status on x86_64 | |
160 | * - test multi-card driver operation | |
161 | * - (ab)use 1MHz DirectX timer as kernel clocksource | |
1da177e4 | 162 | * - test MPU401 MIDI playback etc. |
02330fba | 163 | * - add more power micro-management (disable various units of the card |
dfbf9511 AM |
164 | * as long as they're unused, to improve audio quality and save power). |
165 | * However this requires more I/O ports which I haven't figured out yet | |
166 | * and which thus might not even exist... | |
ca54bde3 AM |
167 | * The standard suspend/resume functionality could probably make use of |
168 | * some improvement, too... | |
1da177e4 | 169 | * - figure out what all unknown port bits are responsible for |
13769e3f AM |
170 | * - figure out some cleverly evil scheme to possibly make ALSA AC97 code |
171 | * fully accept our quite incompatible ""AC97"" mixer and thus save some | |
172 | * code (but I'm not too optimistic that doing this is possible at all) | |
02330fba | 173 | * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport. |
1da177e4 LT |
174 | */ |
175 | ||
1da177e4 LT |
176 | #include <asm/io.h> |
177 | #include <linux/init.h> | |
178 | #include <linux/pci.h> | |
179 | #include <linux/delay.h> | |
180 | #include <linux/slab.h> | |
181 | #include <linux/gameport.h> | |
182 | #include <linux/moduleparam.h> | |
910638ae | 183 | #include <linux/dma-mapping.h> |
1da177e4 LT |
184 | #include <sound/core.h> |
185 | #include <sound/control.h> | |
186 | #include <sound/pcm.h> | |
187 | #include <sound/rawmidi.h> | |
188 | #include <sound/mpu401.h> | |
189 | #include <sound/opl3.h> | |
190 | #include <sound/initval.h> | |
191 | #include "azt3328.h" | |
192 | ||
d91c64c8 | 193 | MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>"); |
1da177e4 LT |
194 | MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)"); |
195 | MODULE_LICENSE("GPL"); | |
196 | MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}"); | |
197 | ||
198 | #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) | |
02330fba | 199 | #define SUPPORT_GAMEPORT 1 |
1da177e4 LT |
200 | #endif |
201 | ||
dfbf9511 AM |
202 | /* === Debug settings === |
203 | Further diagnostic functionality than the settings below | |
adf5931f | 204 | does not need to be provided, since one can easily write a POSIX shell script |
dfbf9511 | 205 | to dump the card's I/O ports (those listed in lspci -v -v): |
adf5931f | 206 | dump() |
dfbf9511 AM |
207 | { |
208 | local descr=$1; local addr=$2; local count=$3 | |
209 | ||
210 | echo "${descr}: ${count} @ ${addr}:" | |
adf5931f AM |
211 | dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \ |
212 | 2>/dev/null| hexdump -C | |
dfbf9511 AM |
213 | } |
214 | and then use something like | |
215 | "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8", | |
216 | "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8", | |
217 | possibly within a "while true; do ... sleep 1; done" loop. | |
218 | Tweaking ports could be done using | |
219 | VALSTRING="`printf "%02x" $value`" | |
adf5931f AM |
220 | printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \ |
221 | 2>/dev/null | |
dfbf9511 AM |
222 | */ |
223 | ||
1da177e4 LT |
224 | #define DEBUG_MISC 0 |
225 | #define DEBUG_CALLS 0 | |
226 | #define DEBUG_MIXER 0 | |
78df617a | 227 | #define DEBUG_CODEC 0 |
d91c64c8 | 228 | #define DEBUG_TIMER 0 |
02330fba | 229 | #define DEBUG_GAME 0 |
78df617a | 230 | #define DEBUG_PM 0 |
1da177e4 LT |
231 | #define MIXER_TESTING 0 |
232 | ||
233 | #if DEBUG_MISC | |
78df617a | 234 | #define snd_azf3328_dbgmisc(format, args...) printk(KERN_DEBUG format, ##args) |
1da177e4 LT |
235 | #else |
236 | #define snd_azf3328_dbgmisc(format, args...) | |
02330fba | 237 | #endif |
1da177e4 LT |
238 | |
239 | #if DEBUG_CALLS | |
240 | #define snd_azf3328_dbgcalls(format, args...) printk(format, ##args) | |
78df617a AM |
241 | #define snd_azf3328_dbgcallenter() printk(KERN_DEBUG "--> %s\n", __func__) |
242 | #define snd_azf3328_dbgcallleave() printk(KERN_DEBUG "<-- %s\n", __func__) | |
1da177e4 LT |
243 | #else |
244 | #define snd_azf3328_dbgcalls(format, args...) | |
245 | #define snd_azf3328_dbgcallenter() | |
246 | #define snd_azf3328_dbgcallleave() | |
02330fba | 247 | #endif |
1da177e4 LT |
248 | |
249 | #if DEBUG_MIXER | |
ee419653 | 250 | #define snd_azf3328_dbgmixer(format, args...) printk(KERN_DEBUG format, ##args) |
1da177e4 LT |
251 | #else |
252 | #define snd_azf3328_dbgmixer(format, args...) | |
02330fba | 253 | #endif |
1da177e4 | 254 | |
78df617a AM |
255 | #if DEBUG_CODEC |
256 | #define snd_azf3328_dbgcodec(format, args...) printk(KERN_DEBUG format, ##args) | |
1da177e4 | 257 | #else |
78df617a | 258 | #define snd_azf3328_dbgcodec(format, args...) |
02330fba | 259 | #endif |
1da177e4 | 260 | |
d91c64c8 | 261 | #if DEBUG_MISC |
ee419653 | 262 | #define snd_azf3328_dbgtimer(format, args...) printk(KERN_DEBUG format, ##args) |
1da177e4 | 263 | #else |
d91c64c8 | 264 | #define snd_azf3328_dbgtimer(format, args...) |
02330fba AM |
265 | #endif |
266 | ||
267 | #if DEBUG_GAME | |
ee419653 | 268 | #define snd_azf3328_dbggame(format, args...) printk(KERN_DEBUG format, ##args) |
02330fba AM |
269 | #else |
270 | #define snd_azf3328_dbggame(format, args...) | |
271 | #endif | |
d91c64c8 | 272 | |
78df617a AM |
273 | #if DEBUG_PM |
274 | #define snd_azf3328_dbgpm(format, args...) printk(KERN_DEBUG format, ##args) | |
275 | #else | |
276 | #define snd_azf3328_dbgpm(format, args...) | |
277 | #endif | |
278 | ||
1da177e4 LT |
279 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
280 | module_param_array(index, int, NULL, 0444); | |
281 | MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard."); | |
282 | ||
283 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
284 | module_param_array(id, charp, NULL, 0444); | |
285 | MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard."); | |
286 | ||
287 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ | |
288 | module_param_array(enable, bool, NULL, 0444); | |
289 | MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard."); | |
290 | ||
d91c64c8 AM |
291 | static int seqtimer_scaling = 128; |
292 | module_param(seqtimer_scaling, int, 0444); | |
293 | MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128."); | |
1da177e4 | 294 | |
dfbf9511 | 295 | enum snd_azf3328_codec_type { |
adf5931f | 296 | /* warning: fixed indices (also used for bitmask checks!) */ |
dfbf9511 AM |
297 | AZF_CODEC_PLAYBACK = 0, |
298 | AZF_CODEC_CAPTURE = 1, | |
299 | AZF_CODEC_I2S_OUT = 2, | |
02330fba AM |
300 | }; |
301 | ||
da237f35 AM |
302 | struct snd_azf3328_codec_data { |
303 | unsigned long io_base; /* keep first! (avoid offset calc) */ | |
304 | unsigned int dma_base; /* helper to avoid an indirection in hotpath */ | |
305 | spinlock_t *lock; /* TODO: convert to our own per-codec lock member */ | |
306 | struct snd_pcm_substream *substream; | |
307 | bool running; | |
308 | enum snd_azf3328_codec_type type; | |
309 | const char *name; | |
310 | }; | |
311 | ||
95de7766 | 312 | struct snd_azf3328 { |
d91c64c8 | 313 | /* often-used fields towards beginning, then grouped */ |
02330fba | 314 | |
dfbf9511 | 315 | unsigned long ctrl_io; /* usually 0xb000, size 128 */ |
02330fba AM |
316 | unsigned long game_io; /* usually 0xb400, size 8 */ |
317 | unsigned long mpu_io; /* usually 0xb800, size 4 */ | |
318 | unsigned long opl3_io; /* usually 0xbc00, size 8 */ | |
319 | unsigned long mixer_io; /* usually 0xc000, size 64 */ | |
1da177e4 | 320 | |
d91c64c8 | 321 | spinlock_t reg_lock; |
1da177e4 | 322 | |
95de7766 | 323 | struct snd_timer *timer; |
02330fba | 324 | |
dfbf9511 AM |
325 | struct snd_pcm *pcm[3]; |
326 | ||
327 | /* playback, recording and I2S out codecs */ | |
328 | struct snd_azf3328_codec_data codecs[3]; | |
1da177e4 | 329 | |
95de7766 TI |
330 | struct snd_card *card; |
331 | struct snd_rawmidi *rmidi; | |
d91c64c8 | 332 | |
02330fba | 333 | #ifdef SUPPORT_GAMEPORT |
d91c64c8 | 334 | struct gameport *gameport; |
dfbf9511 | 335 | u16 axes[4]; |
d91c64c8 | 336 | #endif |
1da177e4 | 337 | |
d91c64c8 AM |
338 | struct pci_dev *pci; |
339 | int irq; | |
ca54bde3 | 340 | |
627d3e7a AM |
341 | /* register 0x6a is write-only, thus need to remember setting. |
342 | * If we need to add more registers here, then we might try to fold this | |
343 | * into some transparent combined shadow register handling with | |
344 | * CONFIG_PM register storage below, but that's slightly difficult. */ | |
dfbf9511 | 345 | u16 shadow_reg_ctrl_6AH; |
627d3e7a | 346 | |
ca54bde3 AM |
347 | #ifdef CONFIG_PM |
348 | /* register value containers for power management | |
78df617a AM |
349 | * Note: not always full I/O range preserved (similar to Win driver!) */ |
350 | u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4]; | |
351 | u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4]; | |
352 | u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4]; | |
353 | u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4]; | |
354 | u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4]; | |
ca54bde3 | 355 | #endif |
95de7766 | 356 | }; |
d91c64c8 | 357 | |
cebe41d4 | 358 | static DEFINE_PCI_DEVICE_TABLE(snd_azf3328_ids) = { |
1da177e4 LT |
359 | { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */ |
360 | { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */ | |
361 | { 0, } | |
362 | }; | |
363 | ||
364 | MODULE_DEVICE_TABLE(pci, snd_azf3328_ids); | |
365 | ||
02330fba AM |
366 | |
367 | static int | |
dfbf9511 | 368 | snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set) |
02330fba | 369 | { |
adf5931f AM |
370 | /* Well, strictly spoken, the inb/outb sequence isn't atomic |
371 | and would need locking. However we currently don't care | |
372 | since it potentially complicates matters. */ | |
02330fba AM |
373 | u8 prev = inb(reg), new; |
374 | ||
375 | new = (do_set) ? (prev|mask) : (prev & ~mask); | |
376 | /* we need to always write the new value no matter whether it differs | |
377 | * or not, since some register bits don't indicate their setting */ | |
378 | outb(new, reg); | |
379 | if (new != prev) | |
380 | return 1; | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
d91c64c8 | 385 | static inline void |
dfbf9511 AM |
386 | snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec, |
387 | unsigned reg, | |
388 | u8 value | |
389 | ) | |
d91c64c8 | 390 | { |
dfbf9511 | 391 | outb(value, codec->io_base + reg); |
d91c64c8 AM |
392 | } |
393 | ||
394 | static inline u8 | |
dfbf9511 | 395 | snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg) |
d91c64c8 | 396 | { |
dfbf9511 | 397 | return inb(codec->io_base + reg); |
d91c64c8 AM |
398 | } |
399 | ||
400 | static inline void | |
dfbf9511 AM |
401 | snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec, |
402 | unsigned reg, | |
403 | u16 value | |
404 | ) | |
d91c64c8 | 405 | { |
dfbf9511 | 406 | outw(value, codec->io_base + reg); |
d91c64c8 AM |
407 | } |
408 | ||
409 | static inline u16 | |
dfbf9511 | 410 | snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg) |
02330fba | 411 | { |
dfbf9511 | 412 | return inw(codec->io_base + reg); |
02330fba AM |
413 | } |
414 | ||
415 | static inline void | |
dfbf9511 AM |
416 | snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec, |
417 | unsigned reg, | |
418 | u32 value | |
419 | ) | |
02330fba | 420 | { |
dfbf9511 | 421 | outl(value, codec->io_base + reg); |
02330fba AM |
422 | } |
423 | ||
424 | static inline u32 | |
dfbf9511 AM |
425 | snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg) |
426 | { | |
427 | return inl(codec->io_base + reg); | |
428 | } | |
429 | ||
430 | static inline void | |
431 | snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) | |
d91c64c8 | 432 | { |
dfbf9511 AM |
433 | outb(value, chip->ctrl_io + reg); |
434 | } | |
435 | ||
436 | static inline u8 | |
437 | snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg) | |
438 | { | |
439 | return inb(chip->ctrl_io + reg); | |
440 | } | |
441 | ||
442 | static inline void | |
443 | snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) | |
444 | { | |
445 | outw(value, chip->ctrl_io + reg); | |
446 | } | |
447 | ||
448 | static inline void | |
449 | snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value) | |
450 | { | |
451 | outl(value, chip->ctrl_io + reg); | |
d91c64c8 AM |
452 | } |
453 | ||
454 | static inline void | |
02330fba | 455 | snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) |
d91c64c8 | 456 | { |
02330fba | 457 | outb(value, chip->game_io + reg); |
d91c64c8 AM |
458 | } |
459 | ||
460 | static inline void | |
02330fba | 461 | snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) |
1da177e4 | 462 | { |
02330fba | 463 | outw(value, chip->game_io + reg); |
1da177e4 LT |
464 | } |
465 | ||
d91c64c8 | 466 | static inline u8 |
02330fba AM |
467 | snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg) |
468 | { | |
469 | return inb(chip->game_io + reg); | |
470 | } | |
471 | ||
472 | static inline u16 | |
473 | snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg) | |
1da177e4 | 474 | { |
02330fba | 475 | return inw(chip->game_io + reg); |
1da177e4 LT |
476 | } |
477 | ||
d91c64c8 | 478 | static inline void |
02330fba | 479 | snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) |
1da177e4 | 480 | { |
02330fba | 481 | outw(value, chip->mixer_io + reg); |
d91c64c8 AM |
482 | } |
483 | ||
484 | static inline u16 | |
02330fba | 485 | snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg) |
d91c64c8 | 486 | { |
02330fba | 487 | return inw(chip->mixer_io + reg); |
1da177e4 LT |
488 | } |
489 | ||
02330fba AM |
490 | #define AZF_MUTE_BIT 0x80 |
491 | ||
dfbf9511 | 492 | static bool |
02330fba | 493 | snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip, |
dfbf9511 | 494 | unsigned reg, bool do_mute |
02330fba | 495 | ) |
1da177e4 | 496 | { |
02330fba | 497 | unsigned long portbase = chip->mixer_io + reg + 1; |
dfbf9511 | 498 | bool updated; |
1da177e4 LT |
499 | |
500 | /* the mute bit is on the *second* (i.e. right) register of a | |
501 | * left/right channel setting */ | |
02330fba AM |
502 | updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute); |
503 | ||
504 | /* indicate whether it was muted before */ | |
505 | return (do_mute) ? !updated : updated; | |
1da177e4 LT |
506 | } |
507 | ||
d91c64c8 | 508 | static void |
02330fba AM |
509 | snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, |
510 | unsigned reg, | |
511 | unsigned char dst_vol_left, | |
512 | unsigned char dst_vol_right, | |
513 | int chan_sel, int delay | |
514 | ) | |
1da177e4 | 515 | { |
02330fba | 516 | unsigned long portbase = chip->mixer_io + reg; |
1da177e4 | 517 | unsigned char curr_vol_left = 0, curr_vol_right = 0; |
02330fba AM |
518 | int left_change = 0, right_change = 0; |
519 | ||
1da177e4 | 520 | snd_azf3328_dbgcallenter(); |
02330fba AM |
521 | |
522 | if (chan_sel & SET_CHAN_LEFT) { | |
d91c64c8 | 523 | curr_vol_left = inb(portbase + 1); |
02330fba AM |
524 | |
525 | /* take care of muting flag contained in left channel */ | |
526 | if (curr_vol_left & AZF_MUTE_BIT) | |
527 | dst_vol_left |= AZF_MUTE_BIT; | |
528 | else | |
529 | dst_vol_left &= ~AZF_MUTE_BIT; | |
530 | ||
531 | left_change = (curr_vol_left > dst_vol_left) ? -1 : 1; | |
532 | } | |
533 | ||
534 | if (chan_sel & SET_CHAN_RIGHT) { | |
d91c64c8 | 535 | curr_vol_right = inb(portbase + 0); |
02330fba AM |
536 | |
537 | right_change = (curr_vol_right > dst_vol_right) ? -1 : 1; | |
538 | } | |
1da177e4 | 539 | |
e2f87260 | 540 | do { |
02330fba AM |
541 | if (left_change) { |
542 | if (curr_vol_left != dst_vol_left) { | |
543 | curr_vol_left += left_change; | |
544 | outb(curr_vol_left, portbase + 1); | |
545 | } else | |
546 | left_change = 0; | |
1da177e4 | 547 | } |
02330fba AM |
548 | if (right_change) { |
549 | if (curr_vol_right != dst_vol_right) { | |
550 | curr_vol_right += right_change; | |
551 | ||
1da177e4 LT |
552 | /* during volume change, the right channel is crackling |
553 | * somewhat more than the left channel, unfortunately. | |
554 | * This seems to be a hardware issue. */ | |
02330fba AM |
555 | outb(curr_vol_right, portbase + 0); |
556 | } else | |
557 | right_change = 0; | |
1da177e4 LT |
558 | } |
559 | if (delay) | |
560 | mdelay(delay); | |
02330fba | 561 | } while ((left_change) || (right_change)); |
1da177e4 LT |
562 | snd_azf3328_dbgcallleave(); |
563 | } | |
564 | ||
565 | /* | |
566 | * general mixer element | |
567 | */ | |
95de7766 | 568 | struct azf3328_mixer_reg { |
02330fba | 569 | unsigned reg; |
1da177e4 LT |
570 | unsigned int lchan_shift, rchan_shift; |
571 | unsigned int mask; | |
572 | unsigned int invert: 1; | |
573 | unsigned int stereo: 1; | |
574 | unsigned int enum_c: 4; | |
95de7766 | 575 | }; |
1da177e4 LT |
576 | |
577 | #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \ | |
d91c64c8 AM |
578 | ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \ |
579 | (mask << 16) | \ | |
580 | (invert << 24) | \ | |
581 | (stereo << 25) | \ | |
582 | (enum_c << 26)) | |
1da177e4 | 583 | |
95de7766 | 584 | static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val) |
1da177e4 LT |
585 | { |
586 | r->reg = val & 0xff; | |
587 | r->lchan_shift = (val >> 8) & 0x0f; | |
588 | r->rchan_shift = (val >> 12) & 0x0f; | |
589 | r->mask = (val >> 16) & 0xff; | |
590 | r->invert = (val >> 24) & 1; | |
591 | r->stereo = (val >> 25) & 1; | |
592 | r->enum_c = (val >> 26) & 0x0f; | |
593 | } | |
594 | ||
595 | /* | |
596 | * mixer switches/volumes | |
597 | */ | |
598 | ||
599 | #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \ | |
600 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
601 | .info = snd_azf3328_info_mixer, \ | |
602 | .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ | |
603 | .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \ | |
604 | } | |
605 | ||
606 | #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \ | |
607 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
608 | .info = snd_azf3328_info_mixer, \ | |
609 | .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ | |
610 | .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \ | |
611 | } | |
612 | ||
613 | #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \ | |
614 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
615 | .info = snd_azf3328_info_mixer, \ | |
616 | .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ | |
617 | .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \ | |
618 | } | |
619 | ||
620 | #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \ | |
621 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
622 | .info = snd_azf3328_info_mixer, \ | |
623 | .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ | |
624 | .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \ | |
625 | } | |
626 | ||
627 | #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \ | |
628 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
629 | .info = snd_azf3328_info_mixer_enum, \ | |
630 | .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \ | |
631 | .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \ | |
632 | } | |
633 | ||
d91c64c8 | 634 | static int |
95de7766 TI |
635 | snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol, |
636 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 | 637 | { |
95de7766 | 638 | struct azf3328_mixer_reg reg; |
1da177e4 LT |
639 | |
640 | snd_azf3328_dbgcallenter(); | |
641 | snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); | |
d91c64c8 AM |
642 | uinfo->type = reg.mask == 1 ? |
643 | SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1da177e4 LT |
644 | uinfo->count = reg.stereo + 1; |
645 | uinfo->value.integer.min = 0; | |
646 | uinfo->value.integer.max = reg.mask; | |
647 | snd_azf3328_dbgcallleave(); | |
648 | return 0; | |
649 | } | |
650 | ||
d91c64c8 | 651 | static int |
95de7766 TI |
652 | snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol, |
653 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 654 | { |
95de7766 TI |
655 | struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); |
656 | struct azf3328_mixer_reg reg; | |
dfbf9511 | 657 | u16 oreg, val; |
1da177e4 LT |
658 | |
659 | snd_azf3328_dbgcallenter(); | |
660 | snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); | |
661 | ||
d91c64c8 | 662 | oreg = snd_azf3328_mixer_inw(chip, reg.reg); |
1da177e4 LT |
663 | val = (oreg >> reg.lchan_shift) & reg.mask; |
664 | if (reg.invert) | |
665 | val = reg.mask - val; | |
666 | ucontrol->value.integer.value[0] = val; | |
667 | if (reg.stereo) { | |
668 | val = (oreg >> reg.rchan_shift) & reg.mask; | |
669 | if (reg.invert) | |
670 | val = reg.mask - val; | |
671 | ucontrol->value.integer.value[1] = val; | |
672 | } | |
d91c64c8 AM |
673 | snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx " |
674 | "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n", | |
675 | reg.reg, oreg, | |
676 | ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], | |
677 | reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo); | |
1da177e4 LT |
678 | snd_azf3328_dbgcallleave(); |
679 | return 0; | |
680 | } | |
681 | ||
d91c64c8 | 682 | static int |
95de7766 TI |
683 | snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol, |
684 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 685 | { |
95de7766 TI |
686 | struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); |
687 | struct azf3328_mixer_reg reg; | |
dfbf9511 | 688 | u16 oreg, nreg, val; |
1da177e4 LT |
689 | |
690 | snd_azf3328_dbgcallenter(); | |
691 | snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); | |
d91c64c8 | 692 | oreg = snd_azf3328_mixer_inw(chip, reg.reg); |
1da177e4 LT |
693 | val = ucontrol->value.integer.value[0] & reg.mask; |
694 | if (reg.invert) | |
695 | val = reg.mask - val; | |
696 | nreg = oreg & ~(reg.mask << reg.lchan_shift); | |
697 | nreg |= (val << reg.lchan_shift); | |
698 | if (reg.stereo) { | |
699 | val = ucontrol->value.integer.value[1] & reg.mask; | |
700 | if (reg.invert) | |
701 | val = reg.mask - val; | |
702 | nreg &= ~(reg.mask << reg.rchan_shift); | |
703 | nreg |= (val << reg.rchan_shift); | |
704 | } | |
705 | if (reg.mask >= 0x07) /* it's a volume control, so better take care */ | |
d91c64c8 AM |
706 | snd_azf3328_mixer_write_volume_gradually( |
707 | chip, reg.reg, nreg >> 8, nreg & 0xff, | |
708 | /* just set both channels, doesn't matter */ | |
709 | SET_CHAN_LEFT|SET_CHAN_RIGHT, | |
710 | 0); | |
1da177e4 | 711 | else |
d91c64c8 | 712 | snd_azf3328_mixer_outw(chip, reg.reg, nreg); |
1da177e4 | 713 | |
d91c64c8 AM |
714 | snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, " |
715 | "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n", | |
716 | reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], | |
717 | oreg, reg.lchan_shift, reg.rchan_shift, | |
718 | nreg, snd_azf3328_mixer_inw(chip, reg.reg)); | |
1da177e4 LT |
719 | snd_azf3328_dbgcallleave(); |
720 | return (nreg != oreg); | |
721 | } | |
722 | ||
d91c64c8 | 723 | static int |
95de7766 TI |
724 | snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol, |
725 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 | 726 | { |
d91c64c8 | 727 | static const char * const texts1[] = { |
13769e3f | 728 | "Mic1", "Mic2" |
d91c64c8 AM |
729 | }; |
730 | static const char * const texts2[] = { | |
13769e3f | 731 | "Mix", "Mic" |
d91c64c8 AM |
732 | }; |
733 | static const char * const texts3[] = { | |
02330fba | 734 | "Mic", "CD", "Video", "Aux", |
d91c64c8 | 735 | "Line", "Mix", "Mix Mono", "Phone" |
1da177e4 | 736 | }; |
13769e3f AM |
737 | static const char * const texts4[] = { |
738 | "pre 3D", "post 3D" | |
739 | }; | |
95de7766 | 740 | struct azf3328_mixer_reg reg; |
627d3e7a | 741 | const char * const *p = NULL; |
1da177e4 LT |
742 | |
743 | snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); | |
744 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
745 | uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1; | |
746 | uinfo->value.enumerated.items = reg.enum_c; | |
747 | if (uinfo->value.enumerated.item > reg.enum_c - 1U) | |
748 | uinfo->value.enumerated.item = reg.enum_c - 1U; | |
e2f87260 | 749 | if (reg.reg == IDX_MIXER_ADVCTL2) { |
13769e3f AM |
750 | switch(reg.lchan_shift) { |
751 | case 8: /* modem out sel */ | |
627d3e7a | 752 | p = texts1; |
13769e3f AM |
753 | break; |
754 | case 9: /* mono sel source */ | |
627d3e7a | 755 | p = texts2; |
13769e3f AM |
756 | break; |
757 | case 15: /* PCM Out Path */ | |
627d3e7a | 758 | p = texts4; |
13769e3f AM |
759 | break; |
760 | } | |
e2f87260 | 761 | } else |
02330fba | 762 | if (reg.reg == IDX_MIXER_REC_SELECT) |
627d3e7a | 763 | p = texts3; |
02330fba | 764 | |
627d3e7a | 765 | strcpy(uinfo->value.enumerated.name, p[uinfo->value.enumerated.item]); |
1da177e4 LT |
766 | return 0; |
767 | } | |
768 | ||
d91c64c8 | 769 | static int |
95de7766 TI |
770 | snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol, |
771 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 772 | { |
95de7766 TI |
773 | struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); |
774 | struct azf3328_mixer_reg reg; | |
1da177e4 | 775 | unsigned short val; |
02330fba | 776 | |
1da177e4 | 777 | snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); |
d91c64c8 | 778 | val = snd_azf3328_mixer_inw(chip, reg.reg); |
e2f87260 | 779 | if (reg.reg == IDX_MIXER_REC_SELECT) { |
1da177e4 LT |
780 | ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1); |
781 | ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1); | |
e2f87260 | 782 | } else |
1da177e4 | 783 | ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1); |
d91c64c8 AM |
784 | |
785 | snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n", | |
786 | reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1], | |
787 | reg.lchan_shift, reg.enum_c); | |
1da177e4 LT |
788 | return 0; |
789 | } | |
790 | ||
d91c64c8 | 791 | static int |
95de7766 TI |
792 | snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol, |
793 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 794 | { |
95de7766 TI |
795 | struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); |
796 | struct azf3328_mixer_reg reg; | |
dfbf9511 | 797 | u16 oreg, nreg, val; |
02330fba | 798 | |
1da177e4 | 799 | snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); |
d91c64c8 | 800 | oreg = snd_azf3328_mixer_inw(chip, reg.reg); |
1da177e4 | 801 | val = oreg; |
e2f87260 | 802 | if (reg.reg == IDX_MIXER_REC_SELECT) { |
1da177e4 LT |
803 | if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U || |
804 | ucontrol->value.enumerated.item[1] > reg.enum_c - 1U) | |
805 | return -EINVAL; | |
806 | val = (ucontrol->value.enumerated.item[0] << 8) | | |
807 | (ucontrol->value.enumerated.item[1] << 0); | |
e2f87260 | 808 | } else { |
1da177e4 LT |
809 | if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U) |
810 | return -EINVAL; | |
811 | val &= ~((reg.enum_c - 1) << reg.lchan_shift); | |
812 | val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift); | |
813 | } | |
d91c64c8 | 814 | snd_azf3328_mixer_outw(chip, reg.reg, val); |
1da177e4 LT |
815 | nreg = val; |
816 | ||
817 | snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg); | |
818 | return (nreg != oreg); | |
819 | } | |
820 | ||
1b60f6b0 | 821 | static struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = { |
1da177e4 LT |
822 | AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1), |
823 | AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1), | |
627d3e7a AM |
824 | AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1), |
825 | AZF3328_MIXER_VOL_STEREO("PCM Playback Volume", | |
826 | IDX_MIXER_WAVEOUT, 0x1f, 1), | |
827 | AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch", | |
828 | IDX_MIXER_ADVCTL2, 7, 1), | |
1da177e4 LT |
829 | AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1), |
830 | AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1), | |
831 | AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1), | |
832 | AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1), | |
833 | AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1), | |
834 | AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0), | |
835 | AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0), | |
836 | AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1), | |
837 | AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1), | |
838 | AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0), | |
839 | AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1), | |
840 | AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1), | |
d355c82a JK |
841 | AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1), |
842 | AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1), | |
1da177e4 LT |
843 | AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1), |
844 | AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1), | |
845 | AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1), | |
846 | AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1), | |
847 | AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1), | |
848 | AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1), | |
849 | AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1), | |
850 | AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1), | |
13769e3f AM |
851 | AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8), |
852 | AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9), | |
e24a121a | 853 | AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */ |
1da177e4 LT |
854 | AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0), |
855 | AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0), | |
d91c64c8 | 856 | AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0), |
13769e3f AM |
857 | AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */ |
858 | AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */ | |
1da177e4 LT |
859 | #if MIXER_TESTING |
860 | AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0), | |
861 | AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0), | |
862 | AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0), | |
863 | AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0), | |
864 | AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0), | |
865 | AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0), | |
866 | AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0), | |
867 | AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0), | |
868 | AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0), | |
869 | AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0), | |
870 | AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0), | |
871 | AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0), | |
872 | AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0), | |
873 | AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0), | |
874 | AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0), | |
875 | AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0), | |
876 | #endif | |
877 | }; | |
878 | ||
1b60f6b0 | 879 | static u16 __devinitdata snd_azf3328_init_values[][2] = { |
1da177e4 LT |
880 | { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f }, |
881 | { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f }, | |
882 | { IDX_MIXER_BASSTREBLE, 0x0000 }, | |
883 | { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f }, | |
884 | { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f }, | |
885 | { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f }, | |
886 | { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f }, | |
887 | { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f }, | |
888 | { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f }, | |
889 | { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f }, | |
890 | { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f }, | |
891 | { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f }, | |
892 | { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 }, | |
893 | }; | |
894 | ||
d91c64c8 | 895 | static int __devinit |
95de7766 | 896 | snd_azf3328_mixer_new(struct snd_azf3328 *chip) |
1da177e4 | 897 | { |
95de7766 TI |
898 | struct snd_card *card; |
899 | const struct snd_kcontrol_new *sw; | |
1da177e4 LT |
900 | unsigned int idx; |
901 | int err; | |
902 | ||
903 | snd_azf3328_dbgcallenter(); | |
da3cec35 TI |
904 | if (snd_BUG_ON(!chip || !chip->card)) |
905 | return -EINVAL; | |
1da177e4 LT |
906 | |
907 | card = chip->card; | |
908 | ||
909 | /* mixer reset */ | |
d91c64c8 | 910 | snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); |
1da177e4 LT |
911 | |
912 | /* mute and zero volume channels */ | |
02330fba | 913 | for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) { |
d91c64c8 AM |
914 | snd_azf3328_mixer_outw(chip, |
915 | snd_azf3328_init_values[idx][0], | |
916 | snd_azf3328_init_values[idx][1]); | |
1da177e4 | 917 | } |
02330fba | 918 | |
1da177e4 LT |
919 | /* add mixer controls */ |
920 | sw = snd_azf3328_mixer_controls; | |
02330fba AM |
921 | for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); |
922 | ++idx, ++sw) { | |
1da177e4 LT |
923 | if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0) |
924 | return err; | |
925 | } | |
926 | snd_component_add(card, "AZF3328 mixer"); | |
927 | strcpy(card->mixername, "AZF3328 mixer"); | |
928 | ||
929 | snd_azf3328_dbgcallleave(); | |
930 | return 0; | |
931 | } | |
932 | ||
d91c64c8 | 933 | static int |
95de7766 TI |
934 | snd_azf3328_hw_params(struct snd_pcm_substream *substream, |
935 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 LT |
936 | { |
937 | int res; | |
938 | snd_azf3328_dbgcallenter(); | |
939 | res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
940 | snd_azf3328_dbgcallleave(); | |
941 | return res; | |
942 | } | |
943 | ||
d91c64c8 | 944 | static int |
95de7766 | 945 | snd_azf3328_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
946 | { |
947 | snd_azf3328_dbgcallenter(); | |
948 | snd_pcm_lib_free_pages(substream); | |
949 | snd_azf3328_dbgcallleave(); | |
950 | return 0; | |
951 | } | |
952 | ||
d91c64c8 | 953 | static void |
da237f35 | 954 | snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec, |
627d3e7a | 955 | enum azf_freq_t bitrate, |
1da177e4 LT |
956 | unsigned int format_width, |
957 | unsigned int channels | |
958 | ) | |
959 | { | |
1da177e4 | 960 | unsigned long flags; |
dfbf9511 | 961 | u16 val = 0xff00; |
8d9a114e | 962 | u8 freq = 0; |
1da177e4 LT |
963 | |
964 | snd_azf3328_dbgcallenter(); | |
965 | switch (bitrate) { | |
8d9a114e AM |
966 | #define AZF_FMT_XLATE(in_freq, out_bits) \ |
967 | do { \ | |
968 | case AZF_FREQ_ ## in_freq: \ | |
969 | freq = SOUNDFORMAT_FREQ_ ## out_bits; \ | |
970 | break; \ | |
971 | } while (0); | |
972 | AZF_FMT_XLATE(4000, SUSPECTED_4000) | |
973 | AZF_FMT_XLATE(4800, SUSPECTED_4800) | |
974 | /* the AZF3328 names it "5510" for some strange reason: */ | |
975 | AZF_FMT_XLATE(5512, 5510) | |
976 | AZF_FMT_XLATE(6620, 6620) | |
977 | AZF_FMT_XLATE(8000, 8000) | |
978 | AZF_FMT_XLATE(9600, 9600) | |
979 | AZF_FMT_XLATE(11025, 11025) | |
980 | AZF_FMT_XLATE(13240, SUSPECTED_13240) | |
981 | AZF_FMT_XLATE(16000, 16000) | |
982 | AZF_FMT_XLATE(22050, 22050) | |
983 | AZF_FMT_XLATE(32000, 32000) | |
1da177e4 | 984 | default: |
99b359ba | 985 | snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate); |
02330fba | 986 | /* fall-through */ |
8d9a114e AM |
987 | AZF_FMT_XLATE(44100, 44100) |
988 | AZF_FMT_XLATE(48000, 48000) | |
989 | AZF_FMT_XLATE(66200, SUSPECTED_66200) | |
990 | #undef AZF_FMT_XLATE | |
1da177e4 | 991 | } |
d91c64c8 AM |
992 | /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */ |
993 | /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */ | |
994 | /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */ | |
995 | /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */ | |
1da177e4 LT |
996 | /* val = 0xff05; 5m11.556s (... -> 44100Hz) */ |
997 | /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */ | |
998 | /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */ | |
999 | /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */ | |
1000 | /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */ | |
d91c64c8 | 1001 | |
8d9a114e AM |
1002 | val |= freq; |
1003 | ||
1da177e4 LT |
1004 | if (channels == 2) |
1005 | val |= SOUNDFORMAT_FLAG_2CHANNELS; | |
1006 | ||
1007 | if (format_width == 16) | |
1008 | val |= SOUNDFORMAT_FLAG_16BIT; | |
1009 | ||
da237f35 | 1010 | spin_lock_irqsave(codec->lock, flags); |
02330fba | 1011 | |
1da177e4 | 1012 | /* set bitrate/format */ |
dfbf9511 | 1013 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val); |
02330fba | 1014 | |
1da177e4 LT |
1015 | /* changing the bitrate/format settings switches off the |
1016 | * audio output with an annoying click in case of 8/16bit format change | |
1017 | * (maybe shutting down DAC/ADC?), thus immediately | |
1018 | * do some tweaking to reenable it and get rid of the clicking | |
1019 | * (FIXME: yes, it works, but what exactly am I doing here?? :) | |
1020 | * FIXME: does this have some side effects for full-duplex | |
1021 | * or other dramatic side effects? */ | |
adf5931f | 1022 | /* do it for non-capture codecs only */ |
da237f35 | 1023 | if (codec->type != AZF_CODEC_CAPTURE) |
dfbf9511 AM |
1024 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, |
1025 | snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) | | |
1026 | DMA_RUN_SOMETHING1 | | |
1027 | DMA_RUN_SOMETHING2 | | |
d91c64c8 AM |
1028 | SOMETHING_ALMOST_ALWAYS_SET | |
1029 | DMA_EPILOGUE_SOMETHING | | |
1030 | DMA_SOMETHING_ELSE | |
1031 | ); | |
1da177e4 | 1032 | |
da237f35 | 1033 | spin_unlock_irqrestore(codec->lock, flags); |
1da177e4 LT |
1034 | snd_azf3328_dbgcallleave(); |
1035 | } | |
1036 | ||
02330fba | 1037 | static inline void |
da237f35 | 1038 | snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec |
02330fba AM |
1039 | ) |
1040 | { | |
1041 | /* choose lowest frequency for low power consumption. | |
1042 | * While this will cause louder noise due to rather coarse frequency, | |
1043 | * it should never matter since output should always | |
1044 | * get disabled properly when idle anyway. */ | |
da237f35 | 1045 | snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1); |
02330fba AM |
1046 | } |
1047 | ||
627d3e7a | 1048 | static void |
dfbf9511 | 1049 | snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip, |
627d3e7a | 1050 | unsigned bitmask, |
dfbf9511 | 1051 | bool enable |
627d3e7a AM |
1052 | ) |
1053 | { | |
78df617a AM |
1054 | bool do_mask = !enable; |
1055 | if (do_mask) | |
dfbf9511 | 1056 | chip->shadow_reg_ctrl_6AH |= bitmask; |
78df617a AM |
1057 | else |
1058 | chip->shadow_reg_ctrl_6AH &= ~bitmask; | |
1059 | snd_azf3328_dbgcodec("6AH_update mask 0x%04x do_mask %d: val 0x%04x\n", | |
1060 | bitmask, do_mask, chip->shadow_reg_ctrl_6AH); | |
dfbf9511 | 1061 | snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH); |
627d3e7a AM |
1062 | } |
1063 | ||
02330fba | 1064 | static inline void |
dfbf9511 | 1065 | snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable) |
02330fba | 1066 | { |
78df617a | 1067 | snd_azf3328_dbgcodec("codec_enable %d\n", enable); |
02330fba AM |
1068 | /* no idea what exactly is being done here, but I strongly assume it's |
1069 | * PM related */ | |
dfbf9511 | 1070 | snd_azf3328_ctrl_reg_6AH_update( |
627d3e7a | 1071 | chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable |
02330fba AM |
1072 | ); |
1073 | } | |
1074 | ||
1075 | static void | |
dfbf9511 AM |
1076 | snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip, |
1077 | enum snd_azf3328_codec_type codec_type, | |
1078 | bool enable | |
02330fba AM |
1079 | ) |
1080 | { | |
dfbf9511 AM |
1081 | struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; |
1082 | bool need_change = (codec->running != enable); | |
02330fba | 1083 | |
78df617a | 1084 | snd_azf3328_dbgcodec( |
dfbf9511 AM |
1085 | "codec_activity: %s codec, enable %d, need_change %d\n", |
1086 | codec->name, enable, need_change | |
02330fba AM |
1087 | ); |
1088 | if (need_change) { | |
dfbf9511 AM |
1089 | static const struct { |
1090 | enum snd_azf3328_codec_type other1; | |
1091 | enum snd_azf3328_codec_type other2; | |
1092 | } peer_codecs[3] = | |
1093 | { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT }, | |
1094 | { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT }, | |
1095 | { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } }; | |
1096 | bool call_function; | |
1097 | ||
1098 | if (enable) | |
1099 | /* if enable codec, call enable_codecs func | |
1100 | to enable codec supply... */ | |
1101 | call_function = 1; | |
1102 | else { | |
1103 | /* ...otherwise call enable_codecs func | |
1104 | (which globally shuts down operation of codecs) | |
1105 | only in case the other codecs are currently | |
1106 | not active either! */ | |
78df617a AM |
1107 | call_function = |
1108 | ((!chip->codecs[peer_codecs[codec_type].other1] | |
1109 | .running) | |
1110 | && (!chip->codecs[peer_codecs[codec_type].other2] | |
1111 | .running)); | |
dfbf9511 AM |
1112 | } |
1113 | if (call_function) | |
1114 | snd_azf3328_ctrl_enable_codecs(chip, enable); | |
02330fba AM |
1115 | |
1116 | /* ...and adjust clock, too | |
1117 | * (reduce noise and power consumption) */ | |
1118 | if (!enable) | |
da237f35 | 1119 | snd_azf3328_codec_setfmt_lowpower(codec); |
78df617a | 1120 | codec->running = enable; |
02330fba | 1121 | } |
02330fba AM |
1122 | } |
1123 | ||
d91c64c8 | 1124 | static void |
da237f35 | 1125 | snd_azf3328_codec_setdmaa(struct snd_azf3328_codec_data *codec, |
dfbf9511 AM |
1126 | unsigned long addr, |
1127 | unsigned int count, | |
1128 | unsigned int size | |
02330fba | 1129 | ) |
1da177e4 | 1130 | { |
1da177e4 | 1131 | snd_azf3328_dbgcallenter(); |
dfbf9511 AM |
1132 | if (!codec->running) { |
1133 | /* AZF3328 uses a two buffer pointer DMA transfer approach */ | |
02330fba | 1134 | |
78df617a | 1135 | unsigned long flags, addr_area2; |
02330fba AM |
1136 | |
1137 | /* width 32bit (prevent overflow): */ | |
78df617a | 1138 | u32 count_areas, lengths; |
d91c64c8 | 1139 | |
d91c64c8 AM |
1140 | count_areas = size/2; |
1141 | addr_area2 = addr+count_areas; | |
78df617a AM |
1142 | snd_azf3328_dbgcodec("setdma: buffers %08lx[%u] / %08lx[%u]\n", |
1143 | addr, count_areas, addr_area2, count_areas); | |
d91c64c8 | 1144 | |
7974150c AM |
1145 | count_areas--; /* max. index */ |
1146 | ||
d91c64c8 | 1147 | /* build combined I/O buffer length word */ |
dfbf9511 | 1148 | lengths = (count_areas << 16) | (count_areas); |
da237f35 | 1149 | spin_lock_irqsave(codec->lock, flags); |
dfbf9511 AM |
1150 | snd_azf3328_codec_outl(codec, IDX_IO_CODEC_DMA_START_1, addr); |
1151 | snd_azf3328_codec_outl(codec, IDX_IO_CODEC_DMA_START_2, | |
1152 | addr_area2); | |
1153 | snd_azf3328_codec_outl(codec, IDX_IO_CODEC_DMA_LENGTHS, | |
1154 | lengths); | |
da237f35 | 1155 | spin_unlock_irqrestore(codec->lock, flags); |
1da177e4 LT |
1156 | } |
1157 | snd_azf3328_dbgcallleave(); | |
1158 | } | |
1159 | ||
d91c64c8 | 1160 | static int |
da237f35 | 1161 | snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1162 | { |
95de7766 | 1163 | struct snd_pcm_runtime *runtime = substream->runtime; |
da237f35 | 1164 | struct snd_azf3328_codec_data *codec = runtime->private_data; |
34585595 | 1165 | #if 0 |
1da177e4 LT |
1166 | unsigned int size = snd_pcm_lib_buffer_bytes(substream); |
1167 | unsigned int count = snd_pcm_lib_period_bytes(substream); | |
1168 | #endif | |
1169 | ||
1170 | snd_azf3328_dbgcallenter(); | |
34585595 AM |
1171 | |
1172 | codec->dma_base = runtime->dma_addr; | |
1173 | ||
1da177e4 | 1174 | #if 0 |
da237f35 | 1175 | snd_azf3328_codec_setfmt(codec, |
d91c64c8 AM |
1176 | runtime->rate, |
1177 | snd_pcm_format_width(runtime->format), | |
1178 | runtime->channels); | |
da237f35 | 1179 | snd_azf3328_codec_setdmaa(codec, |
dfbf9511 | 1180 | runtime->dma_addr, count, size); |
1da177e4 LT |
1181 | #endif |
1182 | snd_azf3328_dbgcallleave(); | |
1183 | return 0; | |
1184 | } | |
1185 | ||
d91c64c8 | 1186 | static int |
da237f35 | 1187 | snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 1188 | { |
95de7766 TI |
1189 | struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); |
1190 | struct snd_pcm_runtime *runtime = substream->runtime; | |
da237f35 | 1191 | struct snd_azf3328_codec_data *codec = runtime->private_data; |
1da177e4 | 1192 | int result = 0; |
dfbf9511 AM |
1193 | u16 flags1; |
1194 | bool previously_muted = 0; | |
da237f35 | 1195 | bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type); |
1da177e4 | 1196 | |
da237f35 | 1197 | snd_azf3328_dbgcalls("snd_azf3328_pcm_trigger cmd %d\n", cmd); |
d91c64c8 | 1198 | |
1da177e4 LT |
1199 | switch (cmd) { |
1200 | case SNDRV_PCM_TRIGGER_START: | |
78df617a | 1201 | snd_azf3328_dbgcodec("START %s\n", codec->name); |
dfbf9511 | 1202 | |
da237f35 | 1203 | if (is_main_mixer_playback_codec) { |
dfbf9511 AM |
1204 | /* mute WaveOut (avoid clicking during setup) */ |
1205 | previously_muted = | |
1206 | snd_azf3328_mixer_set_mute( | |
1207 | chip, IDX_MIXER_WAVEOUT, 1 | |
1208 | ); | |
1209 | } | |
1da177e4 | 1210 | |
da237f35 | 1211 | snd_azf3328_codec_setfmt(codec, |
d91c64c8 AM |
1212 | runtime->rate, |
1213 | snd_pcm_format_width(runtime->format), | |
1214 | runtime->channels); | |
1da177e4 | 1215 | |
da237f35 | 1216 | spin_lock(codec->lock); |
02330fba | 1217 | /* first, remember current value: */ |
dfbf9511 | 1218 | flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); |
02330fba | 1219 | |
dfbf9511 AM |
1220 | /* stop transfer */ |
1221 | flags1 &= ~DMA_RESUME; | |
1222 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); | |
02330fba | 1223 | |
1da177e4 | 1224 | /* FIXME: clear interrupts or what??? */ |
dfbf9511 | 1225 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff); |
da237f35 | 1226 | spin_unlock(codec->lock); |
1da177e4 | 1227 | |
da237f35 | 1228 | snd_azf3328_codec_setdmaa(codec, runtime->dma_addr, |
d91c64c8 | 1229 | snd_pcm_lib_period_bytes(substream), |
dfbf9511 AM |
1230 | snd_pcm_lib_buffer_bytes(substream) |
1231 | ); | |
1da177e4 | 1232 | |
da237f35 | 1233 | spin_lock(codec->lock); |
1da177e4 LT |
1234 | #ifdef WIN9X |
1235 | /* FIXME: enable playback/recording??? */ | |
dfbf9511 AM |
1236 | flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2; |
1237 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); | |
1da177e4 | 1238 | |
dfbf9511 | 1239 | /* start transfer again */ |
1da177e4 | 1240 | /* FIXME: what is this value (0x0010)??? */ |
dfbf9511 AM |
1241 | flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING; |
1242 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); | |
1da177e4 | 1243 | #else /* NT4 */ |
dfbf9511 | 1244 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, |
d91c64c8 | 1245 | 0x0000); |
dfbf9511 AM |
1246 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, |
1247 | DMA_RUN_SOMETHING1); | |
1248 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, | |
1249 | DMA_RUN_SOMETHING1 | | |
1250 | DMA_RUN_SOMETHING2); | |
1251 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, | |
d91c64c8 AM |
1252 | DMA_RESUME | |
1253 | SOMETHING_ALMOST_ALWAYS_SET | | |
1254 | DMA_EPILOGUE_SOMETHING | | |
1255 | DMA_SOMETHING_ELSE); | |
1da177e4 | 1256 | #endif |
da237f35 AM |
1257 | spin_unlock(codec->lock); |
1258 | snd_azf3328_ctrl_codec_activity(chip, codec->type, 1); | |
dfbf9511 | 1259 | |
da237f35 | 1260 | if (is_main_mixer_playback_codec) { |
dfbf9511 AM |
1261 | /* now unmute WaveOut */ |
1262 | if (!previously_muted) | |
1263 | snd_azf3328_mixer_set_mute( | |
1264 | chip, IDX_MIXER_WAVEOUT, 0 | |
1265 | ); | |
1266 | } | |
1da177e4 | 1267 | |
78df617a | 1268 | snd_azf3328_dbgcodec("STARTED %s\n", codec->name); |
1da177e4 | 1269 | break; |
ca54bde3 | 1270 | case SNDRV_PCM_TRIGGER_RESUME: |
78df617a | 1271 | snd_azf3328_dbgcodec("RESUME %s\n", codec->name); |
dfbf9511 | 1272 | /* resume codec if we were active */ |
da237f35 | 1273 | spin_lock(codec->lock); |
dfbf9511 AM |
1274 | if (codec->running) |
1275 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, | |
1276 | snd_azf3328_codec_inw( | |
1277 | codec, IDX_IO_CODEC_DMA_FLAGS | |
1278 | ) | DMA_RESUME | |
1279 | ); | |
da237f35 | 1280 | spin_unlock(codec->lock); |
ca54bde3 | 1281 | break; |
d91c64c8 | 1282 | case SNDRV_PCM_TRIGGER_STOP: |
78df617a | 1283 | snd_azf3328_dbgcodec("STOP %s\n", codec->name); |
dfbf9511 | 1284 | |
da237f35 | 1285 | if (is_main_mixer_playback_codec) { |
dfbf9511 AM |
1286 | /* mute WaveOut (avoid clicking during setup) */ |
1287 | previously_muted = | |
1288 | snd_azf3328_mixer_set_mute( | |
1289 | chip, IDX_MIXER_WAVEOUT, 1 | |
1290 | ); | |
1291 | } | |
1da177e4 | 1292 | |
da237f35 | 1293 | spin_lock(codec->lock); |
02330fba | 1294 | /* first, remember current value: */ |
dfbf9511 | 1295 | flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); |
1da177e4 | 1296 | |
dfbf9511 AM |
1297 | /* stop transfer */ |
1298 | flags1 &= ~DMA_RESUME; | |
1299 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); | |
1da177e4 | 1300 | |
d91c64c8 AM |
1301 | /* hmm, is this really required? we're resetting the same bit |
1302 | * immediately thereafter... */ | |
dfbf9511 AM |
1303 | flags1 |= DMA_RUN_SOMETHING1; |
1304 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); | |
1da177e4 | 1305 | |
dfbf9511 AM |
1306 | flags1 &= ~DMA_RUN_SOMETHING1; |
1307 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); | |
da237f35 AM |
1308 | spin_unlock(codec->lock); |
1309 | snd_azf3328_ctrl_codec_activity(chip, codec->type, 0); | |
dfbf9511 | 1310 | |
da237f35 | 1311 | if (is_main_mixer_playback_codec) { |
dfbf9511 AM |
1312 | /* now unmute WaveOut */ |
1313 | if (!previously_muted) | |
1314 | snd_azf3328_mixer_set_mute( | |
1315 | chip, IDX_MIXER_WAVEOUT, 0 | |
1316 | ); | |
1317 | } | |
02330fba | 1318 | |
78df617a | 1319 | snd_azf3328_dbgcodec("STOPPED %s\n", codec->name); |
1da177e4 | 1320 | break; |
ca54bde3 | 1321 | case SNDRV_PCM_TRIGGER_SUSPEND: |
78df617a | 1322 | snd_azf3328_dbgcodec("SUSPEND %s\n", codec->name); |
dfbf9511 AM |
1323 | /* make sure codec is stopped */ |
1324 | snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, | |
1325 | snd_azf3328_codec_inw( | |
1326 | codec, IDX_IO_CODEC_DMA_FLAGS | |
1327 | ) & ~DMA_RESUME | |
1328 | ); | |
ca54bde3 | 1329 | break; |
1da177e4 | 1330 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
99b359ba | 1331 | snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n"); |
1da177e4 LT |
1332 | break; |
1333 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
99b359ba | 1334 | snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n"); |
1da177e4 LT |
1335 | break; |
1336 | default: | |
78df617a | 1337 | snd_printk(KERN_ERR "FIXME: unknown trigger mode!\n"); |
1da177e4 LT |
1338 | return -EINVAL; |
1339 | } | |
02330fba | 1340 | |
1da177e4 LT |
1341 | snd_azf3328_dbgcallleave(); |
1342 | return result; | |
1343 | } | |
1344 | ||
d91c64c8 | 1345 | static snd_pcm_uframes_t |
da237f35 | 1346 | snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream |
dfbf9511 | 1347 | ) |
1da177e4 | 1348 | { |
da237f35 AM |
1349 | const struct snd_azf3328_codec_data *codec = |
1350 | substream->runtime->private_data; | |
34585595 | 1351 | unsigned long result; |
1da177e4 LT |
1352 | snd_pcm_uframes_t frmres; |
1353 | ||
dfbf9511 | 1354 | result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS); |
1da177e4 | 1355 | |
d91c64c8 | 1356 | /* calculate offset */ |
34585595 AM |
1357 | #ifdef QUERY_HARDWARE |
1358 | result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1); | |
1359 | #else | |
1360 | result -= codec->dma_base; | |
1361 | #endif | |
d91c64c8 | 1362 | frmres = bytes_to_frames( substream->runtime, result); |
adf5931f AM |
1363 | snd_azf3328_dbgcodec("%08li %s @ 0x%8lx, frames %8ld\n", |
1364 | jiffies, codec->name, result, frmres); | |
1da177e4 LT |
1365 | return frmres; |
1366 | } | |
1367 | ||
02330fba AM |
1368 | /******************************************************************/ |
1369 | ||
1370 | #ifdef SUPPORT_GAMEPORT | |
1371 | static inline void | |
dfbf9511 AM |
1372 | snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip, |
1373 | bool enable | |
1374 | ) | |
02330fba AM |
1375 | { |
1376 | snd_azf3328_io_reg_setb( | |
1377 | chip->game_io+IDX_GAME_HWCONFIG, | |
1378 | GAME_HWCFG_IRQ_ENABLE, | |
1379 | enable | |
1380 | ); | |
1381 | } | |
1382 | ||
1383 | static inline void | |
dfbf9511 AM |
1384 | snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip, |
1385 | bool enable | |
1386 | ) | |
02330fba AM |
1387 | { |
1388 | snd_azf3328_io_reg_setb( | |
1389 | chip->game_io+IDX_GAME_HWCONFIG, | |
1390 | GAME_HWCFG_LEGACY_ADDRESS_ENABLE, | |
1391 | enable | |
1392 | ); | |
1393 | } | |
1394 | ||
dfbf9511 AM |
1395 | static void |
1396 | snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip, | |
1397 | unsigned int freq_cfg | |
1398 | ) | |
1399 | { | |
1400 | snd_azf3328_io_reg_setb( | |
1401 | chip->game_io+IDX_GAME_HWCONFIG, | |
1402 | 0x02, | |
1403 | (freq_cfg & 1) != 0 | |
1404 | ); | |
1405 | snd_azf3328_io_reg_setb( | |
1406 | chip->game_io+IDX_GAME_HWCONFIG, | |
1407 | 0x04, | |
1408 | (freq_cfg & 2) != 0 | |
1409 | ); | |
1410 | } | |
1411 | ||
02330fba | 1412 | static inline void |
dfbf9511 | 1413 | snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable) |
02330fba | 1414 | { |
dfbf9511 | 1415 | snd_azf3328_ctrl_reg_6AH_update( |
627d3e7a | 1416 | chip, IO_6A_SOMETHING2_GAMEPORT, enable |
02330fba AM |
1417 | ); |
1418 | } | |
1419 | ||
1420 | static inline void | |
1421 | snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) | |
1422 | { | |
1423 | /* | |
1424 | * skeleton handler only | |
1425 | * (we do not want axis reading in interrupt handler - too much load!) | |
1426 | */ | |
1427 | snd_azf3328_dbggame("gameport irq\n"); | |
1428 | ||
1429 | /* this should ACK the gameport IRQ properly, hopefully. */ | |
1430 | snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE); | |
1431 | } | |
1432 | ||
1433 | static int | |
1434 | snd_azf3328_gameport_open(struct gameport *gameport, int mode) | |
1435 | { | |
1436 | struct snd_azf3328 *chip = gameport_get_port_data(gameport); | |
1437 | int res; | |
1438 | ||
1439 | snd_azf3328_dbggame("gameport_open, mode %d\n", mode); | |
1440 | switch (mode) { | |
1441 | case GAMEPORT_MODE_COOKED: | |
1442 | case GAMEPORT_MODE_RAW: | |
1443 | res = 0; | |
1444 | break; | |
1445 | default: | |
1446 | res = -1; | |
1447 | break; | |
1448 | } | |
1449 | ||
dfbf9511 AM |
1450 | snd_azf3328_gameport_set_counter_frequency(chip, |
1451 | GAME_HWCFG_ADC_COUNTER_FREQ_STD); | |
02330fba AM |
1452 | snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0)); |
1453 | ||
1454 | return res; | |
1455 | } | |
1456 | ||
1457 | static void | |
1458 | snd_azf3328_gameport_close(struct gameport *gameport) | |
1459 | { | |
1460 | struct snd_azf3328 *chip = gameport_get_port_data(gameport); | |
1461 | ||
1462 | snd_azf3328_dbggame("gameport_close\n"); | |
dfbf9511 AM |
1463 | snd_azf3328_gameport_set_counter_frequency(chip, |
1464 | GAME_HWCFG_ADC_COUNTER_FREQ_1_200); | |
02330fba AM |
1465 | snd_azf3328_gameport_axis_circuit_enable(chip, 0); |
1466 | } | |
1467 | ||
1468 | static int | |
1469 | snd_azf3328_gameport_cooked_read(struct gameport *gameport, | |
1470 | int *axes, | |
1471 | int *buttons | |
1472 | ) | |
1473 | { | |
1474 | struct snd_azf3328 *chip = gameport_get_port_data(gameport); | |
1475 | int i; | |
1476 | u8 val; | |
1477 | unsigned long flags; | |
1478 | ||
da3cec35 TI |
1479 | if (snd_BUG_ON(!chip)) |
1480 | return 0; | |
02330fba AM |
1481 | |
1482 | spin_lock_irqsave(&chip->reg_lock, flags); | |
1483 | val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE); | |
1484 | *buttons = (~(val) >> 4) & 0xf; | |
1485 | ||
1486 | /* ok, this one is a bit dirty: cooked_read is being polled by a timer, | |
1487 | * thus we're atomic and cannot actively wait in here | |
1488 | * (which would be useful for us since it probably would be better | |
1489 | * to trigger a measurement in here, then wait a short amount of | |
1490 | * time until it's finished, then read values of _this_ measurement). | |
1491 | * | |
1492 | * Thus we simply resort to reading values if they're available already | |
1493 | * and trigger the next measurement. | |
1494 | */ | |
1495 | ||
1496 | val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG); | |
1497 | if (val & GAME_AXES_SAMPLING_READY) { | |
dfbf9511 | 1498 | for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) { |
02330fba AM |
1499 | /* configure the axis to read */ |
1500 | val = (i << 4) | 0x0f; | |
1501 | snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); | |
1502 | ||
1503 | chip->axes[i] = snd_azf3328_game_inw( | |
1504 | chip, IDX_GAME_AXIS_VALUE | |
1505 | ); | |
1506 | } | |
1507 | } | |
1508 | ||
adf5931f | 1509 | /* trigger next sampling of axes, to be evaluated the next time we |
02330fba AM |
1510 | * enter this function */ |
1511 | ||
1512 | /* for some very, very strange reason we cannot enable | |
1513 | * Measurement Ready monitoring for all axes here, | |
1514 | * at least not when only one joystick connected */ | |
1515 | val = 0x03; /* we're able to monitor axes 1 and 2 only */ | |
1516 | snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); | |
1517 | ||
1518 | snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff); | |
1519 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1520 | ||
dfbf9511 | 1521 | for (i = 0; i < ARRAY_SIZE(chip->axes); i++) { |
02330fba AM |
1522 | axes[i] = chip->axes[i]; |
1523 | if (axes[i] == 0xffff) | |
1524 | axes[i] = -1; | |
1525 | } | |
1526 | ||
1527 | snd_azf3328_dbggame("cooked_read: axes %d %d %d %d buttons %d\n", | |
1528 | axes[0], axes[1], axes[2], axes[3], *buttons | |
1529 | ); | |
1530 | ||
1531 | return 0; | |
1532 | } | |
1533 | ||
1534 | static int __devinit | |
1535 | snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) | |
1536 | { | |
1537 | struct gameport *gp; | |
1538 | ||
02330fba AM |
1539 | chip->gameport = gp = gameport_allocate_port(); |
1540 | if (!gp) { | |
1541 | printk(KERN_ERR "azt3328: cannot alloc memory for gameport\n"); | |
1542 | return -ENOMEM; | |
1543 | } | |
1544 | ||
1545 | gameport_set_name(gp, "AZF3328 Gameport"); | |
1546 | gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); | |
1547 | gameport_set_dev_parent(gp, &chip->pci->dev); | |
627d3e7a | 1548 | gp->io = chip->game_io; |
02330fba AM |
1549 | gameport_set_port_data(gp, chip); |
1550 | ||
1551 | gp->open = snd_azf3328_gameport_open; | |
1552 | gp->close = snd_azf3328_gameport_close; | |
1553 | gp->fuzz = 16; /* seems ok */ | |
1554 | gp->cooked_read = snd_azf3328_gameport_cooked_read; | |
1555 | ||
1556 | /* DISABLE legacy address: we don't need it! */ | |
1557 | snd_azf3328_gameport_legacy_address_enable(chip, 0); | |
1558 | ||
dfbf9511 AM |
1559 | snd_azf3328_gameport_set_counter_frequency(chip, |
1560 | GAME_HWCFG_ADC_COUNTER_FREQ_1_200); | |
02330fba AM |
1561 | snd_azf3328_gameport_axis_circuit_enable(chip, 0); |
1562 | ||
1563 | gameport_register_port(chip->gameport); | |
1564 | ||
1565 | return 0; | |
1566 | } | |
1567 | ||
1568 | static void | |
1569 | snd_azf3328_gameport_free(struct snd_azf3328 *chip) | |
1570 | { | |
1571 | if (chip->gameport) { | |
1572 | gameport_unregister_port(chip->gameport); | |
1573 | chip->gameport = NULL; | |
1574 | } | |
1575 | snd_azf3328_gameport_irq_enable(chip, 0); | |
1576 | } | |
1577 | #else | |
1578 | static inline int | |
1579 | snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; } | |
1580 | static inline void | |
1581 | snd_azf3328_gameport_free(struct snd_azf3328 *chip) { } | |
1582 | static inline void | |
1583 | snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) | |
1584 | { | |
1585 | printk(KERN_WARNING "huh, game port IRQ occurred!?\n"); | |
1586 | } | |
1587 | #endif /* SUPPORT_GAMEPORT */ | |
1588 | ||
1589 | /******************************************************************/ | |
1590 | ||
627d3e7a AM |
1591 | static inline void |
1592 | snd_azf3328_irq_log_unknown_type(u8 which) | |
1593 | { | |
78df617a | 1594 | snd_azf3328_dbgcodec( |
627d3e7a AM |
1595 | "azt3328: unknown IRQ type (%x) occurred, please report!\n", |
1596 | which | |
1597 | ); | |
1598 | } | |
1599 | ||
dfbf9511 | 1600 | static inline void |
da237f35 AM |
1601 | snd_azf3328_pcm_interrupt(const struct snd_azf3328_codec_data *first_codec, |
1602 | u8 status | |
1603 | ) | |
dfbf9511 AM |
1604 | { |
1605 | u8 which; | |
1606 | enum snd_azf3328_codec_type codec_type; | |
da237f35 | 1607 | const struct snd_azf3328_codec_data *codec = first_codec; |
dfbf9511 AM |
1608 | |
1609 | for (codec_type = AZF_CODEC_PLAYBACK; | |
1610 | codec_type <= AZF_CODEC_I2S_OUT; | |
da237f35 | 1611 | ++codec_type, ++codec) { |
dfbf9511 AM |
1612 | |
1613 | /* skip codec if there's no interrupt for it */ | |
1614 | if (!(status & (1 << codec_type))) | |
1615 | continue; | |
1616 | ||
da237f35 | 1617 | spin_lock(codec->lock); |
dfbf9511 AM |
1618 | which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE); |
1619 | /* ack all IRQ types immediately */ | |
1620 | snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which); | |
da237f35 | 1621 | spin_unlock(codec->lock); |
dfbf9511 | 1622 | |
da237f35 | 1623 | if (codec->substream) { |
78df617a AM |
1624 | snd_pcm_period_elapsed(codec->substream); |
1625 | snd_azf3328_dbgcodec("%s period done (#%x), @ %x\n", | |
dfbf9511 AM |
1626 | codec->name, |
1627 | which, | |
1628 | snd_azf3328_codec_inl( | |
1629 | codec, IDX_IO_CODEC_DMA_CURRPOS | |
1630 | ) | |
1631 | ); | |
1632 | } else | |
1633 | printk(KERN_WARNING "azt3328: irq handler problem!\n"); | |
1634 | if (which & IRQ_SOMETHING) | |
1635 | snd_azf3328_irq_log_unknown_type(which); | |
1636 | } | |
1637 | } | |
1638 | ||
d91c64c8 | 1639 | static irqreturn_t |
7d12e780 | 1640 | snd_azf3328_interrupt(int irq, void *dev_id) |
1da177e4 | 1641 | { |
95de7766 | 1642 | struct snd_azf3328 *chip = dev_id; |
dfbf9511 | 1643 | u8 status; |
78df617a | 1644 | #if DEBUG_CODEC |
d91c64c8 | 1645 | static unsigned long irq_count; |
02330fba | 1646 | #endif |
1da177e4 | 1647 | |
dfbf9511 | 1648 | status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS); |
1da177e4 LT |
1649 | |
1650 | /* fast path out, to ease interrupt sharing */ | |
02330fba | 1651 | if (!(status & |
dfbf9511 AM |
1652 | (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT |
1653 | |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER) | |
02330fba | 1654 | )) |
1da177e4 LT |
1655 | return IRQ_NONE; /* must be interrupt for another device */ |
1656 | ||
78df617a | 1657 | snd_azf3328_dbgcodec( |
dfbf9511 | 1658 | "irq_count %ld! IDX_IO_IRQSTATUS %04x\n", |
627d3e7a | 1659 | irq_count++ /* debug-only */, |
627d3e7a AM |
1660 | status |
1661 | ); | |
02330fba | 1662 | |
e2f87260 | 1663 | if (status & IRQ_TIMER) { |
78df617a | 1664 | /* snd_azf3328_dbgcodec("timer %ld\n", |
02330fba AM |
1665 | snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE) |
1666 | & TIMER_VALUE_MASK | |
1667 | ); */ | |
d91c64c8 AM |
1668 | if (chip->timer) |
1669 | snd_timer_interrupt(chip->timer, chip->timer->sticks); | |
1670 | /* ACK timer */ | |
1671 | spin_lock(&chip->reg_lock); | |
dfbf9511 | 1672 | snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07); |
d91c64c8 | 1673 | spin_unlock(&chip->reg_lock); |
78df617a | 1674 | snd_azf3328_dbgcodec("azt3328: timer IRQ\n"); |
d91c64c8 | 1675 | } |
d91c64c8 | 1676 | |
dfbf9511 | 1677 | if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT)) |
da237f35 | 1678 | snd_azf3328_pcm_interrupt(chip->codecs, status); |
d91c64c8 | 1679 | |
02330fba AM |
1680 | if (status & IRQ_GAMEPORT) |
1681 | snd_azf3328_gameport_interrupt(chip); | |
dfbf9511 | 1682 | |
d91c64c8 AM |
1683 | /* MPU401 has less critical IRQ requirements |
1684 | * than timer and playback/recording, right? */ | |
e2f87260 | 1685 | if (status & IRQ_MPU401) { |
7d12e780 | 1686 | snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); |
d91c64c8 AM |
1687 | |
1688 | /* hmm, do we have to ack the IRQ here somehow? | |
dfbf9511 | 1689 | * If so, then I don't know how yet... */ |
78df617a | 1690 | snd_azf3328_dbgcodec("azt3328: MPU401 IRQ\n"); |
d91c64c8 | 1691 | } |
1da177e4 LT |
1692 | return IRQ_HANDLED; |
1693 | } | |
1694 | ||
1695 | /*****************************************************************/ | |
1696 | ||
dfbf9511 AM |
1697 | /* as long as we think we have identical snd_pcm_hardware parameters |
1698 | for playback, capture and i2s out, we can use the same physical struct | |
1699 | since the struct is simply being copied into a member. | |
1700 | */ | |
1701 | static const struct snd_pcm_hardware snd_azf3328_hardware = | |
1da177e4 LT |
1702 | { |
1703 | /* FIXME!! Correct? */ | |
d91c64c8 AM |
1704 | .info = SNDRV_PCM_INFO_MMAP | |
1705 | SNDRV_PCM_INFO_INTERLEAVED | | |
1706 | SNDRV_PCM_INFO_MMAP_VALID, | |
1707 | .formats = SNDRV_PCM_FMTBIT_S8 | | |
1708 | SNDRV_PCM_FMTBIT_U8 | | |
1709 | SNDRV_PCM_FMTBIT_S16_LE | | |
1710 | SNDRV_PCM_FMTBIT_U16_LE, | |
1711 | .rates = SNDRV_PCM_RATE_5512 | | |
1712 | SNDRV_PCM_RATE_8000_48000 | | |
1713 | SNDRV_PCM_RATE_KNOT, | |
02330fba AM |
1714 | .rate_min = AZF_FREQ_4000, |
1715 | .rate_max = AZF_FREQ_66200, | |
1da177e4 LT |
1716 | .channels_min = 1, |
1717 | .channels_max = 2, | |
7974150c AM |
1718 | .buffer_bytes_max = (64*1024), |
1719 | .period_bytes_min = 1024, | |
1720 | .period_bytes_max = (32*1024), | |
1721 | /* We simply have two DMA areas (instead of a list of descriptors | |
1722 | such as other cards); I believe that this is a fixed hardware | |
1723 | attribute and there isn't much driver magic to be done to expand it. | |
1724 | Thus indicate that we have at least and at most 2 periods. */ | |
1725 | .periods_min = 2, | |
1726 | .periods_max = 2, | |
1da177e4 LT |
1727 | /* FIXME: maybe that card actually has a FIFO? |
1728 | * Hmm, it seems newer revisions do have one, but we still don't know | |
1729 | * its size... */ | |
1730 | .fifo_size = 0, | |
1731 | }; | |
1732 | ||
1da177e4 LT |
1733 | |
1734 | static unsigned int snd_azf3328_fixed_rates[] = { | |
02330fba AM |
1735 | AZF_FREQ_4000, |
1736 | AZF_FREQ_4800, | |
1737 | AZF_FREQ_5512, | |
1738 | AZF_FREQ_6620, | |
1739 | AZF_FREQ_8000, | |
1740 | AZF_FREQ_9600, | |
1741 | AZF_FREQ_11025, | |
1742 | AZF_FREQ_13240, | |
1743 | AZF_FREQ_16000, | |
1744 | AZF_FREQ_22050, | |
1745 | AZF_FREQ_32000, | |
1746 | AZF_FREQ_44100, | |
1747 | AZF_FREQ_48000, | |
1748 | AZF_FREQ_66200 | |
1749 | }; | |
1750 | ||
95de7766 | 1751 | static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = { |
02330fba | 1752 | .count = ARRAY_SIZE(snd_azf3328_fixed_rates), |
1da177e4 LT |
1753 | .list = snd_azf3328_fixed_rates, |
1754 | .mask = 0, | |
1755 | }; | |
1756 | ||
1757 | /*****************************************************************/ | |
1758 | ||
d91c64c8 | 1759 | static int |
dfbf9511 AM |
1760 | snd_azf3328_pcm_open(struct snd_pcm_substream *substream, |
1761 | enum snd_azf3328_codec_type codec_type | |
1762 | ) | |
1da177e4 | 1763 | { |
95de7766 TI |
1764 | struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); |
1765 | struct snd_pcm_runtime *runtime = substream->runtime; | |
da237f35 | 1766 | struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; |
1da177e4 LT |
1767 | |
1768 | snd_azf3328_dbgcallenter(); | |
da237f35 | 1769 | codec->substream = substream; |
dfbf9511 AM |
1770 | |
1771 | /* same parameters for all our codecs - at least we think so... */ | |
1772 | runtime->hw = snd_azf3328_hardware; | |
1773 | ||
1da177e4 LT |
1774 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
1775 | &snd_azf3328_hw_constraints_rates); | |
da237f35 | 1776 | runtime->private_data = codec; |
1da177e4 LT |
1777 | snd_azf3328_dbgcallleave(); |
1778 | return 0; | |
1779 | } | |
1780 | ||
dfbf9511 | 1781 | static int |
da237f35 | 1782 | snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream) |
dfbf9511 AM |
1783 | { |
1784 | return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK); | |
1785 | } | |
1786 | ||
d91c64c8 | 1787 | static int |
da237f35 | 1788 | snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 1789 | { |
dfbf9511 AM |
1790 | return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE); |
1791 | } | |
1da177e4 | 1792 | |
dfbf9511 | 1793 | static int |
da237f35 | 1794 | snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream) |
dfbf9511 AM |
1795 | { |
1796 | return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT); | |
1da177e4 LT |
1797 | } |
1798 | ||
d91c64c8 | 1799 | static int |
da237f35 | 1800 | snd_azf3328_pcm_close(struct snd_pcm_substream *substream |
dfbf9511 | 1801 | ) |
1da177e4 | 1802 | { |
da237f35 AM |
1803 | struct snd_azf3328_codec_data *codec = |
1804 | substream->runtime->private_data; | |
1da177e4 LT |
1805 | |
1806 | snd_azf3328_dbgcallenter(); | |
da237f35 | 1807 | codec->substream = NULL; |
1da177e4 LT |
1808 | snd_azf3328_dbgcallleave(); |
1809 | return 0; | |
1810 | } | |
1811 | ||
1da177e4 LT |
1812 | /******************************************************************/ |
1813 | ||
95de7766 | 1814 | static struct snd_pcm_ops snd_azf3328_playback_ops = { |
da237f35 AM |
1815 | .open = snd_azf3328_pcm_playback_open, |
1816 | .close = snd_azf3328_pcm_close, | |
1da177e4 LT |
1817 | .ioctl = snd_pcm_lib_ioctl, |
1818 | .hw_params = snd_azf3328_hw_params, | |
1819 | .hw_free = snd_azf3328_hw_free, | |
da237f35 AM |
1820 | .prepare = snd_azf3328_pcm_prepare, |
1821 | .trigger = snd_azf3328_pcm_trigger, | |
1822 | .pointer = snd_azf3328_pcm_pointer | |
1da177e4 LT |
1823 | }; |
1824 | ||
95de7766 | 1825 | static struct snd_pcm_ops snd_azf3328_capture_ops = { |
da237f35 AM |
1826 | .open = snd_azf3328_pcm_capture_open, |
1827 | .close = snd_azf3328_pcm_close, | |
1da177e4 LT |
1828 | .ioctl = snd_pcm_lib_ioctl, |
1829 | .hw_params = snd_azf3328_hw_params, | |
1830 | .hw_free = snd_azf3328_hw_free, | |
da237f35 AM |
1831 | .prepare = snd_azf3328_pcm_prepare, |
1832 | .trigger = snd_azf3328_pcm_trigger, | |
1833 | .pointer = snd_azf3328_pcm_pointer | |
dfbf9511 AM |
1834 | }; |
1835 | ||
1836 | static struct snd_pcm_ops snd_azf3328_i2s_out_ops = { | |
da237f35 AM |
1837 | .open = snd_azf3328_pcm_i2s_out_open, |
1838 | .close = snd_azf3328_pcm_close, | |
dfbf9511 AM |
1839 | .ioctl = snd_pcm_lib_ioctl, |
1840 | .hw_params = snd_azf3328_hw_params, | |
1841 | .hw_free = snd_azf3328_hw_free, | |
da237f35 AM |
1842 | .prepare = snd_azf3328_pcm_prepare, |
1843 | .trigger = snd_azf3328_pcm_trigger, | |
1844 | .pointer = snd_azf3328_pcm_pointer | |
1da177e4 LT |
1845 | }; |
1846 | ||
d91c64c8 | 1847 | static int __devinit |
dfbf9511 | 1848 | snd_azf3328_pcm(struct snd_azf3328 *chip) |
1da177e4 | 1849 | { |
dfbf9511 AM |
1850 | enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS }; /* pcm devices */ |
1851 | ||
95de7766 | 1852 | struct snd_pcm *pcm; |
1da177e4 LT |
1853 | int err; |
1854 | ||
1855 | snd_azf3328_dbgcallenter(); | |
dfbf9511 AM |
1856 | |
1857 | err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD, | |
1858 | 1, 1, &pcm); | |
1859 | if (err < 0) | |
1da177e4 | 1860 | return err; |
dfbf9511 AM |
1861 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, |
1862 | &snd_azf3328_playback_ops); | |
1863 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, | |
1864 | &snd_azf3328_capture_ops); | |
1da177e4 LT |
1865 | |
1866 | pcm->private_data = chip; | |
1da177e4 LT |
1867 | pcm->info_flags = 0; |
1868 | strcpy(pcm->name, chip->card->shortname); | |
dfbf9511 AM |
1869 | /* same pcm object for playback/capture (see snd_pcm_new() above) */ |
1870 | chip->pcm[AZF_CODEC_PLAYBACK] = pcm; | |
1871 | chip->pcm[AZF_CODEC_CAPTURE] = pcm; | |
1da177e4 LT |
1872 | |
1873 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
dfbf9511 AM |
1874 | snd_dma_pci_data(chip->pci), |
1875 | 64*1024, 64*1024); | |
1876 | ||
1877 | err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT, | |
1878 | 1, 0, &pcm); | |
1879 | if (err < 0) | |
1880 | return err; | |
1881 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
1882 | &snd_azf3328_i2s_out_ops); | |
1883 | ||
1884 | pcm->private_data = chip; | |
1885 | pcm->info_flags = 0; | |
1886 | strcpy(pcm->name, chip->card->shortname); | |
1887 | chip->pcm[AZF_CODEC_I2S_OUT] = pcm; | |
1888 | ||
1889 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1890 | snd_dma_pci_data(chip->pci), | |
1891 | 64*1024, 64*1024); | |
1da177e4 LT |
1892 | |
1893 | snd_azf3328_dbgcallleave(); | |
1894 | return 0; | |
1895 | } | |
1896 | ||
1897 | /******************************************************************/ | |
1898 | ||
02330fba AM |
1899 | /*** NOTE: the physical timer resolution actually is 1024000 ticks per second |
1900 | *** (probably derived from main crystal via a divider of 24), | |
d91c64c8 AM |
1901 | *** but announcing those attributes to user-space would make programs |
1902 | *** configure the timer to a 1 tick value, resulting in an absolutely fatal | |
1903 | *** timer IRQ storm. | |
1904 | *** Thus I chose to announce a down-scaled virtual timer to the outside and | |
1905 | *** calculate real timer countdown values internally. | |
1906 | *** (the scale factor can be set via module parameter "seqtimer_scaling"). | |
1907 | ***/ | |
1908 | ||
1909 | static int | |
95de7766 | 1910 | snd_azf3328_timer_start(struct snd_timer *timer) |
d91c64c8 | 1911 | { |
95de7766 | 1912 | struct snd_azf3328 *chip; |
d91c64c8 AM |
1913 | unsigned long flags; |
1914 | unsigned int delay; | |
1915 | ||
1916 | snd_azf3328_dbgcallenter(); | |
1917 | chip = snd_timer_chip(timer); | |
1918 | delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK; | |
e2f87260 | 1919 | if (delay < 49) { |
d91c64c8 AM |
1920 | /* uhoh, that's not good, since user-space won't know about |
1921 | * this timing tweak | |
1922 | * (we need to do it to avoid a lockup, though) */ | |
1923 | ||
1924 | snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay); | |
1925 | delay = 49; /* minimum time is 49 ticks */ | |
1926 | } | |
adf5931f | 1927 | snd_azf3328_dbgtimer("setting timer countdown value %d\n", delay); |
02330fba | 1928 | delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE; |
d91c64c8 | 1929 | spin_lock_irqsave(&chip->reg_lock, flags); |
dfbf9511 | 1930 | snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay); |
d91c64c8 AM |
1931 | spin_unlock_irqrestore(&chip->reg_lock, flags); |
1932 | snd_azf3328_dbgcallleave(); | |
1933 | return 0; | |
1934 | } | |
1935 | ||
1936 | static int | |
95de7766 | 1937 | snd_azf3328_timer_stop(struct snd_timer *timer) |
d91c64c8 | 1938 | { |
95de7766 | 1939 | struct snd_azf3328 *chip; |
d91c64c8 AM |
1940 | unsigned long flags; |
1941 | ||
1942 | snd_azf3328_dbgcallenter(); | |
1943 | chip = snd_timer_chip(timer); | |
1944 | spin_lock_irqsave(&chip->reg_lock, flags); | |
1945 | /* disable timer countdown and interrupt */ | |
7974150c AM |
1946 | /* Hmm, should we write TIMER_IRQ_ACK here? |
1947 | YES indeed, otherwise a rogue timer operation - which prompts | |
1948 | ALSA(?) to call repeated stop() in vain, but NOT start() - | |
1949 | will never end (value 0x03 is kept shown in control byte). | |
1950 | Simply manually poking 0x04 _once_ immediately successfully stops | |
1951 | the hardware/ALSA interrupt activity. */ | |
1952 | snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04); | |
d91c64c8 AM |
1953 | spin_unlock_irqrestore(&chip->reg_lock, flags); |
1954 | snd_azf3328_dbgcallleave(); | |
1955 | return 0; | |
1956 | } | |
1957 | ||
1958 | ||
1959 | static int | |
95de7766 | 1960 | snd_azf3328_timer_precise_resolution(struct snd_timer *timer, |
d91c64c8 AM |
1961 | unsigned long *num, unsigned long *den) |
1962 | { | |
1963 | snd_azf3328_dbgcallenter(); | |
1964 | *num = 1; | |
1965 | *den = 1024000 / seqtimer_scaling; | |
1966 | snd_azf3328_dbgcallleave(); | |
1967 | return 0; | |
1968 | } | |
1969 | ||
95de7766 | 1970 | static struct snd_timer_hardware snd_azf3328_timer_hw = { |
d91c64c8 AM |
1971 | .flags = SNDRV_TIMER_HW_AUTO, |
1972 | .resolution = 977, /* 1000000/1024000 = 0.9765625us */ | |
1973 | .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */ | |
1974 | .start = snd_azf3328_timer_start, | |
1975 | .stop = snd_azf3328_timer_stop, | |
1976 | .precise_resolution = snd_azf3328_timer_precise_resolution, | |
1977 | }; | |
1978 | ||
1979 | static int __devinit | |
95de7766 | 1980 | snd_azf3328_timer(struct snd_azf3328 *chip, int device) |
d91c64c8 | 1981 | { |
95de7766 TI |
1982 | struct snd_timer *timer = NULL; |
1983 | struct snd_timer_id tid; | |
d91c64c8 AM |
1984 | int err; |
1985 | ||
1986 | snd_azf3328_dbgcallenter(); | |
1987 | tid.dev_class = SNDRV_TIMER_CLASS_CARD; | |
1988 | tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; | |
1989 | tid.card = chip->card->number; | |
1990 | tid.device = device; | |
1991 | tid.subdevice = 0; | |
1992 | ||
1993 | snd_azf3328_timer_hw.resolution *= seqtimer_scaling; | |
1994 | snd_azf3328_timer_hw.ticks /= seqtimer_scaling; | |
02330fba AM |
1995 | |
1996 | err = snd_timer_new(chip->card, "AZF3328", &tid, &timer); | |
1997 | if (err < 0) | |
d91c64c8 | 1998 | goto out; |
d91c64c8 AM |
1999 | |
2000 | strcpy(timer->name, "AZF3328 timer"); | |
2001 | timer->private_data = chip; | |
2002 | timer->hw = snd_azf3328_timer_hw; | |
2003 | ||
2004 | chip->timer = timer; | |
2005 | ||
02330fba AM |
2006 | snd_azf3328_timer_stop(timer); |
2007 | ||
d91c64c8 AM |
2008 | err = 0; |
2009 | ||
2010 | out: | |
2011 | snd_azf3328_dbgcallleave(); | |
2012 | return err; | |
2013 | } | |
2014 | ||
2015 | /******************************************************************/ | |
2016 | ||
02330fba AM |
2017 | static int |
2018 | snd_azf3328_free(struct snd_azf3328 *chip) | |
2019 | { | |
2020 | if (chip->irq < 0) | |
2021 | goto __end_hw; | |
2022 | ||
2023 | /* reset (close) mixer: | |
2024 | * first mute master volume, then reset | |
2025 | */ | |
2026 | snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); | |
2027 | snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); | |
2028 | ||
2029 | snd_azf3328_timer_stop(chip->timer); | |
2030 | snd_azf3328_gameport_free(chip); | |
2031 | ||
2032 | if (chip->irq >= 0) | |
2033 | synchronize_irq(chip->irq); | |
2034 | __end_hw: | |
2035 | if (chip->irq >= 0) | |
2036 | free_irq(chip->irq, chip); | |
2037 | pci_release_regions(chip->pci); | |
2038 | pci_disable_device(chip->pci); | |
2039 | ||
2040 | kfree(chip); | |
2041 | return 0; | |
2042 | } | |
2043 | ||
2044 | static int | |
2045 | snd_azf3328_dev_free(struct snd_device *device) | |
2046 | { | |
2047 | struct snd_azf3328 *chip = device->device_data; | |
2048 | return snd_azf3328_free(chip); | |
2049 | } | |
2050 | ||
1da177e4 LT |
2051 | #if 0 |
2052 | /* check whether a bit can be modified */ | |
d91c64c8 | 2053 | static void |
02330fba | 2054 | snd_azf3328_test_bit(unsigned unsigned reg, int bit) |
1da177e4 LT |
2055 | { |
2056 | unsigned char val, valoff, valon; | |
2057 | ||
2058 | val = inb(reg); | |
2059 | ||
2060 | outb(val & ~(1 << bit), reg); | |
2061 | valoff = inb(reg); | |
2062 | ||
2063 | outb(val|(1 << bit), reg); | |
2064 | valon = inb(reg); | |
02330fba | 2065 | |
1da177e4 LT |
2066 | outb(val, reg); |
2067 | ||
78df617a | 2068 | printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n", |
02330fba AM |
2069 | reg, bit, val, valoff, valon |
2070 | ); | |
1da177e4 LT |
2071 | } |
2072 | #endif | |
2073 | ||
02330fba | 2074 | static inline void |
95de7766 | 2075 | snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) |
d91c64c8 | 2076 | { |
02330fba | 2077 | #if DEBUG_MISC |
d91c64c8 AM |
2078 | u16 tmp; |
2079 | ||
02330fba | 2080 | snd_azf3328_dbgmisc( |
dfbf9511 | 2081 | "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, " |
02330fba | 2082 | "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n", |
dfbf9511 | 2083 | chip->ctrl_io, chip->game_io, chip->mpu_io, |
02330fba AM |
2084 | chip->opl3_io, chip->mixer_io, chip->irq |
2085 | ); | |
2086 | ||
2087 | snd_azf3328_dbgmisc("game %02x %02x %02x %02x %02x %02x\n", | |
2088 | snd_azf3328_game_inb(chip, 0), | |
2089 | snd_azf3328_game_inb(chip, 1), | |
2090 | snd_azf3328_game_inb(chip, 2), | |
2091 | snd_azf3328_game_inb(chip, 3), | |
2092 | snd_azf3328_game_inb(chip, 4), | |
2093 | snd_azf3328_game_inb(chip, 5) | |
2094 | ); | |
2095 | ||
2096 | for (tmp = 0; tmp < 0x07; tmp += 1) | |
2097 | snd_azf3328_dbgmisc("mpu_io 0x%04x\n", inb(chip->mpu_io + tmp)); | |
2098 | ||
2099 | for (tmp = 0; tmp <= 0x07; tmp += 1) | |
2100 | snd_azf3328_dbgmisc("0x%02x: game200 0x%04x, game208 0x%04x\n", | |
2101 | tmp, inb(0x200 + tmp), inb(0x208 + tmp)); | |
2102 | ||
2103 | for (tmp = 0; tmp <= 0x01; tmp += 1) | |
2104 | snd_azf3328_dbgmisc( | |
2105 | "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, " | |
2106 | "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n", | |
2107 | tmp, | |
2108 | inb(0x300 + tmp), | |
2109 | inb(0x310 + tmp), | |
2110 | inb(0x320 + tmp), | |
2111 | inb(0x330 + tmp), | |
2112 | inb(0x388 + tmp), | |
2113 | inb(0x38c + tmp) | |
2114 | ); | |
d91c64c8 | 2115 | |
dfbf9511 AM |
2116 | for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2) |
2117 | snd_azf3328_dbgmisc("ctrl 0x%02x: 0x%04x\n", | |
2118 | tmp, snd_azf3328_ctrl_inw(chip, tmp) | |
02330fba | 2119 | ); |
e24a121a AM |
2120 | |
2121 | for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2) | |
02330fba AM |
2122 | snd_azf3328_dbgmisc("mixer 0x%02x: 0x%04x\n", |
2123 | tmp, snd_azf3328_mixer_inw(chip, tmp) | |
2124 | ); | |
2125 | #endif /* DEBUG_MISC */ | |
d91c64c8 AM |
2126 | } |
2127 | ||
2128 | static int __devinit | |
95de7766 | 2129 | snd_azf3328_create(struct snd_card *card, |
02330fba AM |
2130 | struct pci_dev *pci, |
2131 | unsigned long device_type, | |
2132 | struct snd_azf3328 **rchip) | |
1da177e4 | 2133 | { |
95de7766 | 2134 | struct snd_azf3328 *chip; |
1da177e4 | 2135 | int err; |
95de7766 | 2136 | static struct snd_device_ops ops = { |
1da177e4 LT |
2137 | .dev_free = snd_azf3328_dev_free, |
2138 | }; | |
dfbf9511 AM |
2139 | u8 dma_init; |
2140 | enum snd_azf3328_codec_type codec_type; | |
da237f35 | 2141 | struct snd_azf3328_codec_data *codec_setup; |
1da177e4 LT |
2142 | |
2143 | *rchip = NULL; | |
2144 | ||
02330fba AM |
2145 | err = pci_enable_device(pci); |
2146 | if (err < 0) | |
1da177e4 LT |
2147 | return err; |
2148 | ||
e560d8d8 | 2149 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1da177e4 | 2150 | if (chip == NULL) { |
d91c64c8 AM |
2151 | err = -ENOMEM; |
2152 | goto out_err; | |
1da177e4 LT |
2153 | } |
2154 | spin_lock_init(&chip->reg_lock); | |
2155 | chip->card = card; | |
2156 | chip->pci = pci; | |
2157 | chip->irq = -1; | |
2158 | ||
2159 | /* check if we can restrict PCI DMA transfers to 24 bits */ | |
2f4f27d4 YH |
2160 | if (pci_set_dma_mask(pci, DMA_BIT_MASK(24)) < 0 || |
2161 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(24)) < 0) { | |
02330fba AM |
2162 | snd_printk(KERN_ERR "architecture does not support " |
2163 | "24bit PCI busmaster DMA\n" | |
2164 | ); | |
d91c64c8 AM |
2165 | err = -ENXIO; |
2166 | goto out_err; | |
1da177e4 LT |
2167 | } |
2168 | ||
02330fba AM |
2169 | err = pci_request_regions(pci, "Aztech AZF3328"); |
2170 | if (err < 0) | |
d91c64c8 | 2171 | goto out_err; |
1da177e4 | 2172 | |
dfbf9511 | 2173 | chip->ctrl_io = pci_resource_start(pci, 0); |
02330fba AM |
2174 | chip->game_io = pci_resource_start(pci, 1); |
2175 | chip->mpu_io = pci_resource_start(pci, 2); | |
dfbf9511 | 2176 | chip->opl3_io = pci_resource_start(pci, 3); |
02330fba AM |
2177 | chip->mixer_io = pci_resource_start(pci, 4); |
2178 | ||
9fd8d36c AM |
2179 | codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK]; |
2180 | codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK; | |
da237f35 AM |
2181 | codec_setup->lock = &chip->reg_lock; |
2182 | codec_setup->type = AZF_CODEC_PLAYBACK; | |
9fd8d36c AM |
2183 | codec_setup->name = "PLAYBACK"; |
2184 | ||
2185 | codec_setup = &chip->codecs[AZF_CODEC_CAPTURE]; | |
2186 | codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE; | |
da237f35 AM |
2187 | codec_setup->lock = &chip->reg_lock; |
2188 | codec_setup->type = AZF_CODEC_CAPTURE; | |
9fd8d36c AM |
2189 | codec_setup->name = "CAPTURE"; |
2190 | ||
2191 | codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT]; | |
2192 | codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT; | |
da237f35 AM |
2193 | codec_setup->lock = &chip->reg_lock; |
2194 | codec_setup->type = AZF_CODEC_I2S_OUT; | |
9fd8d36c | 2195 | codec_setup->name = "I2S_OUT"; |
1da177e4 | 2196 | |
437a5a46 TI |
2197 | if (request_irq(pci->irq, snd_azf3328_interrupt, |
2198 | IRQF_SHARED, card->shortname, chip)) { | |
99b359ba | 2199 | snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); |
d91c64c8 AM |
2200 | err = -EBUSY; |
2201 | goto out_err; | |
1da177e4 LT |
2202 | } |
2203 | chip->irq = pci->irq; | |
2204 | pci_set_master(pci); | |
2205 | synchronize_irq(chip->irq); | |
2206 | ||
d91c64c8 | 2207 | snd_azf3328_debug_show_ports(chip); |
02330fba AM |
2208 | |
2209 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); | |
2210 | if (err < 0) | |
d91c64c8 | 2211 | goto out_err; |
1da177e4 LT |
2212 | |
2213 | /* create mixer interface & switches */ | |
02330fba AM |
2214 | err = snd_azf3328_mixer_new(chip); |
2215 | if (err < 0) | |
d91c64c8 | 2216 | goto out_err; |
1da177e4 | 2217 | |
dfbf9511 AM |
2218 | /* standard codec init stuff */ |
2219 | /* default DMA init value */ | |
2220 | dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE; | |
2221 | ||
2222 | for (codec_type = AZF_CODEC_PLAYBACK; | |
2223 | codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) { | |
2224 | struct snd_azf3328_codec_data *codec = | |
2225 | &chip->codecs[codec_type]; | |
1da177e4 | 2226 | |
adf5931f | 2227 | /* shutdown codecs to reduce power / noise */ |
dfbf9511 AM |
2228 | /* have ...ctrl_codec_activity() act properly */ |
2229 | codec->running = 1; | |
2230 | snd_azf3328_ctrl_codec_activity(chip, codec_type, 0); | |
1da177e4 | 2231 | |
da237f35 | 2232 | spin_lock_irq(codec->lock); |
dfbf9511 AM |
2233 | snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS, |
2234 | dma_init); | |
da237f35 | 2235 | spin_unlock_irq(codec->lock); |
dfbf9511 | 2236 | } |
1da177e4 LT |
2237 | |
2238 | snd_card_set_dev(card, &pci->dev); | |
2239 | ||
2240 | *rchip = chip; | |
d91c64c8 AM |
2241 | |
2242 | err = 0; | |
2243 | goto out; | |
2244 | ||
2245 | out_err: | |
2246 | if (chip) | |
2247 | snd_azf3328_free(chip); | |
2248 | pci_disable_device(pci); | |
2249 | ||
2250 | out: | |
2251 | return err; | |
1da177e4 LT |
2252 | } |
2253 | ||
d91c64c8 AM |
2254 | static int __devinit |
2255 | snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) | |
1da177e4 LT |
2256 | { |
2257 | static int dev; | |
95de7766 TI |
2258 | struct snd_card *card; |
2259 | struct snd_azf3328 *chip; | |
2260 | struct snd_opl3 *opl3; | |
1da177e4 LT |
2261 | int err; |
2262 | ||
2263 | snd_azf3328_dbgcallenter(); | |
2264 | if (dev >= SNDRV_CARDS) | |
2265 | return -ENODEV; | |
2266 | if (!enable[dev]) { | |
2267 | dev++; | |
2268 | return -ENOENT; | |
2269 | } | |
2270 | ||
e58de7ba TI |
2271 | err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); |
2272 | if (err < 0) | |
2273 | return err; | |
1da177e4 LT |
2274 | |
2275 | strcpy(card->driver, "AZF3328"); | |
2276 | strcpy(card->shortname, "Aztech AZF3328 (PCI168)"); | |
2277 | ||
02330fba AM |
2278 | err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip); |
2279 | if (err < 0) | |
d91c64c8 | 2280 | goto out_err; |
1da177e4 | 2281 | |
ca54bde3 AM |
2282 | card->private_data = chip; |
2283 | ||
78df617a AM |
2284 | /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401, |
2285 | since our hardware ought to be similar, thus use same ID. */ | |
02330fba | 2286 | err = snd_mpu401_uart_new( |
78df617a AM |
2287 | card, 0, |
2288 | MPU401_HW_AZT2320, chip->mpu_io, MPU401_INFO_INTEGRATED, | |
02330fba AM |
2289 | pci->irq, 0, &chip->rmidi |
2290 | ); | |
2291 | if (err < 0) { | |
2292 | snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n", | |
2293 | chip->mpu_io | |
2294 | ); | |
d91c64c8 AM |
2295 | goto out_err; |
2296 | } | |
2297 | ||
02330fba AM |
2298 | err = snd_azf3328_timer(chip, 0); |
2299 | if (err < 0) | |
d91c64c8 | 2300 | goto out_err; |
1da177e4 | 2301 | |
dfbf9511 | 2302 | err = snd_azf3328_pcm(chip); |
02330fba | 2303 | if (err < 0) |
d91c64c8 | 2304 | goto out_err; |
1da177e4 | 2305 | |
02330fba | 2306 | if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2, |
1da177e4 | 2307 | OPL3_HW_AUTO, 1, &opl3) < 0) { |
99b359ba | 2308 | snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n", |
02330fba AM |
2309 | chip->opl3_io, chip->opl3_io+2 |
2310 | ); | |
1da177e4 | 2311 | } else { |
02330fba AM |
2312 | /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */ |
2313 | err = snd_opl3_timer_new(opl3, 1, 2); | |
2314 | if (err < 0) | |
2315 | goto out_err; | |
2316 | err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); | |
2317 | if (err < 0) | |
d91c64c8 | 2318 | goto out_err; |
1da177e4 LT |
2319 | } |
2320 | ||
ca54bde3 AM |
2321 | opl3->private_data = chip; |
2322 | ||
1da177e4 | 2323 | sprintf(card->longname, "%s at 0x%lx, irq %i", |
dfbf9511 | 2324 | card->shortname, chip->ctrl_io, chip->irq); |
1da177e4 | 2325 | |
02330fba AM |
2326 | err = snd_card_register(card); |
2327 | if (err < 0) | |
d91c64c8 | 2328 | goto out_err; |
1da177e4 LT |
2329 | |
2330 | #ifdef MODULE | |
78df617a | 2331 | printk(KERN_INFO |
e24a121a AM |
2332 | "azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n" |
2333 | "azt3328: Hardware was completely undocumented, unfortunately.\n" | |
d91c64c8 AM |
2334 | "azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n" |
2335 | "azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n", | |
2336 | 1024000 / seqtimer_scaling, seqtimer_scaling); | |
1da177e4 LT |
2337 | #endif |
2338 | ||
02330fba | 2339 | snd_azf3328_gameport(chip, dev); |
1da177e4 LT |
2340 | |
2341 | pci_set_drvdata(pci, card); | |
2342 | dev++; | |
2343 | ||
d91c64c8 AM |
2344 | err = 0; |
2345 | goto out; | |
02330fba | 2346 | |
d91c64c8 | 2347 | out_err: |
02330fba | 2348 | snd_printk(KERN_ERR "azf3328: something failed, exiting\n"); |
d91c64c8 | 2349 | snd_card_free(card); |
02330fba | 2350 | |
d91c64c8 | 2351 | out: |
1da177e4 | 2352 | snd_azf3328_dbgcallleave(); |
d91c64c8 | 2353 | return err; |
1da177e4 LT |
2354 | } |
2355 | ||
d91c64c8 AM |
2356 | static void __devexit |
2357 | snd_azf3328_remove(struct pci_dev *pci) | |
1da177e4 LT |
2358 | { |
2359 | snd_azf3328_dbgcallenter(); | |
2360 | snd_card_free(pci_get_drvdata(pci)); | |
2361 | pci_set_drvdata(pci, NULL); | |
2362 | snd_azf3328_dbgcallleave(); | |
2363 | } | |
2364 | ||
ca54bde3 | 2365 | #ifdef CONFIG_PM |
78df617a AM |
2366 | static inline void |
2367 | snd_azf3328_suspend_regs(unsigned long io_addr, unsigned count, u32 *saved_regs) | |
2368 | { | |
2369 | unsigned reg; | |
2370 | ||
2371 | for (reg = 0; reg < count; ++reg) { | |
2372 | *saved_regs = inl(io_addr); | |
2373 | snd_azf3328_dbgpm("suspend: io 0x%04lx: 0x%08x\n", | |
2374 | io_addr, *saved_regs); | |
2375 | ++saved_regs; | |
2376 | io_addr += sizeof(*saved_regs); | |
2377 | } | |
2378 | } | |
2379 | ||
ca54bde3 AM |
2380 | static int |
2381 | snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state) | |
2382 | { | |
2383 | struct snd_card *card = pci_get_drvdata(pci); | |
2384 | struct snd_azf3328 *chip = card->private_data; | |
78df617a | 2385 | u16 *saved_regs_ctrl_u16; |
ca54bde3 AM |
2386 | |
2387 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); | |
02330fba | 2388 | |
adf5931f | 2389 | /* same pcm object for playback/capture */ |
dfbf9511 AM |
2390 | snd_pcm_suspend_all(chip->pcm[AZF_CODEC_PLAYBACK]); |
2391 | snd_pcm_suspend_all(chip->pcm[AZF_CODEC_I2S_OUT]); | |
ca54bde3 | 2392 | |
78df617a AM |
2393 | snd_azf3328_suspend_regs(chip->mixer_io, |
2394 | ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer); | |
ca54bde3 AM |
2395 | |
2396 | /* make sure to disable master volume etc. to prevent looping sound */ | |
2397 | snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); | |
2398 | snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1); | |
02330fba | 2399 | |
78df617a AM |
2400 | snd_azf3328_suspend_regs(chip->ctrl_io, |
2401 | ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl); | |
627d3e7a AM |
2402 | |
2403 | /* manually store the one currently relevant write-only reg, too */ | |
78df617a AM |
2404 | saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl; |
2405 | saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH; | |
627d3e7a | 2406 | |
78df617a AM |
2407 | snd_azf3328_suspend_regs(chip->game_io, |
2408 | ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game); | |
2409 | snd_azf3328_suspend_regs(chip->mpu_io, | |
2410 | ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu); | |
2411 | snd_azf3328_suspend_regs(chip->opl3_io, | |
2412 | ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3); | |
ca54bde3 | 2413 | |
ca54bde3 AM |
2414 | pci_disable_device(pci); |
2415 | pci_save_state(pci); | |
30b35399 | 2416 | pci_set_power_state(pci, pci_choose_state(pci, state)); |
ca54bde3 AM |
2417 | return 0; |
2418 | } | |
2419 | ||
78df617a AM |
2420 | static inline void |
2421 | snd_azf3328_resume_regs(const u32 *saved_regs, | |
2422 | unsigned long io_addr, | |
2423 | unsigned count | |
2424 | ) | |
2425 | { | |
2426 | unsigned reg; | |
2427 | ||
2428 | for (reg = 0; reg < count; ++reg) { | |
2429 | outl(*saved_regs, io_addr); | |
2430 | snd_azf3328_dbgpm("resume: io 0x%04lx: 0x%08x --> 0x%08x\n", | |
2431 | io_addr, *saved_regs, inl(io_addr)); | |
2432 | ++saved_regs; | |
2433 | io_addr += sizeof(*saved_regs); | |
2434 | } | |
2435 | } | |
2436 | ||
ca54bde3 AM |
2437 | static int |
2438 | snd_azf3328_resume(struct pci_dev *pci) | |
2439 | { | |
2440 | struct snd_card *card = pci_get_drvdata(pci); | |
dfbf9511 | 2441 | const struct snd_azf3328 *chip = card->private_data; |
ca54bde3 | 2442 | |
ca54bde3 | 2443 | pci_set_power_state(pci, PCI_D0); |
30b35399 TI |
2444 | pci_restore_state(pci); |
2445 | if (pci_enable_device(pci) < 0) { | |
2446 | printk(KERN_ERR "azt3328: pci_enable_device failed, " | |
2447 | "disabling device\n"); | |
2448 | snd_card_disconnect(card); | |
2449 | return -EIO; | |
2450 | } | |
ca54bde3 AM |
2451 | pci_set_master(pci); |
2452 | ||
78df617a AM |
2453 | snd_azf3328_resume_regs(chip->saved_regs_game, chip->game_io, |
2454 | ARRAY_SIZE(chip->saved_regs_game)); | |
2455 | snd_azf3328_resume_regs(chip->saved_regs_mpu, chip->mpu_io, | |
2456 | ARRAY_SIZE(chip->saved_regs_mpu)); | |
2457 | snd_azf3328_resume_regs(chip->saved_regs_opl3, chip->opl3_io, | |
2458 | ARRAY_SIZE(chip->saved_regs_opl3)); | |
2459 | ||
2460 | snd_azf3328_resume_regs(chip->saved_regs_mixer, chip->mixer_io, | |
2461 | ARRAY_SIZE(chip->saved_regs_mixer)); | |
2462 | ||
2463 | /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02) | |
2464 | and IDX_MIXER_RESET (offset 0x00) get touched at the same time, | |
2465 | resulting in a mixer reset condition persisting until _after_ | |
2466 | master vol was restored. Thus master vol needs an extra restore. */ | |
2467 | outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2); | |
2468 | ||
2469 | snd_azf3328_resume_regs(chip->saved_regs_ctrl, chip->ctrl_io, | |
2470 | ARRAY_SIZE(chip->saved_regs_ctrl)); | |
ca54bde3 AM |
2471 | |
2472 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); | |
2473 | return 0; | |
2474 | } | |
02330fba | 2475 | #endif /* CONFIG_PM */ |
ca54bde3 AM |
2476 | |
2477 | ||
1da177e4 LT |
2478 | static struct pci_driver driver = { |
2479 | .name = "AZF3328", | |
2480 | .id_table = snd_azf3328_ids, | |
2481 | .probe = snd_azf3328_probe, | |
2482 | .remove = __devexit_p(snd_azf3328_remove), | |
ca54bde3 AM |
2483 | #ifdef CONFIG_PM |
2484 | .suspend = snd_azf3328_suspend, | |
2485 | .resume = snd_azf3328_resume, | |
2486 | #endif | |
1da177e4 LT |
2487 | }; |
2488 | ||
d91c64c8 AM |
2489 | static int __init |
2490 | alsa_card_azf3328_init(void) | |
1da177e4 LT |
2491 | { |
2492 | int err; | |
2493 | snd_azf3328_dbgcallenter(); | |
01d25d46 | 2494 | err = pci_register_driver(&driver); |
1da177e4 LT |
2495 | snd_azf3328_dbgcallleave(); |
2496 | return err; | |
2497 | } | |
2498 | ||
d91c64c8 AM |
2499 | static void __exit |
2500 | alsa_card_azf3328_exit(void) | |
1da177e4 LT |
2501 | { |
2502 | snd_azf3328_dbgcallenter(); | |
2503 | pci_unregister_driver(&driver); | |
2504 | snd_azf3328_dbgcallleave(); | |
2505 | } | |
2506 | ||
2507 | module_init(alsa_card_azf3328_init) | |
2508 | module_exit(alsa_card_azf3328_exit) |