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1da177e4 LT |
1 | /* |
2 | * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers | |
3 | * | |
4 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <sound/driver.h> | |
23 | #include <asm/io.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/moduleparam.h> | |
30 | #include <sound/core.h> | |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/info.h> | |
34 | #include <sound/ac97_codec.h> | |
35 | #include <sound/initval.h> | |
36 | ||
37 | MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); | |
38 | MODULE_DESCRIPTION("ATI IXP AC97 controller"); | |
39 | MODULE_LICENSE("GPL"); | |
40 | MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400}}"); | |
41 | ||
42 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
43 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
44 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ | |
45 | static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 48000}; | |
46 | static char *ac97_quirk[SNDRV_CARDS]; | |
47 | static int spdif_aclink[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1}; | |
48 | ||
49 | module_param_array(index, int, NULL, 0444); | |
50 | MODULE_PARM_DESC(index, "Index value for ATI IXP controller."); | |
51 | module_param_array(id, charp, NULL, 0444); | |
52 | MODULE_PARM_DESC(id, "ID string for ATI IXP controller."); | |
53 | module_param_array(enable, bool, NULL, 0444); | |
54 | MODULE_PARM_DESC(enable, "Enable audio part of ATI IXP controller."); | |
55 | module_param_array(ac97_clock, int, NULL, 0444); | |
56 | MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz)."); | |
57 | module_param_array(ac97_quirk, charp, NULL, 0444); | |
58 | MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); | |
59 | module_param_array(spdif_aclink, bool, NULL, 0444); | |
60 | MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); | |
61 | ||
62 | ||
63 | /* | |
64 | */ | |
65 | ||
66 | #define ATI_REG_ISR 0x00 /* interrupt source */ | |
67 | #define ATI_REG_ISR_IN_XRUN (1U<<0) | |
68 | #define ATI_REG_ISR_IN_STATUS (1U<<1) | |
69 | #define ATI_REG_ISR_OUT_XRUN (1U<<2) | |
70 | #define ATI_REG_ISR_OUT_STATUS (1U<<3) | |
71 | #define ATI_REG_ISR_SPDF_XRUN (1U<<4) | |
72 | #define ATI_REG_ISR_SPDF_STATUS (1U<<5) | |
73 | #define ATI_REG_ISR_PHYS_INTR (1U<<8) | |
74 | #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9) | |
75 | #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10) | |
76 | #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11) | |
77 | #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12) | |
78 | #define ATI_REG_ISR_NEW_FRAME (1U<<13) | |
79 | ||
80 | #define ATI_REG_IER 0x04 /* interrupt enable */ | |
81 | #define ATI_REG_IER_IN_XRUN_EN (1U<<0) | |
82 | #define ATI_REG_IER_IO_STATUS_EN (1U<<1) | |
83 | #define ATI_REG_IER_OUT_XRUN_EN (1U<<2) | |
84 | #define ATI_REG_IER_OUT_XRUN_COND (1U<<3) | |
85 | #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4) | |
86 | #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5) | |
87 | #define ATI_REG_IER_PHYS_INTR_EN (1U<<8) | |
88 | #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9) | |
89 | #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10) | |
90 | #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11) | |
91 | #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12) | |
92 | #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */ | |
93 | #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */ | |
94 | ||
95 | #define ATI_REG_CMD 0x08 /* command */ | |
96 | #define ATI_REG_CMD_POWERDOWN (1U<<0) | |
97 | #define ATI_REG_CMD_RECEIVE_EN (1U<<1) | |
98 | #define ATI_REG_CMD_SEND_EN (1U<<2) | |
99 | #define ATI_REG_CMD_STATUS_MEM (1U<<3) | |
100 | #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4) | |
101 | #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5) | |
102 | #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6) | |
103 | #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6 | |
104 | #define ATI_REG_CMD_IN_DMA_EN (1U<<8) | |
105 | #define ATI_REG_CMD_OUT_DMA_EN (1U<<9) | |
106 | #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10) | |
107 | #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11) | |
108 | #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12) | |
109 | #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12) | |
110 | #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12) | |
111 | #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12) | |
112 | #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12) | |
113 | #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16) | |
114 | #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20) | |
115 | #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21) | |
116 | #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22) | |
117 | #define ATI_REG_CMD_LOOPBACK_EN (1U<<23) | |
118 | #define ATI_REG_CMD_PACKED_DIS (1U<<24) | |
119 | #define ATI_REG_CMD_BURST_EN (1U<<25) | |
120 | #define ATI_REG_CMD_PANIC_EN (1U<<26) | |
121 | #define ATI_REG_CMD_MODEM_PRESENT (1U<<27) | |
122 | #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28) | |
123 | #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29) | |
124 | #define ATI_REG_CMD_AC_SYNC (1U<<30) | |
125 | #define ATI_REG_CMD_AC_RESET (1U<<31) | |
126 | ||
127 | #define ATI_REG_PHYS_OUT_ADDR 0x0c | |
128 | #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0) | |
129 | #define ATI_REG_PHYS_OUT_RW (1U<<2) | |
130 | #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8) | |
131 | #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9 | |
132 | #define ATI_REG_PHYS_OUT_DATA_SHIFT 16 | |
133 | ||
134 | #define ATI_REG_PHYS_IN_ADDR 0x10 | |
135 | #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8) | |
136 | #define ATI_REG_PHYS_IN_ADDR_SHIFT 9 | |
137 | #define ATI_REG_PHYS_IN_DATA_SHIFT 16 | |
138 | ||
139 | #define ATI_REG_SLOTREQ 0x14 | |
140 | ||
141 | #define ATI_REG_COUNTER 0x18 | |
142 | #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */ | |
143 | #define ATI_REG_COUNTER_BITCLOCK (31U<<8) | |
144 | ||
145 | #define ATI_REG_IN_FIFO_THRESHOLD 0x1c | |
146 | ||
147 | #define ATI_REG_IN_DMA_LINKPTR 0x20 | |
148 | #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */ | |
149 | #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */ | |
150 | #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */ | |
151 | #define ATI_REG_IN_DMA_DT_SIZE 0x30 | |
152 | ||
153 | #define ATI_REG_OUT_DMA_SLOT 0x34 | |
154 | #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3)) | |
155 | #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff | |
156 | #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800 | |
157 | #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11 | |
158 | ||
159 | #define ATI_REG_OUT_DMA_LINKPTR 0x38 | |
160 | #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */ | |
161 | #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */ | |
162 | #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */ | |
163 | #define ATI_REG_OUT_DMA_DT_SIZE 0x48 | |
164 | ||
165 | #define ATI_REG_SPDF_CMD 0x4c | |
166 | #define ATI_REG_SPDF_CMD_LFSR (1U<<4) | |
167 | #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5) | |
168 | #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */ | |
169 | ||
170 | #define ATI_REG_SPDF_DMA_LINKPTR 0x50 | |
171 | #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */ | |
172 | #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */ | |
173 | #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */ | |
174 | #define ATI_REG_SPDF_DMA_DT_SIZE 0x60 | |
175 | ||
176 | #define ATI_REG_MODEM_MIRROR 0x7c | |
177 | #define ATI_REG_AUDIO_MIRROR 0x80 | |
178 | ||
179 | #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */ | |
180 | #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */ | |
181 | ||
182 | #define ATI_REG_FIFO_FLUSH 0x88 | |
183 | #define ATI_REG_FIFO_OUT_FLUSH (1U<<0) | |
184 | #define ATI_REG_FIFO_IN_FLUSH (1U<<1) | |
185 | ||
186 | /* LINKPTR */ | |
187 | #define ATI_REG_LINKPTR_EN (1U<<0) | |
188 | ||
189 | /* [INT|OUT|SPDIF]_DMA_DT_SIZE */ | |
190 | #define ATI_REG_DMA_DT_SIZE (0xffffU<<0) | |
191 | #define ATI_REG_DMA_FIFO_USED (0x1fU<<16) | |
192 | #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21) | |
193 | #define ATI_REG_DMA_STATE (7U<<26) | |
194 | ||
195 | ||
196 | #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */ | |
197 | ||
198 | ||
199 | /* | |
200 | */ | |
201 | ||
202 | typedef struct snd_atiixp atiixp_t; | |
203 | typedef struct snd_atiixp_dma atiixp_dma_t; | |
204 | typedef struct snd_atiixp_dma_ops atiixp_dma_ops_t; | |
205 | ||
206 | ||
207 | /* | |
208 | * DMA packate descriptor | |
209 | */ | |
210 | ||
211 | typedef struct atiixp_dma_desc { | |
212 | u32 addr; /* DMA buffer address */ | |
213 | u16 status; /* status bits */ | |
214 | u16 size; /* size of the packet in dwords */ | |
215 | u32 next; /* address of the next packet descriptor */ | |
216 | } atiixp_dma_desc_t; | |
217 | ||
218 | /* | |
219 | * stream enum | |
220 | */ | |
221 | enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */ | |
222 | enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */ | |
223 | enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */ | |
224 | ||
225 | #define NUM_ATI_CODECS 3 | |
226 | ||
227 | ||
228 | /* | |
229 | * constants and callbacks for each DMA type | |
230 | */ | |
231 | struct snd_atiixp_dma_ops { | |
232 | int type; /* ATI_DMA_XXX */ | |
233 | unsigned int llp_offset; /* LINKPTR offset */ | |
234 | unsigned int dt_cur; /* DT_CUR offset */ | |
235 | void (*enable_dma)(atiixp_t *chip, int on); /* called from open callback */ | |
236 | void (*enable_transfer)(atiixp_t *chip, int on); /* called from trigger (START/STOP) */ | |
237 | void (*flush_dma)(atiixp_t *chip); /* called from trigger (STOP only) */ | |
238 | }; | |
239 | ||
240 | /* | |
241 | * DMA stream | |
242 | */ | |
243 | struct snd_atiixp_dma { | |
244 | const atiixp_dma_ops_t *ops; | |
245 | struct snd_dma_buffer desc_buf; | |
246 | snd_pcm_substream_t *substream; /* assigned PCM substream */ | |
247 | unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */ | |
248 | unsigned int period_bytes, periods; | |
249 | int opened; | |
250 | int running; | |
251 | int pcm_open_flag; | |
252 | int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */ | |
253 | unsigned int saved_curptr; | |
254 | }; | |
255 | ||
256 | /* | |
257 | * ATI IXP chip | |
258 | */ | |
259 | struct snd_atiixp { | |
260 | snd_card_t *card; | |
261 | struct pci_dev *pci; | |
262 | ||
263 | unsigned long addr; | |
264 | void __iomem *remap_addr; | |
265 | int irq; | |
266 | ||
267 | ac97_bus_t *ac97_bus; | |
268 | ac97_t *ac97[NUM_ATI_CODECS]; | |
269 | ||
270 | spinlock_t reg_lock; | |
271 | ||
272 | atiixp_dma_t dmas[NUM_ATI_DMAS]; | |
273 | struct ac97_pcm *pcms[NUM_ATI_PCMS]; | |
274 | snd_pcm_t *pcmdevs[NUM_ATI_PCMDEVS]; | |
275 | ||
276 | int max_channels; /* max. channels for PCM out */ | |
277 | ||
278 | unsigned int codec_not_ready_bits; /* for codec detection */ | |
279 | ||
280 | int spdif_over_aclink; /* passed from the module option */ | |
281 | struct semaphore open_mutex; /* playback open mutex */ | |
282 | }; | |
283 | ||
284 | ||
285 | /* | |
286 | */ | |
287 | static struct pci_device_id snd_atiixp_ids[] = { | |
288 | { 0x1002, 0x4341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB200 */ | |
289 | { 0x1002, 0x4361, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB300 */ | |
290 | { 0x1002, 0x4370, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB400 */ | |
291 | { 0, } | |
292 | }; | |
293 | ||
294 | MODULE_DEVICE_TABLE(pci, snd_atiixp_ids); | |
295 | ||
296 | ||
297 | /* | |
298 | * lowlevel functions | |
299 | */ | |
300 | ||
301 | /* | |
302 | * update the bits of the given register. | |
303 | * return 1 if the bits changed. | |
304 | */ | |
305 | static int snd_atiixp_update_bits(atiixp_t *chip, unsigned int reg, | |
306 | unsigned int mask, unsigned int value) | |
307 | { | |
308 | void __iomem *addr = chip->remap_addr + reg; | |
309 | unsigned int data, old_data; | |
310 | old_data = data = readl(addr); | |
311 | data &= ~mask; | |
312 | data |= value; | |
313 | if (old_data == data) | |
314 | return 0; | |
315 | writel(data, addr); | |
316 | return 1; | |
317 | } | |
318 | ||
319 | /* | |
320 | * macros for easy use | |
321 | */ | |
322 | #define atiixp_write(chip,reg,value) \ | |
323 | writel(value, chip->remap_addr + ATI_REG_##reg) | |
324 | #define atiixp_read(chip,reg) \ | |
325 | readl(chip->remap_addr + ATI_REG_##reg) | |
326 | #define atiixp_update(chip,reg,mask,val) \ | |
327 | snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) | |
328 | ||
329 | /* delay for one tick */ | |
330 | #define do_delay() do { \ | |
331 | set_current_state(TASK_UNINTERRUPTIBLE); \ | |
332 | schedule_timeout(1); \ | |
333 | } while (0) | |
334 | ||
335 | ||
336 | /* | |
337 | * handling DMA packets | |
338 | * | |
339 | * we allocate a linear buffer for the DMA, and split it to each packet. | |
340 | * in a future version, a scatter-gather buffer should be implemented. | |
341 | */ | |
342 | ||
343 | #define ATI_DESC_LIST_SIZE \ | |
344 | PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(atiixp_dma_desc_t)) | |
345 | ||
346 | /* | |
347 | * build packets ring for the given buffer size. | |
348 | * | |
349 | * IXP handles the buffer descriptors, which are connected as a linked | |
350 | * list. although we can change the list dynamically, in this version, | |
351 | * a static RING of buffer descriptors is used. | |
352 | * | |
353 | * the ring is built in this function, and is set up to the hardware. | |
354 | */ | |
355 | static int atiixp_build_dma_packets(atiixp_t *chip, atiixp_dma_t *dma, | |
356 | snd_pcm_substream_t *substream, | |
357 | unsigned int periods, | |
358 | unsigned int period_bytes) | |
359 | { | |
360 | unsigned int i; | |
361 | u32 addr, desc_addr; | |
362 | unsigned long flags; | |
363 | ||
364 | if (periods > ATI_MAX_DESCRIPTORS) | |
365 | return -ENOMEM; | |
366 | ||
367 | if (dma->desc_buf.area == NULL) { | |
368 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
369 | ATI_DESC_LIST_SIZE, &dma->desc_buf) < 0) | |
370 | return -ENOMEM; | |
371 | dma->period_bytes = dma->periods = 0; /* clear */ | |
372 | } | |
373 | ||
374 | if (dma->periods == periods && dma->period_bytes == period_bytes) | |
375 | return 0; | |
376 | ||
377 | /* reset DMA before changing the descriptor table */ | |
378 | spin_lock_irqsave(&chip->reg_lock, flags); | |
379 | writel(0, chip->remap_addr + dma->ops->llp_offset); | |
380 | dma->ops->enable_dma(chip, 0); | |
381 | dma->ops->enable_dma(chip, 1); | |
382 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
383 | ||
384 | /* fill the entries */ | |
385 | addr = (u32)substream->runtime->dma_addr; | |
386 | desc_addr = (u32)dma->desc_buf.addr; | |
387 | for (i = 0; i < periods; i++) { | |
388 | atiixp_dma_desc_t *desc = &((atiixp_dma_desc_t *)dma->desc_buf.area)[i]; | |
389 | desc->addr = cpu_to_le32(addr); | |
390 | desc->status = 0; | |
391 | desc->size = period_bytes >> 2; /* in dwords */ | |
392 | desc_addr += sizeof(atiixp_dma_desc_t); | |
393 | if (i == periods - 1) | |
394 | desc->next = cpu_to_le32((u32)dma->desc_buf.addr); | |
395 | else | |
396 | desc->next = cpu_to_le32(desc_addr); | |
397 | addr += period_bytes; | |
398 | } | |
399 | ||
400 | writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, | |
401 | chip->remap_addr + dma->ops->llp_offset); | |
402 | ||
403 | dma->period_bytes = period_bytes; | |
404 | dma->periods = periods; | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | /* | |
410 | * remove the ring buffer and release it if assigned | |
411 | */ | |
412 | static void atiixp_clear_dma_packets(atiixp_t *chip, atiixp_dma_t *dma, snd_pcm_substream_t *substream) | |
413 | { | |
414 | if (dma->desc_buf.area) { | |
415 | writel(0, chip->remap_addr + dma->ops->llp_offset); | |
416 | snd_dma_free_pages(&dma->desc_buf); | |
417 | dma->desc_buf.area = NULL; | |
418 | } | |
419 | } | |
420 | ||
421 | /* | |
422 | * AC97 interface | |
423 | */ | |
424 | static int snd_atiixp_acquire_codec(atiixp_t *chip) | |
425 | { | |
426 | int timeout = 1000; | |
427 | ||
428 | while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) { | |
429 | if (! timeout--) { | |
430 | snd_printk(KERN_WARNING "atiixp: codec acquire timeout\n"); | |
431 | return -EBUSY; | |
432 | } | |
433 | udelay(1); | |
434 | } | |
435 | return 0; | |
436 | } | |
437 | ||
438 | static unsigned short snd_atiixp_codec_read(atiixp_t *chip, unsigned short codec, unsigned short reg) | |
439 | { | |
440 | unsigned int data; | |
441 | int timeout; | |
442 | ||
443 | if (snd_atiixp_acquire_codec(chip) < 0) | |
444 | return 0xffff; | |
445 | data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | | |
446 | ATI_REG_PHYS_OUT_ADDR_EN | | |
447 | ATI_REG_PHYS_OUT_RW | | |
448 | codec; | |
449 | atiixp_write(chip, PHYS_OUT_ADDR, data); | |
450 | if (snd_atiixp_acquire_codec(chip) < 0) | |
451 | return 0xffff; | |
452 | timeout = 1000; | |
453 | do { | |
454 | data = atiixp_read(chip, PHYS_IN_ADDR); | |
455 | if (data & ATI_REG_PHYS_IN_READ_FLAG) | |
456 | return data >> ATI_REG_PHYS_IN_DATA_SHIFT; | |
457 | udelay(1); | |
458 | } while (--timeout); | |
459 | /* time out may happen during reset */ | |
460 | if (reg < 0x7c) | |
461 | snd_printk(KERN_WARNING "atiixp: codec read timeout (reg %x)\n", reg); | |
462 | return 0xffff; | |
463 | } | |
464 | ||
465 | ||
466 | static void snd_atiixp_codec_write(atiixp_t *chip, unsigned short codec, unsigned short reg, unsigned short val) | |
467 | { | |
468 | unsigned int data; | |
469 | ||
470 | if (snd_atiixp_acquire_codec(chip) < 0) | |
471 | return; | |
472 | data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) | | |
473 | ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | | |
474 | ATI_REG_PHYS_OUT_ADDR_EN | codec; | |
475 | atiixp_write(chip, PHYS_OUT_ADDR, data); | |
476 | } | |
477 | ||
478 | ||
479 | static unsigned short snd_atiixp_ac97_read(ac97_t *ac97, unsigned short reg) | |
480 | { | |
481 | atiixp_t *chip = ac97->private_data; | |
482 | return snd_atiixp_codec_read(chip, ac97->num, reg); | |
483 | ||
484 | } | |
485 | ||
486 | static void snd_atiixp_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val) | |
487 | { | |
488 | atiixp_t *chip = ac97->private_data; | |
489 | snd_atiixp_codec_write(chip, ac97->num, reg, val); | |
490 | } | |
491 | ||
492 | /* | |
493 | * reset AC link | |
494 | */ | |
495 | static int snd_atiixp_aclink_reset(atiixp_t *chip) | |
496 | { | |
497 | int timeout; | |
498 | ||
499 | /* reset powerdoewn */ | |
500 | if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0)) | |
501 | udelay(10); | |
502 | ||
503 | /* perform a software reset */ | |
504 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET); | |
505 | atiixp_read(chip, CMD); | |
506 | udelay(10); | |
507 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0); | |
508 | ||
509 | timeout = 10; | |
510 | while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) { | |
511 | /* do a hard reset */ | |
512 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, | |
513 | ATI_REG_CMD_AC_SYNC); | |
514 | atiixp_read(chip, CMD); | |
515 | do_delay(); | |
516 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET); | |
517 | if (--timeout) { | |
518 | snd_printk(KERN_ERR "atiixp: codec reset timeout\n"); | |
519 | break; | |
520 | } | |
521 | } | |
522 | ||
523 | /* deassert RESET and assert SYNC to make sure */ | |
524 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, | |
525 | ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
530 | #ifdef CONFIG_PM | |
531 | static int snd_atiixp_aclink_down(atiixp_t *chip) | |
532 | { | |
533 | // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */ | |
534 | // return -EBUSY; | |
535 | atiixp_update(chip, CMD, | |
536 | ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET, | |
537 | ATI_REG_CMD_POWERDOWN); | |
538 | return 0; | |
539 | } | |
540 | #endif | |
541 | ||
542 | /* | |
543 | * auto-detection of codecs | |
544 | * | |
545 | * the IXP chip can generate interrupts for the non-existing codecs. | |
546 | * NEW_FRAME interrupt is used to make sure that the interrupt is generated | |
547 | * even if all three codecs are connected. | |
548 | */ | |
549 | ||
550 | #define ALL_CODEC_NOT_READY \ | |
551 | (ATI_REG_ISR_CODEC0_NOT_READY |\ | |
552 | ATI_REG_ISR_CODEC1_NOT_READY |\ | |
553 | ATI_REG_ISR_CODEC2_NOT_READY) | |
554 | #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME) | |
555 | ||
556 | static int snd_atiixp_codec_detect(atiixp_t *chip) | |
557 | { | |
558 | int timeout; | |
559 | ||
560 | chip->codec_not_ready_bits = 0; | |
561 | atiixp_write(chip, IER, CODEC_CHECK_BITS); | |
562 | /* wait for the interrupts */ | |
563 | timeout = HZ / 10; | |
564 | while (timeout-- > 0) { | |
565 | do_delay(); | |
566 | if (chip->codec_not_ready_bits) | |
567 | break; | |
568 | } | |
569 | atiixp_write(chip, IER, 0); /* disable irqs */ | |
570 | ||
571 | if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) { | |
572 | snd_printk(KERN_ERR "atiixp: no codec detected!\n"); | |
573 | return -ENXIO; | |
574 | } | |
575 | return 0; | |
576 | } | |
577 | ||
578 | ||
579 | /* | |
580 | * enable DMA and irqs | |
581 | */ | |
582 | static int snd_atiixp_chip_start(atiixp_t *chip) | |
583 | { | |
584 | unsigned int reg; | |
585 | ||
586 | /* set up spdif, enable burst mode */ | |
587 | reg = atiixp_read(chip, CMD); | |
588 | reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT; | |
589 | reg |= ATI_REG_CMD_BURST_EN; | |
590 | atiixp_write(chip, CMD, reg); | |
591 | ||
592 | reg = atiixp_read(chip, SPDF_CMD); | |
593 | reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH); | |
594 | atiixp_write(chip, SPDF_CMD, reg); | |
595 | ||
596 | /* clear all interrupt source */ | |
597 | atiixp_write(chip, ISR, 0xffffffff); | |
598 | /* enable irqs */ | |
599 | atiixp_write(chip, IER, | |
600 | ATI_REG_IER_IO_STATUS_EN | | |
601 | ATI_REG_IER_IN_XRUN_EN | | |
602 | ATI_REG_IER_OUT_XRUN_EN | | |
603 | ATI_REG_IER_SPDF_XRUN_EN | | |
604 | ATI_REG_IER_SPDF_STATUS_EN); | |
605 | return 0; | |
606 | } | |
607 | ||
608 | ||
609 | /* | |
610 | * disable DMA and IRQs | |
611 | */ | |
612 | static int snd_atiixp_chip_stop(atiixp_t *chip) | |
613 | { | |
614 | /* clear interrupt source */ | |
615 | atiixp_write(chip, ISR, atiixp_read(chip, ISR)); | |
616 | /* disable irqs */ | |
617 | atiixp_write(chip, IER, 0); | |
618 | return 0; | |
619 | } | |
620 | ||
621 | ||
622 | /* | |
623 | * PCM section | |
624 | */ | |
625 | ||
626 | /* | |
627 | * pointer callback simplly reads XXX_DMA_DT_CUR register as the current | |
628 | * position. when SG-buffer is implemented, the offset must be calculated | |
629 | * correctly... | |
630 | */ | |
631 | static snd_pcm_uframes_t snd_atiixp_pcm_pointer(snd_pcm_substream_t *substream) | |
632 | { | |
633 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
634 | snd_pcm_runtime_t *runtime = substream->runtime; | |
635 | atiixp_dma_t *dma = (atiixp_dma_t *)runtime->private_data; | |
636 | unsigned int curptr; | |
637 | int timeout = 1000; | |
638 | ||
639 | while (timeout--) { | |
640 | curptr = readl(chip->remap_addr + dma->ops->dt_cur); | |
641 | if (curptr < dma->buf_addr) | |
642 | continue; | |
643 | curptr -= dma->buf_addr; | |
644 | if (curptr >= dma->buf_bytes) | |
645 | continue; | |
646 | return bytes_to_frames(runtime, curptr); | |
647 | } | |
648 | snd_printd("atiixp: invalid DMA pointer read 0x%x (buf=%x)\n", | |
649 | readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr); | |
650 | return 0; | |
651 | } | |
652 | ||
653 | /* | |
654 | * XRUN detected, and stop the PCM substream | |
655 | */ | |
656 | static void snd_atiixp_xrun_dma(atiixp_t *chip, atiixp_dma_t *dma) | |
657 | { | |
658 | if (! dma->substream || ! dma->running) | |
659 | return; | |
660 | snd_printdd("atiixp: XRUN detected (DMA %d)\n", dma->ops->type); | |
661 | snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN); | |
662 | } | |
663 | ||
664 | /* | |
665 | * the period ack. update the substream. | |
666 | */ | |
667 | static void snd_atiixp_update_dma(atiixp_t *chip, atiixp_dma_t *dma) | |
668 | { | |
669 | if (! dma->substream || ! dma->running) | |
670 | return; | |
671 | snd_pcm_period_elapsed(dma->substream); | |
672 | } | |
673 | ||
674 | /* set BUS_BUSY interrupt bit if any DMA is running */ | |
675 | /* call with spinlock held */ | |
676 | static void snd_atiixp_check_bus_busy(atiixp_t *chip) | |
677 | { | |
678 | unsigned int bus_busy; | |
679 | if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN | | |
680 | ATI_REG_CMD_RECEIVE_EN | | |
681 | ATI_REG_CMD_SPDF_OUT_EN)) | |
682 | bus_busy = ATI_REG_IER_SET_BUS_BUSY; | |
683 | else | |
684 | bus_busy = 0; | |
685 | atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy); | |
686 | } | |
687 | ||
688 | /* common trigger callback | |
689 | * calling the lowlevel callbacks in it | |
690 | */ | |
691 | static int snd_atiixp_pcm_trigger(snd_pcm_substream_t *substream, int cmd) | |
692 | { | |
693 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
694 | atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data; | |
695 | int err = 0; | |
696 | ||
697 | snd_assert(dma->ops->enable_transfer && dma->ops->flush_dma, return -EINVAL); | |
698 | ||
699 | spin_lock(&chip->reg_lock); | |
700 | switch (cmd) { | |
701 | case SNDRV_PCM_TRIGGER_START: | |
702 | dma->ops->enable_transfer(chip, 1); | |
703 | dma->running = 1; | |
704 | break; | |
705 | case SNDRV_PCM_TRIGGER_STOP: | |
706 | dma->ops->enable_transfer(chip, 0); | |
707 | dma->running = 0; | |
708 | break; | |
709 | default: | |
710 | err = -EINVAL; | |
711 | break; | |
712 | } | |
713 | if (! err) { | |
714 | snd_atiixp_check_bus_busy(chip); | |
715 | if (cmd == SNDRV_PCM_TRIGGER_STOP) { | |
716 | dma->ops->flush_dma(chip); | |
717 | snd_atiixp_check_bus_busy(chip); | |
718 | } | |
719 | } | |
720 | spin_unlock(&chip->reg_lock); | |
721 | return err; | |
722 | } | |
723 | ||
724 | ||
725 | /* | |
726 | * lowlevel callbacks for each DMA type | |
727 | * | |
728 | * every callback is supposed to be called in chip->reg_lock spinlock | |
729 | */ | |
730 | ||
731 | /* flush FIFO of analog OUT DMA */ | |
732 | static void atiixp_out_flush_dma(atiixp_t *chip) | |
733 | { | |
734 | atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH); | |
735 | } | |
736 | ||
737 | /* enable/disable analog OUT DMA */ | |
738 | static void atiixp_out_enable_dma(atiixp_t *chip, int on) | |
739 | { | |
740 | unsigned int data; | |
741 | data = atiixp_read(chip, CMD); | |
742 | if (on) { | |
743 | if (data & ATI_REG_CMD_OUT_DMA_EN) | |
744 | return; | |
745 | atiixp_out_flush_dma(chip); | |
746 | data |= ATI_REG_CMD_OUT_DMA_EN; | |
747 | } else | |
748 | data &= ~ATI_REG_CMD_OUT_DMA_EN; | |
749 | atiixp_write(chip, CMD, data); | |
750 | } | |
751 | ||
752 | /* start/stop transfer over OUT DMA */ | |
753 | static void atiixp_out_enable_transfer(atiixp_t *chip, int on) | |
754 | { | |
755 | atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN, | |
756 | on ? ATI_REG_CMD_SEND_EN : 0); | |
757 | } | |
758 | ||
759 | /* enable/disable analog IN DMA */ | |
760 | static void atiixp_in_enable_dma(atiixp_t *chip, int on) | |
761 | { | |
762 | atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN, | |
763 | on ? ATI_REG_CMD_IN_DMA_EN : 0); | |
764 | } | |
765 | ||
766 | /* start/stop analog IN DMA */ | |
767 | static void atiixp_in_enable_transfer(atiixp_t *chip, int on) | |
768 | { | |
769 | if (on) { | |
770 | unsigned int data = atiixp_read(chip, CMD); | |
771 | if (! (data & ATI_REG_CMD_RECEIVE_EN)) { | |
772 | data |= ATI_REG_CMD_RECEIVE_EN; | |
773 | #if 0 /* FIXME: this causes the endless loop */ | |
774 | /* wait until slot 3/4 are finished */ | |
775 | while ((atiixp_read(chip, COUNTER) & | |
776 | ATI_REG_COUNTER_SLOT) != 5) | |
777 | ; | |
778 | #endif | |
779 | atiixp_write(chip, CMD, data); | |
780 | } | |
781 | } else | |
782 | atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0); | |
783 | } | |
784 | ||
785 | /* flush FIFO of analog IN DMA */ | |
786 | static void atiixp_in_flush_dma(atiixp_t *chip) | |
787 | { | |
788 | atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH); | |
789 | } | |
790 | ||
791 | /* enable/disable SPDIF OUT DMA */ | |
792 | static void atiixp_spdif_enable_dma(atiixp_t *chip, int on) | |
793 | { | |
794 | atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN, | |
795 | on ? ATI_REG_CMD_SPDF_DMA_EN : 0); | |
796 | } | |
797 | ||
798 | /* start/stop SPDIF OUT DMA */ | |
799 | static void atiixp_spdif_enable_transfer(atiixp_t *chip, int on) | |
800 | { | |
801 | unsigned int data; | |
802 | data = atiixp_read(chip, CMD); | |
803 | if (on) | |
804 | data |= ATI_REG_CMD_SPDF_OUT_EN; | |
805 | else | |
806 | data &= ~ATI_REG_CMD_SPDF_OUT_EN; | |
807 | atiixp_write(chip, CMD, data); | |
808 | } | |
809 | ||
810 | /* flush FIFO of SPDIF OUT DMA */ | |
811 | static void atiixp_spdif_flush_dma(atiixp_t *chip) | |
812 | { | |
813 | int timeout; | |
814 | ||
815 | /* DMA off, transfer on */ | |
816 | atiixp_spdif_enable_dma(chip, 0); | |
817 | atiixp_spdif_enable_transfer(chip, 1); | |
818 | ||
819 | timeout = 100; | |
820 | do { | |
821 | if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED)) | |
822 | break; | |
823 | udelay(1); | |
824 | } while (timeout-- > 0); | |
825 | ||
826 | atiixp_spdif_enable_transfer(chip, 0); | |
827 | } | |
828 | ||
829 | /* set up slots and formats for SPDIF OUT */ | |
830 | static int snd_atiixp_spdif_prepare(snd_pcm_substream_t *substream) | |
831 | { | |
832 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
833 | ||
834 | spin_lock_irq(&chip->reg_lock); | |
835 | if (chip->spdif_over_aclink) { | |
836 | unsigned int data; | |
837 | /* enable slots 10/11 */ | |
838 | atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, | |
839 | ATI_REG_CMD_SPDF_CONFIG_01); | |
840 | data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; | |
841 | data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | | |
842 | ATI_REG_OUT_DMA_SLOT_BIT(11); | |
843 | data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; | |
844 | atiixp_write(chip, OUT_DMA_SLOT, data); | |
845 | atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, | |
846 | substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? | |
847 | ATI_REG_CMD_INTERLEAVE_OUT : 0); | |
848 | } else { | |
849 | atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0); | |
850 | atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0); | |
851 | } | |
852 | spin_unlock_irq(&chip->reg_lock); | |
853 | return 0; | |
854 | } | |
855 | ||
856 | /* set up slots and formats for analog OUT */ | |
857 | static int snd_atiixp_playback_prepare(snd_pcm_substream_t *substream) | |
858 | { | |
859 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
860 | unsigned int data; | |
861 | ||
862 | spin_lock_irq(&chip->reg_lock); | |
863 | data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; | |
864 | switch (substream->runtime->channels) { | |
865 | case 8: | |
866 | data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | | |
867 | ATI_REG_OUT_DMA_SLOT_BIT(11); | |
868 | /* fallthru */ | |
869 | case 6: | |
870 | data |= ATI_REG_OUT_DMA_SLOT_BIT(7) | | |
871 | ATI_REG_OUT_DMA_SLOT_BIT(8); | |
872 | /* fallthru */ | |
873 | case 4: | |
874 | data |= ATI_REG_OUT_DMA_SLOT_BIT(6) | | |
875 | ATI_REG_OUT_DMA_SLOT_BIT(9); | |
876 | /* fallthru */ | |
877 | default: | |
878 | data |= ATI_REG_OUT_DMA_SLOT_BIT(3) | | |
879 | ATI_REG_OUT_DMA_SLOT_BIT(4); | |
880 | break; | |
881 | } | |
882 | ||
883 | /* set output threshold */ | |
884 | data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; | |
885 | atiixp_write(chip, OUT_DMA_SLOT, data); | |
886 | ||
887 | atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, | |
888 | substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? | |
889 | ATI_REG_CMD_INTERLEAVE_OUT : 0); | |
890 | ||
891 | /* | |
892 | * enable 6 channel re-ordering bit if needed | |
893 | */ | |
894 | atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN, | |
895 | substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0); | |
896 | ||
897 | spin_unlock_irq(&chip->reg_lock); | |
898 | return 0; | |
899 | } | |
900 | ||
901 | /* set up slots and formats for analog IN */ | |
902 | static int snd_atiixp_capture_prepare(snd_pcm_substream_t *substream) | |
903 | { | |
904 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
905 | ||
906 | spin_lock_irq(&chip->reg_lock); | |
907 | atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN, | |
908 | substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? | |
909 | ATI_REG_CMD_INTERLEAVE_IN : 0); | |
910 | spin_unlock_irq(&chip->reg_lock); | |
911 | return 0; | |
912 | } | |
913 | ||
914 | /* | |
915 | * hw_params - allocate the buffer and set up buffer descriptors | |
916 | */ | |
917 | static int snd_atiixp_pcm_hw_params(snd_pcm_substream_t *substream, | |
918 | snd_pcm_hw_params_t *hw_params) | |
919 | { | |
920 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
921 | atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data; | |
922 | int err; | |
923 | ||
924 | err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
925 | if (err < 0) | |
926 | return err; | |
927 | dma->buf_addr = substream->runtime->dma_addr; | |
928 | dma->buf_bytes = params_buffer_bytes(hw_params); | |
929 | ||
930 | err = atiixp_build_dma_packets(chip, dma, substream, | |
931 | params_periods(hw_params), | |
932 | params_period_bytes(hw_params)); | |
933 | if (err < 0) | |
934 | return err; | |
935 | ||
936 | if (dma->ac97_pcm_type >= 0) { | |
937 | struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; | |
938 | /* PCM is bound to AC97 codec(s) | |
939 | * set up the AC97 codecs | |
940 | */ | |
941 | if (dma->pcm_open_flag) { | |
942 | snd_ac97_pcm_close(pcm); | |
943 | dma->pcm_open_flag = 0; | |
944 | } | |
945 | err = snd_ac97_pcm_open(pcm, params_rate(hw_params), | |
946 | params_channels(hw_params), | |
947 | pcm->r[0].slots); | |
948 | if (err >= 0) | |
949 | dma->pcm_open_flag = 1; | |
950 | } | |
951 | ||
952 | return err; | |
953 | } | |
954 | ||
955 | static int snd_atiixp_pcm_hw_free(snd_pcm_substream_t * substream) | |
956 | { | |
957 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
958 | atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data; | |
959 | ||
960 | if (dma->pcm_open_flag) { | |
961 | struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; | |
962 | snd_ac97_pcm_close(pcm); | |
963 | dma->pcm_open_flag = 0; | |
964 | } | |
965 | atiixp_clear_dma_packets(chip, dma, substream); | |
966 | snd_pcm_lib_free_pages(substream); | |
967 | return 0; | |
968 | } | |
969 | ||
970 | ||
971 | /* | |
972 | * pcm hardware definition, identical for all DMA types | |
973 | */ | |
974 | static snd_pcm_hardware_t snd_atiixp_pcm_hw = | |
975 | { | |
976 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
977 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
978 | SNDRV_PCM_INFO_RESUME | | |
979 | SNDRV_PCM_INFO_MMAP_VALID), | |
980 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
981 | .rates = SNDRV_PCM_RATE_48000, | |
982 | .rate_min = 48000, | |
983 | .rate_max = 48000, | |
984 | .channels_min = 2, | |
985 | .channels_max = 2, | |
986 | .buffer_bytes_max = 256 * 1024, | |
987 | .period_bytes_min = 32, | |
988 | .period_bytes_max = 128 * 1024, | |
989 | .periods_min = 2, | |
990 | .periods_max = ATI_MAX_DESCRIPTORS, | |
991 | }; | |
992 | ||
993 | static int snd_atiixp_pcm_open(snd_pcm_substream_t *substream, atiixp_dma_t *dma, int pcm_type) | |
994 | { | |
995 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
996 | snd_pcm_runtime_t *runtime = substream->runtime; | |
997 | int err; | |
998 | ||
999 | snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL); | |
1000 | ||
1001 | if (dma->opened) | |
1002 | return -EBUSY; | |
1003 | dma->substream = substream; | |
1004 | runtime->hw = snd_atiixp_pcm_hw; | |
1005 | dma->ac97_pcm_type = pcm_type; | |
1006 | if (pcm_type >= 0) { | |
1007 | runtime->hw.rates = chip->pcms[pcm_type]->rates; | |
1008 | snd_pcm_limit_hw_rates(runtime); | |
1009 | } else { | |
1010 | /* direct SPDIF */ | |
1011 | runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; | |
1012 | } | |
1013 | if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) | |
1014 | return err; | |
1015 | runtime->private_data = dma; | |
1016 | ||
1017 | /* enable DMA bits */ | |
1018 | spin_lock_irq(&chip->reg_lock); | |
1019 | dma->ops->enable_dma(chip, 1); | |
1020 | spin_unlock_irq(&chip->reg_lock); | |
1021 | dma->opened = 1; | |
1022 | ||
1023 | return 0; | |
1024 | } | |
1025 | ||
1026 | static int snd_atiixp_pcm_close(snd_pcm_substream_t *substream, atiixp_dma_t *dma) | |
1027 | { | |
1028 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
1029 | /* disable DMA bits */ | |
1030 | snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL); | |
1031 | spin_lock_irq(&chip->reg_lock); | |
1032 | dma->ops->enable_dma(chip, 0); | |
1033 | spin_unlock_irq(&chip->reg_lock); | |
1034 | dma->substream = NULL; | |
1035 | dma->opened = 0; | |
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | /* | |
1040 | */ | |
1041 | static int snd_atiixp_playback_open(snd_pcm_substream_t *substream) | |
1042 | { | |
1043 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
1044 | int err; | |
1045 | ||
1046 | down(&chip->open_mutex); | |
1047 | err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0); | |
1048 | up(&chip->open_mutex); | |
1049 | if (err < 0) | |
1050 | return err; | |
1051 | substream->runtime->hw.channels_max = chip->max_channels; | |
1052 | if (chip->max_channels > 2) | |
1053 | /* channels must be even */ | |
1054 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1055 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | static int snd_atiixp_playback_close(snd_pcm_substream_t *substream) | |
1060 | { | |
1061 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
1062 | int err; | |
1063 | down(&chip->open_mutex); | |
1064 | err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); | |
1065 | up(&chip->open_mutex); | |
1066 | return err; | |
1067 | } | |
1068 | ||
1069 | static int snd_atiixp_capture_open(snd_pcm_substream_t *substream) | |
1070 | { | |
1071 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
1072 | return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1); | |
1073 | } | |
1074 | ||
1075 | static int snd_atiixp_capture_close(snd_pcm_substream_t *substream) | |
1076 | { | |
1077 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
1078 | return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]); | |
1079 | } | |
1080 | ||
1081 | static int snd_atiixp_spdif_open(snd_pcm_substream_t *substream) | |
1082 | { | |
1083 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
1084 | int err; | |
1085 | down(&chip->open_mutex); | |
1086 | if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */ | |
1087 | err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2); | |
1088 | else | |
1089 | err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1); | |
1090 | up(&chip->open_mutex); | |
1091 | return err; | |
1092 | } | |
1093 | ||
1094 | static int snd_atiixp_spdif_close(snd_pcm_substream_t *substream) | |
1095 | { | |
1096 | atiixp_t *chip = snd_pcm_substream_chip(substream); | |
1097 | int err; | |
1098 | down(&chip->open_mutex); | |
1099 | if (chip->spdif_over_aclink) | |
1100 | err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); | |
1101 | else | |
1102 | err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]); | |
1103 | up(&chip->open_mutex); | |
1104 | return err; | |
1105 | } | |
1106 | ||
1107 | /* AC97 playback */ | |
1108 | static snd_pcm_ops_t snd_atiixp_playback_ops = { | |
1109 | .open = snd_atiixp_playback_open, | |
1110 | .close = snd_atiixp_playback_close, | |
1111 | .ioctl = snd_pcm_lib_ioctl, | |
1112 | .hw_params = snd_atiixp_pcm_hw_params, | |
1113 | .hw_free = snd_atiixp_pcm_hw_free, | |
1114 | .prepare = snd_atiixp_playback_prepare, | |
1115 | .trigger = snd_atiixp_pcm_trigger, | |
1116 | .pointer = snd_atiixp_pcm_pointer, | |
1117 | }; | |
1118 | ||
1119 | /* AC97 capture */ | |
1120 | static snd_pcm_ops_t snd_atiixp_capture_ops = { | |
1121 | .open = snd_atiixp_capture_open, | |
1122 | .close = snd_atiixp_capture_close, | |
1123 | .ioctl = snd_pcm_lib_ioctl, | |
1124 | .hw_params = snd_atiixp_pcm_hw_params, | |
1125 | .hw_free = snd_atiixp_pcm_hw_free, | |
1126 | .prepare = snd_atiixp_capture_prepare, | |
1127 | .trigger = snd_atiixp_pcm_trigger, | |
1128 | .pointer = snd_atiixp_pcm_pointer, | |
1129 | }; | |
1130 | ||
1131 | /* SPDIF playback */ | |
1132 | static snd_pcm_ops_t snd_atiixp_spdif_ops = { | |
1133 | .open = snd_atiixp_spdif_open, | |
1134 | .close = snd_atiixp_spdif_close, | |
1135 | .ioctl = snd_pcm_lib_ioctl, | |
1136 | .hw_params = snd_atiixp_pcm_hw_params, | |
1137 | .hw_free = snd_atiixp_pcm_hw_free, | |
1138 | .prepare = snd_atiixp_spdif_prepare, | |
1139 | .trigger = snd_atiixp_pcm_trigger, | |
1140 | .pointer = snd_atiixp_pcm_pointer, | |
1141 | }; | |
1142 | ||
1143 | static struct ac97_pcm atiixp_pcm_defs[] __devinitdata = { | |
1144 | /* front PCM */ | |
1145 | { | |
1146 | .exclusive = 1, | |
1147 | .r = { { | |
1148 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
1149 | (1 << AC97_SLOT_PCM_RIGHT) | | |
1150 | (1 << AC97_SLOT_PCM_CENTER) | | |
1151 | (1 << AC97_SLOT_PCM_SLEFT) | | |
1152 | (1 << AC97_SLOT_PCM_SRIGHT) | | |
1153 | (1 << AC97_SLOT_LFE) | |
1154 | } | |
1155 | } | |
1156 | }, | |
1157 | /* PCM IN #1 */ | |
1158 | { | |
1159 | .stream = 1, | |
1160 | .exclusive = 1, | |
1161 | .r = { { | |
1162 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
1163 | (1 << AC97_SLOT_PCM_RIGHT) | |
1164 | } | |
1165 | } | |
1166 | }, | |
1167 | /* S/PDIF OUT (optional) */ | |
1168 | { | |
1169 | .exclusive = 1, | |
1170 | .spdif = 1, | |
1171 | .r = { { | |
1172 | .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | | |
1173 | (1 << AC97_SLOT_SPDIF_RIGHT2) | |
1174 | } | |
1175 | } | |
1176 | }, | |
1177 | }; | |
1178 | ||
1179 | static atiixp_dma_ops_t snd_atiixp_playback_dma_ops = { | |
1180 | .type = ATI_DMA_PLAYBACK, | |
1181 | .llp_offset = ATI_REG_OUT_DMA_LINKPTR, | |
1182 | .dt_cur = ATI_REG_OUT_DMA_DT_CUR, | |
1183 | .enable_dma = atiixp_out_enable_dma, | |
1184 | .enable_transfer = atiixp_out_enable_transfer, | |
1185 | .flush_dma = atiixp_out_flush_dma, | |
1186 | }; | |
1187 | ||
1188 | static atiixp_dma_ops_t snd_atiixp_capture_dma_ops = { | |
1189 | .type = ATI_DMA_CAPTURE, | |
1190 | .llp_offset = ATI_REG_IN_DMA_LINKPTR, | |
1191 | .dt_cur = ATI_REG_IN_DMA_DT_CUR, | |
1192 | .enable_dma = atiixp_in_enable_dma, | |
1193 | .enable_transfer = atiixp_in_enable_transfer, | |
1194 | .flush_dma = atiixp_in_flush_dma, | |
1195 | }; | |
1196 | ||
1197 | static atiixp_dma_ops_t snd_atiixp_spdif_dma_ops = { | |
1198 | .type = ATI_DMA_SPDIF, | |
1199 | .llp_offset = ATI_REG_SPDF_DMA_LINKPTR, | |
1200 | .dt_cur = ATI_REG_SPDF_DMA_DT_CUR, | |
1201 | .enable_dma = atiixp_spdif_enable_dma, | |
1202 | .enable_transfer = atiixp_spdif_enable_transfer, | |
1203 | .flush_dma = atiixp_spdif_flush_dma, | |
1204 | }; | |
1205 | ||
1206 | ||
1207 | static int __devinit snd_atiixp_pcm_new(atiixp_t *chip) | |
1208 | { | |
1209 | snd_pcm_t *pcm; | |
1210 | ac97_bus_t *pbus = chip->ac97_bus; | |
1211 | int err, i, num_pcms; | |
1212 | ||
1213 | /* initialize constants */ | |
1214 | chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops; | |
1215 | chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops; | |
1216 | if (! chip->spdif_over_aclink) | |
1217 | chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops; | |
1218 | ||
1219 | /* assign AC97 pcm */ | |
1220 | if (chip->spdif_over_aclink) | |
1221 | num_pcms = 3; | |
1222 | else | |
1223 | num_pcms = 2; | |
1224 | err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs); | |
1225 | if (err < 0) | |
1226 | return err; | |
1227 | for (i = 0; i < num_pcms; i++) | |
1228 | chip->pcms[i] = &pbus->pcms[i]; | |
1229 | ||
1230 | chip->max_channels = 2; | |
1231 | if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { | |
1232 | if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE)) | |
1233 | chip->max_channels = 6; | |
1234 | else | |
1235 | chip->max_channels = 4; | |
1236 | } | |
1237 | ||
1238 | /* PCM #0: analog I/O */ | |
1239 | err = snd_pcm_new(chip->card, "ATI IXP AC97", ATI_PCMDEV_ANALOG, 1, 1, &pcm); | |
1240 | if (err < 0) | |
1241 | return err; | |
1242 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops); | |
1243 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops); | |
1244 | pcm->private_data = chip; | |
1245 | strcpy(pcm->name, "ATI IXP AC97"); | |
1246 | chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm; | |
1247 | ||
1248 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1249 | snd_dma_pci_data(chip->pci), 64*1024, 128*1024); | |
1250 | ||
1251 | /* no SPDIF support on codec? */ | |
1252 | if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates) | |
1253 | return 0; | |
1254 | ||
1255 | /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */ | |
1256 | if (chip->pcms[ATI_PCM_SPDIF]) | |
1257 | chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000; | |
1258 | ||
1259 | /* PCM #1: spdif playback */ | |
1260 | err = snd_pcm_new(chip->card, "ATI IXP IEC958", ATI_PCMDEV_DIGITAL, 1, 0, &pcm); | |
1261 | if (err < 0) | |
1262 | return err; | |
1263 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops); | |
1264 | pcm->private_data = chip; | |
1265 | if (chip->spdif_over_aclink) | |
1266 | strcpy(pcm->name, "ATI IXP IEC958 (AC97)"); | |
1267 | else | |
1268 | strcpy(pcm->name, "ATI IXP IEC958 (Direct)"); | |
1269 | chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm; | |
1270 | ||
1271 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1272 | snd_dma_pci_data(chip->pci), 64*1024, 128*1024); | |
1273 | ||
1274 | /* pre-select AC97 SPDIF slots 10/11 */ | |
1275 | for (i = 0; i < NUM_ATI_CODECS; i++) { | |
1276 | if (chip->ac97[i]) | |
1277 | snd_ac97_update_bits(chip->ac97[i], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); | |
1278 | } | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | ||
1284 | ||
1285 | /* | |
1286 | * interrupt handler | |
1287 | */ | |
1288 | static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
1289 | { | |
1290 | atiixp_t *chip = dev_id; | |
1291 | unsigned int status; | |
1292 | ||
1293 | status = atiixp_read(chip, ISR); | |
1294 | ||
1295 | if (! status) | |
1296 | return IRQ_NONE; | |
1297 | ||
1298 | /* process audio DMA */ | |
1299 | if (status & ATI_REG_ISR_OUT_XRUN) | |
1300 | snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); | |
1301 | else if (status & ATI_REG_ISR_OUT_STATUS) | |
1302 | snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); | |
1303 | if (status & ATI_REG_ISR_IN_XRUN) | |
1304 | snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); | |
1305 | else if (status & ATI_REG_ISR_IN_STATUS) | |
1306 | snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); | |
1307 | if (! chip->spdif_over_aclink) { | |
1308 | if (status & ATI_REG_ISR_SPDF_XRUN) | |
1309 | snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); | |
1310 | else if (status & ATI_REG_ISR_SPDF_STATUS) | |
1311 | snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); | |
1312 | } | |
1313 | ||
1314 | /* for codec detection */ | |
1315 | if (status & CODEC_CHECK_BITS) { | |
1316 | unsigned int detected; | |
1317 | detected = status & CODEC_CHECK_BITS; | |
1318 | spin_lock(&chip->reg_lock); | |
1319 | chip->codec_not_ready_bits |= detected; | |
1320 | atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */ | |
1321 | spin_unlock(&chip->reg_lock); | |
1322 | } | |
1323 | ||
1324 | /* ack */ | |
1325 | atiixp_write(chip, ISR, status); | |
1326 | ||
1327 | return IRQ_HANDLED; | |
1328 | } | |
1329 | ||
1330 | ||
1331 | /* | |
1332 | * ac97 mixer section | |
1333 | */ | |
1334 | ||
1335 | static struct ac97_quirk ac97_quirks[] __devinitdata = { | |
1336 | { | |
1337 | .vendor = 0x103c, | |
1338 | .device = 0x006b, | |
1339 | .name = "HP Pavilion ZV5030US", | |
1340 | .type = AC97_TUNE_MUTE_LED | |
1341 | }, | |
1342 | { } /* terminator */ | |
1343 | }; | |
1344 | ||
1345 | static int __devinit snd_atiixp_mixer_new(atiixp_t *chip, int clock, const char *quirk_override) | |
1346 | { | |
1347 | ac97_bus_t *pbus; | |
1348 | ac97_template_t ac97; | |
1349 | int i, err; | |
1350 | int codec_count; | |
1351 | static ac97_bus_ops_t ops = { | |
1352 | .write = snd_atiixp_ac97_write, | |
1353 | .read = snd_atiixp_ac97_read, | |
1354 | }; | |
1355 | static unsigned int codec_skip[NUM_ATI_CODECS] = { | |
1356 | ATI_REG_ISR_CODEC0_NOT_READY, | |
1357 | ATI_REG_ISR_CODEC1_NOT_READY, | |
1358 | ATI_REG_ISR_CODEC2_NOT_READY, | |
1359 | }; | |
1360 | ||
1361 | if (snd_atiixp_codec_detect(chip) < 0) | |
1362 | return -ENXIO; | |
1363 | ||
1364 | if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) | |
1365 | return err; | |
1366 | pbus->clock = clock; | |
1367 | pbus->shared_type = AC97_SHARED_TYPE_ATIIXP; /* shared with modem driver */ | |
1368 | chip->ac97_bus = pbus; | |
1369 | ||
1370 | codec_count = 0; | |
1371 | for (i = 0; i < NUM_ATI_CODECS; i++) { | |
1372 | if (chip->codec_not_ready_bits & codec_skip[i]) | |
1373 | continue; | |
1374 | memset(&ac97, 0, sizeof(ac97)); | |
1375 | ac97.private_data = chip; | |
1376 | ac97.pci = chip->pci; | |
1377 | ac97.num = i; | |
1378 | ac97.scaps = AC97_SCAP_SKIP_MODEM; | |
1379 | if (! chip->spdif_over_aclink) | |
1380 | ac97.scaps |= AC97_SCAP_NO_SPDIF; | |
1381 | if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { | |
1382 | chip->ac97[i] = NULL; /* to be sure */ | |
1383 | snd_printdd("atiixp: codec %d not available for audio\n", i); | |
1384 | continue; | |
1385 | } | |
1386 | codec_count++; | |
1387 | } | |
1388 | ||
1389 | if (! codec_count) { | |
1390 | snd_printk(KERN_ERR "atiixp: no codec available\n"); | |
1391 | return -ENODEV; | |
1392 | } | |
1393 | ||
1394 | snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
1399 | ||
1400 | #ifdef CONFIG_PM | |
1401 | /* | |
1402 | * power management | |
1403 | */ | |
1404 | static int snd_atiixp_suspend(snd_card_t *card, pm_message_t state) | |
1405 | { | |
1406 | atiixp_t *chip = card->pm_private_data; | |
1407 | int i; | |
1408 | ||
1409 | for (i = 0; i < NUM_ATI_PCMDEVS; i++) | |
1410 | if (chip->pcmdevs[i]) { | |
1411 | atiixp_dma_t *dma = &chip->dmas[i]; | |
1412 | if (dma->substream && dma->running) | |
1413 | dma->saved_curptr = readl(chip->remap_addr + dma->ops->dt_cur); | |
1414 | snd_pcm_suspend_all(chip->pcmdevs[i]); | |
1415 | } | |
1416 | for (i = 0; i < NUM_ATI_CODECS; i++) | |
1417 | if (chip->ac97[i]) | |
1418 | snd_ac97_suspend(chip->ac97[i]); | |
1419 | snd_atiixp_aclink_down(chip); | |
1420 | snd_atiixp_chip_stop(chip); | |
1421 | ||
1422 | pci_set_power_state(chip->pci, 3); | |
1423 | pci_disable_device(chip->pci); | |
1424 | return 0; | |
1425 | } | |
1426 | ||
1427 | static int snd_atiixp_resume(snd_card_t *card) | |
1428 | { | |
1429 | atiixp_t *chip = card->pm_private_data; | |
1430 | int i; | |
1431 | ||
1432 | pci_enable_device(chip->pci); | |
1433 | pci_set_power_state(chip->pci, 0); | |
1434 | pci_set_master(chip->pci); | |
1435 | ||
1436 | snd_atiixp_aclink_reset(chip); | |
1437 | snd_atiixp_chip_start(chip); | |
1438 | ||
1439 | for (i = 0; i < NUM_ATI_CODECS; i++) | |
1440 | if (chip->ac97[i]) | |
1441 | snd_ac97_resume(chip->ac97[i]); | |
1442 | ||
1443 | for (i = 0; i < NUM_ATI_PCMDEVS; i++) | |
1444 | if (chip->pcmdevs[i]) { | |
1445 | atiixp_dma_t *dma = &chip->dmas[i]; | |
1446 | if (dma->substream && dma->running) { | |
1447 | dma->ops->enable_dma(chip, 1); | |
1448 | writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, | |
1449 | chip->remap_addr + dma->ops->llp_offset); | |
1450 | writel(dma->saved_curptr, chip->remap_addr + dma->ops->dt_cur); | |
1451 | } | |
1452 | } | |
1453 | ||
1454 | return 0; | |
1455 | } | |
1456 | #endif /* CONFIG_PM */ | |
1457 | ||
1458 | ||
1459 | /* | |
1460 | * proc interface for register dump | |
1461 | */ | |
1462 | ||
1463 | static void snd_atiixp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer) | |
1464 | { | |
1465 | atiixp_t *chip = entry->private_data; | |
1466 | int i; | |
1467 | ||
1468 | for (i = 0; i < 256; i += 4) | |
1469 | snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i)); | |
1470 | } | |
1471 | ||
1472 | static void __devinit snd_atiixp_proc_init(atiixp_t *chip) | |
1473 | { | |
1474 | snd_info_entry_t *entry; | |
1475 | ||
1476 | if (! snd_card_proc_new(chip->card, "atiixp", &entry)) | |
1477 | snd_info_set_text_ops(entry, chip, 1024, snd_atiixp_proc_read); | |
1478 | } | |
1479 | ||
1480 | ||
1481 | ||
1482 | /* | |
1483 | * destructor | |
1484 | */ | |
1485 | ||
1486 | static int snd_atiixp_free(atiixp_t *chip) | |
1487 | { | |
1488 | if (chip->irq < 0) | |
1489 | goto __hw_end; | |
1490 | snd_atiixp_chip_stop(chip); | |
1491 | synchronize_irq(chip->irq); | |
1492 | __hw_end: | |
1493 | if (chip->irq >= 0) | |
1494 | free_irq(chip->irq, (void *)chip); | |
1495 | if (chip->remap_addr) | |
1496 | iounmap(chip->remap_addr); | |
1497 | pci_release_regions(chip->pci); | |
1498 | pci_disable_device(chip->pci); | |
1499 | kfree(chip); | |
1500 | return 0; | |
1501 | } | |
1502 | ||
1503 | static int snd_atiixp_dev_free(snd_device_t *device) | |
1504 | { | |
1505 | atiixp_t *chip = device->device_data; | |
1506 | return snd_atiixp_free(chip); | |
1507 | } | |
1508 | ||
1509 | /* | |
1510 | * constructor for chip instance | |
1511 | */ | |
1512 | static int __devinit snd_atiixp_create(snd_card_t *card, | |
1513 | struct pci_dev *pci, | |
1514 | atiixp_t **r_chip) | |
1515 | { | |
1516 | static snd_device_ops_t ops = { | |
1517 | .dev_free = snd_atiixp_dev_free, | |
1518 | }; | |
1519 | atiixp_t *chip; | |
1520 | int err; | |
1521 | ||
1522 | if ((err = pci_enable_device(pci)) < 0) | |
1523 | return err; | |
1524 | ||
1525 | chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); | |
1526 | if (chip == NULL) { | |
1527 | pci_disable_device(pci); | |
1528 | return -ENOMEM; | |
1529 | } | |
1530 | ||
1531 | spin_lock_init(&chip->reg_lock); | |
1532 | init_MUTEX(&chip->open_mutex); | |
1533 | chip->card = card; | |
1534 | chip->pci = pci; | |
1535 | chip->irq = -1; | |
1536 | if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) { | |
1537 | pci_disable_device(pci); | |
1538 | kfree(chip); | |
1539 | return err; | |
1540 | } | |
1541 | chip->addr = pci_resource_start(pci, 0); | |
1542 | chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 0)); | |
1543 | if (chip->remap_addr == NULL) { | |
1544 | snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); | |
1545 | snd_atiixp_free(chip); | |
1546 | return -EIO; | |
1547 | } | |
1548 | ||
1549 | if (request_irq(pci->irq, snd_atiixp_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) { | |
1550 | snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); | |
1551 | snd_atiixp_free(chip); | |
1552 | return -EBUSY; | |
1553 | } | |
1554 | chip->irq = pci->irq; | |
1555 | pci_set_master(pci); | |
1556 | synchronize_irq(chip->irq); | |
1557 | ||
1558 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { | |
1559 | snd_atiixp_free(chip); | |
1560 | return err; | |
1561 | } | |
1562 | ||
1563 | snd_card_set_dev(card, &pci->dev); | |
1564 | ||
1565 | *r_chip = chip; | |
1566 | return 0; | |
1567 | } | |
1568 | ||
1569 | ||
1570 | static int __devinit snd_atiixp_probe(struct pci_dev *pci, | |
1571 | const struct pci_device_id *pci_id) | |
1572 | { | |
1573 | static int dev; | |
1574 | snd_card_t *card; | |
1575 | atiixp_t *chip; | |
1576 | unsigned char revision; | |
1577 | int err; | |
1578 | ||
1579 | if (dev >= SNDRV_CARDS) | |
1580 | return -ENODEV; | |
1581 | if (!enable[dev]) { | |
1582 | dev++; | |
1583 | return -ENOENT; | |
1584 | } | |
1585 | ||
1586 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); | |
1587 | if (card == NULL) | |
1588 | return -ENOMEM; | |
1589 | ||
1590 | pci_read_config_byte(pci, PCI_REVISION_ID, &revision); | |
1591 | ||
1592 | strcpy(card->driver, spdif_aclink[dev] ? "ATIIXP" : "ATIIXP-SPDMA"); | |
1593 | strcpy(card->shortname, "ATI IXP"); | |
1594 | if ((err = snd_atiixp_create(card, pci, &chip)) < 0) | |
1595 | goto __error; | |
1596 | ||
1597 | if ((err = snd_atiixp_aclink_reset(chip)) < 0) | |
1598 | goto __error; | |
1599 | ||
1600 | chip->spdif_over_aclink = spdif_aclink[dev]; | |
1601 | ||
1602 | if ((err = snd_atiixp_mixer_new(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) | |
1603 | goto __error; | |
1604 | ||
1605 | if ((err = snd_atiixp_pcm_new(chip)) < 0) | |
1606 | goto __error; | |
1607 | ||
1608 | snd_atiixp_proc_init(chip); | |
1609 | ||
1610 | snd_atiixp_chip_start(chip); | |
1611 | ||
1612 | snprintf(card->longname, sizeof(card->longname), | |
1613 | "%s rev %x with %s at %#lx, irq %i", card->shortname, revision, | |
1614 | chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?", | |
1615 | chip->addr, chip->irq); | |
1616 | ||
1617 | snd_card_set_pm_callback(card, snd_atiixp_suspend, snd_atiixp_resume, chip); | |
1618 | ||
1619 | if ((err = snd_card_register(card)) < 0) | |
1620 | goto __error; | |
1621 | ||
1622 | pci_set_drvdata(pci, card); | |
1623 | dev++; | |
1624 | return 0; | |
1625 | ||
1626 | __error: | |
1627 | snd_card_free(card); | |
1628 | return err; | |
1629 | } | |
1630 | ||
1631 | static void __devexit snd_atiixp_remove(struct pci_dev *pci) | |
1632 | { | |
1633 | snd_card_free(pci_get_drvdata(pci)); | |
1634 | pci_set_drvdata(pci, NULL); | |
1635 | } | |
1636 | ||
1637 | static struct pci_driver driver = { | |
1638 | .name = "ATI IXP AC97 controller", | |
1639 | .id_table = snd_atiixp_ids, | |
1640 | .probe = snd_atiixp_probe, | |
1641 | .remove = __devexit_p(snd_atiixp_remove), | |
1642 | SND_PCI_PM_CALLBACKS | |
1643 | }; | |
1644 | ||
1645 | ||
1646 | static int __init alsa_card_atiixp_init(void) | |
1647 | { | |
01d25d46 | 1648 | return pci_register_driver(&driver); |
1da177e4 LT |
1649 | } |
1650 | ||
1651 | static void __exit alsa_card_atiixp_exit(void) | |
1652 | { | |
1653 | pci_unregister_driver(&driver); | |
1654 | } | |
1655 | ||
1656 | module_init(alsa_card_atiixp_init) | |
1657 | module_exit(alsa_card_atiixp_exit) |